1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : POWMAN 10 // Version : 1 11 // Bus type : apb 12 // Description : Controls vreg, bor, lposc, chip resets & xosc startup, 13 // powman and provides scratch register for general use and for 14 // bootcode use 15 // ============================================================================= 16 #ifndef _HARDWARE_REGS_POWMAN_H 17 #define _HARDWARE_REGS_POWMAN_H 18 // ============================================================================= 19 // Register : POWMAN_BADPASSWD 20 // Description : Indicates a bad password has been used 21 #define POWMAN_BADPASSWD_OFFSET _u(0x00000000) 22 #define POWMAN_BADPASSWD_BITS _u(0x00000001) 23 #define POWMAN_BADPASSWD_RESET _u(0x00000000) 24 #define POWMAN_BADPASSWD_MSB _u(0) 25 #define POWMAN_BADPASSWD_LSB _u(0) 26 #define POWMAN_BADPASSWD_ACCESS "WC" 27 // ============================================================================= 28 // Register : POWMAN_VREG_CTRL 29 // Description : Voltage Regulator Control 30 #define POWMAN_VREG_CTRL_OFFSET _u(0x00000004) 31 #define POWMAN_VREG_CTRL_BITS _u(0x0000b170) 32 #define POWMAN_VREG_CTRL_RESET _u(0x00008050) 33 // ----------------------------------------------------------------------------- 34 // Field : POWMAN_VREG_CTRL_RST_N 35 // Description : returns the regulator to its startup settings 36 // 0 - reset 37 // 1 - not reset (default) 38 #define POWMAN_VREG_CTRL_RST_N_RESET _u(0x1) 39 #define POWMAN_VREG_CTRL_RST_N_BITS _u(0x00008000) 40 #define POWMAN_VREG_CTRL_RST_N_MSB _u(15) 41 #define POWMAN_VREG_CTRL_RST_N_LSB _u(15) 42 #define POWMAN_VREG_CTRL_RST_N_ACCESS "RW" 43 // ----------------------------------------------------------------------------- 44 // Field : POWMAN_VREG_CTRL_UNLOCK 45 // Description : unlocks the VREG control interface after power up 46 // 0 - Locked (default) 47 // 1 - Unlocked 48 // It cannot be relocked when it is unlocked. 49 #define POWMAN_VREG_CTRL_UNLOCK_RESET _u(0x0) 50 #define POWMAN_VREG_CTRL_UNLOCK_BITS _u(0x00002000) 51 #define POWMAN_VREG_CTRL_UNLOCK_MSB _u(13) 52 #define POWMAN_VREG_CTRL_UNLOCK_LSB _u(13) 53 #define POWMAN_VREG_CTRL_UNLOCK_ACCESS "RW" 54 // ----------------------------------------------------------------------------- 55 // Field : POWMAN_VREG_CTRL_ISOLATE 56 // Description : isolates the VREG control interface 57 // 0 - not isolated (default) 58 // 1 - isolated 59 #define POWMAN_VREG_CTRL_ISOLATE_RESET _u(0x0) 60 #define POWMAN_VREG_CTRL_ISOLATE_BITS _u(0x00001000) 61 #define POWMAN_VREG_CTRL_ISOLATE_MSB _u(12) 62 #define POWMAN_VREG_CTRL_ISOLATE_LSB _u(12) 63 #define POWMAN_VREG_CTRL_ISOLATE_ACCESS "RW" 64 // ----------------------------------------------------------------------------- 65 // Field : POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT 66 // Description : 0=not disabled, 1=enabled 67 #define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_RESET _u(0x0) 68 #define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_BITS _u(0x00000100) 69 #define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_MSB _u(8) 70 #define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_LSB _u(8) 71 #define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_ACCESS "RW" 72 // ----------------------------------------------------------------------------- 73 // Field : POWMAN_VREG_CTRL_HT_TH 74 // Description : high temperature protection threshold 75 // regulator power transistors are disabled when junction 76 // temperature exceeds threshold 77 // 000 - 100C 78 // 001 - 105C 79 // 010 - 110C 80 // 011 - 115C 81 // 100 - 120C 82 // 101 - 125C 83 // 110 - 135C 84 // 111 - 150C 85 #define POWMAN_VREG_CTRL_HT_TH_RESET _u(0x5) 86 #define POWMAN_VREG_CTRL_HT_TH_BITS _u(0x00000070) 87 #define POWMAN_VREG_CTRL_HT_TH_MSB _u(6) 88 #define POWMAN_VREG_CTRL_HT_TH_LSB _u(4) 89 #define POWMAN_VREG_CTRL_HT_TH_ACCESS "RW" 90 // ============================================================================= 91 // Register : POWMAN_VREG_STS 92 // Description : Voltage Regulator Status 93 #define POWMAN_VREG_STS_OFFSET _u(0x00000008) 94 #define POWMAN_VREG_STS_BITS _u(0x00000011) 95 #define POWMAN_VREG_STS_RESET _u(0x00000000) 96 // ----------------------------------------------------------------------------- 97 // Field : POWMAN_VREG_STS_VOUT_OK 98 // Description : output regulation status 99 // 0=not in regulation, 1=in regulation 100 #define POWMAN_VREG_STS_VOUT_OK_RESET _u(0x0) 101 #define POWMAN_VREG_STS_VOUT_OK_BITS _u(0x00000010) 102 #define POWMAN_VREG_STS_VOUT_OK_MSB _u(4) 103 #define POWMAN_VREG_STS_VOUT_OK_LSB _u(4) 104 #define POWMAN_VREG_STS_VOUT_OK_ACCESS "RO" 105 // ----------------------------------------------------------------------------- 106 // Field : POWMAN_VREG_STS_STARTUP 107 // Description : startup status 108 // 0=startup complete, 1=starting up 109 #define POWMAN_VREG_STS_STARTUP_RESET _u(0x0) 110 #define POWMAN_VREG_STS_STARTUP_BITS _u(0x00000001) 111 #define POWMAN_VREG_STS_STARTUP_MSB _u(0) 112 #define POWMAN_VREG_STS_STARTUP_LSB _u(0) 113 #define POWMAN_VREG_STS_STARTUP_ACCESS "RO" 114 // ============================================================================= 115 // Register : POWMAN_VREG 116 // Description : Voltage Regulator Settings 117 #define POWMAN_VREG_OFFSET _u(0x0000000c) 118 #define POWMAN_VREG_BITS _u(0x000081f2) 119 #define POWMAN_VREG_RESET _u(0x000000b0) 120 // ----------------------------------------------------------------------------- 121 // Field : POWMAN_VREG_UPDATE_IN_PROGRESS 122 // Description : regulator state is being updated 123 // writes to the vreg register will be ignored when this field is 124 // set 125 #define POWMAN_VREG_UPDATE_IN_PROGRESS_RESET _u(0x0) 126 #define POWMAN_VREG_UPDATE_IN_PROGRESS_BITS _u(0x00008000) 127 #define POWMAN_VREG_UPDATE_IN_PROGRESS_MSB _u(15) 128 #define POWMAN_VREG_UPDATE_IN_PROGRESS_LSB _u(15) 129 #define POWMAN_VREG_UPDATE_IN_PROGRESS_ACCESS "RO" 130 // ----------------------------------------------------------------------------- 131 // Field : POWMAN_VREG_VSEL 132 // Description : output voltage select 133 // the regulator output voltage is limited to 1.3V unless the 134 // voltage limit 135 // is disabled using the disable_voltage_limit field in the 136 // vreg_ctrl register 137 // 00000 - 0.55V 138 // 00001 - 0.60V 139 // 00010 - 0.65V 140 // 00011 - 0.70V 141 // 00100 - 0.75V 142 // 00101 - 0.80V 143 // 00110 - 0.85V 144 // 00111 - 0.90V 145 // 01000 - 0.95V 146 // 01001 - 1.00V 147 // 01010 - 1.05V 148 // 01011 - 1.10V (default) 149 // 01100 - 1.15V 150 // 01101 - 1.20V 151 // 01110 - 1.25V 152 // 01111 - 1.30V 153 // 10000 - 1.35V 154 // 10001 - 1.40V 155 // 10010 - 1.50V 156 // 10011 - 1.60V 157 // 10100 - 1.65V 158 // 10101 - 1.70V 159 // 10110 - 1.80V 160 // 10111 - 1.90V 161 // 11000 - 2.00V 162 // 11001 - 2.35V 163 // 11010 - 2.50V 164 // 11011 - 2.65V 165 // 11100 - 2.80V 166 // 11101 - 3.00V 167 // 11110 - 3.15V 168 // 11111 - 3.30V 169 #define POWMAN_VREG_VSEL_RESET _u(0x0b) 170 #define POWMAN_VREG_VSEL_BITS _u(0x000001f0) 171 #define POWMAN_VREG_VSEL_MSB _u(8) 172 #define POWMAN_VREG_VSEL_LSB _u(4) 173 #define POWMAN_VREG_VSEL_ACCESS "RW" 174 // ----------------------------------------------------------------------------- 175 // Field : POWMAN_VREG_HIZ 176 // Description : high impedance mode select 177 // 0=not in high impedance mode, 1=in high impedance mode 178 #define POWMAN_VREG_HIZ_RESET _u(0x0) 179 #define POWMAN_VREG_HIZ_BITS _u(0x00000002) 180 #define POWMAN_VREG_HIZ_MSB _u(1) 181 #define POWMAN_VREG_HIZ_LSB _u(1) 182 #define POWMAN_VREG_HIZ_ACCESS "RW" 183 // ============================================================================= 184 // Register : POWMAN_VREG_LP_ENTRY 185 // Description : Voltage Regulator Low Power Entry Settings 186 #define POWMAN_VREG_LP_ENTRY_OFFSET _u(0x00000010) 187 #define POWMAN_VREG_LP_ENTRY_BITS _u(0x000001f6) 188 #define POWMAN_VREG_LP_ENTRY_RESET _u(0x000000b4) 189 // ----------------------------------------------------------------------------- 190 // Field : POWMAN_VREG_LP_ENTRY_VSEL 191 // Description : output voltage select 192 // the regulator output voltage is limited to 1.3V unless the 193 // voltage limit 194 // is disabled using the disable_voltage_limit field in the 195 // vreg_ctrl register 196 // 00000 - 0.55V 197 // 00001 - 0.60V 198 // 00010 - 0.65V 199 // 00011 - 0.70V 200 // 00100 - 0.75V 201 // 00101 - 0.80V 202 // 00110 - 0.85V 203 // 00111 - 0.90V 204 // 01000 - 0.95V 205 // 01001 - 1.00V 206 // 01010 - 1.05V 207 // 01011 - 1.10V (default) 208 // 01100 - 1.15V 209 // 01101 - 1.20V 210 // 01110 - 1.25V 211 // 01111 - 1.30V 212 // 10000 - 1.35V 213 // 10001 - 1.40V 214 // 10010 - 1.50V 215 // 10011 - 1.60V 216 // 10100 - 1.65V 217 // 10101 - 1.70V 218 // 10110 - 1.80V 219 // 10111 - 1.90V 220 // 11000 - 2.00V 221 // 11001 - 2.35V 222 // 11010 - 2.50V 223 // 11011 - 2.65V 224 // 11100 - 2.80V 225 // 11101 - 3.00V 226 // 11110 - 3.15V 227 // 11111 - 3.30V 228 #define POWMAN_VREG_LP_ENTRY_VSEL_RESET _u(0x0b) 229 #define POWMAN_VREG_LP_ENTRY_VSEL_BITS _u(0x000001f0) 230 #define POWMAN_VREG_LP_ENTRY_VSEL_MSB _u(8) 231 #define POWMAN_VREG_LP_ENTRY_VSEL_LSB _u(4) 232 #define POWMAN_VREG_LP_ENTRY_VSEL_ACCESS "RW" 233 // ----------------------------------------------------------------------------- 234 // Field : POWMAN_VREG_LP_ENTRY_MODE 235 // Description : selects either normal (switching) mode or low power (linear) 236 // mode 237 // low power mode can only be selected for output voltages up to 238 // 1.3V 239 // 0 = normal mode (switching) 240 // 1 = low power mode (linear) 241 #define POWMAN_VREG_LP_ENTRY_MODE_RESET _u(0x1) 242 #define POWMAN_VREG_LP_ENTRY_MODE_BITS _u(0x00000004) 243 #define POWMAN_VREG_LP_ENTRY_MODE_MSB _u(2) 244 #define POWMAN_VREG_LP_ENTRY_MODE_LSB _u(2) 245 #define POWMAN_VREG_LP_ENTRY_MODE_ACCESS "RW" 246 // ----------------------------------------------------------------------------- 247 // Field : POWMAN_VREG_LP_ENTRY_HIZ 248 // Description : high impedance mode select 249 // 0=not in high impedance mode, 1=in high impedance mode 250 #define POWMAN_VREG_LP_ENTRY_HIZ_RESET _u(0x0) 251 #define POWMAN_VREG_LP_ENTRY_HIZ_BITS _u(0x00000002) 252 #define POWMAN_VREG_LP_ENTRY_HIZ_MSB _u(1) 253 #define POWMAN_VREG_LP_ENTRY_HIZ_LSB _u(1) 254 #define POWMAN_VREG_LP_ENTRY_HIZ_ACCESS "RW" 255 // ============================================================================= 256 // Register : POWMAN_VREG_LP_EXIT 257 // Description : Voltage Regulator Low Power Exit Settings 258 #define POWMAN_VREG_LP_EXIT_OFFSET _u(0x00000014) 259 #define POWMAN_VREG_LP_EXIT_BITS _u(0x000001f6) 260 #define POWMAN_VREG_LP_EXIT_RESET _u(0x000000b0) 261 // ----------------------------------------------------------------------------- 262 // Field : POWMAN_VREG_LP_EXIT_VSEL 263 // Description : output voltage select 264 // the regulator output voltage is limited to 1.3V unless the 265 // voltage limit 266 // is disabled using the disable_voltage_limit field in the 267 // vreg_ctrl register 268 // 00000 - 0.55V 269 // 00001 - 0.60V 270 // 00010 - 0.65V 271 // 00011 - 0.70V 272 // 00100 - 0.75V 273 // 00101 - 0.80V 274 // 00110 - 0.85V 275 // 00111 - 0.90V 276 // 01000 - 0.95V 277 // 01001 - 1.00V 278 // 01010 - 1.05V 279 // 01011 - 1.10V (default) 280 // 01100 - 1.15V 281 // 01101 - 1.20V 282 // 01110 - 1.25V 283 // 01111 - 1.30V 284 // 10000 - 1.35V 285 // 10001 - 1.40V 286 // 10010 - 1.50V 287 // 10011 - 1.60V 288 // 10100 - 1.65V 289 // 10101 - 1.70V 290 // 10110 - 1.80V 291 // 10111 - 1.90V 292 // 11000 - 2.00V 293 // 11001 - 2.35V 294 // 11010 - 2.50V 295 // 11011 - 2.65V 296 // 11100 - 2.80V 297 // 11101 - 3.00V 298 // 11110 - 3.15V 299 // 11111 - 3.30V 300 #define POWMAN_VREG_LP_EXIT_VSEL_RESET _u(0x0b) 301 #define POWMAN_VREG_LP_EXIT_VSEL_BITS _u(0x000001f0) 302 #define POWMAN_VREG_LP_EXIT_VSEL_MSB _u(8) 303 #define POWMAN_VREG_LP_EXIT_VSEL_LSB _u(4) 304 #define POWMAN_VREG_LP_EXIT_VSEL_ACCESS "RW" 305 // ----------------------------------------------------------------------------- 306 // Field : POWMAN_VREG_LP_EXIT_MODE 307 // Description : selects either normal (switching) mode or low power (linear) 308 // mode 309 // low power mode can only be selected for output voltages up to 310 // 1.3V 311 // 0 = normal mode (switching) 312 // 1 = low power mode (linear) 313 #define POWMAN_VREG_LP_EXIT_MODE_RESET _u(0x0) 314 #define POWMAN_VREG_LP_EXIT_MODE_BITS _u(0x00000004) 315 #define POWMAN_VREG_LP_EXIT_MODE_MSB _u(2) 316 #define POWMAN_VREG_LP_EXIT_MODE_LSB _u(2) 317 #define POWMAN_VREG_LP_EXIT_MODE_ACCESS "RW" 318 // ----------------------------------------------------------------------------- 319 // Field : POWMAN_VREG_LP_EXIT_HIZ 320 // Description : high impedance mode select 321 // 0=not in high impedance mode, 1=in high impedance mode 322 #define POWMAN_VREG_LP_EXIT_HIZ_RESET _u(0x0) 323 #define POWMAN_VREG_LP_EXIT_HIZ_BITS _u(0x00000002) 324 #define POWMAN_VREG_LP_EXIT_HIZ_MSB _u(1) 325 #define POWMAN_VREG_LP_EXIT_HIZ_LSB _u(1) 326 #define POWMAN_VREG_LP_EXIT_HIZ_ACCESS "RW" 327 // ============================================================================= 328 // Register : POWMAN_BOD_CTRL 329 // Description : Brown-out Detection Control 330 #define POWMAN_BOD_CTRL_OFFSET _u(0x00000018) 331 #define POWMAN_BOD_CTRL_BITS _u(0x00001000) 332 #define POWMAN_BOD_CTRL_RESET _u(0x00000000) 333 // ----------------------------------------------------------------------------- 334 // Field : POWMAN_BOD_CTRL_ISOLATE 335 // Description : isolates the brown-out detection control interface 336 // 0 - not isolated (default) 337 // 1 - isolated 338 #define POWMAN_BOD_CTRL_ISOLATE_RESET _u(0x0) 339 #define POWMAN_BOD_CTRL_ISOLATE_BITS _u(0x00001000) 340 #define POWMAN_BOD_CTRL_ISOLATE_MSB _u(12) 341 #define POWMAN_BOD_CTRL_ISOLATE_LSB _u(12) 342 #define POWMAN_BOD_CTRL_ISOLATE_ACCESS "RW" 343 // ============================================================================= 344 // Register : POWMAN_BOD 345 // Description : Brown-out Detection Settings 346 #define POWMAN_BOD_OFFSET _u(0x0000001c) 347 #define POWMAN_BOD_BITS _u(0x000001f1) 348 #define POWMAN_BOD_RESET _u(0x000000b1) 349 // ----------------------------------------------------------------------------- 350 // Field : POWMAN_BOD_VSEL 351 // Description : threshold select 352 // 00000 - 0.473V 353 // 00001 - 0.516V 354 // 00010 - 0.559V 355 // 00011 - 0.602V 356 // 00100 - 0.645VS 357 // 00101 - 0.688V 358 // 00110 - 0.731V 359 // 00111 - 0.774V 360 // 01000 - 0.817V 361 // 01001 - 0.860V (default) 362 // 01010 - 0.903V 363 // 01011 - 0.946V 364 // 01100 - 0.989V 365 // 01101 - 1.032V 366 // 01110 - 1.075V 367 // 01111 - 1.118V 368 // 10000 - 1.161 369 // 10001 - 1.204V 370 #define POWMAN_BOD_VSEL_RESET _u(0x0b) 371 #define POWMAN_BOD_VSEL_BITS _u(0x000001f0) 372 #define POWMAN_BOD_VSEL_MSB _u(8) 373 #define POWMAN_BOD_VSEL_LSB _u(4) 374 #define POWMAN_BOD_VSEL_ACCESS "RW" 375 // ----------------------------------------------------------------------------- 376 // Field : POWMAN_BOD_EN 377 // Description : enable brown-out detection 378 // 0=not enabled, 1=enabled 379 #define POWMAN_BOD_EN_RESET _u(0x1) 380 #define POWMAN_BOD_EN_BITS _u(0x00000001) 381 #define POWMAN_BOD_EN_MSB _u(0) 382 #define POWMAN_BOD_EN_LSB _u(0) 383 #define POWMAN_BOD_EN_ACCESS "RW" 384 // ============================================================================= 385 // Register : POWMAN_BOD_LP_ENTRY 386 // Description : Brown-out Detection Low Power Entry Settings 387 #define POWMAN_BOD_LP_ENTRY_OFFSET _u(0x00000020) 388 #define POWMAN_BOD_LP_ENTRY_BITS _u(0x000001f1) 389 #define POWMAN_BOD_LP_ENTRY_RESET _u(0x000000b0) 390 // ----------------------------------------------------------------------------- 391 // Field : POWMAN_BOD_LP_ENTRY_VSEL 392 // Description : threshold select 393 // 00000 - 0.473V 394 // 00001 - 0.516V 395 // 00010 - 0.559V 396 // 00011 - 0.602V 397 // 00100 - 0.645VS 398 // 00101 - 0.688V 399 // 00110 - 0.731V 400 // 00111 - 0.774V 401 // 01000 - 0.817V 402 // 01001 - 0.860V (default) 403 // 01010 - 0.903V 404 // 01011 - 0.946V 405 // 01100 - 0.989V 406 // 01101 - 1.032V 407 // 01110 - 1.075V 408 // 01111 - 1.118V 409 // 10000 - 1.161 410 // 10001 - 1.204V 411 #define POWMAN_BOD_LP_ENTRY_VSEL_RESET _u(0x0b) 412 #define POWMAN_BOD_LP_ENTRY_VSEL_BITS _u(0x000001f0) 413 #define POWMAN_BOD_LP_ENTRY_VSEL_MSB _u(8) 414 #define POWMAN_BOD_LP_ENTRY_VSEL_LSB _u(4) 415 #define POWMAN_BOD_LP_ENTRY_VSEL_ACCESS "RW" 416 // ----------------------------------------------------------------------------- 417 // Field : POWMAN_BOD_LP_ENTRY_EN 418 // Description : enable brown-out detection 419 // 0=not enabled, 1=enabled 420 #define POWMAN_BOD_LP_ENTRY_EN_RESET _u(0x0) 421 #define POWMAN_BOD_LP_ENTRY_EN_BITS _u(0x00000001) 422 #define POWMAN_BOD_LP_ENTRY_EN_MSB _u(0) 423 #define POWMAN_BOD_LP_ENTRY_EN_LSB _u(0) 424 #define POWMAN_BOD_LP_ENTRY_EN_ACCESS "RW" 425 // ============================================================================= 426 // Register : POWMAN_BOD_LP_EXIT 427 // Description : Brown-out Detection Low Power Exit Settings 428 #define POWMAN_BOD_LP_EXIT_OFFSET _u(0x00000024) 429 #define POWMAN_BOD_LP_EXIT_BITS _u(0x000001f1) 430 #define POWMAN_BOD_LP_EXIT_RESET _u(0x000000b1) 431 // ----------------------------------------------------------------------------- 432 // Field : POWMAN_BOD_LP_EXIT_VSEL 433 // Description : threshold select 434 // 00000 - 0.473V 435 // 00001 - 0.516V 436 // 00010 - 0.559V 437 // 00011 - 0.602V 438 // 00100 - 0.645VS 439 // 00101 - 0.688V 440 // 00110 - 0.731V 441 // 00111 - 0.774V 442 // 01000 - 0.817V 443 // 01001 - 0.860V (default) 444 // 01010 - 0.903V 445 // 01011 - 0.946V 446 // 01100 - 0.989V 447 // 01101 - 1.032V 448 // 01110 - 1.075V 449 // 01111 - 1.118V 450 // 10000 - 1.161 451 // 10001 - 1.204V 452 #define POWMAN_BOD_LP_EXIT_VSEL_RESET _u(0x0b) 453 #define POWMAN_BOD_LP_EXIT_VSEL_BITS _u(0x000001f0) 454 #define POWMAN_BOD_LP_EXIT_VSEL_MSB _u(8) 455 #define POWMAN_BOD_LP_EXIT_VSEL_LSB _u(4) 456 #define POWMAN_BOD_LP_EXIT_VSEL_ACCESS "RW" 457 // ----------------------------------------------------------------------------- 458 // Field : POWMAN_BOD_LP_EXIT_EN 459 // Description : enable brown-out detection 460 // 0=not enabled, 1=enabled 461 #define POWMAN_BOD_LP_EXIT_EN_RESET _u(0x1) 462 #define POWMAN_BOD_LP_EXIT_EN_BITS _u(0x00000001) 463 #define POWMAN_BOD_LP_EXIT_EN_MSB _u(0) 464 #define POWMAN_BOD_LP_EXIT_EN_LSB _u(0) 465 #define POWMAN_BOD_LP_EXIT_EN_ACCESS "RW" 466 // ============================================================================= 467 // Register : POWMAN_LPOSC 468 // Description : Low power oscillator control register. 469 #define POWMAN_LPOSC_OFFSET _u(0x00000028) 470 #define POWMAN_LPOSC_BITS _u(0x000003f3) 471 #define POWMAN_LPOSC_RESET _u(0x00000203) 472 // ----------------------------------------------------------------------------- 473 // Field : POWMAN_LPOSC_TRIM 474 // Description : Frequency trim - the trim step is typically 1% of the reset 475 // frequency, but can be up to 3% 476 #define POWMAN_LPOSC_TRIM_RESET _u(0x20) 477 #define POWMAN_LPOSC_TRIM_BITS _u(0x000003f0) 478 #define POWMAN_LPOSC_TRIM_MSB _u(9) 479 #define POWMAN_LPOSC_TRIM_LSB _u(4) 480 #define POWMAN_LPOSC_TRIM_ACCESS "RW" 481 // ----------------------------------------------------------------------------- 482 // Field : POWMAN_LPOSC_MODE 483 // Description : This feature has been removed 484 #define POWMAN_LPOSC_MODE_RESET _u(0x3) 485 #define POWMAN_LPOSC_MODE_BITS _u(0x00000003) 486 #define POWMAN_LPOSC_MODE_MSB _u(1) 487 #define POWMAN_LPOSC_MODE_LSB _u(0) 488 #define POWMAN_LPOSC_MODE_ACCESS "RW" 489 // ============================================================================= 490 // Register : POWMAN_CHIP_RESET 491 // Description : Chip reset control and status 492 #define POWMAN_CHIP_RESET_OFFSET _u(0x0000002c) 493 #define POWMAN_CHIP_RESET_BITS _u(0x1fef0011) 494 #define POWMAN_CHIP_RESET_RESET _u(0x00000000) 495 // ----------------------------------------------------------------------------- 496 // Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM 497 // Description : Last reset was a watchdog timeout which was configured to reset 498 // the power-on state machine 499 // This resets: 500 // double_tap flag no 501 // DP no 502 // RPAP no 503 // rescue_flag no 504 // timer no 505 // powman no 506 // swcore no 507 // psm yes 508 // and does not change the power state 509 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_RESET _u(0x0) 510 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS _u(0x10000000) 511 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_MSB _u(28) 512 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_LSB _u(28) 513 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_ACCESS "RO" 514 // ----------------------------------------------------------------------------- 515 // Field : POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ 516 // Description : Last reset was a system reset from the hazard debugger 517 // This resets: 518 // double_tap flag no 519 // DP no 520 // RPAP no 521 // rescue_flag no 522 // timer no 523 // powman no 524 // swcore no 525 // psm yes 526 // and does not change the power state 527 #define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_RESET _u(0x0) 528 #define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_BITS _u(0x08000000) 529 #define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_MSB _u(27) 530 #define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_LSB _u(27) 531 #define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_ACCESS "RO" 532 // ----------------------------------------------------------------------------- 533 // Field : POWMAN_CHIP_RESET_HAD_GLITCH_DETECT 534 // Description : Last reset was due to a power supply glitch 535 // This resets: 536 // double_tap flag no 537 // DP no 538 // RPAP no 539 // rescue_flag no 540 // timer no 541 // powman no 542 // swcore no 543 // psm yes 544 // and does not change the power state 545 #define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_RESET _u(0x0) 546 #define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_BITS _u(0x04000000) 547 #define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_MSB _u(26) 548 #define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_LSB _u(26) 549 #define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_ACCESS "RO" 550 // ----------------------------------------------------------------------------- 551 // Field : POWMAN_CHIP_RESET_HAD_SWCORE_PD 552 // Description : Last reset was a switched core powerdown 553 // This resets: 554 // double_tap flag no 555 // DP no 556 // RPAP no 557 // rescue_flag no 558 // timer no 559 // powman no 560 // swcore yes 561 // psm yes 562 // then starts the power sequencer 563 #define POWMAN_CHIP_RESET_HAD_SWCORE_PD_RESET _u(0x0) 564 #define POWMAN_CHIP_RESET_HAD_SWCORE_PD_BITS _u(0x02000000) 565 #define POWMAN_CHIP_RESET_HAD_SWCORE_PD_MSB _u(25) 566 #define POWMAN_CHIP_RESET_HAD_SWCORE_PD_LSB _u(25) 567 #define POWMAN_CHIP_RESET_HAD_SWCORE_PD_ACCESS "RO" 568 // ----------------------------------------------------------------------------- 569 // Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE 570 // Description : Last reset was a watchdog timeout which was configured to reset 571 // the switched-core 572 // This resets: 573 // double_tap flag no 574 // DP no 575 // RPAP no 576 // rescue_flag no 577 // timer no 578 // powman no 579 // swcore yes 580 // psm yes 581 // then starts the power sequencer 582 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_RESET _u(0x0) 583 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS _u(0x01000000) 584 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_MSB _u(24) 585 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_LSB _u(24) 586 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_ACCESS "RO" 587 // ----------------------------------------------------------------------------- 588 // Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN 589 // Description : Last reset was a watchdog timeout which was configured to reset 590 // the power manager 591 // This resets: 592 // double_tap flag no 593 // DP no 594 // RPAP no 595 // rescue_flag no 596 // timer yes 597 // powman yes 598 // swcore yes 599 // psm yes 600 // then starts the power sequencer 601 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_RESET _u(0x0) 602 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS _u(0x00800000) 603 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_MSB _u(23) 604 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_LSB _u(23) 605 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ACCESS "RO" 606 // ----------------------------------------------------------------------------- 607 // Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC 608 // Description : Last reset was a watchdog timeout which was configured to reset 609 // the power manager asynchronously 610 // This resets: 611 // double_tap flag no 612 // DP no 613 // RPAP no 614 // rescue_flag no 615 // timer yes 616 // powman yes 617 // swcore yes 618 // psm yes 619 // then starts the power sequencer 620 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_RESET _u(0x0) 621 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS _u(0x00400000) 622 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_MSB _u(22) 623 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_LSB _u(22) 624 #define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_ACCESS "RO" 625 // ----------------------------------------------------------------------------- 626 // Field : POWMAN_CHIP_RESET_HAD_RESCUE 627 // Description : Last reset was a rescue reset from the debugger 628 // This resets: 629 // double_tap flag no 630 // DP no 631 // RPAP no 632 // rescue_flag no, it sets this flag 633 // timer yes 634 // powman yes 635 // swcore yes 636 // psm yes 637 // then starts the power sequencer 638 #define POWMAN_CHIP_RESET_HAD_RESCUE_RESET _u(0x0) 639 #define POWMAN_CHIP_RESET_HAD_RESCUE_BITS _u(0x00200000) 640 #define POWMAN_CHIP_RESET_HAD_RESCUE_MSB _u(21) 641 #define POWMAN_CHIP_RESET_HAD_RESCUE_LSB _u(21) 642 #define POWMAN_CHIP_RESET_HAD_RESCUE_ACCESS "RO" 643 // ----------------------------------------------------------------------------- 644 // Field : POWMAN_CHIP_RESET_HAD_DP_RESET_REQ 645 // Description : Last reset was an reset request from the arm debugger 646 // This resets: 647 // double_tap flag no 648 // DP no 649 // RPAP no 650 // rescue_flag yes 651 // timer yes 652 // powman yes 653 // swcore yes 654 // psm yes 655 // then starts the power sequencer 656 #define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_RESET _u(0x0) 657 #define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_BITS _u(0x00080000) 658 #define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_MSB _u(19) 659 #define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB _u(19) 660 #define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_ACCESS "RO" 661 // ----------------------------------------------------------------------------- 662 // Field : POWMAN_CHIP_RESET_HAD_RUN_LOW 663 // Description : Last reset was from the RUN pin 664 // This resets: 665 // double_tap flag no 666 // DP yes 667 // RPAP yes 668 // rescue_flag yes 669 // timer yes 670 // powman yes 671 // swcore yes 672 // psm yes 673 // then starts the power sequencer 674 #define POWMAN_CHIP_RESET_HAD_RUN_LOW_RESET _u(0x0) 675 #define POWMAN_CHIP_RESET_HAD_RUN_LOW_BITS _u(0x00040000) 676 #define POWMAN_CHIP_RESET_HAD_RUN_LOW_MSB _u(18) 677 #define POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB _u(18) 678 #define POWMAN_CHIP_RESET_HAD_RUN_LOW_ACCESS "RO" 679 // ----------------------------------------------------------------------------- 680 // Field : POWMAN_CHIP_RESET_HAD_BOR 681 // Description : Last reset was from the brown-out detection block 682 // This resets: 683 // double_tap flag yes 684 // DP yes 685 // RPAP yes 686 // rescue_flag yes 687 // timer yes 688 // powman yes 689 // swcore yes 690 // psm yes 691 // then starts the power sequencer 692 #define POWMAN_CHIP_RESET_HAD_BOR_RESET _u(0x0) 693 #define POWMAN_CHIP_RESET_HAD_BOR_BITS _u(0x00020000) 694 #define POWMAN_CHIP_RESET_HAD_BOR_MSB _u(17) 695 #define POWMAN_CHIP_RESET_HAD_BOR_LSB _u(17) 696 #define POWMAN_CHIP_RESET_HAD_BOR_ACCESS "RO" 697 // ----------------------------------------------------------------------------- 698 // Field : POWMAN_CHIP_RESET_HAD_POR 699 // Description : Last reset was from the power-on reset 700 // This resets: 701 // double_tap flag yes 702 // DP yes 703 // RPAP yes 704 // rescue_flag yes 705 // timer yes 706 // powman yes 707 // swcore yes 708 // psm yes 709 // then starts the power sequencer 710 #define POWMAN_CHIP_RESET_HAD_POR_RESET _u(0x0) 711 #define POWMAN_CHIP_RESET_HAD_POR_BITS _u(0x00010000) 712 #define POWMAN_CHIP_RESET_HAD_POR_MSB _u(16) 713 #define POWMAN_CHIP_RESET_HAD_POR_LSB _u(16) 714 #define POWMAN_CHIP_RESET_HAD_POR_ACCESS "RO" 715 // ----------------------------------------------------------------------------- 716 // Field : POWMAN_CHIP_RESET_RESCUE_FLAG 717 // Description : This is set by a rescue reset from the RP-AP. 718 // Its purpose is to halt before the bootrom before booting from 719 // flash in order to recover from a boot lock-up. 720 // The debugger can then attach once the bootrom has been halted 721 // and flash some working code that does not lock up. 722 #define POWMAN_CHIP_RESET_RESCUE_FLAG_RESET _u(0x0) 723 #define POWMAN_CHIP_RESET_RESCUE_FLAG_BITS _u(0x00000010) 724 #define POWMAN_CHIP_RESET_RESCUE_FLAG_MSB _u(4) 725 #define POWMAN_CHIP_RESET_RESCUE_FLAG_LSB _u(4) 726 #define POWMAN_CHIP_RESET_RESCUE_FLAG_ACCESS "WC" 727 // ----------------------------------------------------------------------------- 728 // Field : POWMAN_CHIP_RESET_DOUBLE_TAP 729 // Description : This flag is set by double-tapping RUN. It tells bootcode to go 730 // into the bootloader. 731 #define POWMAN_CHIP_RESET_DOUBLE_TAP_RESET _u(0x0) 732 #define POWMAN_CHIP_RESET_DOUBLE_TAP_BITS _u(0x00000001) 733 #define POWMAN_CHIP_RESET_DOUBLE_TAP_MSB _u(0) 734 #define POWMAN_CHIP_RESET_DOUBLE_TAP_LSB _u(0) 735 #define POWMAN_CHIP_RESET_DOUBLE_TAP_ACCESS "RW" 736 // ============================================================================= 737 // Register : POWMAN_WDSEL 738 // Description : Allows a watchdog reset to reset the internal state of powman 739 // in addition to the power-on state machine (PSM). 740 // Note that powman ignores watchdog resets that do not select at 741 // least the CLOCKS stage or earlier stages in the PSM. If using 742 // these bits, it's recommended to set PSM_WDSEL to all-ones in 743 // addition to the desired bits in this register. Failing to 744 // select CLOCKS or earlier will result in the POWMAN_WDSEL 745 // register having no effect. 746 #define POWMAN_WDSEL_OFFSET _u(0x00000030) 747 #define POWMAN_WDSEL_BITS _u(0x00001111) 748 #define POWMAN_WDSEL_RESET _u(0x00000000) 749 // ----------------------------------------------------------------------------- 750 // Field : POWMAN_WDSEL_RESET_RSM 751 // Description : If set to 1, a watchdog reset will run the full power-on state 752 // machine (PSM) sequence 753 // From a user perspective it is the same as setting 754 // RSM_WDSEL_PROC_COLD 755 // From a hardware debug perspective it has the same effect as a 756 // reset from a glitch detector 757 #define POWMAN_WDSEL_RESET_RSM_RESET _u(0x0) 758 #define POWMAN_WDSEL_RESET_RSM_BITS _u(0x00001000) 759 #define POWMAN_WDSEL_RESET_RSM_MSB _u(12) 760 #define POWMAN_WDSEL_RESET_RSM_LSB _u(12) 761 #define POWMAN_WDSEL_RESET_RSM_ACCESS "RW" 762 // ----------------------------------------------------------------------------- 763 // Field : POWMAN_WDSEL_RESET_SWCORE 764 // Description : If set to 1, a watchdog reset will reset the switched core 765 // power domain and run the full power-on state machine (PSM) 766 // sequence 767 // From a user perspective it is the same as setting 768 // RSM_WDSEL_PROC_COLD 769 // From a hardware debug perspective it has the same effect as a 770 // power-on reset for the switched core power domain 771 #define POWMAN_WDSEL_RESET_SWCORE_RESET _u(0x0) 772 #define POWMAN_WDSEL_RESET_SWCORE_BITS _u(0x00000100) 773 #define POWMAN_WDSEL_RESET_SWCORE_MSB _u(8) 774 #define POWMAN_WDSEL_RESET_SWCORE_LSB _u(8) 775 #define POWMAN_WDSEL_RESET_SWCORE_ACCESS "RW" 776 // ----------------------------------------------------------------------------- 777 // Field : POWMAN_WDSEL_RESET_POWMAN 778 // Description : If set to 1, a watchdog reset will restore powman defaults, 779 // reset the timer, reset the switched core power domain 780 // and run the full power-on state machine (PSM) sequence 781 // This relies on clk_ref running. Use reset_powman_async if that 782 // may not be true 783 #define POWMAN_WDSEL_RESET_POWMAN_RESET _u(0x0) 784 #define POWMAN_WDSEL_RESET_POWMAN_BITS _u(0x00000010) 785 #define POWMAN_WDSEL_RESET_POWMAN_MSB _u(4) 786 #define POWMAN_WDSEL_RESET_POWMAN_LSB _u(4) 787 #define POWMAN_WDSEL_RESET_POWMAN_ACCESS "RW" 788 // ----------------------------------------------------------------------------- 789 // Field : POWMAN_WDSEL_RESET_POWMAN_ASYNC 790 // Description : If set to 1, a watchdog reset will restore powman defaults, 791 // reset the timer, 792 // reset the switched core domain and run the full power-on state 793 // machine (PSM) sequence 794 // This does not rely on clk_ref running 795 #define POWMAN_WDSEL_RESET_POWMAN_ASYNC_RESET _u(0x0) 796 #define POWMAN_WDSEL_RESET_POWMAN_ASYNC_BITS _u(0x00000001) 797 #define POWMAN_WDSEL_RESET_POWMAN_ASYNC_MSB _u(0) 798 #define POWMAN_WDSEL_RESET_POWMAN_ASYNC_LSB _u(0) 799 #define POWMAN_WDSEL_RESET_POWMAN_ASYNC_ACCESS "RW" 800 // ============================================================================= 801 // Register : POWMAN_SEQ_CFG 802 // Description : For configuration of the power sequencer 803 // Writes are ignored while POWMAN_STATE_CHANGING=1 804 #define POWMAN_SEQ_CFG_OFFSET _u(0x00000034) 805 #define POWMAN_SEQ_CFG_BITS _u(0x001311f3) 806 #define POWMAN_SEQ_CFG_RESET _u(0x001011f0) 807 // ----------------------------------------------------------------------------- 808 // Field : POWMAN_SEQ_CFG_USING_FAST_POWCK 809 // Description : 0 indicates the POWMAN clock is running from the low power 810 // oscillator (32kHz) 811 // 1 indicates the POWMAN clock is running from the reference 812 // clock (2-50MHz) 813 #define POWMAN_SEQ_CFG_USING_FAST_POWCK_RESET _u(0x1) 814 #define POWMAN_SEQ_CFG_USING_FAST_POWCK_BITS _u(0x00100000) 815 #define POWMAN_SEQ_CFG_USING_FAST_POWCK_MSB _u(20) 816 #define POWMAN_SEQ_CFG_USING_FAST_POWCK_LSB _u(20) 817 #define POWMAN_SEQ_CFG_USING_FAST_POWCK_ACCESS "RO" 818 // ----------------------------------------------------------------------------- 819 // Field : POWMAN_SEQ_CFG_USING_BOD_LP 820 // Description : Indicates the brown-out detector (BOD) mode 821 // 0 = BOD high power mode which is the default 822 // 1 = BOD low power mode 823 #define POWMAN_SEQ_CFG_USING_BOD_LP_RESET _u(0x0) 824 #define POWMAN_SEQ_CFG_USING_BOD_LP_BITS _u(0x00020000) 825 #define POWMAN_SEQ_CFG_USING_BOD_LP_MSB _u(17) 826 #define POWMAN_SEQ_CFG_USING_BOD_LP_LSB _u(17) 827 #define POWMAN_SEQ_CFG_USING_BOD_LP_ACCESS "RO" 828 // ----------------------------------------------------------------------------- 829 // Field : POWMAN_SEQ_CFG_USING_VREG_LP 830 // Description : Indicates the voltage regulator (VREG) mode 831 // 0 = VREG high power mode which is the default 832 // 1 = VREG low power mode 833 #define POWMAN_SEQ_CFG_USING_VREG_LP_RESET _u(0x0) 834 #define POWMAN_SEQ_CFG_USING_VREG_LP_BITS _u(0x00010000) 835 #define POWMAN_SEQ_CFG_USING_VREG_LP_MSB _u(16) 836 #define POWMAN_SEQ_CFG_USING_VREG_LP_LSB _u(16) 837 #define POWMAN_SEQ_CFG_USING_VREG_LP_ACCESS "RO" 838 // ----------------------------------------------------------------------------- 839 // Field : POWMAN_SEQ_CFG_USE_FAST_POWCK 840 // Description : selects the reference clock (clk_ref) as the source of the 841 // POWMAN clock when switched-core is powered. The POWMAN clock 842 // always switches to the slow clock (lposc) when switched-core is 843 // powered down because the fast clock stops running. 844 // 0 always run the POWMAN clock from the slow clock (lposc) 845 // 1 run the POWMAN clock from the fast clock when available 846 // This setting takes effect when a power up sequence is next run 847 #define POWMAN_SEQ_CFG_USE_FAST_POWCK_RESET _u(0x1) 848 #define POWMAN_SEQ_CFG_USE_FAST_POWCK_BITS _u(0x00001000) 849 #define POWMAN_SEQ_CFG_USE_FAST_POWCK_MSB _u(12) 850 #define POWMAN_SEQ_CFG_USE_FAST_POWCK_LSB _u(12) 851 #define POWMAN_SEQ_CFG_USE_FAST_POWCK_ACCESS "RW" 852 // ----------------------------------------------------------------------------- 853 // Field : POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP 854 // Description : Set to 0 to stop the low power osc when the switched-core is 855 // powered down, which is unwise if using it to clock the timer 856 // This setting takes effect when the swcore is next powered down 857 #define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_RESET _u(0x1) 858 #define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_BITS _u(0x00000100) 859 #define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_MSB _u(8) 860 #define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_LSB _u(8) 861 #define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_ACCESS "RW" 862 // ----------------------------------------------------------------------------- 863 // Field : POWMAN_SEQ_CFG_USE_BOD_HP 864 // Description : Set to 0 to prevent automatic switching to bod high power mode 865 // when switched-core is powered up 866 // This setting takes effect when the swcore is next powered up 867 #define POWMAN_SEQ_CFG_USE_BOD_HP_RESET _u(0x1) 868 #define POWMAN_SEQ_CFG_USE_BOD_HP_BITS _u(0x00000080) 869 #define POWMAN_SEQ_CFG_USE_BOD_HP_MSB _u(7) 870 #define POWMAN_SEQ_CFG_USE_BOD_HP_LSB _u(7) 871 #define POWMAN_SEQ_CFG_USE_BOD_HP_ACCESS "RW" 872 // ----------------------------------------------------------------------------- 873 // Field : POWMAN_SEQ_CFG_USE_BOD_LP 874 // Description : Set to 0 to prevent automatic switching to bod low power mode 875 // when switched-core is powered down 876 // This setting takes effect when the swcore is next powered down 877 #define POWMAN_SEQ_CFG_USE_BOD_LP_RESET _u(0x1) 878 #define POWMAN_SEQ_CFG_USE_BOD_LP_BITS _u(0x00000040) 879 #define POWMAN_SEQ_CFG_USE_BOD_LP_MSB _u(6) 880 #define POWMAN_SEQ_CFG_USE_BOD_LP_LSB _u(6) 881 #define POWMAN_SEQ_CFG_USE_BOD_LP_ACCESS "RW" 882 // ----------------------------------------------------------------------------- 883 // Field : POWMAN_SEQ_CFG_USE_VREG_HP 884 // Description : Set to 0 to prevent automatic switching to vreg high power mode 885 // when switched-core is powered up 886 // This setting takes effect when the swcore is next powered up 887 #define POWMAN_SEQ_CFG_USE_VREG_HP_RESET _u(0x1) 888 #define POWMAN_SEQ_CFG_USE_VREG_HP_BITS _u(0x00000020) 889 #define POWMAN_SEQ_CFG_USE_VREG_HP_MSB _u(5) 890 #define POWMAN_SEQ_CFG_USE_VREG_HP_LSB _u(5) 891 #define POWMAN_SEQ_CFG_USE_VREG_HP_ACCESS "RW" 892 // ----------------------------------------------------------------------------- 893 // Field : POWMAN_SEQ_CFG_USE_VREG_LP 894 // Description : Set to 0 to prevent automatic switching to vreg low power mode 895 // when switched-core is powered down 896 // This setting takes effect when the swcore is next powered down 897 #define POWMAN_SEQ_CFG_USE_VREG_LP_RESET _u(0x1) 898 #define POWMAN_SEQ_CFG_USE_VREG_LP_BITS _u(0x00000010) 899 #define POWMAN_SEQ_CFG_USE_VREG_LP_MSB _u(4) 900 #define POWMAN_SEQ_CFG_USE_VREG_LP_LSB _u(4) 901 #define POWMAN_SEQ_CFG_USE_VREG_LP_ACCESS "RW" 902 // ----------------------------------------------------------------------------- 903 // Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM0 904 // Description : Specifies the power state of SRAM0 when powering up swcore from 905 // a low power state (P1.xxx) to a high power state (P0.0xx). 906 // 0=power-up 907 // 1=no change 908 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_RESET _u(0x0) 909 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS _u(0x00000002) 910 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_MSB _u(1) 911 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_LSB _u(1) 912 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_ACCESS "RW" 913 // ----------------------------------------------------------------------------- 914 // Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM1 915 // Description : Specifies the power state of SRAM1 when powering up swcore from 916 // a low power state (P1.xxx) to a high power state (P0.0xx). 917 // 0=power-up 918 // 1=no change 919 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_RESET _u(0x0) 920 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS _u(0x00000001) 921 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_MSB _u(0) 922 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_LSB _u(0) 923 #define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_ACCESS "RW" 924 // ============================================================================= 925 // Register : POWMAN_STATE 926 // Description : This register controls the power state of the 4 power domains. 927 // The current power state is indicated in POWMAN_STATE_CURRENT 928 // which is read-only. 929 // To change the state, write to POWMAN_STATE_REQ. 930 // The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ 931 // corresponds to the power states 932 // defined in the datasheet: 933 // bit 3 = SWCORE 934 // bit 2 = XIP cache 935 // bit 1 = SRAM0 936 // bit 0 = SRAM1 937 // 0 = powered up 938 // 1 = powered down 939 // When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag 940 // is set while the Power Manager determines what is required. If 941 // an invalid transition is requested the Power Manager will still 942 // register the request in POWMAN_STATE_REQ but will also set the 943 // POWMAN_BAD_REQ flag. It will then implement the power-up 944 // requests and ignore the power down requests. To do nothing 945 // would risk entering an unrecoverable lock-up state. Invalid 946 // requests are: any combination of power up and power down 947 // requests any request that results in swcore boing powered and 948 // xip unpowered If the request is to power down the switched-core 949 // domain then POWMAN_STATE_WAITING stays active until the 950 // processors halt. During this time the POWMAN_STATE_REQ field 951 // can be re-written to change or cancel the request. When the 952 // power state transition begins the POWMAN_STATE_WAITING_flag is 953 // cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN 954 // register writes are ignored until the transition completes. 955 #define POWMAN_STATE_OFFSET _u(0x00000038) 956 #define POWMAN_STATE_BITS _u(0x00003fff) 957 #define POWMAN_STATE_RESET _u(0x0000000f) 958 // ----------------------------------------------------------------------------- 959 // Field : POWMAN_STATE_CHANGING 960 #define POWMAN_STATE_CHANGING_RESET _u(0x0) 961 #define POWMAN_STATE_CHANGING_BITS _u(0x00002000) 962 #define POWMAN_STATE_CHANGING_MSB _u(13) 963 #define POWMAN_STATE_CHANGING_LSB _u(13) 964 #define POWMAN_STATE_CHANGING_ACCESS "RO" 965 // ----------------------------------------------------------------------------- 966 // Field : POWMAN_STATE_WAITING 967 #define POWMAN_STATE_WAITING_RESET _u(0x0) 968 #define POWMAN_STATE_WAITING_BITS _u(0x00001000) 969 #define POWMAN_STATE_WAITING_MSB _u(12) 970 #define POWMAN_STATE_WAITING_LSB _u(12) 971 #define POWMAN_STATE_WAITING_ACCESS "RO" 972 // ----------------------------------------------------------------------------- 973 // Field : POWMAN_STATE_BAD_HW_REQ 974 // Description : Bad hardware initiated state request. Went back to state 0 975 // (i.e. everything powered up) 976 #define POWMAN_STATE_BAD_HW_REQ_RESET _u(0x0) 977 #define POWMAN_STATE_BAD_HW_REQ_BITS _u(0x00000800) 978 #define POWMAN_STATE_BAD_HW_REQ_MSB _u(11) 979 #define POWMAN_STATE_BAD_HW_REQ_LSB _u(11) 980 #define POWMAN_STATE_BAD_HW_REQ_ACCESS "RO" 981 // ----------------------------------------------------------------------------- 982 // Field : POWMAN_STATE_BAD_SW_REQ 983 // Description : Bad software initiated state request. No action taken. 984 #define POWMAN_STATE_BAD_SW_REQ_RESET _u(0x0) 985 #define POWMAN_STATE_BAD_SW_REQ_BITS _u(0x00000400) 986 #define POWMAN_STATE_BAD_SW_REQ_MSB _u(10) 987 #define POWMAN_STATE_BAD_SW_REQ_LSB _u(10) 988 #define POWMAN_STATE_BAD_SW_REQ_ACCESS "RO" 989 // ----------------------------------------------------------------------------- 990 // Field : POWMAN_STATE_PWRUP_WHILE_WAITING 991 // Description : Request ignored because of a pending pwrup request. See 992 // current_pwrup_req. Note this blocks powering up AND powering 993 // down. 994 #define POWMAN_STATE_PWRUP_WHILE_WAITING_RESET _u(0x0) 995 #define POWMAN_STATE_PWRUP_WHILE_WAITING_BITS _u(0x00000200) 996 #define POWMAN_STATE_PWRUP_WHILE_WAITING_MSB _u(9) 997 #define POWMAN_STATE_PWRUP_WHILE_WAITING_LSB _u(9) 998 #define POWMAN_STATE_PWRUP_WHILE_WAITING_ACCESS "WC" 999 // ----------------------------------------------------------------------------- 1000 // Field : POWMAN_STATE_REQ_IGNORED 1001 #define POWMAN_STATE_REQ_IGNORED_RESET _u(0x0) 1002 #define POWMAN_STATE_REQ_IGNORED_BITS _u(0x00000100) 1003 #define POWMAN_STATE_REQ_IGNORED_MSB _u(8) 1004 #define POWMAN_STATE_REQ_IGNORED_LSB _u(8) 1005 #define POWMAN_STATE_REQ_IGNORED_ACCESS "WC" 1006 // ----------------------------------------------------------------------------- 1007 // Field : POWMAN_STATE_REQ 1008 #define POWMAN_STATE_REQ_RESET _u(0x0) 1009 #define POWMAN_STATE_REQ_BITS _u(0x000000f0) 1010 #define POWMAN_STATE_REQ_MSB _u(7) 1011 #define POWMAN_STATE_REQ_LSB _u(4) 1012 #define POWMAN_STATE_REQ_ACCESS "RW" 1013 // ----------------------------------------------------------------------------- 1014 // Field : POWMAN_STATE_CURRENT 1015 #define POWMAN_STATE_CURRENT_RESET _u(0xf) 1016 #define POWMAN_STATE_CURRENT_BITS _u(0x0000000f) 1017 #define POWMAN_STATE_CURRENT_MSB _u(3) 1018 #define POWMAN_STATE_CURRENT_LSB _u(0) 1019 #define POWMAN_STATE_CURRENT_ACCESS "RO" 1020 // ============================================================================= 1021 // Register : POWMAN_POW_FASTDIV 1022 // Description : None 1023 // divides the POWMAN clock to provide a tick for the delay module 1024 // and state machines 1025 // when clk_pow is running from the slow clock it is not divided 1026 // when clk_pow is running from the fast clock it is divided by 1027 // tick_div 1028 #define POWMAN_POW_FASTDIV_OFFSET _u(0x0000003c) 1029 #define POWMAN_POW_FASTDIV_BITS _u(0x000007ff) 1030 #define POWMAN_POW_FASTDIV_RESET _u(0x00000040) 1031 #define POWMAN_POW_FASTDIV_MSB _u(10) 1032 #define POWMAN_POW_FASTDIV_LSB _u(0) 1033 #define POWMAN_POW_FASTDIV_ACCESS "RW" 1034 // ============================================================================= 1035 // Register : POWMAN_POW_DELAY 1036 // Description : power state machine delays 1037 #define POWMAN_POW_DELAY_OFFSET _u(0x00000040) 1038 #define POWMAN_POW_DELAY_BITS _u(0x0000ffff) 1039 #define POWMAN_POW_DELAY_RESET _u(0x00002011) 1040 // ----------------------------------------------------------------------------- 1041 // Field : POWMAN_POW_DELAY_SRAM_STEP 1042 // Description : timing between the sram0 and sram1 power state machine steps 1043 // measured in units of the powman tick period (>=1us), 0 gives a 1044 // delay of 1 unit 1045 #define POWMAN_POW_DELAY_SRAM_STEP_RESET _u(0x20) 1046 #define POWMAN_POW_DELAY_SRAM_STEP_BITS _u(0x0000ff00) 1047 #define POWMAN_POW_DELAY_SRAM_STEP_MSB _u(15) 1048 #define POWMAN_POW_DELAY_SRAM_STEP_LSB _u(8) 1049 #define POWMAN_POW_DELAY_SRAM_STEP_ACCESS "RW" 1050 // ----------------------------------------------------------------------------- 1051 // Field : POWMAN_POW_DELAY_XIP_STEP 1052 // Description : timing between the xip power state machine steps 1053 // measured in units of the lposc period, 0 gives a delay of 1 1054 // unit 1055 #define POWMAN_POW_DELAY_XIP_STEP_RESET _u(0x1) 1056 #define POWMAN_POW_DELAY_XIP_STEP_BITS _u(0x000000f0) 1057 #define POWMAN_POW_DELAY_XIP_STEP_MSB _u(7) 1058 #define POWMAN_POW_DELAY_XIP_STEP_LSB _u(4) 1059 #define POWMAN_POW_DELAY_XIP_STEP_ACCESS "RW" 1060 // ----------------------------------------------------------------------------- 1061 // Field : POWMAN_POW_DELAY_SWCORE_STEP 1062 // Description : timing between the swcore power state machine steps 1063 // measured in units of the lposc period, 0 gives a delay of 1 1064 // unit 1065 #define POWMAN_POW_DELAY_SWCORE_STEP_RESET _u(0x1) 1066 #define POWMAN_POW_DELAY_SWCORE_STEP_BITS _u(0x0000000f) 1067 #define POWMAN_POW_DELAY_SWCORE_STEP_MSB _u(3) 1068 #define POWMAN_POW_DELAY_SWCORE_STEP_LSB _u(0) 1069 #define POWMAN_POW_DELAY_SWCORE_STEP_ACCESS "RW" 1070 // ============================================================================= 1071 // Register : POWMAN_EXT_CTRL0 1072 // Description : Configures a gpio as a power mode aware control output 1073 #define POWMAN_EXT_CTRL0_OFFSET _u(0x00000044) 1074 #define POWMAN_EXT_CTRL0_BITS _u(0x0000713f) 1075 #define POWMAN_EXT_CTRL0_RESET _u(0x0000003f) 1076 // ----------------------------------------------------------------------------- 1077 // Field : POWMAN_EXT_CTRL0_LP_EXIT_STATE 1078 // Description : output level when exiting the low power state 1079 #define POWMAN_EXT_CTRL0_LP_EXIT_STATE_RESET _u(0x0) 1080 #define POWMAN_EXT_CTRL0_LP_EXIT_STATE_BITS _u(0x00004000) 1081 #define POWMAN_EXT_CTRL0_LP_EXIT_STATE_MSB _u(14) 1082 #define POWMAN_EXT_CTRL0_LP_EXIT_STATE_LSB _u(14) 1083 #define POWMAN_EXT_CTRL0_LP_EXIT_STATE_ACCESS "RW" 1084 // ----------------------------------------------------------------------------- 1085 // Field : POWMAN_EXT_CTRL0_LP_ENTRY_STATE 1086 // Description : output level when entering the low power state 1087 #define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_RESET _u(0x0) 1088 #define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_BITS _u(0x00002000) 1089 #define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_MSB _u(13) 1090 #define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_LSB _u(13) 1091 #define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_ACCESS "RW" 1092 // ----------------------------------------------------------------------------- 1093 // Field : POWMAN_EXT_CTRL0_INIT_STATE 1094 #define POWMAN_EXT_CTRL0_INIT_STATE_RESET _u(0x0) 1095 #define POWMAN_EXT_CTRL0_INIT_STATE_BITS _u(0x00001000) 1096 #define POWMAN_EXT_CTRL0_INIT_STATE_MSB _u(12) 1097 #define POWMAN_EXT_CTRL0_INIT_STATE_LSB _u(12) 1098 #define POWMAN_EXT_CTRL0_INIT_STATE_ACCESS "RW" 1099 // ----------------------------------------------------------------------------- 1100 // Field : POWMAN_EXT_CTRL0_INIT 1101 #define POWMAN_EXT_CTRL0_INIT_RESET _u(0x0) 1102 #define POWMAN_EXT_CTRL0_INIT_BITS _u(0x00000100) 1103 #define POWMAN_EXT_CTRL0_INIT_MSB _u(8) 1104 #define POWMAN_EXT_CTRL0_INIT_LSB _u(8) 1105 #define POWMAN_EXT_CTRL0_INIT_ACCESS "RW" 1106 // ----------------------------------------------------------------------------- 1107 // Field : POWMAN_EXT_CTRL0_GPIO_SELECT 1108 // Description : selects from gpio 0->30 1109 // set to 31 to disable this feature 1110 #define POWMAN_EXT_CTRL0_GPIO_SELECT_RESET _u(0x3f) 1111 #define POWMAN_EXT_CTRL0_GPIO_SELECT_BITS _u(0x0000003f) 1112 #define POWMAN_EXT_CTRL0_GPIO_SELECT_MSB _u(5) 1113 #define POWMAN_EXT_CTRL0_GPIO_SELECT_LSB _u(0) 1114 #define POWMAN_EXT_CTRL0_GPIO_SELECT_ACCESS "RW" 1115 // ============================================================================= 1116 // Register : POWMAN_EXT_CTRL1 1117 // Description : Configures a gpio as a power mode aware control output 1118 #define POWMAN_EXT_CTRL1_OFFSET _u(0x00000048) 1119 #define POWMAN_EXT_CTRL1_BITS _u(0x0000713f) 1120 #define POWMAN_EXT_CTRL1_RESET _u(0x0000003f) 1121 // ----------------------------------------------------------------------------- 1122 // Field : POWMAN_EXT_CTRL1_LP_EXIT_STATE 1123 // Description : output level when exiting the low power state 1124 #define POWMAN_EXT_CTRL1_LP_EXIT_STATE_RESET _u(0x0) 1125 #define POWMAN_EXT_CTRL1_LP_EXIT_STATE_BITS _u(0x00004000) 1126 #define POWMAN_EXT_CTRL1_LP_EXIT_STATE_MSB _u(14) 1127 #define POWMAN_EXT_CTRL1_LP_EXIT_STATE_LSB _u(14) 1128 #define POWMAN_EXT_CTRL1_LP_EXIT_STATE_ACCESS "RW" 1129 // ----------------------------------------------------------------------------- 1130 // Field : POWMAN_EXT_CTRL1_LP_ENTRY_STATE 1131 // Description : output level when entering the low power state 1132 #define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_RESET _u(0x0) 1133 #define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_BITS _u(0x00002000) 1134 #define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_MSB _u(13) 1135 #define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_LSB _u(13) 1136 #define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_ACCESS "RW" 1137 // ----------------------------------------------------------------------------- 1138 // Field : POWMAN_EXT_CTRL1_INIT_STATE 1139 #define POWMAN_EXT_CTRL1_INIT_STATE_RESET _u(0x0) 1140 #define POWMAN_EXT_CTRL1_INIT_STATE_BITS _u(0x00001000) 1141 #define POWMAN_EXT_CTRL1_INIT_STATE_MSB _u(12) 1142 #define POWMAN_EXT_CTRL1_INIT_STATE_LSB _u(12) 1143 #define POWMAN_EXT_CTRL1_INIT_STATE_ACCESS "RW" 1144 // ----------------------------------------------------------------------------- 1145 // Field : POWMAN_EXT_CTRL1_INIT 1146 #define POWMAN_EXT_CTRL1_INIT_RESET _u(0x0) 1147 #define POWMAN_EXT_CTRL1_INIT_BITS _u(0x00000100) 1148 #define POWMAN_EXT_CTRL1_INIT_MSB _u(8) 1149 #define POWMAN_EXT_CTRL1_INIT_LSB _u(8) 1150 #define POWMAN_EXT_CTRL1_INIT_ACCESS "RW" 1151 // ----------------------------------------------------------------------------- 1152 // Field : POWMAN_EXT_CTRL1_GPIO_SELECT 1153 // Description : selects from gpio 0->30 1154 // set to 31 to disable this feature 1155 #define POWMAN_EXT_CTRL1_GPIO_SELECT_RESET _u(0x3f) 1156 #define POWMAN_EXT_CTRL1_GPIO_SELECT_BITS _u(0x0000003f) 1157 #define POWMAN_EXT_CTRL1_GPIO_SELECT_MSB _u(5) 1158 #define POWMAN_EXT_CTRL1_GPIO_SELECT_LSB _u(0) 1159 #define POWMAN_EXT_CTRL1_GPIO_SELECT_ACCESS "RW" 1160 // ============================================================================= 1161 // Register : POWMAN_EXT_TIME_REF 1162 // Description : Select a GPIO to use as a time reference, the source can be 1163 // used to drive the low power clock at 32kHz, or to provide a 1ms 1164 // tick to the timer, or provide a 1Hz tick to the timer. The tick 1165 // selection is controlled by the POWMAN_TIMER register. 1166 #define POWMAN_EXT_TIME_REF_OFFSET _u(0x0000004c) 1167 #define POWMAN_EXT_TIME_REF_BITS _u(0x00000013) 1168 #define POWMAN_EXT_TIME_REF_RESET _u(0x00000000) 1169 // ----------------------------------------------------------------------------- 1170 // Field : POWMAN_EXT_TIME_REF_DRIVE_LPCK 1171 // Description : Use the selected GPIO to drive the 32kHz low power clock, in 1172 // place of LPOSC. This field must only be written when 1173 // POWMAN_TIMER_RUN=0 1174 #define POWMAN_EXT_TIME_REF_DRIVE_LPCK_RESET _u(0x0) 1175 #define POWMAN_EXT_TIME_REF_DRIVE_LPCK_BITS _u(0x00000010) 1176 #define POWMAN_EXT_TIME_REF_DRIVE_LPCK_MSB _u(4) 1177 #define POWMAN_EXT_TIME_REF_DRIVE_LPCK_LSB _u(4) 1178 #define POWMAN_EXT_TIME_REF_DRIVE_LPCK_ACCESS "RW" 1179 // ----------------------------------------------------------------------------- 1180 // Field : POWMAN_EXT_TIME_REF_SOURCE_SEL 1181 // Description : 0 -> gpio12 1182 // 1 -> gpio20 1183 // 2 -> gpio14 1184 // 3 -> gpio22 1185 #define POWMAN_EXT_TIME_REF_SOURCE_SEL_RESET _u(0x0) 1186 #define POWMAN_EXT_TIME_REF_SOURCE_SEL_BITS _u(0x00000003) 1187 #define POWMAN_EXT_TIME_REF_SOURCE_SEL_MSB _u(1) 1188 #define POWMAN_EXT_TIME_REF_SOURCE_SEL_LSB _u(0) 1189 #define POWMAN_EXT_TIME_REF_SOURCE_SEL_ACCESS "RW" 1190 // ============================================================================= 1191 // Register : POWMAN_LPOSC_FREQ_KHZ_INT 1192 // Description : Informs the AON Timer of the integer component of the clock 1193 // frequency when running off the LPOSC. 1194 // Integer component of the LPOSC or GPIO clock source frequency 1195 // in kHz. Default = 32 This field must only be written when 1196 // POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 1197 #define POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET _u(0x00000050) 1198 #define POWMAN_LPOSC_FREQ_KHZ_INT_BITS _u(0x0000003f) 1199 #define POWMAN_LPOSC_FREQ_KHZ_INT_RESET _u(0x00000020) 1200 #define POWMAN_LPOSC_FREQ_KHZ_INT_MSB _u(5) 1201 #define POWMAN_LPOSC_FREQ_KHZ_INT_LSB _u(0) 1202 #define POWMAN_LPOSC_FREQ_KHZ_INT_ACCESS "RW" 1203 // ============================================================================= 1204 // Register : POWMAN_LPOSC_FREQ_KHZ_FRAC 1205 // Description : Informs the AON Timer of the fractional component of the clock 1206 // frequency when running off the LPOSC. 1207 // Fractional component of the LPOSC or GPIO clock source 1208 // frequency in kHz. Default = 0.768 This field must only be 1209 // written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 1210 #define POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET _u(0x00000054) 1211 #define POWMAN_LPOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) 1212 #define POWMAN_LPOSC_FREQ_KHZ_FRAC_RESET _u(0x0000c49c) 1213 #define POWMAN_LPOSC_FREQ_KHZ_FRAC_MSB _u(15) 1214 #define POWMAN_LPOSC_FREQ_KHZ_FRAC_LSB _u(0) 1215 #define POWMAN_LPOSC_FREQ_KHZ_FRAC_ACCESS "RW" 1216 // ============================================================================= 1217 // Register : POWMAN_XOSC_FREQ_KHZ_INT 1218 // Description : Informs the AON Timer of the integer component of the clock 1219 // frequency when running off the XOSC. 1220 // Integer component of the XOSC frequency in kHz. Default = 12000 1221 // Must be >1 This field must only be written when 1222 // POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 1223 #define POWMAN_XOSC_FREQ_KHZ_INT_OFFSET _u(0x00000058) 1224 #define POWMAN_XOSC_FREQ_KHZ_INT_BITS _u(0x0000ffff) 1225 #define POWMAN_XOSC_FREQ_KHZ_INT_RESET _u(0x00002ee0) 1226 #define POWMAN_XOSC_FREQ_KHZ_INT_MSB _u(15) 1227 #define POWMAN_XOSC_FREQ_KHZ_INT_LSB _u(0) 1228 #define POWMAN_XOSC_FREQ_KHZ_INT_ACCESS "RW" 1229 // ============================================================================= 1230 // Register : POWMAN_XOSC_FREQ_KHZ_FRAC 1231 // Description : Informs the AON Timer of the fractional component of the clock 1232 // frequency when running off the XOSC. 1233 // Fractional component of the XOSC frequency in kHz. This field 1234 // must only be written when POWMAN_TIMER_RUN=0 or 1235 // POWMAN_TIMER_USING_XOSC=0 1236 #define POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET _u(0x0000005c) 1237 #define POWMAN_XOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) 1238 #define POWMAN_XOSC_FREQ_KHZ_FRAC_RESET _u(0x00000000) 1239 #define POWMAN_XOSC_FREQ_KHZ_FRAC_MSB _u(15) 1240 #define POWMAN_XOSC_FREQ_KHZ_FRAC_LSB _u(0) 1241 #define POWMAN_XOSC_FREQ_KHZ_FRAC_ACCESS "RW" 1242 // ============================================================================= 1243 // Register : POWMAN_SET_TIME_63TO48 1244 // Description : None 1245 // For setting the time, do not use for reading the time, use 1246 // POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field 1247 // must only be written when POWMAN_TIMER_RUN=0 1248 #define POWMAN_SET_TIME_63TO48_OFFSET _u(0x00000060) 1249 #define POWMAN_SET_TIME_63TO48_BITS _u(0x0000ffff) 1250 #define POWMAN_SET_TIME_63TO48_RESET _u(0x00000000) 1251 #define POWMAN_SET_TIME_63TO48_MSB _u(15) 1252 #define POWMAN_SET_TIME_63TO48_LSB _u(0) 1253 #define POWMAN_SET_TIME_63TO48_ACCESS "RW" 1254 // ============================================================================= 1255 // Register : POWMAN_SET_TIME_47TO32 1256 // Description : None 1257 // For setting the time, do not use for reading the time, use 1258 // POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field 1259 // must only be written when POWMAN_TIMER_RUN=0 1260 #define POWMAN_SET_TIME_47TO32_OFFSET _u(0x00000064) 1261 #define POWMAN_SET_TIME_47TO32_BITS _u(0x0000ffff) 1262 #define POWMAN_SET_TIME_47TO32_RESET _u(0x00000000) 1263 #define POWMAN_SET_TIME_47TO32_MSB _u(15) 1264 #define POWMAN_SET_TIME_47TO32_LSB _u(0) 1265 #define POWMAN_SET_TIME_47TO32_ACCESS "RW" 1266 // ============================================================================= 1267 // Register : POWMAN_SET_TIME_31TO16 1268 // Description : None 1269 // For setting the time, do not use for reading the time, use 1270 // POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field 1271 // must only be written when POWMAN_TIMER_RUN=0 1272 #define POWMAN_SET_TIME_31TO16_OFFSET _u(0x00000068) 1273 #define POWMAN_SET_TIME_31TO16_BITS _u(0x0000ffff) 1274 #define POWMAN_SET_TIME_31TO16_RESET _u(0x00000000) 1275 #define POWMAN_SET_TIME_31TO16_MSB _u(15) 1276 #define POWMAN_SET_TIME_31TO16_LSB _u(0) 1277 #define POWMAN_SET_TIME_31TO16_ACCESS "RW" 1278 // ============================================================================= 1279 // Register : POWMAN_SET_TIME_15TO0 1280 // Description : None 1281 // For setting the time, do not use for reading the time, use 1282 // POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field 1283 // must only be written when POWMAN_TIMER_RUN=0 1284 #define POWMAN_SET_TIME_15TO0_OFFSET _u(0x0000006c) 1285 #define POWMAN_SET_TIME_15TO0_BITS _u(0x0000ffff) 1286 #define POWMAN_SET_TIME_15TO0_RESET _u(0x00000000) 1287 #define POWMAN_SET_TIME_15TO0_MSB _u(15) 1288 #define POWMAN_SET_TIME_15TO0_LSB _u(0) 1289 #define POWMAN_SET_TIME_15TO0_ACCESS "RW" 1290 // ============================================================================= 1291 // Register : POWMAN_READ_TIME_UPPER 1292 // Description : None 1293 // For reading bits 63:32 of the timer. When reading all 64 bits 1294 // it is possible for the LOWER count to rollover during the read. 1295 // It is recommended to read UPPER, then LOWER, then re-read UPPER 1296 // and, if it has changed, re-read LOWER. 1297 #define POWMAN_READ_TIME_UPPER_OFFSET _u(0x00000070) 1298 #define POWMAN_READ_TIME_UPPER_BITS _u(0xffffffff) 1299 #define POWMAN_READ_TIME_UPPER_RESET _u(0x00000000) 1300 #define POWMAN_READ_TIME_UPPER_MSB _u(31) 1301 #define POWMAN_READ_TIME_UPPER_LSB _u(0) 1302 #define POWMAN_READ_TIME_UPPER_ACCESS "RO" 1303 // ============================================================================= 1304 // Register : POWMAN_READ_TIME_LOWER 1305 // Description : None 1306 // For reading bits 31:0 of the timer. 1307 #define POWMAN_READ_TIME_LOWER_OFFSET _u(0x00000074) 1308 #define POWMAN_READ_TIME_LOWER_BITS _u(0xffffffff) 1309 #define POWMAN_READ_TIME_LOWER_RESET _u(0x00000000) 1310 #define POWMAN_READ_TIME_LOWER_MSB _u(31) 1311 #define POWMAN_READ_TIME_LOWER_LSB _u(0) 1312 #define POWMAN_READ_TIME_LOWER_ACCESS "RO" 1313 // ============================================================================= 1314 // Register : POWMAN_ALARM_TIME_63TO48 1315 // Description : None 1316 // This field must only be written when POWMAN_ALARM_ENAB=0 1317 #define POWMAN_ALARM_TIME_63TO48_OFFSET _u(0x00000078) 1318 #define POWMAN_ALARM_TIME_63TO48_BITS _u(0x0000ffff) 1319 #define POWMAN_ALARM_TIME_63TO48_RESET _u(0x00000000) 1320 #define POWMAN_ALARM_TIME_63TO48_MSB _u(15) 1321 #define POWMAN_ALARM_TIME_63TO48_LSB _u(0) 1322 #define POWMAN_ALARM_TIME_63TO48_ACCESS "RW" 1323 // ============================================================================= 1324 // Register : POWMAN_ALARM_TIME_47TO32 1325 // Description : None 1326 // This field must only be written when POWMAN_ALARM_ENAB=0 1327 #define POWMAN_ALARM_TIME_47TO32_OFFSET _u(0x0000007c) 1328 #define POWMAN_ALARM_TIME_47TO32_BITS _u(0x0000ffff) 1329 #define POWMAN_ALARM_TIME_47TO32_RESET _u(0x00000000) 1330 #define POWMAN_ALARM_TIME_47TO32_MSB _u(15) 1331 #define POWMAN_ALARM_TIME_47TO32_LSB _u(0) 1332 #define POWMAN_ALARM_TIME_47TO32_ACCESS "RW" 1333 // ============================================================================= 1334 // Register : POWMAN_ALARM_TIME_31TO16 1335 // Description : None 1336 // This field must only be written when POWMAN_ALARM_ENAB=0 1337 #define POWMAN_ALARM_TIME_31TO16_OFFSET _u(0x00000080) 1338 #define POWMAN_ALARM_TIME_31TO16_BITS _u(0x0000ffff) 1339 #define POWMAN_ALARM_TIME_31TO16_RESET _u(0x00000000) 1340 #define POWMAN_ALARM_TIME_31TO16_MSB _u(15) 1341 #define POWMAN_ALARM_TIME_31TO16_LSB _u(0) 1342 #define POWMAN_ALARM_TIME_31TO16_ACCESS "RW" 1343 // ============================================================================= 1344 // Register : POWMAN_ALARM_TIME_15TO0 1345 // Description : None 1346 // This field must only be written when POWMAN_ALARM_ENAB=0 1347 #define POWMAN_ALARM_TIME_15TO0_OFFSET _u(0x00000084) 1348 #define POWMAN_ALARM_TIME_15TO0_BITS _u(0x0000ffff) 1349 #define POWMAN_ALARM_TIME_15TO0_RESET _u(0x00000000) 1350 #define POWMAN_ALARM_TIME_15TO0_MSB _u(15) 1351 #define POWMAN_ALARM_TIME_15TO0_LSB _u(0) 1352 #define POWMAN_ALARM_TIME_15TO0_ACCESS "RW" 1353 // ============================================================================= 1354 // Register : POWMAN_TIMER 1355 #define POWMAN_TIMER_OFFSET _u(0x00000088) 1356 #define POWMAN_TIMER_BITS _u(0x000f2777) 1357 #define POWMAN_TIMER_RESET _u(0x00000000) 1358 // ----------------------------------------------------------------------------- 1359 // Field : POWMAN_TIMER_USING_GPIO_1HZ 1360 // Description : Timer is synchronised to a 1hz gpio source 1361 #define POWMAN_TIMER_USING_GPIO_1HZ_RESET _u(0x0) 1362 #define POWMAN_TIMER_USING_GPIO_1HZ_BITS _u(0x00080000) 1363 #define POWMAN_TIMER_USING_GPIO_1HZ_MSB _u(19) 1364 #define POWMAN_TIMER_USING_GPIO_1HZ_LSB _u(19) 1365 #define POWMAN_TIMER_USING_GPIO_1HZ_ACCESS "RO" 1366 // ----------------------------------------------------------------------------- 1367 // Field : POWMAN_TIMER_USING_GPIO_1KHZ 1368 // Description : Timer is running from a 1khz gpio source 1369 #define POWMAN_TIMER_USING_GPIO_1KHZ_RESET _u(0x0) 1370 #define POWMAN_TIMER_USING_GPIO_1KHZ_BITS _u(0x00040000) 1371 #define POWMAN_TIMER_USING_GPIO_1KHZ_MSB _u(18) 1372 #define POWMAN_TIMER_USING_GPIO_1KHZ_LSB _u(18) 1373 #define POWMAN_TIMER_USING_GPIO_1KHZ_ACCESS "RO" 1374 // ----------------------------------------------------------------------------- 1375 // Field : POWMAN_TIMER_USING_LPOSC 1376 // Description : Timer is running from lposc 1377 #define POWMAN_TIMER_USING_LPOSC_RESET _u(0x0) 1378 #define POWMAN_TIMER_USING_LPOSC_BITS _u(0x00020000) 1379 #define POWMAN_TIMER_USING_LPOSC_MSB _u(17) 1380 #define POWMAN_TIMER_USING_LPOSC_LSB _u(17) 1381 #define POWMAN_TIMER_USING_LPOSC_ACCESS "RO" 1382 // ----------------------------------------------------------------------------- 1383 // Field : POWMAN_TIMER_USING_XOSC 1384 // Description : Timer is running from xosc 1385 #define POWMAN_TIMER_USING_XOSC_RESET _u(0x0) 1386 #define POWMAN_TIMER_USING_XOSC_BITS _u(0x00010000) 1387 #define POWMAN_TIMER_USING_XOSC_MSB _u(16) 1388 #define POWMAN_TIMER_USING_XOSC_LSB _u(16) 1389 #define POWMAN_TIMER_USING_XOSC_ACCESS "RO" 1390 // ----------------------------------------------------------------------------- 1391 // Field : POWMAN_TIMER_USE_GPIO_1HZ 1392 // Description : Selects the gpio source as the reference for the sec counter. 1393 // The msec counter will continue to use the lposc or xosc 1394 // reference. 1395 #define POWMAN_TIMER_USE_GPIO_1HZ_RESET _u(0x0) 1396 #define POWMAN_TIMER_USE_GPIO_1HZ_BITS _u(0x00002000) 1397 #define POWMAN_TIMER_USE_GPIO_1HZ_MSB _u(13) 1398 #define POWMAN_TIMER_USE_GPIO_1HZ_LSB _u(13) 1399 #define POWMAN_TIMER_USE_GPIO_1HZ_ACCESS "RW" 1400 // ----------------------------------------------------------------------------- 1401 // Field : POWMAN_TIMER_USE_GPIO_1KHZ 1402 // Description : switch to gpio as the source of the 1kHz timer tick 1403 #define POWMAN_TIMER_USE_GPIO_1KHZ_RESET _u(0x0) 1404 #define POWMAN_TIMER_USE_GPIO_1KHZ_BITS _u(0x00000400) 1405 #define POWMAN_TIMER_USE_GPIO_1KHZ_MSB _u(10) 1406 #define POWMAN_TIMER_USE_GPIO_1KHZ_LSB _u(10) 1407 #define POWMAN_TIMER_USE_GPIO_1KHZ_ACCESS "SC" 1408 // ----------------------------------------------------------------------------- 1409 // Field : POWMAN_TIMER_USE_XOSC 1410 // Description : switch to xosc as the source of the 1kHz timer tick 1411 #define POWMAN_TIMER_USE_XOSC_RESET _u(0x0) 1412 #define POWMAN_TIMER_USE_XOSC_BITS _u(0x00000200) 1413 #define POWMAN_TIMER_USE_XOSC_MSB _u(9) 1414 #define POWMAN_TIMER_USE_XOSC_LSB _u(9) 1415 #define POWMAN_TIMER_USE_XOSC_ACCESS "SC" 1416 // ----------------------------------------------------------------------------- 1417 // Field : POWMAN_TIMER_USE_LPOSC 1418 // Description : Switch to lposc as the source of the 1kHz timer tick 1419 #define POWMAN_TIMER_USE_LPOSC_RESET _u(0x0) 1420 #define POWMAN_TIMER_USE_LPOSC_BITS _u(0x00000100) 1421 #define POWMAN_TIMER_USE_LPOSC_MSB _u(8) 1422 #define POWMAN_TIMER_USE_LPOSC_LSB _u(8) 1423 #define POWMAN_TIMER_USE_LPOSC_ACCESS "SC" 1424 // ----------------------------------------------------------------------------- 1425 // Field : POWMAN_TIMER_ALARM 1426 // Description : Alarm has fired. Write to 1 to clear the alarm. 1427 #define POWMAN_TIMER_ALARM_RESET _u(0x0) 1428 #define POWMAN_TIMER_ALARM_BITS _u(0x00000040) 1429 #define POWMAN_TIMER_ALARM_MSB _u(6) 1430 #define POWMAN_TIMER_ALARM_LSB _u(6) 1431 #define POWMAN_TIMER_ALARM_ACCESS "WC" 1432 // ----------------------------------------------------------------------------- 1433 // Field : POWMAN_TIMER_PWRUP_ON_ALARM 1434 // Description : Alarm wakes the chip from low power mode 1435 #define POWMAN_TIMER_PWRUP_ON_ALARM_RESET _u(0x0) 1436 #define POWMAN_TIMER_PWRUP_ON_ALARM_BITS _u(0x00000020) 1437 #define POWMAN_TIMER_PWRUP_ON_ALARM_MSB _u(5) 1438 #define POWMAN_TIMER_PWRUP_ON_ALARM_LSB _u(5) 1439 #define POWMAN_TIMER_PWRUP_ON_ALARM_ACCESS "RW" 1440 // ----------------------------------------------------------------------------- 1441 // Field : POWMAN_TIMER_ALARM_ENAB 1442 // Description : Enables the alarm. The alarm must be disabled while writing the 1443 // alarm time. 1444 #define POWMAN_TIMER_ALARM_ENAB_RESET _u(0x0) 1445 #define POWMAN_TIMER_ALARM_ENAB_BITS _u(0x00000010) 1446 #define POWMAN_TIMER_ALARM_ENAB_MSB _u(4) 1447 #define POWMAN_TIMER_ALARM_ENAB_LSB _u(4) 1448 #define POWMAN_TIMER_ALARM_ENAB_ACCESS "RW" 1449 // ----------------------------------------------------------------------------- 1450 // Field : POWMAN_TIMER_CLEAR 1451 // Description : Clears the timer, does not disable the timer and does not 1452 // affect the alarm. This control can be written at any time. 1453 #define POWMAN_TIMER_CLEAR_RESET _u(0x0) 1454 #define POWMAN_TIMER_CLEAR_BITS _u(0x00000004) 1455 #define POWMAN_TIMER_CLEAR_MSB _u(2) 1456 #define POWMAN_TIMER_CLEAR_LSB _u(2) 1457 #define POWMAN_TIMER_CLEAR_ACCESS "SC" 1458 // ----------------------------------------------------------------------------- 1459 // Field : POWMAN_TIMER_RUN 1460 // Description : Timer enable. Setting this bit causes the timer to begin 1461 // counting up from its current value. Clearing this bit stops the 1462 // timer from counting. 1463 // 1464 // Before enabling the timer, set the POWMAN_LPOSC_FREQ* and 1465 // POWMAN_XOSC_FREQ* registers to configure the count rate, and 1466 // initialise the current time by writing to SET_TIME_63TO48 1467 // through SET_TIME_15TO0. You must not write to the SET_TIME_x 1468 // registers when the timer is running. 1469 // 1470 // Once configured, start the timer by setting POWMAN_TIMER_RUN=1. 1471 // This will start the timer running from the LPOSC. When the XOSC 1472 // is available switch the reference clock to XOSC then select it 1473 // as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 1474 #define POWMAN_TIMER_RUN_RESET _u(0x0) 1475 #define POWMAN_TIMER_RUN_BITS _u(0x00000002) 1476 #define POWMAN_TIMER_RUN_MSB _u(1) 1477 #define POWMAN_TIMER_RUN_LSB _u(1) 1478 #define POWMAN_TIMER_RUN_ACCESS "RW" 1479 // ----------------------------------------------------------------------------- 1480 // Field : POWMAN_TIMER_NONSEC_WRITE 1481 // Description : Control whether Non-secure software can write to the timer 1482 // registers. All other registers are hardwired to be inaccessible 1483 // to Non-secure. 1484 #define POWMAN_TIMER_NONSEC_WRITE_RESET _u(0x0) 1485 #define POWMAN_TIMER_NONSEC_WRITE_BITS _u(0x00000001) 1486 #define POWMAN_TIMER_NONSEC_WRITE_MSB _u(0) 1487 #define POWMAN_TIMER_NONSEC_WRITE_LSB _u(0) 1488 #define POWMAN_TIMER_NONSEC_WRITE_ACCESS "RW" 1489 // ============================================================================= 1490 // Register : POWMAN_PWRUP0 1491 // Description : 4 GPIO powerup events can be configured to wake the chip up 1492 // from a low power state. 1493 // The pwrups are level/edge sensitive and can be set to trigger 1494 // on a high/rising or low/falling event 1495 // The number of gpios available depends on the package option. An 1496 // invalid selection will be ignored 1497 // source = 0 selects gpio0 1498 // . 1499 // . 1500 // source = 47 selects gpio47 1501 // source = 48 selects qspi_ss 1502 // source = 49 selects qspi_sd0 1503 // source = 50 selects qspi_sd1 1504 // source = 51 selects qspi_sd2 1505 // source = 52 selects qspi_sd3 1506 // source = 53 selects qspi_sclk 1507 // level = 0 triggers the pwrup when the source is low 1508 // level = 1 triggers the pwrup when the source is high 1509 #define POWMAN_PWRUP0_OFFSET _u(0x0000008c) 1510 #define POWMAN_PWRUP0_BITS _u(0x000007ff) 1511 #define POWMAN_PWRUP0_RESET _u(0x0000003f) 1512 // ----------------------------------------------------------------------------- 1513 // Field : POWMAN_PWRUP0_RAW_STATUS 1514 // Description : Value of selected gpio pin (only if enable == 1) 1515 #define POWMAN_PWRUP0_RAW_STATUS_RESET _u(0x0) 1516 #define POWMAN_PWRUP0_RAW_STATUS_BITS _u(0x00000400) 1517 #define POWMAN_PWRUP0_RAW_STATUS_MSB _u(10) 1518 #define POWMAN_PWRUP0_RAW_STATUS_LSB _u(10) 1519 #define POWMAN_PWRUP0_RAW_STATUS_ACCESS "RO" 1520 // ----------------------------------------------------------------------------- 1521 // Field : POWMAN_PWRUP0_STATUS 1522 // Description : Status of gpio wakeup. Write to 1 to clear a latched edge 1523 // detect. 1524 #define POWMAN_PWRUP0_STATUS_RESET _u(0x0) 1525 #define POWMAN_PWRUP0_STATUS_BITS _u(0x00000200) 1526 #define POWMAN_PWRUP0_STATUS_MSB _u(9) 1527 #define POWMAN_PWRUP0_STATUS_LSB _u(9) 1528 #define POWMAN_PWRUP0_STATUS_ACCESS "WC" 1529 // ----------------------------------------------------------------------------- 1530 // Field : POWMAN_PWRUP0_MODE 1531 // Description : Edge or level detect. Edge will detect a 0 to 1 transition (or 1532 // 1 to 0 transition). Level will detect a 1 or 0. Both types of 1533 // event get latched into the current_pwrup_req register. 1534 // 0x0 -> level 1535 // 0x1 -> edge 1536 #define POWMAN_PWRUP0_MODE_RESET _u(0x0) 1537 #define POWMAN_PWRUP0_MODE_BITS _u(0x00000100) 1538 #define POWMAN_PWRUP0_MODE_MSB _u(8) 1539 #define POWMAN_PWRUP0_MODE_LSB _u(8) 1540 #define POWMAN_PWRUP0_MODE_ACCESS "RW" 1541 #define POWMAN_PWRUP0_MODE_VALUE_LEVEL _u(0x0) 1542 #define POWMAN_PWRUP0_MODE_VALUE_EDGE _u(0x1) 1543 // ----------------------------------------------------------------------------- 1544 // Field : POWMAN_PWRUP0_DIRECTION 1545 // 0x0 -> low_falling 1546 // 0x1 -> high_rising 1547 #define POWMAN_PWRUP0_DIRECTION_RESET _u(0x0) 1548 #define POWMAN_PWRUP0_DIRECTION_BITS _u(0x00000080) 1549 #define POWMAN_PWRUP0_DIRECTION_MSB _u(7) 1550 #define POWMAN_PWRUP0_DIRECTION_LSB _u(7) 1551 #define POWMAN_PWRUP0_DIRECTION_ACCESS "RW" 1552 #define POWMAN_PWRUP0_DIRECTION_VALUE_LOW_FALLING _u(0x0) 1553 #define POWMAN_PWRUP0_DIRECTION_VALUE_HIGH_RISING _u(0x1) 1554 // ----------------------------------------------------------------------------- 1555 // Field : POWMAN_PWRUP0_ENABLE 1556 // Description : Set to 1 to enable the wakeup source. Set to 0 to disable the 1557 // wakeup source and clear a pending wakeup event. 1558 // If using edge detect a latched edge needs to be cleared by 1559 // writing 1 to the status register also. 1560 #define POWMAN_PWRUP0_ENABLE_RESET _u(0x0) 1561 #define POWMAN_PWRUP0_ENABLE_BITS _u(0x00000040) 1562 #define POWMAN_PWRUP0_ENABLE_MSB _u(6) 1563 #define POWMAN_PWRUP0_ENABLE_LSB _u(6) 1564 #define POWMAN_PWRUP0_ENABLE_ACCESS "RW" 1565 // ----------------------------------------------------------------------------- 1566 // Field : POWMAN_PWRUP0_SOURCE 1567 #define POWMAN_PWRUP0_SOURCE_RESET _u(0x3f) 1568 #define POWMAN_PWRUP0_SOURCE_BITS _u(0x0000003f) 1569 #define POWMAN_PWRUP0_SOURCE_MSB _u(5) 1570 #define POWMAN_PWRUP0_SOURCE_LSB _u(0) 1571 #define POWMAN_PWRUP0_SOURCE_ACCESS "RW" 1572 // ============================================================================= 1573 // Register : POWMAN_PWRUP1 1574 // Description : 4 GPIO powerup events can be configured to wake the chip up 1575 // from a low power state. 1576 // The pwrups are level/edge sensitive and can be set to trigger 1577 // on a high/rising or low/falling event 1578 // The number of gpios available depends on the package option. An 1579 // invalid selection will be ignored 1580 // source = 0 selects gpio0 1581 // . 1582 // . 1583 // source = 47 selects gpio47 1584 // source = 48 selects qspi_ss 1585 // source = 49 selects qspi_sd0 1586 // source = 50 selects qspi_sd1 1587 // source = 51 selects qspi_sd2 1588 // source = 52 selects qspi_sd3 1589 // source = 53 selects qspi_sclk 1590 // level = 0 triggers the pwrup when the source is low 1591 // level = 1 triggers the pwrup when the source is high 1592 #define POWMAN_PWRUP1_OFFSET _u(0x00000090) 1593 #define POWMAN_PWRUP1_BITS _u(0x000007ff) 1594 #define POWMAN_PWRUP1_RESET _u(0x0000003f) 1595 // ----------------------------------------------------------------------------- 1596 // Field : POWMAN_PWRUP1_RAW_STATUS 1597 // Description : Value of selected gpio pin (only if enable == 1) 1598 #define POWMAN_PWRUP1_RAW_STATUS_RESET _u(0x0) 1599 #define POWMAN_PWRUP1_RAW_STATUS_BITS _u(0x00000400) 1600 #define POWMAN_PWRUP1_RAW_STATUS_MSB _u(10) 1601 #define POWMAN_PWRUP1_RAW_STATUS_LSB _u(10) 1602 #define POWMAN_PWRUP1_RAW_STATUS_ACCESS "RO" 1603 // ----------------------------------------------------------------------------- 1604 // Field : POWMAN_PWRUP1_STATUS 1605 // Description : Status of gpio wakeup. Write to 1 to clear a latched edge 1606 // detect. 1607 #define POWMAN_PWRUP1_STATUS_RESET _u(0x0) 1608 #define POWMAN_PWRUP1_STATUS_BITS _u(0x00000200) 1609 #define POWMAN_PWRUP1_STATUS_MSB _u(9) 1610 #define POWMAN_PWRUP1_STATUS_LSB _u(9) 1611 #define POWMAN_PWRUP1_STATUS_ACCESS "WC" 1612 // ----------------------------------------------------------------------------- 1613 // Field : POWMAN_PWRUP1_MODE 1614 // Description : Edge or level detect. Edge will detect a 0 to 1 transition (or 1615 // 1 to 0 transition). Level will detect a 1 or 0. Both types of 1616 // event get latched into the current_pwrup_req register. 1617 // 0x0 -> level 1618 // 0x1 -> edge 1619 #define POWMAN_PWRUP1_MODE_RESET _u(0x0) 1620 #define POWMAN_PWRUP1_MODE_BITS _u(0x00000100) 1621 #define POWMAN_PWRUP1_MODE_MSB _u(8) 1622 #define POWMAN_PWRUP1_MODE_LSB _u(8) 1623 #define POWMAN_PWRUP1_MODE_ACCESS "RW" 1624 #define POWMAN_PWRUP1_MODE_VALUE_LEVEL _u(0x0) 1625 #define POWMAN_PWRUP1_MODE_VALUE_EDGE _u(0x1) 1626 // ----------------------------------------------------------------------------- 1627 // Field : POWMAN_PWRUP1_DIRECTION 1628 // 0x0 -> low_falling 1629 // 0x1 -> high_rising 1630 #define POWMAN_PWRUP1_DIRECTION_RESET _u(0x0) 1631 #define POWMAN_PWRUP1_DIRECTION_BITS _u(0x00000080) 1632 #define POWMAN_PWRUP1_DIRECTION_MSB _u(7) 1633 #define POWMAN_PWRUP1_DIRECTION_LSB _u(7) 1634 #define POWMAN_PWRUP1_DIRECTION_ACCESS "RW" 1635 #define POWMAN_PWRUP1_DIRECTION_VALUE_LOW_FALLING _u(0x0) 1636 #define POWMAN_PWRUP1_DIRECTION_VALUE_HIGH_RISING _u(0x1) 1637 // ----------------------------------------------------------------------------- 1638 // Field : POWMAN_PWRUP1_ENABLE 1639 // Description : Set to 1 to enable the wakeup source. Set to 0 to disable the 1640 // wakeup source and clear a pending wakeup event. 1641 // If using edge detect a latched edge needs to be cleared by 1642 // writing 1 to the status register also. 1643 #define POWMAN_PWRUP1_ENABLE_RESET _u(0x0) 1644 #define POWMAN_PWRUP1_ENABLE_BITS _u(0x00000040) 1645 #define POWMAN_PWRUP1_ENABLE_MSB _u(6) 1646 #define POWMAN_PWRUP1_ENABLE_LSB _u(6) 1647 #define POWMAN_PWRUP1_ENABLE_ACCESS "RW" 1648 // ----------------------------------------------------------------------------- 1649 // Field : POWMAN_PWRUP1_SOURCE 1650 #define POWMAN_PWRUP1_SOURCE_RESET _u(0x3f) 1651 #define POWMAN_PWRUP1_SOURCE_BITS _u(0x0000003f) 1652 #define POWMAN_PWRUP1_SOURCE_MSB _u(5) 1653 #define POWMAN_PWRUP1_SOURCE_LSB _u(0) 1654 #define POWMAN_PWRUP1_SOURCE_ACCESS "RW" 1655 // ============================================================================= 1656 // Register : POWMAN_PWRUP2 1657 // Description : 4 GPIO powerup events can be configured to wake the chip up 1658 // from a low power state. 1659 // The pwrups are level/edge sensitive and can be set to trigger 1660 // on a high/rising or low/falling event 1661 // The number of gpios available depends on the package option. An 1662 // invalid selection will be ignored 1663 // source = 0 selects gpio0 1664 // . 1665 // . 1666 // source = 47 selects gpio47 1667 // source = 48 selects qspi_ss 1668 // source = 49 selects qspi_sd0 1669 // source = 50 selects qspi_sd1 1670 // source = 51 selects qspi_sd2 1671 // source = 52 selects qspi_sd3 1672 // source = 53 selects qspi_sclk 1673 // level = 0 triggers the pwrup when the source is low 1674 // level = 1 triggers the pwrup when the source is high 1675 #define POWMAN_PWRUP2_OFFSET _u(0x00000094) 1676 #define POWMAN_PWRUP2_BITS _u(0x000007ff) 1677 #define POWMAN_PWRUP2_RESET _u(0x0000003f) 1678 // ----------------------------------------------------------------------------- 1679 // Field : POWMAN_PWRUP2_RAW_STATUS 1680 // Description : Value of selected gpio pin (only if enable == 1) 1681 #define POWMAN_PWRUP2_RAW_STATUS_RESET _u(0x0) 1682 #define POWMAN_PWRUP2_RAW_STATUS_BITS _u(0x00000400) 1683 #define POWMAN_PWRUP2_RAW_STATUS_MSB _u(10) 1684 #define POWMAN_PWRUP2_RAW_STATUS_LSB _u(10) 1685 #define POWMAN_PWRUP2_RAW_STATUS_ACCESS "RO" 1686 // ----------------------------------------------------------------------------- 1687 // Field : POWMAN_PWRUP2_STATUS 1688 // Description : Status of gpio wakeup. Write to 1 to clear a latched edge 1689 // detect. 1690 #define POWMAN_PWRUP2_STATUS_RESET _u(0x0) 1691 #define POWMAN_PWRUP2_STATUS_BITS _u(0x00000200) 1692 #define POWMAN_PWRUP2_STATUS_MSB _u(9) 1693 #define POWMAN_PWRUP2_STATUS_LSB _u(9) 1694 #define POWMAN_PWRUP2_STATUS_ACCESS "WC" 1695 // ----------------------------------------------------------------------------- 1696 // Field : POWMAN_PWRUP2_MODE 1697 // Description : Edge or level detect. Edge will detect a 0 to 1 transition (or 1698 // 1 to 0 transition). Level will detect a 1 or 0. Both types of 1699 // event get latched into the current_pwrup_req register. 1700 // 0x0 -> level 1701 // 0x1 -> edge 1702 #define POWMAN_PWRUP2_MODE_RESET _u(0x0) 1703 #define POWMAN_PWRUP2_MODE_BITS _u(0x00000100) 1704 #define POWMAN_PWRUP2_MODE_MSB _u(8) 1705 #define POWMAN_PWRUP2_MODE_LSB _u(8) 1706 #define POWMAN_PWRUP2_MODE_ACCESS "RW" 1707 #define POWMAN_PWRUP2_MODE_VALUE_LEVEL _u(0x0) 1708 #define POWMAN_PWRUP2_MODE_VALUE_EDGE _u(0x1) 1709 // ----------------------------------------------------------------------------- 1710 // Field : POWMAN_PWRUP2_DIRECTION 1711 // 0x0 -> low_falling 1712 // 0x1 -> high_rising 1713 #define POWMAN_PWRUP2_DIRECTION_RESET _u(0x0) 1714 #define POWMAN_PWRUP2_DIRECTION_BITS _u(0x00000080) 1715 #define POWMAN_PWRUP2_DIRECTION_MSB _u(7) 1716 #define POWMAN_PWRUP2_DIRECTION_LSB _u(7) 1717 #define POWMAN_PWRUP2_DIRECTION_ACCESS "RW" 1718 #define POWMAN_PWRUP2_DIRECTION_VALUE_LOW_FALLING _u(0x0) 1719 #define POWMAN_PWRUP2_DIRECTION_VALUE_HIGH_RISING _u(0x1) 1720 // ----------------------------------------------------------------------------- 1721 // Field : POWMAN_PWRUP2_ENABLE 1722 // Description : Set to 1 to enable the wakeup source. Set to 0 to disable the 1723 // wakeup source and clear a pending wakeup event. 1724 // If using edge detect a latched edge needs to be cleared by 1725 // writing 1 to the status register also. 1726 #define POWMAN_PWRUP2_ENABLE_RESET _u(0x0) 1727 #define POWMAN_PWRUP2_ENABLE_BITS _u(0x00000040) 1728 #define POWMAN_PWRUP2_ENABLE_MSB _u(6) 1729 #define POWMAN_PWRUP2_ENABLE_LSB _u(6) 1730 #define POWMAN_PWRUP2_ENABLE_ACCESS "RW" 1731 // ----------------------------------------------------------------------------- 1732 // Field : POWMAN_PWRUP2_SOURCE 1733 #define POWMAN_PWRUP2_SOURCE_RESET _u(0x3f) 1734 #define POWMAN_PWRUP2_SOURCE_BITS _u(0x0000003f) 1735 #define POWMAN_PWRUP2_SOURCE_MSB _u(5) 1736 #define POWMAN_PWRUP2_SOURCE_LSB _u(0) 1737 #define POWMAN_PWRUP2_SOURCE_ACCESS "RW" 1738 // ============================================================================= 1739 // Register : POWMAN_PWRUP3 1740 // Description : 4 GPIO powerup events can be configured to wake the chip up 1741 // from a low power state. 1742 // The pwrups are level/edge sensitive and can be set to trigger 1743 // on a high/rising or low/falling event 1744 // The number of gpios available depends on the package option. An 1745 // invalid selection will be ignored 1746 // source = 0 selects gpio0 1747 // . 1748 // . 1749 // source = 47 selects gpio47 1750 // source = 48 selects qspi_ss 1751 // source = 49 selects qspi_sd0 1752 // source = 50 selects qspi_sd1 1753 // source = 51 selects qspi_sd2 1754 // source = 52 selects qspi_sd3 1755 // source = 53 selects qspi_sclk 1756 // level = 0 triggers the pwrup when the source is low 1757 // level = 1 triggers the pwrup when the source is high 1758 #define POWMAN_PWRUP3_OFFSET _u(0x00000098) 1759 #define POWMAN_PWRUP3_BITS _u(0x000007ff) 1760 #define POWMAN_PWRUP3_RESET _u(0x0000003f) 1761 // ----------------------------------------------------------------------------- 1762 // Field : POWMAN_PWRUP3_RAW_STATUS 1763 // Description : Value of selected gpio pin (only if enable == 1) 1764 #define POWMAN_PWRUP3_RAW_STATUS_RESET _u(0x0) 1765 #define POWMAN_PWRUP3_RAW_STATUS_BITS _u(0x00000400) 1766 #define POWMAN_PWRUP3_RAW_STATUS_MSB _u(10) 1767 #define POWMAN_PWRUP3_RAW_STATUS_LSB _u(10) 1768 #define POWMAN_PWRUP3_RAW_STATUS_ACCESS "RO" 1769 // ----------------------------------------------------------------------------- 1770 // Field : POWMAN_PWRUP3_STATUS 1771 // Description : Status of gpio wakeup. Write to 1 to clear a latched edge 1772 // detect. 1773 #define POWMAN_PWRUP3_STATUS_RESET _u(0x0) 1774 #define POWMAN_PWRUP3_STATUS_BITS _u(0x00000200) 1775 #define POWMAN_PWRUP3_STATUS_MSB _u(9) 1776 #define POWMAN_PWRUP3_STATUS_LSB _u(9) 1777 #define POWMAN_PWRUP3_STATUS_ACCESS "WC" 1778 // ----------------------------------------------------------------------------- 1779 // Field : POWMAN_PWRUP3_MODE 1780 // Description : Edge or level detect. Edge will detect a 0 to 1 transition (or 1781 // 1 to 0 transition). Level will detect a 1 or 0. Both types of 1782 // event get latched into the current_pwrup_req register. 1783 // 0x0 -> level 1784 // 0x1 -> edge 1785 #define POWMAN_PWRUP3_MODE_RESET _u(0x0) 1786 #define POWMAN_PWRUP3_MODE_BITS _u(0x00000100) 1787 #define POWMAN_PWRUP3_MODE_MSB _u(8) 1788 #define POWMAN_PWRUP3_MODE_LSB _u(8) 1789 #define POWMAN_PWRUP3_MODE_ACCESS "RW" 1790 #define POWMAN_PWRUP3_MODE_VALUE_LEVEL _u(0x0) 1791 #define POWMAN_PWRUP3_MODE_VALUE_EDGE _u(0x1) 1792 // ----------------------------------------------------------------------------- 1793 // Field : POWMAN_PWRUP3_DIRECTION 1794 // 0x0 -> low_falling 1795 // 0x1 -> high_rising 1796 #define POWMAN_PWRUP3_DIRECTION_RESET _u(0x0) 1797 #define POWMAN_PWRUP3_DIRECTION_BITS _u(0x00000080) 1798 #define POWMAN_PWRUP3_DIRECTION_MSB _u(7) 1799 #define POWMAN_PWRUP3_DIRECTION_LSB _u(7) 1800 #define POWMAN_PWRUP3_DIRECTION_ACCESS "RW" 1801 #define POWMAN_PWRUP3_DIRECTION_VALUE_LOW_FALLING _u(0x0) 1802 #define POWMAN_PWRUP3_DIRECTION_VALUE_HIGH_RISING _u(0x1) 1803 // ----------------------------------------------------------------------------- 1804 // Field : POWMAN_PWRUP3_ENABLE 1805 // Description : Set to 1 to enable the wakeup source. Set to 0 to disable the 1806 // wakeup source and clear a pending wakeup event. 1807 // If using edge detect a latched edge needs to be cleared by 1808 // writing 1 to the status register also. 1809 #define POWMAN_PWRUP3_ENABLE_RESET _u(0x0) 1810 #define POWMAN_PWRUP3_ENABLE_BITS _u(0x00000040) 1811 #define POWMAN_PWRUP3_ENABLE_MSB _u(6) 1812 #define POWMAN_PWRUP3_ENABLE_LSB _u(6) 1813 #define POWMAN_PWRUP3_ENABLE_ACCESS "RW" 1814 // ----------------------------------------------------------------------------- 1815 // Field : POWMAN_PWRUP3_SOURCE 1816 #define POWMAN_PWRUP3_SOURCE_RESET _u(0x3f) 1817 #define POWMAN_PWRUP3_SOURCE_BITS _u(0x0000003f) 1818 #define POWMAN_PWRUP3_SOURCE_MSB _u(5) 1819 #define POWMAN_PWRUP3_SOURCE_LSB _u(0) 1820 #define POWMAN_PWRUP3_SOURCE_ACCESS "RW" 1821 // ============================================================================= 1822 // Register : POWMAN_CURRENT_PWRUP_REQ 1823 // Description : Indicates current powerup request state 1824 // pwrup events can be cleared by removing the enable from the 1825 // pwrup register. The alarm pwrup req can be cleared by clearing 1826 // timer.alarm_enab 1827 // 0 = chip reset, for the source of the last reset see 1828 // POWMAN_CHIP_RESET 1829 // 1 = pwrup0 1830 // 2 = pwrup1 1831 // 3 = pwrup2 1832 // 4 = pwrup3 1833 // 5 = coresight_pwrup 1834 // 6 = alarm_pwrup 1835 #define POWMAN_CURRENT_PWRUP_REQ_OFFSET _u(0x0000009c) 1836 #define POWMAN_CURRENT_PWRUP_REQ_BITS _u(0x0000007f) 1837 #define POWMAN_CURRENT_PWRUP_REQ_RESET _u(0x00000000) 1838 #define POWMAN_CURRENT_PWRUP_REQ_MSB _u(6) 1839 #define POWMAN_CURRENT_PWRUP_REQ_LSB _u(0) 1840 #define POWMAN_CURRENT_PWRUP_REQ_ACCESS "RO" 1841 // ============================================================================= 1842 // Register : POWMAN_LAST_SWCORE_PWRUP 1843 // Description : Indicates which pwrup source triggered the last switched-core 1844 // power up 1845 // 0 = chip reset, for the source of the last reset see 1846 // POWMAN_CHIP_RESET 1847 // 1 = pwrup0 1848 // 2 = pwrup1 1849 // 3 = pwrup2 1850 // 4 = pwrup3 1851 // 5 = coresight_pwrup 1852 // 6 = alarm_pwrup 1853 #define POWMAN_LAST_SWCORE_PWRUP_OFFSET _u(0x000000a0) 1854 #define POWMAN_LAST_SWCORE_PWRUP_BITS _u(0x0000007f) 1855 #define POWMAN_LAST_SWCORE_PWRUP_RESET _u(0x00000000) 1856 #define POWMAN_LAST_SWCORE_PWRUP_MSB _u(6) 1857 #define POWMAN_LAST_SWCORE_PWRUP_LSB _u(0) 1858 #define POWMAN_LAST_SWCORE_PWRUP_ACCESS "RO" 1859 // ============================================================================= 1860 // Register : POWMAN_DBG_PWRCFG 1861 #define POWMAN_DBG_PWRCFG_OFFSET _u(0x000000a4) 1862 #define POWMAN_DBG_PWRCFG_BITS _u(0x00000001) 1863 #define POWMAN_DBG_PWRCFG_RESET _u(0x00000000) 1864 // ----------------------------------------------------------------------------- 1865 // Field : POWMAN_DBG_PWRCFG_IGNORE 1866 // Description : Ignore pwrup req from debugger. If pwrup req is asserted then 1867 // this will prevent power down and set powerdown blocked. Set 1868 // ignore to stop paying attention to pwrup_req 1869 #define POWMAN_DBG_PWRCFG_IGNORE_RESET _u(0x0) 1870 #define POWMAN_DBG_PWRCFG_IGNORE_BITS _u(0x00000001) 1871 #define POWMAN_DBG_PWRCFG_IGNORE_MSB _u(0) 1872 #define POWMAN_DBG_PWRCFG_IGNORE_LSB _u(0) 1873 #define POWMAN_DBG_PWRCFG_IGNORE_ACCESS "RW" 1874 // ============================================================================= 1875 // Register : POWMAN_BOOTDIS 1876 // Description : Tell the bootrom to ignore the BOOT0..3 registers following the 1877 // next RSM reset (e.g. the next core power down/up). 1878 // 1879 // If an early boot stage has soft-locked some OTP pages in order 1880 // to protect their contents from later stages, there is a risk 1881 // that Secure code running at a later stage can unlock the pages 1882 // by powering the core up and down. 1883 // 1884 // This register can be used to ensure that the bootloader runs as 1885 // normal on the next power up, preventing Secure code at a later 1886 // stage from accessing OTP in its unlocked state. 1887 // 1888 // Should be used in conjunction with the OTP BOOTDIS register. 1889 #define POWMAN_BOOTDIS_OFFSET _u(0x000000a8) 1890 #define POWMAN_BOOTDIS_BITS _u(0x00000003) 1891 #define POWMAN_BOOTDIS_RESET _u(0x00000000) 1892 // ----------------------------------------------------------------------------- 1893 // Field : POWMAN_BOOTDIS_NEXT 1894 // Description : This flag always ORs writes into its current contents. It can 1895 // be set but not cleared by software. 1896 // 1897 // The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the 1898 // core is powered down. Simultaneously, the BOOTDIS_NEXT bit is 1899 // cleared. Setting this bit means that the BOOT0..3 registers 1900 // will be ignored following the next reset of the RSM by powman. 1901 // 1902 // This flag should be set by an early boot stage that has soft- 1903 // locked OTP pages, to prevent later stages from unlocking it by 1904 // power cycling. 1905 #define POWMAN_BOOTDIS_NEXT_RESET _u(0x0) 1906 #define POWMAN_BOOTDIS_NEXT_BITS _u(0x00000002) 1907 #define POWMAN_BOOTDIS_NEXT_MSB _u(1) 1908 #define POWMAN_BOOTDIS_NEXT_LSB _u(1) 1909 #define POWMAN_BOOTDIS_NEXT_ACCESS "RW" 1910 // ----------------------------------------------------------------------------- 1911 // Field : POWMAN_BOOTDIS_NOW 1912 // Description : When powman resets the RSM, the current value of BOOTDIS_NEXT 1913 // is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. 1914 // 1915 // The bootrom checks this flag before reading the BOOT0..3 1916 // registers. If it is set, the bootrom clears it, and ignores the 1917 // BOOT registers. This prevents Secure software from diverting 1918 // the boot path before a bootloader has had the chance to soft 1919 // lock OTP pages containing sensitive data. 1920 #define POWMAN_BOOTDIS_NOW_RESET _u(0x0) 1921 #define POWMAN_BOOTDIS_NOW_BITS _u(0x00000001) 1922 #define POWMAN_BOOTDIS_NOW_MSB _u(0) 1923 #define POWMAN_BOOTDIS_NOW_LSB _u(0) 1924 #define POWMAN_BOOTDIS_NOW_ACCESS "WC" 1925 // ============================================================================= 1926 // Register : POWMAN_DBGCONFIG 1927 #define POWMAN_DBGCONFIG_OFFSET _u(0x000000ac) 1928 #define POWMAN_DBGCONFIG_BITS _u(0x0000000f) 1929 #define POWMAN_DBGCONFIG_RESET _u(0x00000000) 1930 // ----------------------------------------------------------------------------- 1931 // Field : POWMAN_DBGCONFIG_DP_INSTID 1932 // Description : Configure DP instance ID for SWD multidrop selection. 1933 // Recommend that this is NOT changed until you require debug 1934 // access in multi-chip environment 1935 #define POWMAN_DBGCONFIG_DP_INSTID_RESET _u(0x0) 1936 #define POWMAN_DBGCONFIG_DP_INSTID_BITS _u(0x0000000f) 1937 #define POWMAN_DBGCONFIG_DP_INSTID_MSB _u(3) 1938 #define POWMAN_DBGCONFIG_DP_INSTID_LSB _u(0) 1939 #define POWMAN_DBGCONFIG_DP_INSTID_ACCESS "RW" 1940 // ============================================================================= 1941 // Register : POWMAN_SCRATCH0 1942 // Description : Scratch register. Information persists in low power mode 1943 #define POWMAN_SCRATCH0_OFFSET _u(0x000000b0) 1944 #define POWMAN_SCRATCH0_BITS _u(0xffffffff) 1945 #define POWMAN_SCRATCH0_RESET _u(0x00000000) 1946 #define POWMAN_SCRATCH0_MSB _u(31) 1947 #define POWMAN_SCRATCH0_LSB _u(0) 1948 #define POWMAN_SCRATCH0_ACCESS "RW" 1949 // ============================================================================= 1950 // Register : POWMAN_SCRATCH1 1951 // Description : Scratch register. Information persists in low power mode 1952 #define POWMAN_SCRATCH1_OFFSET _u(0x000000b4) 1953 #define POWMAN_SCRATCH1_BITS _u(0xffffffff) 1954 #define POWMAN_SCRATCH1_RESET _u(0x00000000) 1955 #define POWMAN_SCRATCH1_MSB _u(31) 1956 #define POWMAN_SCRATCH1_LSB _u(0) 1957 #define POWMAN_SCRATCH1_ACCESS "RW" 1958 // ============================================================================= 1959 // Register : POWMAN_SCRATCH2 1960 // Description : Scratch register. Information persists in low power mode 1961 #define POWMAN_SCRATCH2_OFFSET _u(0x000000b8) 1962 #define POWMAN_SCRATCH2_BITS _u(0xffffffff) 1963 #define POWMAN_SCRATCH2_RESET _u(0x00000000) 1964 #define POWMAN_SCRATCH2_MSB _u(31) 1965 #define POWMAN_SCRATCH2_LSB _u(0) 1966 #define POWMAN_SCRATCH2_ACCESS "RW" 1967 // ============================================================================= 1968 // Register : POWMAN_SCRATCH3 1969 // Description : Scratch register. Information persists in low power mode 1970 #define POWMAN_SCRATCH3_OFFSET _u(0x000000bc) 1971 #define POWMAN_SCRATCH3_BITS _u(0xffffffff) 1972 #define POWMAN_SCRATCH3_RESET _u(0x00000000) 1973 #define POWMAN_SCRATCH3_MSB _u(31) 1974 #define POWMAN_SCRATCH3_LSB _u(0) 1975 #define POWMAN_SCRATCH3_ACCESS "RW" 1976 // ============================================================================= 1977 // Register : POWMAN_SCRATCH4 1978 // Description : Scratch register. Information persists in low power mode 1979 #define POWMAN_SCRATCH4_OFFSET _u(0x000000c0) 1980 #define POWMAN_SCRATCH4_BITS _u(0xffffffff) 1981 #define POWMAN_SCRATCH4_RESET _u(0x00000000) 1982 #define POWMAN_SCRATCH4_MSB _u(31) 1983 #define POWMAN_SCRATCH4_LSB _u(0) 1984 #define POWMAN_SCRATCH4_ACCESS "RW" 1985 // ============================================================================= 1986 // Register : POWMAN_SCRATCH5 1987 // Description : Scratch register. Information persists in low power mode 1988 #define POWMAN_SCRATCH5_OFFSET _u(0x000000c4) 1989 #define POWMAN_SCRATCH5_BITS _u(0xffffffff) 1990 #define POWMAN_SCRATCH5_RESET _u(0x00000000) 1991 #define POWMAN_SCRATCH5_MSB _u(31) 1992 #define POWMAN_SCRATCH5_LSB _u(0) 1993 #define POWMAN_SCRATCH5_ACCESS "RW" 1994 // ============================================================================= 1995 // Register : POWMAN_SCRATCH6 1996 // Description : Scratch register. Information persists in low power mode 1997 #define POWMAN_SCRATCH6_OFFSET _u(0x000000c8) 1998 #define POWMAN_SCRATCH6_BITS _u(0xffffffff) 1999 #define POWMAN_SCRATCH6_RESET _u(0x00000000) 2000 #define POWMAN_SCRATCH6_MSB _u(31) 2001 #define POWMAN_SCRATCH6_LSB _u(0) 2002 #define POWMAN_SCRATCH6_ACCESS "RW" 2003 // ============================================================================= 2004 // Register : POWMAN_SCRATCH7 2005 // Description : Scratch register. Information persists in low power mode 2006 #define POWMAN_SCRATCH7_OFFSET _u(0x000000cc) 2007 #define POWMAN_SCRATCH7_BITS _u(0xffffffff) 2008 #define POWMAN_SCRATCH7_RESET _u(0x00000000) 2009 #define POWMAN_SCRATCH7_MSB _u(31) 2010 #define POWMAN_SCRATCH7_LSB _u(0) 2011 #define POWMAN_SCRATCH7_ACCESS "RW" 2012 // ============================================================================= 2013 // Register : POWMAN_BOOT0 2014 // Description : Scratch register. Information persists in low power mode 2015 #define POWMAN_BOOT0_OFFSET _u(0x000000d0) 2016 #define POWMAN_BOOT0_BITS _u(0xffffffff) 2017 #define POWMAN_BOOT0_RESET _u(0x00000000) 2018 #define POWMAN_BOOT0_MSB _u(31) 2019 #define POWMAN_BOOT0_LSB _u(0) 2020 #define POWMAN_BOOT0_ACCESS "RW" 2021 // ============================================================================= 2022 // Register : POWMAN_BOOT1 2023 // Description : Scratch register. Information persists in low power mode 2024 #define POWMAN_BOOT1_OFFSET _u(0x000000d4) 2025 #define POWMAN_BOOT1_BITS _u(0xffffffff) 2026 #define POWMAN_BOOT1_RESET _u(0x00000000) 2027 #define POWMAN_BOOT1_MSB _u(31) 2028 #define POWMAN_BOOT1_LSB _u(0) 2029 #define POWMAN_BOOT1_ACCESS "RW" 2030 // ============================================================================= 2031 // Register : POWMAN_BOOT2 2032 // Description : Scratch register. Information persists in low power mode 2033 #define POWMAN_BOOT2_OFFSET _u(0x000000d8) 2034 #define POWMAN_BOOT2_BITS _u(0xffffffff) 2035 #define POWMAN_BOOT2_RESET _u(0x00000000) 2036 #define POWMAN_BOOT2_MSB _u(31) 2037 #define POWMAN_BOOT2_LSB _u(0) 2038 #define POWMAN_BOOT2_ACCESS "RW" 2039 // ============================================================================= 2040 // Register : POWMAN_BOOT3 2041 // Description : Scratch register. Information persists in low power mode 2042 #define POWMAN_BOOT3_OFFSET _u(0x000000dc) 2043 #define POWMAN_BOOT3_BITS _u(0xffffffff) 2044 #define POWMAN_BOOT3_RESET _u(0x00000000) 2045 #define POWMAN_BOOT3_MSB _u(31) 2046 #define POWMAN_BOOT3_LSB _u(0) 2047 #define POWMAN_BOOT3_ACCESS "RW" 2048 // ============================================================================= 2049 // Register : POWMAN_INTR 2050 // Description : Raw Interrupts 2051 #define POWMAN_INTR_OFFSET _u(0x000000e0) 2052 #define POWMAN_INTR_BITS _u(0x0000000f) 2053 #define POWMAN_INTR_RESET _u(0x00000000) 2054 // ----------------------------------------------------------------------------- 2055 // Field : POWMAN_INTR_PWRUP_WHILE_WAITING 2056 // Description : Source is state.pwrup_while_waiting 2057 #define POWMAN_INTR_PWRUP_WHILE_WAITING_RESET _u(0x0) 2058 #define POWMAN_INTR_PWRUP_WHILE_WAITING_BITS _u(0x00000008) 2059 #define POWMAN_INTR_PWRUP_WHILE_WAITING_MSB _u(3) 2060 #define POWMAN_INTR_PWRUP_WHILE_WAITING_LSB _u(3) 2061 #define POWMAN_INTR_PWRUP_WHILE_WAITING_ACCESS "RO" 2062 // ----------------------------------------------------------------------------- 2063 // Field : POWMAN_INTR_STATE_REQ_IGNORED 2064 // Description : Source is state.req_ignored 2065 #define POWMAN_INTR_STATE_REQ_IGNORED_RESET _u(0x0) 2066 #define POWMAN_INTR_STATE_REQ_IGNORED_BITS _u(0x00000004) 2067 #define POWMAN_INTR_STATE_REQ_IGNORED_MSB _u(2) 2068 #define POWMAN_INTR_STATE_REQ_IGNORED_LSB _u(2) 2069 #define POWMAN_INTR_STATE_REQ_IGNORED_ACCESS "RO" 2070 // ----------------------------------------------------------------------------- 2071 // Field : POWMAN_INTR_TIMER 2072 #define POWMAN_INTR_TIMER_RESET _u(0x0) 2073 #define POWMAN_INTR_TIMER_BITS _u(0x00000002) 2074 #define POWMAN_INTR_TIMER_MSB _u(1) 2075 #define POWMAN_INTR_TIMER_LSB _u(1) 2076 #define POWMAN_INTR_TIMER_ACCESS "RO" 2077 // ----------------------------------------------------------------------------- 2078 // Field : POWMAN_INTR_VREG_OUTPUT_LOW 2079 #define POWMAN_INTR_VREG_OUTPUT_LOW_RESET _u(0x0) 2080 #define POWMAN_INTR_VREG_OUTPUT_LOW_BITS _u(0x00000001) 2081 #define POWMAN_INTR_VREG_OUTPUT_LOW_MSB _u(0) 2082 #define POWMAN_INTR_VREG_OUTPUT_LOW_LSB _u(0) 2083 #define POWMAN_INTR_VREG_OUTPUT_LOW_ACCESS "WC" 2084 // ============================================================================= 2085 // Register : POWMAN_INTE 2086 // Description : Interrupt Enable 2087 #define POWMAN_INTE_OFFSET _u(0x000000e4) 2088 #define POWMAN_INTE_BITS _u(0x0000000f) 2089 #define POWMAN_INTE_RESET _u(0x00000000) 2090 // ----------------------------------------------------------------------------- 2091 // Field : POWMAN_INTE_PWRUP_WHILE_WAITING 2092 // Description : Source is state.pwrup_while_waiting 2093 #define POWMAN_INTE_PWRUP_WHILE_WAITING_RESET _u(0x0) 2094 #define POWMAN_INTE_PWRUP_WHILE_WAITING_BITS _u(0x00000008) 2095 #define POWMAN_INTE_PWRUP_WHILE_WAITING_MSB _u(3) 2096 #define POWMAN_INTE_PWRUP_WHILE_WAITING_LSB _u(3) 2097 #define POWMAN_INTE_PWRUP_WHILE_WAITING_ACCESS "RW" 2098 // ----------------------------------------------------------------------------- 2099 // Field : POWMAN_INTE_STATE_REQ_IGNORED 2100 // Description : Source is state.req_ignored 2101 #define POWMAN_INTE_STATE_REQ_IGNORED_RESET _u(0x0) 2102 #define POWMAN_INTE_STATE_REQ_IGNORED_BITS _u(0x00000004) 2103 #define POWMAN_INTE_STATE_REQ_IGNORED_MSB _u(2) 2104 #define POWMAN_INTE_STATE_REQ_IGNORED_LSB _u(2) 2105 #define POWMAN_INTE_STATE_REQ_IGNORED_ACCESS "RW" 2106 // ----------------------------------------------------------------------------- 2107 // Field : POWMAN_INTE_TIMER 2108 #define POWMAN_INTE_TIMER_RESET _u(0x0) 2109 #define POWMAN_INTE_TIMER_BITS _u(0x00000002) 2110 #define POWMAN_INTE_TIMER_MSB _u(1) 2111 #define POWMAN_INTE_TIMER_LSB _u(1) 2112 #define POWMAN_INTE_TIMER_ACCESS "RW" 2113 // ----------------------------------------------------------------------------- 2114 // Field : POWMAN_INTE_VREG_OUTPUT_LOW 2115 #define POWMAN_INTE_VREG_OUTPUT_LOW_RESET _u(0x0) 2116 #define POWMAN_INTE_VREG_OUTPUT_LOW_BITS _u(0x00000001) 2117 #define POWMAN_INTE_VREG_OUTPUT_LOW_MSB _u(0) 2118 #define POWMAN_INTE_VREG_OUTPUT_LOW_LSB _u(0) 2119 #define POWMAN_INTE_VREG_OUTPUT_LOW_ACCESS "RW" 2120 // ============================================================================= 2121 // Register : POWMAN_INTF 2122 // Description : Interrupt Force 2123 #define POWMAN_INTF_OFFSET _u(0x000000e8) 2124 #define POWMAN_INTF_BITS _u(0x0000000f) 2125 #define POWMAN_INTF_RESET _u(0x00000000) 2126 // ----------------------------------------------------------------------------- 2127 // Field : POWMAN_INTF_PWRUP_WHILE_WAITING 2128 // Description : Source is state.pwrup_while_waiting 2129 #define POWMAN_INTF_PWRUP_WHILE_WAITING_RESET _u(0x0) 2130 #define POWMAN_INTF_PWRUP_WHILE_WAITING_BITS _u(0x00000008) 2131 #define POWMAN_INTF_PWRUP_WHILE_WAITING_MSB _u(3) 2132 #define POWMAN_INTF_PWRUP_WHILE_WAITING_LSB _u(3) 2133 #define POWMAN_INTF_PWRUP_WHILE_WAITING_ACCESS "RW" 2134 // ----------------------------------------------------------------------------- 2135 // Field : POWMAN_INTF_STATE_REQ_IGNORED 2136 // Description : Source is state.req_ignored 2137 #define POWMAN_INTF_STATE_REQ_IGNORED_RESET _u(0x0) 2138 #define POWMAN_INTF_STATE_REQ_IGNORED_BITS _u(0x00000004) 2139 #define POWMAN_INTF_STATE_REQ_IGNORED_MSB _u(2) 2140 #define POWMAN_INTF_STATE_REQ_IGNORED_LSB _u(2) 2141 #define POWMAN_INTF_STATE_REQ_IGNORED_ACCESS "RW" 2142 // ----------------------------------------------------------------------------- 2143 // Field : POWMAN_INTF_TIMER 2144 #define POWMAN_INTF_TIMER_RESET _u(0x0) 2145 #define POWMAN_INTF_TIMER_BITS _u(0x00000002) 2146 #define POWMAN_INTF_TIMER_MSB _u(1) 2147 #define POWMAN_INTF_TIMER_LSB _u(1) 2148 #define POWMAN_INTF_TIMER_ACCESS "RW" 2149 // ----------------------------------------------------------------------------- 2150 // Field : POWMAN_INTF_VREG_OUTPUT_LOW 2151 #define POWMAN_INTF_VREG_OUTPUT_LOW_RESET _u(0x0) 2152 #define POWMAN_INTF_VREG_OUTPUT_LOW_BITS _u(0x00000001) 2153 #define POWMAN_INTF_VREG_OUTPUT_LOW_MSB _u(0) 2154 #define POWMAN_INTF_VREG_OUTPUT_LOW_LSB _u(0) 2155 #define POWMAN_INTF_VREG_OUTPUT_LOW_ACCESS "RW" 2156 // ============================================================================= 2157 // Register : POWMAN_INTS 2158 // Description : Interrupt status after masking & forcing 2159 #define POWMAN_INTS_OFFSET _u(0x000000ec) 2160 #define POWMAN_INTS_BITS _u(0x0000000f) 2161 #define POWMAN_INTS_RESET _u(0x00000000) 2162 // ----------------------------------------------------------------------------- 2163 // Field : POWMAN_INTS_PWRUP_WHILE_WAITING 2164 // Description : Source is state.pwrup_while_waiting 2165 #define POWMAN_INTS_PWRUP_WHILE_WAITING_RESET _u(0x0) 2166 #define POWMAN_INTS_PWRUP_WHILE_WAITING_BITS _u(0x00000008) 2167 #define POWMAN_INTS_PWRUP_WHILE_WAITING_MSB _u(3) 2168 #define POWMAN_INTS_PWRUP_WHILE_WAITING_LSB _u(3) 2169 #define POWMAN_INTS_PWRUP_WHILE_WAITING_ACCESS "RO" 2170 // ----------------------------------------------------------------------------- 2171 // Field : POWMAN_INTS_STATE_REQ_IGNORED 2172 // Description : Source is state.req_ignored 2173 #define POWMAN_INTS_STATE_REQ_IGNORED_RESET _u(0x0) 2174 #define POWMAN_INTS_STATE_REQ_IGNORED_BITS _u(0x00000004) 2175 #define POWMAN_INTS_STATE_REQ_IGNORED_MSB _u(2) 2176 #define POWMAN_INTS_STATE_REQ_IGNORED_LSB _u(2) 2177 #define POWMAN_INTS_STATE_REQ_IGNORED_ACCESS "RO" 2178 // ----------------------------------------------------------------------------- 2179 // Field : POWMAN_INTS_TIMER 2180 #define POWMAN_INTS_TIMER_RESET _u(0x0) 2181 #define POWMAN_INTS_TIMER_BITS _u(0x00000002) 2182 #define POWMAN_INTS_TIMER_MSB _u(1) 2183 #define POWMAN_INTS_TIMER_LSB _u(1) 2184 #define POWMAN_INTS_TIMER_ACCESS "RO" 2185 // ----------------------------------------------------------------------------- 2186 // Field : POWMAN_INTS_VREG_OUTPUT_LOW 2187 #define POWMAN_INTS_VREG_OUTPUT_LOW_RESET _u(0x0) 2188 #define POWMAN_INTS_VREG_OUTPUT_LOW_BITS _u(0x00000001) 2189 #define POWMAN_INTS_VREG_OUTPUT_LOW_MSB _u(0) 2190 #define POWMAN_INTS_VREG_OUTPUT_LOW_LSB _u(0) 2191 #define POWMAN_INTS_VREG_OUTPUT_LOW_ACCESS "RO" 2192 // ============================================================================= 2193 #endif // _HARDWARE_REGS_POWMAN_H 2194 2195
