1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef POWER_IP_CFG_DEFINES_H 8 #define POWER_IP_CFG_DEFINES_H 9 10 /** 11 * @file Power_Ip_Cfg_Defines.h 12 * @version 3.0.0 13 * 14 * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. 15 * @details Code template for Post-Build(PB) configuration file generation. 16 * 17 * @addtogroup POWER_DRIVER_CONFIGURATION Power Ip Driver 18 * @{ 19 */ 20 21 #ifdef __cplusplus 22 extern "C"{ 23 #endif 24 25 26 /*================================================================================================== 27 INCLUDE FILES 28 1) system and project includes 29 2) needed interfaces from external units 30 3) internal and external interfaces from this unit 31 ==================================================================================================*/ 32 #include "StandardTypes.h" 33 #include "S32K344_MC_ME.h" 34 #include "S32K344_MC_RGM.h" 35 #include "S32K344_PMC.h" 36 #include "S32K344_DCM_GPR.h" 37 #include "S32K344_FLASH.h" 38 #include "S32K344_SCB.h" 39 /*================================================================================================== 40 SOURCE FILE VERSION INFORMATION 41 ==================================================================================================*/ 42 #define POWER_IP_CFG_DEFINES_VENDOR_ID 43 43 #define POWER_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 44 #define POWER_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 45 #define POWER_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 46 #define POWER_IP_CFG_DEFINES_SW_MAJOR_VERSION 3 47 #define POWER_IP_CFG_DEFINES_SW_MINOR_VERSION 0 48 #define POWER_IP_CFG_DEFINES_SW_PATCH_VERSION 0 49 50 /*================================================================================================== 51 FILE VERSION CHECKS 52 ==================================================================================================*/ 53 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 54 /* Check if Power_Ip_Cfg_Defines.h file and StandardTypes.h file are of the same Autosar version */ 55 #if ((POWER_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ 56 (POWER_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION)) 57 #error "AutoSar Version Numbers of Power_Ip_Cfg_Defines.h and StandardTypes.h are different" 58 #endif 59 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */ 60 61 /*================================================================================================== 62 DEFINES AND MACROS 63 ==================================================================================================*/ 64 65 /** 66 * @brief Derivative used. 67 */ 68 #define POWER_IP_DERIVATIVE_005 69 70 71 #define PMC_CONFIG_RWBITS_MASK ( \ 72 ((uint32)PMC_CONFIG_LMEN_MASK) |\ 73 ((uint32)PMC_CONFIG_LMBCTLEN_MASK) |\ 74 ((uint32)PMC_CONFIG_FASTREC_MASK) |\ 75 ((uint32)PMC_CONFIG_LPM25EN_MASK) |\ 76 ((uint32)PMC_CONFIG_LVRBLPEN_MASK) |\ 77 ((uint32)PMC_CONFIG_HVDIE_MASK) |\ 78 ((uint32)PMC_CONFIG_LVDIE_MASK) |\ 79 ((uint32)PMC_CONFIG_LMAUTOEN_MASK) ) 80 81 82 /** 83 * @brief If this parameter is set to TRUE, the Reset Generation Module (RGM) initialization has to be disabled from the MCU driver. 84 */ 85 86 #define POWER_IP_DISABLE_RGM_INIT (STD_OFF) 87 88 /** 89 * @brief If this parameter is set to TRUE, the Power Management Controller (PMC) initialization has to be disabled from the MCU driver. 90 */ 91 #define POWER_IP_DISABLE_PMC_INIT (STD_OFF) 92 93 /** 94 * @brief If this parameter is set to TRUE, the Switched Mode Power Supply (SMPS) initialization has to be disabled from the MCU driver. 95 */ 96 #define POWER_IP_ENABLE_SMPS_INIT (STD_OFF) 97 98 /** 99 * @brief Support for Low Power mode. 100 */ 101 #define POWER_IP_ENTER_LOW_POWER_MODE (STD_OFF) 102 103 /** 104 * @brief 105 */ 106 #define POWER_IP_PERFORM_RESET_API (STD_ON) 107 108 /** 109 * @brief Configure PRTNm_COREn_ADDR registers 110 */ 111 #define POWER_IP_CONFIGURE_CADDRN (STD_OFF) 112 113 /** 114 * @brief Support for Functional Reset Disable (FERD regiter present). 115 */ 116 #define POWER_IP_FUNCTIONAL_RESET_DISABLE_SUPPORT (STD_ON) 117 118 /** 119 * @brief Max number of MC_ME partitions. 120 */ 121 #define POWER_IP_MAX_NUMBER_OF_PARTITIONS ((uint8)3U) 122 123 124 /** 125 * @brief Support for lockstep configuration (PTRNx_CORE_LOCKSTEP) registers. 126 */ 127 #define POWER_IP_LOCKSTEP_CTRL_SUPPORT (STD_OFF) 128 129 /** 130 * @brief ISR Mcu_ResetAlternate_ISR is/is not available (STD_ON/STD_OFF) 131 */ 132 #define POWER_IP_RESET_ALTERNATE_ISR_USED (STD_OFF) 133 134 /** 135 * @brief 136 */ 137 #define POWER_IP_HAS_OUTPUT_SAFE_STATE (STD_OFF) 138 139 /** 140 * @brief 141 */ 142 #define POWER_IP_RESET_DURING_STANDBY_SUPPORTED (STD_ON) 143 144 145 #define POWER_IP_RESET_DOMAINS_SUPPORTED (STD_OFF) 146 147 /** 148 * @brief PMC_AE Configuration Register (CONFIG) and PMC_AE Monitor Register (MONITOR). 149 */ 150 #define POWER_IP_PMC_AE_SUPPORT (STD_OFF) 151 152 /** 153 * @brief AEC Configuration Register (RSTGEN_CFG). 154 */ 155 #define POWER_IP_AEC_SUPPORT (STD_OFF) 156 157 /** 158 * @brief Enable the usage of Non-Autosar API Power_Ip_PmcAeConfig(). 159 */ 160 #define POWER_IP_PMCAECONFIG_API (STD_OFF) 161 162 /** 163 * @brief Enable the usage of Non-Autosar API Power_Ip_AecResetConfig(). 164 */ 165 #define POWER_IP_AECRESETCONFIG_API (STD_OFF) 166 167 /** 168 * @brief ISR Mcu_PMC_UnderOverVoltage_ISR is/is not available (STD_ON/STD_OFF) 169 */ 170 #define POWER_IP_VOLTAGE_ERROR_ISR_USED (STD_OFF) 171 172 /** 173 * @brief Create defines with the values assigned to Mcu Reset Reason configurations. 174 * These values can be retrieved from Mcu_GetResetReason Api. 175 */ 176 177 #define McuConf_McuResetReasonConf_MCU_POWER_ON_RESET ((uint8)0U) 178 179 #define McuConf_McuResetReasonConf_MCU_FCCU_FTR_RESET ((uint8)1U) 180 181 #define McuConf_McuResetReasonConf_MCU_STCU_URF_RESET ((uint8)2U) 182 183 #define McuConf_McuResetReasonConf_MCU_MC_RGM_FRE_RESET ((uint8)3U) 184 185 #define McuConf_McuResetReasonConf_MCU_FXOSC_FAIL_RESET ((uint8)4U) 186 187 #define McuConf_McuResetReasonConf_MCU_PLL_LOL_RESET ((uint8)5U) 188 189 #define McuConf_McuResetReasonConf_MCU_CORE_CLK_FAIL_RESET ((uint8)6U) 190 191 #define McuConf_McuResetReasonConf_MCU_AIPS_PLAT_CLK_FAIL_RESET ((uint8)7U) 192 193 #define McuConf_McuResetReasonConf_MCU_HSE_CLK_FAIL_RESET ((uint8)8U) 194 195 #define McuConf_McuResetReasonConf_MCU_SYS_DIV_FAIL_RESET ((uint8)9U) 196 197 #define McuConf_McuResetReasonConf_MCU_CM7_CORE_CLK_FAIL_RESET ((uint8)10U) 198 199 #define McuConf_McuResetReasonConf_MCU_HSE_TMPR_RST_RESET ((uint8)11U) 200 201 #define McuConf_McuResetReasonConf_MCU_HSE_SNVS_RST_RESET ((uint8)12U) 202 203 #define McuConf_McuResetReasonConf_MCU_SW_DEST_RESET ((uint8)13U) 204 205 #define McuConf_McuResetReasonConf_MCU_DEBUG_DEST_RESET ((uint8)14U) 206 207 #define McuConf_McuResetReasonConf_MCU_F_EXR_RESET ((uint8)15U) 208 209 #define McuConf_McuResetReasonConf_MCU_FCCU_RST_RESET ((uint8)16U) 210 211 #define McuConf_McuResetReasonConf_MCU_ST_DONE_RESET ((uint8)17U) 212 213 #define McuConf_McuResetReasonConf_MCU_SWT0_RST_RESET ((uint8)18U) 214 215 #define McuConf_McuResetReasonConf_MCU_SWT1_RST_RESET ((uint8)19U) 216 217 #define McuConf_McuResetReasonConf_MCU_SWT2_RST_RESET ((uint8)20U) 218 219 #define McuConf_McuResetReasonConf_MCU_JTAG_RST_RESET ((uint8)21U) 220 221 #define McuConf_McuResetReasonConf_MCU_SWT3_RST_RESET ((uint8)22U) 222 223 #define McuConf_McuResetReasonConf_MCU_PLL_AUX_RESET ((uint8)23U) 224 225 #define McuConf_McuResetReasonConf_MCU_HSE_SWT_RST_RESET ((uint8)24U) 226 227 #define McuConf_McuResetReasonConf_MCU_HSE_BOOT_RST_RESET ((uint8)25U) 228 229 #define McuConf_McuResetReasonConf_MCU_SW_FUNC_RESET ((uint8)26U) 230 231 #define McuConf_McuResetReasonConf_MCU_DEBUG_FUNC_RESET ((uint8)27U) 232 233 #define McuConf_McuResetReasonConf_MCU_WAKEUP_REASON ((uint8)28U) 234 235 #define McuConf_McuResetReasonConf_MCU_NO_RESET_REASON ((uint8)29U) 236 237 #define McuConf_McuResetReasonConf_MCU_MULTIPLE_RESET_REASON ((uint8)30U) 238 239 #define McuConf_McuResetReasonConf_MCU_RESET_UNDEFINED ((uint8)31U) 240 /** 241 * @brief This define controls the availability of function Mcu_SleepOnExit 242 */ 243 #define POWER_IP_SLEEPONEXIT_SUPPORT (STD_ON) 244 /** 245 * @brief Support Mc_Me COFB (COFB regiter present). 246 */ 247 #define POWER_IP_MC_ME_COFB_SUPPORT (STD_ON) 248 /***********************************************************/ 249 /* MC_ME_PRTN0_COFB1_CLKEN */ 250 /***********************************************************/ 251 #define MC_ME_PRTN0_COFB1_CLKEN_RWBITS_MASK ((uint32)( \ 252 MC_ME_PRTN0_COFB1_CLKEN_REQ32_MASK | \ 253 MC_ME_PRTN0_COFB1_CLKEN_REQ33_MASK | \ 254 MC_ME_PRTN0_COFB1_CLKEN_REQ34_MASK | \ 255 MC_ME_PRTN0_COFB1_CLKEN_REQ35_MASK | \ 256 MC_ME_PRTN0_COFB1_CLKEN_REQ36_MASK | \ 257 MC_ME_PRTN0_COFB1_CLKEN_REQ38_MASK | \ 258 MC_ME_PRTN0_COFB1_CLKEN_REQ39_MASK | \ 259 MC_ME_PRTN0_COFB1_CLKEN_REQ40_MASK | \ 260 MC_ME_PRTN0_COFB1_CLKEN_REQ41_MASK | \ 261 MC_ME_PRTN0_COFB1_CLKEN_REQ42_MASK | \ 262 MC_ME_PRTN0_COFB1_CLKEN_REQ44_MASK | \ 263 MC_ME_PRTN0_COFB1_CLKEN_REQ45_MASK | \ 264 0x00000000)) 265 #define MC_ME_PRTN0_COFB1_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN0_COFB1_CLKEN_RWBITS_MASK)) 266 /***********************************************************/ 267 /* MC_ME_PRTN1_COFB0_CLKEN */ 268 /***********************************************************/ 269 #define MC_ME_PRTN1_COFB0_CLKEN_RWBITS_MASK ((uint32)( \ 270 MC_ME_PRTN1_COFB0_CLKEN_REQ3_MASK | \ 271 MC_ME_PRTN1_COFB0_CLKEN_REQ4_MASK | \ 272 MC_ME_PRTN1_COFB0_CLKEN_REQ5_MASK | \ 273 MC_ME_PRTN1_COFB0_CLKEN_REQ6_MASK | \ 274 MC_ME_PRTN1_COFB0_CLKEN_REQ7_MASK | \ 275 MC_ME_PRTN1_COFB0_CLKEN_REQ8_MASK | \ 276 MC_ME_PRTN1_COFB0_CLKEN_REQ9_MASK | \ 277 MC_ME_PRTN1_COFB0_CLKEN_REQ10_MASK | \ 278 MC_ME_PRTN1_COFB0_CLKEN_REQ11_MASK | \ 279 MC_ME_PRTN1_COFB0_CLKEN_REQ12_MASK | \ 280 MC_ME_PRTN1_COFB0_CLKEN_REQ13_MASK | \ 281 MC_ME_PRTN1_COFB0_CLKEN_REQ14_MASK | \ 282 MC_ME_PRTN1_COFB0_CLKEN_REQ15_MASK | \ 283 MC_ME_PRTN1_COFB0_CLKEN_REQ21_MASK | \ 284 MC_ME_PRTN1_COFB0_CLKEN_REQ22_MASK | \ 285 MC_ME_PRTN1_COFB0_CLKEN_REQ23_MASK | \ 286 MC_ME_PRTN1_COFB0_CLKEN_REQ24_MASK | \ 287 MC_ME_PRTN1_COFB0_CLKEN_REQ28_MASK | \ 288 MC_ME_PRTN1_COFB0_CLKEN_REQ29_MASK | \ 289 MC_ME_PRTN1_COFB0_CLKEN_REQ31_MASK | \ 290 0x00000000)) 291 #define MC_ME_PRTN1_COFB0_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN1_COFB0_CLKEN_RWBITS_MASK)) 292 /***********************************************************/ 293 /* MC_ME_PRTN1_COFB1_CLKEN */ 294 /***********************************************************/ 295 #define MC_ME_PRTN1_COFB1_CLKEN_RWBITS_MASK ((uint32)( \ 296 MC_ME_PRTN1_COFB1_CLKEN_REQ32_MASK | \ 297 MC_ME_PRTN1_COFB1_CLKEN_REQ33_MASK | \ 298 MC_ME_PRTN1_COFB1_CLKEN_REQ34_MASK | \ 299 MC_ME_PRTN1_COFB1_CLKEN_REQ42_MASK | \ 300 MC_ME_PRTN1_COFB1_CLKEN_REQ45_MASK | \ 301 MC_ME_PRTN1_COFB1_CLKEN_REQ47_MASK | \ 302 MC_ME_PRTN1_COFB1_CLKEN_REQ49_MASK | \ 303 MC_ME_PRTN1_COFB1_CLKEN_REQ51_MASK | \ 304 MC_ME_PRTN1_COFB1_CLKEN_REQ53_MASK | \ 305 MC_ME_PRTN1_COFB1_CLKEN_REQ56_MASK | \ 306 MC_ME_PRTN1_COFB1_CLKEN_REQ63_MASK | \ 307 0x00000000)) 308 #define MC_ME_PRTN1_COFB1_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN1_COFB1_CLKEN_RWBITS_MASK)) 309 /***********************************************************/ 310 /* MC_ME_PRTN1_COFB2_CLKEN */ 311 /***********************************************************/ 312 #define MC_ME_PRTN1_COFB2_CLKEN_RWBITS_MASK ((uint32)( \ 313 MC_ME_PRTN1_COFB2_CLKEN_REQ65_MASK | \ 314 MC_ME_PRTN1_COFB2_CLKEN_REQ66_MASK | \ 315 MC_ME_PRTN1_COFB2_CLKEN_REQ67_MASK | \ 316 MC_ME_PRTN1_COFB2_CLKEN_REQ68_MASK | \ 317 MC_ME_PRTN1_COFB2_CLKEN_REQ69_MASK | \ 318 MC_ME_PRTN1_COFB2_CLKEN_REQ70_MASK | \ 319 MC_ME_PRTN1_COFB2_CLKEN_REQ73_MASK | \ 320 MC_ME_PRTN1_COFB2_CLKEN_REQ74_MASK | \ 321 MC_ME_PRTN1_COFB2_CLKEN_REQ75_MASK | \ 322 MC_ME_PRTN1_COFB2_CLKEN_REQ76_MASK | \ 323 MC_ME_PRTN1_COFB2_CLKEN_REQ77_MASK | \ 324 MC_ME_PRTN1_COFB2_CLKEN_REQ78_MASK | \ 325 MC_ME_PRTN1_COFB2_CLKEN_REQ79_MASK | \ 326 MC_ME_PRTN1_COFB2_CLKEN_REQ80_MASK | \ 327 MC_ME_PRTN1_COFB2_CLKEN_REQ81_MASK | \ 328 MC_ME_PRTN1_COFB2_CLKEN_REQ84_MASK | \ 329 MC_ME_PRTN1_COFB2_CLKEN_REQ85_MASK | \ 330 MC_ME_PRTN1_COFB2_CLKEN_REQ86_MASK | \ 331 MC_ME_PRTN1_COFB2_CLKEN_REQ87_MASK | \ 332 MC_ME_PRTN1_COFB2_CLKEN_REQ88_MASK | \ 333 MC_ME_PRTN1_COFB2_CLKEN_REQ89_MASK | \ 334 MC_ME_PRTN1_COFB2_CLKEN_REQ91_MASK | \ 335 MC_ME_PRTN1_COFB2_CLKEN_REQ92_MASK | \ 336 MC_ME_PRTN1_COFB2_CLKEN_REQ93_MASK | \ 337 MC_ME_PRTN1_COFB2_CLKEN_REQ95_MASK | \ 338 0x00000000)) 339 #define MC_ME_PRTN1_COFB2_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN1_COFB2_CLKEN_RWBITS_MASK)) 340 /***********************************************************/ 341 /* MC_ME_PRTN1_COFB3_CLKEN */ 342 /***********************************************************/ 343 #define MC_ME_PRTN1_COFB3_CLKEN_RWBITS_MASK ((uint32)( \ 344 MC_ME_PRTN1_COFB3_CLKEN_REQ96_MASK | \ 345 MC_ME_PRTN1_COFB3_CLKEN_REQ104_MASK | \ 346 0x00000000)) 347 #define MC_ME_PRTN1_COFB3_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN1_COFB3_CLKEN_RWBITS_MASK)) 348 /***********************************************************/ 349 /* MC_ME_PRTN2_COFB0_CLKEN */ 350 /***********************************************************/ 351 #define MC_ME_PRTN2_COFB0_CLKEN_RWBITS_MASK ((uint32)( \ 352 MC_ME_PRTN2_COFB0_CLKEN_REQ4_MASK | \ 353 MC_ME_PRTN2_COFB0_CLKEN_REQ5_MASK | \ 354 MC_ME_PRTN2_COFB0_CLKEN_REQ6_MASK | \ 355 MC_ME_PRTN2_COFB0_CLKEN_REQ7_MASK | \ 356 MC_ME_PRTN2_COFB0_CLKEN_REQ8_MASK | \ 357 MC_ME_PRTN2_COFB0_CLKEN_REQ9_MASK | \ 358 MC_ME_PRTN2_COFB0_CLKEN_REQ10_MASK | \ 359 MC_ME_PRTN2_COFB0_CLKEN_REQ11_MASK | \ 360 MC_ME_PRTN2_COFB0_CLKEN_REQ12_MASK | \ 361 MC_ME_PRTN2_COFB0_CLKEN_REQ13_MASK | \ 362 MC_ME_PRTN2_COFB0_CLKEN_REQ14_MASK | \ 363 MC_ME_PRTN2_COFB0_CLKEN_REQ15_MASK | \ 364 MC_ME_PRTN2_COFB0_CLKEN_REQ16_MASK | \ 365 MC_ME_PRTN2_COFB0_CLKEN_REQ17_MASK | \ 366 MC_ME_PRTN2_COFB0_CLKEN_REQ18_MASK | \ 367 MC_ME_PRTN2_COFB0_CLKEN_REQ19_MASK | \ 368 MC_ME_PRTN2_COFB0_CLKEN_REQ20_MASK | \ 369 MC_ME_PRTN2_COFB0_CLKEN_REQ21_MASK | \ 370 MC_ME_PRTN2_COFB0_CLKEN_REQ22_MASK | \ 371 MC_ME_PRTN2_COFB0_CLKEN_REQ23_MASK | \ 372 MC_ME_PRTN2_COFB0_CLKEN_REQ24_MASK | \ 373 MC_ME_PRTN2_COFB0_CLKEN_REQ29_MASK | \ 374 0x00000000)) 375 #define MC_ME_PRTN2_COFB0_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN2_COFB0_CLKEN_RWBITS_MASK)) 376 /***********************************************************/ 377 /* MC_ME_PRTN2_COFB1_CLKEN */ 378 /***********************************************************/ 379 #define MC_ME_PRTN2_COFB1_CLKEN_RWBITS_MASK ((uint32)( \ 380 MC_ME_PRTN2_COFB1_CLKEN_REQ32_MASK | \ 381 MC_ME_PRTN2_COFB1_CLKEN_REQ35_MASK | \ 382 MC_ME_PRTN2_COFB1_CLKEN_REQ36_MASK | \ 383 MC_ME_PRTN2_COFB1_CLKEN_REQ37_MASK | \ 384 MC_ME_PRTN2_COFB1_CLKEN_REQ38_MASK | \ 385 MC_ME_PRTN2_COFB1_CLKEN_REQ39_MASK | \ 386 MC_ME_PRTN2_COFB1_CLKEN_REQ40_MASK | \ 387 MC_ME_PRTN2_COFB1_CLKEN_REQ41_MASK | \ 388 MC_ME_PRTN2_COFB1_CLKEN_REQ42_MASK | \ 389 MC_ME_PRTN2_COFB1_CLKEN_REQ47_MASK | \ 390 MC_ME_PRTN2_COFB1_CLKEN_REQ48_MASK | \ 391 MC_ME_PRTN2_COFB1_CLKEN_REQ51_MASK | \ 392 MC_ME_PRTN2_COFB1_CLKEN_REQ55_MASK | \ 393 MC_ME_PRTN2_COFB1_CLKEN_REQ58_MASK | \ 394 MC_ME_PRTN2_COFB1_CLKEN_REQ62_MASK | \ 395 0x00000000)) 396 #define MC_ME_PRTN2_COFB1_CLKEN(value) ((uint32)(((uint32)(value)) & MC_ME_PRTN2_COFB1_CLKEN_RWBITS_MASK)) 397 398 /*================================================================================================== 399 ENUMS 400 ==================================================================================================*/ 401 402 403 /*================================================================================================== 404 STRUCTURES AND OTHER TYPEDEFS 405 ==================================================================================================*/ 406 407 408 409 #ifdef __cplusplus 410 } 411 #endif 412 413 /** @} */ 414 #endif /* #ifndef POWER_IP_CFG_DEFINES_H */ 415
