1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal power management enums and defines */ 9 10 #ifndef PM_DEFS_H 11 #define PM_DEFS_H 12 13 #include "pm_node.h" 14 15 /********************************************************************* 16 * Macro definitions 17 ********************************************************************/ 18 19 /* State arguments of the self suspend */ 20 #define PM_STATE_CPU_IDLE 0x0U 21 #define PM_STATE_SUSPEND_TO_RAM 0xFU 22 23 #define MAX_LATENCY (~0U) 24 #define MAX_QOS 100U 25 26 /* Processor core device IDs */ 27 #define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ 28 XPM_NODETYPE_DEV_CORE_APU, (IDX)) 29 30 #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) 31 #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) 32 33 #define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \ 34 (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \ 35 (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX)) 36 37 #define PM_GET_CALLBACK_DATA 0xa01U 38 #define PM_GET_TRUSTZONE_VERSION 0xa03U 39 #define TF_A_PM_REGISTER_SGI 0xa04U 40 41 /* PM API Versions */ 42 #define PM_API_BASE_VERSION 1U 43 #define PM_API_VERSION_2 2U 44 45 /* Loader API ids */ 46 #define PM_LOAD_PDI 0x701U 47 #define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU 48 49 /* System shutdown macros */ 50 #define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U 51 #define XPM_SHUTDOWN_TYPE_RESET 1U 52 #define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U 53 54 #define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U 55 #define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U 56 #define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U 57 58 /********************************************************************* 59 * Enum definitions 60 ********************************************************************/ 61 62 /* 63 * ioctl id 64 */ 65 enum { 66 IOCTL_GET_RPU_OPER_MODE = 0, 67 IOCTL_SET_RPU_OPER_MODE = 1, 68 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 69 IOCTL_TCM_COMB_CONFIG = 3, 70 IOCTL_SET_TAPDELAY_BYPASS = 4, 71 IOCTL_SD_DLL_RESET = 6, 72 IOCTL_SET_SD_TAPDELAY = 7, 73 /* Ioctl for clock driver */ 74 IOCTL_SET_PLL_FRAC_MODE = 8, 75 IOCTL_GET_PLL_FRAC_MODE = 9, 76 IOCTL_SET_PLL_FRAC_DATA = 10, 77 IOCTL_GET_PLL_FRAC_DATA = 11, 78 IOCTL_WRITE_GGS = 12, 79 IOCTL_READ_GGS = 13, 80 IOCTL_WRITE_PGGS = 14, 81 IOCTL_READ_PGGS = 15, 82 /* IOCTL for ULPI reset */ 83 IOCTL_ULPI_RESET = 16, 84 /* Set healthy bit value */ 85 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 86 IOCTL_AFI = 18, 87 /* Probe counter read/write */ 88 IOCTL_PROBE_COUNTER_READ = 19, 89 IOCTL_PROBE_COUNTER_WRITE = 20, 90 IOCTL_OSPI_MUX_SELECT = 21, 91 /* IOCTL for USB power request */ 92 IOCTL_USB_SET_STATE = 22, 93 /* IOCTL to get last reset reason */ 94 IOCTL_GET_LAST_RESET_REASON = 23, 95 /* AI engine NPI ISR clear */ 96 IOCTL_AIE_ISR_CLEAR = 24, 97 /* Register SGI to TF-A */ 98 IOCTL_SET_SGI = 25, 99 }; 100 101 /** 102 * enum pm_pll_param - enum represents the parameters for a phase-locked loop. 103 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL. 104 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL. 105 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL. 106 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input. 107 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode. 108 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize. 109 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting. 110 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control. 111 * @PM_PLL_PARAM_CP: PLL charge pump control. 112 * @PM_PLL_PARAM_RES: PLL loop filter resistor control. 113 * @PM_PLL_PARAM_MAX: Represents the maximum parameter value for the PLL 114 */ 115 enum pm_pll_param { 116 PM_PLL_PARAM_DIV2, 117 PM_PLL_PARAM_FBDIV, 118 PM_PLL_PARAM_DATA, 119 PM_PLL_PARAM_PRE_SRC, 120 PM_PLL_PARAM_POST_SRC, 121 PM_PLL_PARAM_LOCK_DLY, 122 PM_PLL_PARAM_LOCK_CNT, 123 PM_PLL_PARAM_LFHF, 124 PM_PLL_PARAM_CP, 125 PM_PLL_PARAM_RES, 126 PM_PLL_PARAM_MAX, 127 }; 128 129 enum pm_api_id { 130 /* Miscellaneous API functions: */ 131 PM_GET_API_VERSION = 1, /* Do not change or move */ 132 PM_SET_CONFIGURATION, 133 PM_GET_NODE_STATUS, 134 PM_GET_OP_CHARACTERISTIC, 135 PM_REGISTER_NOTIFIER, 136 /* API for suspending of PUs: */ 137 PM_REQ_SUSPEND, 138 PM_SELF_SUSPEND, 139 PM_FORCE_POWERDOWN, 140 PM_ABORT_SUSPEND, 141 PM_REQ_WAKEUP, 142 PM_SET_WAKEUP_SOURCE, 143 PM_SYSTEM_SHUTDOWN, 144 /* API for managing PM slaves: */ 145 PM_REQ_NODE, 146 PM_RELEASE_NODE, 147 PM_SET_REQUIREMENT, 148 PM_SET_MAX_LATENCY, 149 /* Direct control API functions: */ 150 PM_RESET_ASSERT, 151 PM_RESET_GET_STATUS, 152 PM_MMIO_WRITE, 153 PM_MMIO_READ, 154 PM_INIT_FINALIZE, 155 PM_FPGA_LOAD, 156 PM_FPGA_GET_STATUS, 157 PM_GET_CHIPID, 158 PM_SECURE_RSA_AES, 159 PM_SECURE_SHA, 160 PM_SECURE_RSA, 161 PM_PINCTRL_REQUEST, 162 PM_PINCTRL_RELEASE, 163 PM_PINCTRL_GET_FUNCTION, 164 PM_PINCTRL_SET_FUNCTION, 165 PM_PINCTRL_CONFIG_PARAM_GET, 166 PM_PINCTRL_CONFIG_PARAM_SET, 167 PM_IOCTL, 168 /* API to query information from firmware */ 169 PM_QUERY_DATA, 170 /* Clock control API functions */ 171 PM_CLOCK_ENABLE, 172 PM_CLOCK_DISABLE, 173 PM_CLOCK_GETSTATE, 174 PM_CLOCK_SETDIVIDER, 175 PM_CLOCK_GETDIVIDER, 176 PM_CLOCK_SETPARENT = 43, 177 PM_CLOCK_GETPARENT, 178 PM_SECURE_IMAGE, 179 /* FPGA PL Readback */ 180 PM_FPGA_READ, 181 PM_SECURE_AES, 182 /* PLL control API functions */ 183 PM_PLL_SET_PARAMETER, 184 PM_PLL_GET_PARAMETER, 185 PM_PLL_SET_MODE, 186 PM_PLL_GET_MODE, 187 /* PM Register Access API */ 188 PM_REGISTER_ACCESS, 189 PM_EFUSE_ACCESS, 190 PM_FPGA_GET_VERSION, 191 PM_FPGA_GET_FEATURE_LIST, 192 PM_FEATURE_CHECK = 63, 193 PM_API_MAX = 74 194 }; 195 196 enum pm_abort_reason { 197 ABORT_REASON_WKUP_EVENT = 100, 198 ABORT_REASON_PU_BUSY, 199 ABORT_REASON_NO_PWRDN, 200 ABORT_REASON_UNKNOWN, 201 }; 202 203 enum pm_opchar_type { 204 PM_OPCHAR_TYPE_POWER = 1, 205 PM_OPCHAR_TYPE_TEMP, 206 PM_OPCHAR_TYPE_LATENCY, 207 }; 208 209 /* 210 * Subsystem IDs 211 */ 212 typedef enum { 213 XPM_SUBSYSID_PMC, 214 XPM_SUBSYSID_PSM, 215 XPM_SUBSYSID_APU, 216 XPM_SUBSYSID_RPU0_LOCK, 217 XPM_SUBSYSID_RPU0_0, 218 XPM_SUBSYSID_RPU0_1, 219 XPM_SUBSYSID_DDR0, 220 XPM_SUBSYSID_ME, 221 XPM_SUBSYSID_PL, 222 XPM_SUBSYSID_MAX, 223 } XPm_SubsystemId; 224 225 /* TODO: move pm_ret_status from device specific location to common location */ 226 /** 227 * enum pm_ret_status - enum represents the return status codes for a PM 228 * operation. 229 * @PM_RET_SUCCESS: success. 230 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated). 231 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated). 232 * @PM_RET_ERROR_NOFEATURE: feature is not available. 233 * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication. 234 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled. 235 * @PM_RET_ERROR_INTERNAL: internal error. 236 * @PM_RET_ERROR_CONFLICT: conflict. 237 * @PM_RET_ERROR_ACCESS: access rights violation. 238 * @PM_RET_ERROR_INVALID_NODE: invalid node. 239 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node. 240 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted. 241 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU. 242 * @PM_RET_ERROR_NODE_USED: node is already in use. 243 * @PM_RET_ERROR_NO_FEATURE: indicates that the requested feature is not 244 * supported. 245 */ 246 enum pm_ret_status { 247 PM_RET_SUCCESS, 248 PM_RET_ERROR_ARGS = 1, 249 PM_RET_ERROR_NOTSUPPORTED = 4, 250 PM_RET_ERROR_NOFEATURE = 19, 251 PM_RET_ERROR_INVALID_CRC = 301, 252 PM_RET_ERROR_NOT_ENABLED = 29, 253 PM_RET_ERROR_INTERNAL = 2000, 254 PM_RET_ERROR_CONFLICT = 2001, 255 PM_RET_ERROR_ACCESS = 2002, 256 PM_RET_ERROR_INVALID_NODE = 2003, 257 PM_RET_ERROR_DOUBLE_REQ = 2004, 258 PM_RET_ERROR_ABORT_SUSPEND = 2005, 259 PM_RET_ERROR_TIMEOUT = 2006, 260 PM_RET_ERROR_NODE_USED = 2007, 261 PM_RET_ERROR_NO_FEATURE = 2008 262 }; 263 264 /* 265 * Qids 266 */ 267 enum pm_query_id { 268 XPM_QID_INVALID, 269 XPM_QID_CLOCK_GET_NAME, 270 XPM_QID_CLOCK_GET_TOPOLOGY, 271 XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, 272 XPM_QID_CLOCK_GET_MUXSOURCES, 273 XPM_QID_CLOCK_GET_ATTRIBUTES, 274 XPM_QID_PINCTRL_GET_NUM_PINS, 275 XPM_QID_PINCTRL_GET_NUM_FUNCTIONS, 276 XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, 277 XPM_QID_PINCTRL_GET_FUNCTION_NAME, 278 XPM_QID_PINCTRL_GET_FUNCTION_GROUPS, 279 XPM_QID_PINCTRL_GET_PIN_GROUPS, 280 XPM_QID_CLOCK_GET_NUM_CLOCKS, 281 XPM_QID_CLOCK_GET_MAX_DIVISOR, 282 XPM_QID_PLD_GET_PARENT, 283 }; 284 #endif /* PM_DEFS_H */ 285
