1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* ZynqMP power management enums and defines */ 8 9 #ifndef PM_DEFS_H 10 #define PM_DEFS_H 11 12 /********************************************************************* 13 * Macro definitions 14 ********************************************************************/ 15 16 /* 17 * Version number is a 32bit value, like: 18 * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR 19 */ 20 #define PM_VERSION_MAJOR 1U 21 #define PM_VERSION_MINOR 1U 22 23 #define PM_VERSION ((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR) 24 25 /** 26 * PM API versions 27 */ 28 /* Expected version of firmware APIs */ 29 #define FW_API_BASE_VERSION (1U) 30 /* Expected version of firmware API for feature check */ 31 #define FW_API_VERSION_2 (2U) 32 /* Version of APIs implemented in ATF */ 33 #define ATF_API_BASE_VERSION (1U) 34 35 /* Capabilities for RAM */ 36 #define PM_CAP_ACCESS 0x1U 37 #define PM_CAP_CONTEXT 0x2U 38 39 #define MAX_LATENCY (~0U) 40 #define MAX_QOS 100U 41 42 /* State arguments of the self suspend */ 43 #define PM_STATE_CPU_IDLE 0x0U 44 #define PM_STATE_SUSPEND_TO_RAM 0xFU 45 46 /* APU processor states */ 47 #define PM_PROC_STATE_FORCEDOFF 0U 48 #define PM_PROC_STATE_ACTIVE 1U 49 #define PM_PROC_STATE_SLEEP 2U 50 #define PM_PROC_STATE_SUSPENDING 3U 51 52 #define EM_FUNID_NUM_MASK 0xF0000U 53 54 #define PM_GET_CALLBACK_DATA 0xa01 55 #define PM_SET_SUSPEND_MODE 0xa02 56 #define PM_GET_TRUSTZONE_VERSION 0xa03 57 58 /********************************************************************* 59 * Enum definitions 60 ********************************************************************/ 61 62 enum pm_api_id { 63 /* Miscellaneous API functions: */ 64 PM_GET_API_VERSION = 1, /* Do not change or move */ 65 PM_SET_CONFIGURATION, 66 PM_GET_NODE_STATUS, 67 PM_GET_OP_CHARACTERISTIC, 68 PM_REGISTER_NOTIFIER, 69 /* API for suspending of PUs: */ 70 PM_REQ_SUSPEND, 71 PM_SELF_SUSPEND, 72 PM_FORCE_POWERDOWN, 73 PM_ABORT_SUSPEND, 74 PM_REQ_WAKEUP, 75 PM_SET_WAKEUP_SOURCE, 76 PM_SYSTEM_SHUTDOWN, 77 /* API for managing PM slaves: */ 78 PM_REQ_NODE, 79 PM_RELEASE_NODE, 80 PM_SET_REQUIREMENT, 81 PM_SET_MAX_LATENCY, 82 /* Direct control API functions: */ 83 PM_RESET_ASSERT, 84 PM_RESET_GET_STATUS, 85 PM_MMIO_WRITE, 86 PM_MMIO_READ, 87 PM_INIT_FINALIZE, 88 PM_FPGA_LOAD, 89 PM_FPGA_GET_STATUS, 90 PM_GET_CHIPID, 91 PM_SECURE_RSA_AES, 92 PM_SECURE_SHA, 93 PM_SECURE_RSA, 94 PM_PINCTRL_REQUEST, 95 PM_PINCTRL_RELEASE, 96 PM_PINCTRL_GET_FUNCTION, 97 PM_PINCTRL_SET_FUNCTION, 98 PM_PINCTRL_CONFIG_PARAM_GET, 99 PM_PINCTRL_CONFIG_PARAM_SET, 100 PM_IOCTL, 101 /* API to query information from firmware */ 102 PM_QUERY_DATA, 103 /* Clock control API functions */ 104 PM_CLOCK_ENABLE, 105 PM_CLOCK_DISABLE, 106 PM_CLOCK_GETSTATE, 107 PM_CLOCK_SETDIVIDER, 108 PM_CLOCK_GETDIVIDER, 109 PM_CLOCK_SETRATE, 110 PM_CLOCK_GETRATE, 111 PM_CLOCK_SETPARENT, 112 PM_CLOCK_GETPARENT, 113 PM_SECURE_IMAGE, 114 /* FPGA PL Readback */ 115 PM_FPGA_READ, 116 PM_SECURE_AES, 117 /* PLL control API functions */ 118 PM_PLL_SET_PARAMETER, 119 PM_PLL_GET_PARAMETER, 120 PM_PLL_SET_MODE, 121 PM_PLL_GET_MODE, 122 /* PM Register Access API */ 123 PM_REGISTER_ACCESS, 124 PM_EFUSE_ACCESS, 125 PM_FPGA_GET_VERSION, 126 PM_FPGA_GET_FEATURE_LIST, 127 PM_FEATURE_CHECK = 63, 128 PM_API_MAX 129 }; 130 131 enum pm_node_id { 132 NODE_UNKNOWN = 0, 133 NODE_APU, 134 NODE_APU_0, 135 NODE_APU_1, 136 NODE_APU_2, 137 NODE_APU_3, 138 NODE_RPU, 139 NODE_RPU_0, 140 NODE_RPU_1, 141 NODE_PLD, 142 NODE_FPD, 143 NODE_OCM_BANK_0, 144 NODE_OCM_BANK_1, 145 NODE_OCM_BANK_2, 146 NODE_OCM_BANK_3, 147 NODE_TCM_0_A, 148 NODE_TCM_0_B, 149 NODE_TCM_1_A, 150 NODE_TCM_1_B, 151 NODE_L2, 152 NODE_GPU_PP_0, 153 NODE_GPU_PP_1, 154 NODE_USB_0, 155 NODE_USB_1, 156 NODE_TTC_0, 157 NODE_TTC_1, 158 NODE_TTC_2, 159 NODE_TTC_3, 160 NODE_SATA, 161 NODE_ETH_0, 162 NODE_ETH_1, 163 NODE_ETH_2, 164 NODE_ETH_3, 165 NODE_UART_0, 166 NODE_UART_1, 167 NODE_SPI_0, 168 NODE_SPI_1, 169 NODE_I2C_0, 170 NODE_I2C_1, 171 NODE_SD_0, 172 NODE_SD_1, 173 NODE_DP, 174 NODE_GDMA, 175 NODE_ADMA, 176 NODE_NAND, 177 NODE_QSPI, 178 NODE_GPIO, 179 NODE_CAN_0, 180 NODE_CAN_1, 181 NODE_EXTERN, 182 NODE_APLL, 183 NODE_VPLL, 184 NODE_DPLL, 185 NODE_RPLL, 186 NODE_IOPLL, 187 NODE_DDR, 188 NODE_IPI_APU, 189 NODE_IPI_RPU_0, 190 NODE_GPU, 191 NODE_PCIE, 192 NODE_PCAP, 193 NODE_RTC, 194 NODE_LPD, 195 NODE_VCU, 196 NODE_IPI_RPU_1, 197 NODE_IPI_PL_0, 198 NODE_IPI_PL_1, 199 NODE_IPI_PL_2, 200 NODE_IPI_PL_3, 201 NODE_PL, 202 NODE_GEM_TSU, 203 NODE_SWDT_0, 204 NODE_SWDT_1, 205 NODE_CSU, 206 NODE_PJTAG, 207 NODE_TRACE, 208 NODE_TESTSCAN, 209 NODE_PMU, 210 NODE_MAX, 211 }; 212 213 enum pm_request_ack { 214 REQ_ACK_NO = 1, 215 REQ_ACK_BLOCKING, 216 REQ_ACK_NON_BLOCKING, 217 }; 218 219 enum pm_abort_reason { 220 ABORT_REASON_WKUP_EVENT = 100, 221 ABORT_REASON_PU_BUSY, 222 ABORT_REASON_NO_PWRDN, 223 ABORT_REASON_UNKNOWN, 224 }; 225 226 enum pm_suspend_reason { 227 SUSPEND_REASON_PU_REQ = 201, 228 SUSPEND_REASON_ALERT, 229 SUSPEND_REASON_SYS_SHUTDOWN, 230 }; 231 232 enum pm_ram_state { 233 PM_RAM_STATE_OFF = 1, 234 PM_RAM_STATE_RETENTION, 235 PM_RAM_STATE_ON, 236 }; 237 238 enum pm_opchar_type { 239 PM_OPCHAR_TYPE_POWER = 1, 240 PM_OPCHAR_TYPE_TEMP, 241 PM_OPCHAR_TYPE_LATENCY, 242 }; 243 244 /** 245 * @PM_RET_SUCCESS: success 246 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) 247 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated) 248 * @PM_RET_ERROR_INTERNAL: internal error 249 * @PM_RET_ERROR_CONFLICT: conflict 250 * @PM_RET_ERROR_ACCESS: access rights violation 251 * @PM_RET_ERROR_INVALID_NODE: invalid node 252 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node 253 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted 254 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU 255 * @PM_RET_ERROR_NODE_USED: node is already in use 256 */ 257 enum pm_ret_status { 258 PM_RET_SUCCESS, 259 PM_RET_ERROR_ARGS = 1, 260 PM_RET_ERROR_NOTSUPPORTED = 4, 261 PM_RET_ERROR_INTERNAL = 2000, 262 PM_RET_ERROR_CONFLICT = 2001, 263 PM_RET_ERROR_ACCESS = 2002, 264 PM_RET_ERROR_INVALID_NODE = 2003, 265 PM_RET_ERROR_DOUBLE_REQ = 2004, 266 PM_RET_ERROR_ABORT_SUSPEND = 2005, 267 PM_RET_ERROR_TIMEOUT = 2006, 268 PM_RET_ERROR_NODE_USED = 2007, 269 PM_RET_ERROR_NO_FEATURE = 2008 270 }; 271 272 /** 273 * @PM_INITIAL_BOOT: boot is a fresh system startup 274 * @PM_RESUME: boot is a resume 275 * @PM_BOOT_ERROR: error, boot cause cannot be identified 276 */ 277 enum pm_boot_status { 278 PM_INITIAL_BOOT, 279 PM_RESUME, 280 PM_BOOT_ERROR, 281 }; 282 283 /** 284 * @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown 285 * @PMF_SHUTDOWN_TYPE_RESET: reset/reboot 286 * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope 287 */ 288 enum pm_shutdown_type { 289 PMF_SHUTDOWN_TYPE_SHUTDOWN, 290 PMF_SHUTDOWN_TYPE_RESET, 291 PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY, 292 }; 293 294 /** 295 * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only 296 * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL) 297 * @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system 298 */ 299 enum pm_shutdown_subtype { 300 PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM, 301 PMF_SHUTDOWN_SUBTYPE_PS_ONLY, 302 PMF_SHUTDOWN_SUBTYPE_SYSTEM, 303 }; 304 305 /** 306 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL 307 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL 308 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL 309 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input 310 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode 311 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize 312 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting 313 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control 314 * @PM_PLL_PARAM_CP: PLL charge pump control 315 * @PM_PLL_PARAM_RES: PLL loop filter resistor control 316 */ 317 enum pm_pll_param { 318 PM_PLL_PARAM_DIV2, 319 PM_PLL_PARAM_FBDIV, 320 PM_PLL_PARAM_DATA, 321 PM_PLL_PARAM_PRE_SRC, 322 PM_PLL_PARAM_POST_SRC, 323 PM_PLL_PARAM_LOCK_DLY, 324 PM_PLL_PARAM_LOCK_CNT, 325 PM_PLL_PARAM_LFHF, 326 PM_PLL_PARAM_CP, 327 PM_PLL_PARAM_RES, 328 PM_PLL_PARAM_MAX, 329 }; 330 331 /** 332 * @PM_PLL_MODE_RESET: PLL is in reset (not locked) 333 * @PM_PLL_MODE_INTEGER: PLL is locked in integer mode 334 * @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode 335 */ 336 enum pm_pll_mode { 337 PM_PLL_MODE_RESET, 338 PM_PLL_MODE_INTEGER, 339 PM_PLL_MODE_FRACTIONAL, 340 PM_PLL_MODE_MAX, 341 }; 342 343 /** 344 * @PM_CLOCK_DIV0_ID: Clock divider 0 345 * @PM_CLOCK_DIV1_ID: Clock divider 1 346 */ 347 enum pm_clock_div_id { 348 PM_CLOCK_DIV0_ID, 349 PM_CLOCK_DIV1_ID, 350 }; 351 352 /** 353 * EM API IDs 354 */ 355 enum em_api_id { 356 EM_SET_ACTION = 1, 357 EM_REMOVE_ACTION, 358 EM_SEND_ERRORS, 359 }; 360 361 #endif /* PM_DEFS_H */ 362
