1 /* 2 * Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 /** 7 * @file SoC configuration macros for the Atmel SAM4L family processors. 8 */ 9 10 #ifndef _SOC_ATMEL_SAM_SAM4L_SOC_H_ 11 #define _SOC_ATMEL_SAM_SAM4L_SOC_H_ 12 13 #ifndef _ASMLANGUAGE 14 15 #define DONT_USE_CMSIS_INIT 16 #define DONT_USE_PREDEFINED_CORE_HANDLERS 17 #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS 18 19 #if defined(CONFIG_SOC_SAM4LS8C) 20 #include <sam4ls8c.h> 21 #elif defined(CONFIG_SOC_SAM4LS8B) 22 #include <sam4ls8b.h> 23 #elif defined(CONFIG_SOC_SAM4LS8A) 24 #include <sam4ls8a.h> 25 #elif defined(CONFIG_SOC_SAM4LS4C) 26 #include <sam4ls4c.h> 27 #elif defined(CONFIG_SOC_SAM4LS4B) 28 #include <sam4ls4b.h> 29 #elif defined(CONFIG_SOC_SAM4LS4A) 30 #include <sam4ls4a.h> 31 #elif defined(CONFIG_SOC_SAM4LS2C) 32 #include <sam4ls2c.h> 33 #elif defined(CONFIG_SOC_SAM4LS2B) 34 #include <sam4ls2b.h> 35 #elif defined(CONFIG_SOC_SAM4LS2A) 36 #include <sam4ls2a.h> 37 #elif defined(CONFIG_SOC_SAM4LC8C) 38 #include <sam4lc8c.h> 39 #elif defined(CONFIG_SOC_SAM4LC8B) 40 #include <sam4lc8b.h> 41 #elif defined(CONFIG_SOC_SAM4LC8A) 42 #include <sam4lc8a.h> 43 #elif defined(CONFIG_SOC_SAM4LC4C) 44 #include <sam4lc4c.h> 45 #elif defined(CONFIG_SOC_SAM4LC4B) 46 #include <sam4lc4b.h> 47 #elif defined(CONFIG_SOC_SAM4LC4A) 48 #include <sam4lc4a.h> 49 #elif defined(CONFIG_SOC_SAM4LC2C) 50 #include <sam4lc2c.h> 51 #elif defined(CONFIG_SOC_SAM4LC2B) 52 #include <sam4lc2b.h> 53 #elif defined(CONFIG_SOC_SAM4LC2A) 54 #include <sam4lc2a.h> 55 #else 56 #error Library does not support the specified device. 57 #endif 58 59 #include "../common/soc_pmc.h" 60 #include "../common/soc_gpio.h" 61 #include "../common/atmel_sam_dt.h" 62 63 /** Processor Clock (HCLK) Frequency */ 64 #define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ 65 66 /** Master Clock (MCK) Frequency */ 67 #define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ 68 69 #define SOC_ATMEL_SAM_RCSYS_NOMINAL_HZ 115000 70 #define SOC_ATMEL_SAM_RC32K_NOMINAL_HZ 32768 71 72 /** Oscillator identifiers 73 * External Oscillator 0 74 * External 32 kHz oscillator 75 * Internal 32 kHz RC oscillator 76 * Internal 80 MHz RC oscillator 77 * Internal 4-8-12 MHz RCFAST oscillator 78 * Internal 1 MHz RC oscillator 79 * Internal System RC oscillator 80 */ 81 #define OSC_ID_OSC0 0 82 #define OSC_ID_OSC32 1 83 #define OSC_ID_RC32K 2 84 #define OSC_ID_RC80M 3 85 #define OSC_ID_RCFAST 4 86 #define OSC_ID_RC1M 5 87 #define OSC_ID_RCSYS 6 88 89 /** System clock source 90 * System RC oscillator 91 * Oscillator 0 92 * Phase Locked Loop 0 93 * Digital Frequency Locked Loop 94 * 80 MHz RC oscillator 95 * 4-8-12 MHz RC oscillator 96 * 1 MHz RC oscillator 97 */ 98 #define OSC_SRC_RCSYS 0 99 #define OSC_SRC_OSC0 1 100 #define OSC_SRC_PLL0 2 101 #define OSC_SRC_DFLL 3 102 #define OSC_SRC_RC80M 4 103 #define OSC_SRC_RCFAST 5 104 #define OSC_SRC_RC1M 6 105 106 #define PM_CLOCK_MASK(bus, per) ((bus << 5) + per) 107 108 /** Bus index of maskable module clocks. Peripheral ids are defined out of 109 * order. It start from PBA up to PBD, then move to HSB, and finally CPU. 110 */ 111 #define PM_CLK_GRP_CPU 5 112 #define PM_CLK_GRP_HSB 4 113 #define PM_CLK_GRP_PBA 0 114 #define PM_CLK_GRP_PBB 1 115 #define PM_CLK_GRP_PBC 2 116 #define PM_CLK_GRP_PBD 3 117 118 /** Clocks derived from the CPU clock 119 */ 120 #define SYSCLK_OCD 0 121 122 /** Clocks derived from the HSB clock 123 */ 124 #define SYSCLK_PDCA_HSB 0 125 #define SYSCLK_HFLASHC_DATA 1 126 #define SYSCLK_HRAMC1_DATA 2 127 #define SYSCLK_USBC_DATA 3 128 #define SYSCLK_CRCCU_DATA 4 129 #define SYSCLK_PBA_BRIDGE 5 130 #define SYSCLK_PBB_BRIDGE 6 131 #define SYSCLK_PBC_BRIDGE 7 132 #define SYSCLK_PBD_BRIDGE 8 133 #define SYSCLK_AESA_HSB 9 134 135 /** Clocks derived from the PBA clock 136 */ 137 #define SYSCLK_IISC 0 138 #define SYSCLK_SPI 1 139 #define SYSCLK_TC0 2 140 #define SYSCLK_TC1 3 141 #define SYSCLK_TWIM0 4 142 #define SYSCLK_TWIS0 5 143 #define SYSCLK_TWIM1 6 144 #define SYSCLK_TWIS1 7 145 #define SYSCLK_USART0 8 146 #define SYSCLK_USART1 9 147 #define SYSCLK_USART2 10 148 #define SYSCLK_USART3 11 149 #define SYSCLK_ADCIFE 12 150 #define SYSCLK_DACC 13 151 #define SYSCLK_ACIFC 14 152 #define SYSCLK_GLOC 15 153 #define SYSCLK_ABDACB 16 154 #define SYSCLK_TRNG 17 155 #define SYSCLK_PARC 18 156 #define SYSCLK_CATB 19 157 #define SYSCLK_TWIM2 21 158 #define SYSCLK_TWIM3 22 159 #define SYSCLK_LCDCA 23 160 161 /** Clocks derived from the PBB clock 162 */ 163 #define SYSCLK_HFLASHC_REGS 0 164 #define SYSCLK_HRAMC1_REGS 1 165 #define SYSCLK_HMATRIX 2 166 #define SYSCLK_PDCA_PB 3 167 #define SYSCLK_CRCCU_REGS 4 168 #define SYSCLK_USBC_REGS 5 169 #define SYSCLK_PEVC 6 170 171 /** Clocks derived from the PBC clock 172 */ 173 #define SYSCLK_PM 0 174 #define SYSCLK_CHIPID 1 175 #define SYSCLK_SCIF 2 176 #define SYSCLK_FREQM 3 177 #define SYSCLK_GPIO 4 178 179 /** Clocks derived from the PBD clock 180 */ 181 #define SYSCLK_BPM 0 182 #define SYSCLK_BSCIF 1 183 #define SYSCLK_AST 2 184 #define SYSCLK_WDT 3 185 #define SYSCLK_EIC 4 186 #define SYSCLK_PICOUART 5 187 188 /** Divided clock mask derived from the PBA clock 189 */ 190 #define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) 191 #define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) 192 #define PBA_DIVMASK_CLK_USART (1u << 2) 193 #define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) 194 #define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) 195 #define PBA_DIVMASK_Msk (0x7Fu << 0) 196 197 /** Generic Clock Instances 198 * 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) 199 * 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER) 200 * 2- AST and GCLK2 pin 201 * 3- CATB and GCLK3 pin 202 * 4- AESA 203 * 5- GLOC, TC0 and RC32KIFB_REF 204 * 6- ABDACB and IISC 205 * 7- USBC 206 * 8- TC1 and PEVC[0] 207 * 9- PLL0 and PEVC[1] 208 * 10- ADCIFE 209 * 11- Master generic clock. Can be used as source for other generic clocks. 210 */ 211 #define GEN_CLK_DFLL_REF 0 212 #define GEN_CLK_DFLL_DITHER 1 213 #define GEN_CLK_AST 2 214 #define GEN_CLK_CATB 3 215 #define GEN_CLK_AESA 4 216 #define GEN_CLK_TC0_GLOC_RC32 5 217 #define GEN_CLK_ABDACB 6 218 #define GEN_CLK_USBC 7 219 #define GEN_CLK_TC1_PEVC0 8 220 #define GEN_CLK_PLL0_PEVC1 9 221 #define GEN_CLK_ADCIFE 10 222 #define GEN_CLK_MASTER_GEN 11 223 224 /** 225 * 0- System RC oscillator 226 * 1- 32 kHz oscillator 227 * 2- DFLL 228 * 3- Oscillator 0 229 * 4- 80 MHz RC oscillator 230 * 5- 4-8-12 MHz RC oscillator 231 * 6- 1 MHz RC oscillator 232 * 7- CPU clock 233 * 8- High Speed Bus clock 234 * 9- Peripheral Bus A clock 235 * 10- Peripheral Bus B clock 236 * 11- Peripheral Bus C clock 237 * 12- Peripheral Bus D clock 238 * 13- 32 kHz RC oscillator 239 * 15- 1 kHz output from OSC32K 240 * 16- PLL0 241 * 17- High resolution prescaler 242 * 18- Fractional prescaler 243 * 19- GCLKIN0 244 * 20- GCLKIN1 245 * 21- GCLK11 246 */ 247 248 #define GEN_CLK_SRC_RCSYS 0 249 #define GEN_CLK_SRC_OSC32K 1 250 #define GEN_CLK_SRC_DFLL 2 251 #define GEN_CLK_SRC_OSC0 3 252 #define GEN_CLK_SRC_RC80M 4 253 #define GEN_CLK_SRC_RCFAST 5 254 #define GEN_CLK_SRC_RC1M 6 255 #define GEN_CLK_SRC_CLK_CPU 7 256 #define GEN_CLK_SRC_CLK_HSB 8 257 #define GEN_CLK_SRC_CLK_PBA 9 258 #define GEN_CLK_SRC_CLK_PBB 10 259 #define GEN_CLK_SRC_CLK_PBC 11 260 #define GEN_CLK_SRC_CLK_PBD 12 261 #define GEN_CLK_SRC_RC32K 13 262 #define GEN_CLK_SRC_CLK_1K 15 263 #define GEN_CLK_SRC_PLL0 16 264 #define GEN_CLK_SRC_HRPCLK 17 265 #define GEN_CLK_SRC_FPCLK 18 266 #define GEN_CLK_SRC_GCLKIN0 19 267 #define GEN_CLK_SRC_GCLKIN1 20 268 #define GEN_CLK_SRC_GCLK11 21 269 270 #endif /* !_ASMLANGUAGE */ 271 272 #endif /* _SOC_ATMEL_SAM_SAM4L_SOC_H_ */ 273
