PMU_REG_3P0_ENABLE_ILIMIT_MASK (definition) in projects: hal_nxp-3.5.0

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Searched defs:PMU_REG_3P0_ENABLE_ILIMIT_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
D	MIMXRT1011.h	`23102 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
D	MIMXRT1015.h	`25793 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
D	MIMXRT1021.h	`29980 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
D	MIMXRT1024.h	`29963 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
D	MIMXRT1041.h	`32608 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
D	MIMXRT1051.h	`31023 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
D	MIMXRT1052.h	`33730 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
D	MIMXRT1061.h	`33353 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
D	MIMXRT1042.h	`34459 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
D	MIMXRT1062.h	`35988 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
D	MIMXRT1064.h	`35982 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro`
/hal_nxp-3.5.0/imx/devices/MCIMX6X/
D	MCIMX6X_M4.h	`28667 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u macro`

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