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Searched defs:PMU_REG_2P5_ENABLE_ILIMIT_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h23282 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h25973 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h30160 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h30143 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h32788 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h31203 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h33910 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h33533 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h34639 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h36168 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h36162 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) macro
/hal_nxp-3.5.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28686 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK 0x4u macro