1 /*
2 ** ###################################################################
3 **     Processors:          MCIMX7D_M4
4 **
5 **     Compilers:           Keil ARM C/C++ Compiler
6 **                          Freescale C/C++ for Embedded ARM
7 **                          GNU C Compiler
8 **                          GNU C Compiler - CodeSourcery Sourcery G++
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **
11 **     Reference manual:
12 **     Version:             rev. 1.0, 2015-07-15
13 **     Build:               b150715
14 **
15 **     Abstract:
16 **         CMSIS Peripheral Access Layer for MCIMX7D_M4
17 **
18 **     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
19 **     All rights reserved.
20 **
21 **     Redistribution and use in source and binary forms, with or without modification,
22 **     are permitted provided that the following conditions are met:
23 **
24 **     o Redistributions of source code must retain the above copyright notice, this list
25 **       of conditions and the following disclaimer.
26 **
27 **     o Redistributions in binary form must reproduce the above copyright notice, this
28 **       list of conditions and the following disclaimer in the documentation and/or
29 **       other materials provided with the distribution.
30 **
31 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
32 **       contributors may be used to endorse or promote products derived from this
33 **       software without specific prior written permission.
34 **
35 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
37 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
39 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
44 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 **
46 **     http:                 www.freescale.com
47 **     mail:                 support@freescale.com
48 **
49 **     Revisions:
50 **     - rev. 1.0 (2015-07-15)
51 **         Initial version .
52 **
53 ** ###################################################################
54 */
55 
56 /*!
57  * @file MCIMX7D_M4.h
58  * @version 1.0
59  * @date 2015-07-15
60  * @brief CMSIS Peripheral Access Layer for MCIMX7D_M4
61  *
62  * CMSIS Peripheral Access Layer for MCIMX7D_M4
63  */
64 
65 
66 /* ----------------------------------------------------------------------------
67    -- MCU activation
68    ---------------------------------------------------------------------------- */
69 
70 /* Prevention from multiple including the same memory map */
71 #if !defined(MCIMX7D_M4_H_)  /* Check if memory map has not been already included */
72 #define MCIMX7D_M4_H_
73 #define MCU_MCIMX7D_M4
74 
75 
76 /* Check if another memory map has not been also included */
77 #if (defined(MCU_ACTIVE))
78     #error MCIMX7D_M4 memory map: There is already included another memory map. Only one memory map can be included.
79 #endif /* (defined(MCU_ACTIVE)) */
80 #define MCU_ACTIVE
81 
82 #include <stdint.h>
83 
84 /** Memory map major version (memory maps with equal major version number are
85  * compatible) */
86 #define MCU_MEM_MAP_VERSION 0x0100u
87 /** Memory map minor version */
88 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
89 
90 
91 /* ----------------------------------------------------------------------------
92    -- Interrupt vector numbers
93    ---------------------------------------------------------------------------- */
94 
95 /*!
96  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
97  * @{
98  */
99 
100 /** Interrupt Number Definitions */
101 #define NUMBER_OF_INT_VECTORS 144                  /**< Number of interrupts in the Vector table */
102 
103 typedef enum IRQn {
104   /* Auxiliary constants */
105   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
106 
107   /* Core interrupts */
108   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
109   HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
110   MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
111   BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
112   UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
113   SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
114   DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
115   PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
116   SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
117 
118   /* Device specific interrupts */
119   GPR_IRQn                     = 0,                /**<  Used to notify cores on exception condition while boot */
120   DAP_IRQn                     = 1,                /**<  DAP Interrupt */
121   SDMA_IRQn                    = 2,                /**<  AND of all 48 SDMA interrupts (events) from all the channels */
122   DBGMON_IRQn                  = 3,                /**<  DBGMON Sync Interrupt */
123   SNVS_IRQn                    = 4,                /**<  ON-OFF button press shorter than 5 seconds (pulse event) */
124   LCDIF_IRQn                   = 5,                /**<  LCDIF Sync Interrupt */
125   SIM2_IRQn                    = 6,                /**<  SIM Interrupt */
126   CSI_IRQn                     = 7,                /**<  CSI Interrupt */
127   PXP1_IRQn                    = 8,                /**<  PXP Interrupt */
128   Reserved_IRQn                = 9,                /**<  Reserved */
129   WDOG3_IRQn                   = 10,               /**<  Watchdog Timer reset */
130   SEMA4_HS_M4_IRQn             = 11,               /**<  SEMA4-HS M4 Interrupt Request */
131   APBHDMA_IRQn                 = 12,               /**<  GPMI operation channel 0 description complete interrupt */
132   EIM_IRQn                     = 13,               /**<  EIM Interrupt */
133   BCH_IRQn                     = 14,               /**<  BCH operation complete interrupt */
134   GPMI_IRQn                    = 15,               /**<  GPMI operation TIMEOUT ERROR interrupt */
135   UART6_IRQn                   = 16,               /**<  UART-6 ORed interrupt */
136   FTM1_IRQn                    = 17,               /**<  Flex Timer1 Fault / Counter / Channel interrupt */
137   FTM2_IRQn                    = 18,               /**<  Flex Timer2 Fault / Counter / Channel interrupt */
138   SNVS_CONSOLIDATED_IRQn       = 19,               /**<  SRTC Consolidated Interrupt. Non TZ. */
139   SNVS_SECURITY_IRQn           = 20,               /**<  SRTC Security Interrupt. TZ. */
140   CSU_IRQn                     = 21,               /**<  CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted */
141   uSDHC1_IRQn                  = 22,               /**<  uSDHC1 Enhanced SDHC Interrupt Request */
142   uSDHC2_IRQn                  = 23,               /**<  uSDHC2 Enhanced SDHC Interrupt Request */
143   uSDHC3_IRQn                  = 24,               /**<  uSDHC3 Enhanced SDHC Interrupt Request */
144   MIPI_CSI_IRQn                = 25,               /**<  MIPI CSI interrupt */
145   UART1_IRQn                   = 26,               /**<  UART-1 ORed interrupt */
146   UART2_IRQn                   = 27,               /**<  UART-2 ORed interrupt */
147   UART3_IRQn                   = 28,               /**<  UART-3 ORed interrupt */
148   UART4_IRQn                   = 29,               /**<  UART-4 ORed interrupt */
149   UART5_IRQn                   = 30,               /**<  UART-5 ORed interrupt */
150   eCSPI1_IRQn                  = 31,               /**<  eCSPI1 interrupt request line to the core. */
151   eCSPI2_IRQn                  = 32,               /**<  eCSPI2 interrupt request line to the core. */
152   eCSPI3_IRQn                  = 33,               /**<  eCSPI3 interrupt request line to the core. */
153   eCSPI4_IRQn                  = 34,               /**<  eCSPI4 interrupt request line to the core. */
154   I2C1_IRQn                    = 35,               /**<  I2C-1 Interrupt */
155   I2C2_IRQn                    = 36,               /**<  I2C-2 Interrupt */
156   I2C3_IRQn                    = 37,               /**<  I2C-3 Interrupt */
157   I2C4_IRQn                    = 38,               /**<  I2C-4 Interrupt */
158   RDC_IRQn                     = 39,               /**<  RDC interrupt */
159   USB_OH3_OTG2_1_IRQn          = 40,               /**<  USB OH3 OTG2 */
160   MIPI_DSI_IRQn                = 41,               /**<  MIPI CSI Interrupt */
161   USB_OH3_OTG2_2_IRQn          = 42,               /**<  USB OH3 OTG2 */
162   USB_OH2_OTG_IRQn             = 43,               /**<  USB OH2 OTG */
163   USB_OTG1_IRQn                = 44,               /**<  USB OTG1 Interrupt */
164   USB_OTG2_IRQn                = 45,               /**<  USB OTG2 Interrupt */
165   PXP2_IRQn                    = 46,               /**<  PXP interrupt */
166   SCTR1_IRQn                   = 47,               /**<  ISO7816IP Interrupt */
167   SCTR2_IRQn                   = 48,               /**<  ISO7816IP Interrupt */
168   Analog_TempSensor_IRQn       = 49,               /**<  TempSensor (Temperature low alarm). */
169   SAI3_IRQn                    = 50,               /**<  SAI3 Receive / Transmit Interrupt */
170   Analog_brown_out_IRQn        = 51,               /**<  Brown-out event on either analog regulators. */
171   GPT4_IRQn                    = 52,               /**<  OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */
172   GPT3_IRQn                    = 53,               /**<  OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */
173   GPT2_IRQn                    = 54,               /**<  OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */
174   GPT1_IRQn                    = 55,               /**<  OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */
175   GPIO1_INT7_IRQn              = 56,               /**<  Active HIGH Interrupt from INT7 from GPIO */
176   GPIO1_INT6_IRQn              = 57,               /**<  Active HIGH Interrupt from INT6 from GPIO */
177   GPIO1_INT5_IRQn              = 58,               /**<  Active HIGH Interrupt from INT5 from GPIO */
178   GPIO1_INT4_IRQn              = 59,               /**<  Active HIGH Interrupt from INT4 from GPIO */
179   GPIO1_INT3_IRQn              = 60,               /**<  Active HIGH Interrupt from INT3 from GPIO */
180   GPIO1_INT2_IRQn              = 61,               /**<  Active HIGH Interrupt from INT2 from GPIO */
181   GPIO1_INT1_IRQn              = 62,               /**<  Active HIGH Interrupt from INT1 from GPIO */
182   GPIO1_INT0_IRQn              = 63,               /**<  Active HIGH Interrupt from INT0 from GPIO */
183   GPIO1_INT15_0_IRQn           = 64,               /**<  Combined interrupt indication for GPIO1 signal 0 throughout 15 */
184   GPIO1_INT31_16_IRQn          = 65,               /**<  Combined interrupt indication for GPIO1 signal 16 throughout 31 */
185   GPIO2_INT15_0_IRQn           = 66,               /**<  Combined interrupt indication for GPIO2 signal 0 throughout 15 */
186   GPIO2_INT31_16_IRQn          = 67,               /**<  Combined interrupt indication for GPIO2 signals 16 throughout 31 */
187   GPIO3_INT15_0_IRQn           = 68,               /**<  Combined interrupt indication for GPIO3 signal 0 throughout 15 */
188   GPIO3_INT31_16_IRQn          = 69,               /**<  Combined interrupt indication for GPIO3 signals 16 throughout 31 */
189   GPIO4_INT15_0_IRQn           = 70,               /**<  Combined interrupt indication for GPIO4 signal 0 throughout 15 */
190   GPIO4_INT31_16_IRQn          = 71,               /**<  Combined interrupt indication for GPIO4 signal 16 throughout 31 */
191   GPIO5_INT15_0_IRQn           = 72,               /**<  Combined interrupt indication for GPIO5 signals 0 throughout 15 */
192   GPIO5_INT31_16_IRQn          = 73,               /**<  Combined interrupt indication for GPIO5 signals 16 throughout 31 */
193   GPIO6_INT15_0_IRQn           = 74,               /**<  Combined interrupt indication for GPIO6 signals 0 throughtout 15 */
194   GPIO6_INT31_16_IRQn          = 75,               /**<  Combined interrupt indication for GPIO6 signals 16 throughtout 31 */
195   GPIO7_INT15_0_IRQn           = 76,               /**<  Combined interrupt indication for GPIO7 signals 0 throughout 15 */
196   GPIO7_INT31_16_IRQn          = 77,               /**<  Combined interrupt indication for GPIO7 signals 16 throughout 31 */
197   WDOG1_IRQn                   = 78,               /**<  Watchdog Timer reset */
198   WDOG2_IRQn                   = 79,               /**<  Watchdog Timer reset */
199   KPP_IRQn                     = 80,               /**<  Keypad Interrupt */
200   PWM1_IRQn                    = 81,               /**<  Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */
201   PWM2_IRQn                    = 82,               /**<  Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */
202   PWM3_IRQn                    = 83,               /**<  Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */
203   PWM4_IRQn                    = 84,               /**<  Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */
204   CCM1_IRQn                    = 85,               /**<  CCM, Interrupt Request 1 */
205   CCM2_IRQn                    = 86,               /**<  CCM, Interrupt Request 2 */
206   GPC_IRQn                     = 87,               /**<  GPC Interrupt Request 1 */
207   MU_A7_IRQn                   = 88,               /**<  Interrupt to A7 */
208   SRC_IRQn                     = 89,               /**<  SRC interrupt request */
209   SIM1_IRQn                    = 90,               /**<  Sim Interrupt */
210   RTIC_IRQn                    = 91,               /**<  RTIC Interrupt */
211   CPU_IRQn                     = 92,               /**<  Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0])
212                                                          Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */
213   CPU_CTI_IRQn                 = 93,               /**<  CTI trigger outputs (internal: nCTIIRQ[0])
214                                                          CTI trigger outputs (internal: nCTIIRQ[1]) */
215   CCM_SRC_GPC_IRQn             = 94,               /**<  SRC GPC Combined CPU wdog interrupts (4x) out of SRC. */
216   SAI1_IRQn                    = 95,               /**<  SAI1 Receive / Transmit Interrupt */
217   SAI2_IRQn                    = 96,               /**<  SAI2 Receive / Transmit Interrupt */
218   MU_M4_IRQn                   = 97,               /**<  Interrupt to M4 */
219   ADC1_IRQn                    = 98,               /**<  ADC-1 Interrupt */
220   ADC2_IRQn                    = 99,               /**<  ADC-2 Interrupt */
221   ENET2_MAC0_TRANS1_IRQn       = 100,              /**<  MAC 0 Receive / Transmit Frame / Buffer Done */
222   ENET2_MAC0_TRANS2_IRQn       = 101,              /**<  MAC 0 Receive / Transmit Frame / Buffer Done */
223   ENET2_MAC0_IRQ_IRQn          = 102,              /**<  MAC 0 IRQ */
224   ENET2_1588_TIMER_IRQ_IRQn    = 103,              /**<  MAC 0 1588 Timer Interrupt - synchronous */
225   TPR_IRQn                     = 104,              /**<  IRQ TPR IRQ */
226   CAAM_QUEUE_IRQn              = 105,              /**<  WRAPPER CAAM interrupt queue for JQ */
227   CAAM_ERROR_IRQn              = 106,              /**<  WRAPPER CAAM interrupt queue for JQ */
228   QSPI_IRQn                    = 107,              /**<  QSPI Interrupt */
229   TZASC1_IRQn                  = 108,              /**<  TZASC (PL380) interrupt */
230   WDOG4_IRQn                   = 109,              /**<  Watchdog Timer reset */
231   FLEXCAN1_IRQn                = 110,              /**<  FlexCAN1 Interrupt */
232   FLEXCAN2_IRQn                = 111,              /**<  FlexCAN2 Interrupt */
233   PERFMON1_IRQn                = 112,              /**<  General interrupt */
234   PERFMON2_IRQn                = 113,              /**<  General interrupt */
235   CAAM_WRAPPER1_IRQn           = 114,              /**<  CAAM interrupt queue for JQ */
236   CAAM_WRAPPER2_IRQn           = 115,              /**<  Recoverable error interrupt */
237   SEMA4_HS_A7_IRQn             = 116,              /**<  SEMA4-HS processor A7 Interrupt Request */
238   EPDC_IRQn                    = 117,              /**<  EPDC Interrupt */
239   ENET1_MAC0_TRANS1_IRQn       = 118,              /**<  MAC 0 Receive / Trasmit Frame / Buffer Done */
240   ENET1_MAC0_TRANS2_IRQn       = 119,              /**<  MAC 0 Receive / Trasmit Frame / Buffer Done */
241   ENET1_MAC0_IRQn              = 120,              /**<  MAC 0 IRQ */
242   ENET1_1588_TIMER_IRQn        = 121,              /**<  MAC 0 1588 Timer Interrupt - synchronous */
243   PCIE_CTRL1_IRQn              = 122,              /**<  Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
244   PCIE_CTRL2_IRQn              = 123,              /**<  Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
245   PCIE_CTRL3_IRQn              = 124,              /**<  Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
246   PCIE_CTRL4_IRQn              = 125,              /**<  Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
247   UART7_IRQn                   = 126,              /**<  UART-7 ORed interrupt */
248   PCIE_CTRL_REQUEST_IRQn       = 127,              /**<  Channels [63:32] interrupts requests */
249 } IRQn_Type;
250 
251 /*!
252  * @}
253  */ /* end of group Interrupt_vector_numbers */
254 
255 /* ----------------------------------------------------------------------------
256    -- Cortex M4 Core Configuration
257    ---------------------------------------------------------------------------- */
258 
259 /*!
260  * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
261  * @{
262  */
263 
264 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
265 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
266 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
267 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
268 
269 #include "core_cm4.h"                  /* Core Peripheral Access Layer */
270 
271 /*!
272  * @}
273  */ /* end of group Cortex_Core_Configuration */
274 
275 
276 /* ----------------------------------------------------------------------------
277    -- Device Peripheral Access Layer
278    ---------------------------------------------------------------------------- */
279 
280 /*!
281  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
282  * @{
283  */
284 
285 
286 /*
287 ** Start of section using anonymous unions
288 */
289 
290 #if defined(__ARMCC_VERSION)
291   #pragma push
292   #pragma anon_unions
293 #elif defined(__GNUC__)
294   /* anonymous unions are enabled by default */
295 #elif defined(__IAR_SYSTEMS_ICC__)
296   #pragma language=extended
297 #else
298   #error Not supported compiler type
299 #endif
300 /* ----------------------------------------------------------------------------
301    -- ADC Peripheral Access Layer
302    ---------------------------------------------------------------------------- */
303 
304 /*!
305  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
306  * @{
307  */
308 
309 /** ADC - Register Layout Typedef */
310 typedef struct {
311   __IO  uint32_t CH_A_CFG1;                              /**< Channel A configuration 1, offset: 0x0 */
312   uint8_t RESERVED_0[12];
313   __IO  uint32_t CH_A_CFG2;                              /**< Channel A configuration 2, offset: 0x10 */
314   uint8_t RESERVED_1[12];
315   __IO  uint32_t CH_B_CFG1;                              /**< , offset: 0x20 */
316   uint8_t RESERVED_2[12];
317   __IO  uint32_t CH_B_CFG2;                              /**< Channel B Configuration 2, offset: 0x30 */
318   uint8_t RESERVED_3[12];
319   __IO  uint32_t CH_C_CFG1;                              /**< Channel C Configuration 1, offset: 0x40 */
320   uint8_t RESERVED_4[12];
321   __IO  uint32_t CH_C_CFG2;                              /**< Channel C Configuration 2, offset: 0x50 */
322   uint8_t RESERVED_5[12];
323   __IO  uint32_t CH_D_CFG1;                              /**< Channel D Configuration 1, offset: 0x60 */
324   uint8_t RESERVED_6[12];
325   __IO  uint32_t CH_D_CFG2;                              /**< Channel D Configuration 2, offset: 0x70 */
326   uint8_t RESERVED_7[12];
327   __IO  uint32_t CH_SW_CFG;                              /**< Channel Software Configuration, offset: 0x80 */
328   uint8_t RESERVED_8[12];
329   __IO  uint32_t TIMER_UNIT;                             /**< Timer Unit, offset: 0x90 */
330   uint8_t RESERVED_9[12];
331   __IO  uint32_t DMA_FIFO;                               /**< DMA FIFO, offset: 0xA0 */
332   uint8_t RESERVED_10[12];
333   __IO  uint32_t FIFO_STATUS;                            /**< FIFO Status, offset: 0xB0 */
334   uint8_t RESERVED_11[12];
335   __IO  uint32_t INT_SIG_EN;                             /**< , offset: 0xC0 */
336   uint8_t RESERVED_12[12];
337   __IO  uint32_t INT_EN;                                 /**< Interrupt Enable, offset: 0xD0 */
338   uint8_t RESERVED_13[12];
339   __IO  uint32_t INT_STATUS;                             /**< , offset: 0xE0 */
340   uint8_t RESERVED_14[12];
341   __IO  uint32_t CHA_B_CNV_RSLT;                         /**< Channel A and B Conversion Result, offset: 0xF0 */
342   uint8_t RESERVED_15[12];
343   __IO  uint32_t CHC_D_CNV_RSLT;                         /**< Channel C and D Conversion Result, offset: 0x100 */
344   uint8_t RESERVED_16[12];
345   __IO  uint32_t CH_SW_CNV_RSLT;                         /**< Channel Software Conversion Result, offset: 0x110 */
346   uint8_t RESERVED_17[12];
347   __IO  uint32_t DMA_FIFO_DAT;                           /**< DMA FIFO Data, offset: 0x120 */
348   uint8_t RESERVED_18[12];
349   __IO  uint32_t ADC_CFG;                                /**< ADC Configuration, offset: 0x130 */
350 } ADC_Type, *ADC_MemMapPtr;
351 /* ----------------------------------------------------------------------------
352    -- ADC - Register accessor macros
353    ---------------------------------------------------------------------------- */
354 
355 /*!
356  * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
357  * @{
358  */
359 
360 
361 /* ADC - Register accessors */
362 #define ADC_CH_A_CFG1_REG(base)                  ((base)->CH_A_CFG1)
363 #define ADC_CH_A_CFG2_REG(base)                  ((base)->CH_A_CFG2)
364 #define ADC_CH_B_CFG1_REG(base)                  ((base)->CH_B_CFG1)
365 #define ADC_CH_B_CFG2_REG(base)                  ((base)->CH_B_CFG2)
366 #define ADC_CH_C_CFG1_REG(base)                  ((base)->CH_C_CFG1)
367 #define ADC_CH_C_CFG2_REG(base)                  ((base)->CH_C_CFG2)
368 #define ADC_CH_D_CFG1_REG(base)                  ((base)->CH_D_CFG1)
369 #define ADC_CH_D_CFG2_REG(base)                  ((base)->CH_D_CFG2)
370 #define ADC_CH_SW_CFG_REG(base)                  ((base)->CH_SW_CFG)
371 #define ADC_TIMER_UNIT_REG(base)                 ((base)->TIMER_UNIT)
372 #define ADC_DMA_FIFO_REG(base)                   ((base)->DMA_FIFO)
373 #define ADC_FIFO_STATUS_REG(base)                ((base)->FIFO_STATUS)
374 #define ADC_INT_SIG_EN_REG(base)                 ((base)->INT_SIG_EN)
375 #define ADC_INT_EN_REG(base)                     ((base)->INT_EN)
376 #define ADC_INT_STATUS_REG(base)                 ((base)->INT_STATUS)
377 #define ADC_CHA_B_CNV_RSLT_REG(base)             ((base)->CHA_B_CNV_RSLT)
378 #define ADC_CHC_D_CNV_RSLT_REG(base)             ((base)->CHC_D_CNV_RSLT)
379 #define ADC_CH_SW_CNV_RSLT_REG(base)             ((base)->CH_SW_CNV_RSLT)
380 #define ADC_DMA_FIFO_DAT_REG(base)               ((base)->DMA_FIFO_DAT)
381 #define ADC_ADC_CFG_REG(base)                    ((base)->ADC_CFG)
382 
383 /*!
384  * @}
385  */ /* end of group ADC_Register_Accessor_Macros */
386 /* ----------------------------------------------------------------------------
387    -- ADC Register Masks
388    ---------------------------------------------------------------------------- */
389 
390 /*!
391  * @addtogroup ADC_Register_Masks ADC Register Masks
392  * @{
393  */
394 
395 /* CH_A_CFG1 Bit Fields */
396 #define ADC_CH_A_CFG1_CHA_TIMER_MASK             0xFFFFFFu
397 #define ADC_CH_A_CFG1_CHA_TIMER_SHIFT            0
398 #define ADC_CH_A_CFG1_CHA_TIMER(x)               (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG1_CHA_TIMER_SHIFT))&ADC_CH_A_CFG1_CHA_TIMER_MASK)
399 #define ADC_CH_A_CFG1_CHA_SEL_MASK               0xF000000u
400 #define ADC_CH_A_CFG1_CHA_SEL_SHIFT              24
401 #define ADC_CH_A_CFG1_CHA_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG1_CHA_SEL_SHIFT))&ADC_CH_A_CFG1_CHA_SEL_MASK)
402 #define ADC_CH_A_CFG1_CHA_AVG_EN_MASK            0x20000000u
403 #define ADC_CH_A_CFG1_CHA_AVG_EN_SHIFT           29
404 #define ADC_CH_A_CFG1_CHA_SINGLE_MASK            0x40000000u
405 #define ADC_CH_A_CFG1_CHA_SINGLE_SHIFT           30
406 #define ADC_CH_A_CFG1_CHA_EN_MASK                0x80000000u
407 #define ADC_CH_A_CFG1_CHA_EN_SHIFT               31
408 /* CH_A_CFG2 Bit Fields */
409 #define ADC_CH_A_CFG2_CHA_LOW_THRES_MASK         0xFFFu
410 #define ADC_CH_A_CFG2_CHA_LOW_THRES_SHIFT        0
411 #define ADC_CH_A_CFG2_CHA_LOW_THRES(x)           (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_LOW_THRES_SHIFT))&ADC_CH_A_CFG2_CHA_LOW_THRES_MASK)
412 #define ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK        0x3000u
413 #define ADC_CH_A_CFG2_CHA_AVG_NUMBER_SHIFT       12
414 #define ADC_CH_A_CFG2_CHA_AVG_NUMBER(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_AVG_NUMBER_SHIFT))&ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK)
415 #define ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK          0x8000u
416 #define ADC_CH_A_CFG2_CHA_AUTO_DIS_SHIFT         15
417 #define ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK        0xFFF0000u
418 #define ADC_CH_A_CFG2_CHA_HIGH_THRES_SHIFT       16
419 #define ADC_CH_A_CFG2_CHA_HIGH_THRES(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_HIGH_THRES_SHIFT))&ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK)
420 #define ADC_CH_A_CFG2_CHA_CMP_MODE_MASK          0xE0000000u
421 #define ADC_CH_A_CFG2_CHA_CMP_MODE_SHIFT         29
422 #define ADC_CH_A_CFG2_CHA_CMP_MODE(x)            (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_CMP_MODE_SHIFT))&ADC_CH_A_CFG2_CHA_CMP_MODE_MASK)
423 /* CH_B_CFG1 Bit Fields */
424 #define ADC_CH_B_CFG1_CHB_TIMER_MASK             0xFFFFFFu
425 #define ADC_CH_B_CFG1_CHB_TIMER_SHIFT            0
426 #define ADC_CH_B_CFG1_CHB_TIMER(x)               (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG1_CHB_TIMER_SHIFT))&ADC_CH_B_CFG1_CHB_TIMER_MASK)
427 #define ADC_CH_B_CFG1_CHB_SEL_MASK               0xF000000u
428 #define ADC_CH_B_CFG1_CHB_SEL_SHIFT              24
429 #define ADC_CH_B_CFG1_CHB_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG1_CHB_SEL_SHIFT))&ADC_CH_B_CFG1_CHB_SEL_MASK)
430 #define ADC_CH_B_CFG1_CHB_AVG_EN_MASK            0x20000000u
431 #define ADC_CH_B_CFG1_CHB_AVG_EN_SHIFT           29
432 #define ADC_CH_B_CFG1_CHB_SINGLE_MASK            0x40000000u
433 #define ADC_CH_B_CFG1_CHB_SINGLE_SHIFT           30
434 #define ADC_CH_B_CFG1_CHB_EN_MASK                0x80000000u
435 #define ADC_CH_B_CFG1_CHB_EN_SHIFT               31
436 /* CH_B_CFG2 Bit Fields */
437 #define ADC_CH_B_CFG2_CHB_LOW_THRES_MASK         0xFFFu
438 #define ADC_CH_B_CFG2_CHB_LOW_THRES_SHIFT        0
439 #define ADC_CH_B_CFG2_CHB_LOW_THRES(x)           (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_LOW_THRES_SHIFT))&ADC_CH_B_CFG2_CHB_LOW_THRES_MASK)
440 #define ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK        0x3000u
441 #define ADC_CH_B_CFG2_CHB_AVG_NUMBER_SHIFT       12
442 #define ADC_CH_B_CFG2_CHB_AVG_NUMBER(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_AVG_NUMBER_SHIFT))&ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK)
443 #define ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK          0x8000u
444 #define ADC_CH_B_CFG2_CHB_AUTO_DIS_SHIFT         15
445 #define ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK        0xFFF0000u
446 #define ADC_CH_B_CFG2_CHB_HIGH_THRES_SHIFT       16
447 #define ADC_CH_B_CFG2_CHB_HIGH_THRES(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_HIGH_THRES_SHIFT))&ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK)
448 #define ADC_CH_B_CFG2_CHB_CMP_MODE_MASK          0xE0000000u
449 #define ADC_CH_B_CFG2_CHB_CMP_MODE_SHIFT         29
450 #define ADC_CH_B_CFG2_CHB_CMP_MODE(x)            (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_CMP_MODE_SHIFT))&ADC_CH_B_CFG2_CHB_CMP_MODE_MASK)
451 /* CH_C_CFG1 Bit Fields */
452 #define ADC_CH_C_CFG1_CHC_TIMER_MASK             0xFFFFFFu
453 #define ADC_CH_C_CFG1_CHC_TIMER_SHIFT            0
454 #define ADC_CH_C_CFG1_CHC_TIMER(x)               (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG1_CHC_TIMER_SHIFT))&ADC_CH_C_CFG1_CHC_TIMER_MASK)
455 #define ADC_CH_C_CFG1_CHC_SEL_MASK               0xF000000u
456 #define ADC_CH_C_CFG1_CHC_SEL_SHIFT              24
457 #define ADC_CH_C_CFG1_CHC_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG1_CHC_SEL_SHIFT))&ADC_CH_C_CFG1_CHC_SEL_MASK)
458 #define ADC_CH_C_CFG1_CHC_AVG_EN_MASK            0x20000000u
459 #define ADC_CH_C_CFG1_CHC_AVG_EN_SHIFT           29
460 #define ADC_CH_C_CFG1_CHC_SINGLE_MASK            0x40000000u
461 #define ADC_CH_C_CFG1_CHC_SINGLE_SHIFT           30
462 #define ADC_CH_C_CFG1_CHC_EN_MASK                0x80000000u
463 #define ADC_CH_C_CFG1_CHC_EN_SHIFT               31
464 /* CH_C_CFG2 Bit Fields */
465 #define ADC_CH_C_CFG2_CHC_LOW_THRES_MASK         0xFFFu
466 #define ADC_CH_C_CFG2_CHC_LOW_THRES_SHIFT        0
467 #define ADC_CH_C_CFG2_CHC_LOW_THRES(x)           (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_LOW_THRES_SHIFT))&ADC_CH_C_CFG2_CHC_LOW_THRES_MASK)
468 #define ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK        0x3000u
469 #define ADC_CH_C_CFG2_CHC_AVG_NUMBER_SHIFT       12
470 #define ADC_CH_C_CFG2_CHC_AVG_NUMBER(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_AVG_NUMBER_SHIFT))&ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK)
471 #define ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK          0x8000u
472 #define ADC_CH_C_CFG2_CHC_AUTO_DIS_SHIFT         15
473 #define ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK        0xFFF0000u
474 #define ADC_CH_C_CFG2_CHC_HIGH_THRES_SHIFT       16
475 #define ADC_CH_C_CFG2_CHC_HIGH_THRES(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_HIGH_THRES_SHIFT))&ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK)
476 #define ADC_CH_C_CFG2_CHC_CMP_MODE_MASK          0xE0000000u
477 #define ADC_CH_C_CFG2_CHC_CMP_MODE_SHIFT         29
478 #define ADC_CH_C_CFG2_CHC_CMP_MODE(x)            (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_CMP_MODE_SHIFT))&ADC_CH_C_CFG2_CHC_CMP_MODE_MASK)
479 /* CH_D_CFG1 Bit Fields */
480 #define ADC_CH_D_CFG1_CHD_TIMER_MASK             0xFFFFFFu
481 #define ADC_CH_D_CFG1_CHD_TIMER_SHIFT            0
482 #define ADC_CH_D_CFG1_CHD_TIMER(x)               (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG1_CHD_TIMER_SHIFT))&ADC_CH_D_CFG1_CHD_TIMER_MASK)
483 #define ADC_CH_D_CFG1_CHD_SEL_MASK               0xF000000u
484 #define ADC_CH_D_CFG1_CHD_SEL_SHIFT              24
485 #define ADC_CH_D_CFG1_CHD_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG1_CHD_SEL_SHIFT))&ADC_CH_D_CFG1_CHD_SEL_MASK)
486 #define ADC_CH_D_CFG1_CHD_AVG_EN_MASK            0x20000000u
487 #define ADC_CH_D_CFG1_CHD_AVG_EN_SHIFT           29
488 #define ADC_CH_D_CFG1_CHD_SINGLE_MASK            0x40000000u
489 #define ADC_CH_D_CFG1_CHD_SINGLE_SHIFT           30
490 #define ADC_CH_D_CFG1_CHD_EN_MASK                0x80000000u
491 #define ADC_CH_D_CFG1_CHD_EN_SHIFT               31
492 /* CH_D_CFG2 Bit Fields */
493 #define ADC_CH_D_CFG2_CHD_LOW_THRES_MASK         0xFFFu
494 #define ADC_CH_D_CFG2_CHD_LOW_THRES_SHIFT        0
495 #define ADC_CH_D_CFG2_CHD_LOW_THRES(x)           (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_LOW_THRES_SHIFT))&ADC_CH_D_CFG2_CHD_LOW_THRES_MASK)
496 #define ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK        0x3000u
497 #define ADC_CH_D_CFG2_CHD_AVG_NUMBER_SHIFT       12
498 #define ADC_CH_D_CFG2_CHD_AVG_NUMBER(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_AVG_NUMBER_SHIFT))&ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK)
499 #define ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK          0x8000u
500 #define ADC_CH_D_CFG2_CHD_AUTO_DIS_SHIFT         15
501 #define ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK        0xFFF0000u
502 #define ADC_CH_D_CFG2_CHD_HIGH_THRES_SHIFT       16
503 #define ADC_CH_D_CFG2_CHD_HIGH_THRES(x)          (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_HIGH_THRES_SHIFT))&ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK)
504 #define ADC_CH_D_CFG2_CHD_CMP_MODE_MASK          0xE0000000u
505 #define ADC_CH_D_CFG2_CHD_CMP_MODE_SHIFT         29
506 #define ADC_CH_D_CFG2_CHD_CMP_MODE(x)            (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_CMP_MODE_SHIFT))&ADC_CH_D_CFG2_CHD_CMP_MODE_MASK)
507 /* CH_SW_CFG Bit Fields */
508 #define ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK      0x600000u
509 #define ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_SHIFT     21
510 #define ADC_CH_SW_CFG_CH_SW_AVG_NUMBER(x)        (((uint32_t)(((uint32_t)(x))<<ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_SHIFT))&ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK)
511 #define ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK          0x800000u
512 #define ADC_CH_SW_CFG_CH_SW_AVG_EN_SHIFT         23
513 #define ADC_CH_SW_CFG_CH_SW_SEL_MASK             0xF000000u
514 #define ADC_CH_SW_CFG_CH_SW_SEL_SHIFT            24
515 #define ADC_CH_SW_CFG_CH_SW_SEL(x)               (((uint32_t)(((uint32_t)(x))<<ADC_CH_SW_CFG_CH_SW_SEL_SHIFT))&ADC_CH_SW_CFG_CH_SW_SEL_MASK)
516 #define ADC_CH_SW_CFG_START_CONV_MASK            0x80000000u
517 #define ADC_CH_SW_CFG_START_CONV_SHIFT           31
518 /* TIMER_UNIT Bit Fields */
519 #define ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK      0x1Fu
520 #define ADC_TIMER_UNIT_CORE_TIMER_UNIT_SHIFT     0
521 #define ADC_TIMER_UNIT_CORE_TIMER_UNIT(x)        (((uint32_t)(((uint32_t)(x))<<ADC_TIMER_UNIT_CORE_TIMER_UNIT_SHIFT))&ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK)
522 #define ADC_TIMER_UNIT_PRE_DIV_MASK              0xE0000000u
523 #define ADC_TIMER_UNIT_PRE_DIV_SHIFT             29
524 #define ADC_TIMER_UNIT_PRE_DIV(x)                (((uint32_t)(((uint32_t)(x))<<ADC_TIMER_UNIT_PRE_DIV_SHIFT))&ADC_TIMER_UNIT_PRE_DIV_MASK)
525 /* DMA_FIFO Bit Fields */
526 #define ADC_DMA_FIFO_DMA_WM_LVL_MASK             0x1Fu
527 #define ADC_DMA_FIFO_DMA_WM_LVL_SHIFT            0
528 #define ADC_DMA_FIFO_DMA_WM_LVL(x)               (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DMA_WM_LVL_SHIFT))&ADC_DMA_FIFO_DMA_WM_LVL_MASK)
529 #define ADC_DMA_FIFO_DMA_CH_SEL_MASK             0x60u
530 #define ADC_DMA_FIFO_DMA_CH_SEL_SHIFT            5
531 #define ADC_DMA_FIFO_DMA_CH_SEL(x)               (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DMA_CH_SEL_SHIFT))&ADC_DMA_FIFO_DMA_CH_SEL_MASK)
532 #define ADC_DMA_FIFO_DMA_EN_MASK                 0x80u
533 #define ADC_DMA_FIFO_DMA_EN_SHIFT                7
534 #define ADC_DMA_FIFO_DMA_FIFO_EN_MASK            0x100u
535 #define ADC_DMA_FIFO_DMA_FIFO_EN_SHIFT           8
536 #define ADC_DMA_FIFO_DMA_RST_MASK                0x200u
537 #define ADC_DMA_FIFO_DMA_RST_SHIFT               9
538 /* FIFO_STATUS Bit Fields */
539 #define ADC_FIFO_STATUS_FIFO_ENTRIES_MASK        0x3Fu
540 #define ADC_FIFO_STATUS_FIFO_ENTRIES_SHIFT       0
541 #define ADC_FIFO_STATUS_FIFO_ENTRIES(x)          (((uint32_t)(((uint32_t)(x))<<ADC_FIFO_STATUS_FIFO_ENTRIES_SHIFT))&ADC_FIFO_STATUS_FIFO_ENTRIES_MASK)
542 #define ADC_FIFO_STATUS_FIFO_EMPTY_MASK          0x100u
543 #define ADC_FIFO_STATUS_FIFO_EMPTY_SHIFT         8
544 #define ADC_FIFO_STATUS_FIFO_FULL_MASK           0x200u
545 #define ADC_FIFO_STATUS_FIFO_FULL_SHIFT          9
546 /* INT_SIG_EN Bit Fields */
547 #define ADC_INT_SIG_EN_CHA_CMP_INT_SIG_EN_MASK   0x1u
548 #define ADC_INT_SIG_EN_CHA_CMP_INT_SIG_EN_SHIFT  0
549 #define ADC_INT_SIG_EN_CHB_CMP_INT_SIG_EN_MASK   0x2u
550 #define ADC_INT_SIG_EN_CHB_CMP_INT_SIG_EN_SHIFT  1
551 #define ADC_INT_SIG_EN_CHC_CMP_INT_SIG_EN_MASK   0x4u
552 #define ADC_INT_SIG_EN_CHC_CMP_INT_SIG_EN_SHIFT  2
553 #define ADC_INT_SIG_EN_CHD_CMP_INT_SIG_EN_MASK   0x8u
554 #define ADC_INT_SIG_EN_CHD_CMP_INT_SIG_EN_SHIFT  3
555 #define ADC_INT_SIG_EN_DMA_REACH_WM_INT_SIG_EN_MASK 0x20u
556 #define ADC_INT_SIG_EN_DMA_REACH_WM_INT_SIG_EN_SHIFT 5
557 #define ADC_INT_SIG_EN_FIFO_UNDERRUN_INT_SIG_EN_MASK 0x40u
558 #define ADC_INT_SIG_EN_FIFO_UNDERRUN_INT_SIG_EN_SHIFT 6
559 #define ADC_INT_SIG_EN_FIFO_OVRRUN_INT_SIG_EN_MASK 0x80u
560 #define ADC_INT_SIG_EN_FIFO_OVRRUN_INT_SIG_EN_SHIFT 7
561 #define ADC_INT_SIG_EN_CHA_COV_INT_SIG_EN_MASK   0x100u
562 #define ADC_INT_SIG_EN_CHA_COV_INT_SIG_EN_SHIFT  8
563 #define ADC_INT_SIG_EN_CHB_COV_INT_SIG_EN_MASK   0x200u
564 #define ADC_INT_SIG_EN_CHB_COV_INT_SIG_EN_SHIFT  9
565 #define ADC_INT_SIG_EN_CHC_COV_INT_SIG_EN_MASK   0x400u
566 #define ADC_INT_SIG_EN_CHC_COV_INT_SIG_EN_SHIFT  10
567 #define ADC_INT_SIG_EN_CHD_COV_INT_SIG_EN_MASK   0x800u
568 #define ADC_INT_SIG_EN_CHD_COV_INT_SIG_EN_SHIFT  11
569 #define ADC_INT_SIG_EN_SW_CH_COV_INT_SIG_EN_MASK 0x1000u
570 #define ADC_INT_SIG_EN_SW_CH_COV_INT_SIG_EN_SHIFT 12
571 #define ADC_INT_SIG_EN_CHA_COV_TO_INT_SIG_EN_MASK 0x10000u
572 #define ADC_INT_SIG_EN_CHA_COV_TO_INT_SIG_EN_SHIFT 16
573 #define ADC_INT_SIG_EN_CHB_COV_TO_INT_SIG_EN_MASK 0x20000u
574 #define ADC_INT_SIG_EN_CHB_COV_TO_INT_SIG_EN_SHIFT 17
575 #define ADC_INT_SIG_EN_CHC_COV_TO_INT_SIG_EN_MASK 0x40000u
576 #define ADC_INT_SIG_EN_CHC_COV_TO_INT_SIG_EN_SHIFT 18
577 #define ADC_INT_SIG_EN_CHD_COV_TO_INT_SIG_EN_MASK 0x80000u
578 #define ADC_INT_SIG_EN_CHD_COV_TO_INT_SIG_EN_SHIFT 19
579 #define ADC_INT_SIG_EN_SW_CH_COV_TO_INT_SIG_EN_MASK 0x100000u
580 #define ADC_INT_SIG_EN_SW_CH_COV_TO_INT_SIG_EN_SHIFT 20
581 #define ADC_INT_SIG_EN_LAST_FIFO_DATA_READ_SIG_EN_MASK 0x200000u
582 #define ADC_INT_SIG_EN_LAST_FIFO_DATA_READ_SIG_EN_SHIFT 21
583 /* INT_EN Bit Fields */
584 #define ADC_INT_EN_CHA_CMP_INT_EN_MASK           0x1u
585 #define ADC_INT_EN_CHA_CMP_INT_EN_SHIFT          0
586 #define ADC_INT_EN_CHB_CMP_INT_EN_MASK           0x2u
587 #define ADC_INT_EN_CHB_CMP_INT_EN_SHIFT          1
588 #define ADC_INT_EN_CHC_CMP_INT_EN_MASK           0x4u
589 #define ADC_INT_EN_CHC_CMP_INT_EN_SHIFT          2
590 #define ADC_INT_EN_CHD_CMP_INT_EN_MASK           0x8u
591 #define ADC_INT_EN_CHD_CMP_INT_EN_SHIFT          3
592 #define ADC_INT_EN_DMA_REACH_WM_INT_EN_MASK      0x20u
593 #define ADC_INT_EN_DMA_REACH_WM_INT_EN_SHIFT     5
594 #define ADC_INT_EN_FIFO_UNDERRUN_INT_EN_MASK     0x40u
595 #define ADC_INT_EN_FIFO_UNDERRUN_INT_EN_SHIFT    6
596 #define ADC_INT_EN_FIFO_OVERRUN_INT_EN_MASK      0x80u
597 #define ADC_INT_EN_FIFO_OVERRUN_INT_EN_SHIFT     7
598 #define ADC_INT_EN_CHA_COV_INT_EN_MASK           0x100u
599 #define ADC_INT_EN_CHA_COV_INT_EN_SHIFT          8
600 #define ADC_INT_EN_CHB_COV_INT_EN_MASK           0x200u
601 #define ADC_INT_EN_CHB_COV_INT_EN_SHIFT          9
602 #define ADC_INT_EN_CHC_COV_INT_EN_MASK           0x400u
603 #define ADC_INT_EN_CHC_COV_INT_EN_SHIFT          10
604 #define ADC_INT_EN_CHD_COV_INT_EN_MASK           0x800u
605 #define ADC_INT_EN_CHD_COV_INT_EN_SHIFT          11
606 #define ADC_INT_EN_SW_CH_COV_INT_EN_MASK         0x1000u
607 #define ADC_INT_EN_SW_CH_COV_INT_EN_SHIFT        12
608 #define ADC_INT_EN_CHA_COV_TO_INT_EN_MASK        0x10000u
609 #define ADC_INT_EN_CHA_COV_TO_INT_EN_SHIFT       16
610 #define ADC_INT_EN_CHB_COV_TO_INT_EN_MASK        0x20000u
611 #define ADC_INT_EN_CHB_COV_TO_INT_EN_SHIFT       17
612 #define ADC_INT_EN_CHC_COV_TO_INT_EN_MASK        0x40000u
613 #define ADC_INT_EN_CHC_COV_TO_INT_EN_SHIFT       18
614 #define ADC_INT_EN_CHD_COV_TO_INT_EN_MASK        0x80000u
615 #define ADC_INT_EN_CHD_COV_TO_INT_EN_SHIFT       19
616 #define ADC_INT_EN_SW_CH_COV_TO_INT_EN_MASK      0x100000u
617 #define ADC_INT_EN_SW_CH_COV_TO_INT_EN_SHIFT     20
618 #define ADC_INT_EN_LAST_FIFO_DATA_READ_EN_MASK   0x200000u
619 #define ADC_INT_EN_LAST_FIFO_DATA_READ_EN_SHIFT  21
620 /* INT_STATUS Bit Fields */
621 #define ADC_INT_STATUS_CHA_CMP_MASK              0x1u
622 #define ADC_INT_STATUS_CHA_CMP_SHIFT             0
623 #define ADC_INT_STATUS_CHB_CMP_MASK              0x2u
624 #define ADC_INT_STATUS_CHB_CMP_SHIFT             1
625 #define ADC_INT_STATUS_CHC_CMP_MASK              0x4u
626 #define ADC_INT_STATUS_CHC_CMP_SHIFT             2
627 #define ADC_INT_STATUS_CHD_CMP_MASK              0x8u
628 #define ADC_INT_STATUS_CHD_CMP_SHIFT             3
629 #define ADC_INT_STATUS_DMA_REACH_WM_MASK         0x20u
630 #define ADC_INT_STATUS_DMA_REACH_WM_SHIFT        5
631 #define ADC_INT_STATUS_FIFO_UNDERRUN_MASK        0x40u
632 #define ADC_INT_STATUS_FIFO_UNDERRUN_SHIFT       6
633 #define ADC_INT_STATUS_FIFO_OVERRUN_MASK         0x80u
634 #define ADC_INT_STATUS_FIFO_OVERRUN_SHIFT        7
635 #define ADC_INT_STATUS_CHA_COV_MASK              0x100u
636 #define ADC_INT_STATUS_CHA_COV_SHIFT             8
637 #define ADC_INT_STATUS_CHB_COV_MASK              0x200u
638 #define ADC_INT_STATUS_CHB_COV_SHIFT             9
639 #define ADC_INT_STATUS_CHC_COV_MASK              0x400u
640 #define ADC_INT_STATUS_CHC_COV_SHIFT             10
641 #define ADC_INT_STATUS_CHD_COV_MASK              0x800u
642 #define ADC_INT_STATUS_CHD_COV_SHIFT             11
643 #define ADC_INT_STATUS_SW_CH_COV_MASK            0x1000u
644 #define ADC_INT_STATUS_SW_CH_COV_SHIFT           12
645 #define ADC_INT_STATUS_CHA_COV_TO_MASK           0x10000u
646 #define ADC_INT_STATUS_CHA_COV_TO_SHIFT          16
647 #define ADC_INT_STATUS_CHB_COV_TO_MASK           0x20000u
648 #define ADC_INT_STATUS_CHB_COV_TO_SHIFT          17
649 #define ADC_INT_STATUS_CHC_COV_TO_MASK           0x40000u
650 #define ADC_INT_STATUS_CHC_COV_TO_SHIFT          18
651 #define ADC_INT_STATUS_CHD_COV_TO_MASK           0x80000u
652 #define ADC_INT_STATUS_CHD_COV_TO_SHIFT          19
653 #define ADC_INT_STATUS_SW_CH_COV_TO_MASK         0x100000u
654 #define ADC_INT_STATUS_SW_CH_COV_TO_SHIFT        20
655 #define ADC_INT_STATUS_LAST_FIFO_DATA_READ_MASK  0x200000u
656 #define ADC_INT_STATUS_LAST_FIFO_DATA_READ_SHIFT 21
657 /* CHA_B_CNV_RSLT Bit Fields */
658 #define ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK     0xFFFu
659 #define ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_SHIFT    0
660 #define ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT(x)       (((uint32_t)(((uint32_t)(x))<<ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_SHIFT))&ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK)
661 #define ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_MASK     0xFFF0000u
662 #define ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT    16
663 #define ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT(x)       (((uint32_t)(((uint32_t)(x))<<ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT))&ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_MASK)
664 /* CHC_D_CNV_RSLT Bit Fields */
665 #define ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK     0xFFFu
666 #define ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_SHIFT    0
667 #define ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT(x)       (((uint32_t)(((uint32_t)(x))<<ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_SHIFT))&ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK)
668 #define ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_MASK     0xFFF0000u
669 #define ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT    16
670 #define ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT(x)       (((uint32_t)(((uint32_t)(x))<<ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT))&ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_MASK)
671 /* CH_SW_CNV_RSLT Bit Fields */
672 #define ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK   0xFFFu
673 #define ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_SHIFT  0
674 #define ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT(x)     (((uint32_t)(((uint32_t)(x))<<ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_SHIFT))&ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK)
675 /* DMA_FIFO_DAT Bit Fields */
676 #define ADC_DMA_FIFO_DAT_DMA_FIFO_0_MASK         0xFFFu
677 #define ADC_DMA_FIFO_DAT_DMA_FIFO_0_SHIFT        0
678 #define ADC_DMA_FIFO_DAT_DMA_FIFO_0(x)           (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DMA_FIFO_0_SHIFT))&ADC_DMA_FIFO_DAT_DMA_FIFO_0_MASK)
679 #define ADC_DMA_FIFO_DAT_DAT2_FLAG_MASK          0xC000u
680 #define ADC_DMA_FIFO_DAT_DAT2_FLAG_SHIFT         14
681 #define ADC_DMA_FIFO_DAT_DAT2_FLAG(x)            (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DAT2_FLAG_SHIFT))&ADC_DMA_FIFO_DAT_DAT2_FLAG_MASK)
682 #define ADC_DMA_FIFO_DAT_DMA_FIFO_1_MASK         0xFFF0000u
683 #define ADC_DMA_FIFO_DAT_DMA_FIFO_1_SHIFT        16
684 #define ADC_DMA_FIFO_DAT_DMA_FIFO_1(x)           (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DMA_FIFO_1_SHIFT))&ADC_DMA_FIFO_DAT_DMA_FIFO_1_MASK)
685 #define ADC_DMA_FIFO_DAT_DAT1_FLAG_MASK          0xC0000000u
686 #define ADC_DMA_FIFO_DAT_DAT1_FLAG_SHIFT         30
687 #define ADC_DMA_FIFO_DAT_DAT1_FLAG(x)            (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DAT1_FLAG_SHIFT))&ADC_DMA_FIFO_DAT_DAT1_FLAG_MASK)
688 /* ADC_CFG Bit Fields */
689 #define ADC_ADC_CFG_ADC_EN_MASK                  0x1u
690 #define ADC_ADC_CFG_ADC_EN_SHIFT                 0
691 #define ADC_ADC_CFG_ADC_PD_MASK                  0x2u
692 #define ADC_ADC_CFG_ADC_PD_SHIFT                 1
693 #define ADC_ADC_CFG_ADC_PD_OK_MASK               0x80u
694 #define ADC_ADC_CFG_ADC_PD_OK_SHIFT              7
695 #define ADC_ADC_CFG_ADC_CLK_DOWN_MASK            0x80000000u
696 #define ADC_ADC_CFG_ADC_CLK_DOWN_SHIFT           31
697 
698 /*!
699  * @}
700  */ /* end of group ADC_Register_Masks */
701 
702 /* ADC - Peripheral instance base addresses */
703 /** Peripheral ADC1 base address */
704 #define ADC1_BASE                                (0x30610000u)
705 /** Peripheral ADC1 base pointer */
706 #define ADC1                                     ((ADC_Type *)ADC1_BASE)
707 #define ADC1_BASE_PTR                            (ADC1)
708 /** Peripheral ADC2 base address */
709 #define ADC2_BASE                                (0x30620000u)
710 /** Peripheral ADC2 base pointer */
711 #define ADC2                                     ((ADC_Type *)ADC2_BASE)
712 #define ADC2_BASE_PTR                            (ADC2)
713 /** Array initializer of ADC peripheral base addresses */
714 #define ADC_BASE_ADDRS                           { ADC1_BASE, ADC2_BASE }
715 /** Array initializer of ADC peripheral base pointers */
716 #define ADC_BASE_PTRS                            { ADC1, ADC2 }
717 /** Interrupt vectors for the ADC peripheral type */
718 #define ADC_IRQS                                 { ADC1_IRQn, ADC2_IRQn }
719 /* ----------------------------------------------------------------------------
720    -- ADC - Register accessor macros
721    ---------------------------------------------------------------------------- */
722 
723 /*!
724  * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
725  * @{
726  */
727 
728 
729 /* ADC - Register instance definitions */
730 /* ADC1 */
731 #define ADC1_CH_A_CFG1                           ADC_CH_A_CFG1_REG(ADC1_BASE_PTR)
732 #define ADC1_CH_A_CFG2                           ADC_CH_A_CFG2_REG(ADC1_BASE_PTR)
733 #define ADC1_CH_B_CFG1                           ADC_CH_B_CFG1_REG(ADC1_BASE_PTR)
734 #define ADC1_CH_B_CFG2                           ADC_CH_B_CFG2_REG(ADC1_BASE_PTR)
735 #define ADC1_CH_C_CFG1                           ADC_CH_C_CFG1_REG(ADC1_BASE_PTR)
736 #define ADC1_CH_C_CFG2                           ADC_CH_C_CFG2_REG(ADC1_BASE_PTR)
737 #define ADC1_CH_D_CFG1                           ADC_CH_D_CFG1_REG(ADC1_BASE_PTR)
738 #define ADC1_CH_D_CFG2                           ADC_CH_D_CFG2_REG(ADC1_BASE_PTR)
739 #define ADC1_CH_SW_CFG                           ADC_CH_SW_CFG_REG(ADC1_BASE_PTR)
740 #define ADC1_TIMER_UNIT                          ADC_TIMER_UNIT_REG(ADC1_BASE_PTR)
741 #define ADC1_DMA_FIFO                            ADC_DMA_FIFO_REG(ADC1_BASE_PTR)
742 #define ADC1_FIFO_STATUS                         ADC_FIFO_STATUS_REG(ADC1_BASE_PTR)
743 #define ADC1_INT_SIG_EN                          ADC_INT_SIG_EN_REG(ADC1_BASE_PTR)
744 #define ADC1_INT_EN                              ADC_INT_EN_REG(ADC1_BASE_PTR)
745 #define ADC1_INT_STATUS                          ADC_INT_STATUS_REG(ADC1_BASE_PTR)
746 #define ADC1_CHA_B_CNV_RSLT                      ADC_CHA_B_CNV_RSLT_REG(ADC1_BASE_PTR)
747 #define ADC1_CHC_D_CNV_RSLT                      ADC_CHC_D_CNV_RSLT_REG(ADC1_BASE_PTR)
748 #define ADC1_CH_SW_CNV_RSLT                      ADC_CH_SW_CNV_RSLT_REG(ADC1_BASE_PTR)
749 #define ADC1_DMA_FIFO_DAT                        ADC_DMA_FIFO_DAT_REG(ADC1_BASE_PTR)
750 #define ADC1_ADC_CFG                             ADC_ADC_CFG_REG(ADC1_BASE_PTR)
751 /* ADC2 */
752 #define ADC2_CH_A_CFG1                           ADC_CH_A_CFG1_REG(ADC2_BASE_PTR)
753 #define ADC2_CH_A_CFG2                           ADC_CH_A_CFG2_REG(ADC2_BASE_PTR)
754 #define ADC2_CH_B_CFG1                           ADC_CH_B_CFG1_REG(ADC2_BASE_PTR)
755 #define ADC2_CH_B_CFG2                           ADC_CH_B_CFG2_REG(ADC2_BASE_PTR)
756 #define ADC2_CH_C_CFG1                           ADC_CH_C_CFG1_REG(ADC2_BASE_PTR)
757 #define ADC2_CH_C_CFG2                           ADC_CH_C_CFG2_REG(ADC2_BASE_PTR)
758 #define ADC2_CH_D_CFG1                           ADC_CH_D_CFG1_REG(ADC2_BASE_PTR)
759 #define ADC2_CH_D_CFG2                           ADC_CH_D_CFG2_REG(ADC2_BASE_PTR)
760 #define ADC2_CH_SW_CFG                           ADC_CH_SW_CFG_REG(ADC2_BASE_PTR)
761 #define ADC2_TIMER_UNIT                          ADC_TIMER_UNIT_REG(ADC2_BASE_PTR)
762 #define ADC2_DMA_FIFO                            ADC_DMA_FIFO_REG(ADC2_BASE_PTR)
763 #define ADC2_FIFO_STATUS                         ADC_FIFO_STATUS_REG(ADC2_BASE_PTR)
764 #define ADC2_INT_SIG_EN                          ADC_INT_SIG_EN_REG(ADC2_BASE_PTR)
765 #define ADC2_INT_EN                              ADC_INT_EN_REG(ADC2_BASE_PTR)
766 #define ADC2_INT_STATUS                          ADC_INT_STATUS_REG(ADC2_BASE_PTR)
767 #define ADC2_CHA_B_CNV_RSLT                      ADC_CHA_B_CNV_RSLT_REG(ADC2_BASE_PTR)
768 #define ADC2_CHC_D_CNV_RSLT                      ADC_CHC_D_CNV_RSLT_REG(ADC2_BASE_PTR)
769 #define ADC2_CH_SW_CNV_RSLT                      ADC_CH_SW_CNV_RSLT_REG(ADC2_BASE_PTR)
770 #define ADC2_DMA_FIFO_DAT                        ADC_DMA_FIFO_DAT_REG(ADC2_BASE_PTR)
771 #define ADC2_ADC_CFG                             ADC_ADC_CFG_REG(ADC2_BASE_PTR)
772 /*!
773  * @}
774  */ /* end of group ADC_Register_Accessor_Macros */
775 
776 
777 /*!
778  * @}
779  */ /* end of group ADC_Peripheral */
780 
781 /* ----------------------------------------------------------------------------
782    -- APBH Peripheral Access Layer
783    ---------------------------------------------------------------------------- */
784 
785 /*!
786  * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
787  * @{
788  */
789 
790 /** APBH - Register Layout Typedef */
791 typedef struct {
792   __IO  uint32_t CTRL0;                                  /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
793   __IO  uint32_t CTRL0_SET;                              /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
794   __IO  uint32_t CTRL0_CLR;                              /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
795   __IO  uint32_t CTRL0_TOG;                              /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
796   __IO  uint32_t CTRL1;                                  /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
797   __IO  uint32_t CTRL1_SET;                              /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
798   __IO  uint32_t CTRL1_CLR;                              /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
799   __IO  uint32_t CTRL1_TOG;                              /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
800   __IO  uint32_t CTRL2;                                  /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
801   __IO  uint32_t CTRL2_SET;                              /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
802   __IO  uint32_t CTRL2_CLR;                              /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
803   __IO  uint32_t CTRL2_TOG;                              /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
804   __IO  uint32_t CHANNEL_CTRL;                           /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
805   __IO  uint32_t CHANNEL_CTRL_SET;                       /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
806   __IO  uint32_t CHANNEL_CTRL_CLR;                       /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
807   __IO  uint32_t CHANNEL_CTRL_TOG;                       /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
808   __IO  uint32_t DEVSEL;                                 /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
809   uint8_t RESERVED_0[12];
810   __IO  uint32_t DMA_BURST_SIZE;                         /**< AHB to APBH DMA burst size, offset: 0x50 */
811   uint8_t RESERVED_1[12];
812   __IO  uint32_t DEBUG;                                  /**< AHB to APBH DMA Debug Register, offset: 0x60 */
813   uint8_t RESERVED_2[156];
814   struct {                                         /* offset: 0x100, array step: 0x70 */
815   __IO    uint32_t CH_CURCMDAR;                            /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
816     uint8_t RESERVED_0[12];
817   __IO    uint32_t CH_NXTCMDAR;                            /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
818     uint8_t RESERVED_1[12];
819   __IO    uint32_t CH_CMD;                                 /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
820     uint8_t RESERVED_2[12];
821   __IO    uint32_t CH_BAR;                                 /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
822     uint8_t RESERVED_3[12];
823   __IO    uint32_t CH_SEMA;                                /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
824     uint8_t RESERVED_4[12];
825   __IO    uint32_t CH_DEBUG1;                              /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
826     uint8_t RESERVED_5[12];
827   __IO    uint32_t CH_DEBUG2;                              /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
828     uint8_t RESERVED_6[12];
829  } CH[16];
830   __IO  uint32_t VERSION;                                /**< APBH Bridge Version Register, offset: 0x800 */
831 } APBH_Type, *APBH_MemMapPtr;
832 /* ----------------------------------------------------------------------------
833    -- APBH - Register accessor macros
834    ---------------------------------------------------------------------------- */
835 
836 /*!
837  * @addtogroup APBH_Register_Accessor_Macros APBH - Register accessor macros
838  * @{
839  */
840 
841 
842 /* APBH - Register accessors */
843 #define APBH_CTRL0_REG(base)                     ((base)->CTRL0)
844 #define APBH_CTRL0_SET_REG(base)                 ((base)->CTRL0_SET)
845 #define APBH_CTRL0_CLR_REG(base)                 ((base)->CTRL0_CLR)
846 #define APBH_CTRL0_TOG_REG(base)                 ((base)->CTRL0_TOG)
847 #define APBH_CTRL1_REG(base)                     ((base)->CTRL1)
848 #define APBH_CTRL1_SET_REG(base)                 ((base)->CTRL1_SET)
849 #define APBH_CTRL1_CLR_REG(base)                 ((base)->CTRL1_CLR)
850 #define APBH_CTRL1_TOG_REG(base)                 ((base)->CTRL1_TOG)
851 #define APBH_CTRL2_REG(base)                     ((base)->CTRL2)
852 #define APBH_CTRL2_SET_REG(base)                 ((base)->CTRL2_SET)
853 #define APBH_CTRL2_CLR_REG(base)                 ((base)->CTRL2_CLR)
854 #define APBH_CTRL2_TOG_REG(base)                 ((base)->CTRL2_TOG)
855 #define APBH_CHANNEL_CTRL_REG(base)              ((base)->CHANNEL_CTRL)
856 #define APBH_CHANNEL_CTRL_SET_REG(base)          ((base)->CHANNEL_CTRL_SET)
857 #define APBH_CHANNEL_CTRL_CLR_REG(base)          ((base)->CHANNEL_CTRL_CLR)
858 #define APBH_CHANNEL_CTRL_TOG_REG(base)          ((base)->CHANNEL_CTRL_TOG)
859 #define APBH_DEVSEL_REG(base)                    ((base)->DEVSEL)
860 #define APBH_DMA_BURST_SIZE_REG(base)            ((base)->DMA_BURST_SIZE)
861 #define APBH_DEBUG_REG(base)                     ((base)->DEBUG)
862 #define APBH_CH_CURCMDAR_REG(base,index)         ((base)->CH[index].CH_CURCMDAR)
863 #define APBH_CH_NXTCMDAR_REG(base,index)         ((base)->CH[index].CH_NXTCMDAR)
864 #define APBH_CH_CMD_REG(base,index)              ((base)->CH[index].CH_CMD)
865 #define APBH_CH_BAR_REG(base,index)              ((base)->CH[index].CH_BAR)
866 #define APBH_CH_SEMA_REG(base,index)             ((base)->CH[index].CH_SEMA)
867 #define APBH_CH_DEBUG1_REG(base,index)           ((base)->CH[index].CH_DEBUG1)
868 #define APBH_CH_DEBUG2_REG(base,index)           ((base)->CH[index].CH_DEBUG2)
869 #define APBH_VERSION_REG(base)                   ((base)->VERSION)
870 
871 /*!
872  * @}
873  */ /* end of group APBH_Register_Accessor_Macros */
874 /* ----------------------------------------------------------------------------
875    -- APBH Register Masks
876    ---------------------------------------------------------------------------- */
877 
878 /*!
879  * @addtogroup APBH_Register_Masks APBH Register Masks
880  * @{
881  */
882 
883 /* CTRL0 Bit Fields */
884 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK          0xFFFFu
885 #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT         0
886 #define APBH_CTRL0_CLKGATE_CHANNEL(x)            (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_CLKGATE_CHANNEL_MASK)
887 #define APBH_CTRL0_RSVD0_MASK                    0xFFF0000u
888 #define APBH_CTRL0_RSVD0_SHIFT                   16
889 #define APBH_CTRL0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_RSVD0_SHIFT))&APBH_CTRL0_RSVD0_MASK)
890 #define APBH_CTRL0_APB_BURST_EN_MASK             0x10000000u
891 #define APBH_CTRL0_APB_BURST_EN_SHIFT            28
892 #define APBH_CTRL0_AHB_BURST8_EN_MASK            0x20000000u
893 #define APBH_CTRL0_AHB_BURST8_EN_SHIFT           29
894 #define APBH_CTRL0_CLKGATE_MASK                  0x40000000u
895 #define APBH_CTRL0_CLKGATE_SHIFT                 30
896 #define APBH_CTRL0_SFTRST_MASK                   0x80000000u
897 #define APBH_CTRL0_SFTRST_SHIFT                  31
898 /* CTRL0_SET Bit Fields */
899 #define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK      0xFFFFu
900 #define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT     0
901 #define APBH_CTRL0_SET_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
902 #define APBH_CTRL0_SET_RSVD0_MASK                0xFFF0000u
903 #define APBH_CTRL0_SET_RSVD0_SHIFT               16
904 #define APBH_CTRL0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_SET_RSVD0_SHIFT))&APBH_CTRL0_SET_RSVD0_MASK)
905 #define APBH_CTRL0_SET_APB_BURST_EN_MASK         0x10000000u
906 #define APBH_CTRL0_SET_APB_BURST_EN_SHIFT        28
907 #define APBH_CTRL0_SET_AHB_BURST8_EN_MASK        0x20000000u
908 #define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT       29
909 #define APBH_CTRL0_SET_CLKGATE_MASK              0x40000000u
910 #define APBH_CTRL0_SET_CLKGATE_SHIFT             30
911 #define APBH_CTRL0_SET_SFTRST_MASK               0x80000000u
912 #define APBH_CTRL0_SET_SFTRST_SHIFT              31
913 /* CTRL0_CLR Bit Fields */
914 #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK      0xFFFFu
915 #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT     0
916 #define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
917 #define APBH_CTRL0_CLR_RSVD0_MASK                0xFFF0000u
918 #define APBH_CTRL0_CLR_RSVD0_SHIFT               16
919 #define APBH_CTRL0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_CLR_RSVD0_SHIFT))&APBH_CTRL0_CLR_RSVD0_MASK)
920 #define APBH_CTRL0_CLR_APB_BURST_EN_MASK         0x10000000u
921 #define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT        28
922 #define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK        0x20000000u
923 #define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT       29
924 #define APBH_CTRL0_CLR_CLKGATE_MASK              0x40000000u
925 #define APBH_CTRL0_CLR_CLKGATE_SHIFT             30
926 #define APBH_CTRL0_CLR_SFTRST_MASK               0x80000000u
927 #define APBH_CTRL0_CLR_SFTRST_SHIFT              31
928 /* CTRL0_TOG Bit Fields */
929 #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK      0xFFFFu
930 #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT     0
931 #define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
932 #define APBH_CTRL0_TOG_RSVD0_MASK                0xFFF0000u
933 #define APBH_CTRL0_TOG_RSVD0_SHIFT               16
934 #define APBH_CTRL0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_TOG_RSVD0_SHIFT))&APBH_CTRL0_TOG_RSVD0_MASK)
935 #define APBH_CTRL0_TOG_APB_BURST_EN_MASK         0x10000000u
936 #define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT        28
937 #define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK        0x20000000u
938 #define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT       29
939 #define APBH_CTRL0_TOG_CLKGATE_MASK              0x40000000u
940 #define APBH_CTRL0_TOG_CLKGATE_SHIFT             30
941 #define APBH_CTRL0_TOG_SFTRST_MASK               0x80000000u
942 #define APBH_CTRL0_TOG_SFTRST_SHIFT              31
943 /* CTRL1 Bit Fields */
944 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK         0x1u
945 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT        0
946 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK         0x2u
947 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT        1
948 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK         0x4u
949 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT        2
950 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK         0x8u
951 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT        3
952 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK         0x10u
953 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT        4
954 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK         0x20u
955 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT        5
956 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK         0x40u
957 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT        6
958 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK         0x80u
959 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT        7
960 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK         0x100u
961 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT        8
962 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK         0x200u
963 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT        9
964 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK        0x400u
965 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT       10
966 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK        0x800u
967 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT       11
968 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK        0x1000u
969 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT       12
970 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK        0x2000u
971 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT       13
972 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK        0x4000u
973 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT       14
974 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK        0x8000u
975 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT       15
976 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK      0x10000u
977 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT     16
978 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK      0x20000u
979 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT     17
980 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK      0x40000u
981 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT     18
982 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK      0x80000u
983 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT     19
984 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK      0x100000u
985 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT     20
986 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK      0x200000u
987 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT     21
988 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK      0x400000u
989 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT     22
990 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK      0x800000u
991 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT     23
992 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK      0x1000000u
993 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT     24
994 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK      0x2000000u
995 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT     25
996 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK     0x4000000u
997 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT    26
998 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK     0x8000000u
999 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT    27
1000 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK     0x10000000u
1001 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT    28
1002 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK     0x20000000u
1003 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT    29
1004 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK     0x40000000u
1005 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT    30
1006 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK     0x80000000u
1007 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT    31
1008 /* CTRL1_SET Bit Fields */
1009 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK     0x1u
1010 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT    0
1011 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK     0x2u
1012 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT    1
1013 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK     0x4u
1014 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT    2
1015 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK     0x8u
1016 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT    3
1017 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK     0x10u
1018 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT    4
1019 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK     0x20u
1020 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT    5
1021 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK     0x40u
1022 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT    6
1023 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK     0x80u
1024 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT    7
1025 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK     0x100u
1026 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT    8
1027 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK     0x200u
1028 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT    9
1029 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK    0x400u
1030 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT   10
1031 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK    0x800u
1032 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT   11
1033 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK    0x1000u
1034 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT   12
1035 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK    0x2000u
1036 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT   13
1037 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK    0x4000u
1038 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT   14
1039 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK    0x8000u
1040 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT   15
1041 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK  0x10000u
1042 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT 16
1043 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK  0x20000u
1044 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT 17
1045 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK  0x40000u
1046 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT 18
1047 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK  0x80000u
1048 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT 19
1049 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK  0x100000u
1050 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT 20
1051 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK  0x200000u
1052 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT 21
1053 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK  0x400000u
1054 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT 22
1055 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK  0x800000u
1056 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT 23
1057 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK  0x1000000u
1058 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT 24
1059 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK  0x2000000u
1060 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT 25
1061 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u
1062 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT 26
1063 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u
1064 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT 27
1065 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u
1066 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT 28
1067 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u
1068 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT 29
1069 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u
1070 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT 30
1071 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u
1072 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT 31
1073 /* CTRL1_CLR Bit Fields */
1074 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK     0x1u
1075 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT    0
1076 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK     0x2u
1077 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT    1
1078 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK     0x4u
1079 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT    2
1080 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK     0x8u
1081 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT    3
1082 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK     0x10u
1083 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT    4
1084 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK     0x20u
1085 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT    5
1086 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK     0x40u
1087 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT    6
1088 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK     0x80u
1089 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT    7
1090 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK     0x100u
1091 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT    8
1092 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK     0x200u
1093 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT    9
1094 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK    0x400u
1095 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT   10
1096 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK    0x800u
1097 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT   11
1098 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK    0x1000u
1099 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT   12
1100 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK    0x2000u
1101 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT   13
1102 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK    0x4000u
1103 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT   14
1104 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK    0x8000u
1105 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT   15
1106 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK  0x10000u
1107 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT 16
1108 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK  0x20000u
1109 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT 17
1110 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK  0x40000u
1111 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT 18
1112 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK  0x80000u
1113 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT 19
1114 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK  0x100000u
1115 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT 20
1116 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK  0x200000u
1117 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT 21
1118 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK  0x400000u
1119 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT 22
1120 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK  0x800000u
1121 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT 23
1122 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK  0x1000000u
1123 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT 24
1124 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK  0x2000000u
1125 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT 25
1126 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u
1127 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT 26
1128 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u
1129 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT 27
1130 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u
1131 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT 28
1132 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u
1133 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT 29
1134 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u
1135 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT 30
1136 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u
1137 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT 31
1138 /* CTRL1_TOG Bit Fields */
1139 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK     0x1u
1140 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT    0
1141 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK     0x2u
1142 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT    1
1143 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK     0x4u
1144 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT    2
1145 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK     0x8u
1146 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT    3
1147 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK     0x10u
1148 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT    4
1149 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK     0x20u
1150 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT    5
1151 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK     0x40u
1152 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT    6
1153 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK     0x80u
1154 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT    7
1155 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK     0x100u
1156 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT    8
1157 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK     0x200u
1158 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT    9
1159 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK    0x400u
1160 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT   10
1161 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK    0x800u
1162 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT   11
1163 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK    0x1000u
1164 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT   12
1165 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK    0x2000u
1166 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT   13
1167 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK    0x4000u
1168 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT   14
1169 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK    0x8000u
1170 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT   15
1171 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK  0x10000u
1172 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT 16
1173 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK  0x20000u
1174 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT 17
1175 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK  0x40000u
1176 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT 18
1177 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK  0x80000u
1178 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT 19
1179 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK  0x100000u
1180 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT 20
1181 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK  0x200000u
1182 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT 21
1183 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK  0x400000u
1184 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT 22
1185 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK  0x800000u
1186 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT 23
1187 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK  0x1000000u
1188 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT 24
1189 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK  0x2000000u
1190 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT 25
1191 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u
1192 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT 26
1193 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u
1194 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT 27
1195 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u
1196 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT 28
1197 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u
1198 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT 29
1199 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u
1200 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT 30
1201 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u
1202 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT 31
1203 /* CTRL2 Bit Fields */
1204 #define APBH_CTRL2_CH0_ERROR_IRQ_MASK            0x1u
1205 #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT           0
1206 #define APBH_CTRL2_CH1_ERROR_IRQ_MASK            0x2u
1207 #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT           1
1208 #define APBH_CTRL2_CH2_ERROR_IRQ_MASK            0x4u
1209 #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT           2
1210 #define APBH_CTRL2_CH3_ERROR_IRQ_MASK            0x8u
1211 #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT           3
1212 #define APBH_CTRL2_CH4_ERROR_IRQ_MASK            0x10u
1213 #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT           4
1214 #define APBH_CTRL2_CH5_ERROR_IRQ_MASK            0x20u
1215 #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT           5
1216 #define APBH_CTRL2_CH6_ERROR_IRQ_MASK            0x40u
1217 #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT           6
1218 #define APBH_CTRL2_CH7_ERROR_IRQ_MASK            0x80u
1219 #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT           7
1220 #define APBH_CTRL2_CH8_ERROR_IRQ_MASK            0x100u
1221 #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT           8
1222 #define APBH_CTRL2_CH9_ERROR_IRQ_MASK            0x200u
1223 #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT           9
1224 #define APBH_CTRL2_CH10_ERROR_IRQ_MASK           0x400u
1225 #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT          10
1226 #define APBH_CTRL2_CH11_ERROR_IRQ_MASK           0x800u
1227 #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT          11
1228 #define APBH_CTRL2_CH12_ERROR_IRQ_MASK           0x1000u
1229 #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT          12
1230 #define APBH_CTRL2_CH13_ERROR_IRQ_MASK           0x2000u
1231 #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT          13
1232 #define APBH_CTRL2_CH14_ERROR_IRQ_MASK           0x4000u
1233 #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT          14
1234 #define APBH_CTRL2_CH15_ERROR_IRQ_MASK           0x8000u
1235 #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT          15
1236 #define APBH_CTRL2_CH0_ERROR_STATUS_MASK         0x10000u
1237 #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT        16
1238 #define APBH_CTRL2_CH1_ERROR_STATUS_MASK         0x20000u
1239 #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT        17
1240 #define APBH_CTRL2_CH2_ERROR_STATUS_MASK         0x40000u
1241 #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT        18
1242 #define APBH_CTRL2_CH3_ERROR_STATUS_MASK         0x80000u
1243 #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT        19
1244 #define APBH_CTRL2_CH4_ERROR_STATUS_MASK         0x100000u
1245 #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT        20
1246 #define APBH_CTRL2_CH5_ERROR_STATUS_MASK         0x200000u
1247 #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT        21
1248 #define APBH_CTRL2_CH6_ERROR_STATUS_MASK         0x400000u
1249 #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT        22
1250 #define APBH_CTRL2_CH7_ERROR_STATUS_MASK         0x800000u
1251 #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT        23
1252 #define APBH_CTRL2_CH8_ERROR_STATUS_MASK         0x1000000u
1253 #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT        24
1254 #define APBH_CTRL2_CH9_ERROR_STATUS_MASK         0x2000000u
1255 #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT        25
1256 #define APBH_CTRL2_CH10_ERROR_STATUS_MASK        0x4000000u
1257 #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT       26
1258 #define APBH_CTRL2_CH11_ERROR_STATUS_MASK        0x8000000u
1259 #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT       27
1260 #define APBH_CTRL2_CH12_ERROR_STATUS_MASK        0x10000000u
1261 #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT       28
1262 #define APBH_CTRL2_CH13_ERROR_STATUS_MASK        0x20000000u
1263 #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT       29
1264 #define APBH_CTRL2_CH14_ERROR_STATUS_MASK        0x40000000u
1265 #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT       30
1266 #define APBH_CTRL2_CH15_ERROR_STATUS_MASK        0x80000000u
1267 #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT       31
1268 /* CTRL2_SET Bit Fields */
1269 #define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK        0x1u
1270 #define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT       0
1271 #define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK        0x2u
1272 #define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT       1
1273 #define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK        0x4u
1274 #define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT       2
1275 #define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK        0x8u
1276 #define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT       3
1277 #define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK        0x10u
1278 #define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT       4
1279 #define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK        0x20u
1280 #define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT       5
1281 #define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK        0x40u
1282 #define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT       6
1283 #define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK        0x80u
1284 #define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT       7
1285 #define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK        0x100u
1286 #define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT       8
1287 #define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK        0x200u
1288 #define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT       9
1289 #define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK       0x400u
1290 #define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT      10
1291 #define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK       0x800u
1292 #define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT      11
1293 #define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK       0x1000u
1294 #define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT      12
1295 #define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK       0x2000u
1296 #define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT      13
1297 #define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK       0x4000u
1298 #define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT      14
1299 #define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK       0x8000u
1300 #define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT      15
1301 #define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK     0x10000u
1302 #define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT    16
1303 #define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK     0x20000u
1304 #define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT    17
1305 #define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK     0x40000u
1306 #define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT    18
1307 #define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK     0x80000u
1308 #define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT    19
1309 #define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK     0x100000u
1310 #define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT    20
1311 #define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK     0x200000u
1312 #define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT    21
1313 #define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK     0x400000u
1314 #define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT    22
1315 #define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK     0x800000u
1316 #define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT    23
1317 #define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK     0x1000000u
1318 #define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT    24
1319 #define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK     0x2000000u
1320 #define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT    25
1321 #define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK    0x4000000u
1322 #define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT   26
1323 #define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK    0x8000000u
1324 #define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT   27
1325 #define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK    0x10000000u
1326 #define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT   28
1327 #define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK    0x20000000u
1328 #define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT   29
1329 #define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK    0x40000000u
1330 #define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT   30
1331 #define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK    0x80000000u
1332 #define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT   31
1333 /* CTRL2_CLR Bit Fields */
1334 #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK        0x1u
1335 #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT       0
1336 #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK        0x2u
1337 #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT       1
1338 #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK        0x4u
1339 #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT       2
1340 #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK        0x8u
1341 #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT       3
1342 #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK        0x10u
1343 #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT       4
1344 #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK        0x20u
1345 #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT       5
1346 #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK        0x40u
1347 #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT       6
1348 #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK        0x80u
1349 #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT       7
1350 #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK        0x100u
1351 #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT       8
1352 #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK        0x200u
1353 #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT       9
1354 #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK       0x400u
1355 #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT      10
1356 #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK       0x800u
1357 #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT      11
1358 #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK       0x1000u
1359 #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT      12
1360 #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK       0x2000u
1361 #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT      13
1362 #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK       0x4000u
1363 #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT      14
1364 #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK       0x8000u
1365 #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT      15
1366 #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK     0x10000u
1367 #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT    16
1368 #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK     0x20000u
1369 #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT    17
1370 #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK     0x40000u
1371 #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT    18
1372 #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK     0x80000u
1373 #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT    19
1374 #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK     0x100000u
1375 #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT    20
1376 #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK     0x200000u
1377 #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT    21
1378 #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK     0x400000u
1379 #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT    22
1380 #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK     0x800000u
1381 #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT    23
1382 #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK     0x1000000u
1383 #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT    24
1384 #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK     0x2000000u
1385 #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT    25
1386 #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK    0x4000000u
1387 #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT   26
1388 #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK    0x8000000u
1389 #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT   27
1390 #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK    0x10000000u
1391 #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT   28
1392 #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK    0x20000000u
1393 #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT   29
1394 #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK    0x40000000u
1395 #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT   30
1396 #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK    0x80000000u
1397 #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT   31
1398 /* CTRL2_TOG Bit Fields */
1399 #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK        0x1u
1400 #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT       0
1401 #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK        0x2u
1402 #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT       1
1403 #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK        0x4u
1404 #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT       2
1405 #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK        0x8u
1406 #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT       3
1407 #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK        0x10u
1408 #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT       4
1409 #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK        0x20u
1410 #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT       5
1411 #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK        0x40u
1412 #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT       6
1413 #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK        0x80u
1414 #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT       7
1415 #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK        0x100u
1416 #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT       8
1417 #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK        0x200u
1418 #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT       9
1419 #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK       0x400u
1420 #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT      10
1421 #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK       0x800u
1422 #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT      11
1423 #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK       0x1000u
1424 #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT      12
1425 #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK       0x2000u
1426 #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT      13
1427 #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK       0x4000u
1428 #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT      14
1429 #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK       0x8000u
1430 #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT      15
1431 #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK     0x10000u
1432 #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT    16
1433 #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK     0x20000u
1434 #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT    17
1435 #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK     0x40000u
1436 #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT    18
1437 #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK     0x80000u
1438 #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT    19
1439 #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK     0x100000u
1440 #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT    20
1441 #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK     0x200000u
1442 #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT    21
1443 #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK     0x400000u
1444 #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT    22
1445 #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK     0x800000u
1446 #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT    23
1447 #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK     0x1000000u
1448 #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT    24
1449 #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK     0x2000000u
1450 #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT    25
1451 #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK    0x4000000u
1452 #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT   26
1453 #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK    0x8000000u
1454 #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT   27
1455 #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK    0x10000000u
1456 #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT   28
1457 #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK    0x20000000u
1458 #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT   29
1459 #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK    0x40000000u
1460 #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT   30
1461 #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK    0x80000000u
1462 #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT   31
1463 /* CHANNEL_CTRL Bit Fields */
1464 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK    0xFFFFu
1465 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT   0
1466 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x)      (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1467 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK     0xFFFF0000u
1468 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT    16
1469 #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x)       (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1470 /* CHANNEL_CTRL_SET Bit Fields */
1471 #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK 0xFFFFu
1472 #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT 0
1473 #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
1474 #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK 0xFFFF0000u
1475 #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT 16
1476 #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
1477 /* CHANNEL_CTRL_CLR Bit Fields */
1478 #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK 0xFFFFu
1479 #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT 0
1480 #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
1481 #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK 0xFFFF0000u
1482 #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT 16
1483 #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
1484 /* CHANNEL_CTRL_TOG Bit Fields */
1485 #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK 0xFFFFu
1486 #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT 0
1487 #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
1488 #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK 0xFFFF0000u
1489 #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT 16
1490 #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
1491 /* DEVSEL Bit Fields */
1492 #define APBH_DEVSEL_CH0_MASK                     0x3u
1493 #define APBH_DEVSEL_CH0_SHIFT                    0
1494 #define APBH_DEVSEL_CH0(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH0_SHIFT))&APBH_DEVSEL_CH0_MASK)
1495 #define APBH_DEVSEL_CH1_MASK                     0xCu
1496 #define APBH_DEVSEL_CH1_SHIFT                    2
1497 #define APBH_DEVSEL_CH1(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH1_SHIFT))&APBH_DEVSEL_CH1_MASK)
1498 #define APBH_DEVSEL_CH2_MASK                     0x30u
1499 #define APBH_DEVSEL_CH2_SHIFT                    4
1500 #define APBH_DEVSEL_CH2(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH2_SHIFT))&APBH_DEVSEL_CH2_MASK)
1501 #define APBH_DEVSEL_CH3_MASK                     0xC0u
1502 #define APBH_DEVSEL_CH3_SHIFT                    6
1503 #define APBH_DEVSEL_CH3(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH3_SHIFT))&APBH_DEVSEL_CH3_MASK)
1504 #define APBH_DEVSEL_CH4_MASK                     0x300u
1505 #define APBH_DEVSEL_CH4_SHIFT                    8
1506 #define APBH_DEVSEL_CH4(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH4_SHIFT))&APBH_DEVSEL_CH4_MASK)
1507 #define APBH_DEVSEL_CH5_MASK                     0xC00u
1508 #define APBH_DEVSEL_CH5_SHIFT                    10
1509 #define APBH_DEVSEL_CH5(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH5_SHIFT))&APBH_DEVSEL_CH5_MASK)
1510 #define APBH_DEVSEL_CH6_MASK                     0x3000u
1511 #define APBH_DEVSEL_CH6_SHIFT                    12
1512 #define APBH_DEVSEL_CH6(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH6_SHIFT))&APBH_DEVSEL_CH6_MASK)
1513 #define APBH_DEVSEL_CH7_MASK                     0xC000u
1514 #define APBH_DEVSEL_CH7_SHIFT                    14
1515 #define APBH_DEVSEL_CH7(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH7_SHIFT))&APBH_DEVSEL_CH7_MASK)
1516 #define APBH_DEVSEL_CH8_MASK                     0x30000u
1517 #define APBH_DEVSEL_CH8_SHIFT                    16
1518 #define APBH_DEVSEL_CH8(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH8_SHIFT))&APBH_DEVSEL_CH8_MASK)
1519 #define APBH_DEVSEL_CH9_MASK                     0xC0000u
1520 #define APBH_DEVSEL_CH9_SHIFT                    18
1521 #define APBH_DEVSEL_CH9(x)                       (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH9_SHIFT))&APBH_DEVSEL_CH9_MASK)
1522 #define APBH_DEVSEL_CH10_MASK                    0x300000u
1523 #define APBH_DEVSEL_CH10_SHIFT                   20
1524 #define APBH_DEVSEL_CH10(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH10_SHIFT))&APBH_DEVSEL_CH10_MASK)
1525 #define APBH_DEVSEL_CH11_MASK                    0xC00000u
1526 #define APBH_DEVSEL_CH11_SHIFT                   22
1527 #define APBH_DEVSEL_CH11(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH11_SHIFT))&APBH_DEVSEL_CH11_MASK)
1528 #define APBH_DEVSEL_CH12_MASK                    0x3000000u
1529 #define APBH_DEVSEL_CH12_SHIFT                   24
1530 #define APBH_DEVSEL_CH12(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH12_SHIFT))&APBH_DEVSEL_CH12_MASK)
1531 #define APBH_DEVSEL_CH13_MASK                    0xC000000u
1532 #define APBH_DEVSEL_CH13_SHIFT                   26
1533 #define APBH_DEVSEL_CH13(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH13_SHIFT))&APBH_DEVSEL_CH13_MASK)
1534 #define APBH_DEVSEL_CH14_MASK                    0x30000000u
1535 #define APBH_DEVSEL_CH14_SHIFT                   28
1536 #define APBH_DEVSEL_CH14(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH14_SHIFT))&APBH_DEVSEL_CH14_MASK)
1537 #define APBH_DEVSEL_CH15_MASK                    0xC0000000u
1538 #define APBH_DEVSEL_CH15_SHIFT                   30
1539 #define APBH_DEVSEL_CH15(x)                      (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH15_SHIFT))&APBH_DEVSEL_CH15_MASK)
1540 /* DMA_BURST_SIZE Bit Fields */
1541 #define APBH_DMA_BURST_SIZE_CH0_MASK             0x3u
1542 #define APBH_DMA_BURST_SIZE_CH0_SHIFT            0
1543 #define APBH_DMA_BURST_SIZE_CH0(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH0_SHIFT))&APBH_DMA_BURST_SIZE_CH0_MASK)
1544 #define APBH_DMA_BURST_SIZE_CH1_MASK             0xCu
1545 #define APBH_DMA_BURST_SIZE_CH1_SHIFT            2
1546 #define APBH_DMA_BURST_SIZE_CH1(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH1_SHIFT))&APBH_DMA_BURST_SIZE_CH1_MASK)
1547 #define APBH_DMA_BURST_SIZE_CH2_MASK             0x30u
1548 #define APBH_DMA_BURST_SIZE_CH2_SHIFT            4
1549 #define APBH_DMA_BURST_SIZE_CH2(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH2_SHIFT))&APBH_DMA_BURST_SIZE_CH2_MASK)
1550 #define APBH_DMA_BURST_SIZE_CH3_MASK             0xC0u
1551 #define APBH_DMA_BURST_SIZE_CH3_SHIFT            6
1552 #define APBH_DMA_BURST_SIZE_CH3(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH3_SHIFT))&APBH_DMA_BURST_SIZE_CH3_MASK)
1553 #define APBH_DMA_BURST_SIZE_CH4_MASK             0x300u
1554 #define APBH_DMA_BURST_SIZE_CH4_SHIFT            8
1555 #define APBH_DMA_BURST_SIZE_CH4(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH4_SHIFT))&APBH_DMA_BURST_SIZE_CH4_MASK)
1556 #define APBH_DMA_BURST_SIZE_CH5_MASK             0xC00u
1557 #define APBH_DMA_BURST_SIZE_CH5_SHIFT            10
1558 #define APBH_DMA_BURST_SIZE_CH5(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH5_SHIFT))&APBH_DMA_BURST_SIZE_CH5_MASK)
1559 #define APBH_DMA_BURST_SIZE_CH6_MASK             0x3000u
1560 #define APBH_DMA_BURST_SIZE_CH6_SHIFT            12
1561 #define APBH_DMA_BURST_SIZE_CH6(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH6_SHIFT))&APBH_DMA_BURST_SIZE_CH6_MASK)
1562 #define APBH_DMA_BURST_SIZE_CH7_MASK             0xC000u
1563 #define APBH_DMA_BURST_SIZE_CH7_SHIFT            14
1564 #define APBH_DMA_BURST_SIZE_CH7(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH7_SHIFT))&APBH_DMA_BURST_SIZE_CH7_MASK)
1565 #define APBH_DMA_BURST_SIZE_CH8_MASK             0x30000u
1566 #define APBH_DMA_BURST_SIZE_CH8_SHIFT            16
1567 #define APBH_DMA_BURST_SIZE_CH8(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH8_SHIFT))&APBH_DMA_BURST_SIZE_CH8_MASK)
1568 #define APBH_DMA_BURST_SIZE_CH9_MASK             0xC0000u
1569 #define APBH_DMA_BURST_SIZE_CH9_SHIFT            18
1570 #define APBH_DMA_BURST_SIZE_CH9(x)               (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH9_SHIFT))&APBH_DMA_BURST_SIZE_CH9_MASK)
1571 #define APBH_DMA_BURST_SIZE_CH10_MASK            0x300000u
1572 #define APBH_DMA_BURST_SIZE_CH10_SHIFT           20
1573 #define APBH_DMA_BURST_SIZE_CH10(x)              (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH10_SHIFT))&APBH_DMA_BURST_SIZE_CH10_MASK)
1574 #define APBH_DMA_BURST_SIZE_CH11_MASK            0xC00000u
1575 #define APBH_DMA_BURST_SIZE_CH11_SHIFT           22
1576 #define APBH_DMA_BURST_SIZE_CH11(x)              (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH11_SHIFT))&APBH_DMA_BURST_SIZE_CH11_MASK)
1577 #define APBH_DMA_BURST_SIZE_CH12_MASK            0x3000000u
1578 #define APBH_DMA_BURST_SIZE_CH12_SHIFT           24
1579 #define APBH_DMA_BURST_SIZE_CH12(x)              (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH12_SHIFT))&APBH_DMA_BURST_SIZE_CH12_MASK)
1580 #define APBH_DMA_BURST_SIZE_CH13_MASK            0xC000000u
1581 #define APBH_DMA_BURST_SIZE_CH13_SHIFT           26
1582 #define APBH_DMA_BURST_SIZE_CH13(x)              (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH13_SHIFT))&APBH_DMA_BURST_SIZE_CH13_MASK)
1583 #define APBH_DMA_BURST_SIZE_CH14_MASK            0x30000000u
1584 #define APBH_DMA_BURST_SIZE_CH14_SHIFT           28
1585 #define APBH_DMA_BURST_SIZE_CH14(x)              (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH14_SHIFT))&APBH_DMA_BURST_SIZE_CH14_MASK)
1586 #define APBH_DMA_BURST_SIZE_CH15_MASK            0xC0000000u
1587 #define APBH_DMA_BURST_SIZE_CH15_SHIFT           30
1588 #define APBH_DMA_BURST_SIZE_CH15(x)              (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH15_SHIFT))&APBH_DMA_BURST_SIZE_CH15_MASK)
1589 /* DEBUG Bit Fields */
1590 #define APBH_DEBUG_GPMI_ONE_FIFO_MASK            0x1u
1591 #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT           0
1592 /* CH_CURCMDAR Bit Fields */
1593 #define APBH_CH_CURCMDAR_CMD_ADDR_MASK           0xFFFFFFFFu
1594 #define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT          0
1595 #define APBH_CH_CURCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x))<<APBH_CH_CURCMDAR_CMD_ADDR_SHIFT))&APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1596 /* CH_NXTCMDAR Bit Fields */
1597 #define APBH_CH_NXTCMDAR_CMD_ADDR_MASK           0xFFFFFFFFu
1598 #define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT          0
1599 #define APBH_CH_NXTCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x))<<APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT))&APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1600 /* CH_CMD Bit Fields */
1601 #define APBH_CH_CMD_COMMAND_MASK                 0x3u
1602 #define APBH_CH_CMD_COMMAND_SHIFT                0
1603 #define APBH_CH_CMD_COMMAND(x)                   (((uint32_t)(((uint32_t)(x))<<APBH_CH_CMD_COMMAND_SHIFT))&APBH_CH_CMD_COMMAND_MASK)
1604 #define APBH_CH_CMD_CHAIN_MASK                   0x4u
1605 #define APBH_CH_CMD_CHAIN_SHIFT                  2
1606 #define APBH_CH_CMD_IRQONCMPLT_MASK              0x8u
1607 #define APBH_CH_CMD_IRQONCMPLT_SHIFT             3
1608 #define APBH_CH_CMD_NANDLOCK_MASK                0x10u
1609 #define APBH_CH_CMD_NANDLOCK_SHIFT               4
1610 #define APBH_CH_CMD_NANDWAIT4READY_MASK          0x20u
1611 #define APBH_CH_CMD_NANDWAIT4READY_SHIFT         5
1612 #define APBH_CH_CMD_SEMAPHORE_MASK               0x40u
1613 #define APBH_CH_CMD_SEMAPHORE_SHIFT              6
1614 #define APBH_CH_CMD_WAIT4ENDCMD_MASK             0x80u
1615 #define APBH_CH_CMD_WAIT4ENDCMD_SHIFT            7
1616 #define APBH_CH_CMD_HALTONTERMINATE_MASK         0x100u
1617 #define APBH_CH_CMD_HALTONTERMINATE_SHIFT        8
1618 #define APBH_CH_CMD_CMDWORDS_MASK                0xF000u
1619 #define APBH_CH_CMD_CMDWORDS_SHIFT               12
1620 #define APBH_CH_CMD_CMDWORDS(x)                  (((uint32_t)(((uint32_t)(x))<<APBH_CH_CMD_CMDWORDS_SHIFT))&APBH_CH_CMD_CMDWORDS_MASK)
1621 #define APBH_CH_CMD_XFER_COUNT_MASK              0xFFFF0000u
1622 #define APBH_CH_CMD_XFER_COUNT_SHIFT             16
1623 #define APBH_CH_CMD_XFER_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<APBH_CH_CMD_XFER_COUNT_SHIFT))&APBH_CH_CMD_XFER_COUNT_MASK)
1624 /* CH_BAR Bit Fields */
1625 #define APBH_CH_BAR_ADDRESS_MASK                 0xFFFFFFFFu
1626 #define APBH_CH_BAR_ADDRESS_SHIFT                0
1627 #define APBH_CH_BAR_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x))<<APBH_CH_BAR_ADDRESS_SHIFT))&APBH_CH_BAR_ADDRESS_MASK)
1628 /* CH_SEMA Bit Fields */
1629 #define APBH_CH_SEMA_INCREMENT_SEMA_MASK         0xFFu
1630 #define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT        0
1631 #define APBH_CH_SEMA_INCREMENT_SEMA(x)           (((uint32_t)(((uint32_t)(x))<<APBH_CH_SEMA_INCREMENT_SEMA_SHIFT))&APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1632 #define APBH_CH_SEMA_PHORE_MASK                  0xFF0000u
1633 #define APBH_CH_SEMA_PHORE_SHIFT                 16
1634 #define APBH_CH_SEMA_PHORE(x)                    (((uint32_t)(((uint32_t)(x))<<APBH_CH_SEMA_PHORE_SHIFT))&APBH_CH_SEMA_PHORE_MASK)
1635 /* CH_DEBUG1 Bit Fields */
1636 #define APBH_CH_DEBUG1_STATEMACHINE_MASK         0x1Fu
1637 #define APBH_CH_DEBUG1_STATEMACHINE_SHIFT        0
1638 #define APBH_CH_DEBUG1_STATEMACHINE(x)           (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG1_STATEMACHINE_SHIFT))&APBH_CH_DEBUG1_STATEMACHINE_MASK)
1639 #define APBH_CH_DEBUG1_RSVD1_MASK                0xFFFE0u
1640 #define APBH_CH_DEBUG1_RSVD1_SHIFT               5
1641 #define APBH_CH_DEBUG1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG1_RSVD1_SHIFT))&APBH_CH_DEBUG1_RSVD1_MASK)
1642 #define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK         0x100000u
1643 #define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT        20
1644 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK        0x200000u
1645 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT       21
1646 #define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK         0x400000u
1647 #define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT        22
1648 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK        0x800000u
1649 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT       23
1650 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK     0x1000000u
1651 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT    24
1652 #define APBH_CH_DEBUG1_LOCK_MASK                 0x2000000u
1653 #define APBH_CH_DEBUG1_LOCK_SHIFT                25
1654 #define APBH_CH_DEBUG1_READY_MASK                0x4000000u
1655 #define APBH_CH_DEBUG1_READY_SHIFT               26
1656 #define APBH_CH_DEBUG1_SENSE_MASK                0x8000000u
1657 #define APBH_CH_DEBUG1_SENSE_SHIFT               27
1658 #define APBH_CH_DEBUG1_END_MASK                  0x10000000u
1659 #define APBH_CH_DEBUG1_END_SHIFT                 28
1660 #define APBH_CH_DEBUG1_KICK_MASK                 0x20000000u
1661 #define APBH_CH_DEBUG1_KICK_SHIFT                29
1662 #define APBH_CH_DEBUG1_BURST_MASK                0x40000000u
1663 #define APBH_CH_DEBUG1_BURST_SHIFT               30
1664 #define APBH_CH_DEBUG1_REQ_MASK                  0x80000000u
1665 #define APBH_CH_DEBUG1_REQ_SHIFT                 31
1666 /* CH_DEBUG2 Bit Fields */
1667 #define APBH_CH_DEBUG2_AHB_BYTES_MASK            0xFFFFu
1668 #define APBH_CH_DEBUG2_AHB_BYTES_SHIFT           0
1669 #define APBH_CH_DEBUG2_AHB_BYTES(x)              (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG2_AHB_BYTES_SHIFT))&APBH_CH_DEBUG2_AHB_BYTES_MASK)
1670 #define APBH_CH_DEBUG2_APB_BYTES_MASK            0xFFFF0000u
1671 #define APBH_CH_DEBUG2_APB_BYTES_SHIFT           16
1672 #define APBH_CH_DEBUG2_APB_BYTES(x)              (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG2_APB_BYTES_SHIFT))&APBH_CH_DEBUG2_APB_BYTES_MASK)
1673 /* VERSION Bit Fields */
1674 #define APBH_VERSION_STEP_MASK                   0xFFFFu
1675 #define APBH_VERSION_STEP_SHIFT                  0
1676 #define APBH_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x))<<APBH_VERSION_STEP_SHIFT))&APBH_VERSION_STEP_MASK)
1677 #define APBH_VERSION_MINOR_MASK                  0xFF0000u
1678 #define APBH_VERSION_MINOR_SHIFT                 16
1679 #define APBH_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x))<<APBH_VERSION_MINOR_SHIFT))&APBH_VERSION_MINOR_MASK)
1680 #define APBH_VERSION_MAJOR_MASK                  0xFF000000u
1681 #define APBH_VERSION_MAJOR_SHIFT                 24
1682 #define APBH_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x))<<APBH_VERSION_MAJOR_SHIFT))&APBH_VERSION_MAJOR_MASK)
1683 
1684 /*!
1685  * @}
1686  */ /* end of group APBH_Register_Masks */
1687 
1688 /* APBH - Peripheral instance base addresses */
1689 /** Peripheral APBH base address */
1690 #define APBH_BASE                                (0x33000000u)
1691 /** Peripheral APBH base pointer */
1692 #define APBH                                     ((APBH_Type *)APBH_BASE)
1693 #define APBH_BASE_PTR                            (APBH)
1694 /** Array initializer of APBH peripheral base addresses */
1695 #define APBH_BASE_ADDRS                          { APBH_BASE }
1696 /** Array initializer of APBH peripheral base pointers */
1697 #define APBH_BASE_PTRS                           { APBH }
1698 /** Interrupt vectors for the APBH peripheral type */
1699 #define APBH_IRQS                                { APBHDMA_IRQn }
1700 /* ----------------------------------------------------------------------------
1701    -- APBH - Register accessor macros
1702    ---------------------------------------------------------------------------- */
1703 
1704 /*!
1705  * @addtogroup APBH_Register_Accessor_Macros APBH - Register accessor macros
1706  * @{
1707  */
1708 
1709 
1710 /* APBH - Register instance definitions */
1711 /* APBH */
1712 #define APBH_CTRL0                               APBH_CTRL0_REG(APBH_BASE_PTR)
1713 #define APBH_CTRL0_SET                           APBH_CTRL0_SET_REG(APBH_BASE_PTR)
1714 #define APBH_CTRL0_CLR                           APBH_CTRL0_CLR_REG(APBH_BASE_PTR)
1715 #define APBH_CTRL0_TOG                           APBH_CTRL0_TOG_REG(APBH_BASE_PTR)
1716 #define APBH_CTRL1                               APBH_CTRL1_REG(APBH_BASE_PTR)
1717 #define APBH_CTRL1_SET                           APBH_CTRL1_SET_REG(APBH_BASE_PTR)
1718 #define APBH_CTRL1_CLR                           APBH_CTRL1_CLR_REG(APBH_BASE_PTR)
1719 #define APBH_CTRL1_TOG                           APBH_CTRL1_TOG_REG(APBH_BASE_PTR)
1720 #define APBH_CTRL2                               APBH_CTRL2_REG(APBH_BASE_PTR)
1721 #define APBH_CTRL2_SET                           APBH_CTRL2_SET_REG(APBH_BASE_PTR)
1722 #define APBH_CTRL2_CLR                           APBH_CTRL2_CLR_REG(APBH_BASE_PTR)
1723 #define APBH_CTRL2_TOG                           APBH_CTRL2_TOG_REG(APBH_BASE_PTR)
1724 #define APBH_CHANNEL_CTRL                        APBH_CHANNEL_CTRL_REG(APBH_BASE_PTR)
1725 #define APBH_CHANNEL_CTRL_SET                    APBH_CHANNEL_CTRL_SET_REG(APBH_BASE_PTR)
1726 #define APBH_CHANNEL_CTRL_CLR                    APBH_CHANNEL_CTRL_CLR_REG(APBH_BASE_PTR)
1727 #define APBH_CHANNEL_CTRL_TOG                    APBH_CHANNEL_CTRL_TOG_REG(APBH_BASE_PTR)
1728 #define APBH_DEVSEL                              APBH_DEVSEL_REG(APBH_BASE_PTR)
1729 #define APBH_DMA_BURST_SIZE                      APBH_DMA_BURST_SIZE_REG(APBH_BASE_PTR)
1730 #define APBH_DEBUG                               APBH_DEBUG_REG(APBH_BASE_PTR)
1731 #define APBH_CH0_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,0)
1732 #define APBH_CH0_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,0)
1733 #define APBH_CH0_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,0)
1734 #define APBH_CH0_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,0)
1735 #define APBH_CH0_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,0)
1736 #define APBH_CH0_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,0)
1737 #define APBH_CH0_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,0)
1738 #define APBH_CH1_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,1)
1739 #define APBH_CH1_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,1)
1740 #define APBH_CH1_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,1)
1741 #define APBH_CH1_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,1)
1742 #define APBH_CH1_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,1)
1743 #define APBH_CH1_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,1)
1744 #define APBH_CH1_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,1)
1745 #define APBH_CH2_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,2)
1746 #define APBH_CH2_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,2)
1747 #define APBH_CH2_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,2)
1748 #define APBH_CH2_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,2)
1749 #define APBH_CH2_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,2)
1750 #define APBH_CH2_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,2)
1751 #define APBH_CH2_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,2)
1752 #define APBH_CH3_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,3)
1753 #define APBH_CH3_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,3)
1754 #define APBH_CH3_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,3)
1755 #define APBH_CH3_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,3)
1756 #define APBH_CH3_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,3)
1757 #define APBH_CH3_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,3)
1758 #define APBH_CH3_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,3)
1759 #define APBH_CH4_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,4)
1760 #define APBH_CH4_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,4)
1761 #define APBH_CH4_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,4)
1762 #define APBH_CH4_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,4)
1763 #define APBH_CH4_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,4)
1764 #define APBH_CH4_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,4)
1765 #define APBH_CH4_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,4)
1766 #define APBH_CH5_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,5)
1767 #define APBH_CH5_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,5)
1768 #define APBH_CH5_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,5)
1769 #define APBH_CH5_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,5)
1770 #define APBH_CH5_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,5)
1771 #define APBH_CH5_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,5)
1772 #define APBH_CH5_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,5)
1773 #define APBH_CH6_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,6)
1774 #define APBH_CH6_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,6)
1775 #define APBH_CH6_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,6)
1776 #define APBH_CH6_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,6)
1777 #define APBH_CH6_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,6)
1778 #define APBH_CH6_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,6)
1779 #define APBH_CH6_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,6)
1780 #define APBH_CH7_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,7)
1781 #define APBH_CH7_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,7)
1782 #define APBH_CH7_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,7)
1783 #define APBH_CH7_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,7)
1784 #define APBH_CH7_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,7)
1785 #define APBH_CH7_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,7)
1786 #define APBH_CH7_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,7)
1787 #define APBH_CH8_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,8)
1788 #define APBH_CH8_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,8)
1789 #define APBH_CH8_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,8)
1790 #define APBH_CH8_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,8)
1791 #define APBH_CH8_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,8)
1792 #define APBH_CH8_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,8)
1793 #define APBH_CH8_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,8)
1794 #define APBH_CH9_CURCMDAR                        APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,9)
1795 #define APBH_CH9_NXTCMDAR                        APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,9)
1796 #define APBH_CH9_CMD                             APBH_CH_CMD_REG(APBH_BASE_PTR,9)
1797 #define APBH_CH9_BAR                             APBH_CH_BAR_REG(APBH_BASE_PTR,9)
1798 #define APBH_CH9_SEMA                            APBH_CH_SEMA_REG(APBH_BASE_PTR,9)
1799 #define APBH_CH9_DEBUG1                          APBH_CH_DEBUG1_REG(APBH_BASE_PTR,9)
1800 #define APBH_CH9_DEBUG2                          APBH_CH_DEBUG2_REG(APBH_BASE_PTR,9)
1801 #define APBH_CH10_CURCMDAR                       APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,10)
1802 #define APBH_CH10_NXTCMDAR                       APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,10)
1803 #define APBH_CH10_CMD                            APBH_CH_CMD_REG(APBH_BASE_PTR,10)
1804 #define APBH_CH10_BAR                            APBH_CH_BAR_REG(APBH_BASE_PTR,10)
1805 #define APBH_CH10_SEMA                           APBH_CH_SEMA_REG(APBH_BASE_PTR,10)
1806 #define APBH_CH10_DEBUG1                         APBH_CH_DEBUG1_REG(APBH_BASE_PTR,10)
1807 #define APBH_CH10_DEBUG2                         APBH_CH_DEBUG2_REG(APBH_BASE_PTR,10)
1808 #define APBH_CH11_CURCMDAR                       APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,11)
1809 #define APBH_CH11_NXTCMDAR                       APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,11)
1810 #define APBH_CH11_CMD                            APBH_CH_CMD_REG(APBH_BASE_PTR,11)
1811 #define APBH_CH11_BAR                            APBH_CH_BAR_REG(APBH_BASE_PTR,11)
1812 #define APBH_CH11_SEMA                           APBH_CH_SEMA_REG(APBH_BASE_PTR,11)
1813 #define APBH_CH11_DEBUG1                         APBH_CH_DEBUG1_REG(APBH_BASE_PTR,11)
1814 #define APBH_CH11_DEBUG2                         APBH_CH_DEBUG2_REG(APBH_BASE_PTR,11)
1815 #define APBH_CH12_CURCMDAR                       APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,12)
1816 #define APBH_CH12_NXTCMDAR                       APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,12)
1817 #define APBH_CH12_CMD                            APBH_CH_CMD_REG(APBH_BASE_PTR,12)
1818 #define APBH_CH12_BAR                            APBH_CH_BAR_REG(APBH_BASE_PTR,12)
1819 #define APBH_CH12_SEMA                           APBH_CH_SEMA_REG(APBH_BASE_PTR,12)
1820 #define APBH_CH12_DEBUG1                         APBH_CH_DEBUG1_REG(APBH_BASE_PTR,12)
1821 #define APBH_CH12_DEBUG2                         APBH_CH_DEBUG2_REG(APBH_BASE_PTR,12)
1822 #define APBH_CH13_CURCMDAR                       APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,13)
1823 #define APBH_CH13_NXTCMDAR                       APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,13)
1824 #define APBH_CH13_CMD                            APBH_CH_CMD_REG(APBH_BASE_PTR,13)
1825 #define APBH_CH13_BAR                            APBH_CH_BAR_REG(APBH_BASE_PTR,13)
1826 #define APBH_CH13_SEMA                           APBH_CH_SEMA_REG(APBH_BASE_PTR,13)
1827 #define APBH_CH13_DEBUG1                         APBH_CH_DEBUG1_REG(APBH_BASE_PTR,13)
1828 #define APBH_CH13_DEBUG2                         APBH_CH_DEBUG2_REG(APBH_BASE_PTR,13)
1829 #define APBH_CH14_CURCMDAR                       APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,14)
1830 #define APBH_CH14_NXTCMDAR                       APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,14)
1831 #define APBH_CH14_CMD                            APBH_CH_CMD_REG(APBH_BASE_PTR,14)
1832 #define APBH_CH14_BAR                            APBH_CH_BAR_REG(APBH_BASE_PTR,14)
1833 #define APBH_CH14_SEMA                           APBH_CH_SEMA_REG(APBH_BASE_PTR,14)
1834 #define APBH_CH14_DEBUG1                         APBH_CH_DEBUG1_REG(APBH_BASE_PTR,14)
1835 #define APBH_CH14_DEBUG2                         APBH_CH_DEBUG2_REG(APBH_BASE_PTR,14)
1836 #define APBH_CH15_CURCMDAR                       APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,15)
1837 #define APBH_CH15_NXTCMDAR                       APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,15)
1838 #define APBH_CH15_CMD                            APBH_CH_CMD_REG(APBH_BASE_PTR,15)
1839 #define APBH_CH15_BAR                            APBH_CH_BAR_REG(APBH_BASE_PTR,15)
1840 #define APBH_CH15_SEMA                           APBH_CH_SEMA_REG(APBH_BASE_PTR,15)
1841 #define APBH_CH15_DEBUG1                         APBH_CH_DEBUG1_REG(APBH_BASE_PTR,15)
1842 #define APBH_CH15_DEBUG2                         APBH_CH_DEBUG2_REG(APBH_BASE_PTR,15)
1843 #define APBH_VERSION                             APBH_VERSION_REG(APBH_BASE_PTR)
1844 /* APBH - Register array accessors */
1845 #define APBH_CH_CURCMDAR(index)                  APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,index)
1846 #define APBH_CH_NXTCMDAR(index)                  APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,index)
1847 #define APBH_CH_CMD(index)                       APBH_CH_CMD_REG(APBH_BASE_PTR,index)
1848 #define APBH_CH_BAR(index)                       APBH_CH_BAR_REG(APBH_BASE_PTR,index)
1849 #define APBH_CH_SEMA(index)                      APBH_CH_SEMA_REG(APBH_BASE_PTR,index)
1850 #define APBH_CH_DEBUG1(index)                    APBH_CH_DEBUG1_REG(APBH_BASE_PTR,index)
1851 #define APBH_CH_DEBUG2(index)                    APBH_CH_DEBUG2_REG(APBH_BASE_PTR,index)
1852 /*!
1853  * @}
1854  */ /* end of group APBH_Register_Accessor_Macros */
1855 
1856 
1857 /*!
1858  * @}
1859  */ /* end of group APBH_Peripheral */
1860 
1861 /* ----------------------------------------------------------------------------
1862    -- BCH Peripheral Access Layer
1863    ---------------------------------------------------------------------------- */
1864 
1865 /*!
1866  * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
1867  * @{
1868  */
1869 
1870 /** BCH - Register Layout Typedef */
1871 typedef struct {
1872   __IO  uint32_t CTRL;                                   /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
1873   __IO  uint32_t CTRL_SET;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
1874   __IO  uint32_t CTRL_CLR;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
1875   __IO  uint32_t CTRL_TOG;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
1876   __I   uint32_t STATUS0;                                /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
1877   __I   uint32_t STATUS0_SET;                            /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
1878   __I   uint32_t STATUS0_CLR;                            /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
1879   __I   uint32_t STATUS0_TOG;                            /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
1880   __IO  uint32_t MODE;                                   /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
1881   __IO  uint32_t MODE_SET;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
1882   __IO  uint32_t MODE_CLR;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
1883   __IO  uint32_t MODE_TOG;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
1884   __IO  uint32_t ENCODEPTR;                              /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
1885   __IO  uint32_t ENCODEPTR_SET;                          /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
1886   __IO  uint32_t ENCODEPTR_CLR;                          /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
1887   __IO  uint32_t ENCODEPTR_TOG;                          /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
1888   __IO  uint32_t DATAPTR;                                /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
1889   __IO  uint32_t DATAPTR_SET;                            /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
1890   __IO  uint32_t DATAPTR_CLR;                            /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
1891   __IO  uint32_t DATAPTR_TOG;                            /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
1892   __IO  uint32_t METAPTR;                                /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
1893   __IO  uint32_t METAPTR_SET;                            /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
1894   __IO  uint32_t METAPTR_CLR;                            /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
1895   __IO  uint32_t METAPTR_TOG;                            /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
1896   uint8_t RESERVED_0[16];
1897   __IO  uint32_t LAYOUTSELECT;                           /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
1898   __IO  uint32_t LAYOUTSELECT_SET;                       /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
1899   __IO  uint32_t LAYOUTSELECT_CLR;                       /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
1900   __IO  uint32_t LAYOUTSELECT_TOG;                       /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
1901   __IO  uint32_t FLASH0LAYOUT0;                          /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
1902   __IO  uint32_t FLASH0LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
1903   __IO  uint32_t FLASH0LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
1904   __IO  uint32_t FLASH0LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
1905   __IO  uint32_t FLASH0LAYOUT1;                          /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
1906   __IO  uint32_t FLASH0LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
1907   __IO  uint32_t FLASH0LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
1908   __IO  uint32_t FLASH0LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
1909   __IO  uint32_t FLASH1LAYOUT0;                          /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
1910   __IO  uint32_t FLASH1LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
1911   __IO  uint32_t FLASH1LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
1912   __IO  uint32_t FLASH1LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
1913   __IO  uint32_t FLASH1LAYOUT1;                          /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
1914   __IO  uint32_t FLASH1LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
1915   __IO  uint32_t FLASH1LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
1916   __IO  uint32_t FLASH1LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
1917   __IO  uint32_t FLASH2LAYOUT0;                          /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
1918   __IO  uint32_t FLASH2LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
1919   __IO  uint32_t FLASH2LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
1920   __IO  uint32_t FLASH2LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
1921   __IO  uint32_t FLASH2LAYOUT1;                          /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
1922   __IO  uint32_t FLASH2LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
1923   __IO  uint32_t FLASH2LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
1924   __IO  uint32_t FLASH2LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
1925   __IO  uint32_t FLASH3LAYOUT0;                          /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
1926   __IO  uint32_t FLASH3LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
1927   __IO  uint32_t FLASH3LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
1928   __IO  uint32_t FLASH3LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
1929   __IO  uint32_t FLASH3LAYOUT1;                          /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
1930   __IO  uint32_t FLASH3LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
1931   __IO  uint32_t FLASH3LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
1932   __IO  uint32_t FLASH3LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
1933   __IO  uint32_t DEBUG0;                                 /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
1934   __IO  uint32_t DEBUG0_SET;                             /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
1935   __IO  uint32_t DEBUG0_CLR;                             /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
1936   __IO  uint32_t DEBUG0_TOG;                             /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
1937   __I   uint32_t DBGKESREAD;                             /**< KES Debug Read Register, offset: 0x110 */
1938   __I   uint32_t DBGKESREAD_SET;                         /**< KES Debug Read Register, offset: 0x114 */
1939   __I   uint32_t DBGKESREAD_CLR;                         /**< KES Debug Read Register, offset: 0x118 */
1940   __I   uint32_t DBGKESREAD_TOG;                         /**< KES Debug Read Register, offset: 0x11C */
1941   __I   uint32_t DBGCSFEREAD;                            /**< Chien Search Debug Read Register, offset: 0x120 */
1942   __I   uint32_t DBGCSFEREAD_SET;                        /**< Chien Search Debug Read Register, offset: 0x124 */
1943   __I   uint32_t DBGCSFEREAD_CLR;                        /**< Chien Search Debug Read Register, offset: 0x128 */
1944   __I   uint32_t DBGCSFEREAD_TOG;                        /**< Chien Search Debug Read Register, offset: 0x12C */
1945   __I   uint32_t DBGSYNDGENREAD;                         /**< Syndrome Generator Debug Read Register, offset: 0x130 */
1946   __I   uint32_t DBGSYNDGENREAD_SET;                     /**< Syndrome Generator Debug Read Register, offset: 0x134 */
1947   __I   uint32_t DBGSYNDGENREAD_CLR;                     /**< Syndrome Generator Debug Read Register, offset: 0x138 */
1948   __I   uint32_t DBGSYNDGENREAD_TOG;                     /**< Syndrome Generator Debug Read Register, offset: 0x13C */
1949   __I   uint32_t DBGAHBMREAD;                            /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
1950   __I   uint32_t DBGAHBMREAD_SET;                        /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
1951   __I   uint32_t DBGAHBMREAD_CLR;                        /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
1952   __I   uint32_t DBGAHBMREAD_TOG;                        /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
1953   __I   uint32_t BLOCKNAME;                              /**< Block Name Register, offset: 0x150 */
1954   __I   uint32_t BLOCKNAME_SET;                          /**< Block Name Register, offset: 0x154 */
1955   __I   uint32_t BLOCKNAME_CLR;                          /**< Block Name Register, offset: 0x158 */
1956   __I   uint32_t BLOCKNAME_TOG;                          /**< Block Name Register, offset: 0x15C */
1957   __I   uint32_t VERSION;                                /**< BCH Version Register, offset: 0x160 */
1958   __I   uint32_t VERSION_SET;                            /**< BCH Version Register, offset: 0x164 */
1959   __I   uint32_t VERSION_CLR;                            /**< BCH Version Register, offset: 0x168 */
1960   __I   uint32_t VERSION_TOG;                            /**< BCH Version Register, offset: 0x16C */
1961   __IO  uint32_t DEBUG1;                                 /**< Hardware BCH ECC Debug Register 1 , offset: 0x170 */
1962   __IO  uint32_t DEBUG1_SET;                             /**< Hardware BCH ECC Debug Register 1 , offset: 0x174 */
1963   __IO  uint32_t DEBUG1_CLR;                             /**< Hardware BCH ECC Debug Register 1 , offset: 0x178 */
1964   __IO  uint32_t DEBUG1_TOG;                             /**< Hardware BCH ECC Debug Register 1 , offset: 0x17C */
1965 } BCH_Type, *BCH_MemMapPtr;
1966 /* ----------------------------------------------------------------------------
1967    -- BCH - Register accessor macros
1968    ---------------------------------------------------------------------------- */
1969 
1970 /*!
1971  * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros
1972  * @{
1973  */
1974 
1975 
1976 /* BCH - Register accessors */
1977 #define BCH_CTRL_REG(base)                       ((base)->CTRL)
1978 #define BCH_CTRL_SET_REG(base)                   ((base)->CTRL_SET)
1979 #define BCH_CTRL_CLR_REG(base)                   ((base)->CTRL_CLR)
1980 #define BCH_CTRL_TOG_REG(base)                   ((base)->CTRL_TOG)
1981 #define BCH_STATUS0_REG(base)                    ((base)->STATUS0)
1982 #define BCH_STATUS0_SET_REG(base)                ((base)->STATUS0_SET)
1983 #define BCH_STATUS0_CLR_REG(base)                ((base)->STATUS0_CLR)
1984 #define BCH_STATUS0_TOG_REG(base)                ((base)->STATUS0_TOG)
1985 #define BCH_MODE_REG(base)                       ((base)->MODE)
1986 #define BCH_MODE_SET_REG(base)                   ((base)->MODE_SET)
1987 #define BCH_MODE_CLR_REG(base)                   ((base)->MODE_CLR)
1988 #define BCH_MODE_TOG_REG(base)                   ((base)->MODE_TOG)
1989 #define BCH_ENCODEPTR_REG(base)                  ((base)->ENCODEPTR)
1990 #define BCH_ENCODEPTR_SET_REG(base)              ((base)->ENCODEPTR_SET)
1991 #define BCH_ENCODEPTR_CLR_REG(base)              ((base)->ENCODEPTR_CLR)
1992 #define BCH_ENCODEPTR_TOG_REG(base)              ((base)->ENCODEPTR_TOG)
1993 #define BCH_DATAPTR_REG(base)                    ((base)->DATAPTR)
1994 #define BCH_DATAPTR_SET_REG(base)                ((base)->DATAPTR_SET)
1995 #define BCH_DATAPTR_CLR_REG(base)                ((base)->DATAPTR_CLR)
1996 #define BCH_DATAPTR_TOG_REG(base)                ((base)->DATAPTR_TOG)
1997 #define BCH_METAPTR_REG(base)                    ((base)->METAPTR)
1998 #define BCH_METAPTR_SET_REG(base)                ((base)->METAPTR_SET)
1999 #define BCH_METAPTR_CLR_REG(base)                ((base)->METAPTR_CLR)
2000 #define BCH_METAPTR_TOG_REG(base)                ((base)->METAPTR_TOG)
2001 #define BCH_LAYOUTSELECT_REG(base)               ((base)->LAYOUTSELECT)
2002 #define BCH_LAYOUTSELECT_SET_REG(base)           ((base)->LAYOUTSELECT_SET)
2003 #define BCH_LAYOUTSELECT_CLR_REG(base)           ((base)->LAYOUTSELECT_CLR)
2004 #define BCH_LAYOUTSELECT_TOG_REG(base)           ((base)->LAYOUTSELECT_TOG)
2005 #define BCH_FLASH0LAYOUT0_REG(base)              ((base)->FLASH0LAYOUT0)
2006 #define BCH_FLASH0LAYOUT0_SET_REG(base)          ((base)->FLASH0LAYOUT0_SET)
2007 #define BCH_FLASH0LAYOUT0_CLR_REG(base)          ((base)->FLASH0LAYOUT0_CLR)
2008 #define BCH_FLASH0LAYOUT0_TOG_REG(base)          ((base)->FLASH0LAYOUT0_TOG)
2009 #define BCH_FLASH0LAYOUT1_REG(base)              ((base)->FLASH0LAYOUT1)
2010 #define BCH_FLASH0LAYOUT1_SET_REG(base)          ((base)->FLASH0LAYOUT1_SET)
2011 #define BCH_FLASH0LAYOUT1_CLR_REG(base)          ((base)->FLASH0LAYOUT1_CLR)
2012 #define BCH_FLASH0LAYOUT1_TOG_REG(base)          ((base)->FLASH0LAYOUT1_TOG)
2013 #define BCH_FLASH1LAYOUT0_REG(base)              ((base)->FLASH1LAYOUT0)
2014 #define BCH_FLASH1LAYOUT0_SET_REG(base)          ((base)->FLASH1LAYOUT0_SET)
2015 #define BCH_FLASH1LAYOUT0_CLR_REG(base)          ((base)->FLASH1LAYOUT0_CLR)
2016 #define BCH_FLASH1LAYOUT0_TOG_REG(base)          ((base)->FLASH1LAYOUT0_TOG)
2017 #define BCH_FLASH1LAYOUT1_REG(base)              ((base)->FLASH1LAYOUT1)
2018 #define BCH_FLASH1LAYOUT1_SET_REG(base)          ((base)->FLASH1LAYOUT1_SET)
2019 #define BCH_FLASH1LAYOUT1_CLR_REG(base)          ((base)->FLASH1LAYOUT1_CLR)
2020 #define BCH_FLASH1LAYOUT1_TOG_REG(base)          ((base)->FLASH1LAYOUT1_TOG)
2021 #define BCH_FLASH2LAYOUT0_REG(base)              ((base)->FLASH2LAYOUT0)
2022 #define BCH_FLASH2LAYOUT0_SET_REG(base)          ((base)->FLASH2LAYOUT0_SET)
2023 #define BCH_FLASH2LAYOUT0_CLR_REG(base)          ((base)->FLASH2LAYOUT0_CLR)
2024 #define BCH_FLASH2LAYOUT0_TOG_REG(base)          ((base)->FLASH2LAYOUT0_TOG)
2025 #define BCH_FLASH2LAYOUT1_REG(base)              ((base)->FLASH2LAYOUT1)
2026 #define BCH_FLASH2LAYOUT1_SET_REG(base)          ((base)->FLASH2LAYOUT1_SET)
2027 #define BCH_FLASH2LAYOUT1_CLR_REG(base)          ((base)->FLASH2LAYOUT1_CLR)
2028 #define BCH_FLASH2LAYOUT1_TOG_REG(base)          ((base)->FLASH2LAYOUT1_TOG)
2029 #define BCH_FLASH3LAYOUT0_REG(base)              ((base)->FLASH3LAYOUT0)
2030 #define BCH_FLASH3LAYOUT0_SET_REG(base)          ((base)->FLASH3LAYOUT0_SET)
2031 #define BCH_FLASH3LAYOUT0_CLR_REG(base)          ((base)->FLASH3LAYOUT0_CLR)
2032 #define BCH_FLASH3LAYOUT0_TOG_REG(base)          ((base)->FLASH3LAYOUT0_TOG)
2033 #define BCH_FLASH3LAYOUT1_REG(base)              ((base)->FLASH3LAYOUT1)
2034 #define BCH_FLASH3LAYOUT1_SET_REG(base)          ((base)->FLASH3LAYOUT1_SET)
2035 #define BCH_FLASH3LAYOUT1_CLR_REG(base)          ((base)->FLASH3LAYOUT1_CLR)
2036 #define BCH_FLASH3LAYOUT1_TOG_REG(base)          ((base)->FLASH3LAYOUT1_TOG)
2037 #define BCH_DEBUG0_REG(base)                     ((base)->DEBUG0)
2038 #define BCH_DEBUG0_SET_REG(base)                 ((base)->DEBUG0_SET)
2039 #define BCH_DEBUG0_CLR_REG(base)                 ((base)->DEBUG0_CLR)
2040 #define BCH_DEBUG0_TOG_REG(base)                 ((base)->DEBUG0_TOG)
2041 #define BCH_DBGKESREAD_REG(base)                 ((base)->DBGKESREAD)
2042 #define BCH_DBGKESREAD_SET_REG(base)             ((base)->DBGKESREAD_SET)
2043 #define BCH_DBGKESREAD_CLR_REG(base)             ((base)->DBGKESREAD_CLR)
2044 #define BCH_DBGKESREAD_TOG_REG(base)             ((base)->DBGKESREAD_TOG)
2045 #define BCH_DBGCSFEREAD_REG(base)                ((base)->DBGCSFEREAD)
2046 #define BCH_DBGCSFEREAD_SET_REG(base)            ((base)->DBGCSFEREAD_SET)
2047 #define BCH_DBGCSFEREAD_CLR_REG(base)            ((base)->DBGCSFEREAD_CLR)
2048 #define BCH_DBGCSFEREAD_TOG_REG(base)            ((base)->DBGCSFEREAD_TOG)
2049 #define BCH_DBGSYNDGENREAD_REG(base)             ((base)->DBGSYNDGENREAD)
2050 #define BCH_DBGSYNDGENREAD_SET_REG(base)         ((base)->DBGSYNDGENREAD_SET)
2051 #define BCH_DBGSYNDGENREAD_CLR_REG(base)         ((base)->DBGSYNDGENREAD_CLR)
2052 #define BCH_DBGSYNDGENREAD_TOG_REG(base)         ((base)->DBGSYNDGENREAD_TOG)
2053 #define BCH_DBGAHBMREAD_REG(base)                ((base)->DBGAHBMREAD)
2054 #define BCH_DBGAHBMREAD_SET_REG(base)            ((base)->DBGAHBMREAD_SET)
2055 #define BCH_DBGAHBMREAD_CLR_REG(base)            ((base)->DBGAHBMREAD_CLR)
2056 #define BCH_DBGAHBMREAD_TOG_REG(base)            ((base)->DBGAHBMREAD_TOG)
2057 #define BCH_BLOCKNAME_REG(base)                  ((base)->BLOCKNAME)
2058 #define BCH_BLOCKNAME_SET_REG(base)              ((base)->BLOCKNAME_SET)
2059 #define BCH_BLOCKNAME_CLR_REG(base)              ((base)->BLOCKNAME_CLR)
2060 #define BCH_BLOCKNAME_TOG_REG(base)              ((base)->BLOCKNAME_TOG)
2061 #define BCH_VERSION_REG(base)                    ((base)->VERSION)
2062 #define BCH_VERSION_SET_REG(base)                ((base)->VERSION_SET)
2063 #define BCH_VERSION_CLR_REG(base)                ((base)->VERSION_CLR)
2064 #define BCH_VERSION_TOG_REG(base)                ((base)->VERSION_TOG)
2065 #define BCH_DEBUG1_REG(base)                     ((base)->DEBUG1)
2066 #define BCH_DEBUG1_SET_REG(base)                 ((base)->DEBUG1_SET)
2067 #define BCH_DEBUG1_CLR_REG(base)                 ((base)->DEBUG1_CLR)
2068 #define BCH_DEBUG1_TOG_REG(base)                 ((base)->DEBUG1_TOG)
2069 
2070 /*!
2071  * @}
2072  */ /* end of group BCH_Register_Accessor_Macros */
2073 /* ----------------------------------------------------------------------------
2074    -- BCH Register Masks
2075    ---------------------------------------------------------------------------- */
2076 
2077 /*!
2078  * @addtogroup BCH_Register_Masks BCH Register Masks
2079  * @{
2080  */
2081 
2082 /* CTRL Bit Fields */
2083 #define BCH_CTRL_COMPLETE_IRQ_MASK               0x1u
2084 #define BCH_CTRL_COMPLETE_IRQ_SHIFT              0
2085 #define BCH_CTRL_RSVD0_MASK                      0x2u
2086 #define BCH_CTRL_RSVD0_SHIFT                     1
2087 #define BCH_CTRL_DEBUG_STALL_IRQ_MASK            0x4u
2088 #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           2
2089 #define BCH_CTRL_BM_ERROR_IRQ_MASK               0x8u
2090 #define BCH_CTRL_BM_ERROR_IRQ_SHIFT              3
2091 #define BCH_CTRL_RSVD1_MASK                      0xF0u
2092 #define BCH_CTRL_RSVD1_SHIFT                     4
2093 #define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD1_SHIFT))&BCH_CTRL_RSVD1_MASK)
2094 #define BCH_CTRL_COMPLETE_IRQ_EN_MASK            0x100u
2095 #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           8
2096 #define BCH_CTRL_RSVD2_MASK                      0x200u
2097 #define BCH_CTRL_RSVD2_SHIFT                     9
2098 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         0x400u
2099 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        10
2100 #define BCH_CTRL_RSVD3_MASK                      0xF800u
2101 #define BCH_CTRL_RSVD3_SHIFT                     11
2102 #define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD3_SHIFT))&BCH_CTRL_RSVD3_MASK)
2103 #define BCH_CTRL_M2M_ENABLE_MASK                 0x10000u
2104 #define BCH_CTRL_M2M_ENABLE_SHIFT                16
2105 #define BCH_CTRL_M2M_ENCODE_MASK                 0x20000u
2106 #define BCH_CTRL_M2M_ENCODE_SHIFT                17
2107 #define BCH_CTRL_M2M_LAYOUT_MASK                 0xC0000u
2108 #define BCH_CTRL_M2M_LAYOUT_SHIFT                18
2109 #define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_M2M_LAYOUT_SHIFT))&BCH_CTRL_M2M_LAYOUT_MASK)
2110 #define BCH_CTRL_RSVD4_MASK                      0x300000u
2111 #define BCH_CTRL_RSVD4_SHIFT                     20
2112 #define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD4_SHIFT))&BCH_CTRL_RSVD4_MASK)
2113 #define BCH_CTRL_DEBUGSYNDROME_MASK              0x400000u
2114 #define BCH_CTRL_DEBUGSYNDROME_SHIFT             22
2115 #define BCH_CTRL_RSVD5_MASK                      0x3F800000u
2116 #define BCH_CTRL_RSVD5_SHIFT                     23
2117 #define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD5_SHIFT))&BCH_CTRL_RSVD5_MASK)
2118 #define BCH_CTRL_CLKGATE_MASK                    0x40000000u
2119 #define BCH_CTRL_CLKGATE_SHIFT                   30
2120 #define BCH_CTRL_SFTRST_MASK                     0x80000000u
2121 #define BCH_CTRL_SFTRST_SHIFT                    31
2122 /* CTRL_SET Bit Fields */
2123 #define BCH_CTRL_SET_COMPLETE_IRQ_MASK           0x1u
2124 #define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT          0
2125 #define BCH_CTRL_SET_RSVD0_MASK                  0x2u
2126 #define BCH_CTRL_SET_RSVD0_SHIFT                 1
2127 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK        0x4u
2128 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT       2
2129 #define BCH_CTRL_SET_BM_ERROR_IRQ_MASK           0x8u
2130 #define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT          3
2131 #define BCH_CTRL_SET_RSVD1_MASK                  0xF0u
2132 #define BCH_CTRL_SET_RSVD1_SHIFT                 4
2133 #define BCH_CTRL_SET_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD1_SHIFT))&BCH_CTRL_SET_RSVD1_MASK)
2134 #define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK        0x100u
2135 #define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT       8
2136 #define BCH_CTRL_SET_RSVD2_MASK                  0x200u
2137 #define BCH_CTRL_SET_RSVD2_SHIFT                 9
2138 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK     0x400u
2139 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT    10
2140 #define BCH_CTRL_SET_RSVD3_MASK                  0xF800u
2141 #define BCH_CTRL_SET_RSVD3_SHIFT                 11
2142 #define BCH_CTRL_SET_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD3_SHIFT))&BCH_CTRL_SET_RSVD3_MASK)
2143 #define BCH_CTRL_SET_M2M_ENABLE_MASK             0x10000u
2144 #define BCH_CTRL_SET_M2M_ENABLE_SHIFT            16
2145 #define BCH_CTRL_SET_M2M_ENCODE_MASK             0x20000u
2146 #define BCH_CTRL_SET_M2M_ENCODE_SHIFT            17
2147 #define BCH_CTRL_SET_M2M_LAYOUT_MASK             0xC0000u
2148 #define BCH_CTRL_SET_M2M_LAYOUT_SHIFT            18
2149 #define BCH_CTRL_SET_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_M2M_LAYOUT_SHIFT))&BCH_CTRL_SET_M2M_LAYOUT_MASK)
2150 #define BCH_CTRL_SET_RSVD4_MASK                  0x300000u
2151 #define BCH_CTRL_SET_RSVD4_SHIFT                 20
2152 #define BCH_CTRL_SET_RSVD4(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD4_SHIFT))&BCH_CTRL_SET_RSVD4_MASK)
2153 #define BCH_CTRL_SET_DEBUGSYNDROME_MASK          0x400000u
2154 #define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT         22
2155 #define BCH_CTRL_SET_RSVD5_MASK                  0x3F800000u
2156 #define BCH_CTRL_SET_RSVD5_SHIFT                 23
2157 #define BCH_CTRL_SET_RSVD5(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD5_SHIFT))&BCH_CTRL_SET_RSVD5_MASK)
2158 #define BCH_CTRL_SET_CLKGATE_MASK                0x40000000u
2159 #define BCH_CTRL_SET_CLKGATE_SHIFT               30
2160 #define BCH_CTRL_SET_SFTRST_MASK                 0x80000000u
2161 #define BCH_CTRL_SET_SFTRST_SHIFT                31
2162 /* CTRL_CLR Bit Fields */
2163 #define BCH_CTRL_CLR_COMPLETE_IRQ_MASK           0x1u
2164 #define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT          0
2165 #define BCH_CTRL_CLR_RSVD0_MASK                  0x2u
2166 #define BCH_CTRL_CLR_RSVD0_SHIFT                 1
2167 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK        0x4u
2168 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT       2
2169 #define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK           0x8u
2170 #define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT          3
2171 #define BCH_CTRL_CLR_RSVD1_MASK                  0xF0u
2172 #define BCH_CTRL_CLR_RSVD1_SHIFT                 4
2173 #define BCH_CTRL_CLR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD1_SHIFT))&BCH_CTRL_CLR_RSVD1_MASK)
2174 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK        0x100u
2175 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT       8
2176 #define BCH_CTRL_CLR_RSVD2_MASK                  0x200u
2177 #define BCH_CTRL_CLR_RSVD2_SHIFT                 9
2178 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK     0x400u
2179 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT    10
2180 #define BCH_CTRL_CLR_RSVD3_MASK                  0xF800u
2181 #define BCH_CTRL_CLR_RSVD3_SHIFT                 11
2182 #define BCH_CTRL_CLR_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD3_SHIFT))&BCH_CTRL_CLR_RSVD3_MASK)
2183 #define BCH_CTRL_CLR_M2M_ENABLE_MASK             0x10000u
2184 #define BCH_CTRL_CLR_M2M_ENABLE_SHIFT            16
2185 #define BCH_CTRL_CLR_M2M_ENCODE_MASK             0x20000u
2186 #define BCH_CTRL_CLR_M2M_ENCODE_SHIFT            17
2187 #define BCH_CTRL_CLR_M2M_LAYOUT_MASK             0xC0000u
2188 #define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT            18
2189 #define BCH_CTRL_CLR_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_M2M_LAYOUT_SHIFT))&BCH_CTRL_CLR_M2M_LAYOUT_MASK)
2190 #define BCH_CTRL_CLR_RSVD4_MASK                  0x300000u
2191 #define BCH_CTRL_CLR_RSVD4_SHIFT                 20
2192 #define BCH_CTRL_CLR_RSVD4(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD4_SHIFT))&BCH_CTRL_CLR_RSVD4_MASK)
2193 #define BCH_CTRL_CLR_DEBUGSYNDROME_MASK          0x400000u
2194 #define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT         22
2195 #define BCH_CTRL_CLR_RSVD5_MASK                  0x3F800000u
2196 #define BCH_CTRL_CLR_RSVD5_SHIFT                 23
2197 #define BCH_CTRL_CLR_RSVD5(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD5_SHIFT))&BCH_CTRL_CLR_RSVD5_MASK)
2198 #define BCH_CTRL_CLR_CLKGATE_MASK                0x40000000u
2199 #define BCH_CTRL_CLR_CLKGATE_SHIFT               30
2200 #define BCH_CTRL_CLR_SFTRST_MASK                 0x80000000u
2201 #define BCH_CTRL_CLR_SFTRST_SHIFT                31
2202 /* CTRL_TOG Bit Fields */
2203 #define BCH_CTRL_TOG_COMPLETE_IRQ_MASK           0x1u
2204 #define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT          0
2205 #define BCH_CTRL_TOG_RSVD0_MASK                  0x2u
2206 #define BCH_CTRL_TOG_RSVD0_SHIFT                 1
2207 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK        0x4u
2208 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT       2
2209 #define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK           0x8u
2210 #define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT          3
2211 #define BCH_CTRL_TOG_RSVD1_MASK                  0xF0u
2212 #define BCH_CTRL_TOG_RSVD1_SHIFT                 4
2213 #define BCH_CTRL_TOG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD1_SHIFT))&BCH_CTRL_TOG_RSVD1_MASK)
2214 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK        0x100u
2215 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT       8
2216 #define BCH_CTRL_TOG_RSVD2_MASK                  0x200u
2217 #define BCH_CTRL_TOG_RSVD2_SHIFT                 9
2218 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK     0x400u
2219 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT    10
2220 #define BCH_CTRL_TOG_RSVD3_MASK                  0xF800u
2221 #define BCH_CTRL_TOG_RSVD3_SHIFT                 11
2222 #define BCH_CTRL_TOG_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD3_SHIFT))&BCH_CTRL_TOG_RSVD3_MASK)
2223 #define BCH_CTRL_TOG_M2M_ENABLE_MASK             0x10000u
2224 #define BCH_CTRL_TOG_M2M_ENABLE_SHIFT            16
2225 #define BCH_CTRL_TOG_M2M_ENCODE_MASK             0x20000u
2226 #define BCH_CTRL_TOG_M2M_ENCODE_SHIFT            17
2227 #define BCH_CTRL_TOG_M2M_LAYOUT_MASK             0xC0000u
2228 #define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT            18
2229 #define BCH_CTRL_TOG_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_M2M_LAYOUT_SHIFT))&BCH_CTRL_TOG_M2M_LAYOUT_MASK)
2230 #define BCH_CTRL_TOG_RSVD4_MASK                  0x300000u
2231 #define BCH_CTRL_TOG_RSVD4_SHIFT                 20
2232 #define BCH_CTRL_TOG_RSVD4(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD4_SHIFT))&BCH_CTRL_TOG_RSVD4_MASK)
2233 #define BCH_CTRL_TOG_DEBUGSYNDROME_MASK          0x400000u
2234 #define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT         22
2235 #define BCH_CTRL_TOG_RSVD5_MASK                  0x3F800000u
2236 #define BCH_CTRL_TOG_RSVD5_SHIFT                 23
2237 #define BCH_CTRL_TOG_RSVD5(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD5_SHIFT))&BCH_CTRL_TOG_RSVD5_MASK)
2238 #define BCH_CTRL_TOG_CLKGATE_MASK                0x40000000u
2239 #define BCH_CTRL_TOG_CLKGATE_SHIFT               30
2240 #define BCH_CTRL_TOG_SFTRST_MASK                 0x80000000u
2241 #define BCH_CTRL_TOG_SFTRST_SHIFT                31
2242 /* STATUS0 Bit Fields */
2243 #define BCH_STATUS0_RSVD0_MASK                   0x3u
2244 #define BCH_STATUS0_RSVD0_SHIFT                  0
2245 #define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD0_SHIFT))&BCH_STATUS0_RSVD0_MASK)
2246 #define BCH_STATUS0_UNCORRECTABLE_MASK           0x4u
2247 #define BCH_STATUS0_UNCORRECTABLE_SHIFT          2
2248 #define BCH_STATUS0_CORRECTED_MASK               0x8u
2249 #define BCH_STATUS0_CORRECTED_SHIFT              3
2250 #define BCH_STATUS0_ALLONES_MASK                 0x10u
2251 #define BCH_STATUS0_ALLONES_SHIFT                4
2252 #define BCH_STATUS0_RSVD1_MASK                   0xE0u
2253 #define BCH_STATUS0_RSVD1_SHIFT                  5
2254 #define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD1_SHIFT))&BCH_STATUS0_RSVD1_MASK)
2255 #define BCH_STATUS0_STATUS_BLK0_MASK             0xFF00u
2256 #define BCH_STATUS0_STATUS_BLK0_SHIFT            8
2257 #define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_STATUS_BLK0_SHIFT))&BCH_STATUS0_STATUS_BLK0_MASK)
2258 #define BCH_STATUS0_COMPLETED_CE_MASK            0xF0000u
2259 #define BCH_STATUS0_COMPLETED_CE_SHIFT           16
2260 #define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_COMPLETED_CE_SHIFT))&BCH_STATUS0_COMPLETED_CE_MASK)
2261 #define BCH_STATUS0_HANDLE_MASK                  0xFFF00000u
2262 #define BCH_STATUS0_HANDLE_SHIFT                 20
2263 #define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_HANDLE_SHIFT))&BCH_STATUS0_HANDLE_MASK)
2264 /* STATUS0_SET Bit Fields */
2265 #define BCH_STATUS0_SET_RSVD0_MASK               0x3u
2266 #define BCH_STATUS0_SET_RSVD0_SHIFT              0
2267 #define BCH_STATUS0_SET_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD0_SHIFT))&BCH_STATUS0_SET_RSVD0_MASK)
2268 #define BCH_STATUS0_SET_UNCORRECTABLE_MASK       0x4u
2269 #define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT      2
2270 #define BCH_STATUS0_SET_CORRECTED_MASK           0x8u
2271 #define BCH_STATUS0_SET_CORRECTED_SHIFT          3
2272 #define BCH_STATUS0_SET_ALLONES_MASK             0x10u
2273 #define BCH_STATUS0_SET_ALLONES_SHIFT            4
2274 #define BCH_STATUS0_SET_RSVD1_MASK               0xE0u
2275 #define BCH_STATUS0_SET_RSVD1_SHIFT              5
2276 #define BCH_STATUS0_SET_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD1_SHIFT))&BCH_STATUS0_SET_RSVD1_MASK)
2277 #define BCH_STATUS0_SET_STATUS_BLK0_MASK         0xFF00u
2278 #define BCH_STATUS0_SET_STATUS_BLK0_SHIFT        8
2279 #define BCH_STATUS0_SET_STATUS_BLK0(x)           (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_STATUS_BLK0_SHIFT))&BCH_STATUS0_SET_STATUS_BLK0_MASK)
2280 #define BCH_STATUS0_SET_COMPLETED_CE_MASK        0xF0000u
2281 #define BCH_STATUS0_SET_COMPLETED_CE_SHIFT       16
2282 #define BCH_STATUS0_SET_COMPLETED_CE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_COMPLETED_CE_SHIFT))&BCH_STATUS0_SET_COMPLETED_CE_MASK)
2283 #define BCH_STATUS0_SET_HANDLE_MASK              0xFFF00000u
2284 #define BCH_STATUS0_SET_HANDLE_SHIFT             20
2285 #define BCH_STATUS0_SET_HANDLE(x)                (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_HANDLE_SHIFT))&BCH_STATUS0_SET_HANDLE_MASK)
2286 /* STATUS0_CLR Bit Fields */
2287 #define BCH_STATUS0_CLR_RSVD0_MASK               0x3u
2288 #define BCH_STATUS0_CLR_RSVD0_SHIFT              0
2289 #define BCH_STATUS0_CLR_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD0_SHIFT))&BCH_STATUS0_CLR_RSVD0_MASK)
2290 #define BCH_STATUS0_CLR_UNCORRECTABLE_MASK       0x4u
2291 #define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT      2
2292 #define BCH_STATUS0_CLR_CORRECTED_MASK           0x8u
2293 #define BCH_STATUS0_CLR_CORRECTED_SHIFT          3
2294 #define BCH_STATUS0_CLR_ALLONES_MASK             0x10u
2295 #define BCH_STATUS0_CLR_ALLONES_SHIFT            4
2296 #define BCH_STATUS0_CLR_RSVD1_MASK               0xE0u
2297 #define BCH_STATUS0_CLR_RSVD1_SHIFT              5
2298 #define BCH_STATUS0_CLR_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD1_SHIFT))&BCH_STATUS0_CLR_RSVD1_MASK)
2299 #define BCH_STATUS0_CLR_STATUS_BLK0_MASK         0xFF00u
2300 #define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT        8
2301 #define BCH_STATUS0_CLR_STATUS_BLK0(x)           (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_STATUS_BLK0_SHIFT))&BCH_STATUS0_CLR_STATUS_BLK0_MASK)
2302 #define BCH_STATUS0_CLR_COMPLETED_CE_MASK        0xF0000u
2303 #define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT       16
2304 #define BCH_STATUS0_CLR_COMPLETED_CE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_COMPLETED_CE_SHIFT))&BCH_STATUS0_CLR_COMPLETED_CE_MASK)
2305 #define BCH_STATUS0_CLR_HANDLE_MASK              0xFFF00000u
2306 #define BCH_STATUS0_CLR_HANDLE_SHIFT             20
2307 #define BCH_STATUS0_CLR_HANDLE(x)                (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_HANDLE_SHIFT))&BCH_STATUS0_CLR_HANDLE_MASK)
2308 /* STATUS0_TOG Bit Fields */
2309 #define BCH_STATUS0_TOG_RSVD0_MASK               0x3u
2310 #define BCH_STATUS0_TOG_RSVD0_SHIFT              0
2311 #define BCH_STATUS0_TOG_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD0_SHIFT))&BCH_STATUS0_TOG_RSVD0_MASK)
2312 #define BCH_STATUS0_TOG_UNCORRECTABLE_MASK       0x4u
2313 #define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT      2
2314 #define BCH_STATUS0_TOG_CORRECTED_MASK           0x8u
2315 #define BCH_STATUS0_TOG_CORRECTED_SHIFT          3
2316 #define BCH_STATUS0_TOG_ALLONES_MASK             0x10u
2317 #define BCH_STATUS0_TOG_ALLONES_SHIFT            4
2318 #define BCH_STATUS0_TOG_RSVD1_MASK               0xE0u
2319 #define BCH_STATUS0_TOG_RSVD1_SHIFT              5
2320 #define BCH_STATUS0_TOG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD1_SHIFT))&BCH_STATUS0_TOG_RSVD1_MASK)
2321 #define BCH_STATUS0_TOG_STATUS_BLK0_MASK         0xFF00u
2322 #define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT        8
2323 #define BCH_STATUS0_TOG_STATUS_BLK0(x)           (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_STATUS_BLK0_SHIFT))&BCH_STATUS0_TOG_STATUS_BLK0_MASK)
2324 #define BCH_STATUS0_TOG_COMPLETED_CE_MASK        0xF0000u
2325 #define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT       16
2326 #define BCH_STATUS0_TOG_COMPLETED_CE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_COMPLETED_CE_SHIFT))&BCH_STATUS0_TOG_COMPLETED_CE_MASK)
2327 #define BCH_STATUS0_TOG_HANDLE_MASK              0xFFF00000u
2328 #define BCH_STATUS0_TOG_HANDLE_SHIFT             20
2329 #define BCH_STATUS0_TOG_HANDLE(x)                (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_HANDLE_SHIFT))&BCH_STATUS0_TOG_HANDLE_MASK)
2330 /* MODE Bit Fields */
2331 #define BCH_MODE_ERASE_THRESHOLD_MASK            0xFFu
2332 #define BCH_MODE_ERASE_THRESHOLD_SHIFT           0
2333 #define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x))<<BCH_MODE_ERASE_THRESHOLD_SHIFT))&BCH_MODE_ERASE_THRESHOLD_MASK)
2334 #define BCH_MODE_RSVD_MASK                       0xFFFFFF00u
2335 #define BCH_MODE_RSVD_SHIFT                      8
2336 #define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x))<<BCH_MODE_RSVD_SHIFT))&BCH_MODE_RSVD_MASK)
2337 /* MODE_SET Bit Fields */
2338 #define BCH_MODE_SET_ERASE_THRESHOLD_MASK        0xFFu
2339 #define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT       0
2340 #define BCH_MODE_SET_ERASE_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_ERASE_THRESHOLD_SHIFT))&BCH_MODE_SET_ERASE_THRESHOLD_MASK)
2341 #define BCH_MODE_SET_RSVD_MASK                   0xFFFFFF00u
2342 #define BCH_MODE_SET_RSVD_SHIFT                  8
2343 #define BCH_MODE_SET_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_RSVD_SHIFT))&BCH_MODE_SET_RSVD_MASK)
2344 /* MODE_CLR Bit Fields */
2345 #define BCH_MODE_CLR_ERASE_THRESHOLD_MASK        0xFFu
2346 #define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT       0
2347 #define BCH_MODE_CLR_ERASE_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT))&BCH_MODE_CLR_ERASE_THRESHOLD_MASK)
2348 #define BCH_MODE_CLR_RSVD_MASK                   0xFFFFFF00u
2349 #define BCH_MODE_CLR_RSVD_SHIFT                  8
2350 #define BCH_MODE_CLR_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_RSVD_SHIFT))&BCH_MODE_CLR_RSVD_MASK)
2351 /* MODE_TOG Bit Fields */
2352 #define BCH_MODE_TOG_ERASE_THRESHOLD_MASK        0xFFu
2353 #define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT       0
2354 #define BCH_MODE_TOG_ERASE_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT))&BCH_MODE_TOG_ERASE_THRESHOLD_MASK)
2355 #define BCH_MODE_TOG_RSVD_MASK                   0xFFFFFF00u
2356 #define BCH_MODE_TOG_RSVD_SHIFT                  8
2357 #define BCH_MODE_TOG_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_RSVD_SHIFT))&BCH_MODE_TOG_RSVD_MASK)
2358 /* ENCODEPTR Bit Fields */
2359 #define BCH_ENCODEPTR_ADDR_MASK                  0xFFFFFFFFu
2360 #define BCH_ENCODEPTR_ADDR_SHIFT                 0
2361 #define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_ADDR_SHIFT))&BCH_ENCODEPTR_ADDR_MASK)
2362 /* ENCODEPTR_SET Bit Fields */
2363 #define BCH_ENCODEPTR_SET_ADDR_MASK              0xFFFFFFFFu
2364 #define BCH_ENCODEPTR_SET_ADDR_SHIFT             0
2365 #define BCH_ENCODEPTR_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_SET_ADDR_SHIFT))&BCH_ENCODEPTR_SET_ADDR_MASK)
2366 /* ENCODEPTR_CLR Bit Fields */
2367 #define BCH_ENCODEPTR_CLR_ADDR_MASK              0xFFFFFFFFu
2368 #define BCH_ENCODEPTR_CLR_ADDR_SHIFT             0
2369 #define BCH_ENCODEPTR_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_CLR_ADDR_SHIFT))&BCH_ENCODEPTR_CLR_ADDR_MASK)
2370 /* ENCODEPTR_TOG Bit Fields */
2371 #define BCH_ENCODEPTR_TOG_ADDR_MASK              0xFFFFFFFFu
2372 #define BCH_ENCODEPTR_TOG_ADDR_SHIFT             0
2373 #define BCH_ENCODEPTR_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_TOG_ADDR_SHIFT))&BCH_ENCODEPTR_TOG_ADDR_MASK)
2374 /* DATAPTR Bit Fields */
2375 #define BCH_DATAPTR_ADDR_MASK                    0xFFFFFFFFu
2376 #define BCH_DATAPTR_ADDR_SHIFT                   0
2377 #define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_ADDR_SHIFT))&BCH_DATAPTR_ADDR_MASK)
2378 /* DATAPTR_SET Bit Fields */
2379 #define BCH_DATAPTR_SET_ADDR_MASK                0xFFFFFFFFu
2380 #define BCH_DATAPTR_SET_ADDR_SHIFT               0
2381 #define BCH_DATAPTR_SET_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_SET_ADDR_SHIFT))&BCH_DATAPTR_SET_ADDR_MASK)
2382 /* DATAPTR_CLR Bit Fields */
2383 #define BCH_DATAPTR_CLR_ADDR_MASK                0xFFFFFFFFu
2384 #define BCH_DATAPTR_CLR_ADDR_SHIFT               0
2385 #define BCH_DATAPTR_CLR_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_CLR_ADDR_SHIFT))&BCH_DATAPTR_CLR_ADDR_MASK)
2386 /* DATAPTR_TOG Bit Fields */
2387 #define BCH_DATAPTR_TOG_ADDR_MASK                0xFFFFFFFFu
2388 #define BCH_DATAPTR_TOG_ADDR_SHIFT               0
2389 #define BCH_DATAPTR_TOG_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_TOG_ADDR_SHIFT))&BCH_DATAPTR_TOG_ADDR_MASK)
2390 /* METAPTR Bit Fields */
2391 #define BCH_METAPTR_ADDR_MASK                    0xFFFFFFFFu
2392 #define BCH_METAPTR_ADDR_SHIFT                   0
2393 #define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_ADDR_SHIFT))&BCH_METAPTR_ADDR_MASK)
2394 /* METAPTR_SET Bit Fields */
2395 #define BCH_METAPTR_SET_ADDR_MASK                0xFFFFFFFFu
2396 #define BCH_METAPTR_SET_ADDR_SHIFT               0
2397 #define BCH_METAPTR_SET_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_SET_ADDR_SHIFT))&BCH_METAPTR_SET_ADDR_MASK)
2398 /* METAPTR_CLR Bit Fields */
2399 #define BCH_METAPTR_CLR_ADDR_MASK                0xFFFFFFFFu
2400 #define BCH_METAPTR_CLR_ADDR_SHIFT               0
2401 #define BCH_METAPTR_CLR_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_CLR_ADDR_SHIFT))&BCH_METAPTR_CLR_ADDR_MASK)
2402 /* METAPTR_TOG Bit Fields */
2403 #define BCH_METAPTR_TOG_ADDR_MASK                0xFFFFFFFFu
2404 #define BCH_METAPTR_TOG_ADDR_SHIFT               0
2405 #define BCH_METAPTR_TOG_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_TOG_ADDR_SHIFT))&BCH_METAPTR_TOG_ADDR_MASK)
2406 /* LAYOUTSELECT Bit Fields */
2407 #define BCH_LAYOUTSELECT_CS0_SELECT_MASK         0x3u
2408 #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        0
2409 #define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS0_SELECT_MASK)
2410 #define BCH_LAYOUTSELECT_CS1_SELECT_MASK         0xCu
2411 #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        2
2412 #define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS1_SELECT_MASK)
2413 #define BCH_LAYOUTSELECT_CS2_SELECT_MASK         0x30u
2414 #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        4
2415 #define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS2_SELECT_MASK)
2416 #define BCH_LAYOUTSELECT_CS3_SELECT_MASK         0xC0u
2417 #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        6
2418 #define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS3_SELECT_MASK)
2419 #define BCH_LAYOUTSELECT_CS4_SELECT_MASK         0x300u
2420 #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        8
2421 #define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS4_SELECT_MASK)
2422 #define BCH_LAYOUTSELECT_CS5_SELECT_MASK         0xC00u
2423 #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        10
2424 #define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS5_SELECT_MASK)
2425 #define BCH_LAYOUTSELECT_CS6_SELECT_MASK         0x3000u
2426 #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        12
2427 #define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS6_SELECT_MASK)
2428 #define BCH_LAYOUTSELECT_CS7_SELECT_MASK         0xC000u
2429 #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        14
2430 #define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS7_SELECT_MASK)
2431 #define BCH_LAYOUTSELECT_CS8_SELECT_MASK         0x30000u
2432 #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        16
2433 #define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS8_SELECT_MASK)
2434 #define BCH_LAYOUTSELECT_CS9_SELECT_MASK         0xC0000u
2435 #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        18
2436 #define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS9_SELECT_MASK)
2437 #define BCH_LAYOUTSELECT_CS10_SELECT_MASK        0x300000u
2438 #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       20
2439 #define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS10_SELECT_MASK)
2440 #define BCH_LAYOUTSELECT_CS11_SELECT_MASK        0xC00000u
2441 #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       22
2442 #define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS11_SELECT_MASK)
2443 #define BCH_LAYOUTSELECT_CS12_SELECT_MASK        0x3000000u
2444 #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       24
2445 #define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS12_SELECT_MASK)
2446 #define BCH_LAYOUTSELECT_CS13_SELECT_MASK        0xC000000u
2447 #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       26
2448 #define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS13_SELECT_MASK)
2449 #define BCH_LAYOUTSELECT_CS14_SELECT_MASK        0x30000000u
2450 #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       28
2451 #define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS14_SELECT_MASK)
2452 #define BCH_LAYOUTSELECT_CS15_SELECT_MASK        0xC0000000u
2453 #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       30
2454 #define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS15_SELECT_MASK)
2455 /* LAYOUTSELECT_SET Bit Fields */
2456 #define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK     0x3u
2457 #define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT    0
2458 #define BCH_LAYOUTSELECT_SET_CS0_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK)
2459 #define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK     0xCu
2460 #define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT    2
2461 #define BCH_LAYOUTSELECT_SET_CS1_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK)
2462 #define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK     0x30u
2463 #define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT    4
2464 #define BCH_LAYOUTSELECT_SET_CS2_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK)
2465 #define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK     0xC0u
2466 #define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT    6
2467 #define BCH_LAYOUTSELECT_SET_CS3_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK)
2468 #define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK     0x300u
2469 #define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT    8
2470 #define BCH_LAYOUTSELECT_SET_CS4_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK)
2471 #define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK     0xC00u
2472 #define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT    10
2473 #define BCH_LAYOUTSELECT_SET_CS5_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK)
2474 #define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK     0x3000u
2475 #define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT    12
2476 #define BCH_LAYOUTSELECT_SET_CS6_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK)
2477 #define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK     0xC000u
2478 #define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT    14
2479 #define BCH_LAYOUTSELECT_SET_CS7_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK)
2480 #define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK     0x30000u
2481 #define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT    16
2482 #define BCH_LAYOUTSELECT_SET_CS8_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK)
2483 #define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK     0xC0000u
2484 #define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT    18
2485 #define BCH_LAYOUTSELECT_SET_CS9_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK)
2486 #define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK    0x300000u
2487 #define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT   20
2488 #define BCH_LAYOUTSELECT_SET_CS10_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK)
2489 #define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK    0xC00000u
2490 #define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT   22
2491 #define BCH_LAYOUTSELECT_SET_CS11_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK)
2492 #define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK    0x3000000u
2493 #define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT   24
2494 #define BCH_LAYOUTSELECT_SET_CS12_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK)
2495 #define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK    0xC000000u
2496 #define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT   26
2497 #define BCH_LAYOUTSELECT_SET_CS13_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK)
2498 #define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK    0x30000000u
2499 #define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT   28
2500 #define BCH_LAYOUTSELECT_SET_CS14_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK)
2501 #define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK    0xC0000000u
2502 #define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT   30
2503 #define BCH_LAYOUTSELECT_SET_CS15_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK)
2504 /* LAYOUTSELECT_CLR Bit Fields */
2505 #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK     0x3u
2506 #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT    0
2507 #define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK)
2508 #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK     0xCu
2509 #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT    2
2510 #define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK)
2511 #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK     0x30u
2512 #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT    4
2513 #define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK)
2514 #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK     0xC0u
2515 #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT    6
2516 #define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK)
2517 #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK     0x300u
2518 #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT    8
2519 #define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK)
2520 #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK     0xC00u
2521 #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT    10
2522 #define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK)
2523 #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK     0x3000u
2524 #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT    12
2525 #define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK)
2526 #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK     0xC000u
2527 #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT    14
2528 #define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK)
2529 #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK     0x30000u
2530 #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT    16
2531 #define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK)
2532 #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK     0xC0000u
2533 #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT    18
2534 #define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK)
2535 #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK    0x300000u
2536 #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT   20
2537 #define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK)
2538 #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK    0xC00000u
2539 #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT   22
2540 #define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK)
2541 #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK    0x3000000u
2542 #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT   24
2543 #define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK)
2544 #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK    0xC000000u
2545 #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT   26
2546 #define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK)
2547 #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK    0x30000000u
2548 #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT   28
2549 #define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK)
2550 #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK    0xC0000000u
2551 #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT   30
2552 #define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK)
2553 /* LAYOUTSELECT_TOG Bit Fields */
2554 #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK     0x3u
2555 #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT    0
2556 #define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK)
2557 #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK     0xCu
2558 #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT    2
2559 #define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK)
2560 #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK     0x30u
2561 #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT    4
2562 #define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK)
2563 #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK     0xC0u
2564 #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT    6
2565 #define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK)
2566 #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK     0x300u
2567 #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT    8
2568 #define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK)
2569 #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK     0xC00u
2570 #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT    10
2571 #define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK)
2572 #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK     0x3000u
2573 #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT    12
2574 #define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK)
2575 #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK     0xC000u
2576 #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT    14
2577 #define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK)
2578 #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK     0x30000u
2579 #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT    16
2580 #define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK)
2581 #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK     0xC0000u
2582 #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT    18
2583 #define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK)
2584 #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK    0x300000u
2585 #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT   20
2586 #define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK)
2587 #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK    0xC00000u
2588 #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT   22
2589 #define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK)
2590 #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK    0x3000000u
2591 #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT   24
2592 #define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK)
2593 #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK    0xC000000u
2594 #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT   26
2595 #define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK)
2596 #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK    0x30000000u
2597 #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT   28
2598 #define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK)
2599 #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK    0xC0000000u
2600 #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT   30
2601 #define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK)
2602 /* FLASH0LAYOUT0 Bit Fields */
2603 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2604 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       0
2605 #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
2606 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2607 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT    10
2608 #define BCH_FLASH0LAYOUT0_ECC0_MASK              0xF800u
2609 #define BCH_FLASH0LAYOUT0_ECC0_SHIFT             11
2610 #define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_ECC0_MASK)
2611 #define BCH_FLASH0LAYOUT0_META_SIZE_MASK         0xFF0000u
2612 #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        16
2613 #define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_META_SIZE_MASK)
2614 #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           0xFF000000u
2615 #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          24
2616 #define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
2617 /* FLASH0LAYOUT0_SET Bit Fields */
2618 #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2619 #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2620 #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK)
2621 #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2622 #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2623 #define BCH_FLASH0LAYOUT0_SET_ECC0_MASK          0xF800u
2624 #define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT         11
2625 #define BCH_FLASH0LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_SET_ECC0_MASK)
2626 #define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2627 #define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT    16
2628 #define BCH_FLASH0LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK)
2629 #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2630 #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT      24
2631 #define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK)
2632 /* FLASH0LAYOUT0_CLR Bit Fields */
2633 #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2634 #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2635 #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK)
2636 #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2637 #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2638 #define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK          0xF800u
2639 #define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT         11
2640 #define BCH_FLASH0LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_CLR_ECC0_MASK)
2641 #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2642 #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT    16
2643 #define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK)
2644 #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2645 #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT      24
2646 #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK)
2647 /* FLASH0LAYOUT0_TOG Bit Fields */
2648 #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2649 #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2650 #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK)
2651 #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2652 #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2653 #define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK          0xF800u
2654 #define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT         11
2655 #define BCH_FLASH0LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_TOG_ECC0_MASK)
2656 #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2657 #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT    16
2658 #define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK)
2659 #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2660 #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT      24
2661 #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK)
2662 /* FLASH0LAYOUT1 Bit Fields */
2663 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2664 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       0
2665 #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
2666 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2667 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT    10
2668 #define BCH_FLASH0LAYOUT1_ECCN_MASK              0xF800u
2669 #define BCH_FLASH0LAYOUT1_ECCN_SHIFT             11
2670 #define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_ECCN_MASK)
2671 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2672 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        16
2673 #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
2674 /* FLASH0LAYOUT1_SET Bit Fields */
2675 #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2676 #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2677 #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK)
2678 #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2679 #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2680 #define BCH_FLASH0LAYOUT1_SET_ECCN_MASK          0xF800u
2681 #define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT         11
2682 #define BCH_FLASH0LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_SET_ECCN_MASK)
2683 #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2684 #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2685 #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK)
2686 /* FLASH0LAYOUT1_CLR Bit Fields */
2687 #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2688 #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2689 #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK)
2690 #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2691 #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2692 #define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK          0xF800u
2693 #define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT         11
2694 #define BCH_FLASH0LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_CLR_ECCN_MASK)
2695 #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2696 #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2697 #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK)
2698 /* FLASH0LAYOUT1_TOG Bit Fields */
2699 #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2700 #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2701 #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK)
2702 #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2703 #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2704 #define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK          0xF800u
2705 #define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT         11
2706 #define BCH_FLASH0LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_TOG_ECCN_MASK)
2707 #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2708 #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2709 #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK)
2710 /* FLASH1LAYOUT0 Bit Fields */
2711 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2712 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       0
2713 #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
2714 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2715 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT    10
2716 #define BCH_FLASH1LAYOUT0_ECC0_MASK              0xF800u
2717 #define BCH_FLASH1LAYOUT0_ECC0_SHIFT             11
2718 #define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_ECC0_MASK)
2719 #define BCH_FLASH1LAYOUT0_META_SIZE_MASK         0xFF0000u
2720 #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        16
2721 #define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_META_SIZE_MASK)
2722 #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           0xFF000000u
2723 #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          24
2724 #define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
2725 /* FLASH1LAYOUT0_SET Bit Fields */
2726 #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2727 #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2728 #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK)
2729 #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2730 #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2731 #define BCH_FLASH1LAYOUT0_SET_ECC0_MASK          0xF800u
2732 #define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT         11
2733 #define BCH_FLASH1LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_SET_ECC0_MASK)
2734 #define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2735 #define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT    16
2736 #define BCH_FLASH1LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK)
2737 #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2738 #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT      24
2739 #define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK)
2740 /* FLASH1LAYOUT0_CLR Bit Fields */
2741 #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2742 #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2743 #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK)
2744 #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2745 #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2746 #define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK          0xF800u
2747 #define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT         11
2748 #define BCH_FLASH1LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_CLR_ECC0_MASK)
2749 #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2750 #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT    16
2751 #define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK)
2752 #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2753 #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT      24
2754 #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK)
2755 /* FLASH1LAYOUT0_TOG Bit Fields */
2756 #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2757 #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2758 #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK)
2759 #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2760 #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2761 #define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK          0xF800u
2762 #define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT         11
2763 #define BCH_FLASH1LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_TOG_ECC0_MASK)
2764 #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2765 #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT    16
2766 #define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK)
2767 #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2768 #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT      24
2769 #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK)
2770 /* FLASH1LAYOUT1 Bit Fields */
2771 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2772 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       0
2773 #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
2774 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2775 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT    10
2776 #define BCH_FLASH1LAYOUT1_ECCN_MASK              0xF800u
2777 #define BCH_FLASH1LAYOUT1_ECCN_SHIFT             11
2778 #define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_ECCN_MASK)
2779 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2780 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        16
2781 #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
2782 /* FLASH1LAYOUT1_SET Bit Fields */
2783 #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2784 #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2785 #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK)
2786 #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2787 #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2788 #define BCH_FLASH1LAYOUT1_SET_ECCN_MASK          0xF800u
2789 #define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT         11
2790 #define BCH_FLASH1LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_SET_ECCN_MASK)
2791 #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2792 #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2793 #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK)
2794 /* FLASH1LAYOUT1_CLR Bit Fields */
2795 #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2796 #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2797 #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK)
2798 #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2799 #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2800 #define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK          0xF800u
2801 #define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT         11
2802 #define BCH_FLASH1LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_CLR_ECCN_MASK)
2803 #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2804 #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2805 #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK)
2806 /* FLASH1LAYOUT1_TOG Bit Fields */
2807 #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2808 #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2809 #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK)
2810 #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2811 #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2812 #define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK          0xF800u
2813 #define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT         11
2814 #define BCH_FLASH1LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_TOG_ECCN_MASK)
2815 #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2816 #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2817 #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK)
2818 /* FLASH2LAYOUT0 Bit Fields */
2819 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2820 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       0
2821 #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
2822 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2823 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT    10
2824 #define BCH_FLASH2LAYOUT0_ECC0_MASK              0xF800u
2825 #define BCH_FLASH2LAYOUT0_ECC0_SHIFT             11
2826 #define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_ECC0_MASK)
2827 #define BCH_FLASH2LAYOUT0_META_SIZE_MASK         0xFF0000u
2828 #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        16
2829 #define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_META_SIZE_MASK)
2830 #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           0xFF000000u
2831 #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          24
2832 #define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
2833 /* FLASH2LAYOUT0_SET Bit Fields */
2834 #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2835 #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2836 #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK)
2837 #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2838 #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2839 #define BCH_FLASH2LAYOUT0_SET_ECC0_MASK          0xF800u
2840 #define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT         11
2841 #define BCH_FLASH2LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_SET_ECC0_MASK)
2842 #define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2843 #define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT    16
2844 #define BCH_FLASH2LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK)
2845 #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2846 #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT      24
2847 #define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK)
2848 /* FLASH2LAYOUT0_CLR Bit Fields */
2849 #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2850 #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2851 #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK)
2852 #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2853 #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2854 #define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK          0xF800u
2855 #define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT         11
2856 #define BCH_FLASH2LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_CLR_ECC0_MASK)
2857 #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2858 #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT    16
2859 #define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK)
2860 #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2861 #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT      24
2862 #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK)
2863 /* FLASH2LAYOUT0_TOG Bit Fields */
2864 #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2865 #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2866 #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK)
2867 #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2868 #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2869 #define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK          0xF800u
2870 #define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT         11
2871 #define BCH_FLASH2LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_TOG_ECC0_MASK)
2872 #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2873 #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT    16
2874 #define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK)
2875 #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2876 #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT      24
2877 #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK)
2878 /* FLASH2LAYOUT1 Bit Fields */
2879 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2880 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       0
2881 #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
2882 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2883 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT    10
2884 #define BCH_FLASH2LAYOUT1_ECCN_MASK              0xF800u
2885 #define BCH_FLASH2LAYOUT1_ECCN_SHIFT             11
2886 #define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_ECCN_MASK)
2887 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2888 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        16
2889 #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
2890 /* FLASH2LAYOUT1_SET Bit Fields */
2891 #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2892 #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2893 #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK)
2894 #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2895 #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2896 #define BCH_FLASH2LAYOUT1_SET_ECCN_MASK          0xF800u
2897 #define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT         11
2898 #define BCH_FLASH2LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_SET_ECCN_MASK)
2899 #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2900 #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2901 #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK)
2902 /* FLASH2LAYOUT1_CLR Bit Fields */
2903 #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2904 #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2905 #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK)
2906 #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2907 #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2908 #define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK          0xF800u
2909 #define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT         11
2910 #define BCH_FLASH2LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_CLR_ECCN_MASK)
2911 #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2912 #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2913 #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK)
2914 /* FLASH2LAYOUT1_TOG Bit Fields */
2915 #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2916 #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2917 #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK)
2918 #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2919 #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2920 #define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK          0xF800u
2921 #define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT         11
2922 #define BCH_FLASH2LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_TOG_ECCN_MASK)
2923 #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2924 #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2925 #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK)
2926 /* FLASH3LAYOUT0 Bit Fields */
2927 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2928 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       0
2929 #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
2930 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2931 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT    10
2932 #define BCH_FLASH3LAYOUT0_ECC0_MASK              0xF800u
2933 #define BCH_FLASH3LAYOUT0_ECC0_SHIFT             11
2934 #define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_ECC0_MASK)
2935 #define BCH_FLASH3LAYOUT0_META_SIZE_MASK         0xFF0000u
2936 #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        16
2937 #define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_META_SIZE_MASK)
2938 #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           0xFF000000u
2939 #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          24
2940 #define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
2941 /* FLASH3LAYOUT0_SET Bit Fields */
2942 #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2943 #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2944 #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK)
2945 #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2946 #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2947 #define BCH_FLASH3LAYOUT0_SET_ECC0_MASK          0xF800u
2948 #define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT         11
2949 #define BCH_FLASH3LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_SET_ECC0_MASK)
2950 #define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2951 #define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT    16
2952 #define BCH_FLASH3LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK)
2953 #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2954 #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT      24
2955 #define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK)
2956 /* FLASH3LAYOUT0_CLR Bit Fields */
2957 #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2958 #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2959 #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK)
2960 #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2961 #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2962 #define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK          0xF800u
2963 #define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT         11
2964 #define BCH_FLASH3LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_CLR_ECC0_MASK)
2965 #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2966 #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT    16
2967 #define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK)
2968 #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2969 #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT      24
2970 #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK)
2971 /* FLASH3LAYOUT0_TOG Bit Fields */
2972 #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2973 #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2974 #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK)
2975 #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2976 #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2977 #define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK          0xF800u
2978 #define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT         11
2979 #define BCH_FLASH3LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_TOG_ECC0_MASK)
2980 #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2981 #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT    16
2982 #define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK)
2983 #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2984 #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT      24
2985 #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK)
2986 /* FLASH3LAYOUT1 Bit Fields */
2987 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2988 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       0
2989 #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
2990 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2991 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT    10
2992 #define BCH_FLASH3LAYOUT1_ECCN_MASK              0xF800u
2993 #define BCH_FLASH3LAYOUT1_ECCN_SHIFT             11
2994 #define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_ECCN_MASK)
2995 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2996 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        16
2997 #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
2998 /* FLASH3LAYOUT1_SET Bit Fields */
2999 #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
3000 #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT   0
3001 #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK)
3002 #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
3003 #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
3004 #define BCH_FLASH3LAYOUT1_SET_ECCN_MASK          0xF800u
3005 #define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT         11
3006 #define BCH_FLASH3LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_SET_ECCN_MASK)
3007 #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
3008 #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT    16
3009 #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK)
3010 /* FLASH3LAYOUT1_CLR Bit Fields */
3011 #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
3012 #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
3013 #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK)
3014 #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
3015 #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
3016 #define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK          0xF800u
3017 #define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT         11
3018 #define BCH_FLASH3LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_CLR_ECCN_MASK)
3019 #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
3020 #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
3021 #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK)
3022 /* FLASH3LAYOUT1_TOG Bit Fields */
3023 #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
3024 #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
3025 #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK)
3026 #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
3027 #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
3028 #define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK          0xF800u
3029 #define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT         11
3030 #define BCH_FLASH3LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_TOG_ECCN_MASK)
3031 #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
3032 #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
3033 #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK)
3034 /* DEBUG0 Bit Fields */
3035 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         0x3Fu
3036 #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        0
3037 #define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
3038 #define BCH_DEBUG0_RSVD0_MASK                    0xC0u
3039 #define BCH_DEBUG0_RSVD0_SHIFT                   6
3040 #define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD0_SHIFT))&BCH_DEBUG0_RSVD0_MASK)
3041 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       0x100u
3042 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      8
3043 #define BCH_DEBUG0_KES_DEBUG_STALL_MASK          0x200u
3044 #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         9
3045 #define BCH_DEBUG0_KES_DEBUG_STEP_MASK           0x400u
3046 #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          10
3047 #define BCH_DEBUG0_KES_STANDALONE_MASK           0x800u
3048 #define BCH_DEBUG0_KES_STANDALONE_SHIFT          11
3049 #define BCH_DEBUG0_KES_DEBUG_KICK_MASK           0x1000u
3050 #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          12
3051 #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         0x2000u
3052 #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        13
3053 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   0x4000u
3054 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  14
3055 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     0x8000u
3056 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    15
3057 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3058 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3059 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3060 #define BCH_DEBUG0_RSVD1_MASK                    0xFE000000u
3061 #define BCH_DEBUG0_RSVD1_SHIFT                   25
3062 #define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD1_SHIFT))&BCH_DEBUG0_RSVD1_MASK)
3063 /* DEBUG0_SET Bit Fields */
3064 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK     0x3Fu
3065 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT    0
3066 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
3067 #define BCH_DEBUG0_SET_RSVD0_MASK                0xC0u
3068 #define BCH_DEBUG0_SET_RSVD0_SHIFT               6
3069 #define BCH_DEBUG0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD0_SHIFT))&BCH_DEBUG0_SET_RSVD0_MASK)
3070 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK   0x100u
3071 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT  8
3072 #define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK      0x200u
3073 #define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT     9
3074 #define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK       0x400u
3075 #define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT      10
3076 #define BCH_DEBUG0_SET_KES_STANDALONE_MASK       0x800u
3077 #define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT      11
3078 #define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK       0x1000u
3079 #define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT      12
3080 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK     0x2000u
3081 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT    13
3082 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u
3083 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14
3084 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK 0x8000u
3085 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT 15
3086 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3087 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3088 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3089 #define BCH_DEBUG0_SET_RSVD1_MASK                0xFE000000u
3090 #define BCH_DEBUG0_SET_RSVD1_SHIFT               25
3091 #define BCH_DEBUG0_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD1_SHIFT))&BCH_DEBUG0_SET_RSVD1_MASK)
3092 /* DEBUG0_CLR Bit Fields */
3093 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK     0x3Fu
3094 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT    0
3095 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
3096 #define BCH_DEBUG0_CLR_RSVD0_MASK                0xC0u
3097 #define BCH_DEBUG0_CLR_RSVD0_SHIFT               6
3098 #define BCH_DEBUG0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD0_SHIFT))&BCH_DEBUG0_CLR_RSVD0_MASK)
3099 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK   0x100u
3100 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT  8
3101 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK      0x200u
3102 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT     9
3103 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK       0x400u
3104 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT      10
3105 #define BCH_DEBUG0_CLR_KES_STANDALONE_MASK       0x800u
3106 #define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT      11
3107 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK       0x1000u
3108 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT      12
3109 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK     0x2000u
3110 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT    13
3111 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u
3112 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14
3113 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK 0x8000u
3114 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT 15
3115 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3116 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3117 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3118 #define BCH_DEBUG0_CLR_RSVD1_MASK                0xFE000000u
3119 #define BCH_DEBUG0_CLR_RSVD1_SHIFT               25
3120 #define BCH_DEBUG0_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD1_SHIFT))&BCH_DEBUG0_CLR_RSVD1_MASK)
3121 /* DEBUG0_TOG Bit Fields */
3122 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK     0x3Fu
3123 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT    0
3124 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
3125 #define BCH_DEBUG0_TOG_RSVD0_MASK                0xC0u
3126 #define BCH_DEBUG0_TOG_RSVD0_SHIFT               6
3127 #define BCH_DEBUG0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD0_SHIFT))&BCH_DEBUG0_TOG_RSVD0_MASK)
3128 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK   0x100u
3129 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT  8
3130 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK      0x200u
3131 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT     9
3132 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK       0x400u
3133 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT      10
3134 #define BCH_DEBUG0_TOG_KES_STANDALONE_MASK       0x800u
3135 #define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT      11
3136 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK       0x1000u
3137 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT      12
3138 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK     0x2000u
3139 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT    13
3140 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u
3141 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14
3142 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK 0x8000u
3143 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT 15
3144 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3145 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3146 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3147 #define BCH_DEBUG0_TOG_RSVD1_MASK                0xFE000000u
3148 #define BCH_DEBUG0_TOG_RSVD1_SHIFT               25
3149 #define BCH_DEBUG0_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD1_SHIFT))&BCH_DEBUG0_TOG_RSVD1_MASK)
3150 /* DBGKESREAD Bit Fields */
3151 #define BCH_DBGKESREAD_VALUES_MASK               0xFFFFFFFFu
3152 #define BCH_DBGKESREAD_VALUES_SHIFT              0
3153 #define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_VALUES_SHIFT))&BCH_DBGKESREAD_VALUES_MASK)
3154 /* DBGKESREAD_SET Bit Fields */
3155 #define BCH_DBGKESREAD_SET_VALUES_MASK           0xFFFFFFFFu
3156 #define BCH_DBGKESREAD_SET_VALUES_SHIFT          0
3157 #define BCH_DBGKESREAD_SET_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_SET_VALUES_SHIFT))&BCH_DBGKESREAD_SET_VALUES_MASK)
3158 /* DBGKESREAD_CLR Bit Fields */
3159 #define BCH_DBGKESREAD_CLR_VALUES_MASK           0xFFFFFFFFu
3160 #define BCH_DBGKESREAD_CLR_VALUES_SHIFT          0
3161 #define BCH_DBGKESREAD_CLR_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_CLR_VALUES_SHIFT))&BCH_DBGKESREAD_CLR_VALUES_MASK)
3162 /* DBGKESREAD_TOG Bit Fields */
3163 #define BCH_DBGKESREAD_TOG_VALUES_MASK           0xFFFFFFFFu
3164 #define BCH_DBGKESREAD_TOG_VALUES_SHIFT          0
3165 #define BCH_DBGKESREAD_TOG_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_TOG_VALUES_SHIFT))&BCH_DBGKESREAD_TOG_VALUES_MASK)
3166 /* DBGCSFEREAD Bit Fields */
3167 #define BCH_DBGCSFEREAD_VALUES_MASK              0xFFFFFFFFu
3168 #define BCH_DBGCSFEREAD_VALUES_SHIFT             0
3169 #define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_VALUES_SHIFT))&BCH_DBGCSFEREAD_VALUES_MASK)
3170 /* DBGCSFEREAD_SET Bit Fields */
3171 #define BCH_DBGCSFEREAD_SET_VALUES_MASK          0xFFFFFFFFu
3172 #define BCH_DBGCSFEREAD_SET_VALUES_SHIFT         0
3173 #define BCH_DBGCSFEREAD_SET_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_SET_VALUES_SHIFT))&BCH_DBGCSFEREAD_SET_VALUES_MASK)
3174 /* DBGCSFEREAD_CLR Bit Fields */
3175 #define BCH_DBGCSFEREAD_CLR_VALUES_MASK          0xFFFFFFFFu
3176 #define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT         0
3177 #define BCH_DBGCSFEREAD_CLR_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_CLR_VALUES_SHIFT))&BCH_DBGCSFEREAD_CLR_VALUES_MASK)
3178 /* DBGCSFEREAD_TOG Bit Fields */
3179 #define BCH_DBGCSFEREAD_TOG_VALUES_MASK          0xFFFFFFFFu
3180 #define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT         0
3181 #define BCH_DBGCSFEREAD_TOG_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_TOG_VALUES_SHIFT))&BCH_DBGCSFEREAD_TOG_VALUES_MASK)
3182 /* DBGSYNDGENREAD Bit Fields */
3183 #define BCH_DBGSYNDGENREAD_VALUES_MASK           0xFFFFFFFFu
3184 #define BCH_DBGSYNDGENREAD_VALUES_SHIFT          0
3185 #define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_VALUES_MASK)
3186 /* DBGSYNDGENREAD_SET Bit Fields */
3187 #define BCH_DBGSYNDGENREAD_SET_VALUES_MASK       0xFFFFFFFFu
3188 #define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT      0
3189 #define BCH_DBGSYNDGENREAD_SET_VALUES(x)         (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_SET_VALUES_MASK)
3190 /* DBGSYNDGENREAD_CLR Bit Fields */
3191 #define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK       0xFFFFFFFFu
3192 #define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT      0
3193 #define BCH_DBGSYNDGENREAD_CLR_VALUES(x)         (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_CLR_VALUES_MASK)
3194 /* DBGSYNDGENREAD_TOG Bit Fields */
3195 #define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK       0xFFFFFFFFu
3196 #define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT      0
3197 #define BCH_DBGSYNDGENREAD_TOG_VALUES(x)         (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_TOG_VALUES_MASK)
3198 /* DBGAHBMREAD Bit Fields */
3199 #define BCH_DBGAHBMREAD_VALUES_MASK              0xFFFFFFFFu
3200 #define BCH_DBGAHBMREAD_VALUES_SHIFT             0
3201 #define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_VALUES_SHIFT))&BCH_DBGAHBMREAD_VALUES_MASK)
3202 /* DBGAHBMREAD_SET Bit Fields */
3203 #define BCH_DBGAHBMREAD_SET_VALUES_MASK          0xFFFFFFFFu
3204 #define BCH_DBGAHBMREAD_SET_VALUES_SHIFT         0
3205 #define BCH_DBGAHBMREAD_SET_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_SET_VALUES_SHIFT))&BCH_DBGAHBMREAD_SET_VALUES_MASK)
3206 /* DBGAHBMREAD_CLR Bit Fields */
3207 #define BCH_DBGAHBMREAD_CLR_VALUES_MASK          0xFFFFFFFFu
3208 #define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT         0
3209 #define BCH_DBGAHBMREAD_CLR_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_CLR_VALUES_SHIFT))&BCH_DBGAHBMREAD_CLR_VALUES_MASK)
3210 /* DBGAHBMREAD_TOG Bit Fields */
3211 #define BCH_DBGAHBMREAD_TOG_VALUES_MASK          0xFFFFFFFFu
3212 #define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT         0
3213 #define BCH_DBGAHBMREAD_TOG_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_TOG_VALUES_SHIFT))&BCH_DBGAHBMREAD_TOG_VALUES_MASK)
3214 /* BLOCKNAME Bit Fields */
3215 #define BCH_BLOCKNAME_NAME_MASK                  0xFFFFFFFFu
3216 #define BCH_BLOCKNAME_NAME_SHIFT                 0
3217 #define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_NAME_SHIFT))&BCH_BLOCKNAME_NAME_MASK)
3218 /* BLOCKNAME_SET Bit Fields */
3219 #define BCH_BLOCKNAME_SET_NAME_MASK              0xFFFFFFFFu
3220 #define BCH_BLOCKNAME_SET_NAME_SHIFT             0
3221 #define BCH_BLOCKNAME_SET_NAME(x)                (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_SET_NAME_SHIFT))&BCH_BLOCKNAME_SET_NAME_MASK)
3222 /* BLOCKNAME_CLR Bit Fields */
3223 #define BCH_BLOCKNAME_CLR_NAME_MASK              0xFFFFFFFFu
3224 #define BCH_BLOCKNAME_CLR_NAME_SHIFT             0
3225 #define BCH_BLOCKNAME_CLR_NAME(x)                (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_CLR_NAME_SHIFT))&BCH_BLOCKNAME_CLR_NAME_MASK)
3226 /* BLOCKNAME_TOG Bit Fields */
3227 #define BCH_BLOCKNAME_TOG_NAME_MASK              0xFFFFFFFFu
3228 #define BCH_BLOCKNAME_TOG_NAME_SHIFT             0
3229 #define BCH_BLOCKNAME_TOG_NAME(x)                (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_TOG_NAME_SHIFT))&BCH_BLOCKNAME_TOG_NAME_MASK)
3230 /* VERSION Bit Fields */
3231 #define BCH_VERSION_STEP_MASK                    0xFFFFu
3232 #define BCH_VERSION_STEP_SHIFT                   0
3233 #define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_STEP_SHIFT))&BCH_VERSION_STEP_MASK)
3234 #define BCH_VERSION_MINOR_MASK                   0xFF0000u
3235 #define BCH_VERSION_MINOR_SHIFT                  16
3236 #define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MINOR_SHIFT))&BCH_VERSION_MINOR_MASK)
3237 #define BCH_VERSION_MAJOR_MASK                   0xFF000000u
3238 #define BCH_VERSION_MAJOR_SHIFT                  24
3239 #define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MAJOR_SHIFT))&BCH_VERSION_MAJOR_MASK)
3240 /* VERSION_SET Bit Fields */
3241 #define BCH_VERSION_SET_STEP_MASK                0xFFFFu
3242 #define BCH_VERSION_SET_STEP_SHIFT               0
3243 #define BCH_VERSION_SET_STEP(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_STEP_SHIFT))&BCH_VERSION_SET_STEP_MASK)
3244 #define BCH_VERSION_SET_MINOR_MASK               0xFF0000u
3245 #define BCH_VERSION_SET_MINOR_SHIFT              16
3246 #define BCH_VERSION_SET_MINOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MINOR_SHIFT))&BCH_VERSION_SET_MINOR_MASK)
3247 #define BCH_VERSION_SET_MAJOR_MASK               0xFF000000u
3248 #define BCH_VERSION_SET_MAJOR_SHIFT              24
3249 #define BCH_VERSION_SET_MAJOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MAJOR_SHIFT))&BCH_VERSION_SET_MAJOR_MASK)
3250 /* VERSION_CLR Bit Fields */
3251 #define BCH_VERSION_CLR_STEP_MASK                0xFFFFu
3252 #define BCH_VERSION_CLR_STEP_SHIFT               0
3253 #define BCH_VERSION_CLR_STEP(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_STEP_SHIFT))&BCH_VERSION_CLR_STEP_MASK)
3254 #define BCH_VERSION_CLR_MINOR_MASK               0xFF0000u
3255 #define BCH_VERSION_CLR_MINOR_SHIFT              16
3256 #define BCH_VERSION_CLR_MINOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MINOR_SHIFT))&BCH_VERSION_CLR_MINOR_MASK)
3257 #define BCH_VERSION_CLR_MAJOR_MASK               0xFF000000u
3258 #define BCH_VERSION_CLR_MAJOR_SHIFT              24
3259 #define BCH_VERSION_CLR_MAJOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MAJOR_SHIFT))&BCH_VERSION_CLR_MAJOR_MASK)
3260 /* VERSION_TOG Bit Fields */
3261 #define BCH_VERSION_TOG_STEP_MASK                0xFFFFu
3262 #define BCH_VERSION_TOG_STEP_SHIFT               0
3263 #define BCH_VERSION_TOG_STEP(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_STEP_SHIFT))&BCH_VERSION_TOG_STEP_MASK)
3264 #define BCH_VERSION_TOG_MINOR_MASK               0xFF0000u
3265 #define BCH_VERSION_TOG_MINOR_SHIFT              16
3266 #define BCH_VERSION_TOG_MINOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MINOR_SHIFT))&BCH_VERSION_TOG_MINOR_MASK)
3267 #define BCH_VERSION_TOG_MAJOR_MASK               0xFF000000u
3268 #define BCH_VERSION_TOG_MAJOR_SHIFT              24
3269 #define BCH_VERSION_TOG_MAJOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MAJOR_SHIFT))&BCH_VERSION_TOG_MAJOR_MASK)
3270 /* DEBUG1 Bit Fields */
3271 #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        0x1FFu
3272 #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       0
3273 #define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
3274 #define BCH_DEBUG1_RSVD_MASK                     0x7FFFFE00u
3275 #define BCH_DEBUG1_RSVD_SHIFT                    9
3276 #define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_RSVD_SHIFT))&BCH_DEBUG1_RSVD_MASK)
3277 #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       0x80000000u
3278 #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      31
3279 /* DEBUG1_SET Bit Fields */
3280 #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK    0x1FFu
3281 #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT   0
3282 #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK)
3283 #define BCH_DEBUG1_SET_RSVD_MASK                 0x7FFFFE00u
3284 #define BCH_DEBUG1_SET_RSVD_SHIFT                9
3285 #define BCH_DEBUG1_SET_RSVD(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_RSVD_SHIFT))&BCH_DEBUG1_SET_RSVD_MASK)
3286 #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK   0x80000000u
3287 #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT  31
3288 /* DEBUG1_CLR Bit Fields */
3289 #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK    0x1FFu
3290 #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT   0
3291 #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK)
3292 #define BCH_DEBUG1_CLR_RSVD_MASK                 0x7FFFFE00u
3293 #define BCH_DEBUG1_CLR_RSVD_SHIFT                9
3294 #define BCH_DEBUG1_CLR_RSVD(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_RSVD_SHIFT))&BCH_DEBUG1_CLR_RSVD_MASK)
3295 #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK   0x80000000u
3296 #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT  31
3297 /* DEBUG1_TOG Bit Fields */
3298 #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK    0x1FFu
3299 #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT   0
3300 #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK)
3301 #define BCH_DEBUG1_TOG_RSVD_MASK                 0x7FFFFE00u
3302 #define BCH_DEBUG1_TOG_RSVD_SHIFT                9
3303 #define BCH_DEBUG1_TOG_RSVD(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_RSVD_SHIFT))&BCH_DEBUG1_TOG_RSVD_MASK)
3304 #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK   0x80000000u
3305 #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT  31
3306 
3307 /*!
3308  * @}
3309  */ /* end of group BCH_Register_Masks */
3310 
3311 /* BCH - Peripheral instance base addresses */
3312 /** Peripheral BCH base address */
3313 #define BCH_BASE                                 (0x33004000u)
3314 /** Peripheral BCH base pointer */
3315 #define BCH                                      ((BCH_Type *)BCH_BASE)
3316 #define BCH_BASE_PTR                             (BCH)
3317 /** Array initializer of BCH peripheral base addresses */
3318 #define BCH_BASE_ADDRS                           { BCH_BASE }
3319 /** Array initializer of BCH peripheral base pointers */
3320 #define BCH_BASE_PTRS                            { BCH }
3321 /** Interrupt vectors for the BCH peripheral type */
3322 #define BCH_IRQS                                 { BCH_IRQn }
3323 /* ----------------------------------------------------------------------------
3324    -- BCH - Register accessor macros
3325    ---------------------------------------------------------------------------- */
3326 
3327 /*!
3328  * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros
3329  * @{
3330  */
3331 
3332 
3333 /* BCH - Register instance definitions */
3334 /* BCH */
3335 #define BCH_CTRL                                 BCH_CTRL_REG(BCH_BASE_PTR)
3336 #define BCH_CTRL_SET                             BCH_CTRL_SET_REG(BCH_BASE_PTR)
3337 #define BCH_CTRL_CLR                             BCH_CTRL_CLR_REG(BCH_BASE_PTR)
3338 #define BCH_CTRL_TOG                             BCH_CTRL_TOG_REG(BCH_BASE_PTR)
3339 #define BCH_STATUS0                              BCH_STATUS0_REG(BCH_BASE_PTR)
3340 #define BCH_STATUS0_SET                          BCH_STATUS0_SET_REG(BCH_BASE_PTR)
3341 #define BCH_STATUS0_CLR                          BCH_STATUS0_CLR_REG(BCH_BASE_PTR)
3342 #define BCH_STATUS0_TOG                          BCH_STATUS0_TOG_REG(BCH_BASE_PTR)
3343 #define BCH_MODE                                 BCH_MODE_REG(BCH_BASE_PTR)
3344 #define BCH_MODE_SET                             BCH_MODE_SET_REG(BCH_BASE_PTR)
3345 #define BCH_MODE_CLR                             BCH_MODE_CLR_REG(BCH_BASE_PTR)
3346 #define BCH_MODE_TOG                             BCH_MODE_TOG_REG(BCH_BASE_PTR)
3347 #define BCH_ENCODEPTR                            BCH_ENCODEPTR_REG(BCH_BASE_PTR)
3348 #define BCH_ENCODEPTR_SET                        BCH_ENCODEPTR_SET_REG(BCH_BASE_PTR)
3349 #define BCH_ENCODEPTR_CLR                        BCH_ENCODEPTR_CLR_REG(BCH_BASE_PTR)
3350 #define BCH_ENCODEPTR_TOG                        BCH_ENCODEPTR_TOG_REG(BCH_BASE_PTR)
3351 #define BCH_DATAPTR                              BCH_DATAPTR_REG(BCH_BASE_PTR)
3352 #define BCH_DATAPTR_SET                          BCH_DATAPTR_SET_REG(BCH_BASE_PTR)
3353 #define BCH_DATAPTR_CLR                          BCH_DATAPTR_CLR_REG(BCH_BASE_PTR)
3354 #define BCH_DATAPTR_TOG                          BCH_DATAPTR_TOG_REG(BCH_BASE_PTR)
3355 #define BCH_METAPTR                              BCH_METAPTR_REG(BCH_BASE_PTR)
3356 #define BCH_METAPTR_SET                          BCH_METAPTR_SET_REG(BCH_BASE_PTR)
3357 #define BCH_METAPTR_CLR                          BCH_METAPTR_CLR_REG(BCH_BASE_PTR)
3358 #define BCH_METAPTR_TOG                          BCH_METAPTR_TOG_REG(BCH_BASE_PTR)
3359 #define BCH_LAYOUTSELECT                         BCH_LAYOUTSELECT_REG(BCH_BASE_PTR)
3360 #define BCH_LAYOUTSELECT_SET                     BCH_LAYOUTSELECT_SET_REG(BCH_BASE_PTR)
3361 #define BCH_LAYOUTSELECT_CLR                     BCH_LAYOUTSELECT_CLR_REG(BCH_BASE_PTR)
3362 #define BCH_LAYOUTSELECT_TOG                     BCH_LAYOUTSELECT_TOG_REG(BCH_BASE_PTR)
3363 #define BCH_FLASH0LAYOUT0                        BCH_FLASH0LAYOUT0_REG(BCH_BASE_PTR)
3364 #define BCH_FLASH0LAYOUT0_SET                    BCH_FLASH0LAYOUT0_SET_REG(BCH_BASE_PTR)
3365 #define BCH_FLASH0LAYOUT0_CLR                    BCH_FLASH0LAYOUT0_CLR_REG(BCH_BASE_PTR)
3366 #define BCH_FLASH0LAYOUT0_TOG                    BCH_FLASH0LAYOUT0_TOG_REG(BCH_BASE_PTR)
3367 #define BCH_FLASH0LAYOUT1                        BCH_FLASH0LAYOUT1_REG(BCH_BASE_PTR)
3368 #define BCH_FLASH0LAYOUT1_SET                    BCH_FLASH0LAYOUT1_SET_REG(BCH_BASE_PTR)
3369 #define BCH_FLASH0LAYOUT1_CLR                    BCH_FLASH0LAYOUT1_CLR_REG(BCH_BASE_PTR)
3370 #define BCH_FLASH0LAYOUT1_TOG                    BCH_FLASH0LAYOUT1_TOG_REG(BCH_BASE_PTR)
3371 #define BCH_FLASH1LAYOUT0                        BCH_FLASH1LAYOUT0_REG(BCH_BASE_PTR)
3372 #define BCH_FLASH1LAYOUT0_SET                    BCH_FLASH1LAYOUT0_SET_REG(BCH_BASE_PTR)
3373 #define BCH_FLASH1LAYOUT0_CLR                    BCH_FLASH1LAYOUT0_CLR_REG(BCH_BASE_PTR)
3374 #define BCH_FLASH1LAYOUT0_TOG                    BCH_FLASH1LAYOUT0_TOG_REG(BCH_BASE_PTR)
3375 #define BCH_FLASH1LAYOUT1                        BCH_FLASH1LAYOUT1_REG(BCH_BASE_PTR)
3376 #define BCH_FLASH1LAYOUT1_SET                    BCH_FLASH1LAYOUT1_SET_REG(BCH_BASE_PTR)
3377 #define BCH_FLASH1LAYOUT1_CLR                    BCH_FLASH1LAYOUT1_CLR_REG(BCH_BASE_PTR)
3378 #define BCH_FLASH1LAYOUT1_TOG                    BCH_FLASH1LAYOUT1_TOG_REG(BCH_BASE_PTR)
3379 #define BCH_FLASH2LAYOUT0                        BCH_FLASH2LAYOUT0_REG(BCH_BASE_PTR)
3380 #define BCH_FLASH2LAYOUT0_SET                    BCH_FLASH2LAYOUT0_SET_REG(BCH_BASE_PTR)
3381 #define BCH_FLASH2LAYOUT0_CLR                    BCH_FLASH2LAYOUT0_CLR_REG(BCH_BASE_PTR)
3382 #define BCH_FLASH2LAYOUT0_TOG                    BCH_FLASH2LAYOUT0_TOG_REG(BCH_BASE_PTR)
3383 #define BCH_FLASH2LAYOUT1                        BCH_FLASH2LAYOUT1_REG(BCH_BASE_PTR)
3384 #define BCH_FLASH2LAYOUT1_SET                    BCH_FLASH2LAYOUT1_SET_REG(BCH_BASE_PTR)
3385 #define BCH_FLASH2LAYOUT1_CLR                    BCH_FLASH2LAYOUT1_CLR_REG(BCH_BASE_PTR)
3386 #define BCH_FLASH2LAYOUT1_TOG                    BCH_FLASH2LAYOUT1_TOG_REG(BCH_BASE_PTR)
3387 #define BCH_FLASH3LAYOUT0                        BCH_FLASH3LAYOUT0_REG(BCH_BASE_PTR)
3388 #define BCH_FLASH3LAYOUT0_SET                    BCH_FLASH3LAYOUT0_SET_REG(BCH_BASE_PTR)
3389 #define BCH_FLASH3LAYOUT0_CLR                    BCH_FLASH3LAYOUT0_CLR_REG(BCH_BASE_PTR)
3390 #define BCH_FLASH3LAYOUT0_TOG                    BCH_FLASH3LAYOUT0_TOG_REG(BCH_BASE_PTR)
3391 #define BCH_FLASH3LAYOUT1                        BCH_FLASH3LAYOUT1_REG(BCH_BASE_PTR)
3392 #define BCH_FLASH3LAYOUT1_SET                    BCH_FLASH3LAYOUT1_SET_REG(BCH_BASE_PTR)
3393 #define BCH_FLASH3LAYOUT1_CLR                    BCH_FLASH3LAYOUT1_CLR_REG(BCH_BASE_PTR)
3394 #define BCH_FLASH3LAYOUT1_TOG                    BCH_FLASH3LAYOUT1_TOG_REG(BCH_BASE_PTR)
3395 #define BCH_DEBUG0                               BCH_DEBUG0_REG(BCH_BASE_PTR)
3396 #define BCH_DEBUG0_SET                           BCH_DEBUG0_SET_REG(BCH_BASE_PTR)
3397 #define BCH_DEBUG0_CLR                           BCH_DEBUG0_CLR_REG(BCH_BASE_PTR)
3398 #define BCH_DEBUG0_TOG                           BCH_DEBUG0_TOG_REG(BCH_BASE_PTR)
3399 #define BCH_DBGKESREAD                           BCH_DBGKESREAD_REG(BCH_BASE_PTR)
3400 #define BCH_DBGKESREAD_SET                       BCH_DBGKESREAD_SET_REG(BCH_BASE_PTR)
3401 #define BCH_DBGKESREAD_CLR                       BCH_DBGKESREAD_CLR_REG(BCH_BASE_PTR)
3402 #define BCH_DBGKESREAD_TOG                       BCH_DBGKESREAD_TOG_REG(BCH_BASE_PTR)
3403 #define BCH_DBGCSFEREAD                          BCH_DBGCSFEREAD_REG(BCH_BASE_PTR)
3404 #define BCH_DBGCSFEREAD_SET                      BCH_DBGCSFEREAD_SET_REG(BCH_BASE_PTR)
3405 #define BCH_DBGCSFEREAD_CLR                      BCH_DBGCSFEREAD_CLR_REG(BCH_BASE_PTR)
3406 #define BCH_DBGCSFEREAD_TOG                      BCH_DBGCSFEREAD_TOG_REG(BCH_BASE_PTR)
3407 #define BCH_DBGSYNDGENREAD                       BCH_DBGSYNDGENREAD_REG(BCH_BASE_PTR)
3408 #define BCH_DBGSYNDGENREAD_SET                   BCH_DBGSYNDGENREAD_SET_REG(BCH_BASE_PTR)
3409 #define BCH_DBGSYNDGENREAD_CLR                   BCH_DBGSYNDGENREAD_CLR_REG(BCH_BASE_PTR)
3410 #define BCH_DBGSYNDGENREAD_TOG                   BCH_DBGSYNDGENREAD_TOG_REG(BCH_BASE_PTR)
3411 #define BCH_DBGAHBMREAD                          BCH_DBGAHBMREAD_REG(BCH_BASE_PTR)
3412 #define BCH_DBGAHBMREAD_SET                      BCH_DBGAHBMREAD_SET_REG(BCH_BASE_PTR)
3413 #define BCH_DBGAHBMREAD_CLR                      BCH_DBGAHBMREAD_CLR_REG(BCH_BASE_PTR)
3414 #define BCH_DBGAHBMREAD_TOG                      BCH_DBGAHBMREAD_TOG_REG(BCH_BASE_PTR)
3415 #define BCH_BLOCKNAME                            BCH_BLOCKNAME_REG(BCH_BASE_PTR)
3416 #define BCH_BLOCKNAME_SET                        BCH_BLOCKNAME_SET_REG(BCH_BASE_PTR)
3417 #define BCH_BLOCKNAME_CLR                        BCH_BLOCKNAME_CLR_REG(BCH_BASE_PTR)
3418 #define BCH_BLOCKNAME_TOG                        BCH_BLOCKNAME_TOG_REG(BCH_BASE_PTR)
3419 #define BCH_VERSION                              BCH_VERSION_REG(BCH_BASE_PTR)
3420 #define BCH_VERSION_SET                          BCH_VERSION_SET_REG(BCH_BASE_PTR)
3421 #define BCH_VERSION_CLR                          BCH_VERSION_CLR_REG(BCH_BASE_PTR)
3422 #define BCH_VERSION_TOG                          BCH_VERSION_TOG_REG(BCH_BASE_PTR)
3423 #define BCH_DEBUG1                               BCH_DEBUG1_REG(BCH_BASE_PTR)
3424 #define BCH_DEBUG1_SET                           BCH_DEBUG1_SET_REG(BCH_BASE_PTR)
3425 #define BCH_DEBUG1_CLR                           BCH_DEBUG1_CLR_REG(BCH_BASE_PTR)
3426 #define BCH_DEBUG1_TOG                           BCH_DEBUG1_TOG_REG(BCH_BASE_PTR)
3427 /*!
3428  * @}
3429  */ /* end of group BCH_Register_Accessor_Macros */
3430 
3431 
3432 /*!
3433  * @}
3434  */ /* end of group BCH_Peripheral */
3435 
3436 /* ----------------------------------------------------------------------------
3437    -- CAN Peripheral Access Layer
3438    ---------------------------------------------------------------------------- */
3439 
3440 /*!
3441  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3442  * @{
3443  */
3444 
3445 /** CAN - Register Layout Typedef */
3446 typedef struct {
3447   __IO  uint32_t MCR;                                    /**< Module Configuration Register, offset: 0x0 */
3448   __IO  uint32_t CTRL1;                                  /**< Control 1 Register, offset: 0x4 */
3449   __IO  uint32_t TIMER;                                  /**< Free Running Timer Register, offset: 0x8 */
3450   uint8_t RESERVED_0[4];
3451   __IO  uint32_t RXMGMASK;                               /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
3452   __IO  uint32_t RX14MASK;                               /**< Rx Buffer 14 Mask Register, offset: 0x14 */
3453   __IO  uint32_t RX15MASK;                               /**< Rx Buffer 15 Mask Register, offset: 0x18 */
3454   __IO  uint32_t ECR;                                    /**< Error Counter Register, offset: 0x1C */
3455   __IO  uint32_t ESR1;                                   /**< Error and Status 1 Register, offset: 0x20 */
3456   __IO  uint32_t IMASK2;                                 /**< Interrupt Masks 2 Register, offset: 0x24 */
3457   __IO  uint32_t IMASK1;                                 /**< Interrupt Masks 1 Register, offset: 0x28 */
3458   __IO  uint32_t IFLAG2;                                 /**< Interrupt Flags 2 Register, offset: 0x2C */
3459   __IO  uint32_t IFLAG1;                                 /**< Interrupt Flags 1 Register, offset: 0x30 */
3460   __IO  uint32_t CTRL2;                                  /**< Control 2 Register, offset: 0x34 */
3461   __I   uint32_t ESR2;                                   /**< Error and Status 2 Register, offset: 0x38 */
3462   uint8_t RESERVED_1[8];
3463   __I   uint32_t CRCR;                                   /**< CRC Register, offset: 0x44 */
3464   __IO  uint32_t RXFGMASK;                               /**< Rx FIFO Global Mask Register, offset: 0x48 */
3465   __I   uint32_t RXFIR;                                  /**< Rx FIFO Information Register, offset: 0x4C */
3466   uint8_t RESERVED_2[48];
3467   struct {                                         /* offset: 0x80, array step: 0x10 */
3468   __IO    uint32_t CS;                                     /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3469   __IO    uint32_t ID;                                     /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3470   __IO    uint32_t WORD0;                                  /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
3471   __IO    uint32_t WORD1;                                  /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
3472  } MB[64];
3473   uint8_t RESERVED_3[1024];
3474   __IO  uint32_t RXIMR[64];                              /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
3475   uint8_t RESERVED_4[96];
3476   __IO  uint32_t GFWR;                                   /**< Glitch Filter Width Registers, offset: 0x9E0 */
3477 } CAN_Type, *CAN_MemMapPtr;
3478 /* ----------------------------------------------------------------------------
3479    -- CAN - Register accessor macros
3480    ---------------------------------------------------------------------------- */
3481 
3482 /*!
3483  * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
3484  * @{
3485  */
3486 
3487 
3488 /* CAN - Register accessors */
3489 #define CAN_MCR_REG(base)                        ((base)->MCR)
3490 #define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
3491 #define CAN_TIMER_REG(base)                      ((base)->TIMER)
3492 #define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
3493 #define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
3494 #define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
3495 #define CAN_ECR_REG(base)                        ((base)->ECR)
3496 #define CAN_ESR1_REG(base)                       ((base)->ESR1)
3497 #define CAN_IMASK2_REG(base)                     ((base)->IMASK2)
3498 #define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
3499 #define CAN_IFLAG2_REG(base)                     ((base)->IFLAG2)
3500 #define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
3501 #define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
3502 #define CAN_ESR2_REG(base)                       ((base)->ESR2)
3503 #define CAN_CRCR_REG(base)                       ((base)->CRCR)
3504 #define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
3505 #define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
3506 #define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
3507 #define CAN_CS_COUNT                             64
3508 #define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
3509 #define CAN_ID_COUNT                             64
3510 #define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
3511 #define CAN_WORD0_COUNT                          64
3512 #define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
3513 #define CAN_WORD1_COUNT                          64
3514 #define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
3515 #define CAN_RXIMR_COUNT                          64
3516 #define CAN_GFWR_REG(base)                       ((base)->GFWR)
3517 
3518 /*!
3519  * @}
3520  */ /* end of group CAN_Register_Accessor_Macros */
3521 /* ----------------------------------------------------------------------------
3522    -- CAN Register Masks
3523    ---------------------------------------------------------------------------- */
3524 
3525 /*!
3526  * @addtogroup CAN_Register_Masks CAN Register Masks
3527  * @{
3528  */
3529 
3530 /* MCR Bit Fields */
3531 #define CAN_MCR_MAXMB_MASK                       0x7Fu
3532 #define CAN_MCR_MAXMB_SHIFT                      0
3533 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
3534 #define CAN_MCR_IDAM_MASK                        0x300u
3535 #define CAN_MCR_IDAM_SHIFT                       8
3536 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
3537 #define CAN_MCR_AEN_MASK                         0x1000u
3538 #define CAN_MCR_AEN_SHIFT                        12
3539 #define CAN_MCR_LPRIO_EN_MASK                    0x2000u
3540 #define CAN_MCR_LPRIO_EN_SHIFT                   13
3541 #define CAN_MCR_IRMQ_MASK                        0x10000u
3542 #define CAN_MCR_IRMQ_SHIFT                       16
3543 #define CAN_MCR_SRX_DIS_MASK                     0x20000u
3544 #define CAN_MCR_SRX_DIS_SHIFT                    17
3545 #define CAN_MCR_WAK_SRC_MASK                     0x80000u
3546 #define CAN_MCR_WAK_SRC_SHIFT                    19
3547 #define CAN_MCR_LPM_ACK_MASK                     0x100000u
3548 #define CAN_MCR_LPM_ACK_SHIFT                    20
3549 #define CAN_MCR_WRN_EN_MASK                      0x200000u
3550 #define CAN_MCR_WRN_EN_SHIFT                     21
3551 #define CAN_MCR_SLF_WAK_MASK                     0x400000u
3552 #define CAN_MCR_SLF_WAK_SHIFT                    22
3553 #define CAN_MCR_SUPV_MASK                        0x800000u
3554 #define CAN_MCR_SUPV_SHIFT                       23
3555 #define CAN_MCR_FRZ_ACK_MASK                     0x1000000u
3556 #define CAN_MCR_FRZ_ACK_SHIFT                    24
3557 #define CAN_MCR_SOFT_RST_MASK                    0x2000000u
3558 #define CAN_MCR_SOFT_RST_SHIFT                   25
3559 #define CAN_MCR_WAK_MSK_MASK                     0x4000000u
3560 #define CAN_MCR_WAK_MSK_SHIFT                    26
3561 #define CAN_MCR_NOT_RDY_MASK                     0x8000000u
3562 #define CAN_MCR_NOT_RDY_SHIFT                    27
3563 #define CAN_MCR_HALT_MASK                        0x10000000u
3564 #define CAN_MCR_HALT_SHIFT                       28
3565 #define CAN_MCR_RFEN_MASK                        0x20000000u
3566 #define CAN_MCR_RFEN_SHIFT                       29
3567 #define CAN_MCR_FRZ_MASK                         0x40000000u
3568 #define CAN_MCR_FRZ_SHIFT                        30
3569 #define CAN_MCR_MDIS_MASK                        0x80000000u
3570 #define CAN_MCR_MDIS_SHIFT                       31
3571 /* CTRL1 Bit Fields */
3572 #define CAN_CTRL1_PROP_SEG_MASK                  0x7u
3573 #define CAN_CTRL1_PROP_SEG_SHIFT                 0
3574 #define CAN_CTRL1_PROP_SEG(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROP_SEG_SHIFT))&CAN_CTRL1_PROP_SEG_MASK)
3575 #define CAN_CTRL1_LOM_MASK                       0x8u
3576 #define CAN_CTRL1_LOM_SHIFT                      3
3577 #define CAN_CTRL1_LBUF_MASK                      0x10u
3578 #define CAN_CTRL1_LBUF_SHIFT                     4
3579 #define CAN_CTRL1_TSYN_MASK                      0x20u
3580 #define CAN_CTRL1_TSYN_SHIFT                     5
3581 #define CAN_CTRL1_BOFF_REC_MASK                  0x40u
3582 #define CAN_CTRL1_BOFF_REC_SHIFT                 6
3583 #define CAN_CTRL1_SMP_MASK                       0x80u
3584 #define CAN_CTRL1_SMP_SHIFT                      7
3585 #define CAN_CTRL1_RWRN_MSK_MASK                  0x400u
3586 #define CAN_CTRL1_RWRN_MSK_SHIFT                 10
3587 #define CAN_CTRL1_TWRN_MSK_MASK                  0x800u
3588 #define CAN_CTRL1_TWRN_MSK_SHIFT                 11
3589 #define CAN_CTRL1_LPB_MASK                       0x1000u
3590 #define CAN_CTRL1_LPB_SHIFT                      12
3591 #define CAN_CTRL1_ERR_MSK_MASK                   0x4000u
3592 #define CAN_CTRL1_ERR_MSK_SHIFT                  14
3593 #define CAN_CTRL1_BOFF_MSK_MASK                  0x8000u
3594 #define CAN_CTRL1_BOFF_MSK_SHIFT                 15
3595 #define CAN_CTRL1_PSEG2_MASK                     0x70000u
3596 #define CAN_CTRL1_PSEG2_SHIFT                    16
3597 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
3598 #define CAN_CTRL1_PSEG1_MASK                     0x380000u
3599 #define CAN_CTRL1_PSEG1_SHIFT                    19
3600 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
3601 #define CAN_CTRL1_RJW_MASK                       0xC00000u
3602 #define CAN_CTRL1_RJW_SHIFT                      22
3603 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
3604 #define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
3605 #define CAN_CTRL1_PRESDIV_SHIFT                  24
3606 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
3607 /* TIMER Bit Fields */
3608 #define CAN_TIMER_TIMER_MASK                     0xFFFFu
3609 #define CAN_TIMER_TIMER_SHIFT                    0
3610 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
3611 /* RXMGMASK Bit Fields */
3612 #define CAN_RXMGMASK_MG31_MG0_MASK               0xFFFFFFFFu
3613 #define CAN_RXMGMASK_MG31_MG0_SHIFT              0
3614 #define CAN_RXMGMASK_MG31_MG0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG31_MG0_SHIFT))&CAN_RXMGMASK_MG31_MG0_MASK)
3615 /* RX14MASK Bit Fields */
3616 #define CAN_RX14MASK_RX14M31_RX14M0_MASK         0xFFFFFFFFu
3617 #define CAN_RX14MASK_RX14M31_RX14M0_SHIFT        0
3618 #define CAN_RX14MASK_RX14M31_RX14M0(x)           (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M31_RX14M0_SHIFT))&CAN_RX14MASK_RX14M31_RX14M0_MASK)
3619 /* RX15MASK Bit Fields */
3620 #define CAN_RX15MASK_RX15M31_RX15M0_MASK         0xFFFFFFFFu
3621 #define CAN_RX15MASK_RX15M31_RX15M0_SHIFT        0
3622 #define CAN_RX15MASK_RX15M31_RX15M0(x)           (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M31_RX15M0_SHIFT))&CAN_RX15MASK_RX15M31_RX15M0_MASK)
3623 /* ECR Bit Fields */
3624 #define CAN_ECR_Tx_Err_Counter_MASK              0xFFu
3625 #define CAN_ECR_Tx_Err_Counter_SHIFT             0
3626 #define CAN_ECR_Tx_Err_Counter(x)                (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Tx_Err_Counter_SHIFT))&CAN_ECR_Tx_Err_Counter_MASK)
3627 #define CAN_ECR_Rx_Err_Counter_MASK              0xFF00u
3628 #define CAN_ECR_Rx_Err_Counter_SHIFT             8
3629 #define CAN_ECR_Rx_Err_Counter(x)                (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Rx_Err_Counter_SHIFT))&CAN_ECR_Rx_Err_Counter_MASK)
3630 /* ESR1 Bit Fields */
3631 #define CAN_ESR1_WAK_INT_MASK                    0x1u
3632 #define CAN_ESR1_WAK_INT_SHIFT                   0
3633 #define CAN_ESR1_ERR_INT_MASK                    0x2u
3634 #define CAN_ESR1_ERR_INT_SHIFT                   1
3635 #define CAN_ESR1_BOFF_INT_MASK                   0x4u
3636 #define CAN_ESR1_BOFF_INT_SHIFT                  2
3637 #define CAN_ESR1_RX_MASK                         0x8u
3638 #define CAN_ESR1_RX_SHIFT                        3
3639 #define CAN_ESR1_FLT_CONF_MASK                   0x30u
3640 #define CAN_ESR1_FLT_CONF_SHIFT                  4
3641 #define CAN_ESR1_FLT_CONF(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLT_CONF_SHIFT))&CAN_ESR1_FLT_CONF_MASK)
3642 #define CAN_ESR1_TX_MASK                         0x40u
3643 #define CAN_ESR1_TX_SHIFT                        6
3644 #define CAN_ESR1_IDLE_MASK                       0x80u
3645 #define CAN_ESR1_IDLE_SHIFT                      7
3646 #define CAN_ESR1_RX_WRN_MASK                     0x100u
3647 #define CAN_ESR1_RX_WRN_SHIFT                    8
3648 #define CAN_ESR1_TX_WRN_MASK                     0x200u
3649 #define CAN_ESR1_TX_WRN_SHIFT                    9
3650 #define CAN_ESR1_STF_ERR_MASK                    0x400u
3651 #define CAN_ESR1_STF_ERR_SHIFT                   10
3652 #define CAN_ESR1_FRM_ERR_MASK                    0x800u
3653 #define CAN_ESR1_FRM_ERR_SHIFT                   11
3654 #define CAN_ESR1_CRC_ERR_MASK                    0x1000u
3655 #define CAN_ESR1_CRC_ERR_SHIFT                   12
3656 #define CAN_ESR1_ACK_ERR_MASK                    0x2000u
3657 #define CAN_ESR1_ACK_ERR_SHIFT                   13
3658 #define CAN_ESR1_BIT0_ERR_MASK                   0x4000u
3659 #define CAN_ESR1_BIT0_ERR_SHIFT                  14
3660 #define CAN_ESR1_BIT1_ERR_MASK                   0x8000u
3661 #define CAN_ESR1_BIT1_ERR_SHIFT                  15
3662 #define CAN_ESR1_RWRN_INT_MASK                   0x10000u
3663 #define CAN_ESR1_RWRN_INT_SHIFT                  16
3664 #define CAN_ESR1_TWRN_INT_MASK                   0x20000u
3665 #define CAN_ESR1_TWRN_INT_SHIFT                  17
3666 #define CAN_ESR1_SYNCH_MASK                      0x40000u
3667 #define CAN_ESR1_SYNCH_SHIFT                     18
3668 /* IMASK2 Bit Fields */
3669 #define CAN_IMASK2_BUF63M_BUF32M_MASK            0xFFFFFFFFu
3670 #define CAN_IMASK2_BUF63M_BUF32M_SHIFT           0
3671 #define CAN_IMASK2_BUF63M_BUF32M(x)              (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUF63M_BUF32M_SHIFT))&CAN_IMASK2_BUF63M_BUF32M_MASK)
3672 /* IMASK1 Bit Fields */
3673 #define CAN_IMASK1_BUF31M_BUF0M_MASK             0xFFFFFFFFu
3674 #define CAN_IMASK1_BUF31M_BUF0M_SHIFT            0
3675 #define CAN_IMASK1_BUF31M_BUF0M(x)               (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31M_BUF0M_SHIFT))&CAN_IMASK1_BUF31M_BUF0M_MASK)
3676 /* IFLAG2 Bit Fields */
3677 #define CAN_IFLAG2_BUF63I_BUF32I_MASK            0xFFFFFFFFu
3678 #define CAN_IFLAG2_BUF63I_BUF32I_SHIFT           0
3679 #define CAN_IFLAG2_BUF63I_BUF32I(x)              (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUF63I_BUF32I_SHIFT))&CAN_IFLAG2_BUF63I_BUF32I_MASK)
3680 /* IFLAG1 Bit Fields */
3681 #define CAN_IFLAG1_BUF4I_BUF0I_MASK              0x1Fu
3682 #define CAN_IFLAG1_BUF4I_BUF0I_SHIFT             0
3683 #define CAN_IFLAG1_BUF4I_BUF0I(x)                (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4I_BUF0I_SHIFT))&CAN_IFLAG1_BUF4I_BUF0I_MASK)
3684 #define CAN_IFLAG1_BUF5I_MASK                    0x20u
3685 #define CAN_IFLAG1_BUF5I_SHIFT                   5
3686 #define CAN_IFLAG1_BUF6I_MASK                    0x40u
3687 #define CAN_IFLAG1_BUF6I_SHIFT                   6
3688 #define CAN_IFLAG1_BUF7I_MASK                    0x80u
3689 #define CAN_IFLAG1_BUF7I_SHIFT                   7
3690 #define CAN_IFLAG1_BUF31I_BUF8I_MASK             0xFFFFFF00u
3691 #define CAN_IFLAG1_BUF31I_BUF8I_SHIFT            8
3692 #define CAN_IFLAG1_BUF31I_BUF8I(x)               (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31I_BUF8I_SHIFT))&CAN_IFLAG1_BUF31I_BUF8I_MASK)
3693 /* CTRL2 Bit Fields */
3694 #define CAN_CTRL2_EACEN_MASK                     0x10000u
3695 #define CAN_CTRL2_EACEN_SHIFT                    16
3696 #define CAN_CTRL2_RRS_MASK                       0x20000u
3697 #define CAN_CTRL2_RRS_SHIFT                      17
3698 #define CAN_CTRL2_MRP_MASK                       0x40000u
3699 #define CAN_CTRL2_MRP_SHIFT                      18
3700 #define CAN_CTRL2_TASD_MASK                      0xF80000u
3701 #define CAN_CTRL2_TASD_SHIFT                     19
3702 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
3703 #define CAN_CTRL2_RFFN_MASK                      0xF000000u
3704 #define CAN_CTRL2_RFFN_SHIFT                     24
3705 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
3706 #define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
3707 #define CAN_CTRL2_WRMFRZ_SHIFT                   28
3708 /* ESR2 Bit Fields */
3709 #define CAN_ESR2_IMB_MASK                        0x2000u
3710 #define CAN_ESR2_IMB_SHIFT                       13
3711 #define CAN_ESR2_VPS_MASK                        0x4000u
3712 #define CAN_ESR2_VPS_SHIFT                       14
3713 #define CAN_ESR2_LPTM_MASK                       0x7F0000u
3714 #define CAN_ESR2_LPTM_SHIFT                      16
3715 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
3716 /* CRCR Bit Fields */
3717 #define CAN_CRCR_TXCRC_MASK                      0x7FFFu
3718 #define CAN_CRCR_TXCRC_SHIFT                     0
3719 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
3720 #define CAN_CRCR_MBCRC_MASK                      0x7F0000u
3721 #define CAN_CRCR_MBCRC_SHIFT                     16
3722 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
3723 /* RXFGMASK Bit Fields */
3724 #define CAN_RXFGMASK_FGM31_FGM0_MASK             0xFFFFFFFFu
3725 #define CAN_RXFGMASK_FGM31_FGM0_SHIFT            0
3726 #define CAN_RXFGMASK_FGM31_FGM0(x)               (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM31_FGM0_SHIFT))&CAN_RXFGMASK_FGM31_FGM0_MASK)
3727 /* RXFIR Bit Fields */
3728 #define CAN_RXFIR_IDHIT_MASK                     0x1FFu
3729 #define CAN_RXFIR_IDHIT_SHIFT                    0
3730 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
3731 /* CS Bit Fields */
3732 #define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
3733 #define CAN_CS_TIME_STAMP_SHIFT                  0
3734 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
3735 #define CAN_CS_DLC_MASK                          0xF0000u
3736 #define CAN_CS_DLC_SHIFT                         16
3737 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
3738 #define CAN_CS_RTR_MASK                          0x100000u
3739 #define CAN_CS_RTR_SHIFT                         20
3740 #define CAN_CS_IDE_MASK                          0x200000u
3741 #define CAN_CS_IDE_SHIFT                         21
3742 #define CAN_CS_SRR_MASK                          0x400000u
3743 #define CAN_CS_SRR_SHIFT                         22
3744 #define CAN_CS_CODE_MASK                         0xF000000u
3745 #define CAN_CS_CODE_SHIFT                        24
3746 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
3747 /* ID Bit Fields */
3748 #define CAN_ID_EXT_MASK                          0x3FFFFu
3749 #define CAN_ID_EXT_SHIFT                         0
3750 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
3751 #define CAN_ID_STD_MASK                          0x1FFC0000u
3752 #define CAN_ID_STD_SHIFT                         18
3753 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
3754 #define CAN_ID_PRIO_MASK                         0xE0000000u
3755 #define CAN_ID_PRIO_SHIFT                        29
3756 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
3757 /* WORD0 Bit Fields */
3758 #define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
3759 #define CAN_WORD0_DATA_BYTE_3_SHIFT              0
3760 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
3761 #define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
3762 #define CAN_WORD0_DATA_BYTE_2_SHIFT              8
3763 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
3764 #define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
3765 #define CAN_WORD0_DATA_BYTE_1_SHIFT              16
3766 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
3767 #define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
3768 #define CAN_WORD0_DATA_BYTE_0_SHIFT              24
3769 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
3770 /* WORD1 Bit Fields */
3771 #define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
3772 #define CAN_WORD1_DATA_BYTE_7_SHIFT              0
3773 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
3774 #define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
3775 #define CAN_WORD1_DATA_BYTE_6_SHIFT              8
3776 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
3777 #define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
3778 #define CAN_WORD1_DATA_BYTE_5_SHIFT              16
3779 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
3780 #define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
3781 #define CAN_WORD1_DATA_BYTE_4_SHIFT              24
3782 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
3783 /* RXIMR Bit Fields */
3784 #define CAN_RXIMR0_RXIMR63_MI31_MI0_MASK         0xFFFFFFFFu
3785 #define CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT        0
3786 #define CAN_RXIMR0_RXIMR63_MI31_MI0(x)           (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT))&CAN_RXIMR0_RXIMR63_MI31_MI0_MASK)
3787 /* GFWR Bit Fields */
3788 #define CAN_GFWR_GFWR_MASK                       0xFFu
3789 #define CAN_GFWR_GFWR_SHIFT                      0
3790 #define CAN_GFWR_GFWR(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_GFWR_GFWR_SHIFT))&CAN_GFWR_GFWR_MASK)
3791 
3792 /*!
3793  * @}
3794  */ /* end of group CAN_Register_Masks */
3795 
3796 /* CAN - Peripheral instance base addresses */
3797 /** Peripheral CAN1 base address */
3798 #define CAN1_BASE                                (0x30A00000u)
3799 /** Peripheral CAN1 base pointer */
3800 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
3801 #define CAN1_BASE_PTR                            (CAN1)
3802 /** Peripheral CAN2 base address */
3803 #define CAN2_BASE                                (0x30A10000u)
3804 /** Peripheral CAN2 base pointer */
3805 #define CAN2                                     ((CAN_Type *)CAN2_BASE)
3806 #define CAN2_BASE_PTR                            (CAN2)
3807 /** Array initializer of CAN peripheral base addresses */
3808 #define CAN_BASE_ADDRS                           { CAN1_BASE, CAN2_BASE }
3809 /** Array initializer of CAN peripheral base pointers */
3810 #define CAN_BASE_PTRS                            { CAN1, CAN2 }
3811 /** Interrupt vectors for the CAN peripheral type */
3812 #define CAN_IRQS                                 { FLEXCAN1_IRQn, FLEXCAN2_IRQn }
3813 /* ----------------------------------------------------------------------------
3814    -- CAN - Register accessor macros
3815    ---------------------------------------------------------------------------- */
3816 
3817 /*!
3818  * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
3819  * @{
3820  */
3821 
3822 
3823 /* CAN - Register instance definitions */
3824 /* CAN1 */
3825 #define CAN1_MCR                                 CAN_MCR_REG(CAN1_BASE_PTR)
3826 #define CAN1_CTRL1                               CAN_CTRL1_REG(CAN1_BASE_PTR)
3827 #define CAN1_TIMER                               CAN_TIMER_REG(CAN1_BASE_PTR)
3828 #define CAN1_RXMGMASK                            CAN_RXMGMASK_REG(CAN1_BASE_PTR)
3829 #define CAN1_RX14MASK                            CAN_RX14MASK_REG(CAN1_BASE_PTR)
3830 #define CAN1_RX15MASK                            CAN_RX15MASK_REG(CAN1_BASE_PTR)
3831 #define CAN1_ECR                                 CAN_ECR_REG(CAN1_BASE_PTR)
3832 #define CAN1_ESR1                                CAN_ESR1_REG(CAN1_BASE_PTR)
3833 #define CAN1_IMASK2                              CAN_IMASK2_REG(CAN1_BASE_PTR)
3834 #define CAN1_IMASK1                              CAN_IMASK1_REG(CAN1_BASE_PTR)
3835 #define CAN1_IFLAG2                              CAN_IFLAG2_REG(CAN1_BASE_PTR)
3836 #define CAN1_IFLAG1                              CAN_IFLAG1_REG(CAN1_BASE_PTR)
3837 #define CAN1_CTRL2                               CAN_CTRL2_REG(CAN1_BASE_PTR)
3838 #define CAN1_ESR2                                CAN_ESR2_REG(CAN1_BASE_PTR)
3839 #define CAN1_CRCR                                CAN_CRCR_REG(CAN1_BASE_PTR)
3840 #define CAN1_RXFGMASK                            CAN_RXFGMASK_REG(CAN1_BASE_PTR)
3841 #define CAN1_RXFIR                               CAN_RXFIR_REG(CAN1_BASE_PTR)
3842 #define CAN1_CS0                                 CAN_CS_REG(CAN1_BASE_PTR,0)
3843 #define CAN1_ID0                                 CAN_ID_REG(CAN1_BASE_PTR,0)
3844 #define CAN1_WORD00                              CAN_WORD0_REG(CAN1_BASE_PTR,0)
3845 #define CAN1_WORD10                              CAN_WORD1_REG(CAN1_BASE_PTR,0)
3846 #define CAN1_CS1                                 CAN_CS_REG(CAN1_BASE_PTR,1)
3847 #define CAN1_ID1                                 CAN_ID_REG(CAN1_BASE_PTR,1)
3848 #define CAN1_WORD01                              CAN_WORD0_REG(CAN1_BASE_PTR,1)
3849 #define CAN1_WORD11                              CAN_WORD1_REG(CAN1_BASE_PTR,1)
3850 #define CAN1_CS2                                 CAN_CS_REG(CAN1_BASE_PTR,2)
3851 #define CAN1_ID2                                 CAN_ID_REG(CAN1_BASE_PTR,2)
3852 #define CAN1_WORD02                              CAN_WORD0_REG(CAN1_BASE_PTR,2)
3853 #define CAN1_WORD12                              CAN_WORD1_REG(CAN1_BASE_PTR,2)
3854 #define CAN1_CS3                                 CAN_CS_REG(CAN1_BASE_PTR,3)
3855 #define CAN1_ID3                                 CAN_ID_REG(CAN1_BASE_PTR,3)
3856 #define CAN1_WORD03                              CAN_WORD0_REG(CAN1_BASE_PTR,3)
3857 #define CAN1_WORD13                              CAN_WORD1_REG(CAN1_BASE_PTR,3)
3858 #define CAN1_CS4                                 CAN_CS_REG(CAN1_BASE_PTR,4)
3859 #define CAN1_ID4                                 CAN_ID_REG(CAN1_BASE_PTR,4)
3860 #define CAN1_WORD04                              CAN_WORD0_REG(CAN1_BASE_PTR,4)
3861 #define CAN1_WORD14                              CAN_WORD1_REG(CAN1_BASE_PTR,4)
3862 #define CAN1_CS5                                 CAN_CS_REG(CAN1_BASE_PTR,5)
3863 #define CAN1_ID5                                 CAN_ID_REG(CAN1_BASE_PTR,5)
3864 #define CAN1_WORD05                              CAN_WORD0_REG(CAN1_BASE_PTR,5)
3865 #define CAN1_WORD15                              CAN_WORD1_REG(CAN1_BASE_PTR,5)
3866 #define CAN1_CS6                                 CAN_CS_REG(CAN1_BASE_PTR,6)
3867 #define CAN1_ID6                                 CAN_ID_REG(CAN1_BASE_PTR,6)
3868 #define CAN1_WORD06                              CAN_WORD0_REG(CAN1_BASE_PTR,6)
3869 #define CAN1_WORD16                              CAN_WORD1_REG(CAN1_BASE_PTR,6)
3870 #define CAN1_CS7                                 CAN_CS_REG(CAN1_BASE_PTR,7)
3871 #define CAN1_ID7                                 CAN_ID_REG(CAN1_BASE_PTR,7)
3872 #define CAN1_WORD07                              CAN_WORD0_REG(CAN1_BASE_PTR,7)
3873 #define CAN1_WORD17                              CAN_WORD1_REG(CAN1_BASE_PTR,7)
3874 #define CAN1_CS8                                 CAN_CS_REG(CAN1_BASE_PTR,8)
3875 #define CAN1_ID8                                 CAN_ID_REG(CAN1_BASE_PTR,8)
3876 #define CAN1_WORD08                              CAN_WORD0_REG(CAN1_BASE_PTR,8)
3877 #define CAN1_WORD18                              CAN_WORD1_REG(CAN1_BASE_PTR,8)
3878 #define CAN1_CS9                                 CAN_CS_REG(CAN1_BASE_PTR,9)
3879 #define CAN1_ID9                                 CAN_ID_REG(CAN1_BASE_PTR,9)
3880 #define CAN1_WORD09                              CAN_WORD0_REG(CAN1_BASE_PTR,9)
3881 #define CAN1_WORD19                              CAN_WORD1_REG(CAN1_BASE_PTR,9)
3882 #define CAN1_CS10                                CAN_CS_REG(CAN1_BASE_PTR,10)
3883 #define CAN1_ID10                                CAN_ID_REG(CAN1_BASE_PTR,10)
3884 #define CAN1_WORD010                             CAN_WORD0_REG(CAN1_BASE_PTR,10)
3885 #define CAN1_WORD110                             CAN_WORD1_REG(CAN1_BASE_PTR,10)
3886 #define CAN1_CS11                                CAN_CS_REG(CAN1_BASE_PTR,11)
3887 #define CAN1_ID11                                CAN_ID_REG(CAN1_BASE_PTR,11)
3888 #define CAN1_WORD011                             CAN_WORD0_REG(CAN1_BASE_PTR,11)
3889 #define CAN1_WORD111                             CAN_WORD1_REG(CAN1_BASE_PTR,11)
3890 #define CAN1_CS12                                CAN_CS_REG(CAN1_BASE_PTR,12)
3891 #define CAN1_ID12                                CAN_ID_REG(CAN1_BASE_PTR,12)
3892 #define CAN1_WORD012                             CAN_WORD0_REG(CAN1_BASE_PTR,12)
3893 #define CAN1_WORD112                             CAN_WORD1_REG(CAN1_BASE_PTR,12)
3894 #define CAN1_CS13                                CAN_CS_REG(CAN1_BASE_PTR,13)
3895 #define CAN1_ID13                                CAN_ID_REG(CAN1_BASE_PTR,13)
3896 #define CAN1_WORD013                             CAN_WORD0_REG(CAN1_BASE_PTR,13)
3897 #define CAN1_WORD113                             CAN_WORD1_REG(CAN1_BASE_PTR,13)
3898 #define CAN1_CS14                                CAN_CS_REG(CAN1_BASE_PTR,14)
3899 #define CAN1_ID14                                CAN_ID_REG(CAN1_BASE_PTR,14)
3900 #define CAN1_WORD014                             CAN_WORD0_REG(CAN1_BASE_PTR,14)
3901 #define CAN1_WORD114                             CAN_WORD1_REG(CAN1_BASE_PTR,14)
3902 #define CAN1_CS15                                CAN_CS_REG(CAN1_BASE_PTR,15)
3903 #define CAN1_ID15                                CAN_ID_REG(CAN1_BASE_PTR,15)
3904 #define CAN1_WORD015                             CAN_WORD0_REG(CAN1_BASE_PTR,15)
3905 #define CAN1_WORD115                             CAN_WORD1_REG(CAN1_BASE_PTR,15)
3906 #define CAN1_CS16                                CAN_CS_REG(CAN1_BASE_PTR,16)
3907 #define CAN1_ID16                                CAN_ID_REG(CAN1_BASE_PTR,16)
3908 #define CAN1_WORD016                             CAN_WORD0_REG(CAN1_BASE_PTR,16)
3909 #define CAN1_WORD116                             CAN_WORD1_REG(CAN1_BASE_PTR,16)
3910 #define CAN1_CS17                                CAN_CS_REG(CAN1_BASE_PTR,17)
3911 #define CAN1_ID17                                CAN_ID_REG(CAN1_BASE_PTR,17)
3912 #define CAN1_WORD017                             CAN_WORD0_REG(CAN1_BASE_PTR,17)
3913 #define CAN1_WORD117                             CAN_WORD1_REG(CAN1_BASE_PTR,17)
3914 #define CAN1_CS18                                CAN_CS_REG(CAN1_BASE_PTR,18)
3915 #define CAN1_ID18                                CAN_ID_REG(CAN1_BASE_PTR,18)
3916 #define CAN1_WORD018                             CAN_WORD0_REG(CAN1_BASE_PTR,18)
3917 #define CAN1_WORD118                             CAN_WORD1_REG(CAN1_BASE_PTR,18)
3918 #define CAN1_CS19                                CAN_CS_REG(CAN1_BASE_PTR,19)
3919 #define CAN1_ID19                                CAN_ID_REG(CAN1_BASE_PTR,19)
3920 #define CAN1_WORD019                             CAN_WORD0_REG(CAN1_BASE_PTR,19)
3921 #define CAN1_WORD119                             CAN_WORD1_REG(CAN1_BASE_PTR,19)
3922 #define CAN1_CS20                                CAN_CS_REG(CAN1_BASE_PTR,20)
3923 #define CAN1_ID20                                CAN_ID_REG(CAN1_BASE_PTR,20)
3924 #define CAN1_WORD020                             CAN_WORD0_REG(CAN1_BASE_PTR,20)
3925 #define CAN1_WORD120                             CAN_WORD1_REG(CAN1_BASE_PTR,20)
3926 #define CAN1_CS21                                CAN_CS_REG(CAN1_BASE_PTR,21)
3927 #define CAN1_ID21                                CAN_ID_REG(CAN1_BASE_PTR,21)
3928 #define CAN1_WORD021                             CAN_WORD0_REG(CAN1_BASE_PTR,21)
3929 #define CAN1_WORD121                             CAN_WORD1_REG(CAN1_BASE_PTR,21)
3930 #define CAN1_CS22                                CAN_CS_REG(CAN1_BASE_PTR,22)
3931 #define CAN1_ID22                                CAN_ID_REG(CAN1_BASE_PTR,22)
3932 #define CAN1_WORD022                             CAN_WORD0_REG(CAN1_BASE_PTR,22)
3933 #define CAN1_WORD122                             CAN_WORD1_REG(CAN1_BASE_PTR,22)
3934 #define CAN1_CS23                                CAN_CS_REG(CAN1_BASE_PTR,23)
3935 #define CAN1_ID23                                CAN_ID_REG(CAN1_BASE_PTR,23)
3936 #define CAN1_WORD023                             CAN_WORD0_REG(CAN1_BASE_PTR,23)
3937 #define CAN1_WORD123                             CAN_WORD1_REG(CAN1_BASE_PTR,23)
3938 #define CAN1_CS24                                CAN_CS_REG(CAN1_BASE_PTR,24)
3939 #define CAN1_ID24                                CAN_ID_REG(CAN1_BASE_PTR,24)
3940 #define CAN1_WORD024                             CAN_WORD0_REG(CAN1_BASE_PTR,24)
3941 #define CAN1_WORD124                             CAN_WORD1_REG(CAN1_BASE_PTR,24)
3942 #define CAN1_CS25                                CAN_CS_REG(CAN1_BASE_PTR,25)
3943 #define CAN1_ID25                                CAN_ID_REG(CAN1_BASE_PTR,25)
3944 #define CAN1_WORD025                             CAN_WORD0_REG(CAN1_BASE_PTR,25)
3945 #define CAN1_WORD125                             CAN_WORD1_REG(CAN1_BASE_PTR,25)
3946 #define CAN1_CS26                                CAN_CS_REG(CAN1_BASE_PTR,26)
3947 #define CAN1_ID26                                CAN_ID_REG(CAN1_BASE_PTR,26)
3948 #define CAN1_WORD026                             CAN_WORD0_REG(CAN1_BASE_PTR,26)
3949 #define CAN1_WORD126                             CAN_WORD1_REG(CAN1_BASE_PTR,26)
3950 #define CAN1_CS27                                CAN_CS_REG(CAN1_BASE_PTR,27)
3951 #define CAN1_ID27                                CAN_ID_REG(CAN1_BASE_PTR,27)
3952 #define CAN1_WORD027                             CAN_WORD0_REG(CAN1_BASE_PTR,27)
3953 #define CAN1_WORD127                             CAN_WORD1_REG(CAN1_BASE_PTR,27)
3954 #define CAN1_CS28                                CAN_CS_REG(CAN1_BASE_PTR,28)
3955 #define CAN1_ID28                                CAN_ID_REG(CAN1_BASE_PTR,28)
3956 #define CAN1_WORD028                             CAN_WORD0_REG(CAN1_BASE_PTR,28)
3957 #define CAN1_WORD128                             CAN_WORD1_REG(CAN1_BASE_PTR,28)
3958 #define CAN1_CS29                                CAN_CS_REG(CAN1_BASE_PTR,29)
3959 #define CAN1_ID29                                CAN_ID_REG(CAN1_BASE_PTR,29)
3960 #define CAN1_WORD029                             CAN_WORD0_REG(CAN1_BASE_PTR,29)
3961 #define CAN1_WORD129                             CAN_WORD1_REG(CAN1_BASE_PTR,29)
3962 #define CAN1_CS30                                CAN_CS_REG(CAN1_BASE_PTR,30)
3963 #define CAN1_ID30                                CAN_ID_REG(CAN1_BASE_PTR,30)
3964 #define CAN1_WORD030                             CAN_WORD0_REG(CAN1_BASE_PTR,30)
3965 #define CAN1_WORD130                             CAN_WORD1_REG(CAN1_BASE_PTR,30)
3966 #define CAN1_CS31                                CAN_CS_REG(CAN1_BASE_PTR,31)
3967 #define CAN1_ID31                                CAN_ID_REG(CAN1_BASE_PTR,31)
3968 #define CAN1_WORD031                             CAN_WORD0_REG(CAN1_BASE_PTR,31)
3969 #define CAN1_WORD131                             CAN_WORD1_REG(CAN1_BASE_PTR,31)
3970 #define CAN1_CS32                                CAN_CS_REG(CAN1_BASE_PTR,32)
3971 #define CAN1_ID32                                CAN_ID_REG(CAN1_BASE_PTR,32)
3972 #define CAN1_WORD032                             CAN_WORD0_REG(CAN1_BASE_PTR,32)
3973 #define CAN1_WORD132                             CAN_WORD1_REG(CAN1_BASE_PTR,32)
3974 #define CAN1_CS33                                CAN_CS_REG(CAN1_BASE_PTR,33)
3975 #define CAN1_ID33                                CAN_ID_REG(CAN1_BASE_PTR,33)
3976 #define CAN1_WORD033                             CAN_WORD0_REG(CAN1_BASE_PTR,33)
3977 #define CAN1_WORD133                             CAN_WORD1_REG(CAN1_BASE_PTR,33)
3978 #define CAN1_CS34                                CAN_CS_REG(CAN1_BASE_PTR,34)
3979 #define CAN1_ID34                                CAN_ID_REG(CAN1_BASE_PTR,34)
3980 #define CAN1_WORD034                             CAN_WORD0_REG(CAN1_BASE_PTR,34)
3981 #define CAN1_WORD134                             CAN_WORD1_REG(CAN1_BASE_PTR,34)
3982 #define CAN1_CS35                                CAN_CS_REG(CAN1_BASE_PTR,35)
3983 #define CAN1_ID35                                CAN_ID_REG(CAN1_BASE_PTR,35)
3984 #define CAN1_WORD035                             CAN_WORD0_REG(CAN1_BASE_PTR,35)
3985 #define CAN1_WORD135                             CAN_WORD1_REG(CAN1_BASE_PTR,35)
3986 #define CAN1_CS36                                CAN_CS_REG(CAN1_BASE_PTR,36)
3987 #define CAN1_ID36                                CAN_ID_REG(CAN1_BASE_PTR,36)
3988 #define CAN1_WORD036                             CAN_WORD0_REG(CAN1_BASE_PTR,36)
3989 #define CAN1_WORD136                             CAN_WORD1_REG(CAN1_BASE_PTR,36)
3990 #define CAN1_CS37                                CAN_CS_REG(CAN1_BASE_PTR,37)
3991 #define CAN1_ID37                                CAN_ID_REG(CAN1_BASE_PTR,37)
3992 #define CAN1_WORD037                             CAN_WORD0_REG(CAN1_BASE_PTR,37)
3993 #define CAN1_WORD137                             CAN_WORD1_REG(CAN1_BASE_PTR,37)
3994 #define CAN1_CS38                                CAN_CS_REG(CAN1_BASE_PTR,38)
3995 #define CAN1_ID38                                CAN_ID_REG(CAN1_BASE_PTR,38)
3996 #define CAN1_WORD038                             CAN_WORD0_REG(CAN1_BASE_PTR,38)
3997 #define CAN1_WORD138                             CAN_WORD1_REG(CAN1_BASE_PTR,38)
3998 #define CAN1_CS39                                CAN_CS_REG(CAN1_BASE_PTR,39)
3999 #define CAN1_ID39                                CAN_ID_REG(CAN1_BASE_PTR,39)
4000 #define CAN1_WORD039                             CAN_WORD0_REG(CAN1_BASE_PTR,39)
4001 #define CAN1_WORD139                             CAN_WORD1_REG(CAN1_BASE_PTR,39)
4002 #define CAN1_CS40                                CAN_CS_REG(CAN1_BASE_PTR,40)
4003 #define CAN1_ID40                                CAN_ID_REG(CAN1_BASE_PTR,40)
4004 #define CAN1_WORD040                             CAN_WORD0_REG(CAN1_BASE_PTR,40)
4005 #define CAN1_WORD140                             CAN_WORD1_REG(CAN1_BASE_PTR,40)
4006 #define CAN1_CS41                                CAN_CS_REG(CAN1_BASE_PTR,41)
4007 #define CAN1_ID41                                CAN_ID_REG(CAN1_BASE_PTR,41)
4008 #define CAN1_WORD041                             CAN_WORD0_REG(CAN1_BASE_PTR,41)
4009 #define CAN1_WORD141                             CAN_WORD1_REG(CAN1_BASE_PTR,41)
4010 #define CAN1_CS42                                CAN_CS_REG(CAN1_BASE_PTR,42)
4011 #define CAN1_ID42                                CAN_ID_REG(CAN1_BASE_PTR,42)
4012 #define CAN1_WORD042                             CAN_WORD0_REG(CAN1_BASE_PTR,42)
4013 #define CAN1_WORD142                             CAN_WORD1_REG(CAN1_BASE_PTR,42)
4014 #define CAN1_CS43                                CAN_CS_REG(CAN1_BASE_PTR,43)
4015 #define CAN1_ID43                                CAN_ID_REG(CAN1_BASE_PTR,43)
4016 #define CAN1_WORD043                             CAN_WORD0_REG(CAN1_BASE_PTR,43)
4017 #define CAN1_WORD143                             CAN_WORD1_REG(CAN1_BASE_PTR,43)
4018 #define CAN1_CS44                                CAN_CS_REG(CAN1_BASE_PTR,44)
4019 #define CAN1_ID44                                CAN_ID_REG(CAN1_BASE_PTR,44)
4020 #define CAN1_WORD044                             CAN_WORD0_REG(CAN1_BASE_PTR,44)
4021 #define CAN1_WORD144                             CAN_WORD1_REG(CAN1_BASE_PTR,44)
4022 #define CAN1_CS45                                CAN_CS_REG(CAN1_BASE_PTR,45)
4023 #define CAN1_ID45                                CAN_ID_REG(CAN1_BASE_PTR,45)
4024 #define CAN1_WORD045                             CAN_WORD0_REG(CAN1_BASE_PTR,45)
4025 #define CAN1_WORD145                             CAN_WORD1_REG(CAN1_BASE_PTR,45)
4026 #define CAN1_CS46                                CAN_CS_REG(CAN1_BASE_PTR,46)
4027 #define CAN1_ID46                                CAN_ID_REG(CAN1_BASE_PTR,46)
4028 #define CAN1_WORD046                             CAN_WORD0_REG(CAN1_BASE_PTR,46)
4029 #define CAN1_WORD146                             CAN_WORD1_REG(CAN1_BASE_PTR,46)
4030 #define CAN1_CS47                                CAN_CS_REG(CAN1_BASE_PTR,47)
4031 #define CAN1_ID47                                CAN_ID_REG(CAN1_BASE_PTR,47)
4032 #define CAN1_WORD047                             CAN_WORD0_REG(CAN1_BASE_PTR,47)
4033 #define CAN1_WORD147                             CAN_WORD1_REG(CAN1_BASE_PTR,47)
4034 #define CAN1_CS48                                CAN_CS_REG(CAN1_BASE_PTR,48)
4035 #define CAN1_ID48                                CAN_ID_REG(CAN1_BASE_PTR,48)
4036 #define CAN1_WORD048                             CAN_WORD0_REG(CAN1_BASE_PTR,48)
4037 #define CAN1_WORD148                             CAN_WORD1_REG(CAN1_BASE_PTR,48)
4038 #define CAN1_CS49                                CAN_CS_REG(CAN1_BASE_PTR,49)
4039 #define CAN1_ID49                                CAN_ID_REG(CAN1_BASE_PTR,49)
4040 #define CAN1_WORD049                             CAN_WORD0_REG(CAN1_BASE_PTR,49)
4041 #define CAN1_WORD149                             CAN_WORD1_REG(CAN1_BASE_PTR,49)
4042 #define CAN1_CS50                                CAN_CS_REG(CAN1_BASE_PTR,50)
4043 #define CAN1_ID50                                CAN_ID_REG(CAN1_BASE_PTR,50)
4044 #define CAN1_WORD050                             CAN_WORD0_REG(CAN1_BASE_PTR,50)
4045 #define CAN1_WORD150                             CAN_WORD1_REG(CAN1_BASE_PTR,50)
4046 #define CAN1_CS51                                CAN_CS_REG(CAN1_BASE_PTR,51)
4047 #define CAN1_ID51                                CAN_ID_REG(CAN1_BASE_PTR,51)
4048 #define CAN1_WORD051                             CAN_WORD0_REG(CAN1_BASE_PTR,51)
4049 #define CAN1_WORD151                             CAN_WORD1_REG(CAN1_BASE_PTR,51)
4050 #define CAN1_CS52                                CAN_CS_REG(CAN1_BASE_PTR,52)
4051 #define CAN1_ID52                                CAN_ID_REG(CAN1_BASE_PTR,52)
4052 #define CAN1_WORD052                             CAN_WORD0_REG(CAN1_BASE_PTR,52)
4053 #define CAN1_WORD152                             CAN_WORD1_REG(CAN1_BASE_PTR,52)
4054 #define CAN1_CS53                                CAN_CS_REG(CAN1_BASE_PTR,53)
4055 #define CAN1_ID53                                CAN_ID_REG(CAN1_BASE_PTR,53)
4056 #define CAN1_WORD053                             CAN_WORD0_REG(CAN1_BASE_PTR,53)
4057 #define CAN1_WORD153                             CAN_WORD1_REG(CAN1_BASE_PTR,53)
4058 #define CAN1_CS54                                CAN_CS_REG(CAN1_BASE_PTR,54)
4059 #define CAN1_ID54                                CAN_ID_REG(CAN1_BASE_PTR,54)
4060 #define CAN1_WORD054                             CAN_WORD0_REG(CAN1_BASE_PTR,54)
4061 #define CAN1_WORD154                             CAN_WORD1_REG(CAN1_BASE_PTR,54)
4062 #define CAN1_CS55                                CAN_CS_REG(CAN1_BASE_PTR,55)
4063 #define CAN1_ID55                                CAN_ID_REG(CAN1_BASE_PTR,55)
4064 #define CAN1_WORD055                             CAN_WORD0_REG(CAN1_BASE_PTR,55)
4065 #define CAN1_WORD155                             CAN_WORD1_REG(CAN1_BASE_PTR,55)
4066 #define CAN1_CS56                                CAN_CS_REG(CAN1_BASE_PTR,56)
4067 #define CAN1_ID56                                CAN_ID_REG(CAN1_BASE_PTR,56)
4068 #define CAN1_WORD056                             CAN_WORD0_REG(CAN1_BASE_PTR,56)
4069 #define CAN1_WORD156                             CAN_WORD1_REG(CAN1_BASE_PTR,56)
4070 #define CAN1_CS57                                CAN_CS_REG(CAN1_BASE_PTR,57)
4071 #define CAN1_ID57                                CAN_ID_REG(CAN1_BASE_PTR,57)
4072 #define CAN1_WORD057                             CAN_WORD0_REG(CAN1_BASE_PTR,57)
4073 #define CAN1_WORD157                             CAN_WORD1_REG(CAN1_BASE_PTR,57)
4074 #define CAN1_CS58                                CAN_CS_REG(CAN1_BASE_PTR,58)
4075 #define CAN1_ID58                                CAN_ID_REG(CAN1_BASE_PTR,58)
4076 #define CAN1_WORD058                             CAN_WORD0_REG(CAN1_BASE_PTR,58)
4077 #define CAN1_WORD158                             CAN_WORD1_REG(CAN1_BASE_PTR,58)
4078 #define CAN1_CS59                                CAN_CS_REG(CAN1_BASE_PTR,59)
4079 #define CAN1_ID59                                CAN_ID_REG(CAN1_BASE_PTR,59)
4080 #define CAN1_WORD059                             CAN_WORD0_REG(CAN1_BASE_PTR,59)
4081 #define CAN1_WORD159                             CAN_WORD1_REG(CAN1_BASE_PTR,59)
4082 #define CAN1_CS60                                CAN_CS_REG(CAN1_BASE_PTR,60)
4083 #define CAN1_ID60                                CAN_ID_REG(CAN1_BASE_PTR,60)
4084 #define CAN1_WORD060                             CAN_WORD0_REG(CAN1_BASE_PTR,60)
4085 #define CAN1_WORD160                             CAN_WORD1_REG(CAN1_BASE_PTR,60)
4086 #define CAN1_CS61                                CAN_CS_REG(CAN1_BASE_PTR,61)
4087 #define CAN1_ID61                                CAN_ID_REG(CAN1_BASE_PTR,61)
4088 #define CAN1_WORD061                             CAN_WORD0_REG(CAN1_BASE_PTR,61)
4089 #define CAN1_WORD161                             CAN_WORD1_REG(CAN1_BASE_PTR,61)
4090 #define CAN1_CS62                                CAN_CS_REG(CAN1_BASE_PTR,62)
4091 #define CAN1_ID62                                CAN_ID_REG(CAN1_BASE_PTR,62)
4092 #define CAN1_WORD062                             CAN_WORD0_REG(CAN1_BASE_PTR,62)
4093 #define CAN1_WORD162                             CAN_WORD1_REG(CAN1_BASE_PTR,62)
4094 #define CAN1_CS63                                CAN_CS_REG(CAN1_BASE_PTR,63)
4095 #define CAN1_ID63                                CAN_ID_REG(CAN1_BASE_PTR,63)
4096 #define CAN1_WORD063                             CAN_WORD0_REG(CAN1_BASE_PTR,63)
4097 #define CAN1_WORD163                             CAN_WORD1_REG(CAN1_BASE_PTR,63)
4098 #define CAN1_RXIMR0                              CAN_RXIMR_REG(CAN1_BASE_PTR,0)
4099 #define CAN1_RXIMR1                              CAN_RXIMR_REG(CAN1_BASE_PTR,1)
4100 #define CAN1_RXIMR2                              CAN_RXIMR_REG(CAN1_BASE_PTR,2)
4101 #define CAN1_RXIMR3                              CAN_RXIMR_REG(CAN1_BASE_PTR,3)
4102 #define CAN1_RXIMR4                              CAN_RXIMR_REG(CAN1_BASE_PTR,4)
4103 #define CAN1_RXIMR5                              CAN_RXIMR_REG(CAN1_BASE_PTR,5)
4104 #define CAN1_RXIMR6                              CAN_RXIMR_REG(CAN1_BASE_PTR,6)
4105 #define CAN1_RXIMR7                              CAN_RXIMR_REG(CAN1_BASE_PTR,7)
4106 #define CAN1_RXIMR8                              CAN_RXIMR_REG(CAN1_BASE_PTR,8)
4107 #define CAN1_RXIMR9                              CAN_RXIMR_REG(CAN1_BASE_PTR,9)
4108 #define CAN1_RXIMR10                             CAN_RXIMR_REG(CAN1_BASE_PTR,10)
4109 #define CAN1_RXIMR11                             CAN_RXIMR_REG(CAN1_BASE_PTR,11)
4110 #define CAN1_RXIMR12                             CAN_RXIMR_REG(CAN1_BASE_PTR,12)
4111 #define CAN1_RXIMR13                             CAN_RXIMR_REG(CAN1_BASE_PTR,13)
4112 #define CAN1_RXIMR14                             CAN_RXIMR_REG(CAN1_BASE_PTR,14)
4113 #define CAN1_RXIMR15                             CAN_RXIMR_REG(CAN1_BASE_PTR,15)
4114 #define CAN1_RXIMR16                             CAN_RXIMR_REG(CAN1_BASE_PTR,16)
4115 #define CAN1_RXIMR17                             CAN_RXIMR_REG(CAN1_BASE_PTR,17)
4116 #define CAN1_RXIMR18                             CAN_RXIMR_REG(CAN1_BASE_PTR,18)
4117 #define CAN1_RXIMR19                             CAN_RXIMR_REG(CAN1_BASE_PTR,19)
4118 #define CAN1_RXIMR20                             CAN_RXIMR_REG(CAN1_BASE_PTR,20)
4119 #define CAN1_RXIMR21                             CAN_RXIMR_REG(CAN1_BASE_PTR,21)
4120 #define CAN1_RXIMR22                             CAN_RXIMR_REG(CAN1_BASE_PTR,22)
4121 #define CAN1_RXIMR23                             CAN_RXIMR_REG(CAN1_BASE_PTR,23)
4122 #define CAN1_RXIMR24                             CAN_RXIMR_REG(CAN1_BASE_PTR,24)
4123 #define CAN1_RXIMR25                             CAN_RXIMR_REG(CAN1_BASE_PTR,25)
4124 #define CAN1_RXIMR26                             CAN_RXIMR_REG(CAN1_BASE_PTR,26)
4125 #define CAN1_RXIMR27                             CAN_RXIMR_REG(CAN1_BASE_PTR,27)
4126 #define CAN1_RXIMR28                             CAN_RXIMR_REG(CAN1_BASE_PTR,28)
4127 #define CAN1_RXIMR29                             CAN_RXIMR_REG(CAN1_BASE_PTR,29)
4128 #define CAN1_RXIMR30                             CAN_RXIMR_REG(CAN1_BASE_PTR,30)
4129 #define CAN1_RXIMR31                             CAN_RXIMR_REG(CAN1_BASE_PTR,31)
4130 #define CAN1_RXIMR32                             CAN_RXIMR_REG(CAN1_BASE_PTR,32)
4131 #define CAN1_RXIMR33                             CAN_RXIMR_REG(CAN1_BASE_PTR,33)
4132 #define CAN1_RXIMR34                             CAN_RXIMR_REG(CAN1_BASE_PTR,34)
4133 #define CAN1_RXIMR35                             CAN_RXIMR_REG(CAN1_BASE_PTR,35)
4134 #define CAN1_RXIMR36                             CAN_RXIMR_REG(CAN1_BASE_PTR,36)
4135 #define CAN1_RXIMR37                             CAN_RXIMR_REG(CAN1_BASE_PTR,37)
4136 #define CAN1_RXIMR38                             CAN_RXIMR_REG(CAN1_BASE_PTR,38)
4137 #define CAN1_RXIMR39                             CAN_RXIMR_REG(CAN1_BASE_PTR,39)
4138 #define CAN1_RXIMR40                             CAN_RXIMR_REG(CAN1_BASE_PTR,40)
4139 #define CAN1_RXIMR41                             CAN_RXIMR_REG(CAN1_BASE_PTR,41)
4140 #define CAN1_RXIMR42                             CAN_RXIMR_REG(CAN1_BASE_PTR,42)
4141 #define CAN1_RXIMR43                             CAN_RXIMR_REG(CAN1_BASE_PTR,43)
4142 #define CAN1_RXIMR44                             CAN_RXIMR_REG(CAN1_BASE_PTR,44)
4143 #define CAN1_RXIMR45                             CAN_RXIMR_REG(CAN1_BASE_PTR,45)
4144 #define CAN1_RXIMR46                             CAN_RXIMR_REG(CAN1_BASE_PTR,46)
4145 #define CAN1_RXIMR47                             CAN_RXIMR_REG(CAN1_BASE_PTR,47)
4146 #define CAN1_RXIMR48                             CAN_RXIMR_REG(CAN1_BASE_PTR,48)
4147 #define CAN1_RXIMR49                             CAN_RXIMR_REG(CAN1_BASE_PTR,49)
4148 #define CAN1_RXIMR50                             CAN_RXIMR_REG(CAN1_BASE_PTR,50)
4149 #define CAN1_RXIMR51                             CAN_RXIMR_REG(CAN1_BASE_PTR,51)
4150 #define CAN1_RXIMR52                             CAN_RXIMR_REG(CAN1_BASE_PTR,52)
4151 #define CAN1_RXIMR53                             CAN_RXIMR_REG(CAN1_BASE_PTR,53)
4152 #define CAN1_RXIMR54                             CAN_RXIMR_REG(CAN1_BASE_PTR,54)
4153 #define CAN1_RXIMR55                             CAN_RXIMR_REG(CAN1_BASE_PTR,55)
4154 #define CAN1_RXIMR56                             CAN_RXIMR_REG(CAN1_BASE_PTR,56)
4155 #define CAN1_RXIMR57                             CAN_RXIMR_REG(CAN1_BASE_PTR,57)
4156 #define CAN1_RXIMR58                             CAN_RXIMR_REG(CAN1_BASE_PTR,58)
4157 #define CAN1_RXIMR59                             CAN_RXIMR_REG(CAN1_BASE_PTR,59)
4158 #define CAN1_RXIMR60                             CAN_RXIMR_REG(CAN1_BASE_PTR,60)
4159 #define CAN1_RXIMR61                             CAN_RXIMR_REG(CAN1_BASE_PTR,61)
4160 #define CAN1_RXIMR62                             CAN_RXIMR_REG(CAN1_BASE_PTR,62)
4161 #define CAN1_RXIMR63                             CAN_RXIMR_REG(CAN1_BASE_PTR,63)
4162 #define CAN1_GFWR                                CAN_GFWR_REG(CAN1_BASE_PTR)
4163 /* CAN2 */
4164 #define CAN2_MCR                                 CAN_MCR_REG(CAN2_BASE_PTR)
4165 #define CAN2_CTRL1                               CAN_CTRL1_REG(CAN2_BASE_PTR)
4166 #define CAN2_TIMER                               CAN_TIMER_REG(CAN2_BASE_PTR)
4167 #define CAN2_RXMGMASK                            CAN_RXMGMASK_REG(CAN2_BASE_PTR)
4168 #define CAN2_RX14MASK                            CAN_RX14MASK_REG(CAN2_BASE_PTR)
4169 #define CAN2_RX15MASK                            CAN_RX15MASK_REG(CAN2_BASE_PTR)
4170 #define CAN2_ECR                                 CAN_ECR_REG(CAN2_BASE_PTR)
4171 #define CAN2_ESR1                                CAN_ESR1_REG(CAN2_BASE_PTR)
4172 #define CAN2_IMASK2                              CAN_IMASK2_REG(CAN2_BASE_PTR)
4173 #define CAN2_IMASK1                              CAN_IMASK1_REG(CAN2_BASE_PTR)
4174 #define CAN2_IFLAG2                              CAN_IFLAG2_REG(CAN2_BASE_PTR)
4175 #define CAN2_IFLAG1                              CAN_IFLAG1_REG(CAN2_BASE_PTR)
4176 #define CAN2_CTRL2                               CAN_CTRL2_REG(CAN2_BASE_PTR)
4177 #define CAN2_ESR2                                CAN_ESR2_REG(CAN2_BASE_PTR)
4178 #define CAN2_CRCR                                CAN_CRCR_REG(CAN2_BASE_PTR)
4179 #define CAN2_RXFGMASK                            CAN_RXFGMASK_REG(CAN2_BASE_PTR)
4180 #define CAN2_RXFIR                               CAN_RXFIR_REG(CAN2_BASE_PTR)
4181 #define CAN2_CS0                                 CAN_CS_REG(CAN2_BASE_PTR,0)
4182 #define CAN2_ID0                                 CAN_ID_REG(CAN2_BASE_PTR,0)
4183 #define CAN2_WORD00                              CAN_WORD0_REG(CAN2_BASE_PTR,0)
4184 #define CAN2_WORD10                              CAN_WORD1_REG(CAN2_BASE_PTR,0)
4185 #define CAN2_CS1                                 CAN_CS_REG(CAN2_BASE_PTR,1)
4186 #define CAN2_ID1                                 CAN_ID_REG(CAN2_BASE_PTR,1)
4187 #define CAN2_WORD01                              CAN_WORD0_REG(CAN2_BASE_PTR,1)
4188 #define CAN2_WORD11                              CAN_WORD1_REG(CAN2_BASE_PTR,1)
4189 #define CAN2_CS2                                 CAN_CS_REG(CAN2_BASE_PTR,2)
4190 #define CAN2_ID2                                 CAN_ID_REG(CAN2_BASE_PTR,2)
4191 #define CAN2_WORD02                              CAN_WORD0_REG(CAN2_BASE_PTR,2)
4192 #define CAN2_WORD12                              CAN_WORD1_REG(CAN2_BASE_PTR,2)
4193 #define CAN2_CS3                                 CAN_CS_REG(CAN2_BASE_PTR,3)
4194 #define CAN2_ID3                                 CAN_ID_REG(CAN2_BASE_PTR,3)
4195 #define CAN2_WORD03                              CAN_WORD0_REG(CAN2_BASE_PTR,3)
4196 #define CAN2_WORD13                              CAN_WORD1_REG(CAN2_BASE_PTR,3)
4197 #define CAN2_CS4                                 CAN_CS_REG(CAN2_BASE_PTR,4)
4198 #define CAN2_ID4                                 CAN_ID_REG(CAN2_BASE_PTR,4)
4199 #define CAN2_WORD04                              CAN_WORD0_REG(CAN2_BASE_PTR,4)
4200 #define CAN2_WORD14                              CAN_WORD1_REG(CAN2_BASE_PTR,4)
4201 #define CAN2_CS5                                 CAN_CS_REG(CAN2_BASE_PTR,5)
4202 #define CAN2_ID5                                 CAN_ID_REG(CAN2_BASE_PTR,5)
4203 #define CAN2_WORD05                              CAN_WORD0_REG(CAN2_BASE_PTR,5)
4204 #define CAN2_WORD15                              CAN_WORD1_REG(CAN2_BASE_PTR,5)
4205 #define CAN2_CS6                                 CAN_CS_REG(CAN2_BASE_PTR,6)
4206 #define CAN2_ID6                                 CAN_ID_REG(CAN2_BASE_PTR,6)
4207 #define CAN2_WORD06                              CAN_WORD0_REG(CAN2_BASE_PTR,6)
4208 #define CAN2_WORD16                              CAN_WORD1_REG(CAN2_BASE_PTR,6)
4209 #define CAN2_CS7                                 CAN_CS_REG(CAN2_BASE_PTR,7)
4210 #define CAN2_ID7                                 CAN_ID_REG(CAN2_BASE_PTR,7)
4211 #define CAN2_WORD07                              CAN_WORD0_REG(CAN2_BASE_PTR,7)
4212 #define CAN2_WORD17                              CAN_WORD1_REG(CAN2_BASE_PTR,7)
4213 #define CAN2_CS8                                 CAN_CS_REG(CAN2_BASE_PTR,8)
4214 #define CAN2_ID8                                 CAN_ID_REG(CAN2_BASE_PTR,8)
4215 #define CAN2_WORD08                              CAN_WORD0_REG(CAN2_BASE_PTR,8)
4216 #define CAN2_WORD18                              CAN_WORD1_REG(CAN2_BASE_PTR,8)
4217 #define CAN2_CS9                                 CAN_CS_REG(CAN2_BASE_PTR,9)
4218 #define CAN2_ID9                                 CAN_ID_REG(CAN2_BASE_PTR,9)
4219 #define CAN2_WORD09                              CAN_WORD0_REG(CAN2_BASE_PTR,9)
4220 #define CAN2_WORD19                              CAN_WORD1_REG(CAN2_BASE_PTR,9)
4221 #define CAN2_CS10                                CAN_CS_REG(CAN2_BASE_PTR,10)
4222 #define CAN2_ID10                                CAN_ID_REG(CAN2_BASE_PTR,10)
4223 #define CAN2_WORD010                             CAN_WORD0_REG(CAN2_BASE_PTR,10)
4224 #define CAN2_WORD110                             CAN_WORD1_REG(CAN2_BASE_PTR,10)
4225 #define CAN2_CS11                                CAN_CS_REG(CAN2_BASE_PTR,11)
4226 #define CAN2_ID11                                CAN_ID_REG(CAN2_BASE_PTR,11)
4227 #define CAN2_WORD011                             CAN_WORD0_REG(CAN2_BASE_PTR,11)
4228 #define CAN2_WORD111                             CAN_WORD1_REG(CAN2_BASE_PTR,11)
4229 #define CAN2_CS12                                CAN_CS_REG(CAN2_BASE_PTR,12)
4230 #define CAN2_ID12                                CAN_ID_REG(CAN2_BASE_PTR,12)
4231 #define CAN2_WORD012                             CAN_WORD0_REG(CAN2_BASE_PTR,12)
4232 #define CAN2_WORD112                             CAN_WORD1_REG(CAN2_BASE_PTR,12)
4233 #define CAN2_CS13                                CAN_CS_REG(CAN2_BASE_PTR,13)
4234 #define CAN2_ID13                                CAN_ID_REG(CAN2_BASE_PTR,13)
4235 #define CAN2_WORD013                             CAN_WORD0_REG(CAN2_BASE_PTR,13)
4236 #define CAN2_WORD113                             CAN_WORD1_REG(CAN2_BASE_PTR,13)
4237 #define CAN2_CS14                                CAN_CS_REG(CAN2_BASE_PTR,14)
4238 #define CAN2_ID14                                CAN_ID_REG(CAN2_BASE_PTR,14)
4239 #define CAN2_WORD014                             CAN_WORD0_REG(CAN2_BASE_PTR,14)
4240 #define CAN2_WORD114                             CAN_WORD1_REG(CAN2_BASE_PTR,14)
4241 #define CAN2_CS15                                CAN_CS_REG(CAN2_BASE_PTR,15)
4242 #define CAN2_ID15                                CAN_ID_REG(CAN2_BASE_PTR,15)
4243 #define CAN2_WORD015                             CAN_WORD0_REG(CAN2_BASE_PTR,15)
4244 #define CAN2_WORD115                             CAN_WORD1_REG(CAN2_BASE_PTR,15)
4245 #define CAN2_CS16                                CAN_CS_REG(CAN2_BASE_PTR,16)
4246 #define CAN2_ID16                                CAN_ID_REG(CAN2_BASE_PTR,16)
4247 #define CAN2_WORD016                             CAN_WORD0_REG(CAN2_BASE_PTR,16)
4248 #define CAN2_WORD116                             CAN_WORD1_REG(CAN2_BASE_PTR,16)
4249 #define CAN2_CS17                                CAN_CS_REG(CAN2_BASE_PTR,17)
4250 #define CAN2_ID17                                CAN_ID_REG(CAN2_BASE_PTR,17)
4251 #define CAN2_WORD017                             CAN_WORD0_REG(CAN2_BASE_PTR,17)
4252 #define CAN2_WORD117                             CAN_WORD1_REG(CAN2_BASE_PTR,17)
4253 #define CAN2_CS18                                CAN_CS_REG(CAN2_BASE_PTR,18)
4254 #define CAN2_ID18                                CAN_ID_REG(CAN2_BASE_PTR,18)
4255 #define CAN2_WORD018                             CAN_WORD0_REG(CAN2_BASE_PTR,18)
4256 #define CAN2_WORD118                             CAN_WORD1_REG(CAN2_BASE_PTR,18)
4257 #define CAN2_CS19                                CAN_CS_REG(CAN2_BASE_PTR,19)
4258 #define CAN2_ID19                                CAN_ID_REG(CAN2_BASE_PTR,19)
4259 #define CAN2_WORD019                             CAN_WORD0_REG(CAN2_BASE_PTR,19)
4260 #define CAN2_WORD119                             CAN_WORD1_REG(CAN2_BASE_PTR,19)
4261 #define CAN2_CS20                                CAN_CS_REG(CAN2_BASE_PTR,20)
4262 #define CAN2_ID20                                CAN_ID_REG(CAN2_BASE_PTR,20)
4263 #define CAN2_WORD020                             CAN_WORD0_REG(CAN2_BASE_PTR,20)
4264 #define CAN2_WORD120                             CAN_WORD1_REG(CAN2_BASE_PTR,20)
4265 #define CAN2_CS21                                CAN_CS_REG(CAN2_BASE_PTR,21)
4266 #define CAN2_ID21                                CAN_ID_REG(CAN2_BASE_PTR,21)
4267 #define CAN2_WORD021                             CAN_WORD0_REG(CAN2_BASE_PTR,21)
4268 #define CAN2_WORD121                             CAN_WORD1_REG(CAN2_BASE_PTR,21)
4269 #define CAN2_CS22                                CAN_CS_REG(CAN2_BASE_PTR,22)
4270 #define CAN2_ID22                                CAN_ID_REG(CAN2_BASE_PTR,22)
4271 #define CAN2_WORD022                             CAN_WORD0_REG(CAN2_BASE_PTR,22)
4272 #define CAN2_WORD122                             CAN_WORD1_REG(CAN2_BASE_PTR,22)
4273 #define CAN2_CS23                                CAN_CS_REG(CAN2_BASE_PTR,23)
4274 #define CAN2_ID23                                CAN_ID_REG(CAN2_BASE_PTR,23)
4275 #define CAN2_WORD023                             CAN_WORD0_REG(CAN2_BASE_PTR,23)
4276 #define CAN2_WORD123                             CAN_WORD1_REG(CAN2_BASE_PTR,23)
4277 #define CAN2_CS24                                CAN_CS_REG(CAN2_BASE_PTR,24)
4278 #define CAN2_ID24                                CAN_ID_REG(CAN2_BASE_PTR,24)
4279 #define CAN2_WORD024                             CAN_WORD0_REG(CAN2_BASE_PTR,24)
4280 #define CAN2_WORD124                             CAN_WORD1_REG(CAN2_BASE_PTR,24)
4281 #define CAN2_CS25                                CAN_CS_REG(CAN2_BASE_PTR,25)
4282 #define CAN2_ID25                                CAN_ID_REG(CAN2_BASE_PTR,25)
4283 #define CAN2_WORD025                             CAN_WORD0_REG(CAN2_BASE_PTR,25)
4284 #define CAN2_WORD125                             CAN_WORD1_REG(CAN2_BASE_PTR,25)
4285 #define CAN2_CS26                                CAN_CS_REG(CAN2_BASE_PTR,26)
4286 #define CAN2_ID26                                CAN_ID_REG(CAN2_BASE_PTR,26)
4287 #define CAN2_WORD026                             CAN_WORD0_REG(CAN2_BASE_PTR,26)
4288 #define CAN2_WORD126                             CAN_WORD1_REG(CAN2_BASE_PTR,26)
4289 #define CAN2_CS27                                CAN_CS_REG(CAN2_BASE_PTR,27)
4290 #define CAN2_ID27                                CAN_ID_REG(CAN2_BASE_PTR,27)
4291 #define CAN2_WORD027                             CAN_WORD0_REG(CAN2_BASE_PTR,27)
4292 #define CAN2_WORD127                             CAN_WORD1_REG(CAN2_BASE_PTR,27)
4293 #define CAN2_CS28                                CAN_CS_REG(CAN2_BASE_PTR,28)
4294 #define CAN2_ID28                                CAN_ID_REG(CAN2_BASE_PTR,28)
4295 #define CAN2_WORD028                             CAN_WORD0_REG(CAN2_BASE_PTR,28)
4296 #define CAN2_WORD128                             CAN_WORD1_REG(CAN2_BASE_PTR,28)
4297 #define CAN2_CS29                                CAN_CS_REG(CAN2_BASE_PTR,29)
4298 #define CAN2_ID29                                CAN_ID_REG(CAN2_BASE_PTR,29)
4299 #define CAN2_WORD029                             CAN_WORD0_REG(CAN2_BASE_PTR,29)
4300 #define CAN2_WORD129                             CAN_WORD1_REG(CAN2_BASE_PTR,29)
4301 #define CAN2_CS30                                CAN_CS_REG(CAN2_BASE_PTR,30)
4302 #define CAN2_ID30                                CAN_ID_REG(CAN2_BASE_PTR,30)
4303 #define CAN2_WORD030                             CAN_WORD0_REG(CAN2_BASE_PTR,30)
4304 #define CAN2_WORD130                             CAN_WORD1_REG(CAN2_BASE_PTR,30)
4305 #define CAN2_CS31                                CAN_CS_REG(CAN2_BASE_PTR,31)
4306 #define CAN2_ID31                                CAN_ID_REG(CAN2_BASE_PTR,31)
4307 #define CAN2_WORD031                             CAN_WORD0_REG(CAN2_BASE_PTR,31)
4308 #define CAN2_WORD131                             CAN_WORD1_REG(CAN2_BASE_PTR,31)
4309 #define CAN2_CS32                                CAN_CS_REG(CAN2_BASE_PTR,32)
4310 #define CAN2_ID32                                CAN_ID_REG(CAN2_BASE_PTR,32)
4311 #define CAN2_WORD032                             CAN_WORD0_REG(CAN2_BASE_PTR,32)
4312 #define CAN2_WORD132                             CAN_WORD1_REG(CAN2_BASE_PTR,32)
4313 #define CAN2_CS33                                CAN_CS_REG(CAN2_BASE_PTR,33)
4314 #define CAN2_ID33                                CAN_ID_REG(CAN2_BASE_PTR,33)
4315 #define CAN2_WORD033                             CAN_WORD0_REG(CAN2_BASE_PTR,33)
4316 #define CAN2_WORD133                             CAN_WORD1_REG(CAN2_BASE_PTR,33)
4317 #define CAN2_CS34                                CAN_CS_REG(CAN2_BASE_PTR,34)
4318 #define CAN2_ID34                                CAN_ID_REG(CAN2_BASE_PTR,34)
4319 #define CAN2_WORD034                             CAN_WORD0_REG(CAN2_BASE_PTR,34)
4320 #define CAN2_WORD134                             CAN_WORD1_REG(CAN2_BASE_PTR,34)
4321 #define CAN2_CS35                                CAN_CS_REG(CAN2_BASE_PTR,35)
4322 #define CAN2_ID35                                CAN_ID_REG(CAN2_BASE_PTR,35)
4323 #define CAN2_WORD035                             CAN_WORD0_REG(CAN2_BASE_PTR,35)
4324 #define CAN2_WORD135                             CAN_WORD1_REG(CAN2_BASE_PTR,35)
4325 #define CAN2_CS36                                CAN_CS_REG(CAN2_BASE_PTR,36)
4326 #define CAN2_ID36                                CAN_ID_REG(CAN2_BASE_PTR,36)
4327 #define CAN2_WORD036                             CAN_WORD0_REG(CAN2_BASE_PTR,36)
4328 #define CAN2_WORD136                             CAN_WORD1_REG(CAN2_BASE_PTR,36)
4329 #define CAN2_CS37                                CAN_CS_REG(CAN2_BASE_PTR,37)
4330 #define CAN2_ID37                                CAN_ID_REG(CAN2_BASE_PTR,37)
4331 #define CAN2_WORD037                             CAN_WORD0_REG(CAN2_BASE_PTR,37)
4332 #define CAN2_WORD137                             CAN_WORD1_REG(CAN2_BASE_PTR,37)
4333 #define CAN2_CS38                                CAN_CS_REG(CAN2_BASE_PTR,38)
4334 #define CAN2_ID38                                CAN_ID_REG(CAN2_BASE_PTR,38)
4335 #define CAN2_WORD038                             CAN_WORD0_REG(CAN2_BASE_PTR,38)
4336 #define CAN2_WORD138                             CAN_WORD1_REG(CAN2_BASE_PTR,38)
4337 #define CAN2_CS39                                CAN_CS_REG(CAN2_BASE_PTR,39)
4338 #define CAN2_ID39                                CAN_ID_REG(CAN2_BASE_PTR,39)
4339 #define CAN2_WORD039                             CAN_WORD0_REG(CAN2_BASE_PTR,39)
4340 #define CAN2_WORD139                             CAN_WORD1_REG(CAN2_BASE_PTR,39)
4341 #define CAN2_CS40                                CAN_CS_REG(CAN2_BASE_PTR,40)
4342 #define CAN2_ID40                                CAN_ID_REG(CAN2_BASE_PTR,40)
4343 #define CAN2_WORD040                             CAN_WORD0_REG(CAN2_BASE_PTR,40)
4344 #define CAN2_WORD140                             CAN_WORD1_REG(CAN2_BASE_PTR,40)
4345 #define CAN2_CS41                                CAN_CS_REG(CAN2_BASE_PTR,41)
4346 #define CAN2_ID41                                CAN_ID_REG(CAN2_BASE_PTR,41)
4347 #define CAN2_WORD041                             CAN_WORD0_REG(CAN2_BASE_PTR,41)
4348 #define CAN2_WORD141                             CAN_WORD1_REG(CAN2_BASE_PTR,41)
4349 #define CAN2_CS42                                CAN_CS_REG(CAN2_BASE_PTR,42)
4350 #define CAN2_ID42                                CAN_ID_REG(CAN2_BASE_PTR,42)
4351 #define CAN2_WORD042                             CAN_WORD0_REG(CAN2_BASE_PTR,42)
4352 #define CAN2_WORD142                             CAN_WORD1_REG(CAN2_BASE_PTR,42)
4353 #define CAN2_CS43                                CAN_CS_REG(CAN2_BASE_PTR,43)
4354 #define CAN2_ID43                                CAN_ID_REG(CAN2_BASE_PTR,43)
4355 #define CAN2_WORD043                             CAN_WORD0_REG(CAN2_BASE_PTR,43)
4356 #define CAN2_WORD143                             CAN_WORD1_REG(CAN2_BASE_PTR,43)
4357 #define CAN2_CS44                                CAN_CS_REG(CAN2_BASE_PTR,44)
4358 #define CAN2_ID44                                CAN_ID_REG(CAN2_BASE_PTR,44)
4359 #define CAN2_WORD044                             CAN_WORD0_REG(CAN2_BASE_PTR,44)
4360 #define CAN2_WORD144                             CAN_WORD1_REG(CAN2_BASE_PTR,44)
4361 #define CAN2_CS45                                CAN_CS_REG(CAN2_BASE_PTR,45)
4362 #define CAN2_ID45                                CAN_ID_REG(CAN2_BASE_PTR,45)
4363 #define CAN2_WORD045                             CAN_WORD0_REG(CAN2_BASE_PTR,45)
4364 #define CAN2_WORD145                             CAN_WORD1_REG(CAN2_BASE_PTR,45)
4365 #define CAN2_CS46                                CAN_CS_REG(CAN2_BASE_PTR,46)
4366 #define CAN2_ID46                                CAN_ID_REG(CAN2_BASE_PTR,46)
4367 #define CAN2_WORD046                             CAN_WORD0_REG(CAN2_BASE_PTR,46)
4368 #define CAN2_WORD146                             CAN_WORD1_REG(CAN2_BASE_PTR,46)
4369 #define CAN2_CS47                                CAN_CS_REG(CAN2_BASE_PTR,47)
4370 #define CAN2_ID47                                CAN_ID_REG(CAN2_BASE_PTR,47)
4371 #define CAN2_WORD047                             CAN_WORD0_REG(CAN2_BASE_PTR,47)
4372 #define CAN2_WORD147                             CAN_WORD1_REG(CAN2_BASE_PTR,47)
4373 #define CAN2_CS48                                CAN_CS_REG(CAN2_BASE_PTR,48)
4374 #define CAN2_ID48                                CAN_ID_REG(CAN2_BASE_PTR,48)
4375 #define CAN2_WORD048                             CAN_WORD0_REG(CAN2_BASE_PTR,48)
4376 #define CAN2_WORD148                             CAN_WORD1_REG(CAN2_BASE_PTR,48)
4377 #define CAN2_CS49                                CAN_CS_REG(CAN2_BASE_PTR,49)
4378 #define CAN2_ID49                                CAN_ID_REG(CAN2_BASE_PTR,49)
4379 #define CAN2_WORD049                             CAN_WORD0_REG(CAN2_BASE_PTR,49)
4380 #define CAN2_WORD149                             CAN_WORD1_REG(CAN2_BASE_PTR,49)
4381 #define CAN2_CS50                                CAN_CS_REG(CAN2_BASE_PTR,50)
4382 #define CAN2_ID50                                CAN_ID_REG(CAN2_BASE_PTR,50)
4383 #define CAN2_WORD050                             CAN_WORD0_REG(CAN2_BASE_PTR,50)
4384 #define CAN2_WORD150                             CAN_WORD1_REG(CAN2_BASE_PTR,50)
4385 #define CAN2_CS51                                CAN_CS_REG(CAN2_BASE_PTR,51)
4386 #define CAN2_ID51                                CAN_ID_REG(CAN2_BASE_PTR,51)
4387 #define CAN2_WORD051                             CAN_WORD0_REG(CAN2_BASE_PTR,51)
4388 #define CAN2_WORD151                             CAN_WORD1_REG(CAN2_BASE_PTR,51)
4389 #define CAN2_CS52                                CAN_CS_REG(CAN2_BASE_PTR,52)
4390 #define CAN2_ID52                                CAN_ID_REG(CAN2_BASE_PTR,52)
4391 #define CAN2_WORD052                             CAN_WORD0_REG(CAN2_BASE_PTR,52)
4392 #define CAN2_WORD152                             CAN_WORD1_REG(CAN2_BASE_PTR,52)
4393 #define CAN2_CS53                                CAN_CS_REG(CAN2_BASE_PTR,53)
4394 #define CAN2_ID53                                CAN_ID_REG(CAN2_BASE_PTR,53)
4395 #define CAN2_WORD053                             CAN_WORD0_REG(CAN2_BASE_PTR,53)
4396 #define CAN2_WORD153                             CAN_WORD1_REG(CAN2_BASE_PTR,53)
4397 #define CAN2_CS54                                CAN_CS_REG(CAN2_BASE_PTR,54)
4398 #define CAN2_ID54                                CAN_ID_REG(CAN2_BASE_PTR,54)
4399 #define CAN2_WORD054                             CAN_WORD0_REG(CAN2_BASE_PTR,54)
4400 #define CAN2_WORD154                             CAN_WORD1_REG(CAN2_BASE_PTR,54)
4401 #define CAN2_CS55                                CAN_CS_REG(CAN2_BASE_PTR,55)
4402 #define CAN2_ID55                                CAN_ID_REG(CAN2_BASE_PTR,55)
4403 #define CAN2_WORD055                             CAN_WORD0_REG(CAN2_BASE_PTR,55)
4404 #define CAN2_WORD155                             CAN_WORD1_REG(CAN2_BASE_PTR,55)
4405 #define CAN2_CS56                                CAN_CS_REG(CAN2_BASE_PTR,56)
4406 #define CAN2_ID56                                CAN_ID_REG(CAN2_BASE_PTR,56)
4407 #define CAN2_WORD056                             CAN_WORD0_REG(CAN2_BASE_PTR,56)
4408 #define CAN2_WORD156                             CAN_WORD1_REG(CAN2_BASE_PTR,56)
4409 #define CAN2_CS57                                CAN_CS_REG(CAN2_BASE_PTR,57)
4410 #define CAN2_ID57                                CAN_ID_REG(CAN2_BASE_PTR,57)
4411 #define CAN2_WORD057                             CAN_WORD0_REG(CAN2_BASE_PTR,57)
4412 #define CAN2_WORD157                             CAN_WORD1_REG(CAN2_BASE_PTR,57)
4413 #define CAN2_CS58                                CAN_CS_REG(CAN2_BASE_PTR,58)
4414 #define CAN2_ID58                                CAN_ID_REG(CAN2_BASE_PTR,58)
4415 #define CAN2_WORD058                             CAN_WORD0_REG(CAN2_BASE_PTR,58)
4416 #define CAN2_WORD158                             CAN_WORD1_REG(CAN2_BASE_PTR,58)
4417 #define CAN2_CS59                                CAN_CS_REG(CAN2_BASE_PTR,59)
4418 #define CAN2_ID59                                CAN_ID_REG(CAN2_BASE_PTR,59)
4419 #define CAN2_WORD059                             CAN_WORD0_REG(CAN2_BASE_PTR,59)
4420 #define CAN2_WORD159                             CAN_WORD1_REG(CAN2_BASE_PTR,59)
4421 #define CAN2_CS60                                CAN_CS_REG(CAN2_BASE_PTR,60)
4422 #define CAN2_ID60                                CAN_ID_REG(CAN2_BASE_PTR,60)
4423 #define CAN2_WORD060                             CAN_WORD0_REG(CAN2_BASE_PTR,60)
4424 #define CAN2_WORD160                             CAN_WORD1_REG(CAN2_BASE_PTR,60)
4425 #define CAN2_CS61                                CAN_CS_REG(CAN2_BASE_PTR,61)
4426 #define CAN2_ID61                                CAN_ID_REG(CAN2_BASE_PTR,61)
4427 #define CAN2_WORD061                             CAN_WORD0_REG(CAN2_BASE_PTR,61)
4428 #define CAN2_WORD161                             CAN_WORD1_REG(CAN2_BASE_PTR,61)
4429 #define CAN2_CS62                                CAN_CS_REG(CAN2_BASE_PTR,62)
4430 #define CAN2_ID62                                CAN_ID_REG(CAN2_BASE_PTR,62)
4431 #define CAN2_WORD062                             CAN_WORD0_REG(CAN2_BASE_PTR,62)
4432 #define CAN2_WORD162                             CAN_WORD1_REG(CAN2_BASE_PTR,62)
4433 #define CAN2_CS63                                CAN_CS_REG(CAN2_BASE_PTR,63)
4434 #define CAN2_ID63                                CAN_ID_REG(CAN2_BASE_PTR,63)
4435 #define CAN2_WORD063                             CAN_WORD0_REG(CAN2_BASE_PTR,63)
4436 #define CAN2_WORD163                             CAN_WORD1_REG(CAN2_BASE_PTR,63)
4437 #define CAN2_RXIMR0                              CAN_RXIMR_REG(CAN2_BASE_PTR,0)
4438 #define CAN2_RXIMR1                              CAN_RXIMR_REG(CAN2_BASE_PTR,1)
4439 #define CAN2_RXIMR2                              CAN_RXIMR_REG(CAN2_BASE_PTR,2)
4440 #define CAN2_RXIMR3                              CAN_RXIMR_REG(CAN2_BASE_PTR,3)
4441 #define CAN2_RXIMR4                              CAN_RXIMR_REG(CAN2_BASE_PTR,4)
4442 #define CAN2_RXIMR5                              CAN_RXIMR_REG(CAN2_BASE_PTR,5)
4443 #define CAN2_RXIMR6                              CAN_RXIMR_REG(CAN2_BASE_PTR,6)
4444 #define CAN2_RXIMR7                              CAN_RXIMR_REG(CAN2_BASE_PTR,7)
4445 #define CAN2_RXIMR8                              CAN_RXIMR_REG(CAN2_BASE_PTR,8)
4446 #define CAN2_RXIMR9                              CAN_RXIMR_REG(CAN2_BASE_PTR,9)
4447 #define CAN2_RXIMR10                             CAN_RXIMR_REG(CAN2_BASE_PTR,10)
4448 #define CAN2_RXIMR11                             CAN_RXIMR_REG(CAN2_BASE_PTR,11)
4449 #define CAN2_RXIMR12                             CAN_RXIMR_REG(CAN2_BASE_PTR,12)
4450 #define CAN2_RXIMR13                             CAN_RXIMR_REG(CAN2_BASE_PTR,13)
4451 #define CAN2_RXIMR14                             CAN_RXIMR_REG(CAN2_BASE_PTR,14)
4452 #define CAN2_RXIMR15                             CAN_RXIMR_REG(CAN2_BASE_PTR,15)
4453 #define CAN2_RXIMR16                             CAN_RXIMR_REG(CAN2_BASE_PTR,16)
4454 #define CAN2_RXIMR17                             CAN_RXIMR_REG(CAN2_BASE_PTR,17)
4455 #define CAN2_RXIMR18                             CAN_RXIMR_REG(CAN2_BASE_PTR,18)
4456 #define CAN2_RXIMR19                             CAN_RXIMR_REG(CAN2_BASE_PTR,19)
4457 #define CAN2_RXIMR20                             CAN_RXIMR_REG(CAN2_BASE_PTR,20)
4458 #define CAN2_RXIMR21                             CAN_RXIMR_REG(CAN2_BASE_PTR,21)
4459 #define CAN2_RXIMR22                             CAN_RXIMR_REG(CAN2_BASE_PTR,22)
4460 #define CAN2_RXIMR23                             CAN_RXIMR_REG(CAN2_BASE_PTR,23)
4461 #define CAN2_RXIMR24                             CAN_RXIMR_REG(CAN2_BASE_PTR,24)
4462 #define CAN2_RXIMR25                             CAN_RXIMR_REG(CAN2_BASE_PTR,25)
4463 #define CAN2_RXIMR26                             CAN_RXIMR_REG(CAN2_BASE_PTR,26)
4464 #define CAN2_RXIMR27                             CAN_RXIMR_REG(CAN2_BASE_PTR,27)
4465 #define CAN2_RXIMR28                             CAN_RXIMR_REG(CAN2_BASE_PTR,28)
4466 #define CAN2_RXIMR29                             CAN_RXIMR_REG(CAN2_BASE_PTR,29)
4467 #define CAN2_RXIMR30                             CAN_RXIMR_REG(CAN2_BASE_PTR,30)
4468 #define CAN2_RXIMR31                             CAN_RXIMR_REG(CAN2_BASE_PTR,31)
4469 #define CAN2_RXIMR32                             CAN_RXIMR_REG(CAN2_BASE_PTR,32)
4470 #define CAN2_RXIMR33                             CAN_RXIMR_REG(CAN2_BASE_PTR,33)
4471 #define CAN2_RXIMR34                             CAN_RXIMR_REG(CAN2_BASE_PTR,34)
4472 #define CAN2_RXIMR35                             CAN_RXIMR_REG(CAN2_BASE_PTR,35)
4473 #define CAN2_RXIMR36                             CAN_RXIMR_REG(CAN2_BASE_PTR,36)
4474 #define CAN2_RXIMR37                             CAN_RXIMR_REG(CAN2_BASE_PTR,37)
4475 #define CAN2_RXIMR38                             CAN_RXIMR_REG(CAN2_BASE_PTR,38)
4476 #define CAN2_RXIMR39                             CAN_RXIMR_REG(CAN2_BASE_PTR,39)
4477 #define CAN2_RXIMR40                             CAN_RXIMR_REG(CAN2_BASE_PTR,40)
4478 #define CAN2_RXIMR41                             CAN_RXIMR_REG(CAN2_BASE_PTR,41)
4479 #define CAN2_RXIMR42                             CAN_RXIMR_REG(CAN2_BASE_PTR,42)
4480 #define CAN2_RXIMR43                             CAN_RXIMR_REG(CAN2_BASE_PTR,43)
4481 #define CAN2_RXIMR44                             CAN_RXIMR_REG(CAN2_BASE_PTR,44)
4482 #define CAN2_RXIMR45                             CAN_RXIMR_REG(CAN2_BASE_PTR,45)
4483 #define CAN2_RXIMR46                             CAN_RXIMR_REG(CAN2_BASE_PTR,46)
4484 #define CAN2_RXIMR47                             CAN_RXIMR_REG(CAN2_BASE_PTR,47)
4485 #define CAN2_RXIMR48                             CAN_RXIMR_REG(CAN2_BASE_PTR,48)
4486 #define CAN2_RXIMR49                             CAN_RXIMR_REG(CAN2_BASE_PTR,49)
4487 #define CAN2_RXIMR50                             CAN_RXIMR_REG(CAN2_BASE_PTR,50)
4488 #define CAN2_RXIMR51                             CAN_RXIMR_REG(CAN2_BASE_PTR,51)
4489 #define CAN2_RXIMR52                             CAN_RXIMR_REG(CAN2_BASE_PTR,52)
4490 #define CAN2_RXIMR53                             CAN_RXIMR_REG(CAN2_BASE_PTR,53)
4491 #define CAN2_RXIMR54                             CAN_RXIMR_REG(CAN2_BASE_PTR,54)
4492 #define CAN2_RXIMR55                             CAN_RXIMR_REG(CAN2_BASE_PTR,55)
4493 #define CAN2_RXIMR56                             CAN_RXIMR_REG(CAN2_BASE_PTR,56)
4494 #define CAN2_RXIMR57                             CAN_RXIMR_REG(CAN2_BASE_PTR,57)
4495 #define CAN2_RXIMR58                             CAN_RXIMR_REG(CAN2_BASE_PTR,58)
4496 #define CAN2_RXIMR59                             CAN_RXIMR_REG(CAN2_BASE_PTR,59)
4497 #define CAN2_RXIMR60                             CAN_RXIMR_REG(CAN2_BASE_PTR,60)
4498 #define CAN2_RXIMR61                             CAN_RXIMR_REG(CAN2_BASE_PTR,61)
4499 #define CAN2_RXIMR62                             CAN_RXIMR_REG(CAN2_BASE_PTR,62)
4500 #define CAN2_RXIMR63                             CAN_RXIMR_REG(CAN2_BASE_PTR,63)
4501 #define CAN2_GFWR                                CAN_GFWR_REG(CAN2_BASE_PTR)
4502 /* CAN - Register array accessors */
4503 #define CAN1_CS(index)                           CAN_CS_REG(CAN1_BASE_PTR,index)
4504 #define CAN2_CS(index)                           CAN_CS_REG(CAN2_BASE_PTR,index)
4505 #define CAN1_ID(index)                           CAN_ID_REG(CAN1_BASE_PTR,index)
4506 #define CAN2_ID(index)                           CAN_ID_REG(CAN2_BASE_PTR,index)
4507 #define CAN1_WORD0(index)                        CAN_WORD0_REG(CAN1_BASE_PTR,index)
4508 #define CAN2_WORD0(index)                        CAN_WORD0_REG(CAN2_BASE_PTR,index)
4509 #define CAN1_WORD1(index)                        CAN_WORD1_REG(CAN1_BASE_PTR,index)
4510 #define CAN2_WORD1(index)                        CAN_WORD1_REG(CAN2_BASE_PTR,index)
4511 #define CAN1_RXIMR(index)                        CAN_RXIMR_REG(CAN1_BASE_PTR,index)
4512 #define CAN2_RXIMR(index)                        CAN_RXIMR_REG(CAN2_BASE_PTR,index)
4513 /*!
4514  * @}
4515  */ /* end of group CAN_Register_Accessor_Macros */
4516 
4517 
4518 /*!
4519  * @}
4520  */ /* end of group CAN_Peripheral */
4521 
4522 /* ----------------------------------------------------------------------------
4523    -- CCM Peripheral Access Layer
4524    ---------------------------------------------------------------------------- */
4525 
4526 /*!
4527  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
4528  * @{
4529  */
4530 
4531 /** CCM - Register Layout Typedef */
4532 typedef struct {
4533   __IO  uint32_t GPR0;                                   /**< General Purpose Register, offset: 0x0 */
4534   __IO  uint32_t GPR0_SET;                               /**< General Purpose Register, offset: 0x4 */
4535   __IO  uint32_t GPR0_CLR;                               /**< General Purpose Register, offset: 0x8 */
4536   __IO  uint32_t GPR0_TOG;                               /**< General Purpose Register, offset: 0xC */
4537   uint8_t RESERVED_0[2032];
4538   struct {                                         /* offset: 0x800, array step: 0x10 */
4539   __IO    uint32_t PLL_CTRL;                               /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
4540   __IO    uint32_t PLL_CTRL_SET;                           /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
4541   __IO    uint32_t PLL_CTRL_CLR;                           /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
4542   __IO    uint32_t PLL_CTRL_TOG;                           /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
4543  } PLL_CTRL[33];
4544   uint8_t RESERVED_1[13808];
4545   struct {                                         /* offset: 0x4000, array step: 0x10 */
4546   __IO    uint32_t CCGR;                                   /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
4547   __IO    uint32_t CCGR_SET;                               /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
4548   __IO    uint32_t CCGR_CLR;                               /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
4549   __IO    uint32_t CCGR_TOG;                               /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
4550  } CCGR[191];
4551   uint8_t RESERVED_2[13328];
4552   struct {                                         /* offset: 0x8000, array step: 0x80 */
4553   __IO    uint32_t TARGET_ROOT;                            /**< Target Register, array offset: 0x8000, array step: 0x80 */
4554   __IO    uint32_t TARGET_ROOT_SET;                        /**< Target Register, array offset: 0x8004, array step: 0x80 */
4555   __IO    uint32_t TARGET_ROOT_CLR;                        /**< Target Register, array offset: 0x8008, array step: 0x80 */
4556   __IO    uint32_t TARGET_ROOT_TOG;                        /**< Target Register, array offset: 0x800C, array step: 0x80 */
4557   __IO    uint32_t MISC;                                   /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
4558   __IO    uint32_t MISC_ROOT_SET;                          /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
4559   __IO    uint32_t MISC_ROOT_CLR;                          /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
4560   __IO    uint32_t MISC_ROOT_TOG;                          /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
4561   __IO    uint32_t POST;                                   /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
4562   __IO    uint32_t POST_ROOT_SET;                          /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
4563   __IO    uint32_t POST_ROOT_CLR;                          /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
4564   __IO    uint32_t POST_ROOT_TOG;                          /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
4565   __IO    uint32_t PRE;                                    /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
4566   __IO    uint32_t PRE_ROOT_SET;                           /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
4567   __IO    uint32_t PRE_ROOT_CLR;                           /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
4568   __IO    uint32_t PRE_ROOT_TOG;                           /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
4569     uint8_t RESERVED_0[48];
4570   __IO    uint32_t ACCESS_CTRL;                            /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
4571   __IO    uint32_t ACCESS_CTRL_ROOT_SET;                   /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
4572   __IO    uint32_t ACCESS_CTRL_ROOT_CLR;                   /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
4573   __IO    uint32_t ACCESS_CTRL_ROOT_TOG;                   /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
4574  } ACCESS_CTRL_ROOT_TOG[125];
4575 } CCM_Type, *CCM_MemMapPtr;
4576 /* ----------------------------------------------------------------------------
4577    -- CCM - Register accessor macros
4578    ---------------------------------------------------------------------------- */
4579 
4580 /*!
4581  * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros
4582  * @{
4583  */
4584 
4585 
4586 /* CCM - Register accessors */
4587 #define CCM_GPR0_REG(base)                       ((base)->GPR0)
4588 #define CCM_GPR0_SET_REG(base)                   ((base)->GPR0_SET)
4589 #define CCM_GPR0_CLR_REG(base)                   ((base)->GPR0_CLR)
4590 #define CCM_GPR0_TOG_REG(base)                   ((base)->GPR0_TOG)
4591 #define CCM_PLL_CTRL_REG(base,index)             ((base)->PLL_CTRL[index].PLL_CTRL)
4592 #define CCM_PLL_CTRL_SET_REG(base,index)         ((base)->PLL_CTRL[index].PLL_CTRL_SET)
4593 #define CCM_PLL_CTRL_CLR_REG(base,index)         ((base)->PLL_CTRL[index].PLL_CTRL_CLR)
4594 #define CCM_PLL_CTRL_TOG_REG(base,index)         ((base)->PLL_CTRL[index].PLL_CTRL_TOG)
4595 #define CCM_CCGR_REG(base,index)                 ((base)->CCGR[index].CCGR)
4596 #define CCM_CCGR_SET_REG(base,index)             ((base)->CCGR[index].CCGR_SET)
4597 #define CCM_CCGR_CLR_REG(base,index)             ((base)->CCGR[index].CCGR_CLR)
4598 #define CCM_CCGR_TOG_REG(base,index)             ((base)->CCGR[index].CCGR_TOG)
4599 #define CCM_TARGET_ROOT_REG(base,index)          ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT)
4600 #define CCM_TARGET_ROOT_SET_REG(base,index)      ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_SET)
4601 #define CCM_TARGET_ROOT_CLR_REG(base,index)      ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_CLR)
4602 #define CCM_TARGET_ROOT_TOG_REG(base,index)      ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_TOG)
4603 #define CCM_MISC_REG(base,index)                 ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC)
4604 #define CCM_MISC_ROOT_SET_REG(base,index)        ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_SET)
4605 #define CCM_MISC_ROOT_CLR_REG(base,index)        ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_CLR)
4606 #define CCM_MISC_ROOT_TOG_REG(base,index)        ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_TOG)
4607 #define CCM_POST_REG(base,index)                 ((base)->ACCESS_CTRL_ROOT_TOG[index].POST)
4608 #define CCM_POST_ROOT_SET_REG(base,index)        ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_SET)
4609 #define CCM_POST_ROOT_CLR_REG(base,index)        ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_CLR)
4610 #define CCM_POST_ROOT_TOG_REG(base,index)        ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_TOG)
4611 #define CCM_PRE_REG(base,index)                  ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE)
4612 #define CCM_PRE_ROOT_SET_REG(base,index)         ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_SET)
4613 #define CCM_PRE_ROOT_CLR_REG(base,index)         ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_CLR)
4614 #define CCM_PRE_ROOT_TOG_REG(base,index)         ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_TOG)
4615 #define CCM_ACCESS_CTRL_REG(base,index)          ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL)
4616 #define CCM_ACCESS_CTRL_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_SET)
4617 #define CCM_ACCESS_CTRL_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_CLR)
4618 #define CCM_ACCESS_CTRL_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_TOG)
4619 
4620 /*!
4621  * @}
4622  */ /* end of group CCM_Register_Accessor_Macros */
4623 /* ----------------------------------------------------------------------------
4624    -- CCM Register Masks
4625    ---------------------------------------------------------------------------- */
4626 
4627 /*!
4628  * @addtogroup CCM_Register_Masks CCM Register Masks
4629  * @{
4630  */
4631 
4632 /* GPR0 Bit Fields */
4633 #define CCM_GPR0_GP0_MASK                        0xFFFFFFFFu
4634 #define CCM_GPR0_GP0_SHIFT                       0
4635 #define CCM_GPR0_GP0(x)                          (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_GP0_SHIFT))&CCM_GPR0_GP0_MASK)
4636 /* GPR0_SET Bit Fields */
4637 #define CCM_GPR0_SET_GP0_MASK                    0xFFFFFFFFu
4638 #define CCM_GPR0_SET_GP0_SHIFT                   0
4639 #define CCM_GPR0_SET_GP0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_SET_GP0_SHIFT))&CCM_GPR0_SET_GP0_MASK)
4640 /* GPR0_CLR Bit Fields */
4641 #define CCM_GPR0_CLR_GP0_MASK                    0xFFFFFFFFu
4642 #define CCM_GPR0_CLR_GP0_SHIFT                   0
4643 #define CCM_GPR0_CLR_GP0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_CLR_GP0_SHIFT))&CCM_GPR0_CLR_GP0_MASK)
4644 /* GPR0_TOG Bit Fields */
4645 #define CCM_GPR0_TOG_GP0_MASK                    0xFFFFFFFFu
4646 #define CCM_GPR0_TOG_GP0_SHIFT                   0
4647 #define CCM_GPR0_TOG_GP0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_TOG_GP0_SHIFT))&CCM_GPR0_TOG_GP0_MASK)
4648 /* PLL_CTRL Bit Fields */
4649 #define CCM_PLL_CTRL_SETTING0_MASK               0x3u
4650 #define CCM_PLL_CTRL_SETTING0_SHIFT              0
4651 #define CCM_PLL_CTRL_SETTING0(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING0_SHIFT))&CCM_PLL_CTRL_SETTING0_MASK)
4652 #define CCM_PLL_CTRL_SETTING1_MASK               0x30u
4653 #define CCM_PLL_CTRL_SETTING1_SHIFT              4
4654 #define CCM_PLL_CTRL_SETTING1(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING1_SHIFT))&CCM_PLL_CTRL_SETTING1_MASK)
4655 #define CCM_PLL_CTRL_SETTING2_MASK               0x300u
4656 #define CCM_PLL_CTRL_SETTING2_SHIFT              8
4657 #define CCM_PLL_CTRL_SETTING2(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING2_SHIFT))&CCM_PLL_CTRL_SETTING2_MASK)
4658 #define CCM_PLL_CTRL_SETTING3_MASK               0x3000u
4659 #define CCM_PLL_CTRL_SETTING3_SHIFT              12
4660 #define CCM_PLL_CTRL_SETTING3(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING3_SHIFT))&CCM_PLL_CTRL_SETTING3_MASK)
4661 /* PLL_CTRL_SET Bit Fields */
4662 #define CCM_PLL_CTRL_SET_SETTING0_MASK           0x3u
4663 #define CCM_PLL_CTRL_SET_SETTING0_SHIFT          0
4664 #define CCM_PLL_CTRL_SET_SETTING0(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING0_SHIFT))&CCM_PLL_CTRL_SET_SETTING0_MASK)
4665 #define CCM_PLL_CTRL_SET_SETTING1_MASK           0x30u
4666 #define CCM_PLL_CTRL_SET_SETTING1_SHIFT          4
4667 #define CCM_PLL_CTRL_SET_SETTING1(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING1_SHIFT))&CCM_PLL_CTRL_SET_SETTING1_MASK)
4668 #define CCM_PLL_CTRL_SET_SETTING2_MASK           0x300u
4669 #define CCM_PLL_CTRL_SET_SETTING2_SHIFT          8
4670 #define CCM_PLL_CTRL_SET_SETTING2(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING2_SHIFT))&CCM_PLL_CTRL_SET_SETTING2_MASK)
4671 #define CCM_PLL_CTRL_SET_SETTING3_MASK           0x3000u
4672 #define CCM_PLL_CTRL_SET_SETTING3_SHIFT          12
4673 #define CCM_PLL_CTRL_SET_SETTING3(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING3_SHIFT))&CCM_PLL_CTRL_SET_SETTING3_MASK)
4674 /* PLL_CTRL_CLR Bit Fields */
4675 #define CCM_PLL_CTRL_CLR_SETTING0_MASK           0x3u
4676 #define CCM_PLL_CTRL_CLR_SETTING0_SHIFT          0
4677 #define CCM_PLL_CTRL_CLR_SETTING0(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING0_SHIFT))&CCM_PLL_CTRL_CLR_SETTING0_MASK)
4678 #define CCM_PLL_CTRL_CLR_SETTING1_MASK           0x30u
4679 #define CCM_PLL_CTRL_CLR_SETTING1_SHIFT          4
4680 #define CCM_PLL_CTRL_CLR_SETTING1(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING1_SHIFT))&CCM_PLL_CTRL_CLR_SETTING1_MASK)
4681 #define CCM_PLL_CTRL_CLR_SETTING2_MASK           0x300u
4682 #define CCM_PLL_CTRL_CLR_SETTING2_SHIFT          8
4683 #define CCM_PLL_CTRL_CLR_SETTING2(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING2_SHIFT))&CCM_PLL_CTRL_CLR_SETTING2_MASK)
4684 #define CCM_PLL_CTRL_CLR_SETTING3_MASK           0x3000u
4685 #define CCM_PLL_CTRL_CLR_SETTING3_SHIFT          12
4686 #define CCM_PLL_CTRL_CLR_SETTING3(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING3_SHIFT))&CCM_PLL_CTRL_CLR_SETTING3_MASK)
4687 /* PLL_CTRL_TOG Bit Fields */
4688 #define CCM_PLL_CTRL_TOG_SETTING0_MASK           0x3u
4689 #define CCM_PLL_CTRL_TOG_SETTING0_SHIFT          0
4690 #define CCM_PLL_CTRL_TOG_SETTING0(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING0_SHIFT))&CCM_PLL_CTRL_TOG_SETTING0_MASK)
4691 #define CCM_PLL_CTRL_TOG_SETTING1_MASK           0x30u
4692 #define CCM_PLL_CTRL_TOG_SETTING1_SHIFT          4
4693 #define CCM_PLL_CTRL_TOG_SETTING1(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING1_SHIFT))&CCM_PLL_CTRL_TOG_SETTING1_MASK)
4694 #define CCM_PLL_CTRL_TOG_SETTING2_MASK           0x300u
4695 #define CCM_PLL_CTRL_TOG_SETTING2_SHIFT          8
4696 #define CCM_PLL_CTRL_TOG_SETTING2(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING2_SHIFT))&CCM_PLL_CTRL_TOG_SETTING2_MASK)
4697 #define CCM_PLL_CTRL_TOG_SETTING3_MASK           0x3000u
4698 #define CCM_PLL_CTRL_TOG_SETTING3_SHIFT          12
4699 #define CCM_PLL_CTRL_TOG_SETTING3(x)             (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING3_SHIFT))&CCM_PLL_CTRL_TOG_SETTING3_MASK)
4700 /* CCGR Bit Fields */
4701 #define CCM_CCGR_SETTING0_MASK                   0x3u
4702 #define CCM_CCGR_SETTING0_SHIFT                  0
4703 #define CCM_CCGR_SETTING0(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING0_SHIFT))&CCM_CCGR_SETTING0_MASK)
4704 #define CCM_CCGR_SETTING1_MASK                   0x30u
4705 #define CCM_CCGR_SETTING1_SHIFT                  4
4706 #define CCM_CCGR_SETTING1(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING1_SHIFT))&CCM_CCGR_SETTING1_MASK)
4707 #define CCM_CCGR_SETTING2_MASK                   0x300u
4708 #define CCM_CCGR_SETTING2_SHIFT                  8
4709 #define CCM_CCGR_SETTING2(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING2_SHIFT))&CCM_CCGR_SETTING2_MASK)
4710 #define CCM_CCGR_SETTING3_MASK                   0x3000u
4711 #define CCM_CCGR_SETTING3_SHIFT                  12
4712 #define CCM_CCGR_SETTING3(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING3_SHIFT))&CCM_CCGR_SETTING3_MASK)
4713 /* CCGR_SET Bit Fields */
4714 #define CCM_CCGR_SET_SETTING0_MASK               0x3u
4715 #define CCM_CCGR_SET_SETTING0_SHIFT              0
4716 #define CCM_CCGR_SET_SETTING0(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING0_SHIFT))&CCM_CCGR_SET_SETTING0_MASK)
4717 #define CCM_CCGR_SET_SETTING1_MASK               0x30u
4718 #define CCM_CCGR_SET_SETTING1_SHIFT              4
4719 #define CCM_CCGR_SET_SETTING1(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING1_SHIFT))&CCM_CCGR_SET_SETTING1_MASK)
4720 #define CCM_CCGR_SET_SETTING2_MASK               0x300u
4721 #define CCM_CCGR_SET_SETTING2_SHIFT              8
4722 #define CCM_CCGR_SET_SETTING2(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING2_SHIFT))&CCM_CCGR_SET_SETTING2_MASK)
4723 #define CCM_CCGR_SET_SETTING3_MASK               0x3000u
4724 #define CCM_CCGR_SET_SETTING3_SHIFT              12
4725 #define CCM_CCGR_SET_SETTING3(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING3_SHIFT))&CCM_CCGR_SET_SETTING3_MASK)
4726 /* CCGR_CLR Bit Fields */
4727 #define CCM_CCGR_CLR_SETTING0_MASK               0x3u
4728 #define CCM_CCGR_CLR_SETTING0_SHIFT              0
4729 #define CCM_CCGR_CLR_SETTING0(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING0_SHIFT))&CCM_CCGR_CLR_SETTING0_MASK)
4730 #define CCM_CCGR_CLR_SETTING1_MASK               0x30u
4731 #define CCM_CCGR_CLR_SETTING1_SHIFT              4
4732 #define CCM_CCGR_CLR_SETTING1(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING1_SHIFT))&CCM_CCGR_CLR_SETTING1_MASK)
4733 #define CCM_CCGR_CLR_SETTING2_MASK               0x300u
4734 #define CCM_CCGR_CLR_SETTING2_SHIFT              8
4735 #define CCM_CCGR_CLR_SETTING2(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING2_SHIFT))&CCM_CCGR_CLR_SETTING2_MASK)
4736 #define CCM_CCGR_CLR_SETTING3_MASK               0x3000u
4737 #define CCM_CCGR_CLR_SETTING3_SHIFT              12
4738 #define CCM_CCGR_CLR_SETTING3(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING3_SHIFT))&CCM_CCGR_CLR_SETTING3_MASK)
4739 /* CCGR_TOG Bit Fields */
4740 #define CCM_CCGR_TOG_SETTING0_MASK               0x3u
4741 #define CCM_CCGR_TOG_SETTING0_SHIFT              0
4742 #define CCM_CCGR_TOG_SETTING0(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING0_SHIFT))&CCM_CCGR_TOG_SETTING0_MASK)
4743 #define CCM_CCGR_TOG_SETTING1_MASK               0x30u
4744 #define CCM_CCGR_TOG_SETTING1_SHIFT              4
4745 #define CCM_CCGR_TOG_SETTING1(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING1_SHIFT))&CCM_CCGR_TOG_SETTING1_MASK)
4746 #define CCM_CCGR_TOG_SETTING2_MASK               0x300u
4747 #define CCM_CCGR_TOG_SETTING2_SHIFT              8
4748 #define CCM_CCGR_TOG_SETTING2(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING2_SHIFT))&CCM_CCGR_TOG_SETTING2_MASK)
4749 #define CCM_CCGR_TOG_SETTING3_MASK               0x3000u
4750 #define CCM_CCGR_TOG_SETTING3_SHIFT              12
4751 #define CCM_CCGR_TOG_SETTING3(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING3_SHIFT))&CCM_CCGR_TOG_SETTING3_MASK)
4752 /* TARGET_ROOT Bit Fields */
4753 #define CCM_TARGET_ROOT_POST_PODF_MASK           0x3Fu
4754 #define CCM_TARGET_ROOT_POST_PODF_SHIFT          0
4755 #define CCM_TARGET_ROOT_POST_PODF(x)             (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_POST_PODF_SHIFT))&CCM_TARGET_ROOT_POST_PODF_MASK)
4756 #define CCM_TARGET_ROOT_PRE_PODF_MASK            0x70000u
4757 #define CCM_TARGET_ROOT_PRE_PODF_SHIFT           16
4758 #define CCM_TARGET_ROOT_PRE_PODF(x)              (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_PRE_PODF_MASK)
4759 #define CCM_TARGET_ROOT_MUX_MASK                 0x7000000u
4760 #define CCM_TARGET_ROOT_MUX_SHIFT                24
4761 #define CCM_TARGET_ROOT_MUX(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_MUX_SHIFT))&CCM_TARGET_ROOT_MUX_MASK)
4762 #define CCM_TARGET_ROOT_ENABLE_MASK              0x10000000u
4763 #define CCM_TARGET_ROOT_ENABLE_SHIFT             28
4764 /* TARGET_ROOT_SET Bit Fields */
4765 #define CCM_TARGET_ROOT_SET_POST_PODF_MASK       0x3Fu
4766 #define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT      0
4767 #define CCM_TARGET_ROOT_SET_POST_PODF(x)         (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT_SET_POST_PODF_MASK)
4768 #define CCM_TARGET_ROOT_SET_PRE_PODF_MASK        0x70000u
4769 #define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT       16
4770 #define CCM_TARGET_ROOT_SET_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
4771 #define CCM_TARGET_ROOT_SET_MUX_MASK             0x7000000u
4772 #define CCM_TARGET_ROOT_SET_MUX_SHIFT            24
4773 #define CCM_TARGET_ROOT_SET_MUX(x)               (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_SET_MUX_SHIFT))&CCM_TARGET_ROOT_SET_MUX_MASK)
4774 #define CCM_TARGET_ROOT_SET_ENABLE_MASK          0x10000000u
4775 #define CCM_TARGET_ROOT_SET_ENABLE_SHIFT         28
4776 /* TARGET_ROOT_CLR Bit Fields */
4777 #define CCM_TARGET_ROOT_CLR_POST_PODF_MASK       0x3Fu
4778 #define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT      0
4779 #define CCM_TARGET_ROOT_CLR_POST_PODF(x)         (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
4780 #define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK        0x70000u
4781 #define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT       16
4782 #define CCM_TARGET_ROOT_CLR_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
4783 #define CCM_TARGET_ROOT_CLR_MUX_MASK             0x7000000u
4784 #define CCM_TARGET_ROOT_CLR_MUX_SHIFT            24
4785 #define CCM_TARGET_ROOT_CLR_MUX(x)               (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_CLR_MUX_SHIFT))&CCM_TARGET_ROOT_CLR_MUX_MASK)
4786 #define CCM_TARGET_ROOT_CLR_ENABLE_MASK          0x10000000u
4787 #define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT         28
4788 /* TARGET_ROOT_TOG Bit Fields */
4789 #define CCM_TARGET_ROOT_TOG_POST_PODF_MASK       0x3Fu
4790 #define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT      0
4791 #define CCM_TARGET_ROOT_TOG_POST_PODF(x)         (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
4792 #define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK        0x70000u
4793 #define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT       16
4794 #define CCM_TARGET_ROOT_TOG_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
4795 #define CCM_TARGET_ROOT_TOG_MUX_MASK             0x7000000u
4796 #define CCM_TARGET_ROOT_TOG_MUX_SHIFT            24
4797 #define CCM_TARGET_ROOT_TOG_MUX(x)               (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_TOG_MUX_SHIFT))&CCM_TARGET_ROOT_TOG_MUX_MASK)
4798 #define CCM_TARGET_ROOT_TOG_ENABLE_MASK          0x10000000u
4799 #define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT         28
4800 /* MISC Bit Fields */
4801 #define CCM_MISC_AUTHEN_FAIL_MASK                0x1u
4802 #define CCM_MISC_AUTHEN_FAIL_SHIFT               0
4803 #define CCM_MISC_TIMEOUT_MASK                    0x10u
4804 #define CCM_MISC_TIMEOUT_SHIFT                   4
4805 #define CCM_MISC_VIOLATE_MASK                    0x100u
4806 #define CCM_MISC_VIOLATE_SHIFT                   8
4807 /* MISC_ROOT_SET Bit Fields */
4808 #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK       0x1u
4809 #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT      0
4810 #define CCM_MISC_ROOT_SET_TIMEOUT_MASK           0x10u
4811 #define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT          4
4812 #define CCM_MISC_ROOT_SET_VIOLATE_MASK           0x100u
4813 #define CCM_MISC_ROOT_SET_VIOLATE_SHIFT          8
4814 /* MISC_ROOT_CLR Bit Fields */
4815 #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK       0x1u
4816 #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT      0
4817 #define CCM_MISC_ROOT_CLR_TIMEOUT_MASK           0x10u
4818 #define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT          4
4819 #define CCM_MISC_ROOT_CLR_VIOLATE_MASK           0x100u
4820 #define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT          8
4821 /* MISC_ROOT_TOG Bit Fields */
4822 #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK       0x1u
4823 #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT      0
4824 #define CCM_MISC_ROOT_TOG_TIMEOUT_MASK           0x10u
4825 #define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT          4
4826 #define CCM_MISC_ROOT_TOG_VIOLATE_MASK           0x100u
4827 #define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT          8
4828 /* POST Bit Fields */
4829 #define CCM_POST_POST_PODF_MASK                  0x3Fu
4830 #define CCM_POST_POST_PODF_SHIFT                 0
4831 #define CCM_POST_POST_PODF(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_POST_POST_PODF_SHIFT))&CCM_POST_POST_PODF_MASK)
4832 #define CCM_POST_BUSY1_MASK                      0x80u
4833 #define CCM_POST_BUSY1_SHIFT                     7
4834 #define CCM_POST_SELECT_MASK                     0x10000000u
4835 #define CCM_POST_SELECT_SHIFT                    28
4836 #define CCM_POST_BUSY2_MASK                      0x80000000u
4837 #define CCM_POST_BUSY2_SHIFT                     31
4838 /* POST_ROOT_SET Bit Fields */
4839 #define CCM_POST_ROOT_SET_POST_PODF_MASK         0x3Fu
4840 #define CCM_POST_ROOT_SET_POST_PODF_SHIFT        0
4841 #define CCM_POST_ROOT_SET_POST_PODF(x)           (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT_SET_POST_PODF_SHIFT))&CCM_POST_ROOT_SET_POST_PODF_MASK)
4842 #define CCM_POST_ROOT_SET_BUSY1_MASK             0x80u
4843 #define CCM_POST_ROOT_SET_BUSY1_SHIFT            7
4844 #define CCM_POST_ROOT_SET_SELECT_MASK            0x10000000u
4845 #define CCM_POST_ROOT_SET_SELECT_SHIFT           28
4846 #define CCM_POST_ROOT_SET_BUSY2_MASK             0x80000000u
4847 #define CCM_POST_ROOT_SET_BUSY2_SHIFT            31
4848 /* POST_ROOT_CLR Bit Fields */
4849 #define CCM_POST_ROOT_CLR_POST_PODF_MASK         0x3Fu
4850 #define CCM_POST_ROOT_CLR_POST_PODF_SHIFT        0
4851 #define CCM_POST_ROOT_CLR_POST_PODF(x)           (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT_CLR_POST_PODF_MASK)
4852 #define CCM_POST_ROOT_CLR_BUSY1_MASK             0x80u
4853 #define CCM_POST_ROOT_CLR_BUSY1_SHIFT            7
4854 #define CCM_POST_ROOT_CLR_SELECT_MASK            0x10000000u
4855 #define CCM_POST_ROOT_CLR_SELECT_SHIFT           28
4856 #define CCM_POST_ROOT_CLR_BUSY2_MASK             0x80000000u
4857 #define CCM_POST_ROOT_CLR_BUSY2_SHIFT            31
4858 /* POST_ROOT_TOG Bit Fields */
4859 #define CCM_POST_ROOT_TOG_POST_PODF_MASK         0x3Fu
4860 #define CCM_POST_ROOT_TOG_POST_PODF_SHIFT        0
4861 #define CCM_POST_ROOT_TOG_POST_PODF(x)           (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT_TOG_POST_PODF_MASK)
4862 #define CCM_POST_ROOT_TOG_BUSY1_MASK             0x80u
4863 #define CCM_POST_ROOT_TOG_BUSY1_SHIFT            7
4864 #define CCM_POST_ROOT_TOG_SELECT_MASK            0x10000000u
4865 #define CCM_POST_ROOT_TOG_SELECT_SHIFT           28
4866 #define CCM_POST_ROOT_TOG_BUSY2_MASK             0x80000000u
4867 #define CCM_POST_ROOT_TOG_BUSY2_SHIFT            31
4868 /* PRE Bit Fields */
4869 #define CCM_PRE_PRE_PODF_B_MASK                  0x7u
4870 #define CCM_PRE_PRE_PODF_B_SHIFT                 0
4871 #define CCM_PRE_PRE_PODF_B(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_PRE_PRE_PODF_B_SHIFT))&CCM_PRE_PRE_PODF_B_MASK)
4872 #define CCM_PRE_BUSY0_MASK                       0x8u
4873 #define CCM_PRE_BUSY0_SHIFT                      3
4874 #define CCM_PRE_MUX_B_MASK                       0x700u
4875 #define CCM_PRE_MUX_B_SHIFT                      8
4876 #define CCM_PRE_MUX_B(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_PRE_MUX_B_SHIFT))&CCM_PRE_MUX_B_MASK)
4877 #define CCM_PRE_EN_B_MASK                        0x1000u
4878 #define CCM_PRE_EN_B_SHIFT                       12
4879 #define CCM_PRE_BUSY1_MASK                       0x8000u
4880 #define CCM_PRE_BUSY1_SHIFT                      15
4881 #define CCM_PRE_PRE_PODF_A_MASK                  0x70000u
4882 #define CCM_PRE_PRE_PODF_A_SHIFT                 16
4883 #define CCM_PRE_PRE_PODF_A(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_PRE_PRE_PODF_A_SHIFT))&CCM_PRE_PRE_PODF_A_MASK)
4884 #define CCM_PRE_BUSY3_MASK                       0x80000u
4885 #define CCM_PRE_BUSY3_SHIFT                      19
4886 #define CCM_PRE_MUX_A_MASK                       0x7000000u
4887 #define CCM_PRE_MUX_A_SHIFT                      24
4888 #define CCM_PRE_MUX_A(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_PRE_MUX_A_SHIFT))&CCM_PRE_MUX_A_MASK)
4889 #define CCM_PRE_EN_A_MASK                        0x10000000u
4890 #define CCM_PRE_EN_A_SHIFT                       28
4891 #define CCM_PRE_BUSY4_MASK                       0x80000000u
4892 #define CCM_PRE_BUSY4_SHIFT                      31
4893 /* PRE_ROOT_SET Bit Fields */
4894 #define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK         0x7u
4895 #define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT        0
4896 #define CCM_PRE_ROOT_SET_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
4897 #define CCM_PRE_ROOT_SET_BUSY0_MASK              0x8u
4898 #define CCM_PRE_ROOT_SET_BUSY0_SHIFT             3
4899 #define CCM_PRE_ROOT_SET_MUX_B_MASK              0x700u
4900 #define CCM_PRE_ROOT_SET_MUX_B_SHIFT             8
4901 #define CCM_PRE_ROOT_SET_MUX_B(x)                (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_MUX_B_SHIFT))&CCM_PRE_ROOT_SET_MUX_B_MASK)
4902 #define CCM_PRE_ROOT_SET_EN_B_MASK               0x1000u
4903 #define CCM_PRE_ROOT_SET_EN_B_SHIFT              12
4904 #define CCM_PRE_ROOT_SET_BUSY1_MASK              0x8000u
4905 #define CCM_PRE_ROOT_SET_BUSY1_SHIFT             15
4906 #define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK         0x70000u
4907 #define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT        16
4908 #define CCM_PRE_ROOT_SET_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
4909 #define CCM_PRE_ROOT_SET_BUSY3_MASK              0x80000u
4910 #define CCM_PRE_ROOT_SET_BUSY3_SHIFT             19
4911 #define CCM_PRE_ROOT_SET_MUX_A_MASK              0x7000000u
4912 #define CCM_PRE_ROOT_SET_MUX_A_SHIFT             24
4913 #define CCM_PRE_ROOT_SET_MUX_A(x)                (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_MUX_A_SHIFT))&CCM_PRE_ROOT_SET_MUX_A_MASK)
4914 #define CCM_PRE_ROOT_SET_EN_A_MASK               0x10000000u
4915 #define CCM_PRE_ROOT_SET_EN_A_SHIFT              28
4916 #define CCM_PRE_ROOT_SET_BUSY4_MASK              0x80000000u
4917 #define CCM_PRE_ROOT_SET_BUSY4_SHIFT             31
4918 /* PRE_ROOT_CLR Bit Fields */
4919 #define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK         0x7u
4920 #define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT        0
4921 #define CCM_PRE_ROOT_CLR_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
4922 #define CCM_PRE_ROOT_CLR_BUSY0_MASK              0x8u
4923 #define CCM_PRE_ROOT_CLR_BUSY0_SHIFT             3
4924 #define CCM_PRE_ROOT_CLR_MUX_B_MASK              0x700u
4925 #define CCM_PRE_ROOT_CLR_MUX_B_SHIFT             8
4926 #define CCM_PRE_ROOT_CLR_MUX_B(x)                (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT_CLR_MUX_B_MASK)
4927 #define CCM_PRE_ROOT_CLR_EN_B_MASK               0x1000u
4928 #define CCM_PRE_ROOT_CLR_EN_B_SHIFT              12
4929 #define CCM_PRE_ROOT_CLR_BUSY1_MASK              0x8000u
4930 #define CCM_PRE_ROOT_CLR_BUSY1_SHIFT             15
4931 #define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK         0x70000u
4932 #define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT        16
4933 #define CCM_PRE_ROOT_CLR_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
4934 #define CCM_PRE_ROOT_CLR_BUSY3_MASK              0x80000u
4935 #define CCM_PRE_ROOT_CLR_BUSY3_SHIFT             19
4936 #define CCM_PRE_ROOT_CLR_MUX_A_MASK              0x7000000u
4937 #define CCM_PRE_ROOT_CLR_MUX_A_SHIFT             24
4938 #define CCM_PRE_ROOT_CLR_MUX_A(x)                (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT_CLR_MUX_A_MASK)
4939 #define CCM_PRE_ROOT_CLR_EN_A_MASK               0x10000000u
4940 #define CCM_PRE_ROOT_CLR_EN_A_SHIFT              28
4941 #define CCM_PRE_ROOT_CLR_BUSY4_MASK              0x80000000u
4942 #define CCM_PRE_ROOT_CLR_BUSY4_SHIFT             31
4943 /* PRE_ROOT_TOG Bit Fields */
4944 #define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK         0x7u
4945 #define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT        0
4946 #define CCM_PRE_ROOT_TOG_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
4947 #define CCM_PRE_ROOT_TOG_BUSY0_MASK              0x8u
4948 #define CCM_PRE_ROOT_TOG_BUSY0_SHIFT             3
4949 #define CCM_PRE_ROOT_TOG_MUX_B_MASK              0x700u
4950 #define CCM_PRE_ROOT_TOG_MUX_B_SHIFT             8
4951 #define CCM_PRE_ROOT_TOG_MUX_B(x)                (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT_TOG_MUX_B_MASK)
4952 #define CCM_PRE_ROOT_TOG_EN_B_MASK               0x1000u
4953 #define CCM_PRE_ROOT_TOG_EN_B_SHIFT              12
4954 #define CCM_PRE_ROOT_TOG_BUSY1_MASK              0x8000u
4955 #define CCM_PRE_ROOT_TOG_BUSY1_SHIFT             15
4956 #define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK         0x70000u
4957 #define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT        16
4958 #define CCM_PRE_ROOT_TOG_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
4959 #define CCM_PRE_ROOT_TOG_BUSY3_MASK              0x80000u
4960 #define CCM_PRE_ROOT_TOG_BUSY3_SHIFT             19
4961 #define CCM_PRE_ROOT_TOG_MUX_A_MASK              0x7000000u
4962 #define CCM_PRE_ROOT_TOG_MUX_A_SHIFT             24
4963 #define CCM_PRE_ROOT_TOG_MUX_A(x)                (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT_TOG_MUX_A_MASK)
4964 #define CCM_PRE_ROOT_TOG_EN_A_MASK               0x10000000u
4965 #define CCM_PRE_ROOT_TOG_EN_A_SHIFT              28
4966 #define CCM_PRE_ROOT_TOG_BUSY4_MASK              0x80000000u
4967 #define CCM_PRE_ROOT_TOG_BUSY4_SHIFT             31
4968 /* ACCESS_CTRL Bit Fields */
4969 #define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK        0xFu
4970 #define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT       0
4971 #define CCM_ACCESS_CTRL_DOMAIN0_INFO(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
4972 #define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK        0xF0u
4973 #define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT       4
4974 #define CCM_ACCESS_CTRL_DOMAIN1_INFO(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
4975 #define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK        0xF00u
4976 #define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT       8
4977 #define CCM_ACCESS_CTRL_DOMAIN2_INFO(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
4978 #define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK        0xF000u
4979 #define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT       12
4980 #define CCM_ACCESS_CTRL_DOMAIN3_INFO(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
4981 #define CCM_ACCESS_CTRL_OWNER_ID_MASK            0x30000u
4982 #define CCM_ACCESS_CTRL_OWNER_ID_SHIFT           16
4983 #define CCM_ACCESS_CTRL_OWNER_ID(x)              (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_OWNER_ID_MASK)
4984 #define CCM_ACCESS_CTRL_MUTEX_MASK               0x100000u
4985 #define CCM_ACCESS_CTRL_MUTEX_SHIFT              20
4986 #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK   0x1000000u
4987 #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT  24
4988 #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK   0x2000000u
4989 #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT  25
4990 #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK   0x4000000u
4991 #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT  26
4992 #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK   0x8000000u
4993 #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT  27
4994 #define CCM_ACCESS_CTRL_SEMA_EN_MASK             0x10000000u
4995 #define CCM_ACCESS_CTRL_SEMA_EN_SHIFT            28
4996 #define CCM_ACCESS_CTRL_LOCK_MASK                0x80000000u
4997 #define CCM_ACCESS_CTRL_LOCK_SHIFT               31
4998 /* ACCESS_CTRL_ROOT_SET Bit Fields */
4999 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK 0xFu
5000 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT 0
5001 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
5002 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK 0xF0u
5003 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT 4
5004 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
5005 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK 0xF00u
5006 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT 8
5007 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
5008 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK 0xF000u
5009 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT 12
5010 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
5011 #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK   0x30000u
5012 #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT  16
5013 #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
5014 #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK      0x100000u
5015 #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT     20
5016 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK 0x1000000u
5017 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT 24
5018 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK 0x2000000u
5019 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT 25
5020 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK 0x4000000u
5021 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT 26
5022 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK 0x8000000u
5023 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT 27
5024 #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK    0x10000000u
5025 #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT   28
5026 #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK       0x80000000u
5027 #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT      31
5028 /* ACCESS_CTRL_ROOT_CLR Bit Fields */
5029 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK 0xFu
5030 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT 0
5031 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
5032 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK 0xF0u
5033 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT 4
5034 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
5035 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK 0xF00u
5036 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT 8
5037 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
5038 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK 0xF000u
5039 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT 12
5040 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
5041 #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK   0x30000u
5042 #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT  16
5043 #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
5044 #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK      0x100000u
5045 #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT     20
5046 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK 0x1000000u
5047 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT 24
5048 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK 0x2000000u
5049 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT 25
5050 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK 0x4000000u
5051 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT 26
5052 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK 0x8000000u
5053 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT 27
5054 #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK    0x10000000u
5055 #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT   28
5056 #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK       0x80000000u
5057 #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT      31
5058 /* ACCESS_CTRL_ROOT_TOG Bit Fields */
5059 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK 0xFu
5060 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT 0
5061 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
5062 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK 0xF0u
5063 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT 4
5064 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
5065 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK 0xF00u
5066 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT 8
5067 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
5068 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK 0xF000u
5069 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT 12
5070 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
5071 #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK   0x30000u
5072 #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT  16
5073 #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
5074 #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK      0x100000u
5075 #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT     20
5076 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK 0x1000000u
5077 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT 24
5078 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK 0x2000000u
5079 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT 25
5080 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK 0x4000000u
5081 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT 26
5082 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK 0x8000000u
5083 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT 27
5084 #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK    0x10000000u
5085 #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT   28
5086 #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK       0x80000000u
5087 #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT      31
5088 
5089 /*!
5090  * @}
5091  */ /* end of group CCM_Register_Masks */
5092 
5093 /* CCM - Peripheral instance base addresses */
5094 /** Peripheral CCM base address */
5095 #define CCM_BASE                                 (0x30380000u)
5096 /** Peripheral CCM base pointer */
5097 #define CCM                                      ((CCM_Type *)CCM_BASE)
5098 #define CCM_BASE_PTR                             (CCM)
5099 /** Array initializer of CCM peripheral base addresses */
5100 #define CCM_BASE_ADDRS                           { CCM_BASE }
5101 /** Array initializer of CCM peripheral base pointers */
5102 #define CCM_BASE_PTRS                            { CCM }
5103 /* ----------------------------------------------------------------------------
5104    -- CCM - Register accessor macros
5105    ---------------------------------------------------------------------------- */
5106 
5107 /*!
5108  * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros
5109  * @{
5110  */
5111 
5112 
5113 /* CCM - Register instance definitions */
5114 /* CCM */
5115 #define CCM_GPR0                                 CCM_GPR0_REG(CCM_BASE_PTR)
5116 #define CCM_GPR0_SET                             CCM_GPR0_SET_REG(CCM_BASE_PTR)
5117 #define CCM_GPR0_CLR                             CCM_GPR0_CLR_REG(CCM_BASE_PTR)
5118 #define CCM_GPR0_TOG                             CCM_GPR0_TOG_REG(CCM_BASE_PTR)
5119 #define CCM_PLL_CTRL0                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,0)
5120 #define CCM_PLL_CTRL0_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,0)
5121 #define CCM_PLL_CTRL0_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,0)
5122 #define CCM_PLL_CTRL0_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,0)
5123 #define CCM_PLL_CTRL1                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,1)
5124 #define CCM_PLL_CTRL1_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,1)
5125 #define CCM_PLL_CTRL1_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,1)
5126 #define CCM_PLL_CTRL1_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,1)
5127 #define CCM_PLL_CTRL2                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,2)
5128 #define CCM_PLL_CTRL2_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,2)
5129 #define CCM_PLL_CTRL2_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,2)
5130 #define CCM_PLL_CTRL2_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,2)
5131 #define CCM_PLL_CTRL3                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,3)
5132 #define CCM_PLL_CTRL3_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,3)
5133 #define CCM_PLL_CTRL3_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,3)
5134 #define CCM_PLL_CTRL3_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,3)
5135 #define CCM_PLL_CTRL4                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,4)
5136 #define CCM_PLL_CTRL4_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,4)
5137 #define CCM_PLL_CTRL4_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,4)
5138 #define CCM_PLL_CTRL4_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,4)
5139 #define CCM_PLL_CTRL5                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,5)
5140 #define CCM_PLL_CTRL5_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,5)
5141 #define CCM_PLL_CTRL5_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,5)
5142 #define CCM_PLL_CTRL5_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,5)
5143 #define CCM_PLL_CTRL6                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,6)
5144 #define CCM_PLL_CTRL6_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,6)
5145 #define CCM_PLL_CTRL6_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,6)
5146 #define CCM_PLL_CTRL6_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,6)
5147 #define CCM_PLL_CTRL7                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,7)
5148 #define CCM_PLL_CTRL7_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,7)
5149 #define CCM_PLL_CTRL7_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,7)
5150 #define CCM_PLL_CTRL7_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,7)
5151 #define CCM_PLL_CTRL8                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,8)
5152 #define CCM_PLL_CTRL8_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,8)
5153 #define CCM_PLL_CTRL8_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,8)
5154 #define CCM_PLL_CTRL8_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,8)
5155 #define CCM_PLL_CTRL9                            CCM_PLL_CTRL_REG(CCM_BASE_PTR,9)
5156 #define CCM_PLL_CTRL9_SET                        CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,9)
5157 #define CCM_PLL_CTRL9_CLR                        CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,9)
5158 #define CCM_PLL_CTRL9_TOG                        CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,9)
5159 #define CCM_PLL_CTRL10                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,10)
5160 #define CCM_PLL_CTRL10_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,10)
5161 #define CCM_PLL_CTRL10_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,10)
5162 #define CCM_PLL_CTRL10_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,10)
5163 #define CCM_PLL_CTRL11                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,11)
5164 #define CCM_PLL_CTRL11_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,11)
5165 #define CCM_PLL_CTRL11_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,11)
5166 #define CCM_PLL_CTRL11_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,11)
5167 #define CCM_PLL_CTRL12                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,12)
5168 #define CCM_PLL_CTRL12_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,12)
5169 #define CCM_PLL_CTRL12_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,12)
5170 #define CCM_PLL_CTRL12_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,12)
5171 #define CCM_PLL_CTRL13                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,13)
5172 #define CCM_PLL_CTRL13_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,13)
5173 #define CCM_PLL_CTRL13_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,13)
5174 #define CCM_PLL_CTRL13_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,13)
5175 #define CCM_PLL_CTRL14                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,14)
5176 #define CCM_PLL_CTRL14_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,14)
5177 #define CCM_PLL_CTRL14_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,14)
5178 #define CCM_PLL_CTRL14_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,14)
5179 #define CCM_PLL_CTRL15                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,15)
5180 #define CCM_PLL_CTRL15_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,15)
5181 #define CCM_PLL_CTRL15_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,15)
5182 #define CCM_PLL_CTRL15_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,15)
5183 #define CCM_PLL_CTRL16                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,16)
5184 #define CCM_PLL_CTRL16_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,16)
5185 #define CCM_PLL_CTRL16_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,16)
5186 #define CCM_PLL_CTRL16_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,16)
5187 #define CCM_PLL_CTRL17                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,17)
5188 #define CCM_PLL_CTRL17_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,17)
5189 #define CCM_PLL_CTRL17_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,17)
5190 #define CCM_PLL_CTRL17_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,17)
5191 #define CCM_PLL_CTRL18                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,18)
5192 #define CCM_PLL_CTRL18_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,18)
5193 #define CCM_PLL_CTRL18_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,18)
5194 #define CCM_PLL_CTRL18_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,18)
5195 #define CCM_PLL_CTRL19                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,19)
5196 #define CCM_PLL_CTRL19_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,19)
5197 #define CCM_PLL_CTRL19_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,19)
5198 #define CCM_PLL_CTRL19_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,19)
5199 #define CCM_PLL_CTRL20                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,20)
5200 #define CCM_PLL_CTRL20_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,20)
5201 #define CCM_PLL_CTRL20_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,20)
5202 #define CCM_PLL_CTRL20_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,20)
5203 #define CCM_PLL_CTRL21                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,21)
5204 #define CCM_PLL_CTRL21_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,21)
5205 #define CCM_PLL_CTRL21_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,21)
5206 #define CCM_PLL_CTRL21_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,21)
5207 #define CCM_PLL_CTRL22                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,22)
5208 #define CCM_PLL_CTRL22_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,22)
5209 #define CCM_PLL_CTRL22_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,22)
5210 #define CCM_PLL_CTRL22_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,22)
5211 #define CCM_PLL_CTRL23                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,23)
5212 #define CCM_PLL_CTRL23_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,23)
5213 #define CCM_PLL_CTRL23_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,23)
5214 #define CCM_PLL_CTRL23_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,23)
5215 #define CCM_PLL_CTRL24                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,24)
5216 #define CCM_PLL_CTRL24_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,24)
5217 #define CCM_PLL_CTRL24_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,24)
5218 #define CCM_PLL_CTRL24_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,24)
5219 #define CCM_PLL_CTRL25                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,25)
5220 #define CCM_PLL_CTRL25_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,25)
5221 #define CCM_PLL_CTRL25_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,25)
5222 #define CCM_PLL_CTRL25_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,25)
5223 #define CCM_PLL_CTRL26                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,26)
5224 #define CCM_PLL_CTRL26_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,26)
5225 #define CCM_PLL_CTRL26_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,26)
5226 #define CCM_PLL_CTRL26_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,26)
5227 #define CCM_PLL_CTRL27                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,27)
5228 #define CCM_PLL_CTRL27_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,27)
5229 #define CCM_PLL_CTRL27_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,27)
5230 #define CCM_PLL_CTRL27_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,27)
5231 #define CCM_PLL_CTRL28                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,28)
5232 #define CCM_PLL_CTRL28_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,28)
5233 #define CCM_PLL_CTRL28_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,28)
5234 #define CCM_PLL_CTRL28_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,28)
5235 #define CCM_PLL_CTRL29                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,29)
5236 #define CCM_PLL_CTRL29_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,29)
5237 #define CCM_PLL_CTRL29_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,29)
5238 #define CCM_PLL_CTRL29_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,29)
5239 #define CCM_PLL_CTRL30                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,30)
5240 #define CCM_PLL_CTRL30_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,30)
5241 #define CCM_PLL_CTRL30_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,30)
5242 #define CCM_PLL_CTRL30_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,30)
5243 #define CCM_PLL_CTRL31                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,31)
5244 #define CCM_PLL_CTRL31_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,31)
5245 #define CCM_PLL_CTRL31_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,31)
5246 #define CCM_PLL_CTRL31_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,31)
5247 #define CCM_PLL_CTRL32                           CCM_PLL_CTRL_REG(CCM_BASE_PTR,32)
5248 #define CCM_PLL_CTRL32_SET                       CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,32)
5249 #define CCM_PLL_CTRL32_CLR                       CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,32)
5250 #define CCM_PLL_CTRL32_TOG                       CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,32)
5251 #define CCM_CCGR0                                CCM_CCGR_REG(CCM_BASE_PTR,0)
5252 #define CCM_CCGR0_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,0)
5253 #define CCM_CCGR0_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,0)
5254 #define CCM_CCGR0_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,0)
5255 #define CCM_CCGR1                                CCM_CCGR_REG(CCM_BASE_PTR,1)
5256 #define CCM_CCGR1_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,1)
5257 #define CCM_CCGR1_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,1)
5258 #define CCM_CCGR1_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,1)
5259 #define CCM_CCGR2                                CCM_CCGR_REG(CCM_BASE_PTR,2)
5260 #define CCM_CCGR2_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,2)
5261 #define CCM_CCGR2_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,2)
5262 #define CCM_CCGR2_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,2)
5263 #define CCM_CCGR3                                CCM_CCGR_REG(CCM_BASE_PTR,3)
5264 #define CCM_CCGR3_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,3)
5265 #define CCM_CCGR3_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,3)
5266 #define CCM_CCGR3_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,3)
5267 #define CCM_CCGR4                                CCM_CCGR_REG(CCM_BASE_PTR,4)
5268 #define CCM_CCGR4_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,4)
5269 #define CCM_CCGR4_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,4)
5270 #define CCM_CCGR4_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,4)
5271 #define CCM_CCGR5                                CCM_CCGR_REG(CCM_BASE_PTR,5)
5272 #define CCM_CCGR5_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,5)
5273 #define CCM_CCGR5_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,5)
5274 #define CCM_CCGR5_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,5)
5275 #define CCM_CCGR6                                CCM_CCGR_REG(CCM_BASE_PTR,6)
5276 #define CCM_CCGR6_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,6)
5277 #define CCM_CCGR6_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,6)
5278 #define CCM_CCGR6_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,6)
5279 #define CCM_CCGR7                                CCM_CCGR_REG(CCM_BASE_PTR,7)
5280 #define CCM_CCGR7_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,7)
5281 #define CCM_CCGR7_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,7)
5282 #define CCM_CCGR7_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,7)
5283 #define CCM_CCGR8                                CCM_CCGR_REG(CCM_BASE_PTR,8)
5284 #define CCM_CCGR8_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,8)
5285 #define CCM_CCGR8_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,8)
5286 #define CCM_CCGR8_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,8)
5287 #define CCM_CCGR9                                CCM_CCGR_REG(CCM_BASE_PTR,9)
5288 #define CCM_CCGR9_SET                            CCM_CCGR_SET_REG(CCM_BASE_PTR,9)
5289 #define CCM_CCGR9_CLR                            CCM_CCGR_CLR_REG(CCM_BASE_PTR,9)
5290 #define CCM_CCGR9_TOG                            CCM_CCGR_TOG_REG(CCM_BASE_PTR,9)
5291 #define CCM_CCGR10                               CCM_CCGR_REG(CCM_BASE_PTR,10)
5292 #define CCM_CCGR10_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,10)
5293 #define CCM_CCGR10_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,10)
5294 #define CCM_CCGR10_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,10)
5295 #define CCM_CCGR11                               CCM_CCGR_REG(CCM_BASE_PTR,11)
5296 #define CCM_CCGR11_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,11)
5297 #define CCM_CCGR11_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,11)
5298 #define CCM_CCGR11_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,11)
5299 #define CCM_CCGR12                               CCM_CCGR_REG(CCM_BASE_PTR,12)
5300 #define CCM_CCGR12_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,12)
5301 #define CCM_CCGR12_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,12)
5302 #define CCM_CCGR12_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,12)
5303 #define CCM_CCGR13                               CCM_CCGR_REG(CCM_BASE_PTR,13)
5304 #define CCM_CCGR13_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,13)
5305 #define CCM_CCGR13_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,13)
5306 #define CCM_CCGR13_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,13)
5307 #define CCM_CCGR14                               CCM_CCGR_REG(CCM_BASE_PTR,14)
5308 #define CCM_CCGR14_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,14)
5309 #define CCM_CCGR14_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,14)
5310 #define CCM_CCGR14_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,14)
5311 #define CCM_CCGR15                               CCM_CCGR_REG(CCM_BASE_PTR,15)
5312 #define CCM_CCGR15_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,15)
5313 #define CCM_CCGR15_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,15)
5314 #define CCM_CCGR15_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,15)
5315 #define CCM_CCGR16                               CCM_CCGR_REG(CCM_BASE_PTR,16)
5316 #define CCM_CCGR16_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,16)
5317 #define CCM_CCGR16_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,16)
5318 #define CCM_CCGR16_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,16)
5319 #define CCM_CCGR17                               CCM_CCGR_REG(CCM_BASE_PTR,17)
5320 #define CCM_CCGR17_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,17)
5321 #define CCM_CCGR17_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,17)
5322 #define CCM_CCGR17_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,17)
5323 #define CCM_CCGR18                               CCM_CCGR_REG(CCM_BASE_PTR,18)
5324 #define CCM_CCGR18_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,18)
5325 #define CCM_CCGR18_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,18)
5326 #define CCM_CCGR18_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,18)
5327 #define CCM_CCGR19                               CCM_CCGR_REG(CCM_BASE_PTR,19)
5328 #define CCM_CCGR19_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,19)
5329 #define CCM_CCGR19_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,19)
5330 #define CCM_CCGR19_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,19)
5331 #define CCM_CCGR20                               CCM_CCGR_REG(CCM_BASE_PTR,20)
5332 #define CCM_CCGR20_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,20)
5333 #define CCM_CCGR20_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,20)
5334 #define CCM_CCGR20_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,20)
5335 #define CCM_CCGR21                               CCM_CCGR_REG(CCM_BASE_PTR,21)
5336 #define CCM_CCGR21_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,21)
5337 #define CCM_CCGR21_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,21)
5338 #define CCM_CCGR21_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,21)
5339 #define CCM_CCGR22                               CCM_CCGR_REG(CCM_BASE_PTR,22)
5340 #define CCM_CCGR22_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,22)
5341 #define CCM_CCGR22_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,22)
5342 #define CCM_CCGR22_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,22)
5343 #define CCM_CCGR23                               CCM_CCGR_REG(CCM_BASE_PTR,23)
5344 #define CCM_CCGR23_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,23)
5345 #define CCM_CCGR23_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,23)
5346 #define CCM_CCGR23_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,23)
5347 #define CCM_CCGR24                               CCM_CCGR_REG(CCM_BASE_PTR,24)
5348 #define CCM_CCGR24_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,24)
5349 #define CCM_CCGR24_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,24)
5350 #define CCM_CCGR24_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,24)
5351 #define CCM_CCGR25                               CCM_CCGR_REG(CCM_BASE_PTR,25)
5352 #define CCM_CCGR25_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,25)
5353 #define CCM_CCGR25_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,25)
5354 #define CCM_CCGR25_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,25)
5355 #define CCM_CCGR26                               CCM_CCGR_REG(CCM_BASE_PTR,26)
5356 #define CCM_CCGR26_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,26)
5357 #define CCM_CCGR26_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,26)
5358 #define CCM_CCGR26_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,26)
5359 #define CCM_CCGR27                               CCM_CCGR_REG(CCM_BASE_PTR,27)
5360 #define CCM_CCGR27_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,27)
5361 #define CCM_CCGR27_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,27)
5362 #define CCM_CCGR27_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,27)
5363 #define CCM_CCGR28                               CCM_CCGR_REG(CCM_BASE_PTR,28)
5364 #define CCM_CCGR28_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,28)
5365 #define CCM_CCGR28_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,28)
5366 #define CCM_CCGR28_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,28)
5367 #define CCM_CCGR29                               CCM_CCGR_REG(CCM_BASE_PTR,29)
5368 #define CCM_CCGR29_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,29)
5369 #define CCM_CCGR29_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,29)
5370 #define CCM_CCGR29_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,29)
5371 #define CCM_CCGR30                               CCM_CCGR_REG(CCM_BASE_PTR,30)
5372 #define CCM_CCGR30_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,30)
5373 #define CCM_CCGR30_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,30)
5374 #define CCM_CCGR30_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,30)
5375 #define CCM_CCGR31                               CCM_CCGR_REG(CCM_BASE_PTR,31)
5376 #define CCM_CCGR31_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,31)
5377 #define CCM_CCGR31_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,31)
5378 #define CCM_CCGR31_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,31)
5379 #define CCM_CCGR32                               CCM_CCGR_REG(CCM_BASE_PTR,32)
5380 #define CCM_CCGR32_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,32)
5381 #define CCM_CCGR32_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,32)
5382 #define CCM_CCGR32_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,32)
5383 #define CCM_CCGR33                               CCM_CCGR_REG(CCM_BASE_PTR,33)
5384 #define CCM_CCGR33_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,33)
5385 #define CCM_CCGR33_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,33)
5386 #define CCM_CCGR33_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,33)
5387 #define CCM_CCGR34                               CCM_CCGR_REG(CCM_BASE_PTR,34)
5388 #define CCM_CCGR34_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,34)
5389 #define CCM_CCGR34_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,34)
5390 #define CCM_CCGR34_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,34)
5391 #define CCM_CCGR35                               CCM_CCGR_REG(CCM_BASE_PTR,35)
5392 #define CCM_CCGR35_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,35)
5393 #define CCM_CCGR35_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,35)
5394 #define CCM_CCGR35_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,35)
5395 #define CCM_CCGR36                               CCM_CCGR_REG(CCM_BASE_PTR,36)
5396 #define CCM_CCGR36_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,36)
5397 #define CCM_CCGR36_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,36)
5398 #define CCM_CCGR36_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,36)
5399 #define CCM_CCGR37                               CCM_CCGR_REG(CCM_BASE_PTR,37)
5400 #define CCM_CCGR37_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,37)
5401 #define CCM_CCGR37_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,37)
5402 #define CCM_CCGR37_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,37)
5403 #define CCM_CCGR38                               CCM_CCGR_REG(CCM_BASE_PTR,38)
5404 #define CCM_CCGR38_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,38)
5405 #define CCM_CCGR38_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,38)
5406 #define CCM_CCGR38_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,38)
5407 #define CCM_CCGR39                               CCM_CCGR_REG(CCM_BASE_PTR,39)
5408 #define CCM_CCGR39_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,39)
5409 #define CCM_CCGR39_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,39)
5410 #define CCM_CCGR39_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,39)
5411 #define CCM_CCGR40                               CCM_CCGR_REG(CCM_BASE_PTR,40)
5412 #define CCM_CCGR40_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,40)
5413 #define CCM_CCGR40_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,40)
5414 #define CCM_CCGR40_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,40)
5415 #define CCM_CCGR41                               CCM_CCGR_REG(CCM_BASE_PTR,41)
5416 #define CCM_CCGR41_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,41)
5417 #define CCM_CCGR41_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,41)
5418 #define CCM_CCGR41_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,41)
5419 #define CCM_CCGR42                               CCM_CCGR_REG(CCM_BASE_PTR,42)
5420 #define CCM_CCGR42_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,42)
5421 #define CCM_CCGR42_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,42)
5422 #define CCM_CCGR42_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,42)
5423 #define CCM_CCGR43                               CCM_CCGR_REG(CCM_BASE_PTR,43)
5424 #define CCM_CCGR43_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,43)
5425 #define CCM_CCGR43_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,43)
5426 #define CCM_CCGR43_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,43)
5427 #define CCM_CCGR44                               CCM_CCGR_REG(CCM_BASE_PTR,44)
5428 #define CCM_CCGR44_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,44)
5429 #define CCM_CCGR44_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,44)
5430 #define CCM_CCGR44_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,44)
5431 #define CCM_CCGR45                               CCM_CCGR_REG(CCM_BASE_PTR,45)
5432 #define CCM_CCGR45_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,45)
5433 #define CCM_CCGR45_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,45)
5434 #define CCM_CCGR45_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,45)
5435 #define CCM_CCGR46                               CCM_CCGR_REG(CCM_BASE_PTR,46)
5436 #define CCM_CCGR46_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,46)
5437 #define CCM_CCGR46_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,46)
5438 #define CCM_CCGR46_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,46)
5439 #define CCM_CCGR47                               CCM_CCGR_REG(CCM_BASE_PTR,47)
5440 #define CCM_CCGR47_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,47)
5441 #define CCM_CCGR47_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,47)
5442 #define CCM_CCGR47_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,47)
5443 #define CCM_CCGR48                               CCM_CCGR_REG(CCM_BASE_PTR,48)
5444 #define CCM_CCGR48_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,48)
5445 #define CCM_CCGR48_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,48)
5446 #define CCM_CCGR48_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,48)
5447 #define CCM_CCGR49                               CCM_CCGR_REG(CCM_BASE_PTR,49)
5448 #define CCM_CCGR49_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,49)
5449 #define CCM_CCGR49_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,49)
5450 #define CCM_CCGR49_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,49)
5451 #define CCM_CCGR50                               CCM_CCGR_REG(CCM_BASE_PTR,50)
5452 #define CCM_CCGR50_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,50)
5453 #define CCM_CCGR50_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,50)
5454 #define CCM_CCGR50_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,50)
5455 #define CCM_CCGR51                               CCM_CCGR_REG(CCM_BASE_PTR,51)
5456 #define CCM_CCGR51_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,51)
5457 #define CCM_CCGR51_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,51)
5458 #define CCM_CCGR51_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,51)
5459 #define CCM_CCGR52                               CCM_CCGR_REG(CCM_BASE_PTR,52)
5460 #define CCM_CCGR52_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,52)
5461 #define CCM_CCGR52_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,52)
5462 #define CCM_CCGR52_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,52)
5463 #define CCM_CCGR53                               CCM_CCGR_REG(CCM_BASE_PTR,53)
5464 #define CCM_CCGR53_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,53)
5465 #define CCM_CCGR53_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,53)
5466 #define CCM_CCGR53_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,53)
5467 #define CCM_CCGR54                               CCM_CCGR_REG(CCM_BASE_PTR,54)
5468 #define CCM_CCGR54_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,54)
5469 #define CCM_CCGR54_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,54)
5470 #define CCM_CCGR54_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,54)
5471 #define CCM_CCGR55                               CCM_CCGR_REG(CCM_BASE_PTR,55)
5472 #define CCM_CCGR55_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,55)
5473 #define CCM_CCGR55_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,55)
5474 #define CCM_CCGR55_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,55)
5475 #define CCM_CCGR56                               CCM_CCGR_REG(CCM_BASE_PTR,56)
5476 #define CCM_CCGR56_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,56)
5477 #define CCM_CCGR56_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,56)
5478 #define CCM_CCGR56_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,56)
5479 #define CCM_CCGR57                               CCM_CCGR_REG(CCM_BASE_PTR,57)
5480 #define CCM_CCGR57_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,57)
5481 #define CCM_CCGR57_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,57)
5482 #define CCM_CCGR57_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,57)
5483 #define CCM_CCGR58                               CCM_CCGR_REG(CCM_BASE_PTR,58)
5484 #define CCM_CCGR58_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,58)
5485 #define CCM_CCGR58_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,58)
5486 #define CCM_CCGR58_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,58)
5487 #define CCM_CCGR59                               CCM_CCGR_REG(CCM_BASE_PTR,59)
5488 #define CCM_CCGR59_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,59)
5489 #define CCM_CCGR59_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,59)
5490 #define CCM_CCGR59_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,59)
5491 #define CCM_CCGR60                               CCM_CCGR_REG(CCM_BASE_PTR,60)
5492 #define CCM_CCGR60_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,60)
5493 #define CCM_CCGR60_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,60)
5494 #define CCM_CCGR60_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,60)
5495 #define CCM_CCGR61                               CCM_CCGR_REG(CCM_BASE_PTR,61)
5496 #define CCM_CCGR61_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,61)
5497 #define CCM_CCGR61_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,61)
5498 #define CCM_CCGR61_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,61)
5499 #define CCM_CCGR62                               CCM_CCGR_REG(CCM_BASE_PTR,62)
5500 #define CCM_CCGR62_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,62)
5501 #define CCM_CCGR62_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,62)
5502 #define CCM_CCGR62_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,62)
5503 #define CCM_CCGR63                               CCM_CCGR_REG(CCM_BASE_PTR,63)
5504 #define CCM_CCGR63_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,63)
5505 #define CCM_CCGR63_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,63)
5506 #define CCM_CCGR63_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,63)
5507 #define CCM_CCGR64                               CCM_CCGR_REG(CCM_BASE_PTR,64)
5508 #define CCM_CCGR64_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,64)
5509 #define CCM_CCGR64_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,64)
5510 #define CCM_CCGR64_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,64)
5511 #define CCM_CCGR65                               CCM_CCGR_REG(CCM_BASE_PTR,65)
5512 #define CCM_CCGR65_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,65)
5513 #define CCM_CCGR65_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,65)
5514 #define CCM_CCGR65_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,65)
5515 #define CCM_CCGR66                               CCM_CCGR_REG(CCM_BASE_PTR,66)
5516 #define CCM_CCGR66_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,66)
5517 #define CCM_CCGR66_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,66)
5518 #define CCM_CCGR66_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,66)
5519 #define CCM_CCGR67                               CCM_CCGR_REG(CCM_BASE_PTR,67)
5520 #define CCM_CCGR67_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,67)
5521 #define CCM_CCGR67_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,67)
5522 #define CCM_CCGR67_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,67)
5523 #define CCM_CCGR68                               CCM_CCGR_REG(CCM_BASE_PTR,68)
5524 #define CCM_CCGR68_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,68)
5525 #define CCM_CCGR68_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,68)
5526 #define CCM_CCGR68_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,68)
5527 #define CCM_CCGR69                               CCM_CCGR_REG(CCM_BASE_PTR,69)
5528 #define CCM_CCGR69_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,69)
5529 #define CCM_CCGR69_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,69)
5530 #define CCM_CCGR69_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,69)
5531 #define CCM_CCGR70                               CCM_CCGR_REG(CCM_BASE_PTR,70)
5532 #define CCM_CCGR70_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,70)
5533 #define CCM_CCGR70_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,70)
5534 #define CCM_CCGR70_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,70)
5535 #define CCM_CCGR71                               CCM_CCGR_REG(CCM_BASE_PTR,71)
5536 #define CCM_CCGR71_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,71)
5537 #define CCM_CCGR71_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,71)
5538 #define CCM_CCGR71_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,71)
5539 #define CCM_CCGR72                               CCM_CCGR_REG(CCM_BASE_PTR,72)
5540 #define CCM_CCGR72_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,72)
5541 #define CCM_CCGR72_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,72)
5542 #define CCM_CCGR72_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,72)
5543 #define CCM_CCGR73                               CCM_CCGR_REG(CCM_BASE_PTR,73)
5544 #define CCM_CCGR73_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,73)
5545 #define CCM_CCGR73_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,73)
5546 #define CCM_CCGR73_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,73)
5547 #define CCM_CCGR74                               CCM_CCGR_REG(CCM_BASE_PTR,74)
5548 #define CCM_CCGR74_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,74)
5549 #define CCM_CCGR74_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,74)
5550 #define CCM_CCGR74_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,74)
5551 #define CCM_CCGR75                               CCM_CCGR_REG(CCM_BASE_PTR,75)
5552 #define CCM_CCGR75_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,75)
5553 #define CCM_CCGR75_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,75)
5554 #define CCM_CCGR75_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,75)
5555 #define CCM_CCGR76                               CCM_CCGR_REG(CCM_BASE_PTR,76)
5556 #define CCM_CCGR76_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,76)
5557 #define CCM_CCGR76_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,76)
5558 #define CCM_CCGR76_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,76)
5559 #define CCM_CCGR77                               CCM_CCGR_REG(CCM_BASE_PTR,77)
5560 #define CCM_CCGR77_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,77)
5561 #define CCM_CCGR77_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,77)
5562 #define CCM_CCGR77_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,77)
5563 #define CCM_CCGR78                               CCM_CCGR_REG(CCM_BASE_PTR,78)
5564 #define CCM_CCGR78_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,78)
5565 #define CCM_CCGR78_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,78)
5566 #define CCM_CCGR78_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,78)
5567 #define CCM_CCGR79                               CCM_CCGR_REG(CCM_BASE_PTR,79)
5568 #define CCM_CCGR79_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,79)
5569 #define CCM_CCGR79_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,79)
5570 #define CCM_CCGR79_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,79)
5571 #define CCM_CCGR80                               CCM_CCGR_REG(CCM_BASE_PTR,80)
5572 #define CCM_CCGR80_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,80)
5573 #define CCM_CCGR80_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,80)
5574 #define CCM_CCGR80_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,80)
5575 #define CCM_CCGR81                               CCM_CCGR_REG(CCM_BASE_PTR,81)
5576 #define CCM_CCGR81_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,81)
5577 #define CCM_CCGR81_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,81)
5578 #define CCM_CCGR81_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,81)
5579 #define CCM_CCGR82                               CCM_CCGR_REG(CCM_BASE_PTR,82)
5580 #define CCM_CCGR82_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,82)
5581 #define CCM_CCGR82_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,82)
5582 #define CCM_CCGR82_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,82)
5583 #define CCM_CCGR83                               CCM_CCGR_REG(CCM_BASE_PTR,83)
5584 #define CCM_CCGR83_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,83)
5585 #define CCM_CCGR83_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,83)
5586 #define CCM_CCGR83_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,83)
5587 #define CCM_CCGR84                               CCM_CCGR_REG(CCM_BASE_PTR,84)
5588 #define CCM_CCGR84_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,84)
5589 #define CCM_CCGR84_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,84)
5590 #define CCM_CCGR84_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,84)
5591 #define CCM_CCGR85                               CCM_CCGR_REG(CCM_BASE_PTR,85)
5592 #define CCM_CCGR85_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,85)
5593 #define CCM_CCGR85_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,85)
5594 #define CCM_CCGR85_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,85)
5595 #define CCM_CCGR86                               CCM_CCGR_REG(CCM_BASE_PTR,86)
5596 #define CCM_CCGR86_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,86)
5597 #define CCM_CCGR86_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,86)
5598 #define CCM_CCGR86_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,86)
5599 #define CCM_CCGR87                               CCM_CCGR_REG(CCM_BASE_PTR,87)
5600 #define CCM_CCGR87_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,87)
5601 #define CCM_CCGR87_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,87)
5602 #define CCM_CCGR87_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,87)
5603 #define CCM_CCGR88                               CCM_CCGR_REG(CCM_BASE_PTR,88)
5604 #define CCM_CCGR88_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,88)
5605 #define CCM_CCGR88_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,88)
5606 #define CCM_CCGR88_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,88)
5607 #define CCM_CCGR89                               CCM_CCGR_REG(CCM_BASE_PTR,89)
5608 #define CCM_CCGR89_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,89)
5609 #define CCM_CCGR89_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,89)
5610 #define CCM_CCGR89_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,89)
5611 #define CCM_CCGR90                               CCM_CCGR_REG(CCM_BASE_PTR,90)
5612 #define CCM_CCGR90_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,90)
5613 #define CCM_CCGR90_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,90)
5614 #define CCM_CCGR90_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,90)
5615 #define CCM_CCGR91                               CCM_CCGR_REG(CCM_BASE_PTR,91)
5616 #define CCM_CCGR91_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,91)
5617 #define CCM_CCGR91_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,91)
5618 #define CCM_CCGR91_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,91)
5619 #define CCM_CCGR92                               CCM_CCGR_REG(CCM_BASE_PTR,92)
5620 #define CCM_CCGR92_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,92)
5621 #define CCM_CCGR92_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,92)
5622 #define CCM_CCGR92_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,92)
5623 #define CCM_CCGR93                               CCM_CCGR_REG(CCM_BASE_PTR,93)
5624 #define CCM_CCGR93_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,93)
5625 #define CCM_CCGR93_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,93)
5626 #define CCM_CCGR93_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,93)
5627 #define CCM_CCGR94                               CCM_CCGR_REG(CCM_BASE_PTR,94)
5628 #define CCM_CCGR94_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,94)
5629 #define CCM_CCGR94_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,94)
5630 #define CCM_CCGR94_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,94)
5631 #define CCM_CCGR95                               CCM_CCGR_REG(CCM_BASE_PTR,95)
5632 #define CCM_CCGR95_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,95)
5633 #define CCM_CCGR95_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,95)
5634 #define CCM_CCGR95_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,95)
5635 #define CCM_CCGR96                               CCM_CCGR_REG(CCM_BASE_PTR,96)
5636 #define CCM_CCGR96_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,96)
5637 #define CCM_CCGR96_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,96)
5638 #define CCM_CCGR96_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,96)
5639 #define CCM_CCGR97                               CCM_CCGR_REG(CCM_BASE_PTR,97)
5640 #define CCM_CCGR97_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,97)
5641 #define CCM_CCGR97_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,97)
5642 #define CCM_CCGR97_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,97)
5643 #define CCM_CCGR98                               CCM_CCGR_REG(CCM_BASE_PTR,98)
5644 #define CCM_CCGR98_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,98)
5645 #define CCM_CCGR98_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,98)
5646 #define CCM_CCGR98_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,98)
5647 #define CCM_CCGR99                               CCM_CCGR_REG(CCM_BASE_PTR,99)
5648 #define CCM_CCGR99_SET                           CCM_CCGR_SET_REG(CCM_BASE_PTR,99)
5649 #define CCM_CCGR99_CLR                           CCM_CCGR_CLR_REG(CCM_BASE_PTR,99)
5650 #define CCM_CCGR99_TOG                           CCM_CCGR_TOG_REG(CCM_BASE_PTR,99)
5651 #define CCM_CCGR100                              CCM_CCGR_REG(CCM_BASE_PTR,100)
5652 #define CCM_CCGR100_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,100)
5653 #define CCM_CCGR100_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,100)
5654 #define CCM_CCGR100_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,100)
5655 #define CCM_CCGR101                              CCM_CCGR_REG(CCM_BASE_PTR,101)
5656 #define CCM_CCGR101_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,101)
5657 #define CCM_CCGR101_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,101)
5658 #define CCM_CCGR101_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,101)
5659 #define CCM_CCGR102                              CCM_CCGR_REG(CCM_BASE_PTR,102)
5660 #define CCM_CCGR102_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,102)
5661 #define CCM_CCGR102_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,102)
5662 #define CCM_CCGR102_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,102)
5663 #define CCM_CCGR103                              CCM_CCGR_REG(CCM_BASE_PTR,103)
5664 #define CCM_CCGR103_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,103)
5665 #define CCM_CCGR103_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,103)
5666 #define CCM_CCGR103_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,103)
5667 #define CCM_CCGR104                              CCM_CCGR_REG(CCM_BASE_PTR,104)
5668 #define CCM_CCGR104_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,104)
5669 #define CCM_CCGR104_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,104)
5670 #define CCM_CCGR104_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,104)
5671 #define CCM_CCGR105                              CCM_CCGR_REG(CCM_BASE_PTR,105)
5672 #define CCM_CCGR105_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,105)
5673 #define CCM_CCGR105_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,105)
5674 #define CCM_CCGR105_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,105)
5675 #define CCM_CCGR106                              CCM_CCGR_REG(CCM_BASE_PTR,106)
5676 #define CCM_CCGR106_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,106)
5677 #define CCM_CCGR106_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,106)
5678 #define CCM_CCGR106_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,106)
5679 #define CCM_CCGR107                              CCM_CCGR_REG(CCM_BASE_PTR,107)
5680 #define CCM_CCGR107_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,107)
5681 #define CCM_CCGR107_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,107)
5682 #define CCM_CCGR107_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,107)
5683 #define CCM_CCGR108                              CCM_CCGR_REG(CCM_BASE_PTR,108)
5684 #define CCM_CCGR108_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,108)
5685 #define CCM_CCGR108_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,108)
5686 #define CCM_CCGR108_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,108)
5687 #define CCM_CCGR109                              CCM_CCGR_REG(CCM_BASE_PTR,109)
5688 #define CCM_CCGR109_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,109)
5689 #define CCM_CCGR109_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,109)
5690 #define CCM_CCGR109_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,109)
5691 #define CCM_CCGR110                              CCM_CCGR_REG(CCM_BASE_PTR,110)
5692 #define CCM_CCGR110_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,110)
5693 #define CCM_CCGR110_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,110)
5694 #define CCM_CCGR110_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,110)
5695 #define CCM_CCGR111                              CCM_CCGR_REG(CCM_BASE_PTR,111)
5696 #define CCM_CCGR111_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,111)
5697 #define CCM_CCGR111_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,111)
5698 #define CCM_CCGR111_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,111)
5699 #define CCM_CCGR112                              CCM_CCGR_REG(CCM_BASE_PTR,112)
5700 #define CCM_CCGR112_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,112)
5701 #define CCM_CCGR112_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,112)
5702 #define CCM_CCGR112_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,112)
5703 #define CCM_CCGR113                              CCM_CCGR_REG(CCM_BASE_PTR,113)
5704 #define CCM_CCGR113_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,113)
5705 #define CCM_CCGR113_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,113)
5706 #define CCM_CCGR113_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,113)
5707 #define CCM_CCGR114                              CCM_CCGR_REG(CCM_BASE_PTR,114)
5708 #define CCM_CCGR114_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,114)
5709 #define CCM_CCGR114_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,114)
5710 #define CCM_CCGR114_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,114)
5711 #define CCM_CCGR115                              CCM_CCGR_REG(CCM_BASE_PTR,115)
5712 #define CCM_CCGR115_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,115)
5713 #define CCM_CCGR115_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,115)
5714 #define CCM_CCGR115_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,115)
5715 #define CCM_CCGR116                              CCM_CCGR_REG(CCM_BASE_PTR,116)
5716 #define CCM_CCGR116_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,116)
5717 #define CCM_CCGR116_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,116)
5718 #define CCM_CCGR116_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,116)
5719 #define CCM_CCGR117                              CCM_CCGR_REG(CCM_BASE_PTR,117)
5720 #define CCM_CCGR117_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,117)
5721 #define CCM_CCGR117_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,117)
5722 #define CCM_CCGR117_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,117)
5723 #define CCM_CCGR118                              CCM_CCGR_REG(CCM_BASE_PTR,118)
5724 #define CCM_CCGR118_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,118)
5725 #define CCM_CCGR118_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,118)
5726 #define CCM_CCGR118_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,118)
5727 #define CCM_CCGR119                              CCM_CCGR_REG(CCM_BASE_PTR,119)
5728 #define CCM_CCGR119_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,119)
5729 #define CCM_CCGR119_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,119)
5730 #define CCM_CCGR119_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,119)
5731 #define CCM_CCGR120                              CCM_CCGR_REG(CCM_BASE_PTR,120)
5732 #define CCM_CCGR120_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,120)
5733 #define CCM_CCGR120_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,120)
5734 #define CCM_CCGR120_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,120)
5735 #define CCM_CCGR121                              CCM_CCGR_REG(CCM_BASE_PTR,121)
5736 #define CCM_CCGR121_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,121)
5737 #define CCM_CCGR121_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,121)
5738 #define CCM_CCGR121_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,121)
5739 #define CCM_CCGR122                              CCM_CCGR_REG(CCM_BASE_PTR,122)
5740 #define CCM_CCGR122_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,122)
5741 #define CCM_CCGR122_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,122)
5742 #define CCM_CCGR122_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,122)
5743 #define CCM_CCGR123                              CCM_CCGR_REG(CCM_BASE_PTR,123)
5744 #define CCM_CCGR123_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,123)
5745 #define CCM_CCGR123_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,123)
5746 #define CCM_CCGR123_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,123)
5747 #define CCM_CCGR124                              CCM_CCGR_REG(CCM_BASE_PTR,124)
5748 #define CCM_CCGR124_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,124)
5749 #define CCM_CCGR124_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,124)
5750 #define CCM_CCGR124_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,124)
5751 #define CCM_CCGR125                              CCM_CCGR_REG(CCM_BASE_PTR,125)
5752 #define CCM_CCGR125_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,125)
5753 #define CCM_CCGR125_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,125)
5754 #define CCM_CCGR125_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,125)
5755 #define CCM_CCGR126                              CCM_CCGR_REG(CCM_BASE_PTR,126)
5756 #define CCM_CCGR126_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,126)
5757 #define CCM_CCGR126_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,126)
5758 #define CCM_CCGR126_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,126)
5759 #define CCM_CCGR127                              CCM_CCGR_REG(CCM_BASE_PTR,127)
5760 #define CCM_CCGR127_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,127)
5761 #define CCM_CCGR127_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,127)
5762 #define CCM_CCGR127_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,127)
5763 #define CCM_CCGR128                              CCM_CCGR_REG(CCM_BASE_PTR,128)
5764 #define CCM_CCGR128_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,128)
5765 #define CCM_CCGR128_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,128)
5766 #define CCM_CCGR128_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,128)
5767 #define CCM_CCGR129                              CCM_CCGR_REG(CCM_BASE_PTR,129)
5768 #define CCM_CCGR129_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,129)
5769 #define CCM_CCGR129_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,129)
5770 #define CCM_CCGR129_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,129)
5771 #define CCM_CCGR130                              CCM_CCGR_REG(CCM_BASE_PTR,130)
5772 #define CCM_CCGR130_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,130)
5773 #define CCM_CCGR130_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,130)
5774 #define CCM_CCGR130_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,130)
5775 #define CCM_CCGR131                              CCM_CCGR_REG(CCM_BASE_PTR,131)
5776 #define CCM_CCGR131_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,131)
5777 #define CCM_CCGR131_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,131)
5778 #define CCM_CCGR131_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,131)
5779 #define CCM_CCGR132                              CCM_CCGR_REG(CCM_BASE_PTR,132)
5780 #define CCM_CCGR132_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,132)
5781 #define CCM_CCGR132_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,132)
5782 #define CCM_CCGR132_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,132)
5783 #define CCM_CCGR133                              CCM_CCGR_REG(CCM_BASE_PTR,133)
5784 #define CCM_CCGR133_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,133)
5785 #define CCM_CCGR133_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,133)
5786 #define CCM_CCGR133_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,133)
5787 #define CCM_CCGR134                              CCM_CCGR_REG(CCM_BASE_PTR,134)
5788 #define CCM_CCGR134_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,134)
5789 #define CCM_CCGR134_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,134)
5790 #define CCM_CCGR134_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,134)
5791 #define CCM_CCGR135                              CCM_CCGR_REG(CCM_BASE_PTR,135)
5792 #define CCM_CCGR135_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,135)
5793 #define CCM_CCGR135_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,135)
5794 #define CCM_CCGR135_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,135)
5795 #define CCM_CCGR136                              CCM_CCGR_REG(CCM_BASE_PTR,136)
5796 #define CCM_CCGR136_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,136)
5797 #define CCM_CCGR136_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,136)
5798 #define CCM_CCGR136_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,136)
5799 #define CCM_CCGR137                              CCM_CCGR_REG(CCM_BASE_PTR,137)
5800 #define CCM_CCGR137_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,137)
5801 #define CCM_CCGR137_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,137)
5802 #define CCM_CCGR137_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,137)
5803 #define CCM_CCGR138                              CCM_CCGR_REG(CCM_BASE_PTR,138)
5804 #define CCM_CCGR138_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,138)
5805 #define CCM_CCGR138_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,138)
5806 #define CCM_CCGR138_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,138)
5807 #define CCM_CCGR139                              CCM_CCGR_REG(CCM_BASE_PTR,139)
5808 #define CCM_CCGR139_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,139)
5809 #define CCM_CCGR139_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,139)
5810 #define CCM_CCGR139_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,139)
5811 #define CCM_CCGR140                              CCM_CCGR_REG(CCM_BASE_PTR,140)
5812 #define CCM_CCGR140_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,140)
5813 #define CCM_CCGR140_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,140)
5814 #define CCM_CCGR140_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,140)
5815 #define CCM_CCGR141                              CCM_CCGR_REG(CCM_BASE_PTR,141)
5816 #define CCM_CCGR141_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,141)
5817 #define CCM_CCGR141_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,141)
5818 #define CCM_CCGR141_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,141)
5819 #define CCM_CCGR142                              CCM_CCGR_REG(CCM_BASE_PTR,142)
5820 #define CCM_CCGR142_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,142)
5821 #define CCM_CCGR142_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,142)
5822 #define CCM_CCGR142_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,142)
5823 #define CCM_CCGR143                              CCM_CCGR_REG(CCM_BASE_PTR,143)
5824 #define CCM_CCGR143_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,143)
5825 #define CCM_CCGR143_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,143)
5826 #define CCM_CCGR143_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,143)
5827 #define CCM_CCGR144                              CCM_CCGR_REG(CCM_BASE_PTR,144)
5828 #define CCM_CCGR144_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,144)
5829 #define CCM_CCGR144_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,144)
5830 #define CCM_CCGR144_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,144)
5831 #define CCM_CCGR145                              CCM_CCGR_REG(CCM_BASE_PTR,145)
5832 #define CCM_CCGR145_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,145)
5833 #define CCM_CCGR145_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,145)
5834 #define CCM_CCGR145_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,145)
5835 #define CCM_CCGR146                              CCM_CCGR_REG(CCM_BASE_PTR,146)
5836 #define CCM_CCGR146_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,146)
5837 #define CCM_CCGR146_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,146)
5838 #define CCM_CCGR146_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,146)
5839 #define CCM_CCGR147                              CCM_CCGR_REG(CCM_BASE_PTR,147)
5840 #define CCM_CCGR147_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,147)
5841 #define CCM_CCGR147_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,147)
5842 #define CCM_CCGR147_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,147)
5843 #define CCM_CCGR148                              CCM_CCGR_REG(CCM_BASE_PTR,148)
5844 #define CCM_CCGR148_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,148)
5845 #define CCM_CCGR148_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,148)
5846 #define CCM_CCGR148_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,148)
5847 #define CCM_CCGR149                              CCM_CCGR_REG(CCM_BASE_PTR,149)
5848 #define CCM_CCGR149_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,149)
5849 #define CCM_CCGR149_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,149)
5850 #define CCM_CCGR149_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,149)
5851 #define CCM_CCGR150                              CCM_CCGR_REG(CCM_BASE_PTR,150)
5852 #define CCM_CCGR150_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,150)
5853 #define CCM_CCGR150_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,150)
5854 #define CCM_CCGR150_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,150)
5855 #define CCM_CCGR151                              CCM_CCGR_REG(CCM_BASE_PTR,151)
5856 #define CCM_CCGR151_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,151)
5857 #define CCM_CCGR151_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,151)
5858 #define CCM_CCGR151_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,151)
5859 #define CCM_CCGR152                              CCM_CCGR_REG(CCM_BASE_PTR,152)
5860 #define CCM_CCGR152_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,152)
5861 #define CCM_CCGR152_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,152)
5862 #define CCM_CCGR152_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,152)
5863 #define CCM_CCGR153                              CCM_CCGR_REG(CCM_BASE_PTR,153)
5864 #define CCM_CCGR153_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,153)
5865 #define CCM_CCGR153_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,153)
5866 #define CCM_CCGR153_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,153)
5867 #define CCM_CCGR154                              CCM_CCGR_REG(CCM_BASE_PTR,154)
5868 #define CCM_CCGR154_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,154)
5869 #define CCM_CCGR154_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,154)
5870 #define CCM_CCGR154_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,154)
5871 #define CCM_CCGR155                              CCM_CCGR_REG(CCM_BASE_PTR,155)
5872 #define CCM_CCGR155_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,155)
5873 #define CCM_CCGR155_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,155)
5874 #define CCM_CCGR155_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,155)
5875 #define CCM_CCGR156                              CCM_CCGR_REG(CCM_BASE_PTR,156)
5876 #define CCM_CCGR156_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,156)
5877 #define CCM_CCGR156_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,156)
5878 #define CCM_CCGR156_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,156)
5879 #define CCM_CCGR157                              CCM_CCGR_REG(CCM_BASE_PTR,157)
5880 #define CCM_CCGR157_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,157)
5881 #define CCM_CCGR157_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,157)
5882 #define CCM_CCGR157_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,157)
5883 #define CCM_CCGR158                              CCM_CCGR_REG(CCM_BASE_PTR,158)
5884 #define CCM_CCGR158_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,158)
5885 #define CCM_CCGR158_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,158)
5886 #define CCM_CCGR158_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,158)
5887 #define CCM_CCGR159                              CCM_CCGR_REG(CCM_BASE_PTR,159)
5888 #define CCM_CCGR159_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,159)
5889 #define CCM_CCGR159_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,159)
5890 #define CCM_CCGR159_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,159)
5891 #define CCM_CCGR160                              CCM_CCGR_REG(CCM_BASE_PTR,160)
5892 #define CCM_CCGR160_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,160)
5893 #define CCM_CCGR160_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,160)
5894 #define CCM_CCGR160_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,160)
5895 #define CCM_CCGR161                              CCM_CCGR_REG(CCM_BASE_PTR,161)
5896 #define CCM_CCGR161_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,161)
5897 #define CCM_CCGR161_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,161)
5898 #define CCM_CCGR161_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,161)
5899 #define CCM_CCGR162                              CCM_CCGR_REG(CCM_BASE_PTR,162)
5900 #define CCM_CCGR162_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,162)
5901 #define CCM_CCGR162_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,162)
5902 #define CCM_CCGR162_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,162)
5903 #define CCM_CCGR163                              CCM_CCGR_REG(CCM_BASE_PTR,163)
5904 #define CCM_CCGR163_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,163)
5905 #define CCM_CCGR163_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,163)
5906 #define CCM_CCGR163_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,163)
5907 #define CCM_CCGR164                              CCM_CCGR_REG(CCM_BASE_PTR,164)
5908 #define CCM_CCGR164_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,164)
5909 #define CCM_CCGR164_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,164)
5910 #define CCM_CCGR164_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,164)
5911 #define CCM_CCGR165                              CCM_CCGR_REG(CCM_BASE_PTR,165)
5912 #define CCM_CCGR165_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,165)
5913 #define CCM_CCGR165_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,165)
5914 #define CCM_CCGR165_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,165)
5915 #define CCM_CCGR166                              CCM_CCGR_REG(CCM_BASE_PTR,166)
5916 #define CCM_CCGR166_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,166)
5917 #define CCM_CCGR166_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,166)
5918 #define CCM_CCGR166_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,166)
5919 #define CCM_CCGR167                              CCM_CCGR_REG(CCM_BASE_PTR,167)
5920 #define CCM_CCGR167_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,167)
5921 #define CCM_CCGR167_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,167)
5922 #define CCM_CCGR167_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,167)
5923 #define CCM_CCGR168                              CCM_CCGR_REG(CCM_BASE_PTR,168)
5924 #define CCM_CCGR168_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,168)
5925 #define CCM_CCGR168_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,168)
5926 #define CCM_CCGR168_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,168)
5927 #define CCM_CCGR169                              CCM_CCGR_REG(CCM_BASE_PTR,169)
5928 #define CCM_CCGR169_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,169)
5929 #define CCM_CCGR169_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,169)
5930 #define CCM_CCGR169_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,169)
5931 #define CCM_CCGR170                              CCM_CCGR_REG(CCM_BASE_PTR,170)
5932 #define CCM_CCGR170_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,170)
5933 #define CCM_CCGR170_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,170)
5934 #define CCM_CCGR170_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,170)
5935 #define CCM_CCGR171                              CCM_CCGR_REG(CCM_BASE_PTR,171)
5936 #define CCM_CCGR171_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,171)
5937 #define CCM_CCGR171_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,171)
5938 #define CCM_CCGR171_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,171)
5939 #define CCM_CCGR172                              CCM_CCGR_REG(CCM_BASE_PTR,172)
5940 #define CCM_CCGR172_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,172)
5941 #define CCM_CCGR172_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,172)
5942 #define CCM_CCGR172_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,172)
5943 #define CCM_CCGR173                              CCM_CCGR_REG(CCM_BASE_PTR,173)
5944 #define CCM_CCGR173_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,173)
5945 #define CCM_CCGR173_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,173)
5946 #define CCM_CCGR173_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,173)
5947 #define CCM_CCGR174                              CCM_CCGR_REG(CCM_BASE_PTR,174)
5948 #define CCM_CCGR174_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,174)
5949 #define CCM_CCGR174_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,174)
5950 #define CCM_CCGR174_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,174)
5951 #define CCM_CCGR175                              CCM_CCGR_REG(CCM_BASE_PTR,175)
5952 #define CCM_CCGR175_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,175)
5953 #define CCM_CCGR175_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,175)
5954 #define CCM_CCGR175_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,175)
5955 #define CCM_CCGR176                              CCM_CCGR_REG(CCM_BASE_PTR,176)
5956 #define CCM_CCGR176_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,176)
5957 #define CCM_CCGR176_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,176)
5958 #define CCM_CCGR176_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,176)
5959 #define CCM_CCGR177                              CCM_CCGR_REG(CCM_BASE_PTR,177)
5960 #define CCM_CCGR177_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,177)
5961 #define CCM_CCGR177_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,177)
5962 #define CCM_CCGR177_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,177)
5963 #define CCM_CCGR178                              CCM_CCGR_REG(CCM_BASE_PTR,178)
5964 #define CCM_CCGR178_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,178)
5965 #define CCM_CCGR178_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,178)
5966 #define CCM_CCGR178_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,178)
5967 #define CCM_CCGR179                              CCM_CCGR_REG(CCM_BASE_PTR,179)
5968 #define CCM_CCGR179_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,179)
5969 #define CCM_CCGR179_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,179)
5970 #define CCM_CCGR179_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,179)
5971 #define CCM_CCGR180                              CCM_CCGR_REG(CCM_BASE_PTR,180)
5972 #define CCM_CCGR180_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,180)
5973 #define CCM_CCGR180_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,180)
5974 #define CCM_CCGR180_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,180)
5975 #define CCM_CCGR181                              CCM_CCGR_REG(CCM_BASE_PTR,181)
5976 #define CCM_CCGR181_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,181)
5977 #define CCM_CCGR181_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,181)
5978 #define CCM_CCGR181_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,181)
5979 #define CCM_CCGR182                              CCM_CCGR_REG(CCM_BASE_PTR,182)
5980 #define CCM_CCGR182_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,182)
5981 #define CCM_CCGR182_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,182)
5982 #define CCM_CCGR182_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,182)
5983 #define CCM_CCGR183                              CCM_CCGR_REG(CCM_BASE_PTR,183)
5984 #define CCM_CCGR183_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,183)
5985 #define CCM_CCGR183_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,183)
5986 #define CCM_CCGR183_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,183)
5987 #define CCM_CCGR184                              CCM_CCGR_REG(CCM_BASE_PTR,184)
5988 #define CCM_CCGR184_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,184)
5989 #define CCM_CCGR184_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,184)
5990 #define CCM_CCGR184_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,184)
5991 #define CCM_CCGR185                              CCM_CCGR_REG(CCM_BASE_PTR,185)
5992 #define CCM_CCGR185_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,185)
5993 #define CCM_CCGR185_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,185)
5994 #define CCM_CCGR185_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,185)
5995 #define CCM_CCGR186                              CCM_CCGR_REG(CCM_BASE_PTR,186)
5996 #define CCM_CCGR186_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,186)
5997 #define CCM_CCGR186_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,186)
5998 #define CCM_CCGR186_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,186)
5999 #define CCM_CCGR187                              CCM_CCGR_REG(CCM_BASE_PTR,187)
6000 #define CCM_CCGR187_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,187)
6001 #define CCM_CCGR187_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,187)
6002 #define CCM_CCGR187_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,187)
6003 #define CCM_CCGR188                              CCM_CCGR_REG(CCM_BASE_PTR,188)
6004 #define CCM_CCGR188_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,188)
6005 #define CCM_CCGR188_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,188)
6006 #define CCM_CCGR188_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,188)
6007 #define CCM_CCGR189                              CCM_CCGR_REG(CCM_BASE_PTR,189)
6008 #define CCM_CCGR189_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,189)
6009 #define CCM_CCGR189_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,189)
6010 #define CCM_CCGR189_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,189)
6011 #define CCM_CCGR190                              CCM_CCGR_REG(CCM_BASE_PTR,190)
6012 #define CCM_CCGR190_SET                          CCM_CCGR_SET_REG(CCM_BASE_PTR,190)
6013 #define CCM_CCGR190_CLR                          CCM_CCGR_CLR_REG(CCM_BASE_PTR,190)
6014 #define CCM_CCGR190_TOG                          CCM_CCGR_TOG_REG(CCM_BASE_PTR,190)
6015 #define CCM_TARGET_ROOT0                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,0)
6016 #define CCM_TARGET_ROOT0_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,0)
6017 #define CCM_TARGET_ROOT0_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,0)
6018 #define CCM_TARGET_ROOT0_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,0)
6019 #define CCM_MISC0                                CCM_MISC_REG(CCM_BASE_PTR,0)
6020 #define CCM_MISC_ROOT0_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,0)
6021 #define CCM_MISC_ROOT0_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,0)
6022 #define CCM_MISC_ROOT0_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,0)
6023 #define CCM_POST0                                CCM_POST_REG(CCM_BASE_PTR,0)
6024 #define CCM_POST_ROOT0_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,0)
6025 #define CCM_POST_ROOT0_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,0)
6026 #define CCM_POST_ROOT0_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,0)
6027 #define CCM_PRE0                                 CCM_PRE_REG(CCM_BASE_PTR,0)
6028 #define CCM_PRE_ROOT0_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,0)
6029 #define CCM_PRE_ROOT0_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,0)
6030 #define CCM_PRE_ROOT0_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,0)
6031 #define CCM_ACCESS_CTRL0                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,0)
6032 #define CCM_ACCESS_CTRL_ROOT0_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,0)
6033 #define CCM_ACCESS_CTRL_ROOT0_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,0)
6034 #define CCM_ACCESS_CTRL_ROOT0_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,0)
6035 #define CCM_TARGET_ROOT1                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,1)
6036 #define CCM_TARGET_ROOT1_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,1)
6037 #define CCM_TARGET_ROOT1_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,1)
6038 #define CCM_TARGET_ROOT1_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,1)
6039 #define CCM_MISC1                                CCM_MISC_REG(CCM_BASE_PTR,1)
6040 #define CCM_MISC_ROOT1_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,1)
6041 #define CCM_MISC_ROOT1_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,1)
6042 #define CCM_MISC_ROOT1_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,1)
6043 #define CCM_POST1                                CCM_POST_REG(CCM_BASE_PTR,1)
6044 #define CCM_POST_ROOT1_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,1)
6045 #define CCM_POST_ROOT1_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,1)
6046 #define CCM_POST_ROOT1_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,1)
6047 #define CCM_PRE1                                 CCM_PRE_REG(CCM_BASE_PTR,1)
6048 #define CCM_PRE_ROOT1_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,1)
6049 #define CCM_PRE_ROOT1_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,1)
6050 #define CCM_PRE_ROOT1_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,1)
6051 #define CCM_ACCESS_CTRL1                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,1)
6052 #define CCM_ACCESS_CTRL_ROOT1_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,1)
6053 #define CCM_ACCESS_CTRL_ROOT1_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,1)
6054 #define CCM_ACCESS_CTRL_ROOT1_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,1)
6055 #define CCM_TARGET_ROOT2                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,2)
6056 #define CCM_TARGET_ROOT2_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,2)
6057 #define CCM_TARGET_ROOT2_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,2)
6058 #define CCM_TARGET_ROOT2_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,2)
6059 #define CCM_MISC2                                CCM_MISC_REG(CCM_BASE_PTR,2)
6060 #define CCM_MISC_ROOT2_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,2)
6061 #define CCM_MISC_ROOT2_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,2)
6062 #define CCM_MISC_ROOT2_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,2)
6063 #define CCM_POST2                                CCM_POST_REG(CCM_BASE_PTR,2)
6064 #define CCM_POST_ROOT2_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,2)
6065 #define CCM_POST_ROOT2_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,2)
6066 #define CCM_POST_ROOT2_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,2)
6067 #define CCM_PRE2                                 CCM_PRE_REG(CCM_BASE_PTR,2)
6068 #define CCM_PRE_ROOT2_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,2)
6069 #define CCM_PRE_ROOT2_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,2)
6070 #define CCM_PRE_ROOT2_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,2)
6071 #define CCM_ACCESS_CTRL2                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,2)
6072 #define CCM_ACCESS_CTRL_ROOT2_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,2)
6073 #define CCM_ACCESS_CTRL_ROOT2_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,2)
6074 #define CCM_ACCESS_CTRL_ROOT2_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,2)
6075 #define CCM_TARGET_ROOT3                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,3)
6076 #define CCM_TARGET_ROOT3_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,3)
6077 #define CCM_TARGET_ROOT3_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,3)
6078 #define CCM_TARGET_ROOT3_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,3)
6079 #define CCM_MISC3                                CCM_MISC_REG(CCM_BASE_PTR,3)
6080 #define CCM_MISC_ROOT3_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,3)
6081 #define CCM_MISC_ROOT3_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,3)
6082 #define CCM_MISC_ROOT3_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,3)
6083 #define CCM_POST3                                CCM_POST_REG(CCM_BASE_PTR,3)
6084 #define CCM_POST_ROOT3_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,3)
6085 #define CCM_POST_ROOT3_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,3)
6086 #define CCM_POST_ROOT3_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,3)
6087 #define CCM_PRE3                                 CCM_PRE_REG(CCM_BASE_PTR,3)
6088 #define CCM_PRE_ROOT3_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,3)
6089 #define CCM_PRE_ROOT3_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,3)
6090 #define CCM_PRE_ROOT3_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,3)
6091 #define CCM_ACCESS_CTRL3                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,3)
6092 #define CCM_ACCESS_CTRL_ROOT3_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,3)
6093 #define CCM_ACCESS_CTRL_ROOT3_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,3)
6094 #define CCM_ACCESS_CTRL_ROOT3_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,3)
6095 #define CCM_TARGET_ROOT4                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,4)
6096 #define CCM_TARGET_ROOT4_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,4)
6097 #define CCM_TARGET_ROOT4_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,4)
6098 #define CCM_TARGET_ROOT4_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,4)
6099 #define CCM_MISC4                                CCM_MISC_REG(CCM_BASE_PTR,4)
6100 #define CCM_MISC_ROOT4_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,4)
6101 #define CCM_MISC_ROOT4_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,4)
6102 #define CCM_MISC_ROOT4_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,4)
6103 #define CCM_POST4                                CCM_POST_REG(CCM_BASE_PTR,4)
6104 #define CCM_POST_ROOT4_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,4)
6105 #define CCM_POST_ROOT4_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,4)
6106 #define CCM_POST_ROOT4_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,4)
6107 #define CCM_PRE4                                 CCM_PRE_REG(CCM_BASE_PTR,4)
6108 #define CCM_PRE_ROOT4_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,4)
6109 #define CCM_PRE_ROOT4_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,4)
6110 #define CCM_PRE_ROOT4_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,4)
6111 #define CCM_ACCESS_CTRL4                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,4)
6112 #define CCM_ACCESS_CTRL_ROOT4_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,4)
6113 #define CCM_ACCESS_CTRL_ROOT4_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,4)
6114 #define CCM_ACCESS_CTRL_ROOT4_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,4)
6115 #define CCM_TARGET_ROOT5                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,5)
6116 #define CCM_TARGET_ROOT5_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,5)
6117 #define CCM_TARGET_ROOT5_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,5)
6118 #define CCM_TARGET_ROOT5_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,5)
6119 #define CCM_MISC5                                CCM_MISC_REG(CCM_BASE_PTR,5)
6120 #define CCM_MISC_ROOT5_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,5)
6121 #define CCM_MISC_ROOT5_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,5)
6122 #define CCM_MISC_ROOT5_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,5)
6123 #define CCM_POST5                                CCM_POST_REG(CCM_BASE_PTR,5)
6124 #define CCM_POST_ROOT5_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,5)
6125 #define CCM_POST_ROOT5_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,5)
6126 #define CCM_POST_ROOT5_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,5)
6127 #define CCM_PRE5                                 CCM_PRE_REG(CCM_BASE_PTR,5)
6128 #define CCM_PRE_ROOT5_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,5)
6129 #define CCM_PRE_ROOT5_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,5)
6130 #define CCM_PRE_ROOT5_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,5)
6131 #define CCM_ACCESS_CTRL5                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,5)
6132 #define CCM_ACCESS_CTRL_ROOT5_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,5)
6133 #define CCM_ACCESS_CTRL_ROOT5_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,5)
6134 #define CCM_ACCESS_CTRL_ROOT5_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,5)
6135 #define CCM_TARGET_ROOT6                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,6)
6136 #define CCM_TARGET_ROOT6_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,6)
6137 #define CCM_TARGET_ROOT6_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,6)
6138 #define CCM_TARGET_ROOT6_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,6)
6139 #define CCM_MISC6                                CCM_MISC_REG(CCM_BASE_PTR,6)
6140 #define CCM_MISC_ROOT6_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,6)
6141 #define CCM_MISC_ROOT6_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,6)
6142 #define CCM_MISC_ROOT6_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,6)
6143 #define CCM_POST6                                CCM_POST_REG(CCM_BASE_PTR,6)
6144 #define CCM_POST_ROOT6_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,6)
6145 #define CCM_POST_ROOT6_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,6)
6146 #define CCM_POST_ROOT6_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,6)
6147 #define CCM_PRE6                                 CCM_PRE_REG(CCM_BASE_PTR,6)
6148 #define CCM_PRE_ROOT6_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,6)
6149 #define CCM_PRE_ROOT6_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,6)
6150 #define CCM_PRE_ROOT6_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,6)
6151 #define CCM_ACCESS_CTRL6                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,6)
6152 #define CCM_ACCESS_CTRL_ROOT6_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,6)
6153 #define CCM_ACCESS_CTRL_ROOT6_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,6)
6154 #define CCM_ACCESS_CTRL_ROOT6_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,6)
6155 #define CCM_TARGET_ROOT7                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,7)
6156 #define CCM_TARGET_ROOT7_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,7)
6157 #define CCM_TARGET_ROOT7_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,7)
6158 #define CCM_TARGET_ROOT7_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,7)
6159 #define CCM_MISC7                                CCM_MISC_REG(CCM_BASE_PTR,7)
6160 #define CCM_MISC_ROOT7_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,7)
6161 #define CCM_MISC_ROOT7_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,7)
6162 #define CCM_MISC_ROOT7_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,7)
6163 #define CCM_POST7                                CCM_POST_REG(CCM_BASE_PTR,7)
6164 #define CCM_POST_ROOT7_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,7)
6165 #define CCM_POST_ROOT7_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,7)
6166 #define CCM_POST_ROOT7_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,7)
6167 #define CCM_PRE7                                 CCM_PRE_REG(CCM_BASE_PTR,7)
6168 #define CCM_PRE_ROOT7_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,7)
6169 #define CCM_PRE_ROOT7_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,7)
6170 #define CCM_PRE_ROOT7_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,7)
6171 #define CCM_ACCESS_CTRL7                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,7)
6172 #define CCM_ACCESS_CTRL_ROOT7_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,7)
6173 #define CCM_ACCESS_CTRL_ROOT7_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,7)
6174 #define CCM_ACCESS_CTRL_ROOT7_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,7)
6175 #define CCM_TARGET_ROOT8                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,8)
6176 #define CCM_TARGET_ROOT8_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,8)
6177 #define CCM_TARGET_ROOT8_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,8)
6178 #define CCM_TARGET_ROOT8_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,8)
6179 #define CCM_MISC8                                CCM_MISC_REG(CCM_BASE_PTR,8)
6180 #define CCM_MISC_ROOT8_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,8)
6181 #define CCM_MISC_ROOT8_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,8)
6182 #define CCM_MISC_ROOT8_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,8)
6183 #define CCM_POST8                                CCM_POST_REG(CCM_BASE_PTR,8)
6184 #define CCM_POST_ROOT8_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,8)
6185 #define CCM_POST_ROOT8_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,8)
6186 #define CCM_POST_ROOT8_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,8)
6187 #define CCM_PRE8                                 CCM_PRE_REG(CCM_BASE_PTR,8)
6188 #define CCM_PRE_ROOT8_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,8)
6189 #define CCM_PRE_ROOT8_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,8)
6190 #define CCM_PRE_ROOT8_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,8)
6191 #define CCM_ACCESS_CTRL8                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,8)
6192 #define CCM_ACCESS_CTRL_ROOT8_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,8)
6193 #define CCM_ACCESS_CTRL_ROOT8_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,8)
6194 #define CCM_ACCESS_CTRL_ROOT8_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,8)
6195 #define CCM_TARGET_ROOT9                         CCM_TARGET_ROOT_REG(CCM_BASE_PTR,9)
6196 #define CCM_TARGET_ROOT9_SET                     CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,9)
6197 #define CCM_TARGET_ROOT9_CLR                     CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,9)
6198 #define CCM_TARGET_ROOT9_TOG                     CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,9)
6199 #define CCM_MISC9                                CCM_MISC_REG(CCM_BASE_PTR,9)
6200 #define CCM_MISC_ROOT9_SET                       CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,9)
6201 #define CCM_MISC_ROOT9_CLR                       CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,9)
6202 #define CCM_MISC_ROOT9_TOG                       CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,9)
6203 #define CCM_POST9                                CCM_POST_REG(CCM_BASE_PTR,9)
6204 #define CCM_POST_ROOT9_SET                       CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,9)
6205 #define CCM_POST_ROOT9_CLR                       CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,9)
6206 #define CCM_POST_ROOT9_TOG                       CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,9)
6207 #define CCM_PRE9                                 CCM_PRE_REG(CCM_BASE_PTR,9)
6208 #define CCM_PRE_ROOT9_SET                        CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,9)
6209 #define CCM_PRE_ROOT9_CLR                        CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,9)
6210 #define CCM_PRE_ROOT9_TOG                        CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,9)
6211 #define CCM_ACCESS_CTRL9                         CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,9)
6212 #define CCM_ACCESS_CTRL_ROOT9_SET                CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,9)
6213 #define CCM_ACCESS_CTRL_ROOT9_CLR                CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,9)
6214 #define CCM_ACCESS_CTRL_ROOT9_TOG                CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,9)
6215 #define CCM_TARGET_ROOT10                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,10)
6216 #define CCM_TARGET_ROOT10_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,10)
6217 #define CCM_TARGET_ROOT10_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,10)
6218 #define CCM_TARGET_ROOT10_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,10)
6219 #define CCM_MISC10                               CCM_MISC_REG(CCM_BASE_PTR,10)
6220 #define CCM_MISC_ROOT10_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,10)
6221 #define CCM_MISC_ROOT10_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,10)
6222 #define CCM_MISC_ROOT10_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,10)
6223 #define CCM_POST10                               CCM_POST_REG(CCM_BASE_PTR,10)
6224 #define CCM_POST_ROOT10_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,10)
6225 #define CCM_POST_ROOT10_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,10)
6226 #define CCM_POST_ROOT10_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,10)
6227 #define CCM_PRE10                                CCM_PRE_REG(CCM_BASE_PTR,10)
6228 #define CCM_PRE_ROOT10_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,10)
6229 #define CCM_PRE_ROOT10_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,10)
6230 #define CCM_PRE_ROOT10_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,10)
6231 #define CCM_ACCESS_CTRL10                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,10)
6232 #define CCM_ACCESS_CTRL_ROOT10_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,10)
6233 #define CCM_ACCESS_CTRL_ROOT10_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,10)
6234 #define CCM_ACCESS_CTRL_ROOT10_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,10)
6235 #define CCM_TARGET_ROOT11                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,11)
6236 #define CCM_TARGET_ROOT11_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,11)
6237 #define CCM_TARGET_ROOT11_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,11)
6238 #define CCM_TARGET_ROOT11_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,11)
6239 #define CCM_MISC11                               CCM_MISC_REG(CCM_BASE_PTR,11)
6240 #define CCM_MISC_ROOT11_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,11)
6241 #define CCM_MISC_ROOT11_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,11)
6242 #define CCM_MISC_ROOT11_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,11)
6243 #define CCM_POST11                               CCM_POST_REG(CCM_BASE_PTR,11)
6244 #define CCM_POST_ROOT11_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,11)
6245 #define CCM_POST_ROOT11_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,11)
6246 #define CCM_POST_ROOT11_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,11)
6247 #define CCM_PRE11                                CCM_PRE_REG(CCM_BASE_PTR,11)
6248 #define CCM_PRE_ROOT11_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,11)
6249 #define CCM_PRE_ROOT11_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,11)
6250 #define CCM_PRE_ROOT11_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,11)
6251 #define CCM_ACCESS_CTRL11                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,11)
6252 #define CCM_ACCESS_CTRL_ROOT11_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,11)
6253 #define CCM_ACCESS_CTRL_ROOT11_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,11)
6254 #define CCM_ACCESS_CTRL_ROOT11_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,11)
6255 #define CCM_TARGET_ROOT12                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,12)
6256 #define CCM_TARGET_ROOT12_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,12)
6257 #define CCM_TARGET_ROOT12_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,12)
6258 #define CCM_TARGET_ROOT12_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,12)
6259 #define CCM_MISC12                               CCM_MISC_REG(CCM_BASE_PTR,12)
6260 #define CCM_MISC_ROOT12_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,12)
6261 #define CCM_MISC_ROOT12_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,12)
6262 #define CCM_MISC_ROOT12_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,12)
6263 #define CCM_POST12                               CCM_POST_REG(CCM_BASE_PTR,12)
6264 #define CCM_POST_ROOT12_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,12)
6265 #define CCM_POST_ROOT12_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,12)
6266 #define CCM_POST_ROOT12_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,12)
6267 #define CCM_PRE12                                CCM_PRE_REG(CCM_BASE_PTR,12)
6268 #define CCM_PRE_ROOT12_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,12)
6269 #define CCM_PRE_ROOT12_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,12)
6270 #define CCM_PRE_ROOT12_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,12)
6271 #define CCM_ACCESS_CTRL12                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,12)
6272 #define CCM_ACCESS_CTRL_ROOT12_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,12)
6273 #define CCM_ACCESS_CTRL_ROOT12_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,12)
6274 #define CCM_ACCESS_CTRL_ROOT12_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,12)
6275 #define CCM_TARGET_ROOT13                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,13)
6276 #define CCM_TARGET_ROOT13_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,13)
6277 #define CCM_TARGET_ROOT13_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,13)
6278 #define CCM_TARGET_ROOT13_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,13)
6279 #define CCM_MISC13                               CCM_MISC_REG(CCM_BASE_PTR,13)
6280 #define CCM_MISC_ROOT13_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,13)
6281 #define CCM_MISC_ROOT13_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,13)
6282 #define CCM_MISC_ROOT13_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,13)
6283 #define CCM_POST13                               CCM_POST_REG(CCM_BASE_PTR,13)
6284 #define CCM_POST_ROOT13_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,13)
6285 #define CCM_POST_ROOT13_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,13)
6286 #define CCM_POST_ROOT13_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,13)
6287 #define CCM_PRE13                                CCM_PRE_REG(CCM_BASE_PTR,13)
6288 #define CCM_PRE_ROOT13_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,13)
6289 #define CCM_PRE_ROOT13_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,13)
6290 #define CCM_PRE_ROOT13_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,13)
6291 #define CCM_ACCESS_CTRL13                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,13)
6292 #define CCM_ACCESS_CTRL_ROOT13_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,13)
6293 #define CCM_ACCESS_CTRL_ROOT13_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,13)
6294 #define CCM_ACCESS_CTRL_ROOT13_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,13)
6295 #define CCM_TARGET_ROOT14                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,14)
6296 #define CCM_TARGET_ROOT14_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,14)
6297 #define CCM_TARGET_ROOT14_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,14)
6298 #define CCM_TARGET_ROOT14_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,14)
6299 #define CCM_MISC14                               CCM_MISC_REG(CCM_BASE_PTR,14)
6300 #define CCM_MISC_ROOT14_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,14)
6301 #define CCM_MISC_ROOT14_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,14)
6302 #define CCM_MISC_ROOT14_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,14)
6303 #define CCM_POST14                               CCM_POST_REG(CCM_BASE_PTR,14)
6304 #define CCM_POST_ROOT14_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,14)
6305 #define CCM_POST_ROOT14_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,14)
6306 #define CCM_POST_ROOT14_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,14)
6307 #define CCM_PRE14                                CCM_PRE_REG(CCM_BASE_PTR,14)
6308 #define CCM_PRE_ROOT14_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,14)
6309 #define CCM_PRE_ROOT14_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,14)
6310 #define CCM_PRE_ROOT14_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,14)
6311 #define CCM_ACCESS_CTRL14                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,14)
6312 #define CCM_ACCESS_CTRL_ROOT14_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,14)
6313 #define CCM_ACCESS_CTRL_ROOT14_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,14)
6314 #define CCM_ACCESS_CTRL_ROOT14_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,14)
6315 #define CCM_TARGET_ROOT15                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,15)
6316 #define CCM_TARGET_ROOT15_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,15)
6317 #define CCM_TARGET_ROOT15_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,15)
6318 #define CCM_TARGET_ROOT15_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,15)
6319 #define CCM_MISC15                               CCM_MISC_REG(CCM_BASE_PTR,15)
6320 #define CCM_MISC_ROOT15_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,15)
6321 #define CCM_MISC_ROOT15_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,15)
6322 #define CCM_MISC_ROOT15_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,15)
6323 #define CCM_POST15                               CCM_POST_REG(CCM_BASE_PTR,15)
6324 #define CCM_POST_ROOT15_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,15)
6325 #define CCM_POST_ROOT15_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,15)
6326 #define CCM_POST_ROOT15_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,15)
6327 #define CCM_PRE15                                CCM_PRE_REG(CCM_BASE_PTR,15)
6328 #define CCM_PRE_ROOT15_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,15)
6329 #define CCM_PRE_ROOT15_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,15)
6330 #define CCM_PRE_ROOT15_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,15)
6331 #define CCM_ACCESS_CTRL15                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,15)
6332 #define CCM_ACCESS_CTRL_ROOT15_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,15)
6333 #define CCM_ACCESS_CTRL_ROOT15_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,15)
6334 #define CCM_ACCESS_CTRL_ROOT15_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,15)
6335 #define CCM_TARGET_ROOT16                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,16)
6336 #define CCM_TARGET_ROOT16_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,16)
6337 #define CCM_TARGET_ROOT16_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,16)
6338 #define CCM_TARGET_ROOT16_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,16)
6339 #define CCM_MISC16                               CCM_MISC_REG(CCM_BASE_PTR,16)
6340 #define CCM_MISC_ROOT16_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,16)
6341 #define CCM_MISC_ROOT16_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,16)
6342 #define CCM_MISC_ROOT16_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,16)
6343 #define CCM_POST16                               CCM_POST_REG(CCM_BASE_PTR,16)
6344 #define CCM_POST_ROOT16_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,16)
6345 #define CCM_POST_ROOT16_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,16)
6346 #define CCM_POST_ROOT16_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,16)
6347 #define CCM_PRE16                                CCM_PRE_REG(CCM_BASE_PTR,16)
6348 #define CCM_PRE_ROOT16_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,16)
6349 #define CCM_PRE_ROOT16_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,16)
6350 #define CCM_PRE_ROOT16_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,16)
6351 #define CCM_ACCESS_CTRL16                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,16)
6352 #define CCM_ACCESS_CTRL_ROOT16_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,16)
6353 #define CCM_ACCESS_CTRL_ROOT16_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,16)
6354 #define CCM_ACCESS_CTRL_ROOT16_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,16)
6355 #define CCM_TARGET_ROOT17                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,17)
6356 #define CCM_TARGET_ROOT17_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,17)
6357 #define CCM_TARGET_ROOT17_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,17)
6358 #define CCM_TARGET_ROOT17_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,17)
6359 #define CCM_MISC17                               CCM_MISC_REG(CCM_BASE_PTR,17)
6360 #define CCM_MISC_ROOT17_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,17)
6361 #define CCM_MISC_ROOT17_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,17)
6362 #define CCM_MISC_ROOT17_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,17)
6363 #define CCM_POST17                               CCM_POST_REG(CCM_BASE_PTR,17)
6364 #define CCM_POST_ROOT17_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,17)
6365 #define CCM_POST_ROOT17_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,17)
6366 #define CCM_POST_ROOT17_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,17)
6367 #define CCM_PRE17                                CCM_PRE_REG(CCM_BASE_PTR,17)
6368 #define CCM_PRE_ROOT17_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,17)
6369 #define CCM_PRE_ROOT17_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,17)
6370 #define CCM_PRE_ROOT17_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,17)
6371 #define CCM_ACCESS_CTRL17                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,17)
6372 #define CCM_ACCESS_CTRL_ROOT17_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,17)
6373 #define CCM_ACCESS_CTRL_ROOT17_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,17)
6374 #define CCM_ACCESS_CTRL_ROOT17_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,17)
6375 #define CCM_TARGET_ROOT18                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,18)
6376 #define CCM_TARGET_ROOT18_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,18)
6377 #define CCM_TARGET_ROOT18_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,18)
6378 #define CCM_TARGET_ROOT18_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,18)
6379 #define CCM_MISC18                               CCM_MISC_REG(CCM_BASE_PTR,18)
6380 #define CCM_MISC_ROOT18_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,18)
6381 #define CCM_MISC_ROOT18_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,18)
6382 #define CCM_MISC_ROOT18_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,18)
6383 #define CCM_POST18                               CCM_POST_REG(CCM_BASE_PTR,18)
6384 #define CCM_POST_ROOT18_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,18)
6385 #define CCM_POST_ROOT18_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,18)
6386 #define CCM_POST_ROOT18_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,18)
6387 #define CCM_PRE18                                CCM_PRE_REG(CCM_BASE_PTR,18)
6388 #define CCM_PRE_ROOT18_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,18)
6389 #define CCM_PRE_ROOT18_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,18)
6390 #define CCM_PRE_ROOT18_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,18)
6391 #define CCM_ACCESS_CTRL18                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,18)
6392 #define CCM_ACCESS_CTRL_ROOT18_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,18)
6393 #define CCM_ACCESS_CTRL_ROOT18_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,18)
6394 #define CCM_ACCESS_CTRL_ROOT18_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,18)
6395 #define CCM_TARGET_ROOT19                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,19)
6396 #define CCM_TARGET_ROOT19_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,19)
6397 #define CCM_TARGET_ROOT19_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,19)
6398 #define CCM_TARGET_ROOT19_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,19)
6399 #define CCM_MISC19                               CCM_MISC_REG(CCM_BASE_PTR,19)
6400 #define CCM_MISC_ROOT19_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,19)
6401 #define CCM_MISC_ROOT19_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,19)
6402 #define CCM_MISC_ROOT19_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,19)
6403 #define CCM_POST19                               CCM_POST_REG(CCM_BASE_PTR,19)
6404 #define CCM_POST_ROOT19_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,19)
6405 #define CCM_POST_ROOT19_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,19)
6406 #define CCM_POST_ROOT19_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,19)
6407 #define CCM_PRE19                                CCM_PRE_REG(CCM_BASE_PTR,19)
6408 #define CCM_PRE_ROOT19_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,19)
6409 #define CCM_PRE_ROOT19_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,19)
6410 #define CCM_PRE_ROOT19_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,19)
6411 #define CCM_ACCESS_CTRL19                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,19)
6412 #define CCM_ACCESS_CTRL_ROOT19_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,19)
6413 #define CCM_ACCESS_CTRL_ROOT19_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,19)
6414 #define CCM_ACCESS_CTRL_ROOT19_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,19)
6415 #define CCM_TARGET_ROOT20                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,20)
6416 #define CCM_TARGET_ROOT20_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,20)
6417 #define CCM_TARGET_ROOT20_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,20)
6418 #define CCM_TARGET_ROOT20_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,20)
6419 #define CCM_MISC20                               CCM_MISC_REG(CCM_BASE_PTR,20)
6420 #define CCM_MISC_ROOT20_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,20)
6421 #define CCM_MISC_ROOT20_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,20)
6422 #define CCM_MISC_ROOT20_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,20)
6423 #define CCM_POST20                               CCM_POST_REG(CCM_BASE_PTR,20)
6424 #define CCM_POST_ROOT20_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,20)
6425 #define CCM_POST_ROOT20_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,20)
6426 #define CCM_POST_ROOT20_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,20)
6427 #define CCM_PRE20                                CCM_PRE_REG(CCM_BASE_PTR,20)
6428 #define CCM_PRE_ROOT20_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,20)
6429 #define CCM_PRE_ROOT20_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,20)
6430 #define CCM_PRE_ROOT20_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,20)
6431 #define CCM_ACCESS_CTRL20                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,20)
6432 #define CCM_ACCESS_CTRL_ROOT20_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,20)
6433 #define CCM_ACCESS_CTRL_ROOT20_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,20)
6434 #define CCM_ACCESS_CTRL_ROOT20_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,20)
6435 #define CCM_TARGET_ROOT21                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,21)
6436 #define CCM_TARGET_ROOT21_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,21)
6437 #define CCM_TARGET_ROOT21_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,21)
6438 #define CCM_TARGET_ROOT21_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,21)
6439 #define CCM_MISC21                               CCM_MISC_REG(CCM_BASE_PTR,21)
6440 #define CCM_MISC_ROOT21_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,21)
6441 #define CCM_MISC_ROOT21_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,21)
6442 #define CCM_MISC_ROOT21_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,21)
6443 #define CCM_POST21                               CCM_POST_REG(CCM_BASE_PTR,21)
6444 #define CCM_POST_ROOT21_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,21)
6445 #define CCM_POST_ROOT21_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,21)
6446 #define CCM_POST_ROOT21_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,21)
6447 #define CCM_PRE21                                CCM_PRE_REG(CCM_BASE_PTR,21)
6448 #define CCM_PRE_ROOT21_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,21)
6449 #define CCM_PRE_ROOT21_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,21)
6450 #define CCM_PRE_ROOT21_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,21)
6451 #define CCM_ACCESS_CTRL21                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,21)
6452 #define CCM_ACCESS_CTRL_ROOT21_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,21)
6453 #define CCM_ACCESS_CTRL_ROOT21_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,21)
6454 #define CCM_ACCESS_CTRL_ROOT21_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,21)
6455 #define CCM_TARGET_ROOT22                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,22)
6456 #define CCM_TARGET_ROOT22_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,22)
6457 #define CCM_TARGET_ROOT22_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,22)
6458 #define CCM_TARGET_ROOT22_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,22)
6459 #define CCM_MISC22                               CCM_MISC_REG(CCM_BASE_PTR,22)
6460 #define CCM_MISC_ROOT22_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,22)
6461 #define CCM_MISC_ROOT22_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,22)
6462 #define CCM_MISC_ROOT22_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,22)
6463 #define CCM_POST22                               CCM_POST_REG(CCM_BASE_PTR,22)
6464 #define CCM_POST_ROOT22_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,22)
6465 #define CCM_POST_ROOT22_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,22)
6466 #define CCM_POST_ROOT22_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,22)
6467 #define CCM_PRE22                                CCM_PRE_REG(CCM_BASE_PTR,22)
6468 #define CCM_PRE_ROOT22_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,22)
6469 #define CCM_PRE_ROOT22_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,22)
6470 #define CCM_PRE_ROOT22_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,22)
6471 #define CCM_ACCESS_CTRL22                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,22)
6472 #define CCM_ACCESS_CTRL_ROOT22_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,22)
6473 #define CCM_ACCESS_CTRL_ROOT22_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,22)
6474 #define CCM_ACCESS_CTRL_ROOT22_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,22)
6475 #define CCM_TARGET_ROOT23                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,23)
6476 #define CCM_TARGET_ROOT23_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,23)
6477 #define CCM_TARGET_ROOT23_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,23)
6478 #define CCM_TARGET_ROOT23_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,23)
6479 #define CCM_MISC23                               CCM_MISC_REG(CCM_BASE_PTR,23)
6480 #define CCM_MISC_ROOT23_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,23)
6481 #define CCM_MISC_ROOT23_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,23)
6482 #define CCM_MISC_ROOT23_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,23)
6483 #define CCM_POST23                               CCM_POST_REG(CCM_BASE_PTR,23)
6484 #define CCM_POST_ROOT23_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,23)
6485 #define CCM_POST_ROOT23_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,23)
6486 #define CCM_POST_ROOT23_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,23)
6487 #define CCM_PRE23                                CCM_PRE_REG(CCM_BASE_PTR,23)
6488 #define CCM_PRE_ROOT23_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,23)
6489 #define CCM_PRE_ROOT23_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,23)
6490 #define CCM_PRE_ROOT23_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,23)
6491 #define CCM_ACCESS_CTRL23                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,23)
6492 #define CCM_ACCESS_CTRL_ROOT23_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,23)
6493 #define CCM_ACCESS_CTRL_ROOT23_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,23)
6494 #define CCM_ACCESS_CTRL_ROOT23_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,23)
6495 #define CCM_TARGET_ROOT24                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,24)
6496 #define CCM_TARGET_ROOT24_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,24)
6497 #define CCM_TARGET_ROOT24_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,24)
6498 #define CCM_TARGET_ROOT24_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,24)
6499 #define CCM_MISC24                               CCM_MISC_REG(CCM_BASE_PTR,24)
6500 #define CCM_MISC_ROOT24_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,24)
6501 #define CCM_MISC_ROOT24_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,24)
6502 #define CCM_MISC_ROOT24_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,24)
6503 #define CCM_POST24                               CCM_POST_REG(CCM_BASE_PTR,24)
6504 #define CCM_POST_ROOT24_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,24)
6505 #define CCM_POST_ROOT24_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,24)
6506 #define CCM_POST_ROOT24_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,24)
6507 #define CCM_PRE24                                CCM_PRE_REG(CCM_BASE_PTR,24)
6508 #define CCM_PRE_ROOT24_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,24)
6509 #define CCM_PRE_ROOT24_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,24)
6510 #define CCM_PRE_ROOT24_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,24)
6511 #define CCM_ACCESS_CTRL24                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,24)
6512 #define CCM_ACCESS_CTRL_ROOT24_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,24)
6513 #define CCM_ACCESS_CTRL_ROOT24_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,24)
6514 #define CCM_ACCESS_CTRL_ROOT24_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,24)
6515 #define CCM_TARGET_ROOT25                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,25)
6516 #define CCM_TARGET_ROOT25_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,25)
6517 #define CCM_TARGET_ROOT25_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,25)
6518 #define CCM_TARGET_ROOT25_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,25)
6519 #define CCM_MISC25                               CCM_MISC_REG(CCM_BASE_PTR,25)
6520 #define CCM_MISC_ROOT25_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,25)
6521 #define CCM_MISC_ROOT25_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,25)
6522 #define CCM_MISC_ROOT25_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,25)
6523 #define CCM_POST25                               CCM_POST_REG(CCM_BASE_PTR,25)
6524 #define CCM_POST_ROOT25_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,25)
6525 #define CCM_POST_ROOT25_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,25)
6526 #define CCM_POST_ROOT25_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,25)
6527 #define CCM_PRE25                                CCM_PRE_REG(CCM_BASE_PTR,25)
6528 #define CCM_PRE_ROOT25_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,25)
6529 #define CCM_PRE_ROOT25_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,25)
6530 #define CCM_PRE_ROOT25_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,25)
6531 #define CCM_ACCESS_CTRL25                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,25)
6532 #define CCM_ACCESS_CTRL_ROOT25_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,25)
6533 #define CCM_ACCESS_CTRL_ROOT25_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,25)
6534 #define CCM_ACCESS_CTRL_ROOT25_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,25)
6535 #define CCM_TARGET_ROOT26                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,26)
6536 #define CCM_TARGET_ROOT26_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,26)
6537 #define CCM_TARGET_ROOT26_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,26)
6538 #define CCM_TARGET_ROOT26_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,26)
6539 #define CCM_MISC26                               CCM_MISC_REG(CCM_BASE_PTR,26)
6540 #define CCM_MISC_ROOT26_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,26)
6541 #define CCM_MISC_ROOT26_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,26)
6542 #define CCM_MISC_ROOT26_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,26)
6543 #define CCM_POST26                               CCM_POST_REG(CCM_BASE_PTR,26)
6544 #define CCM_POST_ROOT26_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,26)
6545 #define CCM_POST_ROOT26_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,26)
6546 #define CCM_POST_ROOT26_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,26)
6547 #define CCM_PRE26                                CCM_PRE_REG(CCM_BASE_PTR,26)
6548 #define CCM_PRE_ROOT26_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,26)
6549 #define CCM_PRE_ROOT26_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,26)
6550 #define CCM_PRE_ROOT26_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,26)
6551 #define CCM_ACCESS_CTRL26                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,26)
6552 #define CCM_ACCESS_CTRL_ROOT26_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,26)
6553 #define CCM_ACCESS_CTRL_ROOT26_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,26)
6554 #define CCM_ACCESS_CTRL_ROOT26_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,26)
6555 #define CCM_TARGET_ROOT27                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,27)
6556 #define CCM_TARGET_ROOT27_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,27)
6557 #define CCM_TARGET_ROOT27_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,27)
6558 #define CCM_TARGET_ROOT27_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,27)
6559 #define CCM_MISC27                               CCM_MISC_REG(CCM_BASE_PTR,27)
6560 #define CCM_MISC_ROOT27_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,27)
6561 #define CCM_MISC_ROOT27_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,27)
6562 #define CCM_MISC_ROOT27_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,27)
6563 #define CCM_POST27                               CCM_POST_REG(CCM_BASE_PTR,27)
6564 #define CCM_POST_ROOT27_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,27)
6565 #define CCM_POST_ROOT27_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,27)
6566 #define CCM_POST_ROOT27_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,27)
6567 #define CCM_PRE27                                CCM_PRE_REG(CCM_BASE_PTR,27)
6568 #define CCM_PRE_ROOT27_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,27)
6569 #define CCM_PRE_ROOT27_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,27)
6570 #define CCM_PRE_ROOT27_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,27)
6571 #define CCM_ACCESS_CTRL27                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,27)
6572 #define CCM_ACCESS_CTRL_ROOT27_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,27)
6573 #define CCM_ACCESS_CTRL_ROOT27_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,27)
6574 #define CCM_ACCESS_CTRL_ROOT27_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,27)
6575 #define CCM_TARGET_ROOT28                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,28)
6576 #define CCM_TARGET_ROOT28_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,28)
6577 #define CCM_TARGET_ROOT28_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,28)
6578 #define CCM_TARGET_ROOT28_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,28)
6579 #define CCM_MISC28                               CCM_MISC_REG(CCM_BASE_PTR,28)
6580 #define CCM_MISC_ROOT28_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,28)
6581 #define CCM_MISC_ROOT28_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,28)
6582 #define CCM_MISC_ROOT28_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,28)
6583 #define CCM_POST28                               CCM_POST_REG(CCM_BASE_PTR,28)
6584 #define CCM_POST_ROOT28_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,28)
6585 #define CCM_POST_ROOT28_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,28)
6586 #define CCM_POST_ROOT28_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,28)
6587 #define CCM_PRE28                                CCM_PRE_REG(CCM_BASE_PTR,28)
6588 #define CCM_PRE_ROOT28_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,28)
6589 #define CCM_PRE_ROOT28_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,28)
6590 #define CCM_PRE_ROOT28_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,28)
6591 #define CCM_ACCESS_CTRL28                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,28)
6592 #define CCM_ACCESS_CTRL_ROOT28_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,28)
6593 #define CCM_ACCESS_CTRL_ROOT28_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,28)
6594 #define CCM_ACCESS_CTRL_ROOT28_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,28)
6595 #define CCM_TARGET_ROOT29                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,29)
6596 #define CCM_TARGET_ROOT29_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,29)
6597 #define CCM_TARGET_ROOT29_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,29)
6598 #define CCM_TARGET_ROOT29_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,29)
6599 #define CCM_MISC29                               CCM_MISC_REG(CCM_BASE_PTR,29)
6600 #define CCM_MISC_ROOT29_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,29)
6601 #define CCM_MISC_ROOT29_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,29)
6602 #define CCM_MISC_ROOT29_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,29)
6603 #define CCM_POST29                               CCM_POST_REG(CCM_BASE_PTR,29)
6604 #define CCM_POST_ROOT29_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,29)
6605 #define CCM_POST_ROOT29_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,29)
6606 #define CCM_POST_ROOT29_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,29)
6607 #define CCM_PRE29                                CCM_PRE_REG(CCM_BASE_PTR,29)
6608 #define CCM_PRE_ROOT29_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,29)
6609 #define CCM_PRE_ROOT29_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,29)
6610 #define CCM_PRE_ROOT29_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,29)
6611 #define CCM_ACCESS_CTRL29                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,29)
6612 #define CCM_ACCESS_CTRL_ROOT29_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,29)
6613 #define CCM_ACCESS_CTRL_ROOT29_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,29)
6614 #define CCM_ACCESS_CTRL_ROOT29_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,29)
6615 #define CCM_TARGET_ROOT30                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,30)
6616 #define CCM_TARGET_ROOT30_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,30)
6617 #define CCM_TARGET_ROOT30_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,30)
6618 #define CCM_TARGET_ROOT30_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,30)
6619 #define CCM_MISC30                               CCM_MISC_REG(CCM_BASE_PTR,30)
6620 #define CCM_MISC_ROOT30_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,30)
6621 #define CCM_MISC_ROOT30_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,30)
6622 #define CCM_MISC_ROOT30_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,30)
6623 #define CCM_POST30                               CCM_POST_REG(CCM_BASE_PTR,30)
6624 #define CCM_POST_ROOT30_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,30)
6625 #define CCM_POST_ROOT30_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,30)
6626 #define CCM_POST_ROOT30_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,30)
6627 #define CCM_PRE30                                CCM_PRE_REG(CCM_BASE_PTR,30)
6628 #define CCM_PRE_ROOT30_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,30)
6629 #define CCM_PRE_ROOT30_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,30)
6630 #define CCM_PRE_ROOT30_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,30)
6631 #define CCM_ACCESS_CTRL30                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,30)
6632 #define CCM_ACCESS_CTRL_ROOT30_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,30)
6633 #define CCM_ACCESS_CTRL_ROOT30_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,30)
6634 #define CCM_ACCESS_CTRL_ROOT30_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,30)
6635 #define CCM_TARGET_ROOT31                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,31)
6636 #define CCM_TARGET_ROOT31_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,31)
6637 #define CCM_TARGET_ROOT31_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,31)
6638 #define CCM_TARGET_ROOT31_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,31)
6639 #define CCM_MISC31                               CCM_MISC_REG(CCM_BASE_PTR,31)
6640 #define CCM_MISC_ROOT31_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,31)
6641 #define CCM_MISC_ROOT31_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,31)
6642 #define CCM_MISC_ROOT31_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,31)
6643 #define CCM_POST31                               CCM_POST_REG(CCM_BASE_PTR,31)
6644 #define CCM_POST_ROOT31_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,31)
6645 #define CCM_POST_ROOT31_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,31)
6646 #define CCM_POST_ROOT31_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,31)
6647 #define CCM_PRE31                                CCM_PRE_REG(CCM_BASE_PTR,31)
6648 #define CCM_PRE_ROOT31_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,31)
6649 #define CCM_PRE_ROOT31_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,31)
6650 #define CCM_PRE_ROOT31_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,31)
6651 #define CCM_ACCESS_CTRL31                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,31)
6652 #define CCM_ACCESS_CTRL_ROOT31_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,31)
6653 #define CCM_ACCESS_CTRL_ROOT31_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,31)
6654 #define CCM_ACCESS_CTRL_ROOT31_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,31)
6655 #define CCM_TARGET_ROOT32                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,32)
6656 #define CCM_TARGET_ROOT32_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,32)
6657 #define CCM_TARGET_ROOT32_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,32)
6658 #define CCM_TARGET_ROOT32_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,32)
6659 #define CCM_MISC32                               CCM_MISC_REG(CCM_BASE_PTR,32)
6660 #define CCM_MISC_ROOT32_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,32)
6661 #define CCM_MISC_ROOT32_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,32)
6662 #define CCM_MISC_ROOT32_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,32)
6663 #define CCM_POST32                               CCM_POST_REG(CCM_BASE_PTR,32)
6664 #define CCM_POST_ROOT32_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,32)
6665 #define CCM_POST_ROOT32_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,32)
6666 #define CCM_POST_ROOT32_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,32)
6667 #define CCM_PRE32                                CCM_PRE_REG(CCM_BASE_PTR,32)
6668 #define CCM_PRE_ROOT32_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,32)
6669 #define CCM_PRE_ROOT32_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,32)
6670 #define CCM_PRE_ROOT32_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,32)
6671 #define CCM_ACCESS_CTRL32                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,32)
6672 #define CCM_ACCESS_CTRL_ROOT32_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,32)
6673 #define CCM_ACCESS_CTRL_ROOT32_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,32)
6674 #define CCM_ACCESS_CTRL_ROOT32_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,32)
6675 #define CCM_TARGET_ROOT33                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,33)
6676 #define CCM_TARGET_ROOT33_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,33)
6677 #define CCM_TARGET_ROOT33_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,33)
6678 #define CCM_TARGET_ROOT33_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,33)
6679 #define CCM_MISC33                               CCM_MISC_REG(CCM_BASE_PTR,33)
6680 #define CCM_MISC_ROOT33_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,33)
6681 #define CCM_MISC_ROOT33_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,33)
6682 #define CCM_MISC_ROOT33_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,33)
6683 #define CCM_POST33                               CCM_POST_REG(CCM_BASE_PTR,33)
6684 #define CCM_POST_ROOT33_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,33)
6685 #define CCM_POST_ROOT33_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,33)
6686 #define CCM_POST_ROOT33_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,33)
6687 #define CCM_PRE33                                CCM_PRE_REG(CCM_BASE_PTR,33)
6688 #define CCM_PRE_ROOT33_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,33)
6689 #define CCM_PRE_ROOT33_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,33)
6690 #define CCM_PRE_ROOT33_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,33)
6691 #define CCM_ACCESS_CTRL33                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,33)
6692 #define CCM_ACCESS_CTRL_ROOT33_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,33)
6693 #define CCM_ACCESS_CTRL_ROOT33_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,33)
6694 #define CCM_ACCESS_CTRL_ROOT33_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,33)
6695 #define CCM_TARGET_ROOT34                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,34)
6696 #define CCM_TARGET_ROOT34_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,34)
6697 #define CCM_TARGET_ROOT34_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,34)
6698 #define CCM_TARGET_ROOT34_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,34)
6699 #define CCM_MISC34                               CCM_MISC_REG(CCM_BASE_PTR,34)
6700 #define CCM_MISC_ROOT34_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,34)
6701 #define CCM_MISC_ROOT34_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,34)
6702 #define CCM_MISC_ROOT34_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,34)
6703 #define CCM_POST34                               CCM_POST_REG(CCM_BASE_PTR,34)
6704 #define CCM_POST_ROOT34_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,34)
6705 #define CCM_POST_ROOT34_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,34)
6706 #define CCM_POST_ROOT34_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,34)
6707 #define CCM_PRE34                                CCM_PRE_REG(CCM_BASE_PTR,34)
6708 #define CCM_PRE_ROOT34_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,34)
6709 #define CCM_PRE_ROOT34_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,34)
6710 #define CCM_PRE_ROOT34_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,34)
6711 #define CCM_ACCESS_CTRL34                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,34)
6712 #define CCM_ACCESS_CTRL_ROOT34_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,34)
6713 #define CCM_ACCESS_CTRL_ROOT34_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,34)
6714 #define CCM_ACCESS_CTRL_ROOT34_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,34)
6715 #define CCM_TARGET_ROOT35                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,35)
6716 #define CCM_TARGET_ROOT35_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,35)
6717 #define CCM_TARGET_ROOT35_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,35)
6718 #define CCM_TARGET_ROOT35_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,35)
6719 #define CCM_MISC35                               CCM_MISC_REG(CCM_BASE_PTR,35)
6720 #define CCM_MISC_ROOT35_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,35)
6721 #define CCM_MISC_ROOT35_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,35)
6722 #define CCM_MISC_ROOT35_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,35)
6723 #define CCM_POST35                               CCM_POST_REG(CCM_BASE_PTR,35)
6724 #define CCM_POST_ROOT35_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,35)
6725 #define CCM_POST_ROOT35_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,35)
6726 #define CCM_POST_ROOT35_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,35)
6727 #define CCM_PRE35                                CCM_PRE_REG(CCM_BASE_PTR,35)
6728 #define CCM_PRE_ROOT35_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,35)
6729 #define CCM_PRE_ROOT35_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,35)
6730 #define CCM_PRE_ROOT35_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,35)
6731 #define CCM_ACCESS_CTRL35                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,35)
6732 #define CCM_ACCESS_CTRL_ROOT35_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,35)
6733 #define CCM_ACCESS_CTRL_ROOT35_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,35)
6734 #define CCM_ACCESS_CTRL_ROOT35_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,35)
6735 #define CCM_TARGET_ROOT36                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,36)
6736 #define CCM_TARGET_ROOT36_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,36)
6737 #define CCM_TARGET_ROOT36_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,36)
6738 #define CCM_TARGET_ROOT36_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,36)
6739 #define CCM_MISC36                               CCM_MISC_REG(CCM_BASE_PTR,36)
6740 #define CCM_MISC_ROOT36_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,36)
6741 #define CCM_MISC_ROOT36_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,36)
6742 #define CCM_MISC_ROOT36_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,36)
6743 #define CCM_POST36                               CCM_POST_REG(CCM_BASE_PTR,36)
6744 #define CCM_POST_ROOT36_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,36)
6745 #define CCM_POST_ROOT36_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,36)
6746 #define CCM_POST_ROOT36_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,36)
6747 #define CCM_PRE36                                CCM_PRE_REG(CCM_BASE_PTR,36)
6748 #define CCM_PRE_ROOT36_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,36)
6749 #define CCM_PRE_ROOT36_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,36)
6750 #define CCM_PRE_ROOT36_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,36)
6751 #define CCM_ACCESS_CTRL36                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,36)
6752 #define CCM_ACCESS_CTRL_ROOT36_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,36)
6753 #define CCM_ACCESS_CTRL_ROOT36_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,36)
6754 #define CCM_ACCESS_CTRL_ROOT36_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,36)
6755 #define CCM_TARGET_ROOT37                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,37)
6756 #define CCM_TARGET_ROOT37_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,37)
6757 #define CCM_TARGET_ROOT37_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,37)
6758 #define CCM_TARGET_ROOT37_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,37)
6759 #define CCM_MISC37                               CCM_MISC_REG(CCM_BASE_PTR,37)
6760 #define CCM_MISC_ROOT37_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,37)
6761 #define CCM_MISC_ROOT37_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,37)
6762 #define CCM_MISC_ROOT37_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,37)
6763 #define CCM_POST37                               CCM_POST_REG(CCM_BASE_PTR,37)
6764 #define CCM_POST_ROOT37_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,37)
6765 #define CCM_POST_ROOT37_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,37)
6766 #define CCM_POST_ROOT37_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,37)
6767 #define CCM_PRE37                                CCM_PRE_REG(CCM_BASE_PTR,37)
6768 #define CCM_PRE_ROOT37_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,37)
6769 #define CCM_PRE_ROOT37_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,37)
6770 #define CCM_PRE_ROOT37_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,37)
6771 #define CCM_ACCESS_CTRL37                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,37)
6772 #define CCM_ACCESS_CTRL_ROOT37_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,37)
6773 #define CCM_ACCESS_CTRL_ROOT37_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,37)
6774 #define CCM_ACCESS_CTRL_ROOT37_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,37)
6775 #define CCM_TARGET_ROOT38                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,38)
6776 #define CCM_TARGET_ROOT38_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,38)
6777 #define CCM_TARGET_ROOT38_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,38)
6778 #define CCM_TARGET_ROOT38_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,38)
6779 #define CCM_MISC38                               CCM_MISC_REG(CCM_BASE_PTR,38)
6780 #define CCM_MISC_ROOT38_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,38)
6781 #define CCM_MISC_ROOT38_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,38)
6782 #define CCM_MISC_ROOT38_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,38)
6783 #define CCM_POST38                               CCM_POST_REG(CCM_BASE_PTR,38)
6784 #define CCM_POST_ROOT38_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,38)
6785 #define CCM_POST_ROOT38_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,38)
6786 #define CCM_POST_ROOT38_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,38)
6787 #define CCM_PRE38                                CCM_PRE_REG(CCM_BASE_PTR,38)
6788 #define CCM_PRE_ROOT38_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,38)
6789 #define CCM_PRE_ROOT38_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,38)
6790 #define CCM_PRE_ROOT38_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,38)
6791 #define CCM_ACCESS_CTRL38                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,38)
6792 #define CCM_ACCESS_CTRL_ROOT38_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,38)
6793 #define CCM_ACCESS_CTRL_ROOT38_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,38)
6794 #define CCM_ACCESS_CTRL_ROOT38_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,38)
6795 #define CCM_TARGET_ROOT39                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,39)
6796 #define CCM_TARGET_ROOT39_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,39)
6797 #define CCM_TARGET_ROOT39_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,39)
6798 #define CCM_TARGET_ROOT39_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,39)
6799 #define CCM_MISC39                               CCM_MISC_REG(CCM_BASE_PTR,39)
6800 #define CCM_MISC_ROOT39_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,39)
6801 #define CCM_MISC_ROOT39_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,39)
6802 #define CCM_MISC_ROOT39_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,39)
6803 #define CCM_POST39                               CCM_POST_REG(CCM_BASE_PTR,39)
6804 #define CCM_POST_ROOT39_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,39)
6805 #define CCM_POST_ROOT39_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,39)
6806 #define CCM_POST_ROOT39_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,39)
6807 #define CCM_PRE39                                CCM_PRE_REG(CCM_BASE_PTR,39)
6808 #define CCM_PRE_ROOT39_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,39)
6809 #define CCM_PRE_ROOT39_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,39)
6810 #define CCM_PRE_ROOT39_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,39)
6811 #define CCM_ACCESS_CTRL39                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,39)
6812 #define CCM_ACCESS_CTRL_ROOT39_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,39)
6813 #define CCM_ACCESS_CTRL_ROOT39_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,39)
6814 #define CCM_ACCESS_CTRL_ROOT39_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,39)
6815 #define CCM_TARGET_ROOT40                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,40)
6816 #define CCM_TARGET_ROOT40_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,40)
6817 #define CCM_TARGET_ROOT40_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,40)
6818 #define CCM_TARGET_ROOT40_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,40)
6819 #define CCM_MISC40                               CCM_MISC_REG(CCM_BASE_PTR,40)
6820 #define CCM_MISC_ROOT40_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,40)
6821 #define CCM_MISC_ROOT40_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,40)
6822 #define CCM_MISC_ROOT40_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,40)
6823 #define CCM_POST40                               CCM_POST_REG(CCM_BASE_PTR,40)
6824 #define CCM_POST_ROOT40_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,40)
6825 #define CCM_POST_ROOT40_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,40)
6826 #define CCM_POST_ROOT40_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,40)
6827 #define CCM_PRE40                                CCM_PRE_REG(CCM_BASE_PTR,40)
6828 #define CCM_PRE_ROOT40_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,40)
6829 #define CCM_PRE_ROOT40_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,40)
6830 #define CCM_PRE_ROOT40_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,40)
6831 #define CCM_ACCESS_CTRL40                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,40)
6832 #define CCM_ACCESS_CTRL_ROOT40_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,40)
6833 #define CCM_ACCESS_CTRL_ROOT40_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,40)
6834 #define CCM_ACCESS_CTRL_ROOT40_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,40)
6835 #define CCM_TARGET_ROOT41                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,41)
6836 #define CCM_TARGET_ROOT41_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,41)
6837 #define CCM_TARGET_ROOT41_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,41)
6838 #define CCM_TARGET_ROOT41_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,41)
6839 #define CCM_MISC41                               CCM_MISC_REG(CCM_BASE_PTR,41)
6840 #define CCM_MISC_ROOT41_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,41)
6841 #define CCM_MISC_ROOT41_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,41)
6842 #define CCM_MISC_ROOT41_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,41)
6843 #define CCM_POST41                               CCM_POST_REG(CCM_BASE_PTR,41)
6844 #define CCM_POST_ROOT41_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,41)
6845 #define CCM_POST_ROOT41_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,41)
6846 #define CCM_POST_ROOT41_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,41)
6847 #define CCM_PRE41                                CCM_PRE_REG(CCM_BASE_PTR,41)
6848 #define CCM_PRE_ROOT41_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,41)
6849 #define CCM_PRE_ROOT41_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,41)
6850 #define CCM_PRE_ROOT41_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,41)
6851 #define CCM_ACCESS_CTRL41                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,41)
6852 #define CCM_ACCESS_CTRL_ROOT41_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,41)
6853 #define CCM_ACCESS_CTRL_ROOT41_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,41)
6854 #define CCM_ACCESS_CTRL_ROOT41_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,41)
6855 #define CCM_TARGET_ROOT42                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,42)
6856 #define CCM_TARGET_ROOT42_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,42)
6857 #define CCM_TARGET_ROOT42_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,42)
6858 #define CCM_TARGET_ROOT42_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,42)
6859 #define CCM_MISC42                               CCM_MISC_REG(CCM_BASE_PTR,42)
6860 #define CCM_MISC_ROOT42_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,42)
6861 #define CCM_MISC_ROOT42_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,42)
6862 #define CCM_MISC_ROOT42_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,42)
6863 #define CCM_POST42                               CCM_POST_REG(CCM_BASE_PTR,42)
6864 #define CCM_POST_ROOT42_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,42)
6865 #define CCM_POST_ROOT42_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,42)
6866 #define CCM_POST_ROOT42_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,42)
6867 #define CCM_PRE42                                CCM_PRE_REG(CCM_BASE_PTR,42)
6868 #define CCM_PRE_ROOT42_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,42)
6869 #define CCM_PRE_ROOT42_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,42)
6870 #define CCM_PRE_ROOT42_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,42)
6871 #define CCM_ACCESS_CTRL42                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,42)
6872 #define CCM_ACCESS_CTRL_ROOT42_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,42)
6873 #define CCM_ACCESS_CTRL_ROOT42_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,42)
6874 #define CCM_ACCESS_CTRL_ROOT42_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,42)
6875 #define CCM_TARGET_ROOT43                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,43)
6876 #define CCM_TARGET_ROOT43_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,43)
6877 #define CCM_TARGET_ROOT43_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,43)
6878 #define CCM_TARGET_ROOT43_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,43)
6879 #define CCM_MISC43                               CCM_MISC_REG(CCM_BASE_PTR,43)
6880 #define CCM_MISC_ROOT43_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,43)
6881 #define CCM_MISC_ROOT43_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,43)
6882 #define CCM_MISC_ROOT43_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,43)
6883 #define CCM_POST43                               CCM_POST_REG(CCM_BASE_PTR,43)
6884 #define CCM_POST_ROOT43_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,43)
6885 #define CCM_POST_ROOT43_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,43)
6886 #define CCM_POST_ROOT43_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,43)
6887 #define CCM_PRE43                                CCM_PRE_REG(CCM_BASE_PTR,43)
6888 #define CCM_PRE_ROOT43_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,43)
6889 #define CCM_PRE_ROOT43_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,43)
6890 #define CCM_PRE_ROOT43_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,43)
6891 #define CCM_ACCESS_CTRL43                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,43)
6892 #define CCM_ACCESS_CTRL_ROOT43_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,43)
6893 #define CCM_ACCESS_CTRL_ROOT43_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,43)
6894 #define CCM_ACCESS_CTRL_ROOT43_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,43)
6895 #define CCM_TARGET_ROOT44                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,44)
6896 #define CCM_TARGET_ROOT44_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,44)
6897 #define CCM_TARGET_ROOT44_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,44)
6898 #define CCM_TARGET_ROOT44_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,44)
6899 #define CCM_MISC44                               CCM_MISC_REG(CCM_BASE_PTR,44)
6900 #define CCM_MISC_ROOT44_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,44)
6901 #define CCM_MISC_ROOT44_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,44)
6902 #define CCM_MISC_ROOT44_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,44)
6903 #define CCM_POST44                               CCM_POST_REG(CCM_BASE_PTR,44)
6904 #define CCM_POST_ROOT44_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,44)
6905 #define CCM_POST_ROOT44_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,44)
6906 #define CCM_POST_ROOT44_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,44)
6907 #define CCM_PRE44                                CCM_PRE_REG(CCM_BASE_PTR,44)
6908 #define CCM_PRE_ROOT44_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,44)
6909 #define CCM_PRE_ROOT44_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,44)
6910 #define CCM_PRE_ROOT44_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,44)
6911 #define CCM_ACCESS_CTRL44                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,44)
6912 #define CCM_ACCESS_CTRL_ROOT44_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,44)
6913 #define CCM_ACCESS_CTRL_ROOT44_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,44)
6914 #define CCM_ACCESS_CTRL_ROOT44_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,44)
6915 #define CCM_TARGET_ROOT45                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,45)
6916 #define CCM_TARGET_ROOT45_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,45)
6917 #define CCM_TARGET_ROOT45_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,45)
6918 #define CCM_TARGET_ROOT45_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,45)
6919 #define CCM_MISC45                               CCM_MISC_REG(CCM_BASE_PTR,45)
6920 #define CCM_MISC_ROOT45_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,45)
6921 #define CCM_MISC_ROOT45_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,45)
6922 #define CCM_MISC_ROOT45_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,45)
6923 #define CCM_POST45                               CCM_POST_REG(CCM_BASE_PTR,45)
6924 #define CCM_POST_ROOT45_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,45)
6925 #define CCM_POST_ROOT45_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,45)
6926 #define CCM_POST_ROOT45_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,45)
6927 #define CCM_PRE45                                CCM_PRE_REG(CCM_BASE_PTR,45)
6928 #define CCM_PRE_ROOT45_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,45)
6929 #define CCM_PRE_ROOT45_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,45)
6930 #define CCM_PRE_ROOT45_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,45)
6931 #define CCM_ACCESS_CTRL45                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,45)
6932 #define CCM_ACCESS_CTRL_ROOT45_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,45)
6933 #define CCM_ACCESS_CTRL_ROOT45_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,45)
6934 #define CCM_ACCESS_CTRL_ROOT45_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,45)
6935 #define CCM_TARGET_ROOT46                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,46)
6936 #define CCM_TARGET_ROOT46_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,46)
6937 #define CCM_TARGET_ROOT46_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,46)
6938 #define CCM_TARGET_ROOT46_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,46)
6939 #define CCM_MISC46                               CCM_MISC_REG(CCM_BASE_PTR,46)
6940 #define CCM_MISC_ROOT46_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,46)
6941 #define CCM_MISC_ROOT46_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,46)
6942 #define CCM_MISC_ROOT46_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,46)
6943 #define CCM_POST46                               CCM_POST_REG(CCM_BASE_PTR,46)
6944 #define CCM_POST_ROOT46_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,46)
6945 #define CCM_POST_ROOT46_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,46)
6946 #define CCM_POST_ROOT46_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,46)
6947 #define CCM_PRE46                                CCM_PRE_REG(CCM_BASE_PTR,46)
6948 #define CCM_PRE_ROOT46_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,46)
6949 #define CCM_PRE_ROOT46_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,46)
6950 #define CCM_PRE_ROOT46_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,46)
6951 #define CCM_ACCESS_CTRL46                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,46)
6952 #define CCM_ACCESS_CTRL_ROOT46_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,46)
6953 #define CCM_ACCESS_CTRL_ROOT46_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,46)
6954 #define CCM_ACCESS_CTRL_ROOT46_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,46)
6955 #define CCM_TARGET_ROOT47                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,47)
6956 #define CCM_TARGET_ROOT47_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,47)
6957 #define CCM_TARGET_ROOT47_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,47)
6958 #define CCM_TARGET_ROOT47_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,47)
6959 #define CCM_MISC47                               CCM_MISC_REG(CCM_BASE_PTR,47)
6960 #define CCM_MISC_ROOT47_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,47)
6961 #define CCM_MISC_ROOT47_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,47)
6962 #define CCM_MISC_ROOT47_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,47)
6963 #define CCM_POST47                               CCM_POST_REG(CCM_BASE_PTR,47)
6964 #define CCM_POST_ROOT47_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,47)
6965 #define CCM_POST_ROOT47_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,47)
6966 #define CCM_POST_ROOT47_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,47)
6967 #define CCM_PRE47                                CCM_PRE_REG(CCM_BASE_PTR,47)
6968 #define CCM_PRE_ROOT47_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,47)
6969 #define CCM_PRE_ROOT47_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,47)
6970 #define CCM_PRE_ROOT47_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,47)
6971 #define CCM_ACCESS_CTRL47                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,47)
6972 #define CCM_ACCESS_CTRL_ROOT47_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,47)
6973 #define CCM_ACCESS_CTRL_ROOT47_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,47)
6974 #define CCM_ACCESS_CTRL_ROOT47_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,47)
6975 #define CCM_TARGET_ROOT48                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,48)
6976 #define CCM_TARGET_ROOT48_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,48)
6977 #define CCM_TARGET_ROOT48_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,48)
6978 #define CCM_TARGET_ROOT48_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,48)
6979 #define CCM_MISC48                               CCM_MISC_REG(CCM_BASE_PTR,48)
6980 #define CCM_MISC_ROOT48_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,48)
6981 #define CCM_MISC_ROOT48_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,48)
6982 #define CCM_MISC_ROOT48_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,48)
6983 #define CCM_POST48                               CCM_POST_REG(CCM_BASE_PTR,48)
6984 #define CCM_POST_ROOT48_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,48)
6985 #define CCM_POST_ROOT48_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,48)
6986 #define CCM_POST_ROOT48_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,48)
6987 #define CCM_PRE48                                CCM_PRE_REG(CCM_BASE_PTR,48)
6988 #define CCM_PRE_ROOT48_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,48)
6989 #define CCM_PRE_ROOT48_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,48)
6990 #define CCM_PRE_ROOT48_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,48)
6991 #define CCM_ACCESS_CTRL48                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,48)
6992 #define CCM_ACCESS_CTRL_ROOT48_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,48)
6993 #define CCM_ACCESS_CTRL_ROOT48_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,48)
6994 #define CCM_ACCESS_CTRL_ROOT48_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,48)
6995 #define CCM_TARGET_ROOT49                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,49)
6996 #define CCM_TARGET_ROOT49_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,49)
6997 #define CCM_TARGET_ROOT49_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,49)
6998 #define CCM_TARGET_ROOT49_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,49)
6999 #define CCM_MISC49                               CCM_MISC_REG(CCM_BASE_PTR,49)
7000 #define CCM_MISC_ROOT49_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,49)
7001 #define CCM_MISC_ROOT49_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,49)
7002 #define CCM_MISC_ROOT49_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,49)
7003 #define CCM_POST49                               CCM_POST_REG(CCM_BASE_PTR,49)
7004 #define CCM_POST_ROOT49_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,49)
7005 #define CCM_POST_ROOT49_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,49)
7006 #define CCM_POST_ROOT49_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,49)
7007 #define CCM_PRE49                                CCM_PRE_REG(CCM_BASE_PTR,49)
7008 #define CCM_PRE_ROOT49_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,49)
7009 #define CCM_PRE_ROOT49_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,49)
7010 #define CCM_PRE_ROOT49_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,49)
7011 #define CCM_ACCESS_CTRL49                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,49)
7012 #define CCM_ACCESS_CTRL_ROOT49_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,49)
7013 #define CCM_ACCESS_CTRL_ROOT49_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,49)
7014 #define CCM_ACCESS_CTRL_ROOT49_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,49)
7015 #define CCM_TARGET_ROOT50                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,50)
7016 #define CCM_TARGET_ROOT50_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,50)
7017 #define CCM_TARGET_ROOT50_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,50)
7018 #define CCM_TARGET_ROOT50_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,50)
7019 #define CCM_MISC50                               CCM_MISC_REG(CCM_BASE_PTR,50)
7020 #define CCM_MISC_ROOT50_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,50)
7021 #define CCM_MISC_ROOT50_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,50)
7022 #define CCM_MISC_ROOT50_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,50)
7023 #define CCM_POST50                               CCM_POST_REG(CCM_BASE_PTR,50)
7024 #define CCM_POST_ROOT50_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,50)
7025 #define CCM_POST_ROOT50_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,50)
7026 #define CCM_POST_ROOT50_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,50)
7027 #define CCM_PRE50                                CCM_PRE_REG(CCM_BASE_PTR,50)
7028 #define CCM_PRE_ROOT50_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,50)
7029 #define CCM_PRE_ROOT50_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,50)
7030 #define CCM_PRE_ROOT50_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,50)
7031 #define CCM_ACCESS_CTRL50                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,50)
7032 #define CCM_ACCESS_CTRL_ROOT50_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,50)
7033 #define CCM_ACCESS_CTRL_ROOT50_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,50)
7034 #define CCM_ACCESS_CTRL_ROOT50_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,50)
7035 #define CCM_TARGET_ROOT51                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,51)
7036 #define CCM_TARGET_ROOT51_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,51)
7037 #define CCM_TARGET_ROOT51_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,51)
7038 #define CCM_TARGET_ROOT51_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,51)
7039 #define CCM_MISC51                               CCM_MISC_REG(CCM_BASE_PTR,51)
7040 #define CCM_MISC_ROOT51_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,51)
7041 #define CCM_MISC_ROOT51_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,51)
7042 #define CCM_MISC_ROOT51_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,51)
7043 #define CCM_POST51                               CCM_POST_REG(CCM_BASE_PTR,51)
7044 #define CCM_POST_ROOT51_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,51)
7045 #define CCM_POST_ROOT51_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,51)
7046 #define CCM_POST_ROOT51_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,51)
7047 #define CCM_PRE51                                CCM_PRE_REG(CCM_BASE_PTR,51)
7048 #define CCM_PRE_ROOT51_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,51)
7049 #define CCM_PRE_ROOT51_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,51)
7050 #define CCM_PRE_ROOT51_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,51)
7051 #define CCM_ACCESS_CTRL51                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,51)
7052 #define CCM_ACCESS_CTRL_ROOT51_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,51)
7053 #define CCM_ACCESS_CTRL_ROOT51_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,51)
7054 #define CCM_ACCESS_CTRL_ROOT51_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,51)
7055 #define CCM_TARGET_ROOT52                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,52)
7056 #define CCM_TARGET_ROOT52_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,52)
7057 #define CCM_TARGET_ROOT52_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,52)
7058 #define CCM_TARGET_ROOT52_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,52)
7059 #define CCM_MISC52                               CCM_MISC_REG(CCM_BASE_PTR,52)
7060 #define CCM_MISC_ROOT52_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,52)
7061 #define CCM_MISC_ROOT52_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,52)
7062 #define CCM_MISC_ROOT52_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,52)
7063 #define CCM_POST52                               CCM_POST_REG(CCM_BASE_PTR,52)
7064 #define CCM_POST_ROOT52_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,52)
7065 #define CCM_POST_ROOT52_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,52)
7066 #define CCM_POST_ROOT52_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,52)
7067 #define CCM_PRE52                                CCM_PRE_REG(CCM_BASE_PTR,52)
7068 #define CCM_PRE_ROOT52_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,52)
7069 #define CCM_PRE_ROOT52_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,52)
7070 #define CCM_PRE_ROOT52_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,52)
7071 #define CCM_ACCESS_CTRL52                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,52)
7072 #define CCM_ACCESS_CTRL_ROOT52_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,52)
7073 #define CCM_ACCESS_CTRL_ROOT52_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,52)
7074 #define CCM_ACCESS_CTRL_ROOT52_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,52)
7075 #define CCM_TARGET_ROOT53                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,53)
7076 #define CCM_TARGET_ROOT53_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,53)
7077 #define CCM_TARGET_ROOT53_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,53)
7078 #define CCM_TARGET_ROOT53_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,53)
7079 #define CCM_MISC53                               CCM_MISC_REG(CCM_BASE_PTR,53)
7080 #define CCM_MISC_ROOT53_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,53)
7081 #define CCM_MISC_ROOT53_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,53)
7082 #define CCM_MISC_ROOT53_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,53)
7083 #define CCM_POST53                               CCM_POST_REG(CCM_BASE_PTR,53)
7084 #define CCM_POST_ROOT53_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,53)
7085 #define CCM_POST_ROOT53_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,53)
7086 #define CCM_POST_ROOT53_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,53)
7087 #define CCM_PRE53                                CCM_PRE_REG(CCM_BASE_PTR,53)
7088 #define CCM_PRE_ROOT53_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,53)
7089 #define CCM_PRE_ROOT53_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,53)
7090 #define CCM_PRE_ROOT53_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,53)
7091 #define CCM_ACCESS_CTRL53                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,53)
7092 #define CCM_ACCESS_CTRL_ROOT53_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,53)
7093 #define CCM_ACCESS_CTRL_ROOT53_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,53)
7094 #define CCM_ACCESS_CTRL_ROOT53_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,53)
7095 #define CCM_TARGET_ROOT54                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,54)
7096 #define CCM_TARGET_ROOT54_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,54)
7097 #define CCM_TARGET_ROOT54_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,54)
7098 #define CCM_TARGET_ROOT54_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,54)
7099 #define CCM_MISC54                               CCM_MISC_REG(CCM_BASE_PTR,54)
7100 #define CCM_MISC_ROOT54_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,54)
7101 #define CCM_MISC_ROOT54_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,54)
7102 #define CCM_MISC_ROOT54_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,54)
7103 #define CCM_POST54                               CCM_POST_REG(CCM_BASE_PTR,54)
7104 #define CCM_POST_ROOT54_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,54)
7105 #define CCM_POST_ROOT54_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,54)
7106 #define CCM_POST_ROOT54_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,54)
7107 #define CCM_PRE54                                CCM_PRE_REG(CCM_BASE_PTR,54)
7108 #define CCM_PRE_ROOT54_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,54)
7109 #define CCM_PRE_ROOT54_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,54)
7110 #define CCM_PRE_ROOT54_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,54)
7111 #define CCM_ACCESS_CTRL54                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,54)
7112 #define CCM_ACCESS_CTRL_ROOT54_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,54)
7113 #define CCM_ACCESS_CTRL_ROOT54_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,54)
7114 #define CCM_ACCESS_CTRL_ROOT54_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,54)
7115 #define CCM_TARGET_ROOT55                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,55)
7116 #define CCM_TARGET_ROOT55_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,55)
7117 #define CCM_TARGET_ROOT55_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,55)
7118 #define CCM_TARGET_ROOT55_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,55)
7119 #define CCM_MISC55                               CCM_MISC_REG(CCM_BASE_PTR,55)
7120 #define CCM_MISC_ROOT55_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,55)
7121 #define CCM_MISC_ROOT55_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,55)
7122 #define CCM_MISC_ROOT55_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,55)
7123 #define CCM_POST55                               CCM_POST_REG(CCM_BASE_PTR,55)
7124 #define CCM_POST_ROOT55_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,55)
7125 #define CCM_POST_ROOT55_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,55)
7126 #define CCM_POST_ROOT55_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,55)
7127 #define CCM_PRE55                                CCM_PRE_REG(CCM_BASE_PTR,55)
7128 #define CCM_PRE_ROOT55_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,55)
7129 #define CCM_PRE_ROOT55_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,55)
7130 #define CCM_PRE_ROOT55_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,55)
7131 #define CCM_ACCESS_CTRL55                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,55)
7132 #define CCM_ACCESS_CTRL_ROOT55_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,55)
7133 #define CCM_ACCESS_CTRL_ROOT55_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,55)
7134 #define CCM_ACCESS_CTRL_ROOT55_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,55)
7135 #define CCM_TARGET_ROOT56                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,56)
7136 #define CCM_TARGET_ROOT56_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,56)
7137 #define CCM_TARGET_ROOT56_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,56)
7138 #define CCM_TARGET_ROOT56_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,56)
7139 #define CCM_MISC56                               CCM_MISC_REG(CCM_BASE_PTR,56)
7140 #define CCM_MISC_ROOT56_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,56)
7141 #define CCM_MISC_ROOT56_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,56)
7142 #define CCM_MISC_ROOT56_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,56)
7143 #define CCM_POST56                               CCM_POST_REG(CCM_BASE_PTR,56)
7144 #define CCM_POST_ROOT56_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,56)
7145 #define CCM_POST_ROOT56_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,56)
7146 #define CCM_POST_ROOT56_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,56)
7147 #define CCM_PRE56                                CCM_PRE_REG(CCM_BASE_PTR,56)
7148 #define CCM_PRE_ROOT56_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,56)
7149 #define CCM_PRE_ROOT56_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,56)
7150 #define CCM_PRE_ROOT56_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,56)
7151 #define CCM_ACCESS_CTRL56                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,56)
7152 #define CCM_ACCESS_CTRL_ROOT56_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,56)
7153 #define CCM_ACCESS_CTRL_ROOT56_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,56)
7154 #define CCM_ACCESS_CTRL_ROOT56_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,56)
7155 #define CCM_TARGET_ROOT57                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,57)
7156 #define CCM_TARGET_ROOT57_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,57)
7157 #define CCM_TARGET_ROOT57_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,57)
7158 #define CCM_TARGET_ROOT57_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,57)
7159 #define CCM_MISC57                               CCM_MISC_REG(CCM_BASE_PTR,57)
7160 #define CCM_MISC_ROOT57_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,57)
7161 #define CCM_MISC_ROOT57_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,57)
7162 #define CCM_MISC_ROOT57_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,57)
7163 #define CCM_POST57                               CCM_POST_REG(CCM_BASE_PTR,57)
7164 #define CCM_POST_ROOT57_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,57)
7165 #define CCM_POST_ROOT57_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,57)
7166 #define CCM_POST_ROOT57_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,57)
7167 #define CCM_PRE57                                CCM_PRE_REG(CCM_BASE_PTR,57)
7168 #define CCM_PRE_ROOT57_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,57)
7169 #define CCM_PRE_ROOT57_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,57)
7170 #define CCM_PRE_ROOT57_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,57)
7171 #define CCM_ACCESS_CTRL57                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,57)
7172 #define CCM_ACCESS_CTRL_ROOT57_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,57)
7173 #define CCM_ACCESS_CTRL_ROOT57_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,57)
7174 #define CCM_ACCESS_CTRL_ROOT57_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,57)
7175 #define CCM_TARGET_ROOT58                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,58)
7176 #define CCM_TARGET_ROOT58_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,58)
7177 #define CCM_TARGET_ROOT58_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,58)
7178 #define CCM_TARGET_ROOT58_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,58)
7179 #define CCM_MISC58                               CCM_MISC_REG(CCM_BASE_PTR,58)
7180 #define CCM_MISC_ROOT58_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,58)
7181 #define CCM_MISC_ROOT58_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,58)
7182 #define CCM_MISC_ROOT58_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,58)
7183 #define CCM_POST58                               CCM_POST_REG(CCM_BASE_PTR,58)
7184 #define CCM_POST_ROOT58_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,58)
7185 #define CCM_POST_ROOT58_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,58)
7186 #define CCM_POST_ROOT58_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,58)
7187 #define CCM_PRE58                                CCM_PRE_REG(CCM_BASE_PTR,58)
7188 #define CCM_PRE_ROOT58_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,58)
7189 #define CCM_PRE_ROOT58_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,58)
7190 #define CCM_PRE_ROOT58_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,58)
7191 #define CCM_ACCESS_CTRL58                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,58)
7192 #define CCM_ACCESS_CTRL_ROOT58_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,58)
7193 #define CCM_ACCESS_CTRL_ROOT58_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,58)
7194 #define CCM_ACCESS_CTRL_ROOT58_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,58)
7195 #define CCM_TARGET_ROOT59                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,59)
7196 #define CCM_TARGET_ROOT59_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,59)
7197 #define CCM_TARGET_ROOT59_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,59)
7198 #define CCM_TARGET_ROOT59_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,59)
7199 #define CCM_MISC59                               CCM_MISC_REG(CCM_BASE_PTR,59)
7200 #define CCM_MISC_ROOT59_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,59)
7201 #define CCM_MISC_ROOT59_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,59)
7202 #define CCM_MISC_ROOT59_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,59)
7203 #define CCM_POST59                               CCM_POST_REG(CCM_BASE_PTR,59)
7204 #define CCM_POST_ROOT59_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,59)
7205 #define CCM_POST_ROOT59_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,59)
7206 #define CCM_POST_ROOT59_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,59)
7207 #define CCM_PRE59                                CCM_PRE_REG(CCM_BASE_PTR,59)
7208 #define CCM_PRE_ROOT59_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,59)
7209 #define CCM_PRE_ROOT59_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,59)
7210 #define CCM_PRE_ROOT59_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,59)
7211 #define CCM_ACCESS_CTRL59                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,59)
7212 #define CCM_ACCESS_CTRL_ROOT59_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,59)
7213 #define CCM_ACCESS_CTRL_ROOT59_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,59)
7214 #define CCM_ACCESS_CTRL_ROOT59_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,59)
7215 #define CCM_TARGET_ROOT60                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,60)
7216 #define CCM_TARGET_ROOT60_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,60)
7217 #define CCM_TARGET_ROOT60_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,60)
7218 #define CCM_TARGET_ROOT60_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,60)
7219 #define CCM_MISC60                               CCM_MISC_REG(CCM_BASE_PTR,60)
7220 #define CCM_MISC_ROOT60_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,60)
7221 #define CCM_MISC_ROOT60_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,60)
7222 #define CCM_MISC_ROOT60_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,60)
7223 #define CCM_POST60                               CCM_POST_REG(CCM_BASE_PTR,60)
7224 #define CCM_POST_ROOT60_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,60)
7225 #define CCM_POST_ROOT60_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,60)
7226 #define CCM_POST_ROOT60_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,60)
7227 #define CCM_PRE60                                CCM_PRE_REG(CCM_BASE_PTR,60)
7228 #define CCM_PRE_ROOT60_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,60)
7229 #define CCM_PRE_ROOT60_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,60)
7230 #define CCM_PRE_ROOT60_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,60)
7231 #define CCM_ACCESS_CTRL60                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,60)
7232 #define CCM_ACCESS_CTRL_ROOT60_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,60)
7233 #define CCM_ACCESS_CTRL_ROOT60_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,60)
7234 #define CCM_ACCESS_CTRL_ROOT60_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,60)
7235 #define CCM_TARGET_ROOT61                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,61)
7236 #define CCM_TARGET_ROOT61_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,61)
7237 #define CCM_TARGET_ROOT61_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,61)
7238 #define CCM_TARGET_ROOT61_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,61)
7239 #define CCM_MISC61                               CCM_MISC_REG(CCM_BASE_PTR,61)
7240 #define CCM_MISC_ROOT61_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,61)
7241 #define CCM_MISC_ROOT61_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,61)
7242 #define CCM_MISC_ROOT61_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,61)
7243 #define CCM_POST61                               CCM_POST_REG(CCM_BASE_PTR,61)
7244 #define CCM_POST_ROOT61_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,61)
7245 #define CCM_POST_ROOT61_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,61)
7246 #define CCM_POST_ROOT61_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,61)
7247 #define CCM_PRE61                                CCM_PRE_REG(CCM_BASE_PTR,61)
7248 #define CCM_PRE_ROOT61_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,61)
7249 #define CCM_PRE_ROOT61_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,61)
7250 #define CCM_PRE_ROOT61_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,61)
7251 #define CCM_ACCESS_CTRL61                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,61)
7252 #define CCM_ACCESS_CTRL_ROOT61_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,61)
7253 #define CCM_ACCESS_CTRL_ROOT61_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,61)
7254 #define CCM_ACCESS_CTRL_ROOT61_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,61)
7255 #define CCM_TARGET_ROOT62                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,62)
7256 #define CCM_TARGET_ROOT62_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,62)
7257 #define CCM_TARGET_ROOT62_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,62)
7258 #define CCM_TARGET_ROOT62_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,62)
7259 #define CCM_MISC62                               CCM_MISC_REG(CCM_BASE_PTR,62)
7260 #define CCM_MISC_ROOT62_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,62)
7261 #define CCM_MISC_ROOT62_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,62)
7262 #define CCM_MISC_ROOT62_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,62)
7263 #define CCM_POST62                               CCM_POST_REG(CCM_BASE_PTR,62)
7264 #define CCM_POST_ROOT62_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,62)
7265 #define CCM_POST_ROOT62_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,62)
7266 #define CCM_POST_ROOT62_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,62)
7267 #define CCM_PRE62                                CCM_PRE_REG(CCM_BASE_PTR,62)
7268 #define CCM_PRE_ROOT62_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,62)
7269 #define CCM_PRE_ROOT62_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,62)
7270 #define CCM_PRE_ROOT62_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,62)
7271 #define CCM_ACCESS_CTRL62                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,62)
7272 #define CCM_ACCESS_CTRL_ROOT62_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,62)
7273 #define CCM_ACCESS_CTRL_ROOT62_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,62)
7274 #define CCM_ACCESS_CTRL_ROOT62_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,62)
7275 #define CCM_TARGET_ROOT63                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,63)
7276 #define CCM_TARGET_ROOT63_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,63)
7277 #define CCM_TARGET_ROOT63_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,63)
7278 #define CCM_TARGET_ROOT63_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,63)
7279 #define CCM_MISC63                               CCM_MISC_REG(CCM_BASE_PTR,63)
7280 #define CCM_MISC_ROOT63_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,63)
7281 #define CCM_MISC_ROOT63_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,63)
7282 #define CCM_MISC_ROOT63_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,63)
7283 #define CCM_POST63                               CCM_POST_REG(CCM_BASE_PTR,63)
7284 #define CCM_POST_ROOT63_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,63)
7285 #define CCM_POST_ROOT63_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,63)
7286 #define CCM_POST_ROOT63_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,63)
7287 #define CCM_PRE63                                CCM_PRE_REG(CCM_BASE_PTR,63)
7288 #define CCM_PRE_ROOT63_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,63)
7289 #define CCM_PRE_ROOT63_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,63)
7290 #define CCM_PRE_ROOT63_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,63)
7291 #define CCM_ACCESS_CTRL63                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,63)
7292 #define CCM_ACCESS_CTRL_ROOT63_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,63)
7293 #define CCM_ACCESS_CTRL_ROOT63_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,63)
7294 #define CCM_ACCESS_CTRL_ROOT63_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,63)
7295 #define CCM_TARGET_ROOT64                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,64)
7296 #define CCM_TARGET_ROOT64_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,64)
7297 #define CCM_TARGET_ROOT64_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,64)
7298 #define CCM_TARGET_ROOT64_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,64)
7299 #define CCM_MISC64                               CCM_MISC_REG(CCM_BASE_PTR,64)
7300 #define CCM_MISC_ROOT64_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,64)
7301 #define CCM_MISC_ROOT64_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,64)
7302 #define CCM_MISC_ROOT64_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,64)
7303 #define CCM_POST64                               CCM_POST_REG(CCM_BASE_PTR,64)
7304 #define CCM_POST_ROOT64_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,64)
7305 #define CCM_POST_ROOT64_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,64)
7306 #define CCM_POST_ROOT64_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,64)
7307 #define CCM_PRE64                                CCM_PRE_REG(CCM_BASE_PTR,64)
7308 #define CCM_PRE_ROOT64_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,64)
7309 #define CCM_PRE_ROOT64_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,64)
7310 #define CCM_PRE_ROOT64_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,64)
7311 #define CCM_ACCESS_CTRL64                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,64)
7312 #define CCM_ACCESS_CTRL_ROOT64_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,64)
7313 #define CCM_ACCESS_CTRL_ROOT64_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,64)
7314 #define CCM_ACCESS_CTRL_ROOT64_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,64)
7315 #define CCM_TARGET_ROOT65                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,65)
7316 #define CCM_TARGET_ROOT65_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,65)
7317 #define CCM_TARGET_ROOT65_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,65)
7318 #define CCM_TARGET_ROOT65_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,65)
7319 #define CCM_MISC65                               CCM_MISC_REG(CCM_BASE_PTR,65)
7320 #define CCM_MISC_ROOT65_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,65)
7321 #define CCM_MISC_ROOT65_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,65)
7322 #define CCM_MISC_ROOT65_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,65)
7323 #define CCM_POST65                               CCM_POST_REG(CCM_BASE_PTR,65)
7324 #define CCM_POST_ROOT65_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,65)
7325 #define CCM_POST_ROOT65_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,65)
7326 #define CCM_POST_ROOT65_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,65)
7327 #define CCM_PRE65                                CCM_PRE_REG(CCM_BASE_PTR,65)
7328 #define CCM_PRE_ROOT65_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,65)
7329 #define CCM_PRE_ROOT65_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,65)
7330 #define CCM_PRE_ROOT65_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,65)
7331 #define CCM_ACCESS_CTRL65                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,65)
7332 #define CCM_ACCESS_CTRL_ROOT65_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,65)
7333 #define CCM_ACCESS_CTRL_ROOT65_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,65)
7334 #define CCM_ACCESS_CTRL_ROOT65_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,65)
7335 #define CCM_TARGET_ROOT66                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,66)
7336 #define CCM_TARGET_ROOT66_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,66)
7337 #define CCM_TARGET_ROOT66_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,66)
7338 #define CCM_TARGET_ROOT66_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,66)
7339 #define CCM_MISC66                               CCM_MISC_REG(CCM_BASE_PTR,66)
7340 #define CCM_MISC_ROOT66_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,66)
7341 #define CCM_MISC_ROOT66_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,66)
7342 #define CCM_MISC_ROOT66_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,66)
7343 #define CCM_POST66                               CCM_POST_REG(CCM_BASE_PTR,66)
7344 #define CCM_POST_ROOT66_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,66)
7345 #define CCM_POST_ROOT66_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,66)
7346 #define CCM_POST_ROOT66_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,66)
7347 #define CCM_PRE66                                CCM_PRE_REG(CCM_BASE_PTR,66)
7348 #define CCM_PRE_ROOT66_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,66)
7349 #define CCM_PRE_ROOT66_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,66)
7350 #define CCM_PRE_ROOT66_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,66)
7351 #define CCM_ACCESS_CTRL66                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,66)
7352 #define CCM_ACCESS_CTRL_ROOT66_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,66)
7353 #define CCM_ACCESS_CTRL_ROOT66_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,66)
7354 #define CCM_ACCESS_CTRL_ROOT66_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,66)
7355 #define CCM_TARGET_ROOT67                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,67)
7356 #define CCM_TARGET_ROOT67_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,67)
7357 #define CCM_TARGET_ROOT67_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,67)
7358 #define CCM_TARGET_ROOT67_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,67)
7359 #define CCM_MISC67                               CCM_MISC_REG(CCM_BASE_PTR,67)
7360 #define CCM_MISC_ROOT67_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,67)
7361 #define CCM_MISC_ROOT67_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,67)
7362 #define CCM_MISC_ROOT67_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,67)
7363 #define CCM_POST67                               CCM_POST_REG(CCM_BASE_PTR,67)
7364 #define CCM_POST_ROOT67_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,67)
7365 #define CCM_POST_ROOT67_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,67)
7366 #define CCM_POST_ROOT67_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,67)
7367 #define CCM_PRE67                                CCM_PRE_REG(CCM_BASE_PTR,67)
7368 #define CCM_PRE_ROOT67_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,67)
7369 #define CCM_PRE_ROOT67_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,67)
7370 #define CCM_PRE_ROOT67_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,67)
7371 #define CCM_ACCESS_CTRL67                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,67)
7372 #define CCM_ACCESS_CTRL_ROOT67_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,67)
7373 #define CCM_ACCESS_CTRL_ROOT67_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,67)
7374 #define CCM_ACCESS_CTRL_ROOT67_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,67)
7375 #define CCM_TARGET_ROOT68                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,68)
7376 #define CCM_TARGET_ROOT68_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,68)
7377 #define CCM_TARGET_ROOT68_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,68)
7378 #define CCM_TARGET_ROOT68_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,68)
7379 #define CCM_MISC68                               CCM_MISC_REG(CCM_BASE_PTR,68)
7380 #define CCM_MISC_ROOT68_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,68)
7381 #define CCM_MISC_ROOT68_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,68)
7382 #define CCM_MISC_ROOT68_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,68)
7383 #define CCM_POST68                               CCM_POST_REG(CCM_BASE_PTR,68)
7384 #define CCM_POST_ROOT68_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,68)
7385 #define CCM_POST_ROOT68_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,68)
7386 #define CCM_POST_ROOT68_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,68)
7387 #define CCM_PRE68                                CCM_PRE_REG(CCM_BASE_PTR,68)
7388 #define CCM_PRE_ROOT68_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,68)
7389 #define CCM_PRE_ROOT68_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,68)
7390 #define CCM_PRE_ROOT68_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,68)
7391 #define CCM_ACCESS_CTRL68                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,68)
7392 #define CCM_ACCESS_CTRL_ROOT68_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,68)
7393 #define CCM_ACCESS_CTRL_ROOT68_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,68)
7394 #define CCM_ACCESS_CTRL_ROOT68_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,68)
7395 #define CCM_TARGET_ROOT69                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,69)
7396 #define CCM_TARGET_ROOT69_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,69)
7397 #define CCM_TARGET_ROOT69_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,69)
7398 #define CCM_TARGET_ROOT69_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,69)
7399 #define CCM_MISC69                               CCM_MISC_REG(CCM_BASE_PTR,69)
7400 #define CCM_MISC_ROOT69_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,69)
7401 #define CCM_MISC_ROOT69_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,69)
7402 #define CCM_MISC_ROOT69_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,69)
7403 #define CCM_POST69                               CCM_POST_REG(CCM_BASE_PTR,69)
7404 #define CCM_POST_ROOT69_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,69)
7405 #define CCM_POST_ROOT69_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,69)
7406 #define CCM_POST_ROOT69_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,69)
7407 #define CCM_PRE69                                CCM_PRE_REG(CCM_BASE_PTR,69)
7408 #define CCM_PRE_ROOT69_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,69)
7409 #define CCM_PRE_ROOT69_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,69)
7410 #define CCM_PRE_ROOT69_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,69)
7411 #define CCM_ACCESS_CTRL69                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,69)
7412 #define CCM_ACCESS_CTRL_ROOT69_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,69)
7413 #define CCM_ACCESS_CTRL_ROOT69_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,69)
7414 #define CCM_ACCESS_CTRL_ROOT69_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,69)
7415 #define CCM_TARGET_ROOT70                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,70)
7416 #define CCM_TARGET_ROOT70_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,70)
7417 #define CCM_TARGET_ROOT70_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,70)
7418 #define CCM_TARGET_ROOT70_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,70)
7419 #define CCM_MISC70                               CCM_MISC_REG(CCM_BASE_PTR,70)
7420 #define CCM_MISC_ROOT70_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,70)
7421 #define CCM_MISC_ROOT70_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,70)
7422 #define CCM_MISC_ROOT70_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,70)
7423 #define CCM_POST70                               CCM_POST_REG(CCM_BASE_PTR,70)
7424 #define CCM_POST_ROOT70_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,70)
7425 #define CCM_POST_ROOT70_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,70)
7426 #define CCM_POST_ROOT70_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,70)
7427 #define CCM_PRE70                                CCM_PRE_REG(CCM_BASE_PTR,70)
7428 #define CCM_PRE_ROOT70_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,70)
7429 #define CCM_PRE_ROOT70_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,70)
7430 #define CCM_PRE_ROOT70_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,70)
7431 #define CCM_ACCESS_CTRL70                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,70)
7432 #define CCM_ACCESS_CTRL_ROOT70_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,70)
7433 #define CCM_ACCESS_CTRL_ROOT70_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,70)
7434 #define CCM_ACCESS_CTRL_ROOT70_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,70)
7435 #define CCM_TARGET_ROOT71                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,71)
7436 #define CCM_TARGET_ROOT71_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,71)
7437 #define CCM_TARGET_ROOT71_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,71)
7438 #define CCM_TARGET_ROOT71_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,71)
7439 #define CCM_MISC71                               CCM_MISC_REG(CCM_BASE_PTR,71)
7440 #define CCM_MISC_ROOT71_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,71)
7441 #define CCM_MISC_ROOT71_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,71)
7442 #define CCM_MISC_ROOT71_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,71)
7443 #define CCM_POST71                               CCM_POST_REG(CCM_BASE_PTR,71)
7444 #define CCM_POST_ROOT71_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,71)
7445 #define CCM_POST_ROOT71_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,71)
7446 #define CCM_POST_ROOT71_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,71)
7447 #define CCM_PRE71                                CCM_PRE_REG(CCM_BASE_PTR,71)
7448 #define CCM_PRE_ROOT71_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,71)
7449 #define CCM_PRE_ROOT71_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,71)
7450 #define CCM_PRE_ROOT71_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,71)
7451 #define CCM_ACCESS_CTRL71                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,71)
7452 #define CCM_ACCESS_CTRL_ROOT71_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,71)
7453 #define CCM_ACCESS_CTRL_ROOT71_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,71)
7454 #define CCM_ACCESS_CTRL_ROOT71_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,71)
7455 #define CCM_TARGET_ROOT72                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,72)
7456 #define CCM_TARGET_ROOT72_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,72)
7457 #define CCM_TARGET_ROOT72_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,72)
7458 #define CCM_TARGET_ROOT72_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,72)
7459 #define CCM_MISC72                               CCM_MISC_REG(CCM_BASE_PTR,72)
7460 #define CCM_MISC_ROOT72_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,72)
7461 #define CCM_MISC_ROOT72_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,72)
7462 #define CCM_MISC_ROOT72_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,72)
7463 #define CCM_POST72                               CCM_POST_REG(CCM_BASE_PTR,72)
7464 #define CCM_POST_ROOT72_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,72)
7465 #define CCM_POST_ROOT72_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,72)
7466 #define CCM_POST_ROOT72_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,72)
7467 #define CCM_PRE72                                CCM_PRE_REG(CCM_BASE_PTR,72)
7468 #define CCM_PRE_ROOT72_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,72)
7469 #define CCM_PRE_ROOT72_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,72)
7470 #define CCM_PRE_ROOT72_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,72)
7471 #define CCM_ACCESS_CTRL72                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,72)
7472 #define CCM_ACCESS_CTRL_ROOT72_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,72)
7473 #define CCM_ACCESS_CTRL_ROOT72_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,72)
7474 #define CCM_ACCESS_CTRL_ROOT72_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,72)
7475 #define CCM_TARGET_ROOT73                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,73)
7476 #define CCM_TARGET_ROOT73_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,73)
7477 #define CCM_TARGET_ROOT73_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,73)
7478 #define CCM_TARGET_ROOT73_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,73)
7479 #define CCM_MISC73                               CCM_MISC_REG(CCM_BASE_PTR,73)
7480 #define CCM_MISC_ROOT73_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,73)
7481 #define CCM_MISC_ROOT73_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,73)
7482 #define CCM_MISC_ROOT73_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,73)
7483 #define CCM_POST73                               CCM_POST_REG(CCM_BASE_PTR,73)
7484 #define CCM_POST_ROOT73_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,73)
7485 #define CCM_POST_ROOT73_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,73)
7486 #define CCM_POST_ROOT73_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,73)
7487 #define CCM_PRE73                                CCM_PRE_REG(CCM_BASE_PTR,73)
7488 #define CCM_PRE_ROOT73_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,73)
7489 #define CCM_PRE_ROOT73_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,73)
7490 #define CCM_PRE_ROOT73_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,73)
7491 #define CCM_ACCESS_CTRL73                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,73)
7492 #define CCM_ACCESS_CTRL_ROOT73_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,73)
7493 #define CCM_ACCESS_CTRL_ROOT73_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,73)
7494 #define CCM_ACCESS_CTRL_ROOT73_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,73)
7495 #define CCM_TARGET_ROOT74                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,74)
7496 #define CCM_TARGET_ROOT74_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,74)
7497 #define CCM_TARGET_ROOT74_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,74)
7498 #define CCM_TARGET_ROOT74_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,74)
7499 #define CCM_MISC74                               CCM_MISC_REG(CCM_BASE_PTR,74)
7500 #define CCM_MISC_ROOT74_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,74)
7501 #define CCM_MISC_ROOT74_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,74)
7502 #define CCM_MISC_ROOT74_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,74)
7503 #define CCM_POST74                               CCM_POST_REG(CCM_BASE_PTR,74)
7504 #define CCM_POST_ROOT74_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,74)
7505 #define CCM_POST_ROOT74_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,74)
7506 #define CCM_POST_ROOT74_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,74)
7507 #define CCM_PRE74                                CCM_PRE_REG(CCM_BASE_PTR,74)
7508 #define CCM_PRE_ROOT74_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,74)
7509 #define CCM_PRE_ROOT74_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,74)
7510 #define CCM_PRE_ROOT74_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,74)
7511 #define CCM_ACCESS_CTRL74                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,74)
7512 #define CCM_ACCESS_CTRL_ROOT74_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,74)
7513 #define CCM_ACCESS_CTRL_ROOT74_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,74)
7514 #define CCM_ACCESS_CTRL_ROOT74_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,74)
7515 #define CCM_TARGET_ROOT75                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,75)
7516 #define CCM_TARGET_ROOT75_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,75)
7517 #define CCM_TARGET_ROOT75_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,75)
7518 #define CCM_TARGET_ROOT75_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,75)
7519 #define CCM_MISC75                               CCM_MISC_REG(CCM_BASE_PTR,75)
7520 #define CCM_MISC_ROOT75_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,75)
7521 #define CCM_MISC_ROOT75_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,75)
7522 #define CCM_MISC_ROOT75_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,75)
7523 #define CCM_POST75                               CCM_POST_REG(CCM_BASE_PTR,75)
7524 #define CCM_POST_ROOT75_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,75)
7525 #define CCM_POST_ROOT75_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,75)
7526 #define CCM_POST_ROOT75_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,75)
7527 #define CCM_PRE75                                CCM_PRE_REG(CCM_BASE_PTR,75)
7528 #define CCM_PRE_ROOT75_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,75)
7529 #define CCM_PRE_ROOT75_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,75)
7530 #define CCM_PRE_ROOT75_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,75)
7531 #define CCM_ACCESS_CTRL75                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,75)
7532 #define CCM_ACCESS_CTRL_ROOT75_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,75)
7533 #define CCM_ACCESS_CTRL_ROOT75_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,75)
7534 #define CCM_ACCESS_CTRL_ROOT75_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,75)
7535 #define CCM_TARGET_ROOT76                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,76)
7536 #define CCM_TARGET_ROOT76_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,76)
7537 #define CCM_TARGET_ROOT76_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,76)
7538 #define CCM_TARGET_ROOT76_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,76)
7539 #define CCM_MISC76                               CCM_MISC_REG(CCM_BASE_PTR,76)
7540 #define CCM_MISC_ROOT76_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,76)
7541 #define CCM_MISC_ROOT76_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,76)
7542 #define CCM_MISC_ROOT76_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,76)
7543 #define CCM_POST76                               CCM_POST_REG(CCM_BASE_PTR,76)
7544 #define CCM_POST_ROOT76_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,76)
7545 #define CCM_POST_ROOT76_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,76)
7546 #define CCM_POST_ROOT76_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,76)
7547 #define CCM_PRE76                                CCM_PRE_REG(CCM_BASE_PTR,76)
7548 #define CCM_PRE_ROOT76_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,76)
7549 #define CCM_PRE_ROOT76_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,76)
7550 #define CCM_PRE_ROOT76_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,76)
7551 #define CCM_ACCESS_CTRL76                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,76)
7552 #define CCM_ACCESS_CTRL_ROOT76_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,76)
7553 #define CCM_ACCESS_CTRL_ROOT76_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,76)
7554 #define CCM_ACCESS_CTRL_ROOT76_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,76)
7555 #define CCM_TARGET_ROOT77                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,77)
7556 #define CCM_TARGET_ROOT77_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,77)
7557 #define CCM_TARGET_ROOT77_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,77)
7558 #define CCM_TARGET_ROOT77_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,77)
7559 #define CCM_MISC77                               CCM_MISC_REG(CCM_BASE_PTR,77)
7560 #define CCM_MISC_ROOT77_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,77)
7561 #define CCM_MISC_ROOT77_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,77)
7562 #define CCM_MISC_ROOT77_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,77)
7563 #define CCM_POST77                               CCM_POST_REG(CCM_BASE_PTR,77)
7564 #define CCM_POST_ROOT77_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,77)
7565 #define CCM_POST_ROOT77_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,77)
7566 #define CCM_POST_ROOT77_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,77)
7567 #define CCM_PRE77                                CCM_PRE_REG(CCM_BASE_PTR,77)
7568 #define CCM_PRE_ROOT77_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,77)
7569 #define CCM_PRE_ROOT77_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,77)
7570 #define CCM_PRE_ROOT77_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,77)
7571 #define CCM_ACCESS_CTRL77                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,77)
7572 #define CCM_ACCESS_CTRL_ROOT77_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,77)
7573 #define CCM_ACCESS_CTRL_ROOT77_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,77)
7574 #define CCM_ACCESS_CTRL_ROOT77_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,77)
7575 #define CCM_TARGET_ROOT78                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,78)
7576 #define CCM_TARGET_ROOT78_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,78)
7577 #define CCM_TARGET_ROOT78_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,78)
7578 #define CCM_TARGET_ROOT78_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,78)
7579 #define CCM_MISC78                               CCM_MISC_REG(CCM_BASE_PTR,78)
7580 #define CCM_MISC_ROOT78_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,78)
7581 #define CCM_MISC_ROOT78_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,78)
7582 #define CCM_MISC_ROOT78_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,78)
7583 #define CCM_POST78                               CCM_POST_REG(CCM_BASE_PTR,78)
7584 #define CCM_POST_ROOT78_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,78)
7585 #define CCM_POST_ROOT78_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,78)
7586 #define CCM_POST_ROOT78_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,78)
7587 #define CCM_PRE78                                CCM_PRE_REG(CCM_BASE_PTR,78)
7588 #define CCM_PRE_ROOT78_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,78)
7589 #define CCM_PRE_ROOT78_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,78)
7590 #define CCM_PRE_ROOT78_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,78)
7591 #define CCM_ACCESS_CTRL78                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,78)
7592 #define CCM_ACCESS_CTRL_ROOT78_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,78)
7593 #define CCM_ACCESS_CTRL_ROOT78_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,78)
7594 #define CCM_ACCESS_CTRL_ROOT78_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,78)
7595 #define CCM_TARGET_ROOT79                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,79)
7596 #define CCM_TARGET_ROOT79_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,79)
7597 #define CCM_TARGET_ROOT79_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,79)
7598 #define CCM_TARGET_ROOT79_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,79)
7599 #define CCM_MISC79                               CCM_MISC_REG(CCM_BASE_PTR,79)
7600 #define CCM_MISC_ROOT79_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,79)
7601 #define CCM_MISC_ROOT79_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,79)
7602 #define CCM_MISC_ROOT79_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,79)
7603 #define CCM_POST79                               CCM_POST_REG(CCM_BASE_PTR,79)
7604 #define CCM_POST_ROOT79_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,79)
7605 #define CCM_POST_ROOT79_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,79)
7606 #define CCM_POST_ROOT79_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,79)
7607 #define CCM_PRE79                                CCM_PRE_REG(CCM_BASE_PTR,79)
7608 #define CCM_PRE_ROOT79_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,79)
7609 #define CCM_PRE_ROOT79_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,79)
7610 #define CCM_PRE_ROOT79_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,79)
7611 #define CCM_ACCESS_CTRL79                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,79)
7612 #define CCM_ACCESS_CTRL_ROOT79_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,79)
7613 #define CCM_ACCESS_CTRL_ROOT79_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,79)
7614 #define CCM_ACCESS_CTRL_ROOT79_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,79)
7615 #define CCM_TARGET_ROOT80                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,80)
7616 #define CCM_TARGET_ROOT80_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,80)
7617 #define CCM_TARGET_ROOT80_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,80)
7618 #define CCM_TARGET_ROOT80_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,80)
7619 #define CCM_MISC80                               CCM_MISC_REG(CCM_BASE_PTR,80)
7620 #define CCM_MISC_ROOT80_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,80)
7621 #define CCM_MISC_ROOT80_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,80)
7622 #define CCM_MISC_ROOT80_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,80)
7623 #define CCM_POST80                               CCM_POST_REG(CCM_BASE_PTR,80)
7624 #define CCM_POST_ROOT80_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,80)
7625 #define CCM_POST_ROOT80_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,80)
7626 #define CCM_POST_ROOT80_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,80)
7627 #define CCM_PRE80                                CCM_PRE_REG(CCM_BASE_PTR,80)
7628 #define CCM_PRE_ROOT80_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,80)
7629 #define CCM_PRE_ROOT80_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,80)
7630 #define CCM_PRE_ROOT80_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,80)
7631 #define CCM_ACCESS_CTRL80                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,80)
7632 #define CCM_ACCESS_CTRL_ROOT80_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,80)
7633 #define CCM_ACCESS_CTRL_ROOT80_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,80)
7634 #define CCM_ACCESS_CTRL_ROOT80_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,80)
7635 #define CCM_TARGET_ROOT81                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,81)
7636 #define CCM_TARGET_ROOT81_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,81)
7637 #define CCM_TARGET_ROOT81_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,81)
7638 #define CCM_TARGET_ROOT81_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,81)
7639 #define CCM_MISC81                               CCM_MISC_REG(CCM_BASE_PTR,81)
7640 #define CCM_MISC_ROOT81_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,81)
7641 #define CCM_MISC_ROOT81_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,81)
7642 #define CCM_MISC_ROOT81_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,81)
7643 #define CCM_POST81                               CCM_POST_REG(CCM_BASE_PTR,81)
7644 #define CCM_POST_ROOT81_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,81)
7645 #define CCM_POST_ROOT81_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,81)
7646 #define CCM_POST_ROOT81_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,81)
7647 #define CCM_PRE81                                CCM_PRE_REG(CCM_BASE_PTR,81)
7648 #define CCM_PRE_ROOT81_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,81)
7649 #define CCM_PRE_ROOT81_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,81)
7650 #define CCM_PRE_ROOT81_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,81)
7651 #define CCM_ACCESS_CTRL81                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,81)
7652 #define CCM_ACCESS_CTRL_ROOT81_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,81)
7653 #define CCM_ACCESS_CTRL_ROOT81_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,81)
7654 #define CCM_ACCESS_CTRL_ROOT81_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,81)
7655 #define CCM_TARGET_ROOT82                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,82)
7656 #define CCM_TARGET_ROOT82_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,82)
7657 #define CCM_TARGET_ROOT82_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,82)
7658 #define CCM_TARGET_ROOT82_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,82)
7659 #define CCM_MISC82                               CCM_MISC_REG(CCM_BASE_PTR,82)
7660 #define CCM_MISC_ROOT82_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,82)
7661 #define CCM_MISC_ROOT82_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,82)
7662 #define CCM_MISC_ROOT82_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,82)
7663 #define CCM_POST82                               CCM_POST_REG(CCM_BASE_PTR,82)
7664 #define CCM_POST_ROOT82_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,82)
7665 #define CCM_POST_ROOT82_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,82)
7666 #define CCM_POST_ROOT82_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,82)
7667 #define CCM_PRE82                                CCM_PRE_REG(CCM_BASE_PTR,82)
7668 #define CCM_PRE_ROOT82_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,82)
7669 #define CCM_PRE_ROOT82_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,82)
7670 #define CCM_PRE_ROOT82_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,82)
7671 #define CCM_ACCESS_CTRL82                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,82)
7672 #define CCM_ACCESS_CTRL_ROOT82_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,82)
7673 #define CCM_ACCESS_CTRL_ROOT82_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,82)
7674 #define CCM_ACCESS_CTRL_ROOT82_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,82)
7675 #define CCM_TARGET_ROOT83                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,83)
7676 #define CCM_TARGET_ROOT83_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,83)
7677 #define CCM_TARGET_ROOT83_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,83)
7678 #define CCM_TARGET_ROOT83_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,83)
7679 #define CCM_MISC83                               CCM_MISC_REG(CCM_BASE_PTR,83)
7680 #define CCM_MISC_ROOT83_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,83)
7681 #define CCM_MISC_ROOT83_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,83)
7682 #define CCM_MISC_ROOT83_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,83)
7683 #define CCM_POST83                               CCM_POST_REG(CCM_BASE_PTR,83)
7684 #define CCM_POST_ROOT83_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,83)
7685 #define CCM_POST_ROOT83_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,83)
7686 #define CCM_POST_ROOT83_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,83)
7687 #define CCM_PRE83                                CCM_PRE_REG(CCM_BASE_PTR,83)
7688 #define CCM_PRE_ROOT83_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,83)
7689 #define CCM_PRE_ROOT83_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,83)
7690 #define CCM_PRE_ROOT83_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,83)
7691 #define CCM_ACCESS_CTRL83                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,83)
7692 #define CCM_ACCESS_CTRL_ROOT83_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,83)
7693 #define CCM_ACCESS_CTRL_ROOT83_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,83)
7694 #define CCM_ACCESS_CTRL_ROOT83_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,83)
7695 #define CCM_TARGET_ROOT84                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,84)
7696 #define CCM_TARGET_ROOT84_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,84)
7697 #define CCM_TARGET_ROOT84_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,84)
7698 #define CCM_TARGET_ROOT84_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,84)
7699 #define CCM_MISC84                               CCM_MISC_REG(CCM_BASE_PTR,84)
7700 #define CCM_MISC_ROOT84_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,84)
7701 #define CCM_MISC_ROOT84_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,84)
7702 #define CCM_MISC_ROOT84_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,84)
7703 #define CCM_POST84                               CCM_POST_REG(CCM_BASE_PTR,84)
7704 #define CCM_POST_ROOT84_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,84)
7705 #define CCM_POST_ROOT84_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,84)
7706 #define CCM_POST_ROOT84_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,84)
7707 #define CCM_PRE84                                CCM_PRE_REG(CCM_BASE_PTR,84)
7708 #define CCM_PRE_ROOT84_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,84)
7709 #define CCM_PRE_ROOT84_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,84)
7710 #define CCM_PRE_ROOT84_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,84)
7711 #define CCM_ACCESS_CTRL84                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,84)
7712 #define CCM_ACCESS_CTRL_ROOT84_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,84)
7713 #define CCM_ACCESS_CTRL_ROOT84_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,84)
7714 #define CCM_ACCESS_CTRL_ROOT84_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,84)
7715 #define CCM_TARGET_ROOT85                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,85)
7716 #define CCM_TARGET_ROOT85_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,85)
7717 #define CCM_TARGET_ROOT85_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,85)
7718 #define CCM_TARGET_ROOT85_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,85)
7719 #define CCM_MISC85                               CCM_MISC_REG(CCM_BASE_PTR,85)
7720 #define CCM_MISC_ROOT85_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,85)
7721 #define CCM_MISC_ROOT85_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,85)
7722 #define CCM_MISC_ROOT85_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,85)
7723 #define CCM_POST85                               CCM_POST_REG(CCM_BASE_PTR,85)
7724 #define CCM_POST_ROOT85_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,85)
7725 #define CCM_POST_ROOT85_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,85)
7726 #define CCM_POST_ROOT85_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,85)
7727 #define CCM_PRE85                                CCM_PRE_REG(CCM_BASE_PTR,85)
7728 #define CCM_PRE_ROOT85_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,85)
7729 #define CCM_PRE_ROOT85_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,85)
7730 #define CCM_PRE_ROOT85_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,85)
7731 #define CCM_ACCESS_CTRL85                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,85)
7732 #define CCM_ACCESS_CTRL_ROOT85_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,85)
7733 #define CCM_ACCESS_CTRL_ROOT85_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,85)
7734 #define CCM_ACCESS_CTRL_ROOT85_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,85)
7735 #define CCM_TARGET_ROOT86                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,86)
7736 #define CCM_TARGET_ROOT86_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,86)
7737 #define CCM_TARGET_ROOT86_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,86)
7738 #define CCM_TARGET_ROOT86_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,86)
7739 #define CCM_MISC86                               CCM_MISC_REG(CCM_BASE_PTR,86)
7740 #define CCM_MISC_ROOT86_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,86)
7741 #define CCM_MISC_ROOT86_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,86)
7742 #define CCM_MISC_ROOT86_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,86)
7743 #define CCM_POST86                               CCM_POST_REG(CCM_BASE_PTR,86)
7744 #define CCM_POST_ROOT86_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,86)
7745 #define CCM_POST_ROOT86_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,86)
7746 #define CCM_POST_ROOT86_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,86)
7747 #define CCM_PRE86                                CCM_PRE_REG(CCM_BASE_PTR,86)
7748 #define CCM_PRE_ROOT86_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,86)
7749 #define CCM_PRE_ROOT86_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,86)
7750 #define CCM_PRE_ROOT86_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,86)
7751 #define CCM_ACCESS_CTRL86                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,86)
7752 #define CCM_ACCESS_CTRL_ROOT86_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,86)
7753 #define CCM_ACCESS_CTRL_ROOT86_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,86)
7754 #define CCM_ACCESS_CTRL_ROOT86_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,86)
7755 #define CCM_TARGET_ROOT87                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,87)
7756 #define CCM_TARGET_ROOT87_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,87)
7757 #define CCM_TARGET_ROOT87_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,87)
7758 #define CCM_TARGET_ROOT87_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,87)
7759 #define CCM_MISC87                               CCM_MISC_REG(CCM_BASE_PTR,87)
7760 #define CCM_MISC_ROOT87_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,87)
7761 #define CCM_MISC_ROOT87_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,87)
7762 #define CCM_MISC_ROOT87_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,87)
7763 #define CCM_POST87                               CCM_POST_REG(CCM_BASE_PTR,87)
7764 #define CCM_POST_ROOT87_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,87)
7765 #define CCM_POST_ROOT87_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,87)
7766 #define CCM_POST_ROOT87_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,87)
7767 #define CCM_PRE87                                CCM_PRE_REG(CCM_BASE_PTR,87)
7768 #define CCM_PRE_ROOT87_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,87)
7769 #define CCM_PRE_ROOT87_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,87)
7770 #define CCM_PRE_ROOT87_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,87)
7771 #define CCM_ACCESS_CTRL87                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,87)
7772 #define CCM_ACCESS_CTRL_ROOT87_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,87)
7773 #define CCM_ACCESS_CTRL_ROOT87_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,87)
7774 #define CCM_ACCESS_CTRL_ROOT87_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,87)
7775 #define CCM_TARGET_ROOT88                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,88)
7776 #define CCM_TARGET_ROOT88_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,88)
7777 #define CCM_TARGET_ROOT88_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,88)
7778 #define CCM_TARGET_ROOT88_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,88)
7779 #define CCM_MISC88                               CCM_MISC_REG(CCM_BASE_PTR,88)
7780 #define CCM_MISC_ROOT88_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,88)
7781 #define CCM_MISC_ROOT88_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,88)
7782 #define CCM_MISC_ROOT88_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,88)
7783 #define CCM_POST88                               CCM_POST_REG(CCM_BASE_PTR,88)
7784 #define CCM_POST_ROOT88_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,88)
7785 #define CCM_POST_ROOT88_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,88)
7786 #define CCM_POST_ROOT88_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,88)
7787 #define CCM_PRE88                                CCM_PRE_REG(CCM_BASE_PTR,88)
7788 #define CCM_PRE_ROOT88_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,88)
7789 #define CCM_PRE_ROOT88_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,88)
7790 #define CCM_PRE_ROOT88_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,88)
7791 #define CCM_ACCESS_CTRL88                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,88)
7792 #define CCM_ACCESS_CTRL_ROOT88_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,88)
7793 #define CCM_ACCESS_CTRL_ROOT88_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,88)
7794 #define CCM_ACCESS_CTRL_ROOT88_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,88)
7795 #define CCM_TARGET_ROOT89                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,89)
7796 #define CCM_TARGET_ROOT89_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,89)
7797 #define CCM_TARGET_ROOT89_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,89)
7798 #define CCM_TARGET_ROOT89_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,89)
7799 #define CCM_MISC89                               CCM_MISC_REG(CCM_BASE_PTR,89)
7800 #define CCM_MISC_ROOT89_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,89)
7801 #define CCM_MISC_ROOT89_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,89)
7802 #define CCM_MISC_ROOT89_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,89)
7803 #define CCM_POST89                               CCM_POST_REG(CCM_BASE_PTR,89)
7804 #define CCM_POST_ROOT89_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,89)
7805 #define CCM_POST_ROOT89_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,89)
7806 #define CCM_POST_ROOT89_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,89)
7807 #define CCM_PRE89                                CCM_PRE_REG(CCM_BASE_PTR,89)
7808 #define CCM_PRE_ROOT89_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,89)
7809 #define CCM_PRE_ROOT89_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,89)
7810 #define CCM_PRE_ROOT89_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,89)
7811 #define CCM_ACCESS_CTRL89                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,89)
7812 #define CCM_ACCESS_CTRL_ROOT89_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,89)
7813 #define CCM_ACCESS_CTRL_ROOT89_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,89)
7814 #define CCM_ACCESS_CTRL_ROOT89_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,89)
7815 #define CCM_TARGET_ROOT90                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,90)
7816 #define CCM_TARGET_ROOT90_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,90)
7817 #define CCM_TARGET_ROOT90_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,90)
7818 #define CCM_TARGET_ROOT90_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,90)
7819 #define CCM_MISC90                               CCM_MISC_REG(CCM_BASE_PTR,90)
7820 #define CCM_MISC_ROOT90_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,90)
7821 #define CCM_MISC_ROOT90_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,90)
7822 #define CCM_MISC_ROOT90_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,90)
7823 #define CCM_POST90                               CCM_POST_REG(CCM_BASE_PTR,90)
7824 #define CCM_POST_ROOT90_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,90)
7825 #define CCM_POST_ROOT90_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,90)
7826 #define CCM_POST_ROOT90_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,90)
7827 #define CCM_PRE90                                CCM_PRE_REG(CCM_BASE_PTR,90)
7828 #define CCM_PRE_ROOT90_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,90)
7829 #define CCM_PRE_ROOT90_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,90)
7830 #define CCM_PRE_ROOT90_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,90)
7831 #define CCM_ACCESS_CTRL90                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,90)
7832 #define CCM_ACCESS_CTRL_ROOT90_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,90)
7833 #define CCM_ACCESS_CTRL_ROOT90_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,90)
7834 #define CCM_ACCESS_CTRL_ROOT90_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,90)
7835 #define CCM_TARGET_ROOT91                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,91)
7836 #define CCM_TARGET_ROOT91_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,91)
7837 #define CCM_TARGET_ROOT91_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,91)
7838 #define CCM_TARGET_ROOT91_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,91)
7839 #define CCM_MISC91                               CCM_MISC_REG(CCM_BASE_PTR,91)
7840 #define CCM_MISC_ROOT91_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,91)
7841 #define CCM_MISC_ROOT91_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,91)
7842 #define CCM_MISC_ROOT91_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,91)
7843 #define CCM_POST91                               CCM_POST_REG(CCM_BASE_PTR,91)
7844 #define CCM_POST_ROOT91_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,91)
7845 #define CCM_POST_ROOT91_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,91)
7846 #define CCM_POST_ROOT91_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,91)
7847 #define CCM_PRE91                                CCM_PRE_REG(CCM_BASE_PTR,91)
7848 #define CCM_PRE_ROOT91_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,91)
7849 #define CCM_PRE_ROOT91_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,91)
7850 #define CCM_PRE_ROOT91_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,91)
7851 #define CCM_ACCESS_CTRL91                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,91)
7852 #define CCM_ACCESS_CTRL_ROOT91_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,91)
7853 #define CCM_ACCESS_CTRL_ROOT91_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,91)
7854 #define CCM_ACCESS_CTRL_ROOT91_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,91)
7855 #define CCM_TARGET_ROOT92                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,92)
7856 #define CCM_TARGET_ROOT92_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,92)
7857 #define CCM_TARGET_ROOT92_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,92)
7858 #define CCM_TARGET_ROOT92_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,92)
7859 #define CCM_MISC92                               CCM_MISC_REG(CCM_BASE_PTR,92)
7860 #define CCM_MISC_ROOT92_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,92)
7861 #define CCM_MISC_ROOT92_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,92)
7862 #define CCM_MISC_ROOT92_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,92)
7863 #define CCM_POST92                               CCM_POST_REG(CCM_BASE_PTR,92)
7864 #define CCM_POST_ROOT92_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,92)
7865 #define CCM_POST_ROOT92_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,92)
7866 #define CCM_POST_ROOT92_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,92)
7867 #define CCM_PRE92                                CCM_PRE_REG(CCM_BASE_PTR,92)
7868 #define CCM_PRE_ROOT92_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,92)
7869 #define CCM_PRE_ROOT92_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,92)
7870 #define CCM_PRE_ROOT92_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,92)
7871 #define CCM_ACCESS_CTRL92                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,92)
7872 #define CCM_ACCESS_CTRL_ROOT92_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,92)
7873 #define CCM_ACCESS_CTRL_ROOT92_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,92)
7874 #define CCM_ACCESS_CTRL_ROOT92_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,92)
7875 #define CCM_TARGET_ROOT93                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,93)
7876 #define CCM_TARGET_ROOT93_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,93)
7877 #define CCM_TARGET_ROOT93_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,93)
7878 #define CCM_TARGET_ROOT93_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,93)
7879 #define CCM_MISC93                               CCM_MISC_REG(CCM_BASE_PTR,93)
7880 #define CCM_MISC_ROOT93_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,93)
7881 #define CCM_MISC_ROOT93_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,93)
7882 #define CCM_MISC_ROOT93_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,93)
7883 #define CCM_POST93                               CCM_POST_REG(CCM_BASE_PTR,93)
7884 #define CCM_POST_ROOT93_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,93)
7885 #define CCM_POST_ROOT93_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,93)
7886 #define CCM_POST_ROOT93_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,93)
7887 #define CCM_PRE93                                CCM_PRE_REG(CCM_BASE_PTR,93)
7888 #define CCM_PRE_ROOT93_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,93)
7889 #define CCM_PRE_ROOT93_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,93)
7890 #define CCM_PRE_ROOT93_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,93)
7891 #define CCM_ACCESS_CTRL93                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,93)
7892 #define CCM_ACCESS_CTRL_ROOT93_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,93)
7893 #define CCM_ACCESS_CTRL_ROOT93_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,93)
7894 #define CCM_ACCESS_CTRL_ROOT93_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,93)
7895 #define CCM_TARGET_ROOT94                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,94)
7896 #define CCM_TARGET_ROOT94_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,94)
7897 #define CCM_TARGET_ROOT94_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,94)
7898 #define CCM_TARGET_ROOT94_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,94)
7899 #define CCM_MISC94                               CCM_MISC_REG(CCM_BASE_PTR,94)
7900 #define CCM_MISC_ROOT94_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,94)
7901 #define CCM_MISC_ROOT94_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,94)
7902 #define CCM_MISC_ROOT94_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,94)
7903 #define CCM_POST94                               CCM_POST_REG(CCM_BASE_PTR,94)
7904 #define CCM_POST_ROOT94_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,94)
7905 #define CCM_POST_ROOT94_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,94)
7906 #define CCM_POST_ROOT94_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,94)
7907 #define CCM_PRE94                                CCM_PRE_REG(CCM_BASE_PTR,94)
7908 #define CCM_PRE_ROOT94_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,94)
7909 #define CCM_PRE_ROOT94_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,94)
7910 #define CCM_PRE_ROOT94_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,94)
7911 #define CCM_ACCESS_CTRL94                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,94)
7912 #define CCM_ACCESS_CTRL_ROOT94_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,94)
7913 #define CCM_ACCESS_CTRL_ROOT94_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,94)
7914 #define CCM_ACCESS_CTRL_ROOT94_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,94)
7915 #define CCM_TARGET_ROOT95                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,95)
7916 #define CCM_TARGET_ROOT95_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,95)
7917 #define CCM_TARGET_ROOT95_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,95)
7918 #define CCM_TARGET_ROOT95_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,95)
7919 #define CCM_MISC95                               CCM_MISC_REG(CCM_BASE_PTR,95)
7920 #define CCM_MISC_ROOT95_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,95)
7921 #define CCM_MISC_ROOT95_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,95)
7922 #define CCM_MISC_ROOT95_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,95)
7923 #define CCM_POST95                               CCM_POST_REG(CCM_BASE_PTR,95)
7924 #define CCM_POST_ROOT95_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,95)
7925 #define CCM_POST_ROOT95_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,95)
7926 #define CCM_POST_ROOT95_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,95)
7927 #define CCM_PRE95                                CCM_PRE_REG(CCM_BASE_PTR,95)
7928 #define CCM_PRE_ROOT95_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,95)
7929 #define CCM_PRE_ROOT95_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,95)
7930 #define CCM_PRE_ROOT95_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,95)
7931 #define CCM_ACCESS_CTRL95                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,95)
7932 #define CCM_ACCESS_CTRL_ROOT95_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,95)
7933 #define CCM_ACCESS_CTRL_ROOT95_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,95)
7934 #define CCM_ACCESS_CTRL_ROOT95_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,95)
7935 #define CCM_TARGET_ROOT96                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,96)
7936 #define CCM_TARGET_ROOT96_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,96)
7937 #define CCM_TARGET_ROOT96_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,96)
7938 #define CCM_TARGET_ROOT96_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,96)
7939 #define CCM_MISC96                               CCM_MISC_REG(CCM_BASE_PTR,96)
7940 #define CCM_MISC_ROOT96_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,96)
7941 #define CCM_MISC_ROOT96_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,96)
7942 #define CCM_MISC_ROOT96_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,96)
7943 #define CCM_POST96                               CCM_POST_REG(CCM_BASE_PTR,96)
7944 #define CCM_POST_ROOT96_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,96)
7945 #define CCM_POST_ROOT96_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,96)
7946 #define CCM_POST_ROOT96_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,96)
7947 #define CCM_PRE96                                CCM_PRE_REG(CCM_BASE_PTR,96)
7948 #define CCM_PRE_ROOT96_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,96)
7949 #define CCM_PRE_ROOT96_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,96)
7950 #define CCM_PRE_ROOT96_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,96)
7951 #define CCM_ACCESS_CTRL96                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,96)
7952 #define CCM_ACCESS_CTRL_ROOT96_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,96)
7953 #define CCM_ACCESS_CTRL_ROOT96_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,96)
7954 #define CCM_ACCESS_CTRL_ROOT96_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,96)
7955 #define CCM_TARGET_ROOT97                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,97)
7956 #define CCM_TARGET_ROOT97_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,97)
7957 #define CCM_TARGET_ROOT97_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,97)
7958 #define CCM_TARGET_ROOT97_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,97)
7959 #define CCM_MISC97                               CCM_MISC_REG(CCM_BASE_PTR,97)
7960 #define CCM_MISC_ROOT97_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,97)
7961 #define CCM_MISC_ROOT97_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,97)
7962 #define CCM_MISC_ROOT97_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,97)
7963 #define CCM_POST97                               CCM_POST_REG(CCM_BASE_PTR,97)
7964 #define CCM_POST_ROOT97_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,97)
7965 #define CCM_POST_ROOT97_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,97)
7966 #define CCM_POST_ROOT97_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,97)
7967 #define CCM_PRE97                                CCM_PRE_REG(CCM_BASE_PTR,97)
7968 #define CCM_PRE_ROOT97_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,97)
7969 #define CCM_PRE_ROOT97_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,97)
7970 #define CCM_PRE_ROOT97_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,97)
7971 #define CCM_ACCESS_CTRL97                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,97)
7972 #define CCM_ACCESS_CTRL_ROOT97_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,97)
7973 #define CCM_ACCESS_CTRL_ROOT97_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,97)
7974 #define CCM_ACCESS_CTRL_ROOT97_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,97)
7975 #define CCM_TARGET_ROOT98                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,98)
7976 #define CCM_TARGET_ROOT98_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,98)
7977 #define CCM_TARGET_ROOT98_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,98)
7978 #define CCM_TARGET_ROOT98_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,98)
7979 #define CCM_MISC98                               CCM_MISC_REG(CCM_BASE_PTR,98)
7980 #define CCM_MISC_ROOT98_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,98)
7981 #define CCM_MISC_ROOT98_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,98)
7982 #define CCM_MISC_ROOT98_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,98)
7983 #define CCM_POST98                               CCM_POST_REG(CCM_BASE_PTR,98)
7984 #define CCM_POST_ROOT98_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,98)
7985 #define CCM_POST_ROOT98_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,98)
7986 #define CCM_POST_ROOT98_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,98)
7987 #define CCM_PRE98                                CCM_PRE_REG(CCM_BASE_PTR,98)
7988 #define CCM_PRE_ROOT98_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,98)
7989 #define CCM_PRE_ROOT98_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,98)
7990 #define CCM_PRE_ROOT98_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,98)
7991 #define CCM_ACCESS_CTRL98                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,98)
7992 #define CCM_ACCESS_CTRL_ROOT98_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,98)
7993 #define CCM_ACCESS_CTRL_ROOT98_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,98)
7994 #define CCM_ACCESS_CTRL_ROOT98_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,98)
7995 #define CCM_TARGET_ROOT99                        CCM_TARGET_ROOT_REG(CCM_BASE_PTR,99)
7996 #define CCM_TARGET_ROOT99_SET                    CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,99)
7997 #define CCM_TARGET_ROOT99_CLR                    CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,99)
7998 #define CCM_TARGET_ROOT99_TOG                    CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,99)
7999 #define CCM_MISC99                               CCM_MISC_REG(CCM_BASE_PTR,99)
8000 #define CCM_MISC_ROOT99_SET                      CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,99)
8001 #define CCM_MISC_ROOT99_CLR                      CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,99)
8002 #define CCM_MISC_ROOT99_TOG                      CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,99)
8003 #define CCM_POST99                               CCM_POST_REG(CCM_BASE_PTR,99)
8004 #define CCM_POST_ROOT99_SET                      CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,99)
8005 #define CCM_POST_ROOT99_CLR                      CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,99)
8006 #define CCM_POST_ROOT99_TOG                      CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,99)
8007 #define CCM_PRE99                                CCM_PRE_REG(CCM_BASE_PTR,99)
8008 #define CCM_PRE_ROOT99_SET                       CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,99)
8009 #define CCM_PRE_ROOT99_CLR                       CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,99)
8010 #define CCM_PRE_ROOT99_TOG                       CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,99)
8011 #define CCM_ACCESS_CTRL99                        CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,99)
8012 #define CCM_ACCESS_CTRL_ROOT99_SET               CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,99)
8013 #define CCM_ACCESS_CTRL_ROOT99_CLR               CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,99)
8014 #define CCM_ACCESS_CTRL_ROOT99_TOG               CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,99)
8015 #define CCM_TARGET_ROOT100                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,100)
8016 #define CCM_TARGET_ROOT100_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,100)
8017 #define CCM_TARGET_ROOT100_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,100)
8018 #define CCM_TARGET_ROOT100_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,100)
8019 #define CCM_MISC100                              CCM_MISC_REG(CCM_BASE_PTR,100)
8020 #define CCM_MISC_ROOT100_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,100)
8021 #define CCM_MISC_ROOT100_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,100)
8022 #define CCM_MISC_ROOT100_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,100)
8023 #define CCM_POST100                              CCM_POST_REG(CCM_BASE_PTR,100)
8024 #define CCM_POST_ROOT100_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,100)
8025 #define CCM_POST_ROOT100_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,100)
8026 #define CCM_POST_ROOT100_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,100)
8027 #define CCM_PRE100                               CCM_PRE_REG(CCM_BASE_PTR,100)
8028 #define CCM_PRE_ROOT100_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,100)
8029 #define CCM_PRE_ROOT100_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,100)
8030 #define CCM_PRE_ROOT100_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,100)
8031 #define CCM_ACCESS_CTRL100                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,100)
8032 #define CCM_ACCESS_CTRL_ROOT100_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,100)
8033 #define CCM_ACCESS_CTRL_ROOT100_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,100)
8034 #define CCM_ACCESS_CTRL_ROOT100_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,100)
8035 #define CCM_TARGET_ROOT101                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,101)
8036 #define CCM_TARGET_ROOT101_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,101)
8037 #define CCM_TARGET_ROOT101_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,101)
8038 #define CCM_TARGET_ROOT101_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,101)
8039 #define CCM_MISC101                              CCM_MISC_REG(CCM_BASE_PTR,101)
8040 #define CCM_MISC_ROOT101_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,101)
8041 #define CCM_MISC_ROOT101_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,101)
8042 #define CCM_MISC_ROOT101_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,101)
8043 #define CCM_POST101                              CCM_POST_REG(CCM_BASE_PTR,101)
8044 #define CCM_POST_ROOT101_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,101)
8045 #define CCM_POST_ROOT101_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,101)
8046 #define CCM_POST_ROOT101_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,101)
8047 #define CCM_PRE101                               CCM_PRE_REG(CCM_BASE_PTR,101)
8048 #define CCM_PRE_ROOT101_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,101)
8049 #define CCM_PRE_ROOT101_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,101)
8050 #define CCM_PRE_ROOT101_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,101)
8051 #define CCM_ACCESS_CTRL101                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,101)
8052 #define CCM_ACCESS_CTRL_ROOT101_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,101)
8053 #define CCM_ACCESS_CTRL_ROOT101_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,101)
8054 #define CCM_ACCESS_CTRL_ROOT101_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,101)
8055 #define CCM_TARGET_ROOT102                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,102)
8056 #define CCM_TARGET_ROOT102_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,102)
8057 #define CCM_TARGET_ROOT102_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,102)
8058 #define CCM_TARGET_ROOT102_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,102)
8059 #define CCM_MISC102                              CCM_MISC_REG(CCM_BASE_PTR,102)
8060 #define CCM_MISC_ROOT102_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,102)
8061 #define CCM_MISC_ROOT102_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,102)
8062 #define CCM_MISC_ROOT102_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,102)
8063 #define CCM_POST102                              CCM_POST_REG(CCM_BASE_PTR,102)
8064 #define CCM_POST_ROOT102_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,102)
8065 #define CCM_POST_ROOT102_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,102)
8066 #define CCM_POST_ROOT102_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,102)
8067 #define CCM_PRE102                               CCM_PRE_REG(CCM_BASE_PTR,102)
8068 #define CCM_PRE_ROOT102_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,102)
8069 #define CCM_PRE_ROOT102_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,102)
8070 #define CCM_PRE_ROOT102_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,102)
8071 #define CCM_ACCESS_CTRL102                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,102)
8072 #define CCM_ACCESS_CTRL_ROOT102_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,102)
8073 #define CCM_ACCESS_CTRL_ROOT102_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,102)
8074 #define CCM_ACCESS_CTRL_ROOT102_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,102)
8075 #define CCM_TARGET_ROOT103                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,103)
8076 #define CCM_TARGET_ROOT103_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,103)
8077 #define CCM_TARGET_ROOT103_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,103)
8078 #define CCM_TARGET_ROOT103_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,103)
8079 #define CCM_MISC103                              CCM_MISC_REG(CCM_BASE_PTR,103)
8080 #define CCM_MISC_ROOT103_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,103)
8081 #define CCM_MISC_ROOT103_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,103)
8082 #define CCM_MISC_ROOT103_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,103)
8083 #define CCM_POST103                              CCM_POST_REG(CCM_BASE_PTR,103)
8084 #define CCM_POST_ROOT103_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,103)
8085 #define CCM_POST_ROOT103_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,103)
8086 #define CCM_POST_ROOT103_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,103)
8087 #define CCM_PRE103                               CCM_PRE_REG(CCM_BASE_PTR,103)
8088 #define CCM_PRE_ROOT103_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,103)
8089 #define CCM_PRE_ROOT103_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,103)
8090 #define CCM_PRE_ROOT103_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,103)
8091 #define CCM_ACCESS_CTRL103                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,103)
8092 #define CCM_ACCESS_CTRL_ROOT103_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,103)
8093 #define CCM_ACCESS_CTRL_ROOT103_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,103)
8094 #define CCM_ACCESS_CTRL_ROOT103_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,103)
8095 #define CCM_TARGET_ROOT104                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,104)
8096 #define CCM_TARGET_ROOT104_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,104)
8097 #define CCM_TARGET_ROOT104_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,104)
8098 #define CCM_TARGET_ROOT104_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,104)
8099 #define CCM_MISC104                              CCM_MISC_REG(CCM_BASE_PTR,104)
8100 #define CCM_MISC_ROOT104_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,104)
8101 #define CCM_MISC_ROOT104_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,104)
8102 #define CCM_MISC_ROOT104_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,104)
8103 #define CCM_POST104                              CCM_POST_REG(CCM_BASE_PTR,104)
8104 #define CCM_POST_ROOT104_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,104)
8105 #define CCM_POST_ROOT104_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,104)
8106 #define CCM_POST_ROOT104_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,104)
8107 #define CCM_PRE104                               CCM_PRE_REG(CCM_BASE_PTR,104)
8108 #define CCM_PRE_ROOT104_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,104)
8109 #define CCM_PRE_ROOT104_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,104)
8110 #define CCM_PRE_ROOT104_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,104)
8111 #define CCM_ACCESS_CTRL104                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,104)
8112 #define CCM_ACCESS_CTRL_ROOT104_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,104)
8113 #define CCM_ACCESS_CTRL_ROOT104_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,104)
8114 #define CCM_ACCESS_CTRL_ROOT104_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,104)
8115 #define CCM_TARGET_ROOT105                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,105)
8116 #define CCM_TARGET_ROOT105_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,105)
8117 #define CCM_TARGET_ROOT105_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,105)
8118 #define CCM_TARGET_ROOT105_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,105)
8119 #define CCM_MISC105                              CCM_MISC_REG(CCM_BASE_PTR,105)
8120 #define CCM_MISC_ROOT105_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,105)
8121 #define CCM_MISC_ROOT105_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,105)
8122 #define CCM_MISC_ROOT105_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,105)
8123 #define CCM_POST105                              CCM_POST_REG(CCM_BASE_PTR,105)
8124 #define CCM_POST_ROOT105_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,105)
8125 #define CCM_POST_ROOT105_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,105)
8126 #define CCM_POST_ROOT105_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,105)
8127 #define CCM_PRE105                               CCM_PRE_REG(CCM_BASE_PTR,105)
8128 #define CCM_PRE_ROOT105_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,105)
8129 #define CCM_PRE_ROOT105_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,105)
8130 #define CCM_PRE_ROOT105_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,105)
8131 #define CCM_ACCESS_CTRL105                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,105)
8132 #define CCM_ACCESS_CTRL_ROOT105_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,105)
8133 #define CCM_ACCESS_CTRL_ROOT105_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,105)
8134 #define CCM_ACCESS_CTRL_ROOT105_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,105)
8135 #define CCM_TARGET_ROOT106                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,106)
8136 #define CCM_TARGET_ROOT106_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,106)
8137 #define CCM_TARGET_ROOT106_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,106)
8138 #define CCM_TARGET_ROOT106_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,106)
8139 #define CCM_MISC106                              CCM_MISC_REG(CCM_BASE_PTR,106)
8140 #define CCM_MISC_ROOT106_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,106)
8141 #define CCM_MISC_ROOT106_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,106)
8142 #define CCM_MISC_ROOT106_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,106)
8143 #define CCM_POST106                              CCM_POST_REG(CCM_BASE_PTR,106)
8144 #define CCM_POST_ROOT106_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,106)
8145 #define CCM_POST_ROOT106_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,106)
8146 #define CCM_POST_ROOT106_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,106)
8147 #define CCM_PRE106                               CCM_PRE_REG(CCM_BASE_PTR,106)
8148 #define CCM_PRE_ROOT106_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,106)
8149 #define CCM_PRE_ROOT106_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,106)
8150 #define CCM_PRE_ROOT106_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,106)
8151 #define CCM_ACCESS_CTRL106                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,106)
8152 #define CCM_ACCESS_CTRL_ROOT106_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,106)
8153 #define CCM_ACCESS_CTRL_ROOT106_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,106)
8154 #define CCM_ACCESS_CTRL_ROOT106_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,106)
8155 #define CCM_TARGET_ROOT107                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,107)
8156 #define CCM_TARGET_ROOT107_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,107)
8157 #define CCM_TARGET_ROOT107_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,107)
8158 #define CCM_TARGET_ROOT107_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,107)
8159 #define CCM_MISC107                              CCM_MISC_REG(CCM_BASE_PTR,107)
8160 #define CCM_MISC_ROOT107_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,107)
8161 #define CCM_MISC_ROOT107_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,107)
8162 #define CCM_MISC_ROOT107_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,107)
8163 #define CCM_POST107                              CCM_POST_REG(CCM_BASE_PTR,107)
8164 #define CCM_POST_ROOT107_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,107)
8165 #define CCM_POST_ROOT107_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,107)
8166 #define CCM_POST_ROOT107_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,107)
8167 #define CCM_PRE107                               CCM_PRE_REG(CCM_BASE_PTR,107)
8168 #define CCM_PRE_ROOT107_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,107)
8169 #define CCM_PRE_ROOT107_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,107)
8170 #define CCM_PRE_ROOT107_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,107)
8171 #define CCM_ACCESS_CTRL107                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,107)
8172 #define CCM_ACCESS_CTRL_ROOT107_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,107)
8173 #define CCM_ACCESS_CTRL_ROOT107_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,107)
8174 #define CCM_ACCESS_CTRL_ROOT107_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,107)
8175 #define CCM_TARGET_ROOT108                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,108)
8176 #define CCM_TARGET_ROOT108_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,108)
8177 #define CCM_TARGET_ROOT108_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,108)
8178 #define CCM_TARGET_ROOT108_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,108)
8179 #define CCM_MISC108                              CCM_MISC_REG(CCM_BASE_PTR,108)
8180 #define CCM_MISC_ROOT108_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,108)
8181 #define CCM_MISC_ROOT108_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,108)
8182 #define CCM_MISC_ROOT108_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,108)
8183 #define CCM_POST108                              CCM_POST_REG(CCM_BASE_PTR,108)
8184 #define CCM_POST_ROOT108_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,108)
8185 #define CCM_POST_ROOT108_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,108)
8186 #define CCM_POST_ROOT108_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,108)
8187 #define CCM_PRE108                               CCM_PRE_REG(CCM_BASE_PTR,108)
8188 #define CCM_PRE_ROOT108_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,108)
8189 #define CCM_PRE_ROOT108_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,108)
8190 #define CCM_PRE_ROOT108_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,108)
8191 #define CCM_ACCESS_CTRL108                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,108)
8192 #define CCM_ACCESS_CTRL_ROOT108_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,108)
8193 #define CCM_ACCESS_CTRL_ROOT108_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,108)
8194 #define CCM_ACCESS_CTRL_ROOT108_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,108)
8195 #define CCM_TARGET_ROOT109                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,109)
8196 #define CCM_TARGET_ROOT109_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,109)
8197 #define CCM_TARGET_ROOT109_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,109)
8198 #define CCM_TARGET_ROOT109_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,109)
8199 #define CCM_MISC109                              CCM_MISC_REG(CCM_BASE_PTR,109)
8200 #define CCM_MISC_ROOT109_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,109)
8201 #define CCM_MISC_ROOT109_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,109)
8202 #define CCM_MISC_ROOT109_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,109)
8203 #define CCM_POST109                              CCM_POST_REG(CCM_BASE_PTR,109)
8204 #define CCM_POST_ROOT109_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,109)
8205 #define CCM_POST_ROOT109_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,109)
8206 #define CCM_POST_ROOT109_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,109)
8207 #define CCM_PRE109                               CCM_PRE_REG(CCM_BASE_PTR,109)
8208 #define CCM_PRE_ROOT109_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,109)
8209 #define CCM_PRE_ROOT109_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,109)
8210 #define CCM_PRE_ROOT109_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,109)
8211 #define CCM_ACCESS_CTRL109                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,109)
8212 #define CCM_ACCESS_CTRL_ROOT109_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,109)
8213 #define CCM_ACCESS_CTRL_ROOT109_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,109)
8214 #define CCM_ACCESS_CTRL_ROOT109_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,109)
8215 #define CCM_TARGET_ROOT110                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,110)
8216 #define CCM_TARGET_ROOT110_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,110)
8217 #define CCM_TARGET_ROOT110_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,110)
8218 #define CCM_TARGET_ROOT110_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,110)
8219 #define CCM_MISC110                              CCM_MISC_REG(CCM_BASE_PTR,110)
8220 #define CCM_MISC_ROOT110_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,110)
8221 #define CCM_MISC_ROOT110_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,110)
8222 #define CCM_MISC_ROOT110_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,110)
8223 #define CCM_POST110                              CCM_POST_REG(CCM_BASE_PTR,110)
8224 #define CCM_POST_ROOT110_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,110)
8225 #define CCM_POST_ROOT110_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,110)
8226 #define CCM_POST_ROOT110_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,110)
8227 #define CCM_PRE110                               CCM_PRE_REG(CCM_BASE_PTR,110)
8228 #define CCM_PRE_ROOT110_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,110)
8229 #define CCM_PRE_ROOT110_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,110)
8230 #define CCM_PRE_ROOT110_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,110)
8231 #define CCM_ACCESS_CTRL110                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,110)
8232 #define CCM_ACCESS_CTRL_ROOT110_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,110)
8233 #define CCM_ACCESS_CTRL_ROOT110_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,110)
8234 #define CCM_ACCESS_CTRL_ROOT110_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,110)
8235 #define CCM_TARGET_ROOT111                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,111)
8236 #define CCM_TARGET_ROOT111_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,111)
8237 #define CCM_TARGET_ROOT111_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,111)
8238 #define CCM_TARGET_ROOT111_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,111)
8239 #define CCM_MISC111                              CCM_MISC_REG(CCM_BASE_PTR,111)
8240 #define CCM_MISC_ROOT111_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,111)
8241 #define CCM_MISC_ROOT111_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,111)
8242 #define CCM_MISC_ROOT111_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,111)
8243 #define CCM_POST111                              CCM_POST_REG(CCM_BASE_PTR,111)
8244 #define CCM_POST_ROOT111_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,111)
8245 #define CCM_POST_ROOT111_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,111)
8246 #define CCM_POST_ROOT111_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,111)
8247 #define CCM_PRE111                               CCM_PRE_REG(CCM_BASE_PTR,111)
8248 #define CCM_PRE_ROOT111_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,111)
8249 #define CCM_PRE_ROOT111_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,111)
8250 #define CCM_PRE_ROOT111_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,111)
8251 #define CCM_ACCESS_CTRL111                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,111)
8252 #define CCM_ACCESS_CTRL_ROOT111_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,111)
8253 #define CCM_ACCESS_CTRL_ROOT111_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,111)
8254 #define CCM_ACCESS_CTRL_ROOT111_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,111)
8255 #define CCM_TARGET_ROOT112                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,112)
8256 #define CCM_TARGET_ROOT112_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,112)
8257 #define CCM_TARGET_ROOT112_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,112)
8258 #define CCM_TARGET_ROOT112_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,112)
8259 #define CCM_MISC112                              CCM_MISC_REG(CCM_BASE_PTR,112)
8260 #define CCM_MISC_ROOT112_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,112)
8261 #define CCM_MISC_ROOT112_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,112)
8262 #define CCM_MISC_ROOT112_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,112)
8263 #define CCM_POST112                              CCM_POST_REG(CCM_BASE_PTR,112)
8264 #define CCM_POST_ROOT112_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,112)
8265 #define CCM_POST_ROOT112_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,112)
8266 #define CCM_POST_ROOT112_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,112)
8267 #define CCM_PRE112                               CCM_PRE_REG(CCM_BASE_PTR,112)
8268 #define CCM_PRE_ROOT112_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,112)
8269 #define CCM_PRE_ROOT112_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,112)
8270 #define CCM_PRE_ROOT112_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,112)
8271 #define CCM_ACCESS_CTRL112                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,112)
8272 #define CCM_ACCESS_CTRL_ROOT112_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,112)
8273 #define CCM_ACCESS_CTRL_ROOT112_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,112)
8274 #define CCM_ACCESS_CTRL_ROOT112_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,112)
8275 #define CCM_TARGET_ROOT113                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,113)
8276 #define CCM_TARGET_ROOT113_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,113)
8277 #define CCM_TARGET_ROOT113_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,113)
8278 #define CCM_TARGET_ROOT113_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,113)
8279 #define CCM_MISC113                              CCM_MISC_REG(CCM_BASE_PTR,113)
8280 #define CCM_MISC_ROOT113_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,113)
8281 #define CCM_MISC_ROOT113_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,113)
8282 #define CCM_MISC_ROOT113_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,113)
8283 #define CCM_POST113                              CCM_POST_REG(CCM_BASE_PTR,113)
8284 #define CCM_POST_ROOT113_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,113)
8285 #define CCM_POST_ROOT113_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,113)
8286 #define CCM_POST_ROOT113_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,113)
8287 #define CCM_PRE113                               CCM_PRE_REG(CCM_BASE_PTR,113)
8288 #define CCM_PRE_ROOT113_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,113)
8289 #define CCM_PRE_ROOT113_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,113)
8290 #define CCM_PRE_ROOT113_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,113)
8291 #define CCM_ACCESS_CTRL113                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,113)
8292 #define CCM_ACCESS_CTRL_ROOT113_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,113)
8293 #define CCM_ACCESS_CTRL_ROOT113_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,113)
8294 #define CCM_ACCESS_CTRL_ROOT113_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,113)
8295 #define CCM_TARGET_ROOT114                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,114)
8296 #define CCM_TARGET_ROOT114_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,114)
8297 #define CCM_TARGET_ROOT114_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,114)
8298 #define CCM_TARGET_ROOT114_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,114)
8299 #define CCM_MISC114                              CCM_MISC_REG(CCM_BASE_PTR,114)
8300 #define CCM_MISC_ROOT114_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,114)
8301 #define CCM_MISC_ROOT114_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,114)
8302 #define CCM_MISC_ROOT114_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,114)
8303 #define CCM_POST114                              CCM_POST_REG(CCM_BASE_PTR,114)
8304 #define CCM_POST_ROOT114_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,114)
8305 #define CCM_POST_ROOT114_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,114)
8306 #define CCM_POST_ROOT114_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,114)
8307 #define CCM_PRE114                               CCM_PRE_REG(CCM_BASE_PTR,114)
8308 #define CCM_PRE_ROOT114_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,114)
8309 #define CCM_PRE_ROOT114_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,114)
8310 #define CCM_PRE_ROOT114_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,114)
8311 #define CCM_ACCESS_CTRL114                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,114)
8312 #define CCM_ACCESS_CTRL_ROOT114_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,114)
8313 #define CCM_ACCESS_CTRL_ROOT114_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,114)
8314 #define CCM_ACCESS_CTRL_ROOT114_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,114)
8315 #define CCM_TARGET_ROOT115                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,115)
8316 #define CCM_TARGET_ROOT115_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,115)
8317 #define CCM_TARGET_ROOT115_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,115)
8318 #define CCM_TARGET_ROOT115_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,115)
8319 #define CCM_MISC115                              CCM_MISC_REG(CCM_BASE_PTR,115)
8320 #define CCM_MISC_ROOT115_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,115)
8321 #define CCM_MISC_ROOT115_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,115)
8322 #define CCM_MISC_ROOT115_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,115)
8323 #define CCM_POST115                              CCM_POST_REG(CCM_BASE_PTR,115)
8324 #define CCM_POST_ROOT115_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,115)
8325 #define CCM_POST_ROOT115_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,115)
8326 #define CCM_POST_ROOT115_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,115)
8327 #define CCM_PRE115                               CCM_PRE_REG(CCM_BASE_PTR,115)
8328 #define CCM_PRE_ROOT115_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,115)
8329 #define CCM_PRE_ROOT115_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,115)
8330 #define CCM_PRE_ROOT115_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,115)
8331 #define CCM_ACCESS_CTRL115                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,115)
8332 #define CCM_ACCESS_CTRL_ROOT115_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,115)
8333 #define CCM_ACCESS_CTRL_ROOT115_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,115)
8334 #define CCM_ACCESS_CTRL_ROOT115_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,115)
8335 #define CCM_TARGET_ROOT116                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,116)
8336 #define CCM_TARGET_ROOT116_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,116)
8337 #define CCM_TARGET_ROOT116_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,116)
8338 #define CCM_TARGET_ROOT116_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,116)
8339 #define CCM_MISC116                              CCM_MISC_REG(CCM_BASE_PTR,116)
8340 #define CCM_MISC_ROOT116_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,116)
8341 #define CCM_MISC_ROOT116_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,116)
8342 #define CCM_MISC_ROOT116_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,116)
8343 #define CCM_POST116                              CCM_POST_REG(CCM_BASE_PTR,116)
8344 #define CCM_POST_ROOT116_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,116)
8345 #define CCM_POST_ROOT116_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,116)
8346 #define CCM_POST_ROOT116_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,116)
8347 #define CCM_PRE116                               CCM_PRE_REG(CCM_BASE_PTR,116)
8348 #define CCM_PRE_ROOT116_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,116)
8349 #define CCM_PRE_ROOT116_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,116)
8350 #define CCM_PRE_ROOT116_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,116)
8351 #define CCM_ACCESS_CTRL116                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,116)
8352 #define CCM_ACCESS_CTRL_ROOT116_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,116)
8353 #define CCM_ACCESS_CTRL_ROOT116_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,116)
8354 #define CCM_ACCESS_CTRL_ROOT116_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,116)
8355 #define CCM_TARGET_ROOT117                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,117)
8356 #define CCM_TARGET_ROOT117_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,117)
8357 #define CCM_TARGET_ROOT117_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,117)
8358 #define CCM_TARGET_ROOT117_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,117)
8359 #define CCM_MISC117                              CCM_MISC_REG(CCM_BASE_PTR,117)
8360 #define CCM_MISC_ROOT117_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,117)
8361 #define CCM_MISC_ROOT117_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,117)
8362 #define CCM_MISC_ROOT117_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,117)
8363 #define CCM_POST117                              CCM_POST_REG(CCM_BASE_PTR,117)
8364 #define CCM_POST_ROOT117_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,117)
8365 #define CCM_POST_ROOT117_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,117)
8366 #define CCM_POST_ROOT117_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,117)
8367 #define CCM_PRE117                               CCM_PRE_REG(CCM_BASE_PTR,117)
8368 #define CCM_PRE_ROOT117_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,117)
8369 #define CCM_PRE_ROOT117_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,117)
8370 #define CCM_PRE_ROOT117_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,117)
8371 #define CCM_ACCESS_CTRL117                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,117)
8372 #define CCM_ACCESS_CTRL_ROOT117_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,117)
8373 #define CCM_ACCESS_CTRL_ROOT117_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,117)
8374 #define CCM_ACCESS_CTRL_ROOT117_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,117)
8375 #define CCM_TARGET_ROOT118                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,118)
8376 #define CCM_TARGET_ROOT118_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,118)
8377 #define CCM_TARGET_ROOT118_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,118)
8378 #define CCM_TARGET_ROOT118_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,118)
8379 #define CCM_MISC118                              CCM_MISC_REG(CCM_BASE_PTR,118)
8380 #define CCM_MISC_ROOT118_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,118)
8381 #define CCM_MISC_ROOT118_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,118)
8382 #define CCM_MISC_ROOT118_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,118)
8383 #define CCM_POST118                              CCM_POST_REG(CCM_BASE_PTR,118)
8384 #define CCM_POST_ROOT118_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,118)
8385 #define CCM_POST_ROOT118_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,118)
8386 #define CCM_POST_ROOT118_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,118)
8387 #define CCM_PRE118                               CCM_PRE_REG(CCM_BASE_PTR,118)
8388 #define CCM_PRE_ROOT118_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,118)
8389 #define CCM_PRE_ROOT118_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,118)
8390 #define CCM_PRE_ROOT118_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,118)
8391 #define CCM_ACCESS_CTRL118                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,118)
8392 #define CCM_ACCESS_CTRL_ROOT118_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,118)
8393 #define CCM_ACCESS_CTRL_ROOT118_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,118)
8394 #define CCM_ACCESS_CTRL_ROOT118_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,118)
8395 #define CCM_TARGET_ROOT119                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,119)
8396 #define CCM_TARGET_ROOT119_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,119)
8397 #define CCM_TARGET_ROOT119_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,119)
8398 #define CCM_TARGET_ROOT119_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,119)
8399 #define CCM_MISC119                              CCM_MISC_REG(CCM_BASE_PTR,119)
8400 #define CCM_MISC_ROOT119_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,119)
8401 #define CCM_MISC_ROOT119_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,119)
8402 #define CCM_MISC_ROOT119_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,119)
8403 #define CCM_POST119                              CCM_POST_REG(CCM_BASE_PTR,119)
8404 #define CCM_POST_ROOT119_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,119)
8405 #define CCM_POST_ROOT119_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,119)
8406 #define CCM_POST_ROOT119_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,119)
8407 #define CCM_PRE119                               CCM_PRE_REG(CCM_BASE_PTR,119)
8408 #define CCM_PRE_ROOT119_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,119)
8409 #define CCM_PRE_ROOT119_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,119)
8410 #define CCM_PRE_ROOT119_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,119)
8411 #define CCM_ACCESS_CTRL119                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,119)
8412 #define CCM_ACCESS_CTRL_ROOT119_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,119)
8413 #define CCM_ACCESS_CTRL_ROOT119_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,119)
8414 #define CCM_ACCESS_CTRL_ROOT119_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,119)
8415 #define CCM_TARGET_ROOT120                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,120)
8416 #define CCM_TARGET_ROOT120_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,120)
8417 #define CCM_TARGET_ROOT120_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,120)
8418 #define CCM_TARGET_ROOT120_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,120)
8419 #define CCM_MISC120                              CCM_MISC_REG(CCM_BASE_PTR,120)
8420 #define CCM_MISC_ROOT120_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,120)
8421 #define CCM_MISC_ROOT120_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,120)
8422 #define CCM_MISC_ROOT120_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,120)
8423 #define CCM_POST120                              CCM_POST_REG(CCM_BASE_PTR,120)
8424 #define CCM_POST_ROOT120_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,120)
8425 #define CCM_POST_ROOT120_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,120)
8426 #define CCM_POST_ROOT120_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,120)
8427 #define CCM_PRE120                               CCM_PRE_REG(CCM_BASE_PTR,120)
8428 #define CCM_PRE_ROOT120_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,120)
8429 #define CCM_PRE_ROOT120_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,120)
8430 #define CCM_PRE_ROOT120_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,120)
8431 #define CCM_ACCESS_CTRL120                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,120)
8432 #define CCM_ACCESS_CTRL_ROOT120_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,120)
8433 #define CCM_ACCESS_CTRL_ROOT120_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,120)
8434 #define CCM_ACCESS_CTRL_ROOT120_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,120)
8435 #define CCM_TARGET_ROOT121                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,121)
8436 #define CCM_TARGET_ROOT121_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,121)
8437 #define CCM_TARGET_ROOT121_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,121)
8438 #define CCM_TARGET_ROOT121_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,121)
8439 #define CCM_MISC121                              CCM_MISC_REG(CCM_BASE_PTR,121)
8440 #define CCM_MISC_ROOT121_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,121)
8441 #define CCM_MISC_ROOT121_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,121)
8442 #define CCM_MISC_ROOT121_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,121)
8443 #define CCM_POST121                              CCM_POST_REG(CCM_BASE_PTR,121)
8444 #define CCM_POST_ROOT121_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,121)
8445 #define CCM_POST_ROOT121_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,121)
8446 #define CCM_POST_ROOT121_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,121)
8447 #define CCM_PRE121                               CCM_PRE_REG(CCM_BASE_PTR,121)
8448 #define CCM_PRE_ROOT121_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,121)
8449 #define CCM_PRE_ROOT121_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,121)
8450 #define CCM_PRE_ROOT121_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,121)
8451 #define CCM_ACCESS_CTRL121                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,121)
8452 #define CCM_ACCESS_CTRL_ROOT121_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,121)
8453 #define CCM_ACCESS_CTRL_ROOT121_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,121)
8454 #define CCM_ACCESS_CTRL_ROOT121_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,121)
8455 #define CCM_TARGET_ROOT122                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,122)
8456 #define CCM_TARGET_ROOT122_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,122)
8457 #define CCM_TARGET_ROOT122_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,122)
8458 #define CCM_TARGET_ROOT122_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,122)
8459 #define CCM_MISC122                              CCM_MISC_REG(CCM_BASE_PTR,122)
8460 #define CCM_MISC_ROOT122_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,122)
8461 #define CCM_MISC_ROOT122_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,122)
8462 #define CCM_MISC_ROOT122_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,122)
8463 #define CCM_POST122                              CCM_POST_REG(CCM_BASE_PTR,122)
8464 #define CCM_POST_ROOT122_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,122)
8465 #define CCM_POST_ROOT122_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,122)
8466 #define CCM_POST_ROOT122_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,122)
8467 #define CCM_PRE122                               CCM_PRE_REG(CCM_BASE_PTR,122)
8468 #define CCM_PRE_ROOT122_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,122)
8469 #define CCM_PRE_ROOT122_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,122)
8470 #define CCM_PRE_ROOT122_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,122)
8471 #define CCM_ACCESS_CTRL122                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,122)
8472 #define CCM_ACCESS_CTRL_ROOT122_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,122)
8473 #define CCM_ACCESS_CTRL_ROOT122_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,122)
8474 #define CCM_ACCESS_CTRL_ROOT122_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,122)
8475 #define CCM_TARGET_ROOT123                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,123)
8476 #define CCM_TARGET_ROOT123_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,123)
8477 #define CCM_TARGET_ROOT123_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,123)
8478 #define CCM_TARGET_ROOT123_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,123)
8479 #define CCM_MISC123                              CCM_MISC_REG(CCM_BASE_PTR,123)
8480 #define CCM_MISC_ROOT123_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,123)
8481 #define CCM_MISC_ROOT123_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,123)
8482 #define CCM_MISC_ROOT123_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,123)
8483 #define CCM_POST123                              CCM_POST_REG(CCM_BASE_PTR,123)
8484 #define CCM_POST_ROOT123_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,123)
8485 #define CCM_POST_ROOT123_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,123)
8486 #define CCM_POST_ROOT123_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,123)
8487 #define CCM_PRE123                               CCM_PRE_REG(CCM_BASE_PTR,123)
8488 #define CCM_PRE_ROOT123_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,123)
8489 #define CCM_PRE_ROOT123_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,123)
8490 #define CCM_PRE_ROOT123_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,123)
8491 #define CCM_ACCESS_CTRL123                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,123)
8492 #define CCM_ACCESS_CTRL_ROOT123_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,123)
8493 #define CCM_ACCESS_CTRL_ROOT123_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,123)
8494 #define CCM_ACCESS_CTRL_ROOT123_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,123)
8495 #define CCM_TARGET_ROOT124                       CCM_TARGET_ROOT_REG(CCM_BASE_PTR,124)
8496 #define CCM_TARGET_ROOT124_SET                   CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,124)
8497 #define CCM_TARGET_ROOT124_CLR                   CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,124)
8498 #define CCM_TARGET_ROOT124_TOG                   CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,124)
8499 #define CCM_MISC124                              CCM_MISC_REG(CCM_BASE_PTR,124)
8500 #define CCM_MISC_ROOT124_SET                     CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,124)
8501 #define CCM_MISC_ROOT124_CLR                     CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,124)
8502 #define CCM_MISC_ROOT124_TOG                     CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,124)
8503 #define CCM_POST124                              CCM_POST_REG(CCM_BASE_PTR,124)
8504 #define CCM_POST_ROOT124_SET                     CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,124)
8505 #define CCM_POST_ROOT124_CLR                     CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,124)
8506 #define CCM_POST_ROOT124_TOG                     CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,124)
8507 #define CCM_PRE124                               CCM_PRE_REG(CCM_BASE_PTR,124)
8508 #define CCM_PRE_ROOT124_SET                      CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,124)
8509 #define CCM_PRE_ROOT124_CLR                      CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,124)
8510 #define CCM_PRE_ROOT124_TOG                      CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,124)
8511 #define CCM_ACCESS_CTRL124                       CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,124)
8512 #define CCM_ACCESS_CTRL_ROOT124_SET              CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,124)
8513 #define CCM_ACCESS_CTRL_ROOT124_CLR              CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,124)
8514 #define CCM_ACCESS_CTRL_ROOT124_TOG              CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,124)
8515 /* CCM - Register array accessors */
8516 #define CCM_PLL_CTRL(index)                      CCM_PLL_CTRL_REG(CCM_BASE_PTR,index)
8517 #define CCM_PLL_CTRL_SET(index)                  CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,index)
8518 #define CCM_PLL_CTRL_CLR(index)                  CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,index)
8519 #define CCM_PLL_CTRL_TOG(index)                  CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,index)
8520 #define CCM_CCGR(index)                          CCM_CCGR_REG(CCM_BASE_PTR,index)
8521 #define CCM_CCGR_SET(index)                      CCM_CCGR_SET_REG(CCM_BASE_PTR,index)
8522 #define CCM_CCGR_CLR(index)                      CCM_CCGR_CLR_REG(CCM_BASE_PTR,index)
8523 #define CCM_CCGR_TOG(index)                      CCM_CCGR_TOG_REG(CCM_BASE_PTR,index)
8524 #define CCM_TARGET_ROOT(index)                   CCM_TARGET_ROOT_REG(CCM_BASE_PTR,index)
8525 #define CCM_TARGET_ROOT_SET(index)               CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,index)
8526 #define CCM_TARGET_ROOT_CLR(index)               CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,index)
8527 #define CCM_TARGET_ROOT_TOG(index)               CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,index)
8528 #define CCM_MISC(index)                          CCM_MISC_REG(CCM_BASE_PTR,index)
8529 #define CCM_MISC_ROOT_SET(index)                 CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,index)
8530 #define CCM_MISC_ROOT_CLR(index)                 CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,index)
8531 #define CCM_MISC_ROOT_TOG(index)                 CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,index)
8532 #define CCM_POST(index)                          CCM_POST_REG(CCM_BASE_PTR,index)
8533 #define CCM_POST_ROOT_SET(index)                 CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,index)
8534 #define CCM_POST_ROOT_CLR(index)                 CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,index)
8535 #define CCM_POST_ROOT_TOG(index)                 CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,index)
8536 #define CCM_PRE(index)                           CCM_PRE_REG(CCM_BASE_PTR,index)
8537 #define CCM_PRE_ROOT_SET(index)                  CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,index)
8538 #define CCM_PRE_ROOT_CLR(index)                  CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,index)
8539 #define CCM_PRE_ROOT_TOG(index)                  CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,index)
8540 #define CCM_ACCESS_CTRL(index)                   CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,index)
8541 #define CCM_ACCESS_CTRL_ROOT_SET(index)          CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,index)
8542 #define CCM_ACCESS_CTRL_ROOT_CLR(index)          CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,index)
8543 #define CCM_ACCESS_CTRL_ROOT_TOG(index)          CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,index)
8544 /*!
8545  * @}
8546  */ /* end of group CCM_Register_Accessor_Macros */
8547 
8548 
8549 /*!
8550  * @}
8551  */ /* end of group CCM_Peripheral */
8552 
8553 /* ----------------------------------------------------------------------------
8554    -- CCM_ANALOG Peripheral Access Layer
8555    ---------------------------------------------------------------------------- */
8556 
8557 /*!
8558  * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
8559  * @{
8560  */
8561 
8562 /** CCM_ANALOG - Register Layout Typedef */
8563 typedef struct {
8564   uint8_t RESERVED_0[96];
8565   __IO  uint32_t PLL_ARM;                                /**< Anadig ARM PLL control Register, offset: 0x60 */
8566   __IO  uint32_t PLL_ARM_SET;                            /**< Anadig ARM PLL control Register, offset: 0x64 */
8567   __IO  uint32_t PLL_ARM_CLR;                            /**< Anadig ARM PLL control Register, offset: 0x68 */
8568   __IO  uint32_t PLL_ARM_TOG;                            /**< Anadig ARM PLL control Register, offset: 0x6C */
8569   __IO  uint32_t PLL_DDR;                                /**< Anadig DDR PLL Control Register, offset: 0x70 */
8570   __IO  uint32_t PLL_DDR_SET;                            /**< Anadig DDR PLL Control Register, offset: 0x74 */
8571   __IO  uint32_t PLL_DDR_CLR;                            /**< Anadig DDR PLL Control Register, offset: 0x78 */
8572   __IO  uint32_t PLL_DDR_TOG;                            /**< Anadig DDR PLL Control Register, offset: 0x7C */
8573   __IO  uint32_t PLL_DDR_SS;                             /**< DDR PLL Spread Spectrum Register., offset: 0x80 */
8574   uint8_t RESERVED_1[12];
8575   __IO  uint32_t PLL_DDR_NUM;                            /**< Numerator of DDR PLL Fractional Loop Divider Register, offset: 0x90 */
8576   uint8_t RESERVED_2[12];
8577   __IO  uint32_t PLL_DDR_DENOM;                          /**< Denominator of DDR PLL Fractional Loop Divider Register, offset: 0xA0 */
8578   uint8_t RESERVED_3[12];
8579   __IO  uint32_t PLL_480;                                /**< Anadig 480MHz PLL Control Register, offset: 0xB0 */
8580   __IO  uint32_t PLL_480_SET;                            /**< Anadig 480MHz PLL Control Register, offset: 0xB4 */
8581   __IO  uint32_t PLL_480_CLR;                            /**< Anadig 480MHz PLL Control Register, offset: 0xB8 */
8582   __IO  uint32_t PLL_480_TOG;                            /**< Anadig 480MHz PLL Control Register, offset: 0xBC */
8583   __IO  uint32_t PFD_480A;                               /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xC0 */
8584   __IO  uint32_t PFD_480A_SET;                           /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xC4 */
8585   __IO  uint32_t PFD_480A_CLR;                           /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xC8 */
8586   __IO  uint32_t PFD_480A_TOG;                           /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xCC */
8587   __IO  uint32_t PFD_480B;                               /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xD0 */
8588   __IO  uint32_t PFD_480B_SET;                           /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xD4 */
8589   __IO  uint32_t PFD_480B_CLR;                           /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xD8 */
8590   __IO  uint32_t PFD_480B_TOG;                           /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xDC */
8591   __IO  uint32_t PLL_ENET;                               /**< Anadig ENET PLL Control Register, offset: 0xE0 */
8592   __IO  uint32_t PLL_ENET_SET;                           /**< Anadig ENET PLL Control Register, offset: 0xE4 */
8593   __IO  uint32_t PLL_ENET_CLR;                           /**< Anadig ENET PLL Control Register, offset: 0xE8 */
8594   __IO  uint32_t PLL_ENET_TOG;                           /**< Anadig ENET PLL Control Register, offset: 0xEC */
8595   __IO  uint32_t PLL_AUDIO;                              /**< Anadig Audio PLL control Register, offset: 0xF0 */
8596   __IO  uint32_t PLL_AUDIO_SET;                          /**< Anadig Audio PLL control Register, offset: 0xF4 */
8597   __IO  uint32_t PLL_AUDIO_CLR;                          /**< Anadig Audio PLL control Register, offset: 0xF8 */
8598   __IO  uint32_t PLL_AUDIO_TOG;                          /**< Anadig Audio PLL control Register, offset: 0xFC */
8599   __IO  uint32_t PLL_AUDIO_SS;                           /**< Audio PLL Spread Spectrum Register., offset: 0x100 */
8600   uint8_t RESERVED_4[12];
8601   __IO  uint32_t PLL_AUDIO_NUM;                          /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x110 */
8602   uint8_t RESERVED_5[12];
8603   __IO  uint32_t PLL_AUDIO_DENOM;                        /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x120 */
8604   uint8_t RESERVED_6[12];
8605   __IO  uint32_t PLL_VIDEO;                              /**< Anadig Video PLL control Register, offset: 0x130 */
8606   __IO  uint32_t PLL_VIDEO_SET;                          /**< Anadig Video PLL control Register, offset: 0x134 */
8607   __IO  uint32_t PLL_VIDEO_CLR;                          /**< Anadig Video PLL control Register, offset: 0x138 */
8608   __IO  uint32_t PLL_VIDEO_TOG;                          /**< Anadig Video PLL control Register, offset: 0x13C */
8609   __IO  uint32_t PLL_VIDEO_SS;                           /**< Video PLL Spread Spectrum Register., offset: 0x140 */
8610   uint8_t RESERVED_7[12];
8611   __IO  uint32_t PLL_VIDEO_NUM;                          /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0x150 */
8612   uint8_t RESERVED_8[12];
8613   __IO  uint32_t PLL_VIDEO_DENOM;                        /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0x160 */
8614   uint8_t RESERVED_9[12];
8615   __IO  uint32_t CLK_MISC0;                              /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x170 */
8616   __IO  uint32_t CLK_MISC0_SET;                          /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x174 */
8617   __IO  uint32_t CLK_MISC0_CLR;                          /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x178 */
8618   __IO  uint32_t CLK_MISC0_TOG;                          /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x17C */
8619 } CCM_ANALOG_Type, *CCM_ANALOG_MemMapPtr;
8620 /* ----------------------------------------------------------------------------
8621    -- CCM_ANALOG - Register accessor macros
8622    ---------------------------------------------------------------------------- */
8623 
8624 /*!
8625  * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros
8626  * @{
8627  */
8628 
8629 
8630 /* CCM_ANALOG - Register accessors */
8631 #define CCM_ANALOG_PLL_ARM_REG(base)             ((base)->PLL_ARM)
8632 #define CCM_ANALOG_PLL_ARM_SET_REG(base)         ((base)->PLL_ARM_SET)
8633 #define CCM_ANALOG_PLL_ARM_CLR_REG(base)         ((base)->PLL_ARM_CLR)
8634 #define CCM_ANALOG_PLL_ARM_TOG_REG(base)         ((base)->PLL_ARM_TOG)
8635 #define CCM_ANALOG_PLL_DDR_REG(base)             ((base)->PLL_DDR)
8636 #define CCM_ANALOG_PLL_DDR_SET_REG(base)         ((base)->PLL_DDR_SET)
8637 #define CCM_ANALOG_PLL_DDR_CLR_REG(base)         ((base)->PLL_DDR_CLR)
8638 #define CCM_ANALOG_PLL_DDR_TOG_REG(base)         ((base)->PLL_DDR_TOG)
8639 #define CCM_ANALOG_PLL_DDR_SS_REG(base)          ((base)->PLL_DDR_SS)
8640 #define CCM_ANALOG_PLL_DDR_NUM_REG(base)         ((base)->PLL_DDR_NUM)
8641 #define CCM_ANALOG_PLL_DDR_DENOM_REG(base)       ((base)->PLL_DDR_DENOM)
8642 #define CCM_ANALOG_PLL_480_REG(base)             ((base)->PLL_480)
8643 #define CCM_ANALOG_PLL_480_SET_REG(base)         ((base)->PLL_480_SET)
8644 #define CCM_ANALOG_PLL_480_CLR_REG(base)         ((base)->PLL_480_CLR)
8645 #define CCM_ANALOG_PLL_480_TOG_REG(base)         ((base)->PLL_480_TOG)
8646 #define CCM_ANALOG_PFD_480A_REG(base)            ((base)->PFD_480A)
8647 #define CCM_ANALOG_PFD_480A_SET_REG(base)        ((base)->PFD_480A_SET)
8648 #define CCM_ANALOG_PFD_480A_CLR_REG(base)        ((base)->PFD_480A_CLR)
8649 #define CCM_ANALOG_PFD_480A_TOG_REG(base)        ((base)->PFD_480A_TOG)
8650 #define CCM_ANALOG_PFD_480B_REG(base)            ((base)->PFD_480B)
8651 #define CCM_ANALOG_PFD_480B_SET_REG(base)        ((base)->PFD_480B_SET)
8652 #define CCM_ANALOG_PFD_480B_CLR_REG(base)        ((base)->PFD_480B_CLR)
8653 #define CCM_ANALOG_PFD_480B_TOG_REG(base)        ((base)->PFD_480B_TOG)
8654 #define CCM_ANALOG_PLL_ENET_REG(base)            ((base)->PLL_ENET)
8655 #define CCM_ANALOG_PLL_ENET_SET_REG(base)        ((base)->PLL_ENET_SET)
8656 #define CCM_ANALOG_PLL_ENET_CLR_REG(base)        ((base)->PLL_ENET_CLR)
8657 #define CCM_ANALOG_PLL_ENET_TOG_REG(base)        ((base)->PLL_ENET_TOG)
8658 #define CCM_ANALOG_PLL_AUDIO_REG(base)           ((base)->PLL_AUDIO)
8659 #define CCM_ANALOG_PLL_AUDIO_SET_REG(base)       ((base)->PLL_AUDIO_SET)
8660 #define CCM_ANALOG_PLL_AUDIO_CLR_REG(base)       ((base)->PLL_AUDIO_CLR)
8661 #define CCM_ANALOG_PLL_AUDIO_TOG_REG(base)       ((base)->PLL_AUDIO_TOG)
8662 #define CCM_ANALOG_PLL_AUDIO_SS_REG(base)        ((base)->PLL_AUDIO_SS)
8663 #define CCM_ANALOG_PLL_AUDIO_NUM_REG(base)       ((base)->PLL_AUDIO_NUM)
8664 #define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base)     ((base)->PLL_AUDIO_DENOM)
8665 #define CCM_ANALOG_PLL_VIDEO_REG(base)           ((base)->PLL_VIDEO)
8666 #define CCM_ANALOG_PLL_VIDEO_SET_REG(base)       ((base)->PLL_VIDEO_SET)
8667 #define CCM_ANALOG_PLL_VIDEO_CLR_REG(base)       ((base)->PLL_VIDEO_CLR)
8668 #define CCM_ANALOG_PLL_VIDEO_TOG_REG(base)       ((base)->PLL_VIDEO_TOG)
8669 #define CCM_ANALOG_PLL_VIDEO_SS_REG(base)        ((base)->PLL_VIDEO_SS)
8670 #define CCM_ANALOG_PLL_VIDEO_NUM_REG(base)       ((base)->PLL_VIDEO_NUM)
8671 #define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base)     ((base)->PLL_VIDEO_DENOM)
8672 #define CCM_ANALOG_CLK_MISC0_REG(base)           ((base)->CLK_MISC0)
8673 #define CCM_ANALOG_CLK_MISC0_SET_REG(base)       ((base)->CLK_MISC0_SET)
8674 #define CCM_ANALOG_CLK_MISC0_CLR_REG(base)       ((base)->CLK_MISC0_CLR)
8675 #define CCM_ANALOG_CLK_MISC0_TOG_REG(base)       ((base)->CLK_MISC0_TOG)
8676 
8677 /*!
8678  * @}
8679  */ /* end of group CCM_ANALOG_Register_Accessor_Macros */
8680 /* ----------------------------------------------------------------------------
8681    -- CCM_ANALOG Register Masks
8682    ---------------------------------------------------------------------------- */
8683 
8684 /*!
8685  * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
8686  * @{
8687  */
8688 
8689 /* PLL_ARM Bit Fields */
8690 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK       0x7Fu
8691 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT      0
8692 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
8693 #define CCM_ANALOG_PLL_ARM_HALF_LF_MASK          0x80u
8694 #define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT         7
8695 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK        0x100u
8696 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT       8
8697 #define CCM_ANALOG_PLL_ARM_HALF_CP_MASK          0x200u
8698 #define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT         9
8699 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK        0x400u
8700 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT       10
8701 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK    0x800u
8702 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT   11
8703 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK        0x1000u
8704 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT       12
8705 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK       0x2000u
8706 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT      13
8707 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK   0xC000u
8708 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT  14
8709 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
8710 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK           0x10000u
8711 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT          16
8712 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK         0x20000u
8713 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT        17
8714 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK   0x40000u
8715 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT  18
8716 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK          0x80000u
8717 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT         19
8718 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000u
8719 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20
8720 #define CCM_ANALOG_PLL_ARM_RSVD0_MASK            0x7FE00000u
8721 #define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT           21
8722 #define CCM_ANALOG_PLL_ARM_RSVD0(x)              (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_RSVD0_MASK)
8723 #define CCM_ANALOG_PLL_ARM_LOCK_MASK             0x80000000u
8724 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT            31
8725 /* PLL_ARM_SET Bit Fields */
8726 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK   0x7Fu
8727 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT  0
8728 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
8729 #define CCM_ANALOG_PLL_ARM_SET_HALF_LF_MASK      0x80u
8730 #define CCM_ANALOG_PLL_ARM_SET_HALF_LF_SHIFT     7
8731 #define CCM_ANALOG_PLL_ARM_SET_DOUBLE_LF_MASK    0x100u
8732 #define CCM_ANALOG_PLL_ARM_SET_DOUBLE_LF_SHIFT   8
8733 #define CCM_ANALOG_PLL_ARM_SET_HALF_CP_MASK      0x200u
8734 #define CCM_ANALOG_PLL_ARM_SET_HALF_CP_SHIFT     9
8735 #define CCM_ANALOG_PLL_ARM_SET_DOUBLE_CP_MASK    0x400u
8736 #define CCM_ANALOG_PLL_ARM_SET_DOUBLE_CP_SHIFT   10
8737 #define CCM_ANALOG_PLL_ARM_SET_HOLD_RING_OFF_MASK 0x800u
8738 #define CCM_ANALOG_PLL_ARM_SET_HOLD_RING_OFF_SHIFT 11
8739 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK    0x1000u
8740 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT   12
8741 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_CLK_MASK   0x2000u
8742 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_CLK_SHIFT  13
8743 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK 0xC000u
8744 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT 14
8745 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
8746 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK       0x10000u
8747 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT      16
8748 #define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_MASK     0x20000u
8749 #define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_SHIFT    17
8750 #define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_MASK 0x40000u
8751 #define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_SHIFT 18
8752 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK      0x80000u
8753 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT     19
8754 #define CCM_ANALOG_PLL_ARM_SET_PLL_ARM_OVERRIDE_MASK 0x100000u
8755 #define CCM_ANALOG_PLL_ARM_SET_PLL_ARM_OVERRIDE_SHIFT 20
8756 #define CCM_ANALOG_PLL_ARM_SET_RSVD0_MASK        0x7FE00000u
8757 #define CCM_ANALOG_PLL_ARM_SET_RSVD0_SHIFT       21
8758 #define CCM_ANALOG_PLL_ARM_SET_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_SET_RSVD0_MASK)
8759 #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK         0x80000000u
8760 #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT        31
8761 /* PLL_ARM_CLR Bit Fields */
8762 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK   0x7Fu
8763 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT  0
8764 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
8765 #define CCM_ANALOG_PLL_ARM_CLR_HALF_LF_MASK      0x80u
8766 #define CCM_ANALOG_PLL_ARM_CLR_HALF_LF_SHIFT     7
8767 #define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_LF_MASK    0x100u
8768 #define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_LF_SHIFT   8
8769 #define CCM_ANALOG_PLL_ARM_CLR_HALF_CP_MASK      0x200u
8770 #define CCM_ANALOG_PLL_ARM_CLR_HALF_CP_SHIFT     9
8771 #define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_CP_MASK    0x400u
8772 #define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_CP_SHIFT   10
8773 #define CCM_ANALOG_PLL_ARM_CLR_HOLD_RING_OFF_MASK 0x800u
8774 #define CCM_ANALOG_PLL_ARM_CLR_HOLD_RING_OFF_SHIFT 11
8775 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK    0x1000u
8776 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT   12
8777 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_CLK_MASK   0x2000u
8778 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_CLK_SHIFT  13
8779 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK 0xC000u
8780 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT 14
8781 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
8782 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK       0x10000u
8783 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT      16
8784 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_MASK     0x20000u
8785 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_SHIFT    17
8786 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_MASK 0x40000u
8787 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_SHIFT 18
8788 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK      0x80000u
8789 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT     19
8790 #define CCM_ANALOG_PLL_ARM_CLR_PLL_ARM_OVERRIDE_MASK 0x100000u
8791 #define CCM_ANALOG_PLL_ARM_CLR_PLL_ARM_OVERRIDE_SHIFT 20
8792 #define CCM_ANALOG_PLL_ARM_CLR_RSVD0_MASK        0x7FE00000u
8793 #define CCM_ANALOG_PLL_ARM_CLR_RSVD0_SHIFT       21
8794 #define CCM_ANALOG_PLL_ARM_CLR_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_RSVD0_MASK)
8795 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK         0x80000000u
8796 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT        31
8797 /* PLL_ARM_TOG Bit Fields */
8798 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK   0x7Fu
8799 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT  0
8800 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
8801 #define CCM_ANALOG_PLL_ARM_TOG_HALF_LF_MASK      0x80u
8802 #define CCM_ANALOG_PLL_ARM_TOG_HALF_LF_SHIFT     7
8803 #define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_LF_MASK    0x100u
8804 #define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_LF_SHIFT   8
8805 #define CCM_ANALOG_PLL_ARM_TOG_HALF_CP_MASK      0x200u
8806 #define CCM_ANALOG_PLL_ARM_TOG_HALF_CP_SHIFT     9
8807 #define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_CP_MASK    0x400u
8808 #define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_CP_SHIFT   10
8809 #define CCM_ANALOG_PLL_ARM_TOG_HOLD_RING_OFF_MASK 0x800u
8810 #define CCM_ANALOG_PLL_ARM_TOG_HOLD_RING_OFF_SHIFT 11
8811 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK    0x1000u
8812 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT   12
8813 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_CLK_MASK   0x2000u
8814 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_CLK_SHIFT  13
8815 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK 0xC000u
8816 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT 14
8817 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
8818 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK       0x10000u
8819 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT      16
8820 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_MASK     0x20000u
8821 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_SHIFT    17
8822 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_MASK 0x40000u
8823 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_SHIFT 18
8824 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK      0x80000u
8825 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT     19
8826 #define CCM_ANALOG_PLL_ARM_TOG_PLL_ARM_OVERRIDE_MASK 0x100000u
8827 #define CCM_ANALOG_PLL_ARM_TOG_PLL_ARM_OVERRIDE_SHIFT 20
8828 #define CCM_ANALOG_PLL_ARM_TOG_RSVD0_MASK        0x7FE00000u
8829 #define CCM_ANALOG_PLL_ARM_TOG_RSVD0_SHIFT       21
8830 #define CCM_ANALOG_PLL_ARM_TOG_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_RSVD0_MASK)
8831 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK         0x80000000u
8832 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT        31
8833 /* PLL_DDR Bit Fields */
8834 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK       0x7Fu
8835 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT      0
8836 #define CCM_ANALOG_PLL_DDR_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK)
8837 #define CCM_ANALOG_PLL_DDR_HALF_LF_MASK          0x80u
8838 #define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT         7
8839 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK        0x100u
8840 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT       8
8841 #define CCM_ANALOG_PLL_DDR_HALF_CP_MASK          0x200u
8842 #define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT         9
8843 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK        0x400u
8844 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT       10
8845 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK    0x800u
8846 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT   11
8847 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK  0x1000u
8848 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12
8849 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK       0x2000u
8850 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT      13
8851 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK   0xC000u
8852 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT  14
8853 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK)
8854 #define CCM_ANALOG_PLL_DDR_BYPASS_MASK           0x10000u
8855 #define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT          16
8856 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK    0x20000u
8857 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT   17
8858 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK    0x40000u
8859 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT   18
8860 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000u
8861 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19
8862 #define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK        0x100000u
8863 #define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT       20
8864 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK  0x600000u
8865 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21
8866 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK)
8867 #define CCM_ANALOG_PLL_DDR_RSVD1_MASK            0x7F800000u
8868 #define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT           23
8869 #define CCM_ANALOG_PLL_DDR_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_RSVD1_MASK)
8870 #define CCM_ANALOG_PLL_DDR_LOCK_MASK             0x80000000u
8871 #define CCM_ANALOG_PLL_DDR_LOCK_SHIFT            31
8872 /* PLL_DDR_SET Bit Fields */
8873 #define CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_MASK   0x7Fu
8874 #define CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_SHIFT  0
8875 #define CCM_ANALOG_PLL_DDR_SET_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_MASK)
8876 #define CCM_ANALOG_PLL_DDR_SET_HALF_LF_MASK      0x80u
8877 #define CCM_ANALOG_PLL_DDR_SET_HALF_LF_SHIFT     7
8878 #define CCM_ANALOG_PLL_DDR_SET_DOUBLE_LF_MASK    0x100u
8879 #define CCM_ANALOG_PLL_DDR_SET_DOUBLE_LF_SHIFT   8
8880 #define CCM_ANALOG_PLL_DDR_SET_HALF_CP_MASK      0x200u
8881 #define CCM_ANALOG_PLL_DDR_SET_HALF_CP_SHIFT     9
8882 #define CCM_ANALOG_PLL_DDR_SET_DOUBLE_CP_MASK    0x400u
8883 #define CCM_ANALOG_PLL_DDR_SET_DOUBLE_CP_SHIFT   10
8884 #define CCM_ANALOG_PLL_DDR_SET_HOLD_RING_OFF_MASK 0x800u
8885 #define CCM_ANALOG_PLL_DDR_SET_HOLD_RING_OFF_SHIFT 11
8886 #define CCM_ANALOG_PLL_DDR_SET_DIV2_ENABLE_CLK_MASK 0x1000u
8887 #define CCM_ANALOG_PLL_DDR_SET_DIV2_ENABLE_CLK_SHIFT 12
8888 #define CCM_ANALOG_PLL_DDR_SET_ENABLE_CLK_MASK   0x2000u
8889 #define CCM_ANALOG_PLL_DDR_SET_ENABLE_CLK_SHIFT  13
8890 #define CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_MASK 0xC000u
8891 #define CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_SHIFT 14
8892 #define CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_MASK)
8893 #define CCM_ANALOG_PLL_DDR_SET_BYPASS_MASK       0x10000u
8894 #define CCM_ANALOG_PLL_DDR_SET_BYPASS_SHIFT      16
8895 #define CCM_ANALOG_PLL_DDR_SET_DITHER_ENABLE_MASK 0x20000u
8896 #define CCM_ANALOG_PLL_DDR_SET_DITHER_ENABLE_SHIFT 17
8897 #define CCM_ANALOG_PLL_DDR_SET_PFD_OFFSET_EN_MASK 0x40000u
8898 #define CCM_ANALOG_PLL_DDR_SET_PFD_OFFSET_EN_SHIFT 18
8899 #define CCM_ANALOG_PLL_DDR_SET_PLL_DDR_OVERRIDE_MASK 0x80000u
8900 #define CCM_ANALOG_PLL_DDR_SET_PLL_DDR_OVERRIDE_SHIFT 19
8901 #define CCM_ANALOG_PLL_DDR_SET_POWERDOWN_MASK    0x100000u
8902 #define CCM_ANALOG_PLL_DDR_SET_POWERDOWN_SHIFT   20
8903 #define CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_MASK 0x600000u
8904 #define CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_SHIFT 21
8905 #define CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_MASK)
8906 #define CCM_ANALOG_PLL_DDR_SET_RSVD1_MASK        0x7F800000u
8907 #define CCM_ANALOG_PLL_DDR_SET_RSVD1_SHIFT       23
8908 #define CCM_ANALOG_PLL_DDR_SET_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_SET_RSVD1_MASK)
8909 #define CCM_ANALOG_PLL_DDR_SET_LOCK_MASK         0x80000000u
8910 #define CCM_ANALOG_PLL_DDR_SET_LOCK_SHIFT        31
8911 /* PLL_DDR_CLR Bit Fields */
8912 #define CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_MASK   0x7Fu
8913 #define CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_SHIFT  0
8914 #define CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_MASK)
8915 #define CCM_ANALOG_PLL_DDR_CLR_HALF_LF_MASK      0x80u
8916 #define CCM_ANALOG_PLL_DDR_CLR_HALF_LF_SHIFT     7
8917 #define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_LF_MASK    0x100u
8918 #define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_LF_SHIFT   8
8919 #define CCM_ANALOG_PLL_DDR_CLR_HALF_CP_MASK      0x200u
8920 #define CCM_ANALOG_PLL_DDR_CLR_HALF_CP_SHIFT     9
8921 #define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_CP_MASK    0x400u
8922 #define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_CP_SHIFT   10
8923 #define CCM_ANALOG_PLL_DDR_CLR_HOLD_RING_OFF_MASK 0x800u
8924 #define CCM_ANALOG_PLL_DDR_CLR_HOLD_RING_OFF_SHIFT 11
8925 #define CCM_ANALOG_PLL_DDR_CLR_DIV2_ENABLE_CLK_MASK 0x1000u
8926 #define CCM_ANALOG_PLL_DDR_CLR_DIV2_ENABLE_CLK_SHIFT 12
8927 #define CCM_ANALOG_PLL_DDR_CLR_ENABLE_CLK_MASK   0x2000u
8928 #define CCM_ANALOG_PLL_DDR_CLR_ENABLE_CLK_SHIFT  13
8929 #define CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_MASK 0xC000u
8930 #define CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_SHIFT 14
8931 #define CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_MASK)
8932 #define CCM_ANALOG_PLL_DDR_CLR_BYPASS_MASK       0x10000u
8933 #define CCM_ANALOG_PLL_DDR_CLR_BYPASS_SHIFT      16
8934 #define CCM_ANALOG_PLL_DDR_CLR_DITHER_ENABLE_MASK 0x20000u
8935 #define CCM_ANALOG_PLL_DDR_CLR_DITHER_ENABLE_SHIFT 17
8936 #define CCM_ANALOG_PLL_DDR_CLR_PFD_OFFSET_EN_MASK 0x40000u
8937 #define CCM_ANALOG_PLL_DDR_CLR_PFD_OFFSET_EN_SHIFT 18
8938 #define CCM_ANALOG_PLL_DDR_CLR_PLL_DDR_OVERRIDE_MASK 0x80000u
8939 #define CCM_ANALOG_PLL_DDR_CLR_PLL_DDR_OVERRIDE_SHIFT 19
8940 #define CCM_ANALOG_PLL_DDR_CLR_POWERDOWN_MASK    0x100000u
8941 #define CCM_ANALOG_PLL_DDR_CLR_POWERDOWN_SHIFT   20
8942 #define CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_MASK 0x600000u
8943 #define CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_SHIFT 21
8944 #define CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_MASK)
8945 #define CCM_ANALOG_PLL_DDR_CLR_RSVD1_MASK        0x7F800000u
8946 #define CCM_ANALOG_PLL_DDR_CLR_RSVD1_SHIFT       23
8947 #define CCM_ANALOG_PLL_DDR_CLR_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_RSVD1_MASK)
8948 #define CCM_ANALOG_PLL_DDR_CLR_LOCK_MASK         0x80000000u
8949 #define CCM_ANALOG_PLL_DDR_CLR_LOCK_SHIFT        31
8950 /* PLL_DDR_TOG Bit Fields */
8951 #define CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_MASK   0x7Fu
8952 #define CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_SHIFT  0
8953 #define CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_MASK)
8954 #define CCM_ANALOG_PLL_DDR_TOG_HALF_LF_MASK      0x80u
8955 #define CCM_ANALOG_PLL_DDR_TOG_HALF_LF_SHIFT     7
8956 #define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_LF_MASK    0x100u
8957 #define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_LF_SHIFT   8
8958 #define CCM_ANALOG_PLL_DDR_TOG_HALF_CP_MASK      0x200u
8959 #define CCM_ANALOG_PLL_DDR_TOG_HALF_CP_SHIFT     9
8960 #define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_CP_MASK    0x400u
8961 #define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_CP_SHIFT   10
8962 #define CCM_ANALOG_PLL_DDR_TOG_HOLD_RING_OFF_MASK 0x800u
8963 #define CCM_ANALOG_PLL_DDR_TOG_HOLD_RING_OFF_SHIFT 11
8964 #define CCM_ANALOG_PLL_DDR_TOG_DIV2_ENABLE_CLK_MASK 0x1000u
8965 #define CCM_ANALOG_PLL_DDR_TOG_DIV2_ENABLE_CLK_SHIFT 12
8966 #define CCM_ANALOG_PLL_DDR_TOG_ENABLE_CLK_MASK   0x2000u
8967 #define CCM_ANALOG_PLL_DDR_TOG_ENABLE_CLK_SHIFT  13
8968 #define CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_MASK 0xC000u
8969 #define CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_SHIFT 14
8970 #define CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_MASK)
8971 #define CCM_ANALOG_PLL_DDR_TOG_BYPASS_MASK       0x10000u
8972 #define CCM_ANALOG_PLL_DDR_TOG_BYPASS_SHIFT      16
8973 #define CCM_ANALOG_PLL_DDR_TOG_DITHER_ENABLE_MASK 0x20000u
8974 #define CCM_ANALOG_PLL_DDR_TOG_DITHER_ENABLE_SHIFT 17
8975 #define CCM_ANALOG_PLL_DDR_TOG_PFD_OFFSET_EN_MASK 0x40000u
8976 #define CCM_ANALOG_PLL_DDR_TOG_PFD_OFFSET_EN_SHIFT 18
8977 #define CCM_ANALOG_PLL_DDR_TOG_PLL_DDR_OVERRIDE_MASK 0x80000u
8978 #define CCM_ANALOG_PLL_DDR_TOG_PLL_DDR_OVERRIDE_SHIFT 19
8979 #define CCM_ANALOG_PLL_DDR_TOG_POWERDOWN_MASK    0x100000u
8980 #define CCM_ANALOG_PLL_DDR_TOG_POWERDOWN_SHIFT   20
8981 #define CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_MASK 0x600000u
8982 #define CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_SHIFT 21
8983 #define CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_MASK)
8984 #define CCM_ANALOG_PLL_DDR_TOG_RSVD1_MASK        0x7F800000u
8985 #define CCM_ANALOG_PLL_DDR_TOG_RSVD1_SHIFT       23
8986 #define CCM_ANALOG_PLL_DDR_TOG_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_RSVD1_MASK)
8987 #define CCM_ANALOG_PLL_DDR_TOG_LOCK_MASK         0x80000000u
8988 #define CCM_ANALOG_PLL_DDR_TOG_LOCK_SHIFT        31
8989 /* PLL_DDR_SS Bit Fields */
8990 #define CCM_ANALOG_PLL_DDR_SS_STEP_MASK          0x7FFFu
8991 #define CCM_ANALOG_PLL_DDR_SS_STEP_SHIFT         0
8992 #define CCM_ANALOG_PLL_DDR_SS_STEP(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SS_STEP_SHIFT))&CCM_ANALOG_PLL_DDR_SS_STEP_MASK)
8993 #define CCM_ANALOG_PLL_DDR_SS_ENABLE_MASK        0x8000u
8994 #define CCM_ANALOG_PLL_DDR_SS_ENABLE_SHIFT       15
8995 #define CCM_ANALOG_PLL_DDR_SS_STOP_MASK          0xFFFF0000u
8996 #define CCM_ANALOG_PLL_DDR_SS_STOP_SHIFT         16
8997 #define CCM_ANALOG_PLL_DDR_SS_STOP(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SS_STOP_SHIFT))&CCM_ANALOG_PLL_DDR_SS_STOP_MASK)
8998 /* PLL_DDR_NUM Bit Fields */
8999 #define CCM_ANALOG_PLL_DDR_NUM_A_MASK            0x3FFFFFFFu
9000 #define CCM_ANALOG_PLL_DDR_NUM_A_SHIFT           0
9001 #define CCM_ANALOG_PLL_DDR_NUM_A(x)              (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_NUM_A_SHIFT))&CCM_ANALOG_PLL_DDR_NUM_A_MASK)
9002 #define CCM_ANALOG_PLL_DDR_NUM_RSVD0_MASK        0xC0000000u
9003 #define CCM_ANALOG_PLL_DDR_NUM_RSVD0_SHIFT       30
9004 #define CCM_ANALOG_PLL_DDR_NUM_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_DDR_NUM_RSVD0_MASK)
9005 /* PLL_DDR_DENOM Bit Fields */
9006 #define CCM_ANALOG_PLL_DDR_DENOM_B_MASK          0x3FFFFFFFu
9007 #define CCM_ANALOG_PLL_DDR_DENOM_B_SHIFT         0
9008 #define CCM_ANALOG_PLL_DDR_DENOM_B(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_DENOM_B_SHIFT))&CCM_ANALOG_PLL_DDR_DENOM_B_MASK)
9009 #define CCM_ANALOG_PLL_DDR_DENOM_RSVD0_MASK      0xC0000000u
9010 #define CCM_ANALOG_PLL_DDR_DENOM_RSVD0_SHIFT     30
9011 #define CCM_ANALOG_PLL_DDR_DENOM_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_DDR_DENOM_RSVD0_MASK)
9012 /* PLL_480 Bit Fields */
9013 #define CCM_ANALOG_PLL_480_DIV_SELECT_MASK       0x1u
9014 #define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT      0
9015 #define CCM_ANALOG_PLL_480_RSVD0_MASK            0xEu
9016 #define CCM_ANALOG_PLL_480_RSVD0_SHIFT           1
9017 #define CCM_ANALOG_PLL_480_RSVD0(x)              (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_RSVD0_MASK)
9018 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10u
9019 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4
9020 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20u
9021 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5
9022 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40u
9023 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6
9024 #define CCM_ANALOG_PLL_480_HALF_LF_MASK          0x80u
9025 #define CCM_ANALOG_PLL_480_HALF_LF_SHIFT         7
9026 #define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK        0x100u
9027 #define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT       8
9028 #define CCM_ANALOG_PLL_480_HALF_CP_MASK          0x200u
9029 #define CCM_ANALOG_PLL_480_HALF_CP_SHIFT         9
9030 #define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK        0x400u
9031 #define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT       10
9032 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK    0x800u
9033 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT   11
9034 #define CCM_ANALOG_PLL_480_POWERDOWN_MASK        0x1000u
9035 #define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT       12
9036 #define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK       0x2000u
9037 #define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT      13
9038 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK   0xC000u
9039 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT  14
9040 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK)
9041 #define CCM_ANALOG_PLL_480_BYPASS_MASK           0x10000u
9042 #define CCM_ANALOG_PLL_480_BYPASS_SHIFT          16
9043 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000u
9044 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17
9045 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK    0x40000u
9046 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT   18
9047 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK    0x80000u
9048 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT   19
9049 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK    0x100000u
9050 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT   20
9051 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK    0x200000u
9052 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT   21
9053 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK    0x400000u
9054 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT   22
9055 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK    0x800000u
9056 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT   23
9057 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK    0x1000000u
9058 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT   24
9059 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK    0x2000000u
9060 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT   25
9061 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000u
9062 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26
9063 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000u
9064 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27
9065 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000u
9066 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28
9067 #define CCM_ANALOG_PLL_480_RSVD1_MASK            0x60000000u
9068 #define CCM_ANALOG_PLL_480_RSVD1_SHIFT           29
9069 #define CCM_ANALOG_PLL_480_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_RSVD1_MASK)
9070 #define CCM_ANALOG_PLL_480_LOCK_MASK             0x80000000u
9071 #define CCM_ANALOG_PLL_480_LOCK_SHIFT            31
9072 /* PLL_480_SET Bit Fields */
9073 #define CCM_ANALOG_PLL_480_SET_DIV_SELECT_MASK   0x1u
9074 #define CCM_ANALOG_PLL_480_SET_DIV_SELECT_SHIFT  0
9075 #define CCM_ANALOG_PLL_480_SET_RSVD0_MASK        0xEu
9076 #define CCM_ANALOG_PLL_480_SET_RSVD0_SHIFT       1
9077 #define CCM_ANALOG_PLL_480_SET_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_SET_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_SET_RSVD0_MASK)
9078 #define CCM_ANALOG_PLL_480_SET_MAIN_DIV1_CLKGATE_MASK 0x10u
9079 #define CCM_ANALOG_PLL_480_SET_MAIN_DIV1_CLKGATE_SHIFT 4
9080 #define CCM_ANALOG_PLL_480_SET_MAIN_DIV2_CLKGATE_MASK 0x20u
9081 #define CCM_ANALOG_PLL_480_SET_MAIN_DIV2_CLKGATE_SHIFT 5
9082 #define CCM_ANALOG_PLL_480_SET_MAIN_DIV4_CLKGATE_MASK 0x40u
9083 #define CCM_ANALOG_PLL_480_SET_MAIN_DIV4_CLKGATE_SHIFT 6
9084 #define CCM_ANALOG_PLL_480_SET_HALF_LF_MASK      0x80u
9085 #define CCM_ANALOG_PLL_480_SET_HALF_LF_SHIFT     7
9086 #define CCM_ANALOG_PLL_480_SET_DOUBLE_LF_MASK    0x100u
9087 #define CCM_ANALOG_PLL_480_SET_DOUBLE_LF_SHIFT   8
9088 #define CCM_ANALOG_PLL_480_SET_HALF_CP_MASK      0x200u
9089 #define CCM_ANALOG_PLL_480_SET_HALF_CP_SHIFT     9
9090 #define CCM_ANALOG_PLL_480_SET_DOUBLE_CP_MASK    0x400u
9091 #define CCM_ANALOG_PLL_480_SET_DOUBLE_CP_SHIFT   10
9092 #define CCM_ANALOG_PLL_480_SET_HOLD_RING_OFF_MASK 0x800u
9093 #define CCM_ANALOG_PLL_480_SET_HOLD_RING_OFF_SHIFT 11
9094 #define CCM_ANALOG_PLL_480_SET_POWERDOWN_MASK    0x1000u
9095 #define CCM_ANALOG_PLL_480_SET_POWERDOWN_SHIFT   12
9096 #define CCM_ANALOG_PLL_480_SET_ENABLE_CLK_MASK   0x2000u
9097 #define CCM_ANALOG_PLL_480_SET_ENABLE_CLK_SHIFT  13
9098 #define CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_MASK 0xC000u
9099 #define CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_SHIFT 14
9100 #define CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_MASK)
9101 #define CCM_ANALOG_PLL_480_SET_BYPASS_MASK       0x10000u
9102 #define CCM_ANALOG_PLL_480_SET_BYPASS_SHIFT      16
9103 #define CCM_ANALOG_PLL_480_SET_PLL_480_OVERRIDE_MASK 0x20000u
9104 #define CCM_ANALOG_PLL_480_SET_PLL_480_OVERRIDE_SHIFT 17
9105 #define CCM_ANALOG_PLL_480_SET_PFD0_OVERRIDE_MASK 0x40000u
9106 #define CCM_ANALOG_PLL_480_SET_PFD0_OVERRIDE_SHIFT 18
9107 #define CCM_ANALOG_PLL_480_SET_PFD1_OVERRIDE_MASK 0x80000u
9108 #define CCM_ANALOG_PLL_480_SET_PFD1_OVERRIDE_SHIFT 19
9109 #define CCM_ANALOG_PLL_480_SET_PFD2_OVERRIDE_MASK 0x100000u
9110 #define CCM_ANALOG_PLL_480_SET_PFD2_OVERRIDE_SHIFT 20
9111 #define CCM_ANALOG_PLL_480_SET_PFD3_OVERRIDE_MASK 0x200000u
9112 #define CCM_ANALOG_PLL_480_SET_PFD3_OVERRIDE_SHIFT 21
9113 #define CCM_ANALOG_PLL_480_SET_PFD4_OVERRIDE_MASK 0x400000u
9114 #define CCM_ANALOG_PLL_480_SET_PFD4_OVERRIDE_SHIFT 22
9115 #define CCM_ANALOG_PLL_480_SET_PFD5_OVERRIDE_MASK 0x800000u
9116 #define CCM_ANALOG_PLL_480_SET_PFD5_OVERRIDE_SHIFT 23
9117 #define CCM_ANALOG_PLL_480_SET_PFD6_OVERRIDE_MASK 0x1000000u
9118 #define CCM_ANALOG_PLL_480_SET_PFD6_OVERRIDE_SHIFT 24
9119 #define CCM_ANALOG_PLL_480_SET_PFD7_OVERRIDE_MASK 0x2000000u
9120 #define CCM_ANALOG_PLL_480_SET_PFD7_OVERRIDE_SHIFT 25
9121 #define CCM_ANALOG_PLL_480_SET_PFD0_DIV2_CLKGATE_MASK 0x4000000u
9122 #define CCM_ANALOG_PLL_480_SET_PFD0_DIV2_CLKGATE_SHIFT 26
9123 #define CCM_ANALOG_PLL_480_SET_PFD1_DIV2_CLKGATE_MASK 0x8000000u
9124 #define CCM_ANALOG_PLL_480_SET_PFD1_DIV2_CLKGATE_SHIFT 27
9125 #define CCM_ANALOG_PLL_480_SET_PFD2_DIV2_CLKGATE_MASK 0x10000000u
9126 #define CCM_ANALOG_PLL_480_SET_PFD2_DIV2_CLKGATE_SHIFT 28
9127 #define CCM_ANALOG_PLL_480_SET_RSVD1_MASK        0x60000000u
9128 #define CCM_ANALOG_PLL_480_SET_RSVD1_SHIFT       29
9129 #define CCM_ANALOG_PLL_480_SET_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_SET_RSVD1_MASK)
9130 #define CCM_ANALOG_PLL_480_SET_LOCK_MASK         0x80000000u
9131 #define CCM_ANALOG_PLL_480_SET_LOCK_SHIFT        31
9132 /* PLL_480_CLR Bit Fields */
9133 #define CCM_ANALOG_PLL_480_CLR_DIV_SELECT_MASK   0x1u
9134 #define CCM_ANALOG_PLL_480_CLR_DIV_SELECT_SHIFT  0
9135 #define CCM_ANALOG_PLL_480_CLR_RSVD0_MASK        0xEu
9136 #define CCM_ANALOG_PLL_480_CLR_RSVD0_SHIFT       1
9137 #define CCM_ANALOG_PLL_480_CLR_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_CLR_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_CLR_RSVD0_MASK)
9138 #define CCM_ANALOG_PLL_480_CLR_MAIN_DIV1_CLKGATE_MASK 0x10u
9139 #define CCM_ANALOG_PLL_480_CLR_MAIN_DIV1_CLKGATE_SHIFT 4
9140 #define CCM_ANALOG_PLL_480_CLR_MAIN_DIV2_CLKGATE_MASK 0x20u
9141 #define CCM_ANALOG_PLL_480_CLR_MAIN_DIV2_CLKGATE_SHIFT 5
9142 #define CCM_ANALOG_PLL_480_CLR_MAIN_DIV4_CLKGATE_MASK 0x40u
9143 #define CCM_ANALOG_PLL_480_CLR_MAIN_DIV4_CLKGATE_SHIFT 6
9144 #define CCM_ANALOG_PLL_480_CLR_HALF_LF_MASK      0x80u
9145 #define CCM_ANALOG_PLL_480_CLR_HALF_LF_SHIFT     7
9146 #define CCM_ANALOG_PLL_480_CLR_DOUBLE_LF_MASK    0x100u
9147 #define CCM_ANALOG_PLL_480_CLR_DOUBLE_LF_SHIFT   8
9148 #define CCM_ANALOG_PLL_480_CLR_HALF_CP_MASK      0x200u
9149 #define CCM_ANALOG_PLL_480_CLR_HALF_CP_SHIFT     9
9150 #define CCM_ANALOG_PLL_480_CLR_DOUBLE_CP_MASK    0x400u
9151 #define CCM_ANALOG_PLL_480_CLR_DOUBLE_CP_SHIFT   10
9152 #define CCM_ANALOG_PLL_480_CLR_HOLD_RING_OFF_MASK 0x800u
9153 #define CCM_ANALOG_PLL_480_CLR_HOLD_RING_OFF_SHIFT 11
9154 #define CCM_ANALOG_PLL_480_CLR_POWERDOWN_MASK    0x1000u
9155 #define CCM_ANALOG_PLL_480_CLR_POWERDOWN_SHIFT   12
9156 #define CCM_ANALOG_PLL_480_CLR_ENABLE_CLK_MASK   0x2000u
9157 #define CCM_ANALOG_PLL_480_CLR_ENABLE_CLK_SHIFT  13
9158 #define CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_MASK 0xC000u
9159 #define CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_SHIFT 14
9160 #define CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_MASK)
9161 #define CCM_ANALOG_PLL_480_CLR_BYPASS_MASK       0x10000u
9162 #define CCM_ANALOG_PLL_480_CLR_BYPASS_SHIFT      16
9163 #define CCM_ANALOG_PLL_480_CLR_PLL_480_OVERRIDE_MASK 0x20000u
9164 #define CCM_ANALOG_PLL_480_CLR_PLL_480_OVERRIDE_SHIFT 17
9165 #define CCM_ANALOG_PLL_480_CLR_PFD0_OVERRIDE_MASK 0x40000u
9166 #define CCM_ANALOG_PLL_480_CLR_PFD0_OVERRIDE_SHIFT 18
9167 #define CCM_ANALOG_PLL_480_CLR_PFD1_OVERRIDE_MASK 0x80000u
9168 #define CCM_ANALOG_PLL_480_CLR_PFD1_OVERRIDE_SHIFT 19
9169 #define CCM_ANALOG_PLL_480_CLR_PFD2_OVERRIDE_MASK 0x100000u
9170 #define CCM_ANALOG_PLL_480_CLR_PFD2_OVERRIDE_SHIFT 20
9171 #define CCM_ANALOG_PLL_480_CLR_PFD3_OVERRIDE_MASK 0x200000u
9172 #define CCM_ANALOG_PLL_480_CLR_PFD3_OVERRIDE_SHIFT 21
9173 #define CCM_ANALOG_PLL_480_CLR_PFD4_OVERRIDE_MASK 0x400000u
9174 #define CCM_ANALOG_PLL_480_CLR_PFD4_OVERRIDE_SHIFT 22
9175 #define CCM_ANALOG_PLL_480_CLR_PFD5_OVERRIDE_MASK 0x800000u
9176 #define CCM_ANALOG_PLL_480_CLR_PFD5_OVERRIDE_SHIFT 23
9177 #define CCM_ANALOG_PLL_480_CLR_PFD6_OVERRIDE_MASK 0x1000000u
9178 #define CCM_ANALOG_PLL_480_CLR_PFD6_OVERRIDE_SHIFT 24
9179 #define CCM_ANALOG_PLL_480_CLR_PFD7_OVERRIDE_MASK 0x2000000u
9180 #define CCM_ANALOG_PLL_480_CLR_PFD7_OVERRIDE_SHIFT 25
9181 #define CCM_ANALOG_PLL_480_CLR_PFD0_DIV2_CLKGATE_MASK 0x4000000u
9182 #define CCM_ANALOG_PLL_480_CLR_PFD0_DIV2_CLKGATE_SHIFT 26
9183 #define CCM_ANALOG_PLL_480_CLR_PFD1_DIV2_CLKGATE_MASK 0x8000000u
9184 #define CCM_ANALOG_PLL_480_CLR_PFD1_DIV2_CLKGATE_SHIFT 27
9185 #define CCM_ANALOG_PLL_480_CLR_PFD2_DIV2_CLKGATE_MASK 0x10000000u
9186 #define CCM_ANALOG_PLL_480_CLR_PFD2_DIV2_CLKGATE_SHIFT 28
9187 #define CCM_ANALOG_PLL_480_CLR_RSVD1_MASK        0x60000000u
9188 #define CCM_ANALOG_PLL_480_CLR_RSVD1_SHIFT       29
9189 #define CCM_ANALOG_PLL_480_CLR_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_CLR_RSVD1_MASK)
9190 #define CCM_ANALOG_PLL_480_CLR_LOCK_MASK         0x80000000u
9191 #define CCM_ANALOG_PLL_480_CLR_LOCK_SHIFT        31
9192 /* PLL_480_TOG Bit Fields */
9193 #define CCM_ANALOG_PLL_480_TOG_DIV_SELECT_MASK   0x1u
9194 #define CCM_ANALOG_PLL_480_TOG_DIV_SELECT_SHIFT  0
9195 #define CCM_ANALOG_PLL_480_TOG_RSVD0_MASK        0xEu
9196 #define CCM_ANALOG_PLL_480_TOG_RSVD0_SHIFT       1
9197 #define CCM_ANALOG_PLL_480_TOG_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_TOG_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_TOG_RSVD0_MASK)
9198 #define CCM_ANALOG_PLL_480_TOG_MAIN_DIV1_CLKGATE_MASK 0x10u
9199 #define CCM_ANALOG_PLL_480_TOG_MAIN_DIV1_CLKGATE_SHIFT 4
9200 #define CCM_ANALOG_PLL_480_TOG_MAIN_DIV2_CLKGATE_MASK 0x20u
9201 #define CCM_ANALOG_PLL_480_TOG_MAIN_DIV2_CLKGATE_SHIFT 5
9202 #define CCM_ANALOG_PLL_480_TOG_MAIN_DIV4_CLKGATE_MASK 0x40u
9203 #define CCM_ANALOG_PLL_480_TOG_MAIN_DIV4_CLKGATE_SHIFT 6
9204 #define CCM_ANALOG_PLL_480_TOG_HALF_LF_MASK      0x80u
9205 #define CCM_ANALOG_PLL_480_TOG_HALF_LF_SHIFT     7
9206 #define CCM_ANALOG_PLL_480_TOG_DOUBLE_LF_MASK    0x100u
9207 #define CCM_ANALOG_PLL_480_TOG_DOUBLE_LF_SHIFT   8
9208 #define CCM_ANALOG_PLL_480_TOG_HALF_CP_MASK      0x200u
9209 #define CCM_ANALOG_PLL_480_TOG_HALF_CP_SHIFT     9
9210 #define CCM_ANALOG_PLL_480_TOG_DOUBLE_CP_MASK    0x400u
9211 #define CCM_ANALOG_PLL_480_TOG_DOUBLE_CP_SHIFT   10
9212 #define CCM_ANALOG_PLL_480_TOG_HOLD_RING_OFF_MASK 0x800u
9213 #define CCM_ANALOG_PLL_480_TOG_HOLD_RING_OFF_SHIFT 11
9214 #define CCM_ANALOG_PLL_480_TOG_POWERDOWN_MASK    0x1000u
9215 #define CCM_ANALOG_PLL_480_TOG_POWERDOWN_SHIFT   12
9216 #define CCM_ANALOG_PLL_480_TOG_ENABLE_CLK_MASK   0x2000u
9217 #define CCM_ANALOG_PLL_480_TOG_ENABLE_CLK_SHIFT  13
9218 #define CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_MASK 0xC000u
9219 #define CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_SHIFT 14
9220 #define CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_MASK)
9221 #define CCM_ANALOG_PLL_480_TOG_BYPASS_MASK       0x10000u
9222 #define CCM_ANALOG_PLL_480_TOG_BYPASS_SHIFT      16
9223 #define CCM_ANALOG_PLL_480_TOG_PLL_480_OVERRIDE_MASK 0x20000u
9224 #define CCM_ANALOG_PLL_480_TOG_PLL_480_OVERRIDE_SHIFT 17
9225 #define CCM_ANALOG_PLL_480_TOG_PFD0_OVERRIDE_MASK 0x40000u
9226 #define CCM_ANALOG_PLL_480_TOG_PFD0_OVERRIDE_SHIFT 18
9227 #define CCM_ANALOG_PLL_480_TOG_PFD1_OVERRIDE_MASK 0x80000u
9228 #define CCM_ANALOG_PLL_480_TOG_PFD1_OVERRIDE_SHIFT 19
9229 #define CCM_ANALOG_PLL_480_TOG_PFD2_OVERRIDE_MASK 0x100000u
9230 #define CCM_ANALOG_PLL_480_TOG_PFD2_OVERRIDE_SHIFT 20
9231 #define CCM_ANALOG_PLL_480_TOG_PFD3_OVERRIDE_MASK 0x200000u
9232 #define CCM_ANALOG_PLL_480_TOG_PFD3_OVERRIDE_SHIFT 21
9233 #define CCM_ANALOG_PLL_480_TOG_PFD4_OVERRIDE_MASK 0x400000u
9234 #define CCM_ANALOG_PLL_480_TOG_PFD4_OVERRIDE_SHIFT 22
9235 #define CCM_ANALOG_PLL_480_TOG_PFD5_OVERRIDE_MASK 0x800000u
9236 #define CCM_ANALOG_PLL_480_TOG_PFD5_OVERRIDE_SHIFT 23
9237 #define CCM_ANALOG_PLL_480_TOG_PFD6_OVERRIDE_MASK 0x1000000u
9238 #define CCM_ANALOG_PLL_480_TOG_PFD6_OVERRIDE_SHIFT 24
9239 #define CCM_ANALOG_PLL_480_TOG_PFD7_OVERRIDE_MASK 0x2000000u
9240 #define CCM_ANALOG_PLL_480_TOG_PFD7_OVERRIDE_SHIFT 25
9241 #define CCM_ANALOG_PLL_480_TOG_PFD0_DIV2_CLKGATE_MASK 0x4000000u
9242 #define CCM_ANALOG_PLL_480_TOG_PFD0_DIV2_CLKGATE_SHIFT 26
9243 #define CCM_ANALOG_PLL_480_TOG_PFD1_DIV2_CLKGATE_MASK 0x8000000u
9244 #define CCM_ANALOG_PLL_480_TOG_PFD1_DIV2_CLKGATE_SHIFT 27
9245 #define CCM_ANALOG_PLL_480_TOG_PFD2_DIV2_CLKGATE_MASK 0x10000000u
9246 #define CCM_ANALOG_PLL_480_TOG_PFD2_DIV2_CLKGATE_SHIFT 28
9247 #define CCM_ANALOG_PLL_480_TOG_RSVD1_MASK        0x60000000u
9248 #define CCM_ANALOG_PLL_480_TOG_RSVD1_SHIFT       29
9249 #define CCM_ANALOG_PLL_480_TOG_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_TOG_RSVD1_MASK)
9250 #define CCM_ANALOG_PLL_480_TOG_LOCK_MASK         0x80000000u
9251 #define CCM_ANALOG_PLL_480_TOG_LOCK_SHIFT        31
9252 /* PFD_480A Bit Fields */
9253 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK       0x3Fu
9254 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT      0
9255 #define CCM_ANALOG_PFD_480A_PFD0_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK)
9256 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK     0x40u
9257 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT    6
9258 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80u
9259 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7
9260 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK       0x3F00u
9261 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT      8
9262 #define CCM_ANALOG_PFD_480A_PFD1_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK)
9263 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK     0x4000u
9264 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT    14
9265 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000u
9266 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15
9267 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK       0x3F0000u
9268 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT      16
9269 #define CCM_ANALOG_PFD_480A_PFD2_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK)
9270 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK     0x400000u
9271 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT    22
9272 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000u
9273 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23
9274 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK       0x3F000000u
9275 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT      24
9276 #define CCM_ANALOG_PFD_480A_PFD3_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK)
9277 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK     0x40000000u
9278 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT    30
9279 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000u
9280 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31
9281 /* PFD_480A_SET Bit Fields */
9282 #define CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_MASK   0x3Fu
9283 #define CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_SHIFT  0
9284 #define CCM_ANALOG_PFD_480A_SET_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_MASK)
9285 #define CCM_ANALOG_PFD_480A_SET_PFD0_STABLE_MASK 0x40u
9286 #define CCM_ANALOG_PFD_480A_SET_PFD0_STABLE_SHIFT 6
9287 #define CCM_ANALOG_PFD_480A_SET_PFD0_DIV1_CLKGATE_MASK 0x80u
9288 #define CCM_ANALOG_PFD_480A_SET_PFD0_DIV1_CLKGATE_SHIFT 7
9289 #define CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_MASK   0x3F00u
9290 #define CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_SHIFT  8
9291 #define CCM_ANALOG_PFD_480A_SET_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_MASK)
9292 #define CCM_ANALOG_PFD_480A_SET_PFD1_STABLE_MASK 0x4000u
9293 #define CCM_ANALOG_PFD_480A_SET_PFD1_STABLE_SHIFT 14
9294 #define CCM_ANALOG_PFD_480A_SET_PFD1_DIV1_CLKGATE_MASK 0x8000u
9295 #define CCM_ANALOG_PFD_480A_SET_PFD1_DIV1_CLKGATE_SHIFT 15
9296 #define CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_MASK   0x3F0000u
9297 #define CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_SHIFT  16
9298 #define CCM_ANALOG_PFD_480A_SET_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_MASK)
9299 #define CCM_ANALOG_PFD_480A_SET_PFD2_STABLE_MASK 0x400000u
9300 #define CCM_ANALOG_PFD_480A_SET_PFD2_STABLE_SHIFT 22
9301 #define CCM_ANALOG_PFD_480A_SET_PFD2_DIV1_CLKGATE_MASK 0x800000u
9302 #define CCM_ANALOG_PFD_480A_SET_PFD2_DIV1_CLKGATE_SHIFT 23
9303 #define CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_MASK   0x3F000000u
9304 #define CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_SHIFT  24
9305 #define CCM_ANALOG_PFD_480A_SET_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_MASK)
9306 #define CCM_ANALOG_PFD_480A_SET_PFD3_STABLE_MASK 0x40000000u
9307 #define CCM_ANALOG_PFD_480A_SET_PFD3_STABLE_SHIFT 30
9308 #define CCM_ANALOG_PFD_480A_SET_PFD3_DIV1_CLKGATE_MASK 0x80000000u
9309 #define CCM_ANALOG_PFD_480A_SET_PFD3_DIV1_CLKGATE_SHIFT 31
9310 /* PFD_480A_CLR Bit Fields */
9311 #define CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_MASK   0x3Fu
9312 #define CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_SHIFT  0
9313 #define CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_MASK)
9314 #define CCM_ANALOG_PFD_480A_CLR_PFD0_STABLE_MASK 0x40u
9315 #define CCM_ANALOG_PFD_480A_CLR_PFD0_STABLE_SHIFT 6
9316 #define CCM_ANALOG_PFD_480A_CLR_PFD0_DIV1_CLKGATE_MASK 0x80u
9317 #define CCM_ANALOG_PFD_480A_CLR_PFD0_DIV1_CLKGATE_SHIFT 7
9318 #define CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_MASK   0x3F00u
9319 #define CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_SHIFT  8
9320 #define CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_MASK)
9321 #define CCM_ANALOG_PFD_480A_CLR_PFD1_STABLE_MASK 0x4000u
9322 #define CCM_ANALOG_PFD_480A_CLR_PFD1_STABLE_SHIFT 14
9323 #define CCM_ANALOG_PFD_480A_CLR_PFD1_DIV1_CLKGATE_MASK 0x8000u
9324 #define CCM_ANALOG_PFD_480A_CLR_PFD1_DIV1_CLKGATE_SHIFT 15
9325 #define CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_MASK   0x3F0000u
9326 #define CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_SHIFT  16
9327 #define CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_MASK)
9328 #define CCM_ANALOG_PFD_480A_CLR_PFD2_STABLE_MASK 0x400000u
9329 #define CCM_ANALOG_PFD_480A_CLR_PFD2_STABLE_SHIFT 22
9330 #define CCM_ANALOG_PFD_480A_CLR_PFD2_DIV1_CLKGATE_MASK 0x800000u
9331 #define CCM_ANALOG_PFD_480A_CLR_PFD2_DIV1_CLKGATE_SHIFT 23
9332 #define CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_MASK   0x3F000000u
9333 #define CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_SHIFT  24
9334 #define CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_MASK)
9335 #define CCM_ANALOG_PFD_480A_CLR_PFD3_STABLE_MASK 0x40000000u
9336 #define CCM_ANALOG_PFD_480A_CLR_PFD3_STABLE_SHIFT 30
9337 #define CCM_ANALOG_PFD_480A_CLR_PFD3_DIV1_CLKGATE_MASK 0x80000000u
9338 #define CCM_ANALOG_PFD_480A_CLR_PFD3_DIV1_CLKGATE_SHIFT 31
9339 /* PFD_480A_TOG Bit Fields */
9340 #define CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_MASK   0x3Fu
9341 #define CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_SHIFT  0
9342 #define CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_MASK)
9343 #define CCM_ANALOG_PFD_480A_TOG_PFD0_STABLE_MASK 0x40u
9344 #define CCM_ANALOG_PFD_480A_TOG_PFD0_STABLE_SHIFT 6
9345 #define CCM_ANALOG_PFD_480A_TOG_PFD0_DIV1_CLKGATE_MASK 0x80u
9346 #define CCM_ANALOG_PFD_480A_TOG_PFD0_DIV1_CLKGATE_SHIFT 7
9347 #define CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_MASK   0x3F00u
9348 #define CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_SHIFT  8
9349 #define CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_MASK)
9350 #define CCM_ANALOG_PFD_480A_TOG_PFD1_STABLE_MASK 0x4000u
9351 #define CCM_ANALOG_PFD_480A_TOG_PFD1_STABLE_SHIFT 14
9352 #define CCM_ANALOG_PFD_480A_TOG_PFD1_DIV1_CLKGATE_MASK 0x8000u
9353 #define CCM_ANALOG_PFD_480A_TOG_PFD1_DIV1_CLKGATE_SHIFT 15
9354 #define CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_MASK   0x3F0000u
9355 #define CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_SHIFT  16
9356 #define CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_MASK)
9357 #define CCM_ANALOG_PFD_480A_TOG_PFD2_STABLE_MASK 0x400000u
9358 #define CCM_ANALOG_PFD_480A_TOG_PFD2_STABLE_SHIFT 22
9359 #define CCM_ANALOG_PFD_480A_TOG_PFD2_DIV1_CLKGATE_MASK 0x800000u
9360 #define CCM_ANALOG_PFD_480A_TOG_PFD2_DIV1_CLKGATE_SHIFT 23
9361 #define CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_MASK   0x3F000000u
9362 #define CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_SHIFT  24
9363 #define CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_MASK)
9364 #define CCM_ANALOG_PFD_480A_TOG_PFD3_STABLE_MASK 0x40000000u
9365 #define CCM_ANALOG_PFD_480A_TOG_PFD3_STABLE_SHIFT 30
9366 #define CCM_ANALOG_PFD_480A_TOG_PFD3_DIV1_CLKGATE_MASK 0x80000000u
9367 #define CCM_ANALOG_PFD_480A_TOG_PFD3_DIV1_CLKGATE_SHIFT 31
9368 /* PFD_480B Bit Fields */
9369 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK       0x3Fu
9370 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT      0
9371 #define CCM_ANALOG_PFD_480B_PFD4_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK)
9372 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK     0x40u
9373 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT    6
9374 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80u
9375 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7
9376 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK       0x3F00u
9377 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT      8
9378 #define CCM_ANALOG_PFD_480B_PFD5_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK)
9379 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK     0x4000u
9380 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT    14
9381 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000u
9382 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15
9383 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK       0x3F0000u
9384 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT      16
9385 #define CCM_ANALOG_PFD_480B_PFD6_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK)
9386 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK     0x400000u
9387 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT    22
9388 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000u
9389 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23
9390 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK       0x3F000000u
9391 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT      24
9392 #define CCM_ANALOG_PFD_480B_PFD7_FRAC(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK)
9393 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK     0x40000000u
9394 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT    30
9395 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000u
9396 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31
9397 /* PFD_480B_SET Bit Fields */
9398 #define CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_MASK   0x3Fu
9399 #define CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_SHIFT  0
9400 #define CCM_ANALOG_PFD_480B_SET_PFD4_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_MASK)
9401 #define CCM_ANALOG_PFD_480B_SET_PFD4_STABLE_MASK 0x40u
9402 #define CCM_ANALOG_PFD_480B_SET_PFD4_STABLE_SHIFT 6
9403 #define CCM_ANALOG_PFD_480B_SET_PFD4_DIV1_CLKGATE_MASK 0x80u
9404 #define CCM_ANALOG_PFD_480B_SET_PFD4_DIV1_CLKGATE_SHIFT 7
9405 #define CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_MASK   0x3F00u
9406 #define CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_SHIFT  8
9407 #define CCM_ANALOG_PFD_480B_SET_PFD5_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_MASK)
9408 #define CCM_ANALOG_PFD_480B_SET_PFD5_STABLE_MASK 0x4000u
9409 #define CCM_ANALOG_PFD_480B_SET_PFD5_STABLE_SHIFT 14
9410 #define CCM_ANALOG_PFD_480B_SET_PFD5_DIV1_CLKGATE_MASK 0x8000u
9411 #define CCM_ANALOG_PFD_480B_SET_PFD5_DIV1_CLKGATE_SHIFT 15
9412 #define CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_MASK   0x3F0000u
9413 #define CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_SHIFT  16
9414 #define CCM_ANALOG_PFD_480B_SET_PFD6_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_MASK)
9415 #define CCM_ANALOG_PFD_480B_SET_PFD6_STABLE_MASK 0x400000u
9416 #define CCM_ANALOG_PFD_480B_SET_PFD6_STABLE_SHIFT 22
9417 #define CCM_ANALOG_PFD_480B_SET_PFD6_DIV1_CLKGATE_MASK 0x800000u
9418 #define CCM_ANALOG_PFD_480B_SET_PFD6_DIV1_CLKGATE_SHIFT 23
9419 #define CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_MASK   0x3F000000u
9420 #define CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_SHIFT  24
9421 #define CCM_ANALOG_PFD_480B_SET_PFD7_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_MASK)
9422 #define CCM_ANALOG_PFD_480B_SET_PFD7_STABLE_MASK 0x40000000u
9423 #define CCM_ANALOG_PFD_480B_SET_PFD7_STABLE_SHIFT 30
9424 #define CCM_ANALOG_PFD_480B_SET_PFD7_DIV1_CLKGATE_MASK 0x80000000u
9425 #define CCM_ANALOG_PFD_480B_SET_PFD7_DIV1_CLKGATE_SHIFT 31
9426 /* PFD_480B_CLR Bit Fields */
9427 #define CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_MASK   0x3Fu
9428 #define CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_SHIFT  0
9429 #define CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_MASK)
9430 #define CCM_ANALOG_PFD_480B_CLR_PFD4_STABLE_MASK 0x40u
9431 #define CCM_ANALOG_PFD_480B_CLR_PFD4_STABLE_SHIFT 6
9432 #define CCM_ANALOG_PFD_480B_CLR_PFD4_DIV1_CLKGATE_MASK 0x80u
9433 #define CCM_ANALOG_PFD_480B_CLR_PFD4_DIV1_CLKGATE_SHIFT 7
9434 #define CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_MASK   0x3F00u
9435 #define CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_SHIFT  8
9436 #define CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_MASK)
9437 #define CCM_ANALOG_PFD_480B_CLR_PFD5_STABLE_MASK 0x4000u
9438 #define CCM_ANALOG_PFD_480B_CLR_PFD5_STABLE_SHIFT 14
9439 #define CCM_ANALOG_PFD_480B_CLR_PFD5_DIV1_CLKGATE_MASK 0x8000u
9440 #define CCM_ANALOG_PFD_480B_CLR_PFD5_DIV1_CLKGATE_SHIFT 15
9441 #define CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_MASK   0x3F0000u
9442 #define CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_SHIFT  16
9443 #define CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_MASK)
9444 #define CCM_ANALOG_PFD_480B_CLR_PFD6_STABLE_MASK 0x400000u
9445 #define CCM_ANALOG_PFD_480B_CLR_PFD6_STABLE_SHIFT 22
9446 #define CCM_ANALOG_PFD_480B_CLR_PFD6_DIV1_CLKGATE_MASK 0x800000u
9447 #define CCM_ANALOG_PFD_480B_CLR_PFD6_DIV1_CLKGATE_SHIFT 23
9448 #define CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_MASK   0x3F000000u
9449 #define CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_SHIFT  24
9450 #define CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_MASK)
9451 #define CCM_ANALOG_PFD_480B_CLR_PFD7_STABLE_MASK 0x40000000u
9452 #define CCM_ANALOG_PFD_480B_CLR_PFD7_STABLE_SHIFT 30
9453 #define CCM_ANALOG_PFD_480B_CLR_PFD7_DIV1_CLKGATE_MASK 0x80000000u
9454 #define CCM_ANALOG_PFD_480B_CLR_PFD7_DIV1_CLKGATE_SHIFT 31
9455 /* PFD_480B_TOG Bit Fields */
9456 #define CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_MASK   0x3Fu
9457 #define CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_SHIFT  0
9458 #define CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_MASK)
9459 #define CCM_ANALOG_PFD_480B_TOG_PFD4_STABLE_MASK 0x40u
9460 #define CCM_ANALOG_PFD_480B_TOG_PFD4_STABLE_SHIFT 6
9461 #define CCM_ANALOG_PFD_480B_TOG_PFD4_DIV1_CLKGATE_MASK 0x80u
9462 #define CCM_ANALOG_PFD_480B_TOG_PFD4_DIV1_CLKGATE_SHIFT 7
9463 #define CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_MASK   0x3F00u
9464 #define CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_SHIFT  8
9465 #define CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_MASK)
9466 #define CCM_ANALOG_PFD_480B_TOG_PFD5_STABLE_MASK 0x4000u
9467 #define CCM_ANALOG_PFD_480B_TOG_PFD5_STABLE_SHIFT 14
9468 #define CCM_ANALOG_PFD_480B_TOG_PFD5_DIV1_CLKGATE_MASK 0x8000u
9469 #define CCM_ANALOG_PFD_480B_TOG_PFD5_DIV1_CLKGATE_SHIFT 15
9470 #define CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_MASK   0x3F0000u
9471 #define CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_SHIFT  16
9472 #define CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_MASK)
9473 #define CCM_ANALOG_PFD_480B_TOG_PFD6_STABLE_MASK 0x400000u
9474 #define CCM_ANALOG_PFD_480B_TOG_PFD6_STABLE_SHIFT 22
9475 #define CCM_ANALOG_PFD_480B_TOG_PFD6_DIV1_CLKGATE_MASK 0x800000u
9476 #define CCM_ANALOG_PFD_480B_TOG_PFD6_DIV1_CLKGATE_SHIFT 23
9477 #define CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_MASK   0x3F000000u
9478 #define CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_SHIFT  24
9479 #define CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_MASK)
9480 #define CCM_ANALOG_PFD_480B_TOG_PFD7_STABLE_MASK 0x40000000u
9481 #define CCM_ANALOG_PFD_480B_TOG_PFD7_STABLE_SHIFT 30
9482 #define CCM_ANALOG_PFD_480B_TOG_PFD7_DIV1_CLKGATE_MASK 0x80000000u
9483 #define CCM_ANALOG_PFD_480B_TOG_PFD7_DIV1_CLKGATE_SHIFT 31
9484 /* PLL_ENET Bit Fields */
9485 #define CCM_ANALOG_PLL_ENET_HALF_LF_MASK         0x1u
9486 #define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT        0
9487 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK       0x2u
9488 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT      1
9489 #define CCM_ANALOG_PLL_ENET_HALF_CP_MASK         0x4u
9490 #define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT        2
9491 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK       0x8u
9492 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT      3
9493 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK   0x10u
9494 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT  4
9495 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK       0x20u
9496 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT      5
9497 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40u
9498 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6
9499 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80u
9500 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7
9501 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100u
9502 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8
9503 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200u
9504 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9
9505 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400u
9506 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10
9507 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800u
9508 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11
9509 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000u
9510 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12
9511 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000u
9512 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13
9513 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK  0xC000u
9514 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14
9515 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
9516 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK          0x10000u
9517 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT         16
9518 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK   0x20000u
9519 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT  17
9520 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK   0x40000u
9521 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT  18
9522 #define CCM_ANALOG_PLL_ENET_RSVD1_MASK           0x7FF80000u
9523 #define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT          19
9524 #define CCM_ANALOG_PLL_ENET_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_RSVD1_MASK)
9525 #define CCM_ANALOG_PLL_ENET_LOCK_MASK            0x80000000u
9526 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT           31
9527 /* PLL_ENET_SET Bit Fields */
9528 #define CCM_ANALOG_PLL_ENET_SET_HALF_LF_MASK     0x1u
9529 #define CCM_ANALOG_PLL_ENET_SET_HALF_LF_SHIFT    0
9530 #define CCM_ANALOG_PLL_ENET_SET_DOUBLE_LF_MASK   0x2u
9531 #define CCM_ANALOG_PLL_ENET_SET_DOUBLE_LF_SHIFT  1
9532 #define CCM_ANALOG_PLL_ENET_SET_HALF_CP_MASK     0x4u
9533 #define CCM_ANALOG_PLL_ENET_SET_HALF_CP_SHIFT    2
9534 #define CCM_ANALOG_PLL_ENET_SET_DOUBLE_CP_MASK   0x8u
9535 #define CCM_ANALOG_PLL_ENET_SET_DOUBLE_CP_SHIFT  3
9536 #define CCM_ANALOG_PLL_ENET_SET_HOLD_RING_OFF_MASK 0x10u
9537 #define CCM_ANALOG_PLL_ENET_SET_HOLD_RING_OFF_SHIFT 4
9538 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK   0x20u
9539 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT  5
9540 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_25MHZ_MASK 0x40u
9541 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_25MHZ_SHIFT 6
9542 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_40MHZ_MASK 0x80u
9543 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_40MHZ_SHIFT 7
9544 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_50MHZ_MASK 0x100u
9545 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_50MHZ_SHIFT 8
9546 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_100MHZ_MASK 0x200u
9547 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_100MHZ_SHIFT 9
9548 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_125MHZ_MASK 0x400u
9549 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_125MHZ_SHIFT 10
9550 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_250MHZ_MASK 0x800u
9551 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_250MHZ_SHIFT 11
9552 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_500MHZ_MASK 0x1000u
9553 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_500MHZ_SHIFT 12
9554 #define CCM_ANALOG_PLL_ENET_SET_PLL_ENET_OVERRIDE_MASK 0x2000u
9555 #define CCM_ANALOG_PLL_ENET_SET_PLL_ENET_OVERRIDE_SHIFT 13
9556 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK 0xC000u
9557 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT 14
9558 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
9559 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK      0x10000u
9560 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT     16
9561 #define CCM_ANALOG_PLL_ENET_SET_DITHER_ENABLE_MASK 0x20000u
9562 #define CCM_ANALOG_PLL_ENET_SET_DITHER_ENABLE_SHIFT 17
9563 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK 0x40000u
9564 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT 18
9565 #define CCM_ANALOG_PLL_ENET_SET_RSVD1_MASK       0x7FF80000u
9566 #define CCM_ANALOG_PLL_ENET_SET_RSVD1_SHIFT      19
9567 #define CCM_ANALOG_PLL_ENET_SET_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_SET_RSVD1_MASK)
9568 #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK        0x80000000u
9569 #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT       31
9570 /* PLL_ENET_CLR Bit Fields */
9571 #define CCM_ANALOG_PLL_ENET_CLR_HALF_LF_MASK     0x1u
9572 #define CCM_ANALOG_PLL_ENET_CLR_HALF_LF_SHIFT    0
9573 #define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_LF_MASK   0x2u
9574 #define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_LF_SHIFT  1
9575 #define CCM_ANALOG_PLL_ENET_CLR_HALF_CP_MASK     0x4u
9576 #define CCM_ANALOG_PLL_ENET_CLR_HALF_CP_SHIFT    2
9577 #define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_CP_MASK   0x8u
9578 #define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_CP_SHIFT  3
9579 #define CCM_ANALOG_PLL_ENET_CLR_HOLD_RING_OFF_MASK 0x10u
9580 #define CCM_ANALOG_PLL_ENET_CLR_HOLD_RING_OFF_SHIFT 4
9581 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK   0x20u
9582 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT  5
9583 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_25MHZ_MASK 0x40u
9584 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_25MHZ_SHIFT 6
9585 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_40MHZ_MASK 0x80u
9586 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_40MHZ_SHIFT 7
9587 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_50MHZ_MASK 0x100u
9588 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_50MHZ_SHIFT 8
9589 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_100MHZ_MASK 0x200u
9590 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_100MHZ_SHIFT 9
9591 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_125MHZ_MASK 0x400u
9592 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_125MHZ_SHIFT 10
9593 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_250MHZ_MASK 0x800u
9594 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_250MHZ_SHIFT 11
9595 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_500MHZ_MASK 0x1000u
9596 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_500MHZ_SHIFT 12
9597 #define CCM_ANALOG_PLL_ENET_CLR_PLL_ENET_OVERRIDE_MASK 0x2000u
9598 #define CCM_ANALOG_PLL_ENET_CLR_PLL_ENET_OVERRIDE_SHIFT 13
9599 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK 0xC000u
9600 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT 14
9601 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
9602 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK      0x10000u
9603 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT     16
9604 #define CCM_ANALOG_PLL_ENET_CLR_DITHER_ENABLE_MASK 0x20000u
9605 #define CCM_ANALOG_PLL_ENET_CLR_DITHER_ENABLE_SHIFT 17
9606 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK 0x40000u
9607 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT 18
9608 #define CCM_ANALOG_PLL_ENET_CLR_RSVD1_MASK       0x7FF80000u
9609 #define CCM_ANALOG_PLL_ENET_CLR_RSVD1_SHIFT      19
9610 #define CCM_ANALOG_PLL_ENET_CLR_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_RSVD1_MASK)
9611 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK        0x80000000u
9612 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT       31
9613 /* PLL_ENET_TOG Bit Fields */
9614 #define CCM_ANALOG_PLL_ENET_TOG_HALF_LF_MASK     0x1u
9615 #define CCM_ANALOG_PLL_ENET_TOG_HALF_LF_SHIFT    0
9616 #define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_LF_MASK   0x2u
9617 #define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_LF_SHIFT  1
9618 #define CCM_ANALOG_PLL_ENET_TOG_HALF_CP_MASK     0x4u
9619 #define CCM_ANALOG_PLL_ENET_TOG_HALF_CP_SHIFT    2
9620 #define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_CP_MASK   0x8u
9621 #define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_CP_SHIFT  3
9622 #define CCM_ANALOG_PLL_ENET_TOG_HOLD_RING_OFF_MASK 0x10u
9623 #define CCM_ANALOG_PLL_ENET_TOG_HOLD_RING_OFF_SHIFT 4
9624 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK   0x20u
9625 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT  5
9626 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_25MHZ_MASK 0x40u
9627 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_25MHZ_SHIFT 6
9628 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_40MHZ_MASK 0x80u
9629 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_40MHZ_SHIFT 7
9630 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_50MHZ_MASK 0x100u
9631 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_50MHZ_SHIFT 8
9632 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_100MHZ_MASK 0x200u
9633 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_100MHZ_SHIFT 9
9634 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_125MHZ_MASK 0x400u
9635 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_125MHZ_SHIFT 10
9636 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_250MHZ_MASK 0x800u
9637 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_250MHZ_SHIFT 11
9638 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_500MHZ_MASK 0x1000u
9639 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_500MHZ_SHIFT 12
9640 #define CCM_ANALOG_PLL_ENET_TOG_PLL_ENET_OVERRIDE_MASK 0x2000u
9641 #define CCM_ANALOG_PLL_ENET_TOG_PLL_ENET_OVERRIDE_SHIFT 13
9642 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK 0xC000u
9643 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT 14
9644 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
9645 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK      0x10000u
9646 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT     16
9647 #define CCM_ANALOG_PLL_ENET_TOG_DITHER_ENABLE_MASK 0x20000u
9648 #define CCM_ANALOG_PLL_ENET_TOG_DITHER_ENABLE_SHIFT 17
9649 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK 0x40000u
9650 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT 18
9651 #define CCM_ANALOG_PLL_ENET_TOG_RSVD1_MASK       0x7FF80000u
9652 #define CCM_ANALOG_PLL_ENET_TOG_RSVD1_SHIFT      19
9653 #define CCM_ANALOG_PLL_ENET_TOG_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_RSVD1_MASK)
9654 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK        0x80000000u
9655 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT       31
9656 /* PLL_AUDIO Bit Fields */
9657 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK     0x7Fu
9658 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT    0
9659 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
9660 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK        0x80u
9661 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT       7
9662 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK      0x100u
9663 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT     8
9664 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK        0x200u
9665 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT       9
9666 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK      0x400u
9667 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT     10
9668 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK  0x800u
9669 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11
9670 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK      0x1000u
9671 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT     12
9672 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK     0x2000u
9673 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT    13
9674 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
9675 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14
9676 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
9677 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK         0x10000u
9678 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT        16
9679 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK  0x20000u
9680 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17
9681 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK  0x40000u
9682 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18
9683 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u
9684 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19
9685 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK)
9686 #define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK          0x200000u
9687 #define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT         21
9688 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK   0xC00000u
9689 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT  22
9690 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK)
9691 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
9692 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24
9693 #define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK          0x7E000000u
9694 #define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT         25
9695 #define CCM_ANALOG_PLL_AUDIO_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK)
9696 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK           0x80000000u
9697 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT          31
9698 /* PLL_AUDIO_SET Bit Fields */
9699 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
9700 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
9701 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
9702 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK    0x80u
9703 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT   7
9704 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK  0x100u
9705 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8
9706 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK    0x200u
9707 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT   9
9708 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK  0x400u
9709 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10
9710 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u
9711 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11
9712 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK  0x1000u
9713 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12
9714 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u
9715 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13
9716 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
9717 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14
9718 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
9719 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK     0x10000u
9720 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT    16
9721 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u
9722 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17
9723 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
9724 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18
9725 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u
9726 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19
9727 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK)
9728 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK      0x200000u
9729 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT     21
9730 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u
9731 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22
9732 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK)
9733 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
9734 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24
9735 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK      0x7E000000u
9736 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT     25
9737 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK)
9738 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK       0x80000000u
9739 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT      31
9740 /* PLL_AUDIO_CLR Bit Fields */
9741 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
9742 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
9743 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
9744 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK    0x80u
9745 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT   7
9746 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK  0x100u
9747 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8
9748 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK    0x200u
9749 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT   9
9750 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK  0x400u
9751 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10
9752 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u
9753 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11
9754 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK  0x1000u
9755 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12
9756 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u
9757 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13
9758 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
9759 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14
9760 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
9761 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK     0x10000u
9762 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT    16
9763 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u
9764 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17
9765 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
9766 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18
9767 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u
9768 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19
9769 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK)
9770 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK      0x200000u
9771 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT     21
9772 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u
9773 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22
9774 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK)
9775 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
9776 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24
9777 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK      0x7E000000u
9778 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT     25
9779 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK)
9780 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK       0x80000000u
9781 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT      31
9782 /* PLL_AUDIO_TOG Bit Fields */
9783 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
9784 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
9785 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
9786 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK    0x80u
9787 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT   7
9788 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK  0x100u
9789 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8
9790 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK    0x200u
9791 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT   9
9792 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK  0x400u
9793 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10
9794 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u
9795 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11
9796 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK  0x1000u
9797 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12
9798 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u
9799 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13
9800 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
9801 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14
9802 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
9803 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK     0x10000u
9804 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT    16
9805 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u
9806 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17
9807 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
9808 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18
9809 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u
9810 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19
9811 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK)
9812 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK      0x200000u
9813 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT     21
9814 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u
9815 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22
9816 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK)
9817 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
9818 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24
9819 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK      0x7E000000u
9820 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT     25
9821 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK)
9822 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK       0x80000000u
9823 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT      31
9824 /* PLL_AUDIO_SS Bit Fields */
9825 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK        0x7FFFu
9826 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT       0
9827 #define CCM_ANALOG_PLL_AUDIO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)
9828 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK      0x8000u
9829 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT     15
9830 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK        0xFFFF0000u
9831 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT       16
9832 #define CCM_ANALOG_PLL_AUDIO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK)
9833 /* PLL_AUDIO_NUM Bit Fields */
9834 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK          0x3FFFFFFFu
9835 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT         0
9836 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
9837 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK      0xC0000000u
9838 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT     30
9839 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK)
9840 /* PLL_AUDIO_DENOM Bit Fields */
9841 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK        0x3FFFFFFFu
9842 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT       0
9843 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
9844 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK    0xC0000000u
9845 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT   30
9846 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK)
9847 /* PLL_VIDEO Bit Fields */
9848 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK     0x7Fu
9849 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT    0
9850 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
9851 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK        0x80u
9852 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT       7
9853 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK      0x100u
9854 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT     8
9855 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK        0x200u
9856 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT       9
9857 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK      0x400u
9858 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT     10
9859 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK  0x800u
9860 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11
9861 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK      0x1000u
9862 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT     12
9863 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK     0x2000u
9864 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT    13
9865 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
9866 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14
9867 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
9868 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK         0x10000u
9869 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT        16
9870 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK  0x20000u
9871 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17
9872 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK  0x40000u
9873 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18
9874 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u
9875 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19
9876 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK)
9877 #define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK          0x200000u
9878 #define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT         21
9879 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK   0xC00000u
9880 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT  22
9881 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK)
9882 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
9883 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24
9884 #define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK          0x7E000000u
9885 #define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT         25
9886 #define CCM_ANALOG_PLL_VIDEO_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK)
9887 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK           0x80000000u
9888 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT          31
9889 /* PLL_VIDEO_SET Bit Fields */
9890 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
9891 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
9892 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
9893 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK    0x80u
9894 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT   7
9895 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK  0x100u
9896 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8
9897 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK    0x200u
9898 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT   9
9899 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK  0x400u
9900 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10
9901 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u
9902 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11
9903 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK  0x1000u
9904 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12
9905 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u
9906 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13
9907 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
9908 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14
9909 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
9910 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK     0x10000u
9911 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT    16
9912 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u
9913 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17
9914 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
9915 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18
9916 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u
9917 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19
9918 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK)
9919 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK      0x200000u
9920 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT     21
9921 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u
9922 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22
9923 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK)
9924 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
9925 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24
9926 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK      0x7E000000u
9927 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT     25
9928 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK)
9929 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK       0x80000000u
9930 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT      31
9931 /* PLL_VIDEO_CLR Bit Fields */
9932 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
9933 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
9934 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
9935 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK    0x80u
9936 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT   7
9937 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK  0x100u
9938 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8
9939 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK    0x200u
9940 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT   9
9941 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK  0x400u
9942 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10
9943 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u
9944 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11
9945 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK  0x1000u
9946 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12
9947 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u
9948 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13
9949 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
9950 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14
9951 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
9952 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK     0x10000u
9953 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT    16
9954 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u
9955 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17
9956 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
9957 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18
9958 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u
9959 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19
9960 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK)
9961 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK      0x200000u
9962 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT     21
9963 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u
9964 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22
9965 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK)
9966 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
9967 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24
9968 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK      0x7E000000u
9969 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT     25
9970 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK)
9971 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK       0x80000000u
9972 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT      31
9973 /* PLL_VIDEO_TOG Bit Fields */
9974 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
9975 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
9976 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
9977 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK    0x80u
9978 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT   7
9979 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK  0x100u
9980 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8
9981 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK    0x200u
9982 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT   9
9983 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK  0x400u
9984 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10
9985 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u
9986 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11
9987 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK  0x1000u
9988 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12
9989 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u
9990 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13
9991 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
9992 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14
9993 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
9994 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK     0x10000u
9995 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT    16
9996 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u
9997 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17
9998 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
9999 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18
10000 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u
10001 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19
10002 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK)
10003 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK      0x200000u
10004 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT     21
10005 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u
10006 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22
10007 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK)
10008 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
10009 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24
10010 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK      0x7E000000u
10011 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT     25
10012 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK)
10013 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK       0x80000000u
10014 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT      31
10015 /* PLL_VIDEO_SS Bit Fields */
10016 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK        0x7FFFu
10017 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT       0
10018 #define CCM_ANALOG_PLL_VIDEO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)
10019 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK      0x8000u
10020 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT     15
10021 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK        0xFFFF0000u
10022 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT       16
10023 #define CCM_ANALOG_PLL_VIDEO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK)
10024 /* PLL_VIDEO_NUM Bit Fields */
10025 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK          0x3FFFFFFFu
10026 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT         0
10027 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
10028 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK      0xC0000000u
10029 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT     30
10030 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK)
10031 /* PLL_VIDEO_DENOM Bit Fields */
10032 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK        0x3FFFFFFFu
10033 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT       0
10034 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
10035 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK    0xC0000000u
10036 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT   30
10037 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK)
10038 /* CLK_MISC0 Bit Fields */
10039 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK  0x1Fu
10040 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0
10041 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK)
10042 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK  0x20u
10043 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5
10044 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK  0x40u
10045 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6
10046 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK   0x80u
10047 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT  7
10048 #define CCM_ANALOG_CLK_MISC0_RSVD0_MASK          0xFFFFFF00u
10049 #define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT         8
10050 #define CCM_ANALOG_CLK_MISC0_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK)
10051 /* CLK_MISC0_SET Bit Fields */
10052 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu
10053 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0
10054 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK)
10055 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u
10056 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5
10057 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u
10058 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6
10059 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u
10060 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7
10061 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK      0xFFFFFF00u
10062 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT     8
10063 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK)
10064 /* CLK_MISC0_CLR Bit Fields */
10065 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu
10066 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0
10067 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK)
10068 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u
10069 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5
10070 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u
10071 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6
10072 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u
10073 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7
10074 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK      0xFFFFFF00u
10075 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT     8
10076 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK)
10077 /* CLK_MISC0_TOG Bit Fields */
10078 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu
10079 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0
10080 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK)
10081 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u
10082 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5
10083 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u
10084 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6
10085 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u
10086 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7
10087 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK      0xFFFFFF00u
10088 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT     8
10089 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK)
10090 
10091 /*!
10092  * @}
10093  */ /* end of group CCM_ANALOG_Register_Masks */
10094 
10095 /* CCM_ANALOG - Peripheral instance base addresses */
10096 /** Peripheral CCM_ANALOG base address */
10097 #define CCM_ANALOG_BASE                          (0x30360000u)
10098 /** Peripheral CCM_ANALOG base pointer */
10099 #define CCM_ANALOG                               ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
10100 #define CCM_ANALOG_BASE_PTR                      (CCM_ANALOG)
10101 /** Array initializer of CCM_ANALOG peripheral base addresses */
10102 #define CCM_ANALOG_BASE_ADDRS                    { CCM_ANALOG_BASE }
10103 /** Array initializer of CCM_ANALOG peripheral base pointers */
10104 #define CCM_ANALOG_BASE_PTRS                     { CCM_ANALOG }
10105 /* ----------------------------------------------------------------------------
10106    -- CCM_ANALOG - Register accessor macros
10107    ---------------------------------------------------------------------------- */
10108 
10109 /*!
10110  * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros
10111  * @{
10112  */
10113 
10114 
10115 /* CCM_ANALOG - Register instance definitions */
10116 /* CCM_ANALOG */
10117 #define CCM_ANALOG_PLL_ARM                       CCM_ANALOG_PLL_ARM_REG(CCM_ANALOG_BASE_PTR)
10118 #define CCM_ANALOG_PLL_ARM_SET                   CCM_ANALOG_PLL_ARM_SET_REG(CCM_ANALOG_BASE_PTR)
10119 #define CCM_ANALOG_PLL_ARM_CLR                   CCM_ANALOG_PLL_ARM_CLR_REG(CCM_ANALOG_BASE_PTR)
10120 #define CCM_ANALOG_PLL_ARM_TOG                   CCM_ANALOG_PLL_ARM_TOG_REG(CCM_ANALOG_BASE_PTR)
10121 #define CCM_ANALOG_PLL_DDR                       CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG_BASE_PTR)
10122 #define CCM_ANALOG_PLL_DDR_SET                   CCM_ANALOG_PLL_DDR_SET_REG(CCM_ANALOG_BASE_PTR)
10123 #define CCM_ANALOG_PLL_DDR_CLR                   CCM_ANALOG_PLL_DDR_CLR_REG(CCM_ANALOG_BASE_PTR)
10124 #define CCM_ANALOG_PLL_DDR_TOG                   CCM_ANALOG_PLL_DDR_TOG_REG(CCM_ANALOG_BASE_PTR)
10125 #define CCM_ANALOG_PLL_DDR_SS                    CCM_ANALOG_PLL_DDR_SS_REG(CCM_ANALOG_BASE_PTR)
10126 #define CCM_ANALOG_PLL_DDR_NUM                   CCM_ANALOG_PLL_DDR_NUM_REG(CCM_ANALOG_BASE_PTR)
10127 #define CCM_ANALOG_PLL_DDR_DENOM                 CCM_ANALOG_PLL_DDR_DENOM_REG(CCM_ANALOG_BASE_PTR)
10128 #define CCM_ANALOG_PLL_480                       CCM_ANALOG_PLL_480_REG(CCM_ANALOG_BASE_PTR)
10129 #define CCM_ANALOG_PLL_480_SET                   CCM_ANALOG_PLL_480_SET_REG(CCM_ANALOG_BASE_PTR)
10130 #define CCM_ANALOG_PLL_480_CLR                   CCM_ANALOG_PLL_480_CLR_REG(CCM_ANALOG_BASE_PTR)
10131 #define CCM_ANALOG_PLL_480_TOG                   CCM_ANALOG_PLL_480_TOG_REG(CCM_ANALOG_BASE_PTR)
10132 #define CCM_ANALOG_PFD_480A                      CCM_ANALOG_PFD_480A_REG(CCM_ANALOG_BASE_PTR)
10133 #define CCM_ANALOG_PFD_480A_SET                  CCM_ANALOG_PFD_480A_SET_REG(CCM_ANALOG_BASE_PTR)
10134 #define CCM_ANALOG_PFD_480A_CLR                  CCM_ANALOG_PFD_480A_CLR_REG(CCM_ANALOG_BASE_PTR)
10135 #define CCM_ANALOG_PFD_480A_TOG                  CCM_ANALOG_PFD_480A_TOG_REG(CCM_ANALOG_BASE_PTR)
10136 #define CCM_ANALOG_PFD_480B                      CCM_ANALOG_PFD_480B_REG(CCM_ANALOG_BASE_PTR)
10137 #define CCM_ANALOG_PFD_480B_SET                  CCM_ANALOG_PFD_480B_SET_REG(CCM_ANALOG_BASE_PTR)
10138 #define CCM_ANALOG_PFD_480B_CLR                  CCM_ANALOG_PFD_480B_CLR_REG(CCM_ANALOG_BASE_PTR)
10139 #define CCM_ANALOG_PFD_480B_TOG                  CCM_ANALOG_PFD_480B_TOG_REG(CCM_ANALOG_BASE_PTR)
10140 #define CCM_ANALOG_PLL_ENET                      CCM_ANALOG_PLL_ENET_REG(CCM_ANALOG_BASE_PTR)
10141 #define CCM_ANALOG_PLL_ENET_SET                  CCM_ANALOG_PLL_ENET_SET_REG(CCM_ANALOG_BASE_PTR)
10142 #define CCM_ANALOG_PLL_ENET_CLR                  CCM_ANALOG_PLL_ENET_CLR_REG(CCM_ANALOG_BASE_PTR)
10143 #define CCM_ANALOG_PLL_ENET_TOG                  CCM_ANALOG_PLL_ENET_TOG_REG(CCM_ANALOG_BASE_PTR)
10144 #define CCM_ANALOG_PLL_AUDIO                     CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG_BASE_PTR)
10145 #define CCM_ANALOG_PLL_AUDIO_SET                 CCM_ANALOG_PLL_AUDIO_SET_REG(CCM_ANALOG_BASE_PTR)
10146 #define CCM_ANALOG_PLL_AUDIO_CLR                 CCM_ANALOG_PLL_AUDIO_CLR_REG(CCM_ANALOG_BASE_PTR)
10147 #define CCM_ANALOG_PLL_AUDIO_TOG                 CCM_ANALOG_PLL_AUDIO_TOG_REG(CCM_ANALOG_BASE_PTR)
10148 #define CCM_ANALOG_PLL_AUDIO_SS                  CCM_ANALOG_PLL_AUDIO_SS_REG(CCM_ANALOG_BASE_PTR)
10149 #define CCM_ANALOG_PLL_AUDIO_NUM                 CCM_ANALOG_PLL_AUDIO_NUM_REG(CCM_ANALOG_BASE_PTR)
10150 #define CCM_ANALOG_PLL_AUDIO_DENOM               CCM_ANALOG_PLL_AUDIO_DENOM_REG(CCM_ANALOG_BASE_PTR)
10151 #define CCM_ANALOG_PLL_VIDEO                     CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG_BASE_PTR)
10152 #define CCM_ANALOG_PLL_VIDEO_SET                 CCM_ANALOG_PLL_VIDEO_SET_REG(CCM_ANALOG_BASE_PTR)
10153 #define CCM_ANALOG_PLL_VIDEO_CLR                 CCM_ANALOG_PLL_VIDEO_CLR_REG(CCM_ANALOG_BASE_PTR)
10154 #define CCM_ANALOG_PLL_VIDEO_TOG                 CCM_ANALOG_PLL_VIDEO_TOG_REG(CCM_ANALOG_BASE_PTR)
10155 #define CCM_ANALOG_PLL_VIDEO_SS                  CCM_ANALOG_PLL_VIDEO_SS_REG(CCM_ANALOG_BASE_PTR)
10156 #define CCM_ANALOG_PLL_VIDEO_NUM                 CCM_ANALOG_PLL_VIDEO_NUM_REG(CCM_ANALOG_BASE_PTR)
10157 #define CCM_ANALOG_PLL_VIDEO_DENOM               CCM_ANALOG_PLL_VIDEO_DENOM_REG(CCM_ANALOG_BASE_PTR)
10158 #define CCM_ANALOG_CLK_MISC0                     CCM_ANALOG_CLK_MISC0_REG(CCM_ANALOG_BASE_PTR)
10159 #define CCM_ANALOG_CLK_MISC0_SET                 CCM_ANALOG_CLK_MISC0_SET_REG(CCM_ANALOG_BASE_PTR)
10160 #define CCM_ANALOG_CLK_MISC0_CLR                 CCM_ANALOG_CLK_MISC0_CLR_REG(CCM_ANALOG_BASE_PTR)
10161 #define CCM_ANALOG_CLK_MISC0_TOG                 CCM_ANALOG_CLK_MISC0_TOG_REG(CCM_ANALOG_BASE_PTR)
10162 /*!
10163  * @}
10164  */ /* end of group CCM_ANALOG_Register_Accessor_Macros */
10165 
10166 
10167 /*!
10168  * @}
10169  */ /* end of group CCM_ANALOG_Peripheral */
10170 
10171 /* ----------------------------------------------------------------------------
10172    -- CSI Peripheral Access Layer
10173    ---------------------------------------------------------------------------- */
10174 
10175 /*!
10176  * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
10177  * @{
10178  */
10179 
10180 /** CSI - Register Layout Typedef */
10181 typedef struct {
10182   __IO  uint32_t CSICR1;                                 /**< CSI Control Register 1, offset: 0x0 */
10183   __IO  uint32_t CSICR2;                                 /**< CSI Control Register 2, offset: 0x4 */
10184   __IO  uint32_t CSICR3;                                 /**< CSI Control Register 3, offset: 0x8 */
10185   __I   uint32_t CSISTATFIFO;                            /**< CSI Statistic FIFO Register, offset: 0xC */
10186   __I   uint32_t CSIRFIFO;                               /**< CSI RX FIFO Register, offset: 0x10 */
10187   __IO  uint32_t CSIRXCNT;                               /**< CSI RX Count Register, offset: 0x14 */
10188   __IO  uint32_t CSISR;                                  /**< CSI Status Register, offset: 0x18 */
10189   uint8_t RESERVED_0[4];
10190   __IO  uint32_t CSIDMASA_STATFIFO;                      /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
10191   __IO  uint32_t CSIDMATS_STATFIFO;                      /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
10192   __IO  uint32_t CSIDMASA_FB1;                           /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
10193   __IO  uint32_t CSIDMASA_FB2;                           /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
10194   __IO  uint32_t CSIFBUF_PARA;                           /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
10195   __IO  uint32_t CSIIMAG_PARA;                           /**< CSI Image Parameter Register, offset: 0x34 */
10196   uint8_t RESERVED_1[16];
10197   __IO  uint32_t CSICR18;                                /**< CSI Control Register 18, offset: 0x48 */
10198 } CSI_Type, *CSI_MemMapPtr;
10199 /* ----------------------------------------------------------------------------
10200    -- CSI - Register accessor macros
10201    ---------------------------------------------------------------------------- */
10202 
10203 /*!
10204  * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros
10205  * @{
10206  */
10207 
10208 
10209 /* CSI - Register accessors */
10210 #define CSI_CSICR1_REG(base)                     ((base)->CSICR1)
10211 #define CSI_CSICR2_REG(base)                     ((base)->CSICR2)
10212 #define CSI_CSICR3_REG(base)                     ((base)->CSICR3)
10213 #define CSI_CSISTATFIFO_REG(base)                ((base)->CSISTATFIFO)
10214 #define CSI_CSIRFIFO_REG(base)                   ((base)->CSIRFIFO)
10215 #define CSI_CSIRXCNT_REG(base)                   ((base)->CSIRXCNT)
10216 #define CSI_CSISR_REG(base)                      ((base)->CSISR)
10217 #define CSI_CSIDMASA_STATFIFO_REG(base)          ((base)->CSIDMASA_STATFIFO)
10218 #define CSI_CSIDMATS_STATFIFO_REG(base)          ((base)->CSIDMATS_STATFIFO)
10219 #define CSI_CSIDMASA_FB1_REG(base)               ((base)->CSIDMASA_FB1)
10220 #define CSI_CSIDMASA_FB2_REG(base)               ((base)->CSIDMASA_FB2)
10221 #define CSI_CSIFBUF_PARA_REG(base)               ((base)->CSIFBUF_PARA)
10222 #define CSI_CSIIMAG_PARA_REG(base)               ((base)->CSIIMAG_PARA)
10223 #define CSI_CSICR18_REG(base)                    ((base)->CSICR18)
10224 
10225 /*!
10226  * @}
10227  */ /* end of group CSI_Register_Accessor_Macros */
10228 /* ----------------------------------------------------------------------------
10229    -- CSI Register Masks
10230    ---------------------------------------------------------------------------- */
10231 
10232 /*!
10233  * @addtogroup CSI_Register_Masks CSI Register Masks
10234  * @{
10235  */
10236 
10237 /* CSICR1 Bit Fields */
10238 #define CSI_CSICR1_PIXEL_BIT_MASK                0x1u
10239 #define CSI_CSICR1_PIXEL_BIT_SHIFT               0
10240 #define CSI_CSICR1_REDGE_MASK                    0x2u
10241 #define CSI_CSICR1_REDGE_SHIFT                   1
10242 #define CSI_CSICR1_INV_PCLK_MASK                 0x4u
10243 #define CSI_CSICR1_INV_PCLK_SHIFT                2
10244 #define CSI_CSICR1_INV_DATA_MASK                 0x8u
10245 #define CSI_CSICR1_INV_DATA_SHIFT                3
10246 #define CSI_CSICR1_GCLK_MODE_MASK                0x10u
10247 #define CSI_CSICR1_GCLK_MODE_SHIFT               4
10248 #define CSI_CSICR1_CLR_RXFIFO_MASK               0x20u
10249 #define CSI_CSICR1_CLR_RXFIFO_SHIFT              5
10250 #define CSI_CSICR1_CLR_STATFIFO_MASK             0x40u
10251 #define CSI_CSICR1_CLR_STATFIFO_SHIFT            6
10252 #define CSI_CSICR1_PACK_DIR_MASK                 0x80u
10253 #define CSI_CSICR1_PACK_DIR_SHIFT                7
10254 #define CSI_CSICR1_FCC_MASK                      0x100u
10255 #define CSI_CSICR1_FCC_SHIFT                     8
10256 #define CSI_CSICR1_CCIR_EN_MASK                  0x400u
10257 #define CSI_CSICR1_CCIR_EN_SHIFT                 10
10258 #define CSI_CSICR1_HSYNC_POL_MASK                0x800u
10259 #define CSI_CSICR1_HSYNC_POL_SHIFT               11
10260 #define CSI_CSICR1_SOF_INTEN_MASK                0x10000u
10261 #define CSI_CSICR1_SOF_INTEN_SHIFT               16
10262 #define CSI_CSICR1_SOF_POL_MASK                  0x20000u
10263 #define CSI_CSICR1_SOF_POL_SHIFT                 17
10264 #define CSI_CSICR1_RXFF_INTEN_MASK               0x40000u
10265 #define CSI_CSICR1_RXFF_INTEN_SHIFT              18
10266 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK       0x80000u
10267 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT      19
10268 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK       0x100000u
10269 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT      20
10270 #define CSI_CSICR1_STATFF_INTEN_MASK             0x200000u
10271 #define CSI_CSICR1_STATFF_INTEN_SHIFT            21
10272 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK       0x400000u
10273 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT      22
10274 #define CSI_CSICR1_RF_OR_INTEN_MASK              0x1000000u
10275 #define CSI_CSICR1_RF_OR_INTEN_SHIFT             24
10276 #define CSI_CSICR1_SF_OR_INTEN_MASK              0x2000000u
10277 #define CSI_CSICR1_SF_OR_INTEN_SHIFT             25
10278 #define CSI_CSICR1_COF_INT_EN_MASK               0x4000000u
10279 #define CSI_CSICR1_COF_INT_EN_SHIFT              26
10280 #define CSI_CSICR1_VIDEO_MODE_MASK               0x8000000u
10281 #define CSI_CSICR1_VIDEO_MODE_SHIFT              27
10282 #define CSI_CSICR1_PrP_IF_EN_MASK                0x10000000u
10283 #define CSI_CSICR1_PrP_IF_EN_SHIFT               28
10284 #define CSI_CSICR1_EOF_INT_EN_MASK               0x20000000u
10285 #define CSI_CSICR1_EOF_INT_EN_SHIFT              29
10286 #define CSI_CSICR1_EXT_VSYNC_MASK                0x40000000u
10287 #define CSI_CSICR1_EXT_VSYNC_SHIFT               30
10288 #define CSI_CSICR1_SWAP16_EN_MASK                0x80000000u
10289 #define CSI_CSICR1_SWAP16_EN_SHIFT               31
10290 /* CSICR2 Bit Fields */
10291 #define CSI_CSICR2_HSC_MASK                      0xFFu
10292 #define CSI_CSICR2_HSC_SHIFT                     0
10293 #define CSI_CSICR2_HSC(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_HSC_SHIFT))&CSI_CSICR2_HSC_MASK)
10294 #define CSI_CSICR2_VSC_MASK                      0xFF00u
10295 #define CSI_CSICR2_VSC_SHIFT                     8
10296 #define CSI_CSICR2_VSC(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_VSC_SHIFT))&CSI_CSICR2_VSC_MASK)
10297 #define CSI_CSICR2_LVRM_MASK                     0x70000u
10298 #define CSI_CSICR2_LVRM_SHIFT                    16
10299 #define CSI_CSICR2_LVRM(x)                       (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_LVRM_SHIFT))&CSI_CSICR2_LVRM_MASK)
10300 #define CSI_CSICR2_BTS_MASK                      0x180000u
10301 #define CSI_CSICR2_BTS_SHIFT                     19
10302 #define CSI_CSICR2_BTS(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_BTS_SHIFT))&CSI_CSICR2_BTS_MASK)
10303 #define CSI_CSICR2_SCE_MASK                      0x800000u
10304 #define CSI_CSICR2_SCE_SHIFT                     23
10305 #define CSI_CSICR2_AFS_MASK                      0x3000000u
10306 #define CSI_CSICR2_AFS_SHIFT                     24
10307 #define CSI_CSICR2_AFS(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_AFS_SHIFT))&CSI_CSICR2_AFS_MASK)
10308 #define CSI_CSICR2_DRM_MASK                      0x4000000u
10309 #define CSI_CSICR2_DRM_SHIFT                     26
10310 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK       0x30000000u
10311 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT      28
10312 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)         (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
10313 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK       0xC0000000u
10314 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT      30
10315 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)         (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
10316 /* CSICR3 Bit Fields */
10317 #define CSI_CSICR3_ECC_AUTO_EN_MASK              0x1u
10318 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT             0
10319 #define CSI_CSICR3_ECC_INT_EN_MASK               0x2u
10320 #define CSI_CSICR3_ECC_INT_EN_SHIFT              1
10321 #define CSI_CSICR3_ZERO_PACK_EN_MASK             0x4u
10322 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT            2
10323 #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK          0x8u
10324 #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT         3
10325 #define CSI_CSICR3_RxFF_LEVEL_MASK               0x70u
10326 #define CSI_CSICR3_RxFF_LEVEL_SHIFT              4
10327 #define CSI_CSICR3_RxFF_LEVEL(x)                 (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_RxFF_LEVEL_SHIFT))&CSI_CSICR3_RxFF_LEVEL_MASK)
10328 #define CSI_CSICR3_HRESP_ERR_EN_MASK             0x80u
10329 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT            7
10330 #define CSI_CSICR3_STATFF_LEVEL_MASK             0x700u
10331 #define CSI_CSICR3_STATFF_LEVEL_SHIFT            8
10332 #define CSI_CSICR3_STATFF_LEVEL(x)               (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_STATFF_LEVEL_SHIFT))&CSI_CSICR3_STATFF_LEVEL_MASK)
10333 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK           0x800u
10334 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT          11
10335 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK           0x1000u
10336 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT          12
10337 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK          0x2000u
10338 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT         13
10339 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK          0x4000u
10340 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT         14
10341 #define CSI_CSICR3_FRMCNT_RST_MASK               0x8000u
10342 #define CSI_CSICR3_FRMCNT_RST_SHIFT              15
10343 #define CSI_CSICR3_FRMCNT_MASK                   0xFFFF0000u
10344 #define CSI_CSICR3_FRMCNT_SHIFT                  16
10345 #define CSI_CSICR3_FRMCNT(x)                     (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_FRMCNT_SHIFT))&CSI_CSICR3_FRMCNT_MASK)
10346 /* CSISTATFIFO Bit Fields */
10347 #define CSI_CSISTATFIFO_STAT_MASK                0xFFFFFFFFu
10348 #define CSI_CSISTATFIFO_STAT_SHIFT               0
10349 #define CSI_CSISTATFIFO_STAT(x)                  (((uint32_t)(((uint32_t)(x))<<CSI_CSISTATFIFO_STAT_SHIFT))&CSI_CSISTATFIFO_STAT_MASK)
10350 /* CSIRFIFO Bit Fields */
10351 #define CSI_CSIRFIFO_IMAGE_MASK                  0xFFFFFFFFu
10352 #define CSI_CSIRFIFO_IMAGE_SHIFT                 0
10353 #define CSI_CSIRFIFO_IMAGE(x)                    (((uint32_t)(((uint32_t)(x))<<CSI_CSIRFIFO_IMAGE_SHIFT))&CSI_CSIRFIFO_IMAGE_MASK)
10354 /* CSIRXCNT Bit Fields */
10355 #define CSI_CSIRXCNT_RXCNT_MASK                  0x3FFFFFu
10356 #define CSI_CSIRXCNT_RXCNT_SHIFT                 0
10357 #define CSI_CSIRXCNT_RXCNT(x)                    (((uint32_t)(((uint32_t)(x))<<CSI_CSIRXCNT_RXCNT_SHIFT))&CSI_CSIRXCNT_RXCNT_MASK)
10358 /* CSISR Bit Fields */
10359 #define CSI_CSISR_DRDY_MASK                      0x1u
10360 #define CSI_CSISR_DRDY_SHIFT                     0
10361 #define CSI_CSISR_ECC_INT_MASK                   0x2u
10362 #define CSI_CSISR_ECC_INT_SHIFT                  1
10363 #define CSI_CSISR_HRESP_ERR_INT_MASK             0x80u
10364 #define CSI_CSISR_HRESP_ERR_INT_SHIFT            7
10365 #define CSI_CSISR_COF_INT_MASK                   0x2000u
10366 #define CSI_CSISR_COF_INT_SHIFT                  13
10367 #define CSI_CSISR_F1_INT_MASK                    0x4000u
10368 #define CSI_CSISR_F1_INT_SHIFT                   14
10369 #define CSI_CSISR_F2_INT_MASK                    0x8000u
10370 #define CSI_CSISR_F2_INT_SHIFT                   15
10371 #define CSI_CSISR_SOF_INT_MASK                   0x10000u
10372 #define CSI_CSISR_SOF_INT_SHIFT                  16
10373 #define CSI_CSISR_EOF_INT_MASK                   0x20000u
10374 #define CSI_CSISR_EOF_INT_SHIFT                  17
10375 #define CSI_CSISR_RxFF_INT_MASK                  0x40000u
10376 #define CSI_CSISR_RxFF_INT_SHIFT                 18
10377 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK          0x80000u
10378 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT         19
10379 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK          0x100000u
10380 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT         20
10381 #define CSI_CSISR_STATFF_INT_MASK                0x200000u
10382 #define CSI_CSISR_STATFF_INT_SHIFT               21
10383 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK          0x400000u
10384 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT         22
10385 #define CSI_CSISR_RF_OR_INT_MASK                 0x1000000u
10386 #define CSI_CSISR_RF_OR_INT_SHIFT                24
10387 #define CSI_CSISR_SF_OR_INT_MASK                 0x2000000u
10388 #define CSI_CSISR_SF_OR_INT_SHIFT                25
10389 #define CSI_CSISR_DMA_FIELD1_DONE_MASK           0x4000000u
10390 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT          26
10391 #define CSI_CSISR_DMA_FIELD0_DONE_MASK           0x8000000u
10392 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT          27
10393 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK    0x10000000u
10394 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT   28
10395 /* CSIDMASA_STATFIFO Bit Fields */
10396 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK 0xFFFFFFFCu
10397 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT 2
10398 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT))&CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
10399 /* CSIDMATS_STATFIFO Bit Fields */
10400 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK 0xFFFFFFFFu
10401 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT 0
10402 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT))&CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
10403 /* CSIDMASA_FB1 Bit Fields */
10404 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK 0xFFFFFFFCu
10405 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT 2
10406 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)   (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT))&CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
10407 /* CSIDMASA_FB2 Bit Fields */
10408 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK 0xFFFFFFFCu
10409 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT 2
10410 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)   (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT))&CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
10411 /* CSIFBUF_PARA Bit Fields */
10412 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK        0xFFFFu
10413 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT       0
10414 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x)          (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
10415 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK 0xFFFF0000u
10416 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT 16
10417 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x)   (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
10418 /* CSIIMAG_PARA Bit Fields */
10419 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK       0xFFFFu
10420 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT      0
10421 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)         (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
10422 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK        0xFFFF0000u
10423 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT       16
10424 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)          (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
10425 /* CSICR18 Bit Fields */
10426 #define CSI_CSICR18_DEINTERLACE_EN_MASK          0x4u
10427 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT         2
10428 #define CSI_CSICR18_PARALLEL24_EN_MASK           0x8u
10429 #define CSI_CSICR18_PARALLEL24_EN_SHIFT          3
10430 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK      0x10u
10431 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT     4
10432 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     0x20u
10433 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT    5
10434 #define CSI_CSICR18_FIELD0_DONE_IE_MASK          0x40u
10435 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT         6
10436 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK      0x80u
10437 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     7
10438 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK        0x100u
10439 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT       8
10440 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK 0x200u
10441 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT 9
10442 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK      0x400u
10443 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     10
10444 #define CSI_CSICR18_AHB_HPROT_MASK               0xF000u
10445 #define CSI_CSICR18_AHB_HPROT_SHIFT              12
10446 #define CSI_CSICR18_AHB_HPROT(x)                 (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_AHB_HPROT_SHIFT))&CSI_CSICR18_AHB_HPROT_MASK)
10447 #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK  0x30000u
10448 #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT 16
10449 #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x)    (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT))&CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK)
10450 #define CSI_CSICR18_MASK_OPTION_MASK             0xC0000u
10451 #define CSI_CSICR18_MASK_OPTION_SHIFT            18
10452 #define CSI_CSICR18_MASK_OPTION(x)               (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MASK_OPTION_SHIFT))&CSI_CSICR18_MASK_OPTION_MASK)
10453 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK       0x100000u
10454 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT      20
10455 #define CSI_CSICR18_MIPI_YU_SWAP_MASK            0x200000u
10456 #define CSI_CSICR18_MIPI_YU_SWAP_SHIFT           21
10457 #define CSI_CSICR18_DATA_FROM_MIPI_MASK          0x400000u
10458 #define CSI_CSICR18_DATA_FROM_MIPI_SHIFT         22
10459 #define CSI_CSICR18_LINE_STRIDE_EN_MASK          0x1000000u
10460 #define CSI_CSICR18_LINE_STRIDE_EN_SHIFT         24
10461 #define CSI_CSICR18_MIPI_DATA_FORMAT_MASK        0x7E000000u
10462 #define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT       25
10463 #define CSI_CSICR18_MIPI_DATA_FORMAT(x)          (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT))&CSI_CSICR18_MIPI_DATA_FORMAT_MASK)
10464 #define CSI_CSICR18_CSI_ENABLE_MASK              0x80000000u
10465 #define CSI_CSICR18_CSI_ENABLE_SHIFT             31
10466 
10467 /*!
10468  * @}
10469  */ /* end of group CSI_Register_Masks */
10470 
10471 /* CSI - Peripheral instance base addresses */
10472 /** Peripheral CSI1 base address */
10473 #define CSI1_BASE                                (0x30710000u)
10474 /** Peripheral CSI1 base pointer */
10475 #define CSI1                                     ((CSI_Type *)CSI1_BASE)
10476 #define CSI1_BASE_PTR                            (CSI1)
10477 /** Peripheral CSI2 base address */
10478 #define CSI2_BASE                                (0x30718000u)
10479 /** Peripheral CSI2 base pointer */
10480 #define CSI2                                     ((CSI_Type *)CSI2_BASE)
10481 #define CSI2_BASE_PTR                            (CSI2)
10482 /** Array initializer of CSI peripheral base addresses */
10483 #define CSI_BASE_ADDRS                           { CSI1_BASE, CSI2_BASE }
10484 /** Array initializer of CSI peripheral base pointers */
10485 #define CSI_BASE_PTRS                            { CSI1, CSI2 }
10486 /* ----------------------------------------------------------------------------
10487    -- CSI - Register accessor macros
10488    ---------------------------------------------------------------------------- */
10489 
10490 /*!
10491  * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros
10492  * @{
10493  */
10494 
10495 
10496 /* CSI - Register instance definitions */
10497 /* CSI1 */
10498 #define CSI1_CSICR1                              CSI_CSICR1_REG(CSI1_BASE_PTR)
10499 #define CSI1_CSICR2                              CSI_CSICR2_REG(CSI1_BASE_PTR)
10500 #define CSI1_CSICR3                              CSI_CSICR3_REG(CSI1_BASE_PTR)
10501 #define CSI1_CSISTATFIFO                         CSI_CSISTATFIFO_REG(CSI1_BASE_PTR)
10502 #define CSI1_CSIRFIFO                            CSI_CSIRFIFO_REG(CSI1_BASE_PTR)
10503 #define CSI1_CSIRXCNT                            CSI_CSIRXCNT_REG(CSI1_BASE_PTR)
10504 #define CSI1_CSISR                               CSI_CSISR_REG(CSI1_BASE_PTR)
10505 #define CSI1_CSIDMASA_STATFIFO                   CSI_CSIDMASA_STATFIFO_REG(CSI1_BASE_PTR)
10506 #define CSI1_CSIDMATS_STATFIFO                   CSI_CSIDMATS_STATFIFO_REG(CSI1_BASE_PTR)
10507 #define CSI1_CSIDMASA_FB1                        CSI_CSIDMASA_FB1_REG(CSI1_BASE_PTR)
10508 #define CSI1_CSIDMASA_FB2                        CSI_CSIDMASA_FB2_REG(CSI1_BASE_PTR)
10509 #define CSI1_CSIFBUF_PARA                        CSI_CSIFBUF_PARA_REG(CSI1_BASE_PTR)
10510 #define CSI1_CSIIMAG_PARA                        CSI_CSIIMAG_PARA_REG(CSI1_BASE_PTR)
10511 #define CSI1_CSICR18                             CSI_CSICR18_REG(CSI1_BASE_PTR)
10512 /* CSI2 */
10513 #define CSI2_CSICR1                              CSI_CSICR1_REG(CSI2_BASE_PTR)
10514 #define CSI2_CSICR2                              CSI_CSICR2_REG(CSI2_BASE_PTR)
10515 #define CSI2_CSICR3                              CSI_CSICR3_REG(CSI2_BASE_PTR)
10516 #define CSI2_CSISTATFIFO                         CSI_CSISTATFIFO_REG(CSI2_BASE_PTR)
10517 #define CSI2_CSIRFIFO                            CSI_CSIRFIFO_REG(CSI2_BASE_PTR)
10518 #define CSI2_CSIRXCNT                            CSI_CSIRXCNT_REG(CSI2_BASE_PTR)
10519 #define CSI2_CSISR                               CSI_CSISR_REG(CSI2_BASE_PTR)
10520 #define CSI2_CSIDMASA_STATFIFO                   CSI_CSIDMASA_STATFIFO_REG(CSI2_BASE_PTR)
10521 #define CSI2_CSIDMATS_STATFIFO                   CSI_CSIDMATS_STATFIFO_REG(CSI2_BASE_PTR)
10522 #define CSI2_CSIDMASA_FB1                        CSI_CSIDMASA_FB1_REG(CSI2_BASE_PTR)
10523 #define CSI2_CSIDMASA_FB2                        CSI_CSIDMASA_FB2_REG(CSI2_BASE_PTR)
10524 #define CSI2_CSIFBUF_PARA                        CSI_CSIFBUF_PARA_REG(CSI2_BASE_PTR)
10525 #define CSI2_CSIIMAG_PARA                        CSI_CSIIMAG_PARA_REG(CSI2_BASE_PTR)
10526 #define CSI2_CSICR18                             CSI_CSICR18_REG(CSI2_BASE_PTR)
10527 /*!
10528  * @}
10529  */ /* end of group CSI_Register_Accessor_Macros */
10530 
10531 
10532 /*!
10533  * @}
10534  */ /* end of group CSI_Peripheral */
10535 
10536 /* ----------------------------------------------------------------------------
10537    -- DDRC Peripheral Access Layer
10538    ---------------------------------------------------------------------------- */
10539 
10540 /*!
10541  * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
10542  * @{
10543  */
10544 
10545 /** DDRC - Register Layout Typedef */
10546 typedef struct {
10547   __IO  uint32_t MSTR;                                   /**< Master Register, offset: 0x0 */
10548   __IO  uint32_t STAT;                                   /**< Operating Mode Status Register, offset: 0x4 */
10549   uint8_t RESERVED_0[8];
10550   __IO  uint32_t MRCTRL0;                                /**< Mode Register Read / Write Control Register 0, offset: 0x10 */
10551   __IO  uint32_t MRCTRL1;                                /**< Mode Register Read / Write Control Register 1, offset: 0x14 */
10552   __I   uint32_t MRSTAT;                                 /**< Mode Register Read / Write Status Register, offset: 0x18 */
10553   uint8_t RESERVED_1[4];
10554   __IO  uint32_t DERATEEN;                               /**< Temperature Derate Enable Register, offset: 0x20 */
10555   __IO  uint32_t DERATEINT;                              /**< Temperature Derate Interval Register, offset: 0x24 */
10556   uint8_t RESERVED_2[8];
10557   __IO  uint32_t PWRCTL;                                 /**< Low Power Control Register, offset: 0x30 */
10558   __IO  uint32_t PWRTMG;                                 /**< Low Power Timing Register, offset: 0x34 */
10559   __IO  uint32_t HWLPCTL;                                /**< Hardware Low Power Control Register, offset: 0x38 */
10560   uint8_t RESERVED_3[20];
10561   __IO  uint32_t RFSHCTL0;                               /**< Refresh Control Register 0, offset: 0x50 */
10562   __IO  uint32_t RFSHCTL1;                               /**< Refresh Control Register 1, offset: 0x54 */
10563   uint8_t RESERVED_4[8];
10564   __IO  uint32_t RFSHCTL3;                               /**< Refresh Control Register 0, offset: 0x60 */
10565   __IO  uint32_t RFSHTMG;                                /**< Refresh Timing Register, offset: 0x64 */
10566   uint8_t RESERVED_5[104];
10567   __IO  uint32_t INIT0;                                  /**< SDRAM Initialization Register 0, offset: 0xD0 */
10568   __IO  uint32_t INIT1;                                  /**< SDRAM Initialization Register 1, offset: 0xD4 */
10569   __IO  uint32_t INIT2;                                  /**< SDRAM Initialization Register 2, offset: 0xD8 */
10570   __IO  uint32_t INIT3;                                  /**< SDRAM Initialization Register 3, offset: 0xDC */
10571   __IO  uint32_t INIT4;                                  /**< SDRAM Initialization Register 4, offset: 0xE0 */
10572   __IO  uint32_t INIT5;                                  /**< SDRAM Initialization Register 5, offset: 0xE4 */
10573   uint8_t RESERVED_6[12];
10574   __IO  uint32_t RANKCTL;                                /**< Rank Control Register, offset: 0xF4 */
10575   uint8_t RESERVED_7[8];
10576   __IO  uint32_t DRAMTMG0;                               /**< SDRAM Timing Register 0, offset: 0x100 */
10577   __IO  uint32_t DRAMTMG1;                               /**< SDRAM Timing Register 1, offset: 0x104 */
10578   __IO  uint32_t DRAMTMG2;                               /**< SDRAM Timing Register 2, offset: 0x108 */
10579   __IO  uint32_t DRAMTMG3;                               /**< SDRAM Timing Register 3, offset: 0x10C */
10580   __IO  uint32_t DRAMTMG4;                               /**< SDRAM Timing Register 4, offset: 0x110 */
10581   __IO  uint32_t DRAMTMG5;                               /**< SDRAM Timing Register5, offset: 0x114 */
10582   __IO  uint32_t DRAMTMG6;                               /**< SDRAM Timing Register 6, offset: 0x118 */
10583   __IO  uint32_t DRAMTMG7;                               /**< SDRAM Timing Register 7, offset: 0x11C */
10584   __IO  uint32_t DRAMTMG8;                               /**< SDRAM Timing Register 8, offset: 0x120 */
10585   uint8_t RESERVED_8[92];
10586   __IO  uint32_t ZQCTL0;                                 /**< ZQ Control Register 0, offset: 0x180 */
10587   __IO  uint32_t ZQCTL1;                                 /**< ZQ Control Register 1, offset: 0x184 */
10588   __IO  uint32_t ZQCTL2;                                 /**< ZQ Control Register 2, offset: 0x188 */
10589   __IO  uint32_t ZQSTAT;                                 /**< ZQ Status Register, offset: 0x18C */
10590   __IO  uint32_t DFITMG0;                                /**< DFI Timing Register 0, offset: 0x190 */
10591   __IO  uint32_t DFITMG1;                                /**< DFI Timing Register 1, offset: 0x194 */
10592   __IO  uint32_t DFILPCFG0;                              /**< DFI Low Power Configuration Register 0, offset: 0x198 */
10593   uint8_t RESERVED_9[4];
10594   __IO  uint32_t DFIUPD0;                                /**< DFI Update Register 0, offset: 0x1A0 */
10595   __IO  uint32_t DFIUPD1;                                /**< DFI Update Register 1, offset: 0x1A4 */
10596   __IO  uint32_t DFIUPD2;                                /**< DFI Update Register 2, offset: 0x1A8 */
10597   __IO  uint32_t DFIUPD3;                                /**< DFI Update Register 3, offset: 0x1AC */
10598   __IO  uint32_t DFIMISC;                                /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
10599   uint8_t RESERVED_10[76];
10600   __IO  uint32_t ADDRMAP0;                               /**< Address Map Register 0, offset: 0x200 */
10601   __IO  uint32_t ADDRMAP1;                               /**< Address Map Register 1, offset: 0x204 */
10602   __IO  uint32_t ADDRMAP2;                               /**< Address Map Register 2, offset: 0x208 */
10603   __IO  uint32_t ADDRMAP3;                               /**< Address Map Register 3, offset: 0x20C */
10604   __IO  uint32_t ADDRMAP4;                               /**< Address Map Register 4, offset: 0x210 */
10605   __IO  uint32_t ADDRMAP5;                               /**< Address Map Register 5, offset: 0x214 */
10606   __IO  uint32_t ADDRMAP6;                               /**< Address Map Register 6, offset: 0x218 */
10607   uint8_t RESERVED_11[36];
10608   __IO  uint32_t ODTCFG;                                 /**< ODT Configuration Register, offset: 0x240 */
10609   __IO  uint32_t ODTMAP;                                 /**< ODT / Rank Map Register, offset: 0x244 */
10610   uint8_t RESERVED_12[8];
10611   __IO  uint32_t SCHED;                                  /**< Scheduler Control Register, offset: 0x250 */
10612   __IO  uint32_t SCHED1;                                 /**< Scheduler Control Register 1, offset: 0x254 */
10613   uint8_t RESERVED_13[4];
10614   __IO  uint32_t PERFHPR1;                               /**< High Priority Read CAM Register 1, offset: 0x25C */
10615   uint8_t RESERVED_14[4];
10616   __IO  uint32_t PERFLPR1;                               /**< Low Priority Read CAM Register 1, offset: 0x264 */
10617   uint8_t RESERVED_15[4];
10618   __IO  uint32_t PERFWR1;                                /**< Write CAM Register 1, offset: 0x26C */
10619   uint8_t RESERVED_16[4];
10620   __IO  uint32_t PERFVPR1;                               /**< Variable Priority Read CAM Register 1, offset: 0x274 */
10621   __IO  uint32_t PERFVPW1;                               /**< Variable Priority Write CAM Register 1, offset: 0x278 */
10622   uint8_t RESERVED_17[132];
10623   __IO  uint32_t DBG0;                                   /**< Debug Register 0, offset: 0x300 */
10624   __IO  uint32_t DBG1;                                   /**< Debug Register 1, offset: 0x304 */
10625   __IO  uint32_t DBGCAM;                                 /**< CAM Debug Register, offset: 0x308 */
10626   __IO  uint32_t DBGCMD;                                 /**< Command Debug Register, offset: 0x30C */
10627   __IO  uint32_t DBGSTAT;                                /**< Status Debug Register, offset: 0x310 */
10628   uint8_t RESERVED_18[12];
10629   __IO  uint32_t SWCTL;                                  /**< Software Register Programming Control Enable, offset: 0x320 */
10630   __I   uint32_t SWSTAT;                                 /**< Software Register Programming Control Status, offset: 0x324 */
10631 } DDRC_Type, *DDRC_MemMapPtr;
10632 /* ----------------------------------------------------------------------------
10633    -- DDRC - Register accessor macros
10634    ---------------------------------------------------------------------------- */
10635 
10636 /*!
10637  * @addtogroup DDRC_Register_Accessor_Macros DDRC - Register accessor macros
10638  * @{
10639  */
10640 
10641 
10642 /* DDRC - Register accessors */
10643 #define DDRC_MSTR_REG(base)                      ((base)->MSTR)
10644 #define DDRC_STAT_REG(base)                      ((base)->STAT)
10645 #define DDRC_MRCTRL0_REG(base)                   ((base)->MRCTRL0)
10646 #define DDRC_MRCTRL1_REG(base)                   ((base)->MRCTRL1)
10647 #define DDRC_MRSTAT_REG(base)                    ((base)->MRSTAT)
10648 #define DDRC_DERATEEN_REG(base)                  ((base)->DERATEEN)
10649 #define DDRC_DERATEINT_REG(base)                 ((base)->DERATEINT)
10650 #define DDRC_PWRCTL_REG(base)                    ((base)->PWRCTL)
10651 #define DDRC_PWRTMG_REG(base)                    ((base)->PWRTMG)
10652 #define DDRC_HWLPCTL_REG(base)                   ((base)->HWLPCTL)
10653 #define DDRC_RFSHCTL0_REG(base)                  ((base)->RFSHCTL0)
10654 #define DDRC_RFSHCTL1_REG(base)                  ((base)->RFSHCTL1)
10655 #define DDRC_RFSHCTL3_REG(base)                  ((base)->RFSHCTL3)
10656 #define DDRC_RFSHTMG_REG(base)                   ((base)->RFSHTMG)
10657 #define DDRC_INIT0_REG(base)                     ((base)->INIT0)
10658 #define DDRC_INIT1_REG(base)                     ((base)->INIT1)
10659 #define DDRC_INIT2_REG(base)                     ((base)->INIT2)
10660 #define DDRC_INIT3_REG(base)                     ((base)->INIT3)
10661 #define DDRC_INIT4_REG(base)                     ((base)->INIT4)
10662 #define DDRC_INIT5_REG(base)                     ((base)->INIT5)
10663 #define DDRC_RANKCTL_REG(base)                   ((base)->RANKCTL)
10664 #define DDRC_DRAMTMG0_REG(base)                  ((base)->DRAMTMG0)
10665 #define DDRC_DRAMTMG1_REG(base)                  ((base)->DRAMTMG1)
10666 #define DDRC_DRAMTMG2_REG(base)                  ((base)->DRAMTMG2)
10667 #define DDRC_DRAMTMG3_REG(base)                  ((base)->DRAMTMG3)
10668 #define DDRC_DRAMTMG4_REG(base)                  ((base)->DRAMTMG4)
10669 #define DDRC_DRAMTMG5_REG(base)                  ((base)->DRAMTMG5)
10670 #define DDRC_DRAMTMG6_REG(base)                  ((base)->DRAMTMG6)
10671 #define DDRC_DRAMTMG7_REG(base)                  ((base)->DRAMTMG7)
10672 #define DDRC_DRAMTMG8_REG(base)                  ((base)->DRAMTMG8)
10673 #define DDRC_ZQCTL0_REG(base)                    ((base)->ZQCTL0)
10674 #define DDRC_ZQCTL1_REG(base)                    ((base)->ZQCTL1)
10675 #define DDRC_ZQCTL2_REG(base)                    ((base)->ZQCTL2)
10676 #define DDRC_ZQSTAT_REG(base)                    ((base)->ZQSTAT)
10677 #define DDRC_DFITMG0_REG(base)                   ((base)->DFITMG0)
10678 #define DDRC_DFITMG1_REG(base)                   ((base)->DFITMG1)
10679 #define DDRC_DFILPCFG0_REG(base)                 ((base)->DFILPCFG0)
10680 #define DDRC_DFIUPD0_REG(base)                   ((base)->DFIUPD0)
10681 #define DDRC_DFIUPD1_REG(base)                   ((base)->DFIUPD1)
10682 #define DDRC_DFIUPD2_REG(base)                   ((base)->DFIUPD2)
10683 #define DDRC_DFIUPD3_REG(base)                   ((base)->DFIUPD3)
10684 #define DDRC_DFIMISC_REG(base)                   ((base)->DFIMISC)
10685 #define DDRC_ADDRMAP0_REG(base)                  ((base)->ADDRMAP0)
10686 #define DDRC_ADDRMAP1_REG(base)                  ((base)->ADDRMAP1)
10687 #define DDRC_ADDRMAP2_REG(base)                  ((base)->ADDRMAP2)
10688 #define DDRC_ADDRMAP3_REG(base)                  ((base)->ADDRMAP3)
10689 #define DDRC_ADDRMAP4_REG(base)                  ((base)->ADDRMAP4)
10690 #define DDRC_ADDRMAP5_REG(base)                  ((base)->ADDRMAP5)
10691 #define DDRC_ADDRMAP6_REG(base)                  ((base)->ADDRMAP6)
10692 #define DDRC_ODTCFG_REG(base)                    ((base)->ODTCFG)
10693 #define DDRC_ODTMAP_REG(base)                    ((base)->ODTMAP)
10694 #define DDRC_SCHED_REG(base)                     ((base)->SCHED)
10695 #define DDRC_SCHED1_REG(base)                    ((base)->SCHED1)
10696 #define DDRC_PERFHPR1_REG(base)                  ((base)->PERFHPR1)
10697 #define DDRC_PERFLPR1_REG(base)                  ((base)->PERFLPR1)
10698 #define DDRC_PERFWR1_REG(base)                   ((base)->PERFWR1)
10699 #define DDRC_PERFVPR1_REG(base)                  ((base)->PERFVPR1)
10700 #define DDRC_PERFVPW1_REG(base)                  ((base)->PERFVPW1)
10701 #define DDRC_DBG0_REG(base)                      ((base)->DBG0)
10702 #define DDRC_DBG1_REG(base)                      ((base)->DBG1)
10703 #define DDRC_DBGCAM_REG(base)                    ((base)->DBGCAM)
10704 #define DDRC_DBGCMD_REG(base)                    ((base)->DBGCMD)
10705 #define DDRC_DBGSTAT_REG(base)                   ((base)->DBGSTAT)
10706 #define DDRC_SWCTL_REG(base)                     ((base)->SWCTL)
10707 #define DDRC_SWSTAT_REG(base)                    ((base)->SWSTAT)
10708 
10709 /*!
10710  * @}
10711  */ /* end of group DDRC_Register_Accessor_Macros */
10712 /* ----------------------------------------------------------------------------
10713    -- DDRC Register Masks
10714    ---------------------------------------------------------------------------- */
10715 
10716 /*!
10717  * @addtogroup DDRC_Register_Masks DDRC Register Masks
10718  * @{
10719  */
10720 
10721 /* MSTR Bit Fields */
10722 #define DDRC_MSTR_DDR3_MASK                      0x1u
10723 #define DDRC_MSTR_DDR3_SHIFT                     0
10724 #define DDRC_MSTR_LPDDR2_MASK                    0x4u
10725 #define DDRC_MSTR_LPDDR2_SHIFT                   2
10726 #define DDRC_MSTR_LPDDR3_MASK                    0x8u
10727 #define DDRC_MSTR_LPDDR3_SHIFT                   3
10728 #define DDRC_MSTR_BURST_MODE_MASK                0x100u
10729 #define DDRC_MSTR_BURST_MODE_SHIFT               8
10730 #define DDRC_MSTR_BURSTCHOP_MASK                 0x200u
10731 #define DDRC_MSTR_BURSTCHOP_SHIFT                9
10732 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK            0x3000u
10733 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT           12
10734 #define DDRC_MSTR_DATA_BUS_WIDTH(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_MSTR_DATA_BUS_WIDTH_SHIFT))&DDRC_MSTR_DATA_BUS_WIDTH_MASK)
10735 #define DDRC_MSTR_DLL_OFF_MODE_MASK              0x8000u
10736 #define DDRC_MSTR_DLL_OFF_MODE_SHIFT             15
10737 #define DDRC_MSTR_BURST_RDWR_MASK                0xF0000u
10738 #define DDRC_MSTR_BURST_RDWR_SHIFT               16
10739 #define DDRC_MSTR_BURST_RDWR(x)                  (((uint32_t)(((uint32_t)(x))<<DDRC_MSTR_BURST_RDWR_SHIFT))&DDRC_MSTR_BURST_RDWR_MASK)
10740 #define DDRC_MSTR_ACTIVE_RANKS_MASK              0xF000000u
10741 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT             24
10742 #define DDRC_MSTR_ACTIVE_RANKS(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_MSTR_ACTIVE_RANKS_SHIFT))&DDRC_MSTR_ACTIVE_RANKS_MASK)
10743 /* STAT Bit Fields */
10744 #define DDRC_STAT_OPERATING_MODE_MASK            0x7u
10745 #define DDRC_STAT_OPERATING_MODE_SHIFT           0
10746 #define DDRC_STAT_OPERATING_MODE(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_OPERATING_MODE_SHIFT))&DDRC_STAT_OPERATING_MODE_MASK)
10747 #define DDRC_STAT_SELFREF_TYPE_MASK              0x30u
10748 #define DDRC_STAT_SELFREF_TYPE_SHIFT             4
10749 #define DDRC_STAT_SELFREF_TYPE(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_SELFREF_TYPE_SHIFT))&DDRC_STAT_SELFREF_TYPE_MASK)
10750 #define DDRC_STAT_SELFREF_STATE_MASK             0x300u
10751 #define DDRC_STAT_SELFREF_STATE_SHIFT            8
10752 #define DDRC_STAT_SELFREF_STATE(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_SELFREF_STATE_SHIFT))&DDRC_STAT_SELFREF_STATE_MASK)
10753 /* MRCTRL0 Bit Fields */
10754 #define DDRC_MRCTRL0_MR_TYPE_MASK                0x1u
10755 #define DDRC_MRCTRL0_MR_TYPE_SHIFT               0
10756 #define DDRC_MRCTRL0_MR_RANK_MASK                0xF0u
10757 #define DDRC_MRCTRL0_MR_RANK_SHIFT               4
10758 #define DDRC_MRCTRL0_MR_RANK(x)                  (((uint32_t)(((uint32_t)(x))<<DDRC_MRCTRL0_MR_RANK_SHIFT))&DDRC_MRCTRL0_MR_RANK_MASK)
10759 #define DDRC_MRCTRL0_MR_ADDR_MASK                0xF000u
10760 #define DDRC_MRCTRL0_MR_ADDR_SHIFT               12
10761 #define DDRC_MRCTRL0_MR_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<DDRC_MRCTRL0_MR_ADDR_SHIFT))&DDRC_MRCTRL0_MR_ADDR_MASK)
10762 #define DDRC_MRCTRL0_MR_WR_MASK                  0x80000000u
10763 #define DDRC_MRCTRL0_MR_WR_SHIFT                 31
10764 /* MRCTRL1 Bit Fields */
10765 #define DDRC_MRCTRL1_MR_DATA_MASK                0x3FFFFu
10766 #define DDRC_MRCTRL1_MR_DATA_SHIFT               0
10767 #define DDRC_MRCTRL1_MR_DATA(x)                  (((uint32_t)(((uint32_t)(x))<<DDRC_MRCTRL1_MR_DATA_SHIFT))&DDRC_MRCTRL1_MR_DATA_MASK)
10768 /* MRSTAT Bit Fields */
10769 #define DDRC_MRSTAT_MR_WR_BUSY_MASK              0x1u
10770 #define DDRC_MRSTAT_MR_WR_BUSY_SHIFT             0
10771 /* DERATEEN Bit Fields */
10772 #define DDRC_DERATEEN_DERATE_ENABLE_MASK         0x1u
10773 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT        0
10774 #define DDRC_DERATEEN_DERATE_VALUE_MASK          0x2u
10775 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT         1
10776 #define DDRC_DERATEEN_DERATE_BYTE_MASK           0xF0u
10777 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT          4
10778 #define DDRC_DERATEEN_DERATE_BYTE(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_DERATEEN_DERATE_BYTE_SHIFT))&DDRC_DERATEEN_DERATE_BYTE_MASK)
10779 /* DERATEINT Bit Fields */
10780 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK    0xFFFFFFFFu
10781 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT   0
10782 #define DDRC_DERATEINT_MR4_READ_INTERVAL(x)      (((uint32_t)(((uint32_t)(x))<<DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT))&DDRC_DERATEINT_MR4_READ_INTERVAL_MASK)
10783 /* PWRCTL Bit Fields */
10784 #define DDRC_PWRCTL_SELFREF_EN_MASK              0x1u
10785 #define DDRC_PWRCTL_SELFREF_EN_SHIFT             0
10786 #define DDRC_PWRCTL_POWERDOWN_EN_MASK            0x2u
10787 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT           1
10788 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK        0x4u
10789 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT       2
10790 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x8u
10791 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3
10792 #define DDRC_PWRCTL_SELFREF_SW_MASK              0x20u
10793 #define DDRC_PWRCTL_SELFREF_SW_SHIFT             5
10794 /* PWRTMG Bit Fields */
10795 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK        0x1Fu
10796 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT       0
10797 #define DDRC_PWRTMG_POWERDOWN_TO_X32(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT))&DDRC_PWRTMG_POWERDOWN_TO_X32_MASK)
10798 #define DDRC_PWRTMG_T_DPD_X4096_MASK             0xFF00u
10799 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT            8
10800 #define DDRC_PWRTMG_T_DPD_X4096(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_PWRTMG_T_DPD_X4096_SHIFT))&DDRC_PWRTMG_T_DPD_X4096_MASK)
10801 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK          0xFF0000u
10802 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT         16
10803 #define DDRC_PWRTMG_SELFREF_TO_X32(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_PWRTMG_SELFREF_TO_X32_SHIFT))&DDRC_PWRTMG_SELFREF_TO_X32_MASK)
10804 /* HWLPCTL Bit Fields */
10805 #define DDRC_HWLPCTL_HW_LP_EN_MASK               0x1u
10806 #define DDRC_HWLPCTL_HW_LP_EN_SHIFT              0
10807 #define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK     0x2u
10808 #define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT    1
10809 #define DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK         0xFFF0000u
10810 #define DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT        16
10811 #define DDRC_HWLPCTL_HW_LP_IDLE_X32(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT))&DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK)
10812 /* RFSHCTL0 Bit Fields */
10813 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK      0x4u
10814 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT     2
10815 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK         0x1F0u
10816 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT        4
10817 #define DDRC_RFSHCTL0_REFRESH_BURST(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL0_REFRESH_BURST_SHIFT))&DDRC_RFSHCTL0_REFRESH_BURST_MASK)
10818 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK        0x1F000u
10819 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT       12
10820 #define DDRC_RFSHCTL0_REFRESH_TO_X32(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT))&DDRC_RFSHCTL0_REFRESH_TO_X32_MASK)
10821 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK        0xF00000u
10822 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT       20
10823 #define DDRC_RFSHCTL0_REFRESH_MARGIN(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT))&DDRC_RFSHCTL0_REFRESH_MARGIN_MASK)
10824 /* RFSHCTL1 Bit Fields */
10825 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0xFFFu
10826 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0
10827 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT))&DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK)
10828 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0xFFF0000u
10829 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16
10830 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT))&DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK)
10831 /* RFSHCTL3 Bit Fields */
10832 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK      0x1u
10833 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT     0
10834 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK  0x2u
10835 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1
10836 /* RFSHTMG Bit Fields */
10837 #define DDRC_RFSHTMG_T_RFC_MIN_MASK              0x3FFu
10838 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT             0
10839 #define DDRC_RFSHTMG_T_RFC_MIN(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHTMG_T_RFC_MIN_SHIFT))&DDRC_RFSHTMG_T_RFC_MIN_MASK)
10840 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK          0xFFF0000u
10841 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT         16
10842 #define DDRC_RFSHTMG_T_RFC_NOM_X32(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT))&DDRC_RFSHTMG_T_RFC_NOM_X32_MASK)
10843 /* INIT0 Bit Fields */
10844 #define DDRC_INIT0_PRE_CKE_X1024_MASK            0x7FFu
10845 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT           0
10846 #define DDRC_INIT0_PRE_CKE_X1024(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_PRE_CKE_X1024_SHIFT))&DDRC_INIT0_PRE_CKE_X1024_MASK)
10847 #define DDRC_INIT0_POST_CKE_X1024_MASK           0x3FF0000u
10848 #define DDRC_INIT0_POST_CKE_X1024_SHIFT          16
10849 #define DDRC_INIT0_POST_CKE_X1024(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_POST_CKE_X1024_SHIFT))&DDRC_INIT0_POST_CKE_X1024_MASK)
10850 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK           0xC0000000u
10851 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT          30
10852 #define DDRC_INIT0_SKIP_DRAM_INIT(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_SKIP_DRAM_INIT_SHIFT))&DDRC_INIT0_SKIP_DRAM_INIT_MASK)
10853 /* INIT1 Bit Fields */
10854 #define DDRC_INIT1_PRE_OCD_X32_MASK              0xFu
10855 #define DDRC_INIT1_PRE_OCD_X32_SHIFT             0
10856 #define DDRC_INIT1_PRE_OCD_X32(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_INIT1_PRE_OCD_X32_SHIFT))&DDRC_INIT1_PRE_OCD_X32_MASK)
10857 #define DDRC_INIT1_FINAL_WAIT_X32_MASK           0x7F00u
10858 #define DDRC_INIT1_FINAL_WAIT_X32_SHIFT          8
10859 #define DDRC_INIT1_FINAL_WAIT_X32(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_INIT1_FINAL_WAIT_X32_SHIFT))&DDRC_INIT1_FINAL_WAIT_X32_MASK)
10860 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK          0xFF0000u
10861 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT         16
10862 #define DDRC_INIT1_DRAM_RSTN_X1024(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_INIT1_DRAM_RSTN_X1024_SHIFT))&DDRC_INIT1_DRAM_RSTN_X1024_MASK)
10863 /* INIT2 Bit Fields */
10864 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK      0xFu
10865 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT     0
10866 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1(x)        (((uint32_t)(((uint32_t)(x))<<DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT))&DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK)
10867 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK     0xFF00u
10868 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT    8
10869 #define DDRC_INIT2_IDLE_AFTER_RESET_X32(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT))&DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK)
10870 /* INIT3 Bit Fields */
10871 #define DDRC_INIT3_EMR_MASK                      0xFFFFu
10872 #define DDRC_INIT3_EMR_SHIFT                     0
10873 #define DDRC_INIT3_EMR(x)                        (((uint32_t)(((uint32_t)(x))<<DDRC_INIT3_EMR_SHIFT))&DDRC_INIT3_EMR_MASK)
10874 #define DDRC_INIT3_MR_MASK                       0xFFFF0000u
10875 #define DDRC_INIT3_MR_SHIFT                      16
10876 #define DDRC_INIT3_MR(x)                         (((uint32_t)(((uint32_t)(x))<<DDRC_INIT3_MR_SHIFT))&DDRC_INIT3_MR_MASK)
10877 /* INIT4 Bit Fields */
10878 #define DDRC_INIT4_EMR3_MASK                     0xFFFFu
10879 #define DDRC_INIT4_EMR3_SHIFT                    0
10880 #define DDRC_INIT4_EMR3(x)                       (((uint32_t)(((uint32_t)(x))<<DDRC_INIT4_EMR3_SHIFT))&DDRC_INIT4_EMR3_MASK)
10881 #define DDRC_INIT4_EMR2_MASK                     0xFFFF0000u
10882 #define DDRC_INIT4_EMR2_SHIFT                    16
10883 #define DDRC_INIT4_EMR2(x)                       (((uint32_t)(((uint32_t)(x))<<DDRC_INIT4_EMR2_SHIFT))&DDRC_INIT4_EMR2_MASK)
10884 /* INIT5 Bit Fields */
10885 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK      0x3FFu
10886 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT     0
10887 #define DDRC_INIT5_MAX_AUTO_INIT_X1024(x)        (((uint32_t)(((uint32_t)(x))<<DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT))&DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK)
10888 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK           0xFF0000u
10889 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT          16
10890 #define DDRC_INIT5_DEV_ZQINIT_X32(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_INIT5_DEV_ZQINIT_X32_SHIFT))&DDRC_INIT5_DEV_ZQINIT_X32_MASK)
10891 /* RANKCTL Bit Fields */
10892 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK       0xF0u
10893 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT      4
10894 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT))&DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK)
10895 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK       0xF00u
10896 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT      8
10897 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT))&DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK)
10898 /* DRAMTMG0 Bit Fields */
10899 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK             0x3Fu
10900 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT            0
10901 #define DDRC_DRAMTMG0_T_RAS_MIN(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_T_RAS_MIN_SHIFT))&DDRC_DRAMTMG0_T_RAS_MIN_MASK)
10902 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK             0x7F00u
10903 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT            8
10904 #define DDRC_DRAMTMG0_T_RAS_MAX(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_T_RAS_MAX_SHIFT))&DDRC_DRAMTMG0_T_RAS_MAX_MASK)
10905 #define DDRC_DRAMTMG0_T_FAW_MASK                 0x3F0000u
10906 #define DDRC_DRAMTMG0_T_FAW_SHIFT                16
10907 #define DDRC_DRAMTMG0_T_FAW(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_T_FAW_SHIFT))&DDRC_DRAMTMG0_T_FAW_MASK)
10908 #define DDRC_DRAMTMG0_WR2PRE_MASK                0x7F000000u
10909 #define DDRC_DRAMTMG0_WR2PRE_SHIFT               24
10910 #define DDRC_DRAMTMG0_WR2PRE(x)                  (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_WR2PRE_SHIFT))&DDRC_DRAMTMG0_WR2PRE_MASK)
10911 /* DRAMTMG1 Bit Fields */
10912 #define DDRC_DRAMTMG1_T_RC_MASK                  0x7Fu
10913 #define DDRC_DRAMTMG1_T_RC_SHIFT                 0
10914 #define DDRC_DRAMTMG1_T_RC(x)                    (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG1_T_RC_SHIFT))&DDRC_DRAMTMG1_T_RC_MASK)
10915 #define DDRC_DRAMTMG1_RD2PRE_MASK                0x1F00u
10916 #define DDRC_DRAMTMG1_RD2PRE_SHIFT               8
10917 #define DDRC_DRAMTMG1_RD2PRE(x)                  (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG1_RD2PRE_SHIFT))&DDRC_DRAMTMG1_RD2PRE_MASK)
10918 #define DDRC_DRAMTMG1_T_XP_MASK                  0x1F0000u
10919 #define DDRC_DRAMTMG1_T_XP_SHIFT                 16
10920 #define DDRC_DRAMTMG1_T_XP(x)                    (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG1_T_XP_SHIFT))&DDRC_DRAMTMG1_T_XP_MASK)
10921 /* DRAMTMG2 Bit Fields */
10922 #define DDRC_DRAMTMG2_WR2RD_MASK                 0x3Fu
10923 #define DDRC_DRAMTMG2_WR2RD_SHIFT                0
10924 #define DDRC_DRAMTMG2_WR2RD(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_WR2RD_SHIFT))&DDRC_DRAMTMG2_WR2RD_MASK)
10925 #define DDRC_DRAMTMG2_RD2WR_MASK                 0x3F00u
10926 #define DDRC_DRAMTMG2_RD2WR_SHIFT                8
10927 #define DDRC_DRAMTMG2_RD2WR(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_RD2WR_SHIFT))&DDRC_DRAMTMG2_RD2WR_MASK)
10928 #define DDRC_DRAMTMG2_READ_LATENCY_MASK          0x3F0000u
10929 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT         16
10930 #define DDRC_DRAMTMG2_READ_LATENCY(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_READ_LATENCY_SHIFT))&DDRC_DRAMTMG2_READ_LATENCY_MASK)
10931 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK         0x3F000000u
10932 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT        24
10933 #define DDRC_DRAMTMG2_WRITE_LATENCY(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT))&DDRC_DRAMTMG2_WRITE_LATENCY_MASK)
10934 /* DRAMTMG3 Bit Fields */
10935 #define DDRC_DRAMTMG3_T_MOD_MASK                 0x3FFu
10936 #define DDRC_DRAMTMG3_T_MOD_SHIFT                0
10937 #define DDRC_DRAMTMG3_T_MOD(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG3_T_MOD_SHIFT))&DDRC_DRAMTMG3_T_MOD_MASK)
10938 #define DDRC_DRAMTMG3_T_MRD_MASK                 0x3F000u
10939 #define DDRC_DRAMTMG3_T_MRD_SHIFT                12
10940 #define DDRC_DRAMTMG3_T_MRD(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG3_T_MRD_SHIFT))&DDRC_DRAMTMG3_T_MRD_MASK)
10941 #define DDRC_DRAMTMG3_T_MRW_MASK                 0x3FF00000u
10942 #define DDRC_DRAMTMG3_T_MRW_SHIFT                20
10943 #define DDRC_DRAMTMG3_T_MRW(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG3_T_MRW_SHIFT))&DDRC_DRAMTMG3_T_MRW_MASK)
10944 /* DRAMTMG4 Bit Fields */
10945 #define DDRC_DRAMTMG4_T_RP_MASK                  0x1Fu
10946 #define DDRC_DRAMTMG4_T_RP_SHIFT                 0
10947 #define DDRC_DRAMTMG4_T_RP(x)                    (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RP_SHIFT))&DDRC_DRAMTMG4_T_RP_MASK)
10948 #define DDRC_DRAMTMG4_T_RRD_MASK                 0xF00u
10949 #define DDRC_DRAMTMG4_T_RRD_SHIFT                8
10950 #define DDRC_DRAMTMG4_T_RRD(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RRD_SHIFT))&DDRC_DRAMTMG4_T_RRD_MASK)
10951 #define DDRC_DRAMTMG4_T_CCD_MASK                 0xF0000u
10952 #define DDRC_DRAMTMG4_T_CCD_SHIFT                16
10953 #define DDRC_DRAMTMG4_T_CCD(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_CCD_SHIFT))&DDRC_DRAMTMG4_T_CCD_MASK)
10954 #define DDRC_DRAMTMG4_T_RCD_MASK                 0x1F000000u
10955 #define DDRC_DRAMTMG4_T_RCD_SHIFT                24
10956 #define DDRC_DRAMTMG4_T_RCD(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RCD_SHIFT))&DDRC_DRAMTMG4_T_RCD_MASK)
10957 /* DRAMTMG5 Bit Fields */
10958 #define DDRC_DRAMTMG5_T_CKE_MASK                 0x1Fu
10959 #define DDRC_DRAMTMG5_T_CKE_SHIFT                0
10960 #define DDRC_DRAMTMG5_T_CKE(x)                   (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKE_SHIFT))&DDRC_DRAMTMG5_T_CKE_MASK)
10961 #define DDRC_DRAMTMG5_T_CKESR_MASK               0x3F00u
10962 #define DDRC_DRAMTMG5_T_CKESR_SHIFT              8
10963 #define DDRC_DRAMTMG5_T_CKESR(x)                 (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKESR_SHIFT))&DDRC_DRAMTMG5_T_CKESR_MASK)
10964 #define DDRC_DRAMTMG5_T_CKSRE_MASK               0xF0000u
10965 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT              16
10966 #define DDRC_DRAMTMG5_T_CKSRE(x)                 (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKSRE_SHIFT))&DDRC_DRAMTMG5_T_CKSRE_MASK)
10967 #define DDRC_DRAMTMG5_T_CKSRX_MASK               0xF000000u
10968 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT              24
10969 #define DDRC_DRAMTMG5_T_CKSRX(x)                 (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKSRX_SHIFT))&DDRC_DRAMTMG5_T_CKSRX_MASK)
10970 /* DRAMTMG6 Bit Fields */
10971 #define DDRC_DRAMTMG6_T_CKCSX_MASK               0xFu
10972 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT              0
10973 #define DDRC_DRAMTMG6_T_CKCSX(x)                 (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG6_T_CKCSX_SHIFT))&DDRC_DRAMTMG6_T_CKCSX_MASK)
10974 #define DDRC_DRAMTMG6_T_CKDPDX_MASK              0xF0000u
10975 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT             16
10976 #define DDRC_DRAMTMG6_T_CKDPDX(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG6_T_CKDPDX_SHIFT))&DDRC_DRAMTMG6_T_CKDPDX_MASK)
10977 #define DDRC_DRAMTMG6_T_CKDPDE_MASK              0xF000000u
10978 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT             24
10979 #define DDRC_DRAMTMG6_T_CKDPDE(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG6_T_CKDPDE_SHIFT))&DDRC_DRAMTMG6_T_CKDPDE_MASK)
10980 /* DRAMTMG7 Bit Fields */
10981 #define DDRC_DRAMTMG7_T_CKPDX_MASK               0xFu
10982 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT              0
10983 #define DDRC_DRAMTMG7_T_CKPDX(x)                 (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG7_T_CKPDX_SHIFT))&DDRC_DRAMTMG7_T_CKPDX_MASK)
10984 #define DDRC_DRAMTMG7_T_CKPDE_MASK               0xF00u
10985 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT              8
10986 #define DDRC_DRAMTMG7_T_CKPDE(x)                 (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG7_T_CKPDE_SHIFT))&DDRC_DRAMTMG7_T_CKPDE_MASK)
10987 /* DRAMTMG8 Bit Fields */
10988 #define DDRC_DRAMTMG8_T_XS_X32_MASK              0x7Fu
10989 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT             0
10990 #define DDRC_DRAMTMG8_T_XS_X32(x)                (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG8_T_XS_X32_SHIFT))&DDRC_DRAMTMG8_T_XS_X32_MASK)
10991 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK          0x7F00u
10992 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT         8
10993 #define DDRC_DRAMTMG8_T_XS_DLL_X32(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT))&DDRC_DRAMTMG8_T_XS_DLL_X32_MASK)
10994 /* ZQCTL0 Bit Fields */
10995 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK          0x3FFu
10996 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT         0
10997 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT))&DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK)
10998 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK           0x3FF0000u
10999 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT          16
11000 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT))&DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK)
11001 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK      0x20000000u
11002 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT     29
11003 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK            0x40000000u
11004 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT           30
11005 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK             0x80000000u
11006 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT            31
11007 /* ZQCTL1 Bit Fields */
11008 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0xFFFFFu
11009 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0
11010 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT))&DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK)
11011 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK          0x3FF00000u
11012 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT         20
11013 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT))&DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK)
11014 /* ZQCTL2 Bit Fields */
11015 #define DDRC_ZQCTL2_ZQ_RESET_MASK                0x1u
11016 #define DDRC_ZQCTL2_ZQ_RESET_SHIFT               0
11017 /* ZQSTAT Bit Fields */
11018 #define DDRC_ZQSTAT_ZQ_RESET_BUSY_MASK           0x1u
11019 #define DDRC_ZQSTAT_ZQ_RESET_BUSY_SHIFT          0
11020 /* DFITMG0 Bit Fields */
11021 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK         0x3Fu
11022 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT        0
11023 #define DDRC_DFITMG0_DFI_TPHY_WRLAT(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT))&DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK)
11024 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK        0x3F00u
11025 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT       8
11026 #define DDRC_DFITMG0_DFI_TPHY_WRDATA(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT))&DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK)
11027 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK     0x8000u
11028 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT    15
11029 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK        0x3F0000u
11030 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT       16
11031 #define DDRC_DFITMG0_DFI_T_RDDATA_EN(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT))&DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK)
11032 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK     0x800000u
11033 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT    23
11034 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK       0x1F000000u
11035 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT      24
11036 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT))&DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK)
11037 /* DFITMG1 Bit Fields */
11038 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK  0xFu
11039 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0
11040 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE(x)    (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT))&DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK)
11041 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0xF00u
11042 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8
11043 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE(x)   (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT))&DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK)
11044 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK     0x1F0000u
11045 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT    16
11046 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT))&DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK)
11047 /* DFILPCFG0 Bit Fields */
11048 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK         0x1u
11049 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT        0
11050 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK     0xF0u
11051 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT    4
11052 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT))&DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK)
11053 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK         0x100u
11054 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT        8
11055 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK     0xF000u
11056 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT    12
11057 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT))&DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK)
11058 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK        0x10000u
11059 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT       16
11060 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK    0xF00000u
11061 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT   20
11062 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD(x)      (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT))&DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK)
11063 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK         0xF000000u
11064 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT        24
11065 #define DDRC_DFILPCFG0_DFI_TLP_RESP(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT))&DDRC_DFILPCFG0_DFI_TLP_RESP_MASK)
11066 /* DFIUPD0 Bit Fields */
11067 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK       0x3FFu
11068 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT      0
11069 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT))&DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK)
11070 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK       0x3FF0000u
11071 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT      16
11072 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT))&DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK)
11073 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK   0x40000000u
11074 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT  30
11075 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK       0x80000000u
11076 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT      31
11077 /* DFIUPD1 Bit Fields */
11078 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0xFFu
11079 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0
11080 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT))&DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK)
11081 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0xFF0000u
11082 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16
11083 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT))&DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK)
11084 /* DFIUPD2 Bit Fields */
11085 #define DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_MASK       0xFFFu
11086 #define DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT      0
11087 #define DDRC_DFIUPD2_DFI_PHYUPD_TYPE0(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT))&DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_MASK)
11088 #define DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_MASK       0xFFF0000u
11089 #define DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT      16
11090 #define DDRC_DFIUPD2_DFI_PHYUPD_TYPE1(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT))&DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_MASK)
11091 #define DDRC_DFIUPD2_DFI_PHYUPD_EN_MASK          0x80000000u
11092 #define DDRC_DFIUPD2_DFI_PHYUPD_EN_SHIFT         31
11093 /* DFIUPD3 Bit Fields */
11094 #define DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_MASK       0xFFFu
11095 #define DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT      0
11096 #define DDRC_DFIUPD3_DFI_PHYUPD_TYPE2(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT))&DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_MASK)
11097 #define DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_MASK       0xFFF0000u
11098 #define DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT      16
11099 #define DDRC_DFIUPD3_DFI_PHYUPD_TYPE3(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT))&DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_MASK)
11100 /* DFIMISC Bit Fields */
11101 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK   0x1u
11102 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT  0
11103 /* ADDRMAP0 Bit Fields */
11104 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK       0x1Fu
11105 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT      0
11106 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT))&DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK)
11107 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_MASK       0x1F00u
11108 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_SHIFT      8
11109 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT1(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_SHIFT))&DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_MASK)
11110 /* ADDRMAP1 Bit Fields */
11111 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK       0x1Fu
11112 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT      0
11113 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT))&DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK)
11114 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK       0x1F00u
11115 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT      8
11116 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT))&DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK)
11117 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK       0x1F0000u
11118 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT      16
11119 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT))&DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK)
11120 /* ADDRMAP2 Bit Fields */
11121 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK        0xFu
11122 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT       0
11123 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK)
11124 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK        0xF00u
11125 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT       8
11126 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK)
11127 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK        0xF0000u
11128 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT       16
11129 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK)
11130 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK        0xF000000u
11131 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT       24
11132 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK)
11133 /* ADDRMAP3 Bit Fields */
11134 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK        0xFu
11135 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT       0
11136 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK)
11137 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK        0xF00u
11138 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT       8
11139 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK)
11140 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK        0xF0000u
11141 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT       16
11142 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK)
11143 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK        0xF000000u
11144 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT       24
11145 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK)
11146 /* ADDRMAP4 Bit Fields */
11147 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK       0xFu
11148 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT      0
11149 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT))&DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK)
11150 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK       0xF00u
11151 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT      8
11152 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT))&DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK)
11153 /* ADDRMAP5 Bit Fields */
11154 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK        0xFu
11155 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT       0
11156 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK)
11157 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK        0xF00u
11158 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT       8
11159 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK)
11160 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK     0xF0000u
11161 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT    16
11162 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK)
11163 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK       0xF000000u
11164 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT      24
11165 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK)
11166 /* ADDRMAP6 Bit Fields */
11167 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK       0xFu
11168 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT      0
11169 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK)
11170 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK       0xF00u
11171 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT      8
11172 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK)
11173 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK       0xF0000u
11174 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT      16
11175 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK)
11176 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK       0xF000000u
11177 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT      24
11178 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15(x)         (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK)
11179 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK       0x80000000u
11180 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT      31
11181 /* ODTCFG Bit Fields */
11182 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK            0x7Cu
11183 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT           2
11184 #define DDRC_ODTCFG_RD_ODT_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_RD_ODT_DELAY_SHIFT))&DDRC_ODTCFG_RD_ODT_DELAY_MASK)
11185 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK             0xF00u
11186 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT            8
11187 #define DDRC_ODTCFG_RD_ODT_HOLD(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_RD_ODT_HOLD_SHIFT))&DDRC_ODTCFG_RD_ODT_HOLD_MASK)
11188 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK            0x1F0000u
11189 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT           16
11190 #define DDRC_ODTCFG_WR_ODT_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_WR_ODT_DELAY_SHIFT))&DDRC_ODTCFG_WR_ODT_DELAY_MASK)
11191 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK             0xF000000u
11192 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT            24
11193 #define DDRC_ODTCFG_WR_ODT_HOLD(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_WR_ODT_HOLD_SHIFT))&DDRC_ODTCFG_WR_ODT_HOLD_MASK)
11194 /* ODTMAP Bit Fields */
11195 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK            0xFu
11196 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT           0
11197 #define DDRC_ODTMAP_RANK0_WR_ODT(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK0_WR_ODT_SHIFT))&DDRC_ODTMAP_RANK0_WR_ODT_MASK)
11198 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK            0xF0u
11199 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT           4
11200 #define DDRC_ODTMAP_RANK0_RD_ODT(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK0_RD_ODT_SHIFT))&DDRC_ODTMAP_RANK0_RD_ODT_MASK)
11201 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK            0xF00u
11202 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT           8
11203 #define DDRC_ODTMAP_RANK1_WR_ODT(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK1_WR_ODT_SHIFT))&DDRC_ODTMAP_RANK1_WR_ODT_MASK)
11204 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK            0xF000u
11205 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT           12
11206 #define DDRC_ODTMAP_RANK1_RD_ODT(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK1_RD_ODT_SHIFT))&DDRC_ODTMAP_RANK1_RD_ODT_MASK)
11207 /* SCHED Bit Fields */
11208 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK          0x1u
11209 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT         0
11210 #define DDRC_SCHED_PREFER_WRITE_MASK             0x2u
11211 #define DDRC_SCHED_PREFER_WRITE_SHIFT            1
11212 #define DDRC_SCHED_PAGECLOSE_MASK                0x4u
11213 #define DDRC_SCHED_PAGECLOSE_SHIFT               2
11214 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK          0x3F00u
11215 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT         8
11216 #define DDRC_SCHED_LPR_NUM_ENTRIES(x)            (((uint32_t)(((uint32_t)(x))<<DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT))&DDRC_SCHED_LPR_NUM_ENTRIES_MASK)
11217 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK            0x7F000000u
11218 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT           24
11219 #define DDRC_SCHED_RDWR_IDLE_GAP(x)              (((uint32_t)(((uint32_t)(x))<<DDRC_SCHED_RDWR_IDLE_GAP_SHIFT))&DDRC_SCHED_RDWR_IDLE_GAP_MASK)
11220 /* SCHED1 Bit Fields */
11221 #define DDRC_SCHED1_PAGECLOSE_TIMER_MASK         0xFFu
11222 #define DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT        0
11223 #define DDRC_SCHED1_PAGECLOSE_TIMER(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT))&DDRC_SCHED1_PAGECLOSE_TIMER_MASK)
11224 /* PERFHPR1 Bit Fields */
11225 #define DDRC_PERFHPR1_HPR_MAX_STARVE_MASK        0xFFFFu
11226 #define DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT       0
11227 #define DDRC_PERFHPR1_HPR_MAX_STARVE(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT))&DDRC_PERFHPR1_HPR_MAX_STARVE_MASK)
11228 #define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK   0xFF000000u
11229 #define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT  24
11230 #define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH(x)     (((uint32_t)(((uint32_t)(x))<<DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT))&DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK)
11231 /* PERFLPR1 Bit Fields */
11232 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK        0xFFFFu
11233 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT       0
11234 #define DDRC_PERFLPR1_LPR_MAX_STARVE(x)          (((uint32_t)(((uint32_t)(x))<<DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT))&DDRC_PERFLPR1_LPR_MAX_STARVE_MASK)
11235 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK   0xFF000000u
11236 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT  24
11237 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH(x)     (((uint32_t)(((uint32_t)(x))<<DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT))&DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK)
11238 /* PERFWR1 Bit Fields */
11239 #define DDRC_PERFWR1_W_MAX_STARVE_MASK           0xFFFFu
11240 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT          0
11241 #define DDRC_PERFWR1_W_MAX_STARVE(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_PERFWR1_W_MAX_STARVE_SHIFT))&DDRC_PERFWR1_W_MAX_STARVE_MASK)
11242 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK      0xFF000000u
11243 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT     24
11244 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH(x)        (((uint32_t)(((uint32_t)(x))<<DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT))&DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK)
11245 /* PERFVPR1 Bit Fields */
11246 #define DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_MASK     0x7FFu
11247 #define DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT    0
11248 #define DDRC_PERFVPR1_VPR_TIMEOUT_RANGE(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT))&DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_MASK)
11249 /* PERFVPW1 Bit Fields */
11250 #define DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_MASK     0x7FFu
11251 #define DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT    0
11252 #define DDRC_PERFVPW1_VPW_TIMEOUT_RANGE(x)       (((uint32_t)(((uint32_t)(x))<<DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT))&DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_MASK)
11253 /* DBG0 Bit Fields */
11254 #define DDRC_DBG0_DIS_WC_MASK                    0x1u
11255 #define DDRC_DBG0_DIS_WC_SHIFT                   0
11256 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK    0x10u
11257 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT   4
11258 /* DBG1 Bit Fields */
11259 #define DDRC_DBG1_DIS_DQ_MASK                    0x1u
11260 #define DDRC_DBG1_DIS_DQ_SHIFT                   0
11261 #define DDRC_DBG1_DIS_HIF_MASK                   0x2u
11262 #define DDRC_DBG1_DIS_HIF_SHIFT                  1
11263 /* DBGCAM Bit Fields */
11264 #define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK         0x7Fu
11265 #define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT        0
11266 #define DDRC_DBGCAM_DBG_HPR_Q_DEPTH(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT))&DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK)
11267 #define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK         0x7F00u
11268 #define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT        8
11269 #define DDRC_DBGCAM_DBG_LPR_Q_DEPTH(x)           (((uint32_t)(((uint32_t)(x))<<DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT))&DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK)
11270 #define DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK           0x7F0000u
11271 #define DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT          16
11272 #define DDRC_DBGCAM_DBG_W_Q_DEPTH(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT))&DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK)
11273 #define DDRC_DBGCAM_DBG_STALL_MASK               0x1000000u
11274 #define DDRC_DBGCAM_DBG_STALL_SHIFT              24
11275 #define DDRC_DBGCAM_DBG_RD_Q_EMPTY_MASK          0x2000000u
11276 #define DDRC_DBGCAM_DBG_RD_Q_EMPTY_SHIFT         25
11277 #define DDRC_DBGCAM_DBG_WR_Q_EMPTY_MASK          0x4000000u
11278 #define DDRC_DBGCAM_DBG_WR_Q_EMPTY_SHIFT         26
11279 #define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK  0x10000000u
11280 #define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT 28
11281 #define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK  0x20000000u
11282 #define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT 29
11283 #define DDRC_DBGCAM_DBG_STALL_WR_MASK            0x40000000u
11284 #define DDRC_DBGCAM_DBG_STALL_WR_SHIFT           30
11285 #define DDRC_DBGCAM_DBG_STALL_RD_MASK            0x80000000u
11286 #define DDRC_DBGCAM_DBG_STALL_RD_SHIFT           31
11287 /* DBGCMD Bit Fields */
11288 #define DDRC_DBGCMD_RANK0_REFRESH_MASK           0x1u
11289 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT          0
11290 #define DDRC_DBGCMD_RANK1_REFRESH_MASK           0x2u
11291 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT          1
11292 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK          0x10u
11293 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT         4
11294 #define DDRC_DBGCMD_CTRLUPD_MASK                 0x20u
11295 #define DDRC_DBGCMD_CTRLUPD_SHIFT                5
11296 /* DBGSTAT Bit Fields */
11297 #define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_MASK     0x1u
11298 #define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT    0
11299 #define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_MASK     0x2u
11300 #define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT    1
11301 #define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK    0x10u
11302 #define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT   4
11303 #define DDRC_DBGSTAT_CTRLUPD_BUSY_MASK           0x20u
11304 #define DDRC_DBGSTAT_CTRLUPD_BUSY_SHIFT          5
11305 /* SWCTL Bit Fields */
11306 #define DDRC_SWCTL_SW_DONE_MASK                  0x1u
11307 #define DDRC_SWCTL_SW_DONE_SHIFT                 0
11308 /* SWSTAT Bit Fields */
11309 #define DDRC_SWSTAT_SW_DONE_ACK_MASK             0x1u
11310 #define DDRC_SWSTAT_SW_DONE_ACK_SHIFT            0
11311 
11312 /*!
11313  * @}
11314  */ /* end of group DDRC_Register_Masks */
11315 
11316 /* DDRC - Peripheral instance base addresses */
11317 /** Peripheral DDRC base address */
11318 #define DDRC_BASE                                (0x307A0000u)
11319 /** Peripheral DDRC base pointer */
11320 #define DDRC                                     ((DDRC_Type *)DDRC_BASE)
11321 #define DDRC_BASE_PTR                            (DDRC)
11322 /** Array initializer of DDRC peripheral base addresses */
11323 #define DDRC_BASE_ADDRS                          { DDRC_BASE }
11324 /** Array initializer of DDRC peripheral base pointers */
11325 #define DDRC_BASE_PTRS                           { DDRC }
11326 /* ----------------------------------------------------------------------------
11327    -- DDRC - Register accessor macros
11328    ---------------------------------------------------------------------------- */
11329 
11330 /*!
11331  * @addtogroup DDRC_Register_Accessor_Macros DDRC - Register accessor macros
11332  * @{
11333  */
11334 
11335 
11336 /* DDRC - Register instance definitions */
11337 /* DDRC */
11338 #define DDRC_MSTR                                DDRC_MSTR_REG(DDRC_BASE_PTR)
11339 #define DDRC_STAT                                DDRC_STAT_REG(DDRC_BASE_PTR)
11340 #define DDRC_MRCTRL0                             DDRC_MRCTRL0_REG(DDRC_BASE_PTR)
11341 #define DDRC_MRCTRL1                             DDRC_MRCTRL1_REG(DDRC_BASE_PTR)
11342 #define DDRC_MRSTAT                              DDRC_MRSTAT_REG(DDRC_BASE_PTR)
11343 #define DDRC_DERATEEN                            DDRC_DERATEEN_REG(DDRC_BASE_PTR)
11344 #define DDRC_DERATEINT                           DDRC_DERATEINT_REG(DDRC_BASE_PTR)
11345 #define DDRC_PWRCTL                              DDRC_PWRCTL_REG(DDRC_BASE_PTR)
11346 #define DDRC_PWRTMG                              DDRC_PWRTMG_REG(DDRC_BASE_PTR)
11347 #define DDRC_HWLPCTL                             DDRC_HWLPCTL_REG(DDRC_BASE_PTR)
11348 #define DDRC_RFSHCTL0                            DDRC_RFSHCTL0_REG(DDRC_BASE_PTR)
11349 #define DDRC_RFSHCTL1                            DDRC_RFSHCTL1_REG(DDRC_BASE_PTR)
11350 #define DDRC_RFSHCTL3                            DDRC_RFSHCTL3_REG(DDRC_BASE_PTR)
11351 #define DDRC_RFSHTMG                             DDRC_RFSHTMG_REG(DDRC_BASE_PTR)
11352 #define DDRC_INIT0                               DDRC_INIT0_REG(DDRC_BASE_PTR)
11353 #define DDRC_INIT1                               DDRC_INIT1_REG(DDRC_BASE_PTR)
11354 #define DDRC_INIT2                               DDRC_INIT2_REG(DDRC_BASE_PTR)
11355 #define DDRC_INIT3                               DDRC_INIT3_REG(DDRC_BASE_PTR)
11356 #define DDRC_INIT4                               DDRC_INIT4_REG(DDRC_BASE_PTR)
11357 #define DDRC_INIT5                               DDRC_INIT5_REG(DDRC_BASE_PTR)
11358 #define DDRC_RANKCTL                             DDRC_RANKCTL_REG(DDRC_BASE_PTR)
11359 #define DDRC_DRAMTMG0                            DDRC_DRAMTMG0_REG(DDRC_BASE_PTR)
11360 #define DDRC_DRAMTMG1                            DDRC_DRAMTMG1_REG(DDRC_BASE_PTR)
11361 #define DDRC_DRAMTMG2                            DDRC_DRAMTMG2_REG(DDRC_BASE_PTR)
11362 #define DDRC_DRAMTMG3                            DDRC_DRAMTMG3_REG(DDRC_BASE_PTR)
11363 #define DDRC_DRAMTMG4                            DDRC_DRAMTMG4_REG(DDRC_BASE_PTR)
11364 #define DDRC_DRAMTMG5                            DDRC_DRAMTMG5_REG(DDRC_BASE_PTR)
11365 #define DDRC_DRAMTMG6                            DDRC_DRAMTMG6_REG(DDRC_BASE_PTR)
11366 #define DDRC_DRAMTMG7                            DDRC_DRAMTMG7_REG(DDRC_BASE_PTR)
11367 #define DDRC_DRAMTMG8                            DDRC_DRAMTMG8_REG(DDRC_BASE_PTR)
11368 #define DDRC_ZQCTL0                              DDRC_ZQCTL0_REG(DDRC_BASE_PTR)
11369 #define DDRC_ZQCTL1                              DDRC_ZQCTL1_REG(DDRC_BASE_PTR)
11370 #define DDRC_ZQCTL2                              DDRC_ZQCTL2_REG(DDRC_BASE_PTR)
11371 #define DDRC_ZQSTAT                              DDRC_ZQSTAT_REG(DDRC_BASE_PTR)
11372 #define DDRC_DFITMG0                             DDRC_DFITMG0_REG(DDRC_BASE_PTR)
11373 #define DDRC_DFITMG1                             DDRC_DFITMG1_REG(DDRC_BASE_PTR)
11374 #define DDRC_DFILPCFG0                           DDRC_DFILPCFG0_REG(DDRC_BASE_PTR)
11375 #define DDRC_DFIUPD0                             DDRC_DFIUPD0_REG(DDRC_BASE_PTR)
11376 #define DDRC_DFIUPD1                             DDRC_DFIUPD1_REG(DDRC_BASE_PTR)
11377 #define DDRC_DFIUPD2                             DDRC_DFIUPD2_REG(DDRC_BASE_PTR)
11378 #define DDRC_DFIUPD3                             DDRC_DFIUPD3_REG(DDRC_BASE_PTR)
11379 #define DDRC_DFIMISC                             DDRC_DFIMISC_REG(DDRC_BASE_PTR)
11380 #define DDRC_ADDRMAP0                            DDRC_ADDRMAP0_REG(DDRC_BASE_PTR)
11381 #define DDRC_ADDRMAP1                            DDRC_ADDRMAP1_REG(DDRC_BASE_PTR)
11382 #define DDRC_ADDRMAP2                            DDRC_ADDRMAP2_REG(DDRC_BASE_PTR)
11383 #define DDRC_ADDRMAP3                            DDRC_ADDRMAP3_REG(DDRC_BASE_PTR)
11384 #define DDRC_ADDRMAP4                            DDRC_ADDRMAP4_REG(DDRC_BASE_PTR)
11385 #define DDRC_ADDRMAP5                            DDRC_ADDRMAP5_REG(DDRC_BASE_PTR)
11386 #define DDRC_ADDRMAP6                            DDRC_ADDRMAP6_REG(DDRC_BASE_PTR)
11387 #define DDRC_ODTCFG                              DDRC_ODTCFG_REG(DDRC_BASE_PTR)
11388 #define DDRC_ODTMAP                              DDRC_ODTMAP_REG(DDRC_BASE_PTR)
11389 #define DDRC_SCHED                               DDRC_SCHED_REG(DDRC_BASE_PTR)
11390 #define DDRC_SCHED1                              DDRC_SCHED1_REG(DDRC_BASE_PTR)
11391 #define DDRC_PERFHPR1                            DDRC_PERFHPR1_REG(DDRC_BASE_PTR)
11392 #define DDRC_PERFLPR1                            DDRC_PERFLPR1_REG(DDRC_BASE_PTR)
11393 #define DDRC_PERFWR1                             DDRC_PERFWR1_REG(DDRC_BASE_PTR)
11394 #define DDRC_PERFVPR1                            DDRC_PERFVPR1_REG(DDRC_BASE_PTR)
11395 #define DDRC_PERFVPW1                            DDRC_PERFVPW1_REG(DDRC_BASE_PTR)
11396 #define DDRC_DBG0                                DDRC_DBG0_REG(DDRC_BASE_PTR)
11397 #define DDRC_DBG1                                DDRC_DBG1_REG(DDRC_BASE_PTR)
11398 #define DDRC_DBGCAM                              DDRC_DBGCAM_REG(DDRC_BASE_PTR)
11399 #define DDRC_DBGCMD                              DDRC_DBGCMD_REG(DDRC_BASE_PTR)
11400 #define DDRC_DBGSTAT                             DDRC_DBGSTAT_REG(DDRC_BASE_PTR)
11401 #define DDRC_SWCTL                               DDRC_SWCTL_REG(DDRC_BASE_PTR)
11402 #define DDRC_SWSTAT                              DDRC_SWSTAT_REG(DDRC_BASE_PTR)
11403 /*!
11404  * @}
11405  */ /* end of group DDRC_Register_Accessor_Macros */
11406 
11407 
11408 /*!
11409  * @}
11410  */ /* end of group DDRC_Peripheral */
11411 
11412 /* ----------------------------------------------------------------------------
11413    -- DDRC_MP Peripheral Access Layer
11414    ---------------------------------------------------------------------------- */
11415 
11416 /*!
11417  * @addtogroup DDRC_MP_Peripheral_Access_Layer DDRC_MP Peripheral Access Layer
11418  * @{
11419  */
11420 
11421 /** DDRC_MP - Register Layout Typedef */
11422 typedef struct {
11423   uint8_t RESERVED_0[1020];
11424   __IO  uint32_t PSTAT;                                  /**< Port Status Register, offset: 0x3FC */
11425   __IO  uint32_t PCCFG;                                  /**< Port Common Configuration Register, offset: 0x400 */
11426   __IO  uint32_t PCFGR_0;                                /**< Port n Configuration Read Register, offset: 0x404 */
11427   __IO  uint32_t PCFGW_0;                                /**< Port n Configuration Write Register, offset: 0x408 */
11428   uint8_t RESERVED_1[4];
11429   struct {                                         /* offset: 0x410, array step: 0x8 */
11430   __IO    uint32_t PCFGIDMASKCH_0;                         /**< Port n Channel m Configuration ID Mask Register, array offset: 0x410, array step: 0x8 */
11431   __IO    uint32_t PCFGIDVALUECH_0;                        /**< Port n Channel m Configuration ID Value Register, array offset: 0x414, array step: 0x8 */
11432  } PCFGID[16];
11433   __IO  uint32_t PCTRL_0;                                /**< Port n Control Register, offset: 0x490 */
11434   __IO  uint32_t PCFGQOS0_0;                             /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
11435   __IO  uint32_t PCFGQOS1_0;                             /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
11436   __IO  uint32_t PCFGWQOS0_0;                            /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
11437   __IO  uint32_t PCFGWQOS1_0;                            /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
11438   uint8_t RESERVED_2[2656];
11439   struct {                                         /* offset: 0xF04, array step: 0x8 */
11440   __IO    uint32_t SARBASE;                                /**< SAR Base Address Register n, array offset: 0xF04, array step: 0x8 */
11441   __IO    uint32_t SARSIZE;                                /**< SAR Size Register n, array offset: 0xF08, array step: 0x8 */
11442  } SAR[4];
11443 } DDRC_MP_Type, *DDRC_MP_MemMapPtr;
11444 /* ----------------------------------------------------------------------------
11445    -- DDRC_MP - Register accessor macros
11446    ---------------------------------------------------------------------------- */
11447 
11448 /*!
11449  * @addtogroup DDRC_MP_Register_Accessor_Macros DDRC_MP - Register accessor macros
11450  * @{
11451  */
11452 
11453 
11454 /* DDRC_MP - Register accessors */
11455 #define DDRC_MP_PSTAT_REG(base)                  ((base)->PSTAT)
11456 #define DDRC_MP_PCCFG_REG(base)                  ((base)->PCCFG)
11457 #define DDRC_MP_PCFGR_0_REG(base)                ((base)->PCFGR_0)
11458 #define DDRC_MP_PCFGW_0_REG(base)                ((base)->PCFGW_0)
11459 #define DDRC_MP_PCFGIDMASKCH_0_REG(base,index)   ((base)->PCFGID[index].PCFGIDMASKCH_0)
11460 #define DDRC_MP_PCFGIDVALUECH_0_REG(base,index)  ((base)->PCFGID[index].PCFGIDVALUECH_0)
11461 #define DDRC_MP_PCTRL_0_REG(base)                ((base)->PCTRL_0)
11462 #define DDRC_MP_PCFGQOS0_0_REG(base)             ((base)->PCFGQOS0_0)
11463 #define DDRC_MP_PCFGQOS1_0_REG(base)             ((base)->PCFGQOS1_0)
11464 #define DDRC_MP_PCFGWQOS0_0_REG(base)            ((base)->PCFGWQOS0_0)
11465 #define DDRC_MP_PCFGWQOS1_0_REG(base)            ((base)->PCFGWQOS1_0)
11466 #define DDRC_MP_SARBASE_REG(base,index)          ((base)->SAR[index].SARBASE)
11467 #define DDRC_MP_SARSIZE_REG(base,index)          ((base)->SAR[index].SARSIZE)
11468 
11469 /*!
11470  * @}
11471  */ /* end of group DDRC_MP_Register_Accessor_Macros */
11472 /* ----------------------------------------------------------------------------
11473    -- DDRC_MP Register Masks
11474    ---------------------------------------------------------------------------- */
11475 
11476 /*!
11477  * @addtogroup DDRC_MP_Register_Masks DDRC_MP Register Masks
11478  * @{
11479  */
11480 
11481 /* PSTAT Bit Fields */
11482 #define DDRC_MP_PSTAT_RD_PORT_BUSY_0_MASK        0x1u
11483 #define DDRC_MP_PSTAT_RD_PORT_BUSY_0_SHIFT       0
11484 /* PCCFG Bit Fields */
11485 #define DDRC_MP_PCCFG_GO2CRITICAL_EN_MASK        0x1u
11486 #define DDRC_MP_PCCFG_GO2CRITICAL_EN_SHIFT       0
11487 #define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_MASK       0x10u
11488 #define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_SHIFT      4
11489 /* PCFGR_0 Bit Fields */
11490 #define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK    0x3FFu
11491 #define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT   0
11492 #define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY(x)      (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT))&DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK)
11493 #define DDRC_MP_PCFGR_0_READ_REORDER_BYPASS_EN_MASK 0x800u
11494 #define DDRC_MP_PCFGR_0_READ_REORDER_BYPASS_EN_SHIFT 11
11495 #define DDRC_MP_PCFGR_0_RD_PORT_AGING_EN_MASK    0x1000u
11496 #define DDRC_MP_PCFGR_0_RD_PORT_AGING_EN_SHIFT   12
11497 #define DDRC_MP_PCFGR_0_RD_PORT_URGENT_EN_MASK   0x2000u
11498 #define DDRC_MP_PCFGR_0_RD_PORT_URGENT_EN_SHIFT  13
11499 #define DDRC_MP_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x4000u
11500 #define DDRC_MP_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14
11501 #define DDRC_MP_PCFGR_0_RDWR_ORDERED_EN_MASK     0x10000u
11502 #define DDRC_MP_PCFGR_0_RDWR_ORDERED_EN_SHIFT    16
11503 /* PCFGW_0 Bit Fields */
11504 #define DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_MASK    0x3FFu
11505 #define DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_SHIFT   0
11506 #define DDRC_MP_PCFGW_0_WR_PORT_PRIORITY(x)      (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_SHIFT))&DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_MASK)
11507 #define DDRC_MP_PCFGW_0_WR_PORT_AGING_EN_MASK    0x1000u
11508 #define DDRC_MP_PCFGW_0_WR_PORT_AGING_EN_SHIFT   12
11509 #define DDRC_MP_PCFGW_0_WR_PORT_URGENT_EN_MASK   0x2000u
11510 #define DDRC_MP_PCFGW_0_WR_PORT_URGENT_EN_SHIFT  13
11511 #define DDRC_MP_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x4000u
11512 #define DDRC_MP_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14
11513 /* PCFGIDMASKCH_0 Bit Fields */
11514 #define DDRC_MP_PCFGIDMASKCH_0_ID_MASK_MASK      0xFFFFFFFFu
11515 #define DDRC_MP_PCFGIDMASKCH_0_ID_MASK_SHIFT     0
11516 #define DDRC_MP_PCFGIDMASKCH_0_ID_MASK(x)        (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGIDMASKCH_0_ID_MASK_SHIFT))&DDRC_MP_PCFGIDMASKCH_0_ID_MASK_MASK)
11517 /* PCFGIDVALUECH_0 Bit Fields */
11518 #define DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_MASK    0xFFFFFFFFu
11519 #define DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_SHIFT   0
11520 #define DDRC_MP_PCFGIDVALUECH_0_ID_VALUE(x)      (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_SHIFT))&DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_MASK)
11521 /* PCTRL_0 Bit Fields */
11522 #define DDRC_MP_PCTRL_0_PORT_EN_MASK             0x1u
11523 #define DDRC_MP_PCTRL_0_PORT_EN_SHIFT            0
11524 /* PCFGQOS0_0 Bit Fields */
11525 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK  0xFu
11526 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0
11527 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1(x)    (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK)
11528 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_MASK  0xF00u
11529 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_SHIFT 8
11530 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2(x)    (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_MASK)
11531 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x30000u
11532 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16
11533 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0(x)   (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_MASK)
11534 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x300000u
11535 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20
11536 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1(x)   (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_MASK)
11537 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_MASK 0x3000000u
11538 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_SHIFT 24
11539 #define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2(x)   (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_MASK)
11540 /* PCFGQOS1_0 Bit Fields */
11541 #define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x7FFu
11542 #define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0
11543 #define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB(x)  (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT))&DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK)
11544 #define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x7FF0000u
11545 #define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16
11546 #define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR(x)  (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT))&DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK)
11547 /* PCFGWQOS0_0 Bit Fields */
11548 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK  0xFu
11549 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT 0
11550 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL(x)    (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT))&DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK)
11551 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK 0x30000u
11552 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT 16
11553 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0(x)  (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT))&DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK)
11554 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK 0x300000u
11555 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT 20
11556 #define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1(x)  (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT))&DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK)
11557 /* PCFGWQOS1_0 Bit Fields */
11558 #define DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK 0x7FFu
11559 #define DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT 0
11560 #define DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT))&DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK)
11561 /* SARBASE Bit Fields */
11562 #define DDRC_MP_SARBASE_BASE_ADDR_MASK           0xFFFFFFFFu
11563 #define DDRC_MP_SARBASE_BASE_ADDR_SHIFT          0
11564 #define DDRC_MP_SARBASE_BASE_ADDR(x)             (((uint32_t)(((uint32_t)(x))<<DDRC_MP_SARBASE_BASE_ADDR_SHIFT))&DDRC_MP_SARBASE_BASE_ADDR_MASK)
11565 /* SARSIZE Bit Fields */
11566 #define DDRC_MP_SARSIZE_NBLOCKS_MASK             0xFFu
11567 #define DDRC_MP_SARSIZE_NBLOCKS_SHIFT            0
11568 #define DDRC_MP_SARSIZE_NBLOCKS(x)               (((uint32_t)(((uint32_t)(x))<<DDRC_MP_SARSIZE_NBLOCKS_SHIFT))&DDRC_MP_SARSIZE_NBLOCKS_MASK)
11569 
11570 /*!
11571  * @}
11572  */ /* end of group DDRC_MP_Register_Masks */
11573 
11574 /* DDRC_MP - Peripheral instance base addresses */
11575 /** Peripheral DDRC_MP base address */
11576 #define DDRC_MP_BASE                             (0x307A0000u)
11577 /** Peripheral DDRC_MP base pointer */
11578 #define DDRC_MP                                  ((DDRC_MP_Type *)DDRC_MP_BASE)
11579 #define DDRC_MP_BASE_PTR                         (DDRC_MP)
11580 /** Array initializer of DDRC_MP peripheral base addresses */
11581 #define DDRC_MP_BASE_ADDRS                       { DDRC_MP_BASE }
11582 /** Array initializer of DDRC_MP peripheral base pointers */
11583 #define DDRC_MP_BASE_PTRS                        { DDRC_MP }
11584 /* ----------------------------------------------------------------------------
11585    -- DDRC_MP - Register accessor macros
11586    ---------------------------------------------------------------------------- */
11587 
11588 /*!
11589  * @addtogroup DDRC_MP_Register_Accessor_Macros DDRC_MP - Register accessor macros
11590  * @{
11591  */
11592 
11593 
11594 /* DDRC_MP - Register instance definitions */
11595 /* DDRC_MP */
11596 #define DDRC_MP_PSTAT                            DDRC_MP_PSTAT_REG(DDRC_MP_BASE_PTR)
11597 #define DDRC_MP_PCCFG                            DDRC_MP_PCCFG_REG(DDRC_MP_BASE_PTR)
11598 #define DDRC_MP_PCFGR_0                          DDRC_MP_PCFGR_0_REG(DDRC_MP_BASE_PTR)
11599 #define DDRC_MP_PCFGW_0                          DDRC_MP_PCFGW_0_REG(DDRC_MP_BASE_PTR)
11600 #define DDRC_MP_PCFGIDMASKCH_00                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,0)
11601 #define DDRC_MP_PCFGIDVALUECH_00                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,0)
11602 #define DDRC_MP_PCFGIDMASKCH_10                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,1)
11603 #define DDRC_MP_PCFGIDVALUECH_10                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,1)
11604 #define DDRC_MP_PCFGIDMASKCH_20                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,2)
11605 #define DDRC_MP_PCFGIDVALUECH_20                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,2)
11606 #define DDRC_MP_PCFGIDMASKCH_30                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,3)
11607 #define DDRC_MP_PCFGIDVALUECH_30                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,3)
11608 #define DDRC_MP_PCFGIDMASKCH_40                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,4)
11609 #define DDRC_MP_PCFGIDVALUECH_40                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,4)
11610 #define DDRC_MP_PCFGIDMASKCH_50                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,5)
11611 #define DDRC_MP_PCFGIDVALUECH_50                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,5)
11612 #define DDRC_MP_PCFGIDMASKCH_60                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,6)
11613 #define DDRC_MP_PCFGIDVALUECH_60                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,6)
11614 #define DDRC_MP_PCFGIDMASKCH_70                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,7)
11615 #define DDRC_MP_PCFGIDVALUECH_70                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,7)
11616 #define DDRC_MP_PCFGIDMASKCH_80                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,8)
11617 #define DDRC_MP_PCFGIDVALUECH_80                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,8)
11618 #define DDRC_MP_PCFGIDMASKCH_90                  DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,9)
11619 #define DDRC_MP_PCFGIDVALUECH_90                 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,9)
11620 #define DDRC_MP_PCFGIDMASKCH_100                 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,10)
11621 #define DDRC_MP_PCFGIDVALUECH_100                DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,10)
11622 #define DDRC_MP_PCFGIDMASKCH_110                 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,11)
11623 #define DDRC_MP_PCFGIDVALUECH_110                DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,11)
11624 #define DDRC_MP_PCFGIDMASKCH_120                 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,12)
11625 #define DDRC_MP_PCFGIDVALUECH_120                DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,12)
11626 #define DDRC_MP_PCFGIDMASKCH_130                 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,13)
11627 #define DDRC_MP_PCFGIDVALUECH_130                DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,13)
11628 #define DDRC_MP_PCFGIDMASKCH_140                 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,14)
11629 #define DDRC_MP_PCFGIDVALUECH_140                DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,14)
11630 #define DDRC_MP_PCFGIDMASKCH_150                 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,15)
11631 #define DDRC_MP_PCFGIDVALUECH_150                DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,15)
11632 #define DDRC_MP_PCTRL_0                          DDRC_MP_PCTRL_0_REG(DDRC_MP_BASE_PTR)
11633 #define DDRC_MP_PCFGQOS0_0                       DDRC_MP_PCFGQOS0_0_REG(DDRC_MP_BASE_PTR)
11634 #define DDRC_MP_PCFGQOS1_0                       DDRC_MP_PCFGQOS1_0_REG(DDRC_MP_BASE_PTR)
11635 #define DDRC_MP_PCFGWQOS0_0                      DDRC_MP_PCFGWQOS0_0_REG(DDRC_MP_BASE_PTR)
11636 #define DDRC_MP_PCFGWQOS1_0                      DDRC_MP_PCFGWQOS1_0_REG(DDRC_MP_BASE_PTR)
11637 #define DDRC_MP_SARBASE0                         DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,0)
11638 #define DDRC_MP_SARSIZE0                         DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,0)
11639 #define DDRC_MP_SARBASE1                         DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,1)
11640 #define DDRC_MP_SARSIZE1                         DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,1)
11641 #define DDRC_MP_SARBASE2                         DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,2)
11642 #define DDRC_MP_SARSIZE2                         DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,2)
11643 #define DDRC_MP_SARBASE3                         DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,3)
11644 #define DDRC_MP_SARSIZE3                         DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,3)
11645 /* DDRC_MP - Register array accessors */
11646 #define DDRC_MP_PCFGIDMASKCH_0(index)            DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,index)
11647 #define DDRC_MP_PCFGIDVALUECH_0(index)           DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,index)
11648 #define DDRC_MP_SARBASE(index)                   DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,index)
11649 #define DDRC_MP_SARSIZE(index)                   DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,index)
11650 /*!
11651  * @}
11652  */ /* end of group DDRC_MP_Register_Accessor_Macros */
11653 
11654 
11655 /*!
11656  * @}
11657  */ /* end of group DDRC_MP_Peripheral */
11658 
11659 /* ----------------------------------------------------------------------------
11660    -- DDR_PHY Peripheral Access Layer
11661    ---------------------------------------------------------------------------- */
11662 
11663 /*!
11664  * @addtogroup DDR_PHY_Peripheral_Access_Layer DDR_PHY Peripheral Access Layer
11665  * @{
11666  */
11667 
11668 /** DDR_PHY - Register Layout Typedef */
11669 typedef struct {
11670   __IO  uint32_t PHY_CON0;                               /**< , offset: 0x0 */
11671   __IO  uint32_t PHY_CON1;                               /**< , offset: 0x4 */
11672   __IO  uint32_t PHY_CON2;                               /**< , offset: 0x8 */
11673   __IO  uint32_t PHY_CON3;                               /**< , offset: 0xC */
11674   __IO  uint32_t PHY_CON4;                               /**< , offset: 0x10 */
11675   __IO  uint32_t PHY_CON5;                               /**< , offset: 0x14 */
11676   union {                                          /* offset: 0x18 */
11677   __IO    uint32_t LP_CON0;                                     /**< ,offset: 0x18 */
11678   __IO    uint32_t RODT_CON0;                                   /**< ,offset: 0x18 */
11679   };
11680   uint8_t RESERVED_0[4];
11681   __IO  uint32_t OFFSET_RD_CON0;                         /**< , offset: 0x20 */
11682   uint8_t RESERVED_1[12];
11683   __IO  uint32_t OFFSET_WR_CON0;                         /**< , offset: 0x30 */
11684   uint8_t RESERVED_2[12];
11685   __IO  uint32_t GATE_CODE_CON0;                         /**< , offset: 0x40 */
11686   uint8_t RESERVED_3[8];
11687   __IO  uint32_t SHIFTC_CON0;                            /**< , offset: 0x4C */
11688   __IO  uint32_t CMD_SDLL_CON0;                          /**< , offset: 0x50 */
11689   uint8_t RESERVED_4[24];
11690   __IO  uint32_t LVL_CON0;                               /**< , offset: 0x6C */
11691   uint8_t RESERVED_5[8];
11692   __IO  uint32_t LVL_CON3;                               /**< , offset: 0x78 */
11693   __IO  uint32_t CMD_DESKEW_CON0;                        /**< , offset: 0x7C */
11694   __IO  uint32_t CMD_DESKEW_CON1;                        /**< , offset: 0x80 */
11695   __IO  uint32_t CMD_DESKEW_CON2;                        /**< , offset: 0x84 */
11696   __IO  uint32_t CMD_DESKEW_CON3;                        /**< , offset: 0x88 */
11697   uint8_t RESERVED_6[8];
11698   __IO  uint32_t CMD_DESKEW_CON4;                        /**< , offset: 0x94 */
11699   uint8_t RESERVED_7[4];
11700   __IO  uint32_t DRVDS_CON0;                             /**< , offset: 0x9C */
11701   uint8_t RESERVED_8[16];
11702   __IO  uint32_t MDLL_CON0;                              /**< , offset: 0xB0 */
11703   __IO  uint32_t MDLL_CON1;                              /**< , offset: 0xB4 */
11704   uint8_t RESERVED_9[8];
11705   __IO  uint32_t ZQ_CON0;                                /**< , offset: 0xC0 */
11706   __IO  uint32_t ZQ_CON1;                                /**< , offset: 0xC4 */
11707   __IO  uint32_t ZQ_CON2;                                /**< , offset: 0xC8 */
11708   uint8_t RESERVED_10[196];
11709   __IO  uint32_t RD_DESKEW_CON0;                         /**< , offset: 0x190 */
11710   uint8_t RESERVED_11[8];
11711   __IO  uint32_t RD_DESKEW_CON3;                         /**< , offset: 0x19C */
11712   uint8_t RESERVED_12[8];
11713   __IO  uint32_t RD_DESKEW_CON6;                         /**< , offset: 0x1A8 */
11714   uint8_t RESERVED_13[8];
11715   __IO  uint32_t RD_DESKEW_CON9;                         /**< , offset: 0x1B4 */
11716   uint8_t RESERVED_14[8];
11717   __IO  uint32_t RD_DESKEW_CON12;                        /**< , offset: 0x1C0 */
11718   uint8_t RESERVED_15[8];
11719   __IO  uint32_t RD_DESKEW_CON15;                        /**< , offset: 0x1CC */
11720   uint8_t RESERVED_16[8];
11721   __IO  uint32_t RD_DESKEW_CON18;                        /**< , offset: 0x1D8 */
11722   uint8_t RESERVED_17[8];
11723   __IO  uint32_t RD_DESKEW_CON21;                        /**< , offset: 0x1E4 */
11724   uint8_t RESERVED_18[8];
11725   __IO  uint32_t WR_DESKEW_CON0;                         /**< , offset: 0x1F0 */
11726   uint8_t RESERVED_19[8];
11727   __IO  uint32_t WR_DESKEW_CON3;                         /**< , offset: 0x1FC */
11728   uint8_t RESERVED_20[8];
11729   __IO  uint32_t WR_DESKEW_CON6;                         /**< , offset: 0x208 */
11730   uint8_t RESERVED_21[8];
11731   __IO  uint32_t WR_DESKEW_CON9;                         /**< , offset: 0x214 */
11732   uint8_t RESERVED_22[8];
11733   __IO  uint32_t WR_DESKEW_CON12;                        /**< , offset: 0x220 */
11734   uint8_t RESERVED_23[8];
11735   __IO  uint32_t WR_DESKEW_CON15;                        /**< , offset: 0x22C */
11736   uint8_t RESERVED_24[8];
11737   __IO  uint32_t WR_DESKEW_CON18;                        /**< , offset: 0x238 */
11738   uint8_t RESERVED_25[8];
11739   __IO  uint32_t WR_DESKEW_CON21;                        /**< , offset: 0x244 */
11740   uint8_t RESERVED_26[8];
11741   __IO  uint32_t DM_DESKEW_CON;                          /**< , offset: 0x250 */
11742   uint8_t RESERVED_27[332];
11743   __IO  uint32_t RDATA0;                                 /**< , offset: 0x3A0 */
11744   uint8_t RESERVED_28[8];
11745   __IO  uint32_t STAT0;                                  /**< , offset: 0x3AC */
11746 } DDR_PHY_Type, *DDR_PHY_MemMapPtr;
11747 /* ----------------------------------------------------------------------------
11748    -- DDR_PHY - Register accessor macros
11749    ---------------------------------------------------------------------------- */
11750 
11751 /*!
11752  * @addtogroup DDR_PHY_Register_Accessor_Macros DDR_PHY - Register accessor macros
11753  * @{
11754  */
11755 
11756 
11757 /* DDR_PHY - Register accessors */
11758 #define DDR_PHY_PHY_CON0_REG(base)               ((base)->PHY_CON0)
11759 #define DDR_PHY_PHY_CON1_REG(base)               ((base)->PHY_CON1)
11760 #define DDR_PHY_PHY_CON2_REG(base)               ((base)->PHY_CON2)
11761 #define DDR_PHY_PHY_CON3_REG(base)               ((base)->PHY_CON3)
11762 #define DDR_PHY_PHY_CON4_REG(base)               ((base)->PHY_CON4)
11763 #define DDR_PHY_PHY_CON5_REG(base)               ((base)->PHY_CON5)
11764 #define DDR_PHY_LP_CON0_REG(base)                ((base)->LP_CON0)
11765 #define DDR_PHY_RODT_CON0_REG(base)              ((base)->RODT_CON0)
11766 #define DDR_PHY_OFFSET_RD_CON0_REG(base)         ((base)->OFFSET_RD_CON0)
11767 #define DDR_PHY_OFFSET_WR_CON0_REG(base)         ((base)->OFFSET_WR_CON0)
11768 #define DDR_PHY_GATE_CODE_CON0_REG(base)         ((base)->GATE_CODE_CON0)
11769 #define DDR_PHY_SHIFTC_CON0_REG(base)            ((base)->SHIFTC_CON0)
11770 #define DDR_PHY_CMD_SDLL_CON0_REG(base)          ((base)->CMD_SDLL_CON0)
11771 #define DDR_PHY_LVL_CON0_REG(base)               ((base)->LVL_CON0)
11772 #define DDR_PHY_LVL_CON3_REG(base)               ((base)->LVL_CON3)
11773 #define DDR_PHY_CMD_DESKEW_CON0_REG(base)        ((base)->CMD_DESKEW_CON0)
11774 #define DDR_PHY_CMD_DESKEW_CON1_REG(base)        ((base)->CMD_DESKEW_CON1)
11775 #define DDR_PHY_CMD_DESKEW_CON2_REG(base)        ((base)->CMD_DESKEW_CON2)
11776 #define DDR_PHY_CMD_DESKEW_CON3_REG(base)        ((base)->CMD_DESKEW_CON3)
11777 #define DDR_PHY_CMD_DESKEW_CON4_REG(base)        ((base)->CMD_DESKEW_CON4)
11778 #define DDR_PHY_DRVDS_CON0_REG(base)             ((base)->DRVDS_CON0)
11779 #define DDR_PHY_MDLL_CON0_REG(base)              ((base)->MDLL_CON0)
11780 #define DDR_PHY_MDLL_CON1_REG(base)              ((base)->MDLL_CON1)
11781 #define DDR_PHY_ZQ_CON0_REG(base)                ((base)->ZQ_CON0)
11782 #define DDR_PHY_ZQ_CON1_REG(base)                ((base)->ZQ_CON1)
11783 #define DDR_PHY_ZQ_CON2_REG(base)                ((base)->ZQ_CON2)
11784 #define DDR_PHY_RD_DESKEW_CON0_REG(base)         ((base)->RD_DESKEW_CON0)
11785 #define DDR_PHY_RD_DESKEW_CON3_REG(base)         ((base)->RD_DESKEW_CON3)
11786 #define DDR_PHY_RD_DESKEW_CON6_REG(base)         ((base)->RD_DESKEW_CON6)
11787 #define DDR_PHY_RD_DESKEW_CON9_REG(base)         ((base)->RD_DESKEW_CON9)
11788 #define DDR_PHY_RD_DESKEW_CON12_REG(base)        ((base)->RD_DESKEW_CON12)
11789 #define DDR_PHY_RD_DESKEW_CON15_REG(base)        ((base)->RD_DESKEW_CON15)
11790 #define DDR_PHY_RD_DESKEW_CON18_REG(base)        ((base)->RD_DESKEW_CON18)
11791 #define DDR_PHY_RD_DESKEW_CON21_REG(base)        ((base)->RD_DESKEW_CON21)
11792 #define DDR_PHY_WR_DESKEW_CON0_REG(base)         ((base)->WR_DESKEW_CON0)
11793 #define DDR_PHY_WR_DESKEW_CON3_REG(base)         ((base)->WR_DESKEW_CON3)
11794 #define DDR_PHY_WR_DESKEW_CON6_REG(base)         ((base)->WR_DESKEW_CON6)
11795 #define DDR_PHY_WR_DESKEW_CON9_REG(base)         ((base)->WR_DESKEW_CON9)
11796 #define DDR_PHY_WR_DESKEW_CON12_REG(base)        ((base)->WR_DESKEW_CON12)
11797 #define DDR_PHY_WR_DESKEW_CON15_REG(base)        ((base)->WR_DESKEW_CON15)
11798 #define DDR_PHY_WR_DESKEW_CON18_REG(base)        ((base)->WR_DESKEW_CON18)
11799 #define DDR_PHY_WR_DESKEW_CON21_REG(base)        ((base)->WR_DESKEW_CON21)
11800 #define DDR_PHY_DM_DESKEW_CON_REG(base)          ((base)->DM_DESKEW_CON)
11801 #define DDR_PHY_RDATA0_REG(base)                 ((base)->RDATA0)
11802 #define DDR_PHY_STAT0_REG(base)                  ((base)->STAT0)
11803 
11804 /*!
11805  * @}
11806  */ /* end of group DDR_PHY_Register_Accessor_Macros */
11807 /* ----------------------------------------------------------------------------
11808    -- DDR_PHY Register Masks
11809    ---------------------------------------------------------------------------- */
11810 
11811 /*!
11812  * @addtogroup DDR_PHY_Register_Masks DDR_PHY Register Masks
11813  * @{
11814  */
11815 
11816 /* PHY_CON0 Bit Fields */
11817 #define DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK        0x7u
11818 #define DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT       0
11819 #define DDR_PHY_PHY_CON0_CTRL_FNC_FB(x)          (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT))&DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK)
11820 #define DDR_PHY_PHY_CON0_CTRL_TWPRE_MASK         0x8u
11821 #define DDR_PHY_PHY_CON0_CTRL_TWPRE_SHIFT        3
11822 #define DDR_PHY_PHY_CON0_CTRL_CMOSRCV_MASK       0x10u
11823 #define DDR_PHY_PHY_CON0_CTRL_CMOSRCV_SHIFT      4
11824 #define DDR_PHY_PHY_CON0_CTRL_ATGATE_MASK        0x40u
11825 #define DDR_PHY_PHY_CON0_CTRL_ATGATE_SHIFT       6
11826 #define DDR_PHY_PHY_CON0_CTRL_SHGATE_MASK        0x100u
11827 #define DDR_PHY_PHY_CON0_CTRL_SHGATE_SHIFT       8
11828 #define DDR_PHY_PHY_CON0_CTRL_DFDQS_MASK         0x200u
11829 #define DDR_PHY_PHY_CON0_CTRL_DFDQS_SHIFT        9
11830 #define DDR_PHY_PHY_CON0_CTRL_DDR_MODE_MASK      0x1800u
11831 #define DDR_PHY_PHY_CON0_CTRL_DDR_MODE_SHIFT     11
11832 #define DDR_PHY_PHY_CON0_CTRL_DDR_MODE(x)        (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_DDR_MODE_SHIFT))&DDR_PHY_PHY_CON0_CTRL_DDR_MODE_MASK)
11833 #define DDR_PHY_PHY_CON0_WRLVL_MODE_MASK         0x10000u
11834 #define DDR_PHY_PHY_CON0_WRLVL_MODE_SHIFT        16
11835 #define DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_MASK     0x300000u
11836 #define DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_SHIFT    20
11837 #define DDR_PHY_PHY_CON0_CTRL_UPD_RANGE(x)       (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_SHIFT))&DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_MASK)
11838 #define DDR_PHY_PHY_CON0_CTRL_UPD_MODE_MASK      0xC00000u
11839 #define DDR_PHY_PHY_CON0_CTRL_UPD_MODE_SHIFT     22
11840 #define DDR_PHY_PHY_CON0_CTRL_UPD_MODE(x)        (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_UPD_MODE_SHIFT))&DDR_PHY_PHY_CON0_CTRL_UPD_MODE_MASK)
11841 /* PHY_CON1 Bit Fields */
11842 #define DDR_PHY_PHY_CON1_ctrl_gateduradj_MASK    0xF00000u
11843 #define DDR_PHY_PHY_CON1_ctrl_gateduradj_SHIFT   20
11844 #define DDR_PHY_PHY_CON1_ctrl_gateduradj(x)      (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON1_ctrl_gateduradj_SHIFT))&DDR_PHY_PHY_CON1_ctrl_gateduradj_MASK)
11845 #define DDR_PHY_PHY_CON1_CTRL_GATEADJ_MASK       0xF0000000u
11846 #define DDR_PHY_PHY_CON1_CTRL_GATEADJ_SHIFT      28
11847 #define DDR_PHY_PHY_CON1_CTRL_GATEADJ(x)         (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON1_CTRL_GATEADJ_SHIFT))&DDR_PHY_PHY_CON1_CTRL_GATEADJ_MASK)
11848 /* PHY_CON2 Bit Fields */
11849 #define DDR_PHY_PHY_CON2_RDDESKEW_CLEAR_MASK     0x2000u
11850 #define DDR_PHY_PHY_CON2_RDDESKEW_CLEAR_SHIFT    13
11851 #define DDR_PHY_PHY_CON2_WRDESKEW_CLEAR_MASK     0x4000u
11852 #define DDR_PHY_PHY_CON2_WRDESKEW_CLEAR_SHIFT    14
11853 #define DDR_PHY_PHY_CON2_CA_CAL_MODE_MASK        0x800000u
11854 #define DDR_PHY_PHY_CON2_CA_CAL_MODE_SHIFT       23
11855 #define DDR_PHY_PHY_CON2_GATE_CAL_MODE_MASK      0x1000000u
11856 #define DDR_PHY_PHY_CON2_GATE_CAL_MODE_SHIFT     24
11857 /* PHY_CON3 Bit Fields */
11858 #define DDR_PHY_PHY_CON3_REG_MODE_MASK           0xFFu
11859 #define DDR_PHY_PHY_CON3_REG_MODE_SHIFT          0
11860 #define DDR_PHY_PHY_CON3_REG_MODE(x)             (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON3_REG_MODE_SHIFT))&DDR_PHY_PHY_CON3_REG_MODE_MASK)
11861 #define DDR_PHY_PHY_CON3_WRLVL_START_MASK        0x10000u
11862 #define DDR_PHY_PHY_CON3_WRLVL_START_SHIFT       16
11863 #define DDR_PHY_PHY_CON3_WL_CAL_MODE_MASK        0x100000u
11864 #define DDR_PHY_PHY_CON3_WL_CAL_MODE_SHIFT       20
11865 #define DDR_PHY_PHY_CON3_WL_CAL_START_MASK       0x200000u
11866 #define DDR_PHY_PHY_CON3_WL_CAL_START_SHIFT      21
11867 #define DDR_PHY_PHY_CON3_WRLVL_RESP_MASK         0x1000000u
11868 #define DDR_PHY_PHY_CON3_WRLVL_RESP_SHIFT        24
11869 #define DDR_PHY_PHY_CON3_WL_CAL_RESP_MASK        0x8000000u
11870 #define DDR_PHY_PHY_CON3_WL_CAL_RESP_SHIFT       27
11871 /* PHY_CON4 Bit Fields */
11872 #define DDR_PHY_PHY_CON4_CTRL_RDLAT_MASK         0x1Fu
11873 #define DDR_PHY_PHY_CON4_CTRL_RDLAT_SHIFT        0
11874 #define DDR_PHY_PHY_CON4_CTRL_RDLAT(x)           (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON4_CTRL_RDLAT_SHIFT))&DDR_PHY_PHY_CON4_CTRL_RDLAT_MASK)
11875 #define DDR_PHY_PHY_CON4_CTRL_BSTLEN_MASK        0x1F00u
11876 #define DDR_PHY_PHY_CON4_CTRL_BSTLEN_SHIFT       8
11877 #define DDR_PHY_PHY_CON4_CTRL_BSTLEN(x)          (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON4_CTRL_BSTLEN_SHIFT))&DDR_PHY_PHY_CON4_CTRL_BSTLEN_MASK)
11878 #define DDR_PHY_PHY_CON4_CTRL_WRLAT_MASK         0x1F0000u
11879 #define DDR_PHY_PHY_CON4_CTRL_WRLAT_SHIFT        16
11880 #define DDR_PHY_PHY_CON4_CTRL_WRLAT(x)           (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON4_CTRL_WRLAT_SHIFT))&DDR_PHY_PHY_CON4_CTRL_WRLAT_MASK)
11881 /* PHY_CON5 Bit Fields */
11882 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_MASK 0x7u
11883 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_SHIFT 0
11884 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0(x)   (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_MASK)
11885 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_MASK 0x38u
11886 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_SHIFT 3
11887 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1(x)   (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_MASK)
11888 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_MASK   0x1C0u
11889 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_SHIFT  6
11890 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_MASK)
11891 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_MASK   0xE00u
11892 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_SHIFT  9
11893 #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_MASK)
11894 /* LP_CON0 Bit Fields */
11895 #define DDR_PHY_LP_CON0_CTRL_PULLD_DQS_MASK      0x1FFu
11896 #define DDR_PHY_LP_CON0_CTRL_PULLD_DQS_SHIFT     0
11897 #define DDR_PHY_LP_CON0_CTRL_PULLD_DQS(x)        (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LP_CON0_CTRL_PULLD_DQS_SHIFT))&DDR_PHY_LP_CON0_CTRL_PULLD_DQS_MASK)
11898 #define DDR_PHY_LP_CON0_CTRL_PULLD_DQ_MASK       0x1FF0000u
11899 #define DDR_PHY_LP_CON0_CTRL_PULLD_DQ_SHIFT      16
11900 #define DDR_PHY_LP_CON0_CTRL_PULLD_DQ(x)         (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LP_CON0_CTRL_PULLD_DQ_SHIFT))&DDR_PHY_LP_CON0_CTRL_PULLD_DQ_MASK)
11901 /* RODT_CON0 Bit Fields */
11902 #define DDR_PHY_RODT_CON0_CTRL_READ_DIS_MASK     0x10000u
11903 #define DDR_PHY_RODT_CON0_CTRL_READ_DIS_SHIFT    16
11904 /* OFFSET_RD_CON0 Bit Fields */
11905 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_MASK 0xFFu
11906 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_SHIFT 0
11907 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_MASK)
11908 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_MASK 0xFF00u
11909 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_SHIFT 8
11910 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_MASK)
11911 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_MASK 0xFF0000u
11912 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_SHIFT 16
11913 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_MASK)
11914 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_MASK 0xFF000000u
11915 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_SHIFT 24
11916 #define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_MASK)
11917 /* OFFSET_WR_CON0 Bit Fields */
11918 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_MASK 0xFFu
11919 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_SHIFT 0
11920 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_MASK)
11921 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_MASK 0xFF00u
11922 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_SHIFT 8
11923 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_MASK)
11924 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_MASK 0xFF0000u
11925 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_SHIFT 16
11926 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_MASK)
11927 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_MASK 0xFF000000u
11928 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_SHIFT 24
11929 #define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_MASK)
11930 /* GATE_CODE_CON0 Bit Fields */
11931 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_MASK 0xFFu
11932 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_SHIFT 0
11933 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_MASK)
11934 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_MASK 0xFF00u
11935 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_SHIFT 8
11936 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_MASK)
11937 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_MASK 0xFF0000u
11938 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_SHIFT 16
11939 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_MASK)
11940 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_MASK 0xFF000000u
11941 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_SHIFT 24
11942 #define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_MASK)
11943 /* SHIFTC_CON0 Bit Fields */
11944 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_MASK    0x7u
11945 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_SHIFT   0
11946 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0(x)      (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_MASK)
11947 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_MASK    0x38u
11948 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_SHIFT   3
11949 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1(x)      (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_MASK)
11950 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_MASK    0x1C0u
11951 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_SHIFT   6
11952 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2(x)      (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_MASK)
11953 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_MASK    0xE00u
11954 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_SHIFT   9
11955 #define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3(x)      (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_MASK)
11956 /* CMD_SDLL_CON0 Bit Fields */
11957 #define DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_MASK  0xFFu
11958 #define DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_SHIFT 0
11959 #define DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_SHIFT))&DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_MASK)
11960 #define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK   0x1000000u
11961 #define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_SHIFT  24
11962 #define DDR_PHY_CMD_SDLL_CON0_UPD_MODE_MASK      0x10000000u
11963 #define DDR_PHY_CMD_SDLL_CON0_UPD_MODE_SHIFT     28
11964 /* LVL_CON0 Bit Fields */
11965 #define DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_MASK   0xFFu
11966 #define DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_SHIFT  0
11967 #define DDR_PHY_LVL_CON0_ctrl_wrlvl0_code(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_MASK)
11968 #define DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_MASK   0xFF00u
11969 #define DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_SHIFT  8
11970 #define DDR_PHY_LVL_CON0_ctrl_wrlvl1_code(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_MASK)
11971 #define DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_MASK   0xFF0000u
11972 #define DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_SHIFT  16
11973 #define DDR_PHY_LVL_CON0_ctrl_wrlvl2_code(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_MASK)
11974 #define DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_MASK   0xFF000000u
11975 #define DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_SHIFT  24
11976 #define DDR_PHY_LVL_CON0_ctrl_wrlvl3_code(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_MASK)
11977 /* LVL_CON3 Bit Fields */
11978 #define DDR_PHY_LVL_CON3_CTRL_WRLVL_RESYNC_MASK  0x1u
11979 #define DDR_PHY_LVL_CON3_CTRL_WRLVL_RESYNC_SHIFT 0
11980 /* CMD_DESKEW_CON0 Bit Fields */
11981 #define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_MASK 0xFFu
11982 #define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_SHIFT 0
11983 #define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_MASK)
11984 #define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_MASK 0xFF00u
11985 #define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_SHIFT 8
11986 #define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_MASK)
11987 #define DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_MASK 0xFF0000u
11988 #define DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_SHIFT 16
11989 #define DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_MASK)
11990 #define DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_MASK 0xFF000000u
11991 #define DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_SHIFT 24
11992 #define DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_MASK)
11993 /* CMD_DESKEW_CON1 Bit Fields */
11994 #define DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_MASK 0xFFu
11995 #define DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_SHIFT 0
11996 #define DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_MASK)
11997 #define DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_MASK 0xFF00u
11998 #define DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_SHIFT 8
11999 #define DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_MASK)
12000 #define DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_MASK 0xFF0000u
12001 #define DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_SHIFT 16
12002 #define DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_MASK)
12003 #define DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_MASK 0xFF000000u
12004 #define DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_SHIFT 24
12005 #define DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_MASK)
12006 /* CMD_DESKEW_CON2 Bit Fields */
12007 #define DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_MASK 0xFFu
12008 #define DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_SHIFT 0
12009 #define DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_MASK)
12010 #define DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_MASK 0xFF00u
12011 #define DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_SHIFT 8
12012 #define DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_MASK)
12013 #define DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_MASK 0xFF0000u
12014 #define DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_SHIFT 16
12015 #define DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE(x)  (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_MASK)
12016 #define DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_MASK 0xFF000000u
12017 #define DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_SHIFT 24
12018 #define DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_MASK)
12019 /* CMD_DESKEW_CON3 Bit Fields */
12020 #define DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_MASK 0xFFu
12021 #define DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_SHIFT 0
12022 #define DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_MASK)
12023 #define DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_MASK 0xFF00u
12024 #define DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_SHIFT 8
12025 #define DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_MASK)
12026 #define DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_MASK 0xFF0000u
12027 #define DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_SHIFT 16
12028 #define DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_MASK)
12029 /* CMD_DESKEW_CON4 Bit Fields */
12030 #define DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_MASK 0xFFu
12031 #define DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_SHIFT 0
12032 #define DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_MASK)
12033 /* DRVDS_CON0 Bit Fields */
12034 #define DDR_PHY_DRVDS_CON0_CAADRDRVRDS_MASK      0x7u
12035 #define DDR_PHY_DRVDS_CON0_CAADRDRVRDS_SHIFT     0
12036 #define DDR_PHY_DRVDS_CON0_CAADRDRVRDS(x)        (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CAADRDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CAADRDRVRDS_MASK)
12037 #define DDR_PHY_DRVDS_CON0_CACSDRVRDS_MASK       0x38u
12038 #define DDR_PHY_DRVDS_CON0_CACSDRVRDS_SHIFT      3
12039 #define DDR_PHY_DRVDS_CON0_CACSDRVRDS(x)         (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CACSDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CACSDRVRDS_MASK)
12040 #define DDR_PHY_DRVDS_CON0_CACKEDRVRDS_MASK      0x1C0u
12041 #define DDR_PHY_DRVDS_CON0_CACKEDRVRDS_SHIFT     6
12042 #define DDR_PHY_DRVDS_CON0_CACKEDRVRDS(x)        (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CACKEDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CACKEDRVRDS_MASK)
12043 #define DDR_PHY_DRVDS_CON0_CACKDRVRDS_MASK       0xE00u
12044 #define DDR_PHY_DRVDS_CON0_CACKDRVRDS_SHIFT      9
12045 #define DDR_PHY_DRVDS_CON0_CACKDRVRDS(x)         (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CACKDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CACKDRVRDS_MASK)
12046 /* MDLL_CON0 Bit Fields */
12047 #define DDR_PHY_MDLL_CON0_CTRL_REF_MASK          0x1Eu
12048 #define DDR_PHY_MDLL_CON0_CTRL_REF_SHIFT         1
12049 #define DDR_PHY_MDLL_CON0_CTRL_REF(x)            (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_REF_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_REF_MASK)
12050 #define DDR_PHY_MDLL_CON0_CTRL_DLL_ON_MASK       0x20u
12051 #define DDR_PHY_MDLL_CON0_CTRL_DLL_ON_SHIFT      5
12052 #define DDR_PHY_MDLL_CON0_CTRL_START_MASK        0x40u
12053 #define DDR_PHY_MDLL_CON0_CTRL_START_SHIFT       6
12054 #define DDR_PHY_MDLL_CON0_CTRL_FORCE_MASK        0xFF80u
12055 #define DDR_PHY_MDLL_CON0_CTRL_FORCE_SHIFT       7
12056 #define DDR_PHY_MDLL_CON0_CTRL_FORCE(x)          (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_FORCE_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_FORCE_MASK)
12057 #define DDR_PHY_MDLL_CON0_CTRL_INC_MASK          0x7F0000u
12058 #define DDR_PHY_MDLL_CON0_CTRL_INC_SHIFT         16
12059 #define DDR_PHY_MDLL_CON0_CTRL_INC(x)            (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_INC_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_INC_MASK)
12060 #define DDR_PHY_MDLL_CON0_CTRL_START_POINT_MASK  0x7F000000u
12061 #define DDR_PHY_MDLL_CON0_CTRL_START_POINT_SHIFT 24
12062 #define DDR_PHY_MDLL_CON0_CTRL_START_POINT(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_START_POINT_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_START_POINT_MASK)
12063 /* MDLL_CON1 Bit Fields */
12064 #define DDR_PHY_MDLL_CON1_CTRL_LOCKED_MASK       0x1u
12065 #define DDR_PHY_MDLL_CON1_CTRL_LOCKED_SHIFT      0
12066 #define DDR_PHY_MDLL_CON1_CTRL_FLOCK_MASK        0x2u
12067 #define DDR_PHY_MDLL_CON1_CTRL_FLOCK_SHIFT       1
12068 #define DDR_PHY_MDLL_CON1_CTRL_CLOCK_MASK        0x4u
12069 #define DDR_PHY_MDLL_CON1_CTRL_CLOCK_SHIFT       2
12070 #define DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_MASK   0x1FF00u
12071 #define DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_SHIFT  8
12072 #define DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_SHIFT))&DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_MASK)
12073 /* ZQ_CON0 Bit Fields */
12074 #define DDR_PHY_ZQ_CON0_ZQ_AUTO_EN_MASK          0x1u
12075 #define DDR_PHY_ZQ_CON0_ZQ_AUTO_EN_SHIFT         0
12076 #define DDR_PHY_ZQ_CON0_ZQ_MANUAL_STR_MASK       0x2u
12077 #define DDR_PHY_ZQ_CON0_ZQ_MANUAL_STR_SHIFT      1
12078 #define DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_MASK      0xCu
12079 #define DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_SHIFT     2
12080 #define DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE(x)        (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_MASK)
12081 #define DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_MASK          0xFF0u
12082 #define DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_SHIFT         4
12083 #define DDR_PHY_ZQ_CON0_ZQ_UDT_DLY(x)            (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_MASK)
12084 #define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_MASK       0x7000u
12085 #define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_SHIFT      12
12086 #define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP(x)         (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_MASK)
12087 #define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_MASK       0x38000u
12088 #define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_SHIFT      15
12089 #define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN(x)         (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_MASK)
12090 #define DDR_PHY_ZQ_CON0_ZQ_CLK_DIV_EN_MASK       0x40000u
12091 #define DDR_PHY_ZQ_CON0_ZQ_CLK_DIV_EN_SHIFT      18
12092 #define DDR_PHY_ZQ_CON0_ZQ_MODE_NOTERM_MASK      0x80000u
12093 #define DDR_PHY_ZQ_CON0_ZQ_MODE_NOTERM_SHIFT     19
12094 #define DDR_PHY_ZQ_CON0_ZQ_RGDDR3_MASK           0x100000u
12095 #define DDR_PHY_ZQ_CON0_ZQ_RGDDR3_SHIFT          20
12096 #define DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_MASK        0xE00000u
12097 #define DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_SHIFT       21
12098 #define DDR_PHY_ZQ_CON0_ZQ_MODE_TERM(x)          (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_MASK)
12099 #define DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_MASK         0x7000000u
12100 #define DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_SHIFT        24
12101 #define DDR_PHY_ZQ_CON0_ZQ_MODE_DDS(x)           (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_MASK)
12102 #define DDR_PHY_ZQ_CON0_ZQ_CLK_EN_MASK           0x8000000u
12103 #define DDR_PHY_ZQ_CON0_ZQ_CLK_EN_SHIFT          27
12104 /* ZQ_CON1 Bit Fields */
12105 #define DDR_PHY_ZQ_CON1_ZQ_DONE_MASK             0x1u
12106 #define DDR_PHY_ZQ_CON1_ZQ_DONE_SHIFT            0
12107 #define DDR_PHY_ZQ_CON1_ZQ_PENDING_MASK          0x2u
12108 #define DDR_PHY_ZQ_CON1_ZQ_PENDING_SHIFT         1
12109 #define DDR_PHY_ZQ_CON1_ZQ_ERROR_MASK            0x4u
12110 #define DDR_PHY_ZQ_CON1_ZQ_ERROR_SHIFT           2
12111 #define DDR_PHY_ZQ_CON1_ZQ_NMON_MASK             0x38u
12112 #define DDR_PHY_ZQ_CON1_ZQ_NMON_SHIFT            3
12113 #define DDR_PHY_ZQ_CON1_ZQ_NMON(x)               (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON1_ZQ_NMON_SHIFT))&DDR_PHY_ZQ_CON1_ZQ_NMON_MASK)
12114 #define DDR_PHY_ZQ_CON1_ZQ_PMON_MASK             0x1C0u
12115 #define DDR_PHY_ZQ_CON1_ZQ_PMON_SHIFT            6
12116 #define DDR_PHY_ZQ_CON1_ZQ_PMON(x)               (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON1_ZQ_PMON_SHIFT))&DDR_PHY_ZQ_CON1_ZQ_PMON_MASK)
12117 /* ZQ_CON2 Bit Fields */
12118 #define DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_MASK     0xFFFFu
12119 #define DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_SHIFT    0
12120 #define DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV(x)       (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_SHIFT))&DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_MASK)
12121 /* RD_DESKEW_CON0 Bit Fields */
12122 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_MASK   0xFFu
12123 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_SHIFT  0
12124 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_MASK)
12125 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_MASK   0xFF00u
12126 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_SHIFT  8
12127 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_MASK)
12128 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_MASK   0xFF0000u
12129 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_SHIFT  16
12130 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_MASK)
12131 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_MASK   0xFF000000u
12132 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_SHIFT  24
12133 #define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_MASK)
12134 /* RD_DESKEW_CON3 Bit Fields */
12135 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_MASK   0xFFu
12136 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_SHIFT  0
12137 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_MASK)
12138 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_MASK   0xFF00u
12139 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_SHIFT  8
12140 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_MASK)
12141 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_MASK   0xFF0000u
12142 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_SHIFT  16
12143 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_MASK)
12144 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_MASK   0xFF000000u
12145 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_SHIFT  24
12146 #define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_MASK)
12147 /* RD_DESKEW_CON6 Bit Fields */
12148 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_MASK   0xFFu
12149 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_SHIFT  0
12150 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_MASK)
12151 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_MASK   0xFF00u
12152 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_SHIFT  8
12153 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_MASK)
12154 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_MASK   0xFF0000u
12155 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_SHIFT  16
12156 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_MASK)
12157 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_MASK   0xFF000000u
12158 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_SHIFT  24
12159 #define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_MASK)
12160 /* RD_DESKEW_CON9 Bit Fields */
12161 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_MASK   0xFFu
12162 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_SHIFT  0
12163 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_MASK)
12164 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_MASK   0xFF00u
12165 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_SHIFT  8
12166 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_MASK)
12167 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_MASK   0xFF0000u
12168 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_SHIFT  16
12169 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_MASK)
12170 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_MASK   0xFF000000u
12171 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_SHIFT  24
12172 #define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_MASK)
12173 /* RD_DESKEW_CON12 Bit Fields */
12174 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_MASK  0xFFu
12175 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_SHIFT 0
12176 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_MASK)
12177 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_MASK  0xFF00u
12178 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_SHIFT 8
12179 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_MASK)
12180 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_MASK  0xFF0000u
12181 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_SHIFT 16
12182 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_MASK)
12183 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_MASK  0xFF000000u
12184 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_SHIFT 24
12185 #define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_MASK)
12186 /* RD_DESKEW_CON15 Bit Fields */
12187 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_MASK  0xFFu
12188 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_SHIFT 0
12189 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_MASK)
12190 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_MASK  0xFF00u
12191 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_SHIFT 8
12192 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_MASK)
12193 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_MASK  0xFF0000u
12194 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_SHIFT 16
12195 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_MASK)
12196 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_MASK  0xFF000000u
12197 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_SHIFT 24
12198 #define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_MASK)
12199 /* RD_DESKEW_CON18 Bit Fields */
12200 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_MASK  0xFFu
12201 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_SHIFT 0
12202 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_MASK)
12203 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_MASK  0xFF00u
12204 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_SHIFT 8
12205 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_MASK)
12206 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_MASK  0xFF0000u
12207 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_SHIFT 16
12208 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_MASK)
12209 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_MASK  0xFF000000u
12210 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_SHIFT 24
12211 #define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_MASK)
12212 /* RD_DESKEW_CON21 Bit Fields */
12213 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_MASK  0xFFu
12214 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_SHIFT 0
12215 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_MASK)
12216 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_MASK  0xFF00u
12217 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_SHIFT 8
12218 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_MASK)
12219 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_MASK  0xFF0000u
12220 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_SHIFT 16
12221 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_MASK)
12222 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_MASK  0xFF000000u
12223 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_SHIFT 24
12224 #define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_MASK)
12225 /* WR_DESKEW_CON0 Bit Fields */
12226 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_MASK   0xFFu
12227 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_SHIFT  0
12228 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_MASK)
12229 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_MASK   0xFF00u
12230 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_SHIFT  8
12231 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_MASK)
12232 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_MASK   0xFF0000u
12233 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_SHIFT  16
12234 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_MASK)
12235 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_MASK   0xFF000000u
12236 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_SHIFT  24
12237 #define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_MASK)
12238 /* WR_DESKEW_CON3 Bit Fields */
12239 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_MASK   0xFFu
12240 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_SHIFT  0
12241 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_MASK)
12242 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_MASK   0xFF00u
12243 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_SHIFT  8
12244 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_MASK)
12245 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_MASK   0xFF0000u
12246 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_SHIFT  16
12247 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_MASK)
12248 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_MASK   0xFF000000u
12249 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_SHIFT  24
12250 #define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_MASK)
12251 /* WR_DESKEW_CON6 Bit Fields */
12252 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_MASK   0xFFu
12253 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_SHIFT  0
12254 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_MASK)
12255 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_MASK   0xFF00u
12256 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_SHIFT  8
12257 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_MASK)
12258 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_MASK   0xFF0000u
12259 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_SHIFT  16
12260 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_MASK)
12261 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_MASK   0xFF000000u
12262 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_SHIFT  24
12263 #define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_MASK)
12264 /* WR_DESKEW_CON9 Bit Fields */
12265 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_MASK   0xFFu
12266 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_SHIFT  0
12267 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_MASK)
12268 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_MASK   0xFF00u
12269 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_SHIFT  8
12270 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_MASK)
12271 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_MASK   0xFF0000u
12272 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_SHIFT  16
12273 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_MASK)
12274 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_MASK   0xFF000000u
12275 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_SHIFT  24
12276 #define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3(x)     (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_MASK)
12277 /* WR_DESKEW_CON12 Bit Fields */
12278 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_MASK  0xFFu
12279 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_SHIFT 0
12280 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_MASK)
12281 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_MASK  0xFF00u
12282 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_SHIFT 8
12283 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_MASK)
12284 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_MASK  0xFF0000u
12285 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_SHIFT 16
12286 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_MASK)
12287 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_MASK  0xFF000000u
12288 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_SHIFT 24
12289 #define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_MASK)
12290 /* WR_DESKEW_CON15 Bit Fields */
12291 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_MASK  0xFFu
12292 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_SHIFT 0
12293 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_MASK)
12294 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_MASK  0xFF00u
12295 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_SHIFT 8
12296 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_MASK)
12297 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_MASK  0xFF0000u
12298 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_SHIFT 16
12299 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_MASK)
12300 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_MASK  0xFF000000u
12301 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_SHIFT 24
12302 #define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_MASK)
12303 /* WR_DESKEW_CON18 Bit Fields */
12304 #define DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_MASK  0xFFu
12305 #define DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_SHIFT 0
12306 #define DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_MASK)
12307 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_MASK  0xFF00u
12308 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_SHIFT 8
12309 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_MASK)
12310 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_MASK  0xFF0000u
12311 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_SHIFT 16
12312 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_MASK)
12313 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_MASK  0xFF000000u
12314 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_SHIFT 24
12315 #define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_MASK)
12316 /* WR_DESKEW_CON21 Bit Fields */
12317 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_MASK  0xFFu
12318 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_SHIFT 0
12319 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_MASK)
12320 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_MASK  0xFF00u
12321 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_SHIFT 8
12322 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_MASK)
12323 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_MASK  0xFF0000u
12324 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_SHIFT 16
12325 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_MASK)
12326 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_MASK  0xFF000000u
12327 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_SHIFT 24
12328 #define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3(x)    (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_MASK)
12329 /* DM_DESKEW_CON Bit Fields */
12330 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW0_MASK     0xFFu
12331 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW0_SHIFT    0
12332 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW0(x)       (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW0_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW0_MASK)
12333 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW1_MASK     0xFF00u
12334 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW1_SHIFT    8
12335 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW1(x)       (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW1_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW1_MASK)
12336 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW2_MASK     0xFF0000u
12337 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW2_SHIFT    16
12338 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW2(x)       (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW2_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW2_MASK)
12339 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW3_MASK     0xFF000000u
12340 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW3_SHIFT    24
12341 #define DDR_PHY_DM_DESKEW_CON_DMDESKEW3(x)       (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW3_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW3_MASK)
12342 /* RDATA0 Bit Fields */
12343 #define DDR_PHY_RDATA0_DQ_IO_RD0_MASK            0xFFu
12344 #define DDR_PHY_RDATA0_DQ_IO_RD0_SHIFT           0
12345 #define DDR_PHY_RDATA0_DQ_IO_RD0(x)              (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD0_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD0_MASK)
12346 #define DDR_PHY_RDATA0_DQ_IO_RD1_MASK            0xFF00u
12347 #define DDR_PHY_RDATA0_DQ_IO_RD1_SHIFT           8
12348 #define DDR_PHY_RDATA0_DQ_IO_RD1(x)              (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD1_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD1_MASK)
12349 #define DDR_PHY_RDATA0_DQ_IO_RD2_MASK            0xFF0000u
12350 #define DDR_PHY_RDATA0_DQ_IO_RD2_SHIFT           16
12351 #define DDR_PHY_RDATA0_DQ_IO_RD2(x)              (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD2_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD2_MASK)
12352 #define DDR_PHY_RDATA0_DQ_IO_RD3_MASK            0xFF000000u
12353 #define DDR_PHY_RDATA0_DQ_IO_RD3_SHIFT           24
12354 #define DDR_PHY_RDATA0_DQ_IO_RD3(x)              (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD3_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD3_MASK)
12355 /* STAT0 Bit Fields */
12356 #define DDR_PHY_STAT0_VERSION_INFO_MASK          0xFFFFFFFFu
12357 #define DDR_PHY_STAT0_VERSION_INFO_SHIFT         0
12358 #define DDR_PHY_STAT0_VERSION_INFO(x)            (((uint32_t)(((uint32_t)(x))<<DDR_PHY_STAT0_VERSION_INFO_SHIFT))&DDR_PHY_STAT0_VERSION_INFO_MASK)
12359 
12360 /*!
12361  * @}
12362  */ /* end of group DDR_PHY_Register_Masks */
12363 
12364 /* DDR_PHY - Peripheral instance base addresses */
12365 /** Peripheral DDR_PHY base address */
12366 #define DDR_PHY_BASE                             (0x30790000u)
12367 /** Peripheral DDR_PHY base pointer */
12368 #define DDR_PHY                                  ((DDR_PHY_Type *)DDR_PHY_BASE)
12369 #define DDR_PHY_BASE_PTR                         (DDR_PHY)
12370 /** Array initializer of DDR_PHY peripheral base addresses */
12371 #define DDR_PHY_BASE_ADDRS                       { DDR_PHY_BASE }
12372 /** Array initializer of DDR_PHY peripheral base pointers */
12373 #define DDR_PHY_BASE_PTRS                        { DDR_PHY }
12374 /* ----------------------------------------------------------------------------
12375    -- DDR_PHY - Register accessor macros
12376    ---------------------------------------------------------------------------- */
12377 
12378 /*!
12379  * @addtogroup DDR_PHY_Register_Accessor_Macros DDR_PHY - Register accessor macros
12380  * @{
12381  */
12382 
12383 
12384 /* DDR_PHY - Register instance definitions */
12385 /* DDR_PHY */
12386 #define DDR_PHY_PHY_CON0                         DDR_PHY_PHY_CON0_REG(DDR_PHY_BASE_PTR)
12387 #define DDR_PHY_PHY_CON1                         DDR_PHY_PHY_CON1_REG(DDR_PHY_BASE_PTR)
12388 #define DDR_PHY_PHY_CON2                         DDR_PHY_PHY_CON2_REG(DDR_PHY_BASE_PTR)
12389 #define DDR_PHY_PHY_CON3                         DDR_PHY_PHY_CON3_REG(DDR_PHY_BASE_PTR)
12390 #define DDR_PHY_PHY_CON4                         DDR_PHY_PHY_CON4_REG(DDR_PHY_BASE_PTR)
12391 #define DDR_PHY_PHY_CON5                         DDR_PHY_PHY_CON5_REG(DDR_PHY_BASE_PTR)
12392 #define DDR_PHY_LP_CON0                          DDR_PHY_LP_CON0_REG(DDR_PHY_BASE_PTR)
12393 #define DDR_PHY_RODT_CON0                        DDR_PHY_RODT_CON0_REG(DDR_PHY_BASE_PTR)
12394 #define DDR_PHY_OFFSET_RD_CON0                   DDR_PHY_OFFSET_RD_CON0_REG(DDR_PHY_BASE_PTR)
12395 #define DDR_PHY_OFFSET_WR_CON0                   DDR_PHY_OFFSET_WR_CON0_REG(DDR_PHY_BASE_PTR)
12396 #define DDR_PHY_GATE_CODE_CON0                   DDR_PHY_GATE_CODE_CON0_REG(DDR_PHY_BASE_PTR)
12397 #define DDR_PHY_SHIFTC_CON0                      DDR_PHY_SHIFTC_CON0_REG(DDR_PHY_BASE_PTR)
12398 #define DDR_PHY_CMD_SDLL_CON0                    DDR_PHY_CMD_SDLL_CON0_REG(DDR_PHY_BASE_PTR)
12399 #define DDR_PHY_LVL_CON0                         DDR_PHY_LVL_CON0_REG(DDR_PHY_BASE_PTR)
12400 #define DDR_PHY_LVL_CON3                         DDR_PHY_LVL_CON3_REG(DDR_PHY_BASE_PTR)
12401 #define DDR_PHY_CMD_DESKEW_CON0                  DDR_PHY_CMD_DESKEW_CON0_REG(DDR_PHY_BASE_PTR)
12402 #define DDR_PHY_CMD_DESKEW_CON1                  DDR_PHY_CMD_DESKEW_CON1_REG(DDR_PHY_BASE_PTR)
12403 #define DDR_PHY_CMD_DESKEW_CON2                  DDR_PHY_CMD_DESKEW_CON2_REG(DDR_PHY_BASE_PTR)
12404 #define DDR_PHY_CMD_DESKEW_CON3                  DDR_PHY_CMD_DESKEW_CON3_REG(DDR_PHY_BASE_PTR)
12405 #define DDR_PHY_CMD_DESKEW_CON4                  DDR_PHY_CMD_DESKEW_CON4_REG(DDR_PHY_BASE_PTR)
12406 #define DDR_PHY_DRVDS_CON0                       DDR_PHY_DRVDS_CON0_REG(DDR_PHY_BASE_PTR)
12407 #define DDR_PHY_MDLL_CON0                        DDR_PHY_MDLL_CON0_REG(DDR_PHY_BASE_PTR)
12408 #define DDR_PHY_MDLL_CON1                        DDR_PHY_MDLL_CON1_REG(DDR_PHY_BASE_PTR)
12409 #define DDR_PHY_ZQ_CON0                          DDR_PHY_ZQ_CON0_REG(DDR_PHY_BASE_PTR)
12410 #define DDR_PHY_ZQ_CON1                          DDR_PHY_ZQ_CON1_REG(DDR_PHY_BASE_PTR)
12411 #define DDR_PHY_ZQ_CON2                          DDR_PHY_ZQ_CON2_REG(DDR_PHY_BASE_PTR)
12412 #define DDR_PHY_RD_DESKEW_CON0                   DDR_PHY_RD_DESKEW_CON0_REG(DDR_PHY_BASE_PTR)
12413 #define DDR_PHY_RD_DESKEW_CON3                   DDR_PHY_RD_DESKEW_CON3_REG(DDR_PHY_BASE_PTR)
12414 #define DDR_PHY_RD_DESKEW_CON6                   DDR_PHY_RD_DESKEW_CON6_REG(DDR_PHY_BASE_PTR)
12415 #define DDR_PHY_RD_DESKEW_CON9                   DDR_PHY_RD_DESKEW_CON9_REG(DDR_PHY_BASE_PTR)
12416 #define DDR_PHY_RD_DESKEW_CON12                  DDR_PHY_RD_DESKEW_CON12_REG(DDR_PHY_BASE_PTR)
12417 #define DDR_PHY_RD_DESKEW_CON15                  DDR_PHY_RD_DESKEW_CON15_REG(DDR_PHY_BASE_PTR)
12418 #define DDR_PHY_RD_DESKEW_CON18                  DDR_PHY_RD_DESKEW_CON18_REG(DDR_PHY_BASE_PTR)
12419 #define DDR_PHY_RD_DESKEW_CON21                  DDR_PHY_RD_DESKEW_CON21_REG(DDR_PHY_BASE_PTR)
12420 #define DDR_PHY_WR_DESKEW_CON0                   DDR_PHY_WR_DESKEW_CON0_REG(DDR_PHY_BASE_PTR)
12421 #define DDR_PHY_WR_DESKEW_CON3                   DDR_PHY_WR_DESKEW_CON3_REG(DDR_PHY_BASE_PTR)
12422 #define DDR_PHY_WR_DESKEW_CON6                   DDR_PHY_WR_DESKEW_CON6_REG(DDR_PHY_BASE_PTR)
12423 #define DDR_PHY_WR_DESKEW_CON9                   DDR_PHY_WR_DESKEW_CON9_REG(DDR_PHY_BASE_PTR)
12424 #define DDR_PHY_WR_DESKEW_CON12                  DDR_PHY_WR_DESKEW_CON12_REG(DDR_PHY_BASE_PTR)
12425 #define DDR_PHY_WR_DESKEW_CON15                  DDR_PHY_WR_DESKEW_CON15_REG(DDR_PHY_BASE_PTR)
12426 #define DDR_PHY_WR_DESKEW_CON18                  DDR_PHY_WR_DESKEW_CON18_REG(DDR_PHY_BASE_PTR)
12427 #define DDR_PHY_WR_DESKEW_CON21                  DDR_PHY_WR_DESKEW_CON21_REG(DDR_PHY_BASE_PTR)
12428 #define DDR_PHY_DM_DESKEW_CON                    DDR_PHY_DM_DESKEW_CON_REG(DDR_PHY_BASE_PTR)
12429 #define DDR_PHY_RDATA0                           DDR_PHY_RDATA0_REG(DDR_PHY_BASE_PTR)
12430 #define DDR_PHY_STAT0                            DDR_PHY_STAT0_REG(DDR_PHY_BASE_PTR)
12431 /*!
12432  * @}
12433  */ /* end of group DDR_PHY_Register_Accessor_Macros */
12434 
12435 
12436 /*!
12437  * @}
12438  */ /* end of group DDR_PHY_Peripheral */
12439 
12440 /* ----------------------------------------------------------------------------
12441    -- ECSPI Peripheral Access Layer
12442    ---------------------------------------------------------------------------- */
12443 
12444 /*!
12445  * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
12446  * @{
12447  */
12448 
12449 /** ECSPI - Register Layout Typedef */
12450 typedef struct {
12451   __I   uint32_t RXDATA;                                 /**< Receive Data Register, offset: 0x0 */
12452   __O   uint32_t TXDATA;                                 /**< Transmit Data Register, offset: 0x4 */
12453   __IO  uint32_t CONREG;                                 /**< Control Register, offset: 0x8 */
12454   __IO  uint32_t CONFIGREG;                              /**< Config Register, offset: 0xC */
12455   __IO  uint32_t INTREG;                                 /**< Interrupt Control Register, offset: 0x10 */
12456   __IO  uint32_t DMAREG;                                 /**< DMA Control Register, offset: 0x14 */
12457   __IO  uint32_t STATREG;                                /**< Status Register, offset: 0x18 */
12458   __IO  uint32_t PERIODREG;                              /**< Sample Period Control Register, offset: 0x1C */
12459   __IO  uint32_t TESTREG;                                /**< Test Control Register, offset: 0x20 */
12460   uint8_t RESERVED_0[28];
12461   __O   uint32_t MSGDATA;                                /**< Message Data Register, offset: 0x40 */
12462 } ECSPI_Type, *ECSPI_MemMapPtr;
12463 /* ----------------------------------------------------------------------------
12464    -- ECSPI - Register accessor macros
12465    ---------------------------------------------------------------------------- */
12466 
12467 /*!
12468  * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros
12469  * @{
12470  */
12471 
12472 
12473 /* ECSPI - Register accessors */
12474 #define ECSPI_RXDATA_REG(base)                   ((base)->RXDATA)
12475 #define ECSPI_TXDATA_REG(base)                   ((base)->TXDATA)
12476 #define ECSPI_CONREG_REG(base)                   ((base)->CONREG)
12477 #define ECSPI_CONFIGREG_REG(base)                ((base)->CONFIGREG)
12478 #define ECSPI_INTREG_REG(base)                   ((base)->INTREG)
12479 #define ECSPI_DMAREG_REG(base)                   ((base)->DMAREG)
12480 #define ECSPI_STATREG_REG(base)                  ((base)->STATREG)
12481 #define ECSPI_PERIODREG_REG(base)                ((base)->PERIODREG)
12482 #define ECSPI_TESTREG_REG(base)                  ((base)->TESTREG)
12483 #define ECSPI_MSGDATA_REG(base)                  ((base)->MSGDATA)
12484 
12485 /*!
12486  * @}
12487  */ /* end of group ECSPI_Register_Accessor_Macros */
12488 /* ----------------------------------------------------------------------------
12489    -- ECSPI Register Masks
12490    ---------------------------------------------------------------------------- */
12491 
12492 /*!
12493  * @addtogroup ECSPI_Register_Masks ECSPI Register Masks
12494  * @{
12495  */
12496 
12497 /* RXDATA Bit Fields */
12498 #define ECSPI_RXDATA_ECSPI_RXDATA_MASK           0xFFFFFFFFu
12499 #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT          0
12500 #define ECSPI_RXDATA_ECSPI_RXDATA(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_RXDATA_ECSPI_RXDATA_SHIFT))&ECSPI_RXDATA_ECSPI_RXDATA_MASK)
12501 /* TXDATA Bit Fields */
12502 #define ECSPI_TXDATA_ECSPI_TXDATA_MASK           0xFFFFFFFFu
12503 #define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT          0
12504 #define ECSPI_TXDATA_ECSPI_TXDATA(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_TXDATA_ECSPI_TXDATA_SHIFT))&ECSPI_TXDATA_ECSPI_TXDATA_MASK)
12505 /* CONREG Bit Fields */
12506 #define ECSPI_CONREG_EN_MASK                     0x1u
12507 #define ECSPI_CONREG_EN_SHIFT                    0
12508 #define ECSPI_CONREG_HT_MASK                     0x2u
12509 #define ECSPI_CONREG_HT_SHIFT                    1
12510 #define ECSPI_CONREG_XCH_MASK                    0x4u
12511 #define ECSPI_CONREG_XCH_SHIFT                   2
12512 #define ECSPI_CONREG_SMC_MASK                    0x8u
12513 #define ECSPI_CONREG_SMC_SHIFT                   3
12514 #define ECSPI_CONREG_CHANNEL_MODE_MASK           0xF0u
12515 #define ECSPI_CONREG_CHANNEL_MODE_SHIFT          4
12516 #define ECSPI_CONREG_CHANNEL_MODE(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_MODE_SHIFT))&ECSPI_CONREG_CHANNEL_MODE_MASK)
12517 #define ECSPI_CONREG_POST_DIVIDER_MASK           0xF00u
12518 #define ECSPI_CONREG_POST_DIVIDER_SHIFT          8
12519 #define ECSPI_CONREG_POST_DIVIDER(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_POST_DIVIDER_SHIFT))&ECSPI_CONREG_POST_DIVIDER_MASK)
12520 #define ECSPI_CONREG_PRE_DIVIDER_MASK            0xF000u
12521 #define ECSPI_CONREG_PRE_DIVIDER_SHIFT           12
12522 #define ECSPI_CONREG_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_PRE_DIVIDER_SHIFT))&ECSPI_CONREG_PRE_DIVIDER_MASK)
12523 #define ECSPI_CONREG_DRCTL_MASK                  0x30000u
12524 #define ECSPI_CONREG_DRCTL_SHIFT                 16
12525 #define ECSPI_CONREG_DRCTL(x)                    (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_DRCTL_SHIFT))&ECSPI_CONREG_DRCTL_MASK)
12526 #define ECSPI_CONREG_CHANNEL_SELECT_MASK         0xC0000u
12527 #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT        18
12528 #define ECSPI_CONREG_CHANNEL_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_SELECT_SHIFT))&ECSPI_CONREG_CHANNEL_SELECT_MASK)
12529 #define ECSPI_CONREG_BURST_LENGTH_MASK           0xFFF00000u
12530 #define ECSPI_CONREG_BURST_LENGTH_SHIFT          20
12531 #define ECSPI_CONREG_BURST_LENGTH(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_BURST_LENGTH_SHIFT))&ECSPI_CONREG_BURST_LENGTH_MASK)
12532 /* CONFIGREG Bit Fields */
12533 #define ECSPI_CONFIGREG_SCLK_PHA_MASK            0xFu
12534 #define ECSPI_CONFIGREG_SCLK_PHA_SHIFT           0
12535 #define ECSPI_CONFIGREG_SCLK_PHA(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_PHA_SHIFT))&ECSPI_CONFIGREG_SCLK_PHA_MASK)
12536 #define ECSPI_CONFIGREG_SCLK_POL_MASK            0xF0u
12537 #define ECSPI_CONFIGREG_SCLK_POL_SHIFT           4
12538 #define ECSPI_CONFIGREG_SCLK_POL(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_POL_SHIFT))&ECSPI_CONFIGREG_SCLK_POL_MASK)
12539 #define ECSPI_CONFIGREG_SS_CTL_MASK              0xF00u
12540 #define ECSPI_CONFIGREG_SS_CTL_SHIFT             8
12541 #define ECSPI_CONFIGREG_SS_CTL(x)                (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_CTL_SHIFT))&ECSPI_CONFIGREG_SS_CTL_MASK)
12542 #define ECSPI_CONFIGREG_SS_POL_MASK              0xF000u
12543 #define ECSPI_CONFIGREG_SS_POL_SHIFT             12
12544 #define ECSPI_CONFIGREG_SS_POL(x)                (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_POL_SHIFT))&ECSPI_CONFIGREG_SS_POL_MASK)
12545 #define ECSPI_CONFIGREG_DATA_CTL_MASK            0xF0000u
12546 #define ECSPI_CONFIGREG_DATA_CTL_SHIFT           16
12547 #define ECSPI_CONFIGREG_DATA_CTL(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_DATA_CTL_SHIFT))&ECSPI_CONFIGREG_DATA_CTL_MASK)
12548 #define ECSPI_CONFIGREG_SCLK_CTL_MASK            0xF00000u
12549 #define ECSPI_CONFIGREG_SCLK_CTL_SHIFT           20
12550 #define ECSPI_CONFIGREG_SCLK_CTL(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_CTL_SHIFT))&ECSPI_CONFIGREG_SCLK_CTL_MASK)
12551 #define ECSPI_CONFIGREG_HT_LENGTH_MASK           0x1F000000u
12552 #define ECSPI_CONFIGREG_HT_LENGTH_SHIFT          24
12553 #define ECSPI_CONFIGREG_HT_LENGTH(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_HT_LENGTH_SHIFT))&ECSPI_CONFIGREG_HT_LENGTH_MASK)
12554 /* INTREG Bit Fields */
12555 #define ECSPI_INTREG_TEEN_MASK                   0x1u
12556 #define ECSPI_INTREG_TEEN_SHIFT                  0
12557 #define ECSPI_INTREG_TDREN_MASK                  0x2u
12558 #define ECSPI_INTREG_TDREN_SHIFT                 1
12559 #define ECSPI_INTREG_TFEN_MASK                   0x4u
12560 #define ECSPI_INTREG_TFEN_SHIFT                  2
12561 #define ECSPI_INTREG_RREN_MASK                   0x8u
12562 #define ECSPI_INTREG_RREN_SHIFT                  3
12563 #define ECSPI_INTREG_RDREN_MASK                  0x10u
12564 #define ECSPI_INTREG_RDREN_SHIFT                 4
12565 #define ECSPI_INTREG_RFEN_MASK                   0x20u
12566 #define ECSPI_INTREG_RFEN_SHIFT                  5
12567 #define ECSPI_INTREG_ROEN_MASK                   0x40u
12568 #define ECSPI_INTREG_ROEN_SHIFT                  6
12569 #define ECSPI_INTREG_TCEN_MASK                   0x80u
12570 #define ECSPI_INTREG_TCEN_SHIFT                  7
12571 /* DMAREG Bit Fields */
12572 #define ECSPI_DMAREG_TX_THRESHOLD_MASK           0x3Fu
12573 #define ECSPI_DMAREG_TX_THRESHOLD_SHIFT          0
12574 #define ECSPI_DMAREG_TX_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_TX_THRESHOLD_SHIFT))&ECSPI_DMAREG_TX_THRESHOLD_MASK)
12575 #define ECSPI_DMAREG_TEDEN_MASK                  0x80u
12576 #define ECSPI_DMAREG_TEDEN_SHIFT                 7
12577 #define ECSPI_DMAREG_RX_THRESHOLD_MASK           0x3F0000u
12578 #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT          16
12579 #define ECSPI_DMAREG_RX_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_THRESHOLD_SHIFT))&ECSPI_DMAREG_RX_THRESHOLD_MASK)
12580 #define ECSPI_DMAREG_RXDEN_MASK                  0x800000u
12581 #define ECSPI_DMAREG_RXDEN_SHIFT                 23
12582 #define ECSPI_DMAREG_RX_DMA_LENGTH_MASK          0x3F000000u
12583 #define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT         24
12584 #define ECSPI_DMAREG_RX_DMA_LENGTH(x)            (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT))&ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
12585 #define ECSPI_DMAREG_RXTDEN_MASK                 0x80000000u
12586 #define ECSPI_DMAREG_RXTDEN_SHIFT                31
12587 /* STATREG Bit Fields */
12588 #define ECSPI_STATREG_TE_MASK                    0x1u
12589 #define ECSPI_STATREG_TE_SHIFT                   0
12590 #define ECSPI_STATREG_TDR_MASK                   0x2u
12591 #define ECSPI_STATREG_TDR_SHIFT                  1
12592 #define ECSPI_STATREG_TF_MASK                    0x4u
12593 #define ECSPI_STATREG_TF_SHIFT                   2
12594 #define ECSPI_STATREG_RR_MASK                    0x8u
12595 #define ECSPI_STATREG_RR_SHIFT                   3
12596 #define ECSPI_STATREG_RDR_MASK                   0x10u
12597 #define ECSPI_STATREG_RDR_SHIFT                  4
12598 #define ECSPI_STATREG_RF_MASK                    0x20u
12599 #define ECSPI_STATREG_RF_SHIFT                   5
12600 #define ECSPI_STATREG_RO_MASK                    0x40u
12601 #define ECSPI_STATREG_RO_SHIFT                   6
12602 #define ECSPI_STATREG_TC_MASK                    0x80u
12603 #define ECSPI_STATREG_TC_SHIFT                   7
12604 /* PERIODREG Bit Fields */
12605 #define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK       0x7FFFu
12606 #define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT      0
12607 #define ECSPI_PERIODREG_SAMPLE_PERIOD(x)         (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT))&ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
12608 #define ECSPI_PERIODREG_CSRC_MASK                0x8000u
12609 #define ECSPI_PERIODREG_CSRC_SHIFT               15
12610 #define ECSPI_PERIODREG_CSD_CTL_MASK             0x3F0000u
12611 #define ECSPI_PERIODREG_CSD_CTL_SHIFT            16
12612 #define ECSPI_PERIODREG_CSD_CTL(x)               (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_CSD_CTL_SHIFT))&ECSPI_PERIODREG_CSD_CTL_MASK)
12613 /* TESTREG Bit Fields */
12614 #define ECSPI_TESTREG_TXCNT_MASK                 0x7Fu
12615 #define ECSPI_TESTREG_TXCNT_SHIFT                0
12616 #define ECSPI_TESTREG_TXCNT(x)                   (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_TXCNT_SHIFT))&ECSPI_TESTREG_TXCNT_MASK)
12617 #define ECSPI_TESTREG_RXCNT_MASK                 0x7F00u
12618 #define ECSPI_TESTREG_RXCNT_SHIFT                8
12619 #define ECSPI_TESTREG_RXCNT(x)                   (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_RXCNT_SHIFT))&ECSPI_TESTREG_RXCNT_MASK)
12620 #define ECSPI_TESTREG_LBC_MASK                   0x80000000u
12621 #define ECSPI_TESTREG_LBC_SHIFT                  31
12622 /* MSGDATA Bit Fields */
12623 #define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK         0xFFFFFFFFu
12624 #define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT        0
12625 #define ECSPI_MSGDATA_ECSPI_MSGDATA(x)           (((uint32_t)(((uint32_t)(x))<<ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT))&ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
12626 
12627 /*!
12628  * @}
12629  */ /* end of group ECSPI_Register_Masks */
12630 
12631 /* ECSPI - Peripheral instance base addresses */
12632 /** Peripheral ECSPI1 base address */
12633 #define ECSPI1_BASE                              (0x30820000u)
12634 /** Peripheral ECSPI1 base pointer */
12635 #define ECSPI1                                   ((ECSPI_Type *)ECSPI1_BASE)
12636 #define ECSPI1_BASE_PTR                          (ECSPI1)
12637 /** Peripheral ECSPI2 base address */
12638 #define ECSPI2_BASE                              (0x30830000u)
12639 /** Peripheral ECSPI2 base pointer */
12640 #define ECSPI2                                   ((ECSPI_Type *)ECSPI2_BASE)
12641 #define ECSPI2_BASE_PTR                          (ECSPI2)
12642 /** Peripheral ECSPI3 base address */
12643 #define ECSPI3_BASE                              (0x30840000u)
12644 /** Peripheral ECSPI3 base pointer */
12645 #define ECSPI3                                   ((ECSPI_Type *)ECSPI3_BASE)
12646 #define ECSPI3_BASE_PTR                          (ECSPI3)
12647 /** Peripheral ECSPI4 base address */
12648 #define ECSPI4_BASE                              (0x30630000u)
12649 /** Peripheral ECSPI4 base pointer */
12650 #define ECSPI4                                   ((ECSPI_Type *)ECSPI4_BASE)
12651 #define ECSPI4_BASE_PTR                          (ECSPI4)
12652 /** Array initializer of ECSPI peripheral base addresses */
12653 #define ECSPI_BASE_ADDRS                         { ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE }
12654 /** Array initializer of ECSPI peripheral base pointers */
12655 #define ECSPI_BASE_PTRS                          { ECSPI1, ECSPI2, ECSPI3, ECSPI4 }
12656 /** Interrupt vectors for the ECSPI peripheral type */
12657 #define ECSPI_IRQS                               { eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn }
12658 /* ----------------------------------------------------------------------------
12659    -- ECSPI - Register accessor macros
12660    ---------------------------------------------------------------------------- */
12661 
12662 /*!
12663  * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros
12664  * @{
12665  */
12666 
12667 
12668 /* ECSPI - Register instance definitions */
12669 /* ECSPI1 */
12670 #define ECSPI1_RXDATA                            ECSPI_RXDATA_REG(ECSPI1_BASE_PTR)
12671 #define ECSPI1_TXDATA                            ECSPI_TXDATA_REG(ECSPI1_BASE_PTR)
12672 #define ECSPI1_CONREG                            ECSPI_CONREG_REG(ECSPI1_BASE_PTR)
12673 #define ECSPI1_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI1_BASE_PTR)
12674 #define ECSPI1_INTREG                            ECSPI_INTREG_REG(ECSPI1_BASE_PTR)
12675 #define ECSPI1_DMAREG                            ECSPI_DMAREG_REG(ECSPI1_BASE_PTR)
12676 #define ECSPI1_STATREG                           ECSPI_STATREG_REG(ECSPI1_BASE_PTR)
12677 #define ECSPI1_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI1_BASE_PTR)
12678 #define ECSPI1_TESTREG                           ECSPI_TESTREG_REG(ECSPI1_BASE_PTR)
12679 #define ECSPI1_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI1_BASE_PTR)
12680 /* ECSPI2 */
12681 #define ECSPI2_RXDATA                            ECSPI_RXDATA_REG(ECSPI2_BASE_PTR)
12682 #define ECSPI2_TXDATA                            ECSPI_TXDATA_REG(ECSPI2_BASE_PTR)
12683 #define ECSPI2_CONREG                            ECSPI_CONREG_REG(ECSPI2_BASE_PTR)
12684 #define ECSPI2_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI2_BASE_PTR)
12685 #define ECSPI2_INTREG                            ECSPI_INTREG_REG(ECSPI2_BASE_PTR)
12686 #define ECSPI2_DMAREG                            ECSPI_DMAREG_REG(ECSPI2_BASE_PTR)
12687 #define ECSPI2_STATREG                           ECSPI_STATREG_REG(ECSPI2_BASE_PTR)
12688 #define ECSPI2_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI2_BASE_PTR)
12689 #define ECSPI2_TESTREG                           ECSPI_TESTREG_REG(ECSPI2_BASE_PTR)
12690 #define ECSPI2_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI2_BASE_PTR)
12691 /* ECSPI3 */
12692 #define ECSPI3_RXDATA                            ECSPI_RXDATA_REG(ECSPI3_BASE_PTR)
12693 #define ECSPI3_TXDATA                            ECSPI_TXDATA_REG(ECSPI3_BASE_PTR)
12694 #define ECSPI3_CONREG                            ECSPI_CONREG_REG(ECSPI3_BASE_PTR)
12695 #define ECSPI3_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI3_BASE_PTR)
12696 #define ECSPI3_INTREG                            ECSPI_INTREG_REG(ECSPI3_BASE_PTR)
12697 #define ECSPI3_DMAREG                            ECSPI_DMAREG_REG(ECSPI3_BASE_PTR)
12698 #define ECSPI3_STATREG                           ECSPI_STATREG_REG(ECSPI3_BASE_PTR)
12699 #define ECSPI3_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI3_BASE_PTR)
12700 #define ECSPI3_TESTREG                           ECSPI_TESTREG_REG(ECSPI3_BASE_PTR)
12701 #define ECSPI3_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI3_BASE_PTR)
12702 /* ECSPI4 */
12703 #define ECSPI4_RXDATA                            ECSPI_RXDATA_REG(ECSPI4_BASE_PTR)
12704 #define ECSPI4_TXDATA                            ECSPI_TXDATA_REG(ECSPI4_BASE_PTR)
12705 #define ECSPI4_CONREG                            ECSPI_CONREG_REG(ECSPI4_BASE_PTR)
12706 #define ECSPI4_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI4_BASE_PTR)
12707 #define ECSPI4_INTREG                            ECSPI_INTREG_REG(ECSPI4_BASE_PTR)
12708 #define ECSPI4_DMAREG                            ECSPI_DMAREG_REG(ECSPI4_BASE_PTR)
12709 #define ECSPI4_STATREG                           ECSPI_STATREG_REG(ECSPI4_BASE_PTR)
12710 #define ECSPI4_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI4_BASE_PTR)
12711 #define ECSPI4_TESTREG                           ECSPI_TESTREG_REG(ECSPI4_BASE_PTR)
12712 #define ECSPI4_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI4_BASE_PTR)
12713 /*!
12714  * @}
12715  */ /* end of group ECSPI_Register_Accessor_Macros */
12716 
12717 
12718 /*!
12719  * @}
12720  */ /* end of group ECSPI_Peripheral */
12721 
12722 /* ----------------------------------------------------------------------------
12723    -- EIM Peripheral Access Layer
12724    ---------------------------------------------------------------------------- */
12725 
12726 /*!
12727  * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
12728  * @{
12729  */
12730 
12731 /** EIM - Register Layout Typedef */
12732 typedef struct {
12733   struct {                                         /* offset: 0x0, array step: 0x18 */
12734   __IO    uint32_t CSGCR1;                                 /**< Chip Select n General Configuration Register 1, array offset: 0x0, array step: 0x18 */
12735   __IO    uint32_t CSGCR2;                                 /**< Chip Select n General Configuration Register 2, array offset: 0x4, array step: 0x18 */
12736   __IO    uint32_t CSRCR1;                                 /**< Chip Select n Read Configuration Register 1, array offset: 0x8, array step: 0x18 */
12737   __IO    uint32_t CSRCR2;                                 /**< Chip Select n Read Configuration Register 2, array offset: 0xC, array step: 0x18 */
12738   __IO    uint32_t CSWCR1;                                 /**< Chip Select n Write Configuration Register 1, array offset: 0x10, array step: 0x18 */
12739   __IO    uint32_t CSWCR2;                                 /**< Chip Select n Write Configuration Register 2, array offset: 0x14, array step: 0x18 */
12740  } CS[6];
12741   __IO  uint32_t WCR;                                    /**< EIM Configuration Register, offset: 0x90 */
12742   __IO  uint32_t DCR;                                    /**< DLL Control Register, offset: 0x94 */
12743   __I   uint32_t DSR;                                    /**< DLL Status Register, offset: 0x98 */
12744   __IO  uint32_t WIAR;                                   /**< EIM IP Access Register, offset: 0x9C */
12745   __IO  uint32_t EAR;                                    /**< Error Address Register, offset: 0xA0 */
12746 } EIM_Type, *EIM_MemMapPtr;
12747 /* ----------------------------------------------------------------------------
12748    -- EIM - Register accessor macros
12749    ---------------------------------------------------------------------------- */
12750 
12751 /*!
12752  * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros
12753  * @{
12754  */
12755 
12756 
12757 /* EIM - Register accessors */
12758 #define EIM_CSGCR1_REG(base,index)               ((base)->CS[index].CSGCR1)
12759 #define EIM_CSGCR2_REG(base,index)               ((base)->CS[index].CSGCR2)
12760 #define EIM_CSRCR1_REG(base,index)               ((base)->CS[index].CSRCR1)
12761 #define EIM_CSRCR2_REG(base,index)               ((base)->CS[index].CSRCR2)
12762 #define EIM_CSWCR1_REG(base,index)               ((base)->CS[index].CSWCR1)
12763 #define EIM_CSWCR2_REG(base,index)               ((base)->CS[index].CSWCR2)
12764 #define EIM_WCR_REG(base)                        ((base)->WCR)
12765 #define EIM_DCR_REG(base)                        ((base)->DCR)
12766 #define EIM_DSR_REG(base)                        ((base)->DSR)
12767 #define EIM_WIAR_REG(base)                       ((base)->WIAR)
12768 #define EIM_EAR_REG(base)                        ((base)->EAR)
12769 
12770 /*!
12771  * @}
12772  */ /* end of group EIM_Register_Accessor_Macros */
12773 /* ----------------------------------------------------------------------------
12774    -- EIM Register Masks
12775    ---------------------------------------------------------------------------- */
12776 
12777 /*!
12778  * @addtogroup EIM_Register_Masks EIM Register Masks
12779  * @{
12780  */
12781 
12782 /* CSGCR1 Bit Fields */
12783 #define EIM_CSGCR1_CSEN_MASK                     0x1u
12784 #define EIM_CSGCR1_CSEN_SHIFT                    0
12785 #define EIM_CSGCR1_SWR_MASK                      0x2u
12786 #define EIM_CSGCR1_SWR_SHIFT                     1
12787 #define EIM_CSGCR1_SRD_MASK                      0x4u
12788 #define EIM_CSGCR1_SRD_SHIFT                     2
12789 #define EIM_CSGCR1_MUM_MASK                      0x8u
12790 #define EIM_CSGCR1_MUM_SHIFT                     3
12791 #define EIM_CSGCR1_WFL_MASK                      0x10u
12792 #define EIM_CSGCR1_WFL_SHIFT                     4
12793 #define EIM_CSGCR1_RFL_MASK                      0x20u
12794 #define EIM_CSGCR1_RFL_SHIFT                     5
12795 #define EIM_CSGCR1_CRE_MASK                      0x40u
12796 #define EIM_CSGCR1_CRE_SHIFT                     6
12797 #define EIM_CSGCR1_CREP_MASK                     0x80u
12798 #define EIM_CSGCR1_CREP_SHIFT                    7
12799 #define EIM_CSGCR1_BL_MASK                       0x700u
12800 #define EIM_CSGCR1_BL_SHIFT                      8
12801 #define EIM_CSGCR1_BL(x)                         (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BL_SHIFT))&EIM_CSGCR1_BL_MASK)
12802 #define EIM_CSGCR1_WC_MASK                       0x800u
12803 #define EIM_CSGCR1_WC_SHIFT                      11
12804 #define EIM_CSGCR1_BCD_MASK                      0x3000u
12805 #define EIM_CSGCR1_BCD_SHIFT                     12
12806 #define EIM_CSGCR1_BCD(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCD_SHIFT))&EIM_CSGCR1_BCD_MASK)
12807 #define EIM_CSGCR1_BCS_MASK                      0xC000u
12808 #define EIM_CSGCR1_BCS_SHIFT                     14
12809 #define EIM_CSGCR1_BCS(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCS_SHIFT))&EIM_CSGCR1_BCS_MASK)
12810 #define EIM_CSGCR1_DSZ_MASK                      0x70000u
12811 #define EIM_CSGCR1_DSZ_SHIFT                     16
12812 #define EIM_CSGCR1_DSZ(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_DSZ_SHIFT))&EIM_CSGCR1_DSZ_MASK)
12813 #define EIM_CSGCR1_SP_MASK                       0x80000u
12814 #define EIM_CSGCR1_SP_SHIFT                      19
12815 #define EIM_CSGCR1_CSREC_MASK                    0x700000u
12816 #define EIM_CSGCR1_CSREC_SHIFT                   20
12817 #define EIM_CSGCR1_CSREC(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_CSREC_SHIFT))&EIM_CSGCR1_CSREC_MASK)
12818 #define EIM_CSGCR1_AUS_MASK                      0x800000u
12819 #define EIM_CSGCR1_AUS_SHIFT                     23
12820 #define EIM_CSGCR1_GBC_MASK                      0x7000000u
12821 #define EIM_CSGCR1_GBC_SHIFT                     24
12822 #define EIM_CSGCR1_GBC(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_GBC_SHIFT))&EIM_CSGCR1_GBC_MASK)
12823 #define EIM_CSGCR1_WP_MASK                       0x8000000u
12824 #define EIM_CSGCR1_WP_SHIFT                      27
12825 #define EIM_CSGCR1_PSZ_MASK                      0xF0000000u
12826 #define EIM_CSGCR1_PSZ_SHIFT                     28
12827 #define EIM_CSGCR1_PSZ(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_PSZ_SHIFT))&EIM_CSGCR1_PSZ_MASK)
12828 /* CSGCR2 Bit Fields */
12829 #define EIM_CSGCR2_ADH_MASK                      0x3u
12830 #define EIM_CSGCR2_ADH_SHIFT                     0
12831 #define EIM_CSGCR2_ADH(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_ADH_SHIFT))&EIM_CSGCR2_ADH_MASK)
12832 #define EIM_CSGCR2_DAPS_MASK                     0xF0u
12833 #define EIM_CSGCR2_DAPS_SHIFT                    4
12834 #define EIM_CSGCR2_DAPS(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_DAPS_SHIFT))&EIM_CSGCR2_DAPS_MASK)
12835 #define EIM_CSGCR2_DAE_MASK                      0x100u
12836 #define EIM_CSGCR2_DAE_SHIFT                     8
12837 #define EIM_CSGCR2_DAP_MASK                      0x200u
12838 #define EIM_CSGCR2_DAP_SHIFT                     9
12839 #define EIM_CSGCR2_MUX16_BYP_GRANT_MASK          0x1000u
12840 #define EIM_CSGCR2_MUX16_BYP_GRANT_SHIFT         12
12841 /* CSRCR1 Bit Fields */
12842 #define EIM_CSRCR1_RCSN_MASK                     0x7u
12843 #define EIM_CSRCR1_RCSN_SHIFT                    0
12844 #define EIM_CSRCR1_RCSN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSN_SHIFT))&EIM_CSRCR1_RCSN_MASK)
12845 #define EIM_CSRCR1_RCSA_MASK                     0x70u
12846 #define EIM_CSRCR1_RCSA_SHIFT                    4
12847 #define EIM_CSRCR1_RCSA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSA_SHIFT))&EIM_CSRCR1_RCSA_MASK)
12848 #define EIM_CSRCR1_OEN_MASK                      0x700u
12849 #define EIM_CSRCR1_OEN_SHIFT                     8
12850 #define EIM_CSRCR1_OEN(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEN_SHIFT))&EIM_CSRCR1_OEN_MASK)
12851 #define EIM_CSRCR1_OEA_MASK                      0x7000u
12852 #define EIM_CSRCR1_OEA_SHIFT                     12
12853 #define EIM_CSRCR1_OEA(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEA_SHIFT))&EIM_CSRCR1_OEA_MASK)
12854 #define EIM_CSRCR1_RADVN_MASK                    0x70000u
12855 #define EIM_CSRCR1_RADVN_SHIFT                   16
12856 #define EIM_CSRCR1_RADVN(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVN_SHIFT))&EIM_CSRCR1_RADVN_MASK)
12857 #define EIM_CSRCR1_RAL_MASK                      0x80000u
12858 #define EIM_CSRCR1_RAL_SHIFT                     19
12859 #define EIM_CSRCR1_RADVA_MASK                    0x700000u
12860 #define EIM_CSRCR1_RADVA_SHIFT                   20
12861 #define EIM_CSRCR1_RADVA(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVA_SHIFT))&EIM_CSRCR1_RADVA_MASK)
12862 #define EIM_CSRCR1_RWSC_MASK                     0x3F000000u
12863 #define EIM_CSRCR1_RWSC_SHIFT                    24
12864 #define EIM_CSRCR1_RWSC(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RWSC_SHIFT))&EIM_CSRCR1_RWSC_MASK)
12865 /* CSRCR2 Bit Fields */
12866 #define EIM_CSRCR2_RBEN_MASK                     0x7u
12867 #define EIM_CSRCR2_RBEN_SHIFT                    0
12868 #define EIM_CSRCR2_RBEN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEN_SHIFT))&EIM_CSRCR2_RBEN_MASK)
12869 #define EIM_CSRCR2_RBE_MASK                      0x8u
12870 #define EIM_CSRCR2_RBE_SHIFT                     3
12871 #define EIM_CSRCR2_RBEA_MASK                     0x70u
12872 #define EIM_CSRCR2_RBEA_SHIFT                    4
12873 #define EIM_CSRCR2_RBEA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEA_SHIFT))&EIM_CSRCR2_RBEA_MASK)
12874 #define EIM_CSRCR2_RL_MASK                       0x300u
12875 #define EIM_CSRCR2_RL_SHIFT                      8
12876 #define EIM_CSRCR2_RL(x)                         (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RL_SHIFT))&EIM_CSRCR2_RL_MASK)
12877 #define EIM_CSRCR2_PAT_MASK                      0x7000u
12878 #define EIM_CSRCR2_PAT_SHIFT                     12
12879 #define EIM_CSRCR2_PAT(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_PAT_SHIFT))&EIM_CSRCR2_PAT_MASK)
12880 #define EIM_CSRCR2_APR_MASK                      0x8000u
12881 #define EIM_CSRCR2_APR_SHIFT                     15
12882 /* CSWCR1 Bit Fields */
12883 #define EIM_CSWCR1_WCSN_MASK                     0x7u
12884 #define EIM_CSWCR1_WCSN_SHIFT                    0
12885 #define EIM_CSWCR1_WCSN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSN_SHIFT))&EIM_CSWCR1_WCSN_MASK)
12886 #define EIM_CSWCR1_WCSA_MASK                     0x38u
12887 #define EIM_CSWCR1_WCSA_SHIFT                    3
12888 #define EIM_CSWCR1_WCSA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSA_SHIFT))&EIM_CSWCR1_WCSA_MASK)
12889 #define EIM_CSWCR1_WEN_MASK                      0x1C0u
12890 #define EIM_CSWCR1_WEN_SHIFT                     6
12891 #define EIM_CSWCR1_WEN(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEN_SHIFT))&EIM_CSWCR1_WEN_MASK)
12892 #define EIM_CSWCR1_WEA_MASK                      0xE00u
12893 #define EIM_CSWCR1_WEA_SHIFT                     9
12894 #define EIM_CSWCR1_WEA(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEA_SHIFT))&EIM_CSWCR1_WEA_MASK)
12895 #define EIM_CSWCR1_WBEN_MASK                     0x7000u
12896 #define EIM_CSWCR1_WBEN_SHIFT                    12
12897 #define EIM_CSWCR1_WBEN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEN_SHIFT))&EIM_CSWCR1_WBEN_MASK)
12898 #define EIM_CSWCR1_WBEA_MASK                     0x38000u
12899 #define EIM_CSWCR1_WBEA_SHIFT                    15
12900 #define EIM_CSWCR1_WBEA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEA_SHIFT))&EIM_CSWCR1_WBEA_MASK)
12901 #define EIM_CSWCR1_WADVN_MASK                    0x1C0000u
12902 #define EIM_CSWCR1_WADVN_SHIFT                   18
12903 #define EIM_CSWCR1_WADVN(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVN_SHIFT))&EIM_CSWCR1_WADVN_MASK)
12904 #define EIM_CSWCR1_WADVA_MASK                    0xE00000u
12905 #define EIM_CSWCR1_WADVA_SHIFT                   21
12906 #define EIM_CSWCR1_WADVA(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVA_SHIFT))&EIM_CSWCR1_WADVA_MASK)
12907 #define EIM_CSWCR1_WWSC_MASK                     0x3F000000u
12908 #define EIM_CSWCR1_WWSC_SHIFT                    24
12909 #define EIM_CSWCR1_WWSC(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WWSC_SHIFT))&EIM_CSWCR1_WWSC_MASK)
12910 #define EIM_CSWCR1_WBED_MASK                     0x40000000u
12911 #define EIM_CSWCR1_WBED_SHIFT                    30
12912 #define EIM_CSWCR1_WAL_MASK                      0x80000000u
12913 #define EIM_CSWCR1_WAL_SHIFT                     31
12914 /* CSWCR2 Bit Fields */
12915 #define EIM_CSWCR2_WBCDD_MASK                    0x1u
12916 #define EIM_CSWCR2_WBCDD_SHIFT                   0
12917 /* WCR Bit Fields */
12918 #define EIM_WCR_BCM_MASK                         0x1u
12919 #define EIM_WCR_BCM_SHIFT                        0
12920 #define EIM_WCR_GBCD_MASK                        0x6u
12921 #define EIM_WCR_GBCD_SHIFT                       1
12922 #define EIM_WCR_GBCD(x)                          (((uint32_t)(((uint32_t)(x))<<EIM_WCR_GBCD_SHIFT))&EIM_WCR_GBCD_MASK)
12923 #define EIM_WCR_CONT_BCLK_SEL_MASK               0x8u
12924 #define EIM_WCR_CONT_BCLK_SEL_SHIFT              3
12925 #define EIM_WCR_INTEN_MASK                       0x10u
12926 #define EIM_WCR_INTEN_SHIFT                      4
12927 #define EIM_WCR_INTPOL_MASK                      0x20u
12928 #define EIM_WCR_INTPOL_SHIFT                     5
12929 #define EIM_WCR_WDOG_EN_MASK                     0x100u
12930 #define EIM_WCR_WDOG_EN_SHIFT                    8
12931 #define EIM_WCR_WDOG_LIMIT_MASK                  0x600u
12932 #define EIM_WCR_WDOG_LIMIT_SHIFT                 9
12933 #define EIM_WCR_WDOG_LIMIT(x)                    (((uint32_t)(((uint32_t)(x))<<EIM_WCR_WDOG_LIMIT_SHIFT))&EIM_WCR_WDOG_LIMIT_MASK)
12934 #define EIM_WCR_FRUN_ACLK_EN_MASK                0x800u
12935 #define EIM_WCR_FRUN_ACLK_EN_SHIFT               11
12936 /* DCR Bit Fields */
12937 #define EIM_DCR_DLL_CTRL_ENABLE_MASK             0x1u
12938 #define EIM_DCR_DLL_CTRL_ENABLE_SHIFT            0
12939 #define EIM_DCR_DLL_CTRL_RESET_MASK              0x2u
12940 #define EIM_DCR_DLL_CTRL_RESET_SHIFT             1
12941 #define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_MASK      0x4u
12942 #define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_SHIFT     2
12943 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_MASK     0x8u
12944 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_SHIFT    3
12945 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK         0x70u
12946 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT        4
12947 #define EIM_DCR_DLL_CTRL_SLV_OFFSET(x)           (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK)
12948 #define EIM_DCR_DLL_CTRL_GATE_UPDATE_MASK        0x80u
12949 #define EIM_DCR_DLL_CTRL_GATE_UPDATE_SHIFT       7
12950 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_MASK       0x100u
12951 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_SHIFT      8
12952 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK   0xFE00u
12953 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT  9
12954 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL(x)     (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
12955 #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK    0x7F0000u
12956 #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT   16
12957 #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL(x)      (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT))&EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK)
12958 #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK     0xF800000u
12959 #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT    23
12960 #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT(x)       (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK)
12961 #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK     0xF0000000u
12962 #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT    28
12963 #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT(x)       (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK)
12964 /* DSR Bit Fields */
12965 #define EIM_DSR_DLL_STS_SLV_LOCK_MASK            0x1u
12966 #define EIM_DSR_DLL_STS_SLV_LOCK_SHIFT           0
12967 #define EIM_DSR_DLL_STS_REF_LOCK_MASK            0x2u
12968 #define EIM_DSR_DLL_STS_REF_LOCK_SHIFT           1
12969 #define EIM_DSR_DLL_STS_SLV_SEL_MASK             0x1FCu
12970 #define EIM_DSR_DLL_STS_SLV_SEL_SHIFT            2
12971 #define EIM_DSR_DLL_STS_SLV_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_SLV_SEL_SHIFT))&EIM_DSR_DLL_STS_SLV_SEL_MASK)
12972 #define EIM_DSR_DLL_STS_REF_SEL_MASK             0xFE00u
12973 #define EIM_DSR_DLL_STS_REF_SEL_SHIFT            9
12974 #define EIM_DSR_DLL_STS_REF_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_REF_SEL_SHIFT))&EIM_DSR_DLL_STS_REF_SEL_MASK)
12975 /* WIAR Bit Fields */
12976 #define EIM_WIAR_IPS_REQ_MASK                    0x1u
12977 #define EIM_WIAR_IPS_REQ_SHIFT                   0
12978 #define EIM_WIAR_IPS_ACK_MASK                    0x2u
12979 #define EIM_WIAR_IPS_ACK_SHIFT                   1
12980 #define EIM_WIAR_INT_MASK                        0x4u
12981 #define EIM_WIAR_INT_SHIFT                       2
12982 #define EIM_WIAR_ERRST_MASK                      0x8u
12983 #define EIM_WIAR_ERRST_SHIFT                     3
12984 #define EIM_WIAR_ACLK_EN_MASK                    0x10u
12985 #define EIM_WIAR_ACLK_EN_SHIFT                   4
12986 /* EAR Bit Fields */
12987 #define EIM_EAR_Error_ADDR_MASK                  0xFFFFFFFFu
12988 #define EIM_EAR_Error_ADDR_SHIFT                 0
12989 #define EIM_EAR_Error_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<EIM_EAR_Error_ADDR_SHIFT))&EIM_EAR_Error_ADDR_MASK)
12990 
12991 /*!
12992  * @}
12993  */ /* end of group EIM_Register_Masks */
12994 
12995 /* EIM - Peripheral instance base addresses */
12996 /** Peripheral EIM base address */
12997 #define EIM_BASE                                 (0x30BC0000u)
12998 /** Peripheral EIM base pointer */
12999 #define EIM                                      ((EIM_Type *)EIM_BASE)
13000 #define EIM_BASE_PTR                             (EIM)
13001 /** Array initializer of EIM peripheral base addresses */
13002 #define EIM_BASE_ADDRS                           { EIM_BASE }
13003 /** Array initializer of EIM peripheral base pointers */
13004 #define EIM_BASE_PTRS                            { EIM }
13005 /** Interrupt vectors for the EIM peripheral type */
13006 #define EIM_IRQS                                 { EIM_IRQn }
13007 /* ----------------------------------------------------------------------------
13008    -- EIM - Register accessor macros
13009    ---------------------------------------------------------------------------- */
13010 
13011 /*!
13012  * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros
13013  * @{
13014  */
13015 
13016 
13017 /* EIM - Register instance definitions */
13018 /* EIM */
13019 #define EIM_CS0GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,0)
13020 #define EIM_CS0GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,0)
13021 #define EIM_CS0RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,0)
13022 #define EIM_CS0RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,0)
13023 #define EIM_CS0WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,0)
13024 #define EIM_CS0WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,0)
13025 #define EIM_CS1GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,1)
13026 #define EIM_CS1GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,1)
13027 #define EIM_CS1RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,1)
13028 #define EIM_CS1RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,1)
13029 #define EIM_CS1WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,1)
13030 #define EIM_CS1WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,1)
13031 #define EIM_CS2GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,2)
13032 #define EIM_CS2GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,2)
13033 #define EIM_CS2RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,2)
13034 #define EIM_CS2RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,2)
13035 #define EIM_CS2WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,2)
13036 #define EIM_CS2WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,2)
13037 #define EIM_CS3GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,3)
13038 #define EIM_CS3GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,3)
13039 #define EIM_CS3RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,3)
13040 #define EIM_CS3RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,3)
13041 #define EIM_CS3WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,3)
13042 #define EIM_CS3WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,3)
13043 #define EIM_CS4GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,4)
13044 #define EIM_CS4GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,4)
13045 #define EIM_CS4RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,4)
13046 #define EIM_CS4RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,4)
13047 #define EIM_CS4WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,4)
13048 #define EIM_CS4WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,4)
13049 #define EIM_CS5GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,5)
13050 #define EIM_CS5GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,5)
13051 #define EIM_CS5RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,5)
13052 #define EIM_CS5RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,5)
13053 #define EIM_CS5WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,5)
13054 #define EIM_CS5WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,5)
13055 #define EIM_WCR                                  EIM_WCR_REG(EIM_BASE_PTR)
13056 #define EIM_DCR                                  EIM_DCR_REG(EIM_BASE_PTR)
13057 #define EIM_DSR                                  EIM_DSR_REG(EIM_BASE_PTR)
13058 #define EIM_WIAR                                 EIM_WIAR_REG(EIM_BASE_PTR)
13059 #define EIM_EAR                                  EIM_EAR_REG(EIM_BASE_PTR)
13060 /* EIM - Register array accessors */
13061 #define EIM_CSGCR1(index)                        EIM_CSGCR1_REG(EIM_BASE_PTR,index)
13062 #define EIM_CSGCR2(index)                        EIM_CSGCR2_REG(EIM_BASE_PTR,index)
13063 #define EIM_CSRCR1(index)                        EIM_CSRCR1_REG(EIM_BASE_PTR,index)
13064 #define EIM_CSRCR2(index)                        EIM_CSRCR2_REG(EIM_BASE_PTR,index)
13065 #define EIM_CSWCR1(index)                        EIM_CSWCR1_REG(EIM_BASE_PTR,index)
13066 #define EIM_CSWCR2(index)                        EIM_CSWCR2_REG(EIM_BASE_PTR,index)
13067 /*!
13068  * @}
13069  */ /* end of group EIM_Register_Accessor_Macros */
13070 
13071 
13072 /*!
13073  * @}
13074  */ /* end of group EIM_Peripheral */
13075 
13076 /* ----------------------------------------------------------------------------
13077    -- ENET Peripheral Access Layer
13078    ---------------------------------------------------------------------------- */
13079 
13080 /*!
13081  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
13082  * @{
13083  */
13084 
13085 /** ENET - Register Layout Typedef */
13086 typedef struct {
13087   uint8_t RESERVED_0[4];
13088   __IO  uint32_t EIR;                                    /**< Interrupt Event Register, offset: 0x4 */
13089   __IO  uint32_t EIMR;                                   /**< Interrupt Mask Register, offset: 0x8 */
13090   uint8_t RESERVED_1[4];
13091   __IO  uint32_t RDAR;                                   /**< Receive Descriptor Active Register, offset: 0x10 */
13092   __IO  uint32_t TDAR;                                   /**< Transmit Descriptor Active Register, offset: 0x14 */
13093   uint8_t RESERVED_2[12];
13094   __IO  uint32_t ECR;                                    /**< Ethernet Control Register, offset: 0x24 */
13095   uint8_t RESERVED_3[24];
13096   __IO  uint32_t MMFR;                                   /**< MII Management Frame Register, offset: 0x40 */
13097   __IO  uint32_t MSCR;                                   /**< MII Speed Control Register, offset: 0x44 */
13098   uint8_t RESERVED_4[28];
13099   __IO  uint32_t MIBC;                                   /**< MIB Control Register, offset: 0x64 */
13100   uint8_t RESERVED_5[28];
13101   __IO  uint32_t RCR;                                    /**< Receive Control Register, offset: 0x84 */
13102   uint8_t RESERVED_6[60];
13103   __IO  uint32_t TCR;                                    /**< Transmit Control Register, offset: 0xC4 */
13104   uint8_t RESERVED_7[28];
13105   __IO  uint32_t PALR;                                   /**< Physical Address Lower Register, offset: 0xE4 */
13106   __IO  uint32_t PAUR;                                   /**< Physical Address Upper Register, offset: 0xE8 */
13107   __IO  uint32_t OPD;                                    /**< Opcode/Pause Duration Register, offset: 0xEC */
13108   __IO  uint32_t TXIC[3];                                /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
13109   uint8_t RESERVED_8[4];
13110   __IO  uint32_t RXIC[3];                                /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
13111   uint8_t RESERVED_9[12];
13112   __IO  uint32_t IAUR;                                   /**< Descriptor Individual Upper Address Register, offset: 0x118 */
13113   __IO  uint32_t IALR;                                   /**< Descriptor Individual Lower Address Register, offset: 0x11C */
13114   __IO  uint32_t GAUR;                                   /**< Descriptor Group Upper Address Register, offset: 0x120 */
13115   __IO  uint32_t GALR;                                   /**< Descriptor Group Lower Address Register, offset: 0x124 */
13116   uint8_t RESERVED_10[28];
13117   __IO  uint32_t TFWR;                                   /**< Transmit FIFO Watermark Register, offset: 0x144 */
13118   uint8_t RESERVED_11[24];
13119   __IO  uint32_t RDSR1;                                  /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
13120   __IO  uint32_t TDSR1;                                  /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
13121   __IO  uint32_t MRBR1;                                  /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
13122   __IO  uint32_t RDSR2;                                  /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
13123   __IO  uint32_t TDSR2;                                  /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
13124   __IO  uint32_t MRBR2;                                  /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
13125   uint8_t RESERVED_12[8];
13126   __IO  uint32_t RDSR;                                   /**< Receive Descriptor Ring , offset: 0x180 */
13127   __IO  uint32_t TDSR;                                   /**< Transmit Buffer Descriptor Ring , offset: 0x184 */
13128   __IO  uint32_t MRBR;                                   /**< Maximum Receive Buffer Size Register, offset: 0x188 */
13129   uint8_t RESERVED_13[4];
13130   __IO  uint32_t RSFL;                                   /**< Receive FIFO Section Full Threshold, offset: 0x190 */
13131   __IO  uint32_t RSEM;                                   /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
13132   __IO  uint32_t RAEM;                                   /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
13133   __IO  uint32_t RAFL;                                   /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
13134   __IO  uint32_t TSEM;                                   /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
13135   __IO  uint32_t TAEM;                                   /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
13136   __IO  uint32_t TAFL;                                   /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
13137   __IO  uint32_t TIPG;                                   /**< Transmit Inter-Packet Gap, offset: 0x1AC */
13138   __IO  uint32_t FTRL;                                   /**< Frame Truncation Length, offset: 0x1B0 */
13139   uint8_t RESERVED_14[12];
13140   __IO  uint32_t TACC;                                   /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
13141   __IO  uint32_t RACC;                                   /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
13142   __IO  uint32_t RCMR[2];                                /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
13143   uint8_t RESERVED_15[8];
13144   __IO  uint32_t DMACFG[2];                              /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
13145   __IO  uint32_t RDAR1;                                  /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
13146   __IO  uint32_t TDAR1;                                  /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
13147   __IO  uint32_t RDAR2;                                  /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
13148   __IO  uint32_t TDAR2;                                  /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
13149   __IO  uint32_t QOS;                                    /**< QOS Scheme, offset: 0x1F0 */
13150   uint8_t RESERVED_16[12];
13151   __I   uint32_t RMON_T_DROP;                            /**< Reserved Statistic Register, offset: 0x200 */
13152   __I   uint32_t RMON_T_PACKETS;                         /**< Tx Packet Count Statistic Register, offset: 0x204 */
13153   __I   uint32_t RMON_T_BC_PKT;                          /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
13154   __I   uint32_t RMON_T_MC_PKT;                          /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
13155   __I   uint32_t RMON_T_CRC_ALIGN;                       /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
13156   __I   uint32_t RMON_T_UNDERSIZE;                       /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
13157   __I   uint32_t RMON_T_OVERSIZE;                        /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
13158   __I   uint32_t RMON_T_FRAG;                            /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
13159   __I   uint32_t RMON_T_JAB;                             /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
13160   __I   uint32_t RMON_T_COL;                             /**< Tx Collision Count Statistic Register, offset: 0x224 */
13161   __I   uint32_t RMON_T_P64;                             /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
13162   __I   uint32_t RMON_T_P65TO127;                        /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
13163   __I   uint32_t RMON_T_P128TO255;                       /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
13164   __I   uint32_t RMON_T_P256TO511;                       /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
13165   __I   uint32_t RMON_T_P512TO1023;                      /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
13166   __I   uint32_t RMON_T_P1024TO2047;                     /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
13167   __I   uint32_t RMON_T_P_GTE2048;                       /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
13168   __I   uint32_t RMON_T_OCTETS;                          /**< Tx Octets Statistic Register, offset: 0x244 */
13169   __I   uint32_t IEEE_T_DROP;                            /**< IEEE_T_DROP Reserved Statistic Register, offset: 0x248 */
13170   __I   uint32_t IEEE_T_FRAME_OK;                        /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
13171   __I   uint32_t IEEE_T_1COL;                            /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
13172   __I   uint32_t IEEE_T_MCOL;                            /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
13173   __I   uint32_t IEEE_T_DEF;                             /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
13174   __I   uint32_t IEEE_T_LCOL;                            /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
13175   __I   uint32_t IEEE_T_EXCOL;                           /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
13176   __I   uint32_t IEEE_T_MACERR;                          /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
13177   __I   uint32_t IEEE_T_CSERR;                           /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
13178   __I   uint32_t IEEE_T_SQE;                             /**< , offset: 0x26C */
13179   __I   uint32_t IEEE_T_FDXFC;                           /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
13180   __I   uint32_t IEEE_T_OCTETS_OK;                       /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
13181   uint8_t RESERVED_17[12];
13182   __I   uint32_t RMON_R_PACKETS;                         /**< Rx Packet Count Statistic Register, offset: 0x284 */
13183   __I   uint32_t RMON_R_BC_PKT;                          /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
13184   __I   uint32_t RMON_R_MC_PKT;                          /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
13185   __I   uint32_t RMON_R_CRC_ALIGN;                       /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
13186   __I   uint32_t RMON_R_UNDERSIZE;                       /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
13187   __I   uint32_t RMON_R_OVERSIZE;                        /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
13188   __I   uint32_t RMON_R_FRAG;                            /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
13189   __I   uint32_t RMON_R_JAB;                             /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
13190   __I   uint32_t RMON_R_RESVD_0;                         /**< Reserved Statistic Register, offset: 0x2A4 */
13191   __I   uint32_t RMON_R_P64;                             /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
13192   __I   uint32_t RMON_R_P65TO127;                        /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
13193   __I   uint32_t RMON_R_P128TO255;                       /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
13194   __I   uint32_t RMON_R_P256TO511;                       /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
13195   __I   uint32_t RMON_R_P512TO1023;                      /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
13196   __I   uint32_t RMON_R_P1024TO2047;                     /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
13197   __I   uint32_t RMON_R_P_GTE2048;                       /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
13198   __I   uint32_t RMON_R_OCTETS;                          /**< Rx Octets Statistic Register, offset: 0x2C4 */
13199   __I   uint32_t IEEE_R_DROP;                            /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
13200   __I   uint32_t IEEE_R_FRAME_OK;                        /**< Frames Received OK Statistic Register, offset: 0x2CC */
13201   __I   uint32_t IEEE_R_CRC;                             /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
13202   __I   uint32_t IEEE_R_ALIGN;                           /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
13203   __I   uint32_t IEEE_R_MACERR;                          /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
13204   __I   uint32_t IEEE_R_FDXFC;                           /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
13205   __I   uint32_t IEEE_R_OCTETS_OK;                       /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
13206   uint8_t RESERVED_18[284];
13207   __IO  uint32_t ATCR;                                   /**< Adjustable Timer Control Register, offset: 0x400 */
13208   __IO  uint32_t ATVR;                                   /**< Timer Value Register, offset: 0x404 */
13209   __IO  uint32_t ATOFF;                                  /**< Timer Offset Register, offset: 0x408 */
13210   __IO  uint32_t ATPER;                                  /**< Timer Period Register, offset: 0x40C */
13211   __IO  uint32_t ATCOR;                                  /**< Timer Correction Register, offset: 0x410 */
13212   __IO  uint32_t ATINC;                                  /**< Time-Stamping Clock Period Register, offset: 0x414 */
13213   __I   uint32_t ATSTMP;                                 /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
13214   uint8_t RESERVED_19[488];
13215   __IO  uint32_t TGSR;                                   /**< Timer Global Status Register, offset: 0x604 */
13216   struct {                                         /* offset: 0x608, array step: 0x8 */
13217   __IO    uint32_t TCSR;                                   /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
13218   __IO    uint32_t TCCR;                                   /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
13219  } TC[4];
13220 } ENET_Type, *ENET_MemMapPtr;
13221 /* ----------------------------------------------------------------------------
13222    -- ENET - Register accessor macros
13223    ---------------------------------------------------------------------------- */
13224 
13225 /*!
13226  * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
13227  * @{
13228  */
13229 
13230 
13231 /* ENET - Register accessors */
13232 #define ENET_EIR_REG(base)                       ((base)->EIR)
13233 #define ENET_EIMR_REG(base)                      ((base)->EIMR)
13234 #define ENET_RDAR_REG(base)                      ((base)->RDAR)
13235 #define ENET_TDAR_REG(base)                      ((base)->TDAR)
13236 #define ENET_ECR_REG(base)                       ((base)->ECR)
13237 #define ENET_MMFR_REG(base)                      ((base)->MMFR)
13238 #define ENET_MSCR_REG(base)                      ((base)->MSCR)
13239 #define ENET_MIBC_REG(base)                      ((base)->MIBC)
13240 #define ENET_RCR_REG(base)                       ((base)->RCR)
13241 #define ENET_TCR_REG(base)                       ((base)->TCR)
13242 #define ENET_PALR_REG(base)                      ((base)->PALR)
13243 #define ENET_PAUR_REG(base)                      ((base)->PAUR)
13244 #define ENET_OPD_REG(base)                       ((base)->OPD)
13245 #define ENET_TXIC_REG(base,index)                ((base)->TXIC[index])
13246 #define ENET_RXIC_REG(base,index)                ((base)->RXIC[index])
13247 #define ENET_IAUR_REG(base)                      ((base)->IAUR)
13248 #define ENET_IALR_REG(base)                      ((base)->IALR)
13249 #define ENET_GAUR_REG(base)                      ((base)->GAUR)
13250 #define ENET_GALR_REG(base)                      ((base)->GALR)
13251 #define ENET_TFWR_REG(base)                      ((base)->TFWR)
13252 #define ENET_RDSR1_REG(base)                     ((base)->RDSR1)
13253 #define ENET_TDSR1_REG(base)                     ((base)->TDSR1)
13254 #define ENET_MRBR1_REG(base)                     ((base)->MRBR1)
13255 #define ENET_RDSR2_REG(base)                     ((base)->RDSR2)
13256 #define ENET_TDSR2_REG(base)                     ((base)->TDSR2)
13257 #define ENET_MRBR2_REG(base)                     ((base)->MRBR2)
13258 #define ENET_RDSR_REG(base)                      ((base)->RDSR)
13259 #define ENET_TDSR_REG(base)                      ((base)->TDSR)
13260 #define ENET_MRBR_REG(base)                      ((base)->MRBR)
13261 #define ENET_RSFL_REG(base)                      ((base)->RSFL)
13262 #define ENET_RSEM_REG(base)                      ((base)->RSEM)
13263 #define ENET_RAEM_REG(base)                      ((base)->RAEM)
13264 #define ENET_RAFL_REG(base)                      ((base)->RAFL)
13265 #define ENET_TSEM_REG(base)                      ((base)->TSEM)
13266 #define ENET_TAEM_REG(base)                      ((base)->TAEM)
13267 #define ENET_TAFL_REG(base)                      ((base)->TAFL)
13268 #define ENET_TIPG_REG(base)                      ((base)->TIPG)
13269 #define ENET_FTRL_REG(base)                      ((base)->FTRL)
13270 #define ENET_TACC_REG(base)                      ((base)->TACC)
13271 #define ENET_RACC_REG(base)                      ((base)->RACC)
13272 #define ENET_RCMR_REG(base,index)                ((base)->RCMR[index])
13273 #define ENET_DMACFG_REG(base,index)              ((base)->DMACFG[index])
13274 #define ENET_RDAR1_REG(base)                     ((base)->RDAR1)
13275 #define ENET_TDAR1_REG(base)                     ((base)->TDAR1)
13276 #define ENET_RDAR2_REG(base)                     ((base)->RDAR2)
13277 #define ENET_TDAR2_REG(base)                     ((base)->TDAR2)
13278 #define ENET_QOS_REG(base)                       ((base)->QOS)
13279 #define ENET_RMON_T_DROP_REG(base)               ((base)->RMON_T_DROP)
13280 #define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
13281 #define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
13282 #define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
13283 #define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
13284 #define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
13285 #define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
13286 #define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
13287 #define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
13288 #define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
13289 #define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
13290 #define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
13291 #define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
13292 #define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
13293 #define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
13294 #define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
13295 #define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
13296 #define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
13297 #define ENET_IEEE_T_DROP_REG(base)               ((base)->IEEE_T_DROP)
13298 #define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
13299 #define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
13300 #define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
13301 #define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
13302 #define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
13303 #define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
13304 #define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
13305 #define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
13306 #define ENET_IEEE_T_SQE_REG(base)                ((base)->IEEE_T_SQE)
13307 #define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
13308 #define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
13309 #define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
13310 #define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
13311 #define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
13312 #define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
13313 #define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
13314 #define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
13315 #define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
13316 #define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
13317 #define ENET_RMON_R_RESVD_0_REG(base)            ((base)->RMON_R_RESVD_0)
13318 #define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
13319 #define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
13320 #define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
13321 #define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
13322 #define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
13323 #define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
13324 #define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
13325 #define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
13326 #define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
13327 #define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
13328 #define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
13329 #define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
13330 #define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
13331 #define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
13332 #define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
13333 #define ENET_ATCR_REG(base)                      ((base)->ATCR)
13334 #define ENET_ATVR_REG(base)                      ((base)->ATVR)
13335 #define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
13336 #define ENET_ATPER_REG(base)                     ((base)->ATPER)
13337 #define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
13338 #define ENET_ATINC_REG(base)                     ((base)->ATINC)
13339 #define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
13340 #define ENET_TGSR_REG(base)                      ((base)->TGSR)
13341 #define ENET_TCSR_REG(base,index)                ((base)->TC[index].TCSR)
13342 #define ENET_TCCR_REG(base,index)                ((base)->TC[index].TCCR)
13343 
13344 /*!
13345  * @}
13346  */ /* end of group ENET_Register_Accessor_Macros */
13347 /* ----------------------------------------------------------------------------
13348    -- ENET Register Masks
13349    ---------------------------------------------------------------------------- */
13350 
13351 /*!
13352  * @addtogroup ENET_Register_Masks ENET Register Masks
13353  * @{
13354  */
13355 
13356 /* EIR Bit Fields */
13357 #define ENET_EIR_RXB1_MASK                       0x1u
13358 #define ENET_EIR_RXB1_SHIFT                      0
13359 #define ENET_EIR_RXF1_MASK                       0x2u
13360 #define ENET_EIR_RXF1_SHIFT                      1
13361 #define ENET_EIR_TXB1_MASK                       0x4u
13362 #define ENET_EIR_TXB1_SHIFT                      2
13363 #define ENET_EIR_TXF1_MASK                       0x8u
13364 #define ENET_EIR_TXF1_SHIFT                      3
13365 #define ENET_EIR_RXB2_MASK                       0x10u
13366 #define ENET_EIR_RXB2_SHIFT                      4
13367 #define ENET_EIR_RXF2_MASK                       0x20u
13368 #define ENET_EIR_RXF2_SHIFT                      5
13369 #define ENET_EIR_TXB2_MASK                       0x40u
13370 #define ENET_EIR_TXB2_SHIFT                      6
13371 #define ENET_EIR_TXF2_MASK                       0x80u
13372 #define ENET_EIR_TXF2_SHIFT                      7
13373 #define ENET_EIR_RXFLUSH_0_MASK                  0x1000u
13374 #define ENET_EIR_RXFLUSH_0_SHIFT                 12
13375 #define ENET_EIR_RXFLUSH_1_MASK                  0x2000u
13376 #define ENET_EIR_RXFLUSH_1_SHIFT                 13
13377 #define ENET_EIR_RXFLUSH_2_MASK                  0x4000u
13378 #define ENET_EIR_RXFLUSH_2_SHIFT                 14
13379 #define ENET_EIR_TS_TIMER_MASK                   0x8000u
13380 #define ENET_EIR_TS_TIMER_SHIFT                  15
13381 #define ENET_EIR_TS_AVAIL_MASK                   0x10000u
13382 #define ENET_EIR_TS_AVAIL_SHIFT                  16
13383 #define ENET_EIR_WAKEUP_MASK                     0x20000u
13384 #define ENET_EIR_WAKEUP_SHIFT                    17
13385 #define ENET_EIR_PLR_MASK                        0x40000u
13386 #define ENET_EIR_PLR_SHIFT                       18
13387 #define ENET_EIR_UN_MASK                         0x80000u
13388 #define ENET_EIR_UN_SHIFT                        19
13389 #define ENET_EIR_RL_MASK                         0x100000u
13390 #define ENET_EIR_RL_SHIFT                        20
13391 #define ENET_EIR_LC_MASK                         0x200000u
13392 #define ENET_EIR_LC_SHIFT                        21
13393 #define ENET_EIR_EBERR_MASK                      0x400000u
13394 #define ENET_EIR_EBERR_SHIFT                     22
13395 #define ENET_EIR_MII_MASK                        0x800000u
13396 #define ENET_EIR_MII_SHIFT                       23
13397 #define ENET_EIR_RXB_MASK                        0x1000000u
13398 #define ENET_EIR_RXB_SHIFT                       24
13399 #define ENET_EIR_RXF_MASK                        0x2000000u
13400 #define ENET_EIR_RXF_SHIFT                       25
13401 #define ENET_EIR_TXB_MASK                        0x4000000u
13402 #define ENET_EIR_TXB_SHIFT                       26
13403 #define ENET_EIR_TXF_MASK                        0x8000000u
13404 #define ENET_EIR_TXF_SHIFT                       27
13405 #define ENET_EIR_GRA_MASK                        0x10000000u
13406 #define ENET_EIR_GRA_SHIFT                       28
13407 #define ENET_EIR_BABT_MASK                       0x20000000u
13408 #define ENET_EIR_BABT_SHIFT                      29
13409 #define ENET_EIR_BABR_MASK                       0x40000000u
13410 #define ENET_EIR_BABR_SHIFT                      30
13411 /* EIMR Bit Fields */
13412 #define ENET_EIMR_RXB1_MASK                      0x1u
13413 #define ENET_EIMR_RXB1_SHIFT                     0
13414 #define ENET_EIMR_RXF1_MASK                      0x2u
13415 #define ENET_EIMR_RXF1_SHIFT                     1
13416 #define ENET_EIMR_TXB1_MASK                      0x4u
13417 #define ENET_EIMR_TXB1_SHIFT                     2
13418 #define ENET_EIMR_TXF1_MASK                      0x8u
13419 #define ENET_EIMR_TXF1_SHIFT                     3
13420 #define ENET_EIMR_RXB2_MASK                      0x10u
13421 #define ENET_EIMR_RXB2_SHIFT                     4
13422 #define ENET_EIMR_RXF2_MASK                      0x20u
13423 #define ENET_EIMR_RXF2_SHIFT                     5
13424 #define ENET_EIMR_TXB2_MASK                      0x40u
13425 #define ENET_EIMR_TXB2_SHIFT                     6
13426 #define ENET_EIMR_TXF2_MASK                      0x80u
13427 #define ENET_EIMR_TXF2_SHIFT                     7
13428 #define ENET_EIMR_RXFLUSH_0_MASK                 0x1000u
13429 #define ENET_EIMR_RXFLUSH_0_SHIFT                12
13430 #define ENET_EIMR_RXFLUSH_1_MASK                 0x2000u
13431 #define ENET_EIMR_RXFLUSH_1_SHIFT                13
13432 #define ENET_EIMR_RXFLUSH_2_MASK                 0x4000u
13433 #define ENET_EIMR_RXFLUSH_2_SHIFT                14
13434 #define ENET_EIMR_TS_TIMER_MASK                  0x8000u
13435 #define ENET_EIMR_TS_TIMER_SHIFT                 15
13436 #define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
13437 #define ENET_EIMR_TS_AVAIL_SHIFT                 16
13438 #define ENET_EIMR_WAKEUP_MASK                    0x20000u
13439 #define ENET_EIMR_WAKEUP_SHIFT                   17
13440 #define ENET_EIMR_PLR_MASK                       0x40000u
13441 #define ENET_EIMR_PLR_SHIFT                      18
13442 #define ENET_EIMR_UN_MASK                        0x80000u
13443 #define ENET_EIMR_UN_SHIFT                       19
13444 #define ENET_EIMR_RL_MASK                        0x100000u
13445 #define ENET_EIMR_RL_SHIFT                       20
13446 #define ENET_EIMR_LC_MASK                        0x200000u
13447 #define ENET_EIMR_LC_SHIFT                       21
13448 #define ENET_EIMR_EBERR_MASK                     0x400000u
13449 #define ENET_EIMR_EBERR_SHIFT                    22
13450 #define ENET_EIMR_MII_MASK                       0x800000u
13451 #define ENET_EIMR_MII_SHIFT                      23
13452 #define ENET_EIMR_RXB_MASK                       0x1000000u
13453 #define ENET_EIMR_RXB_SHIFT                      24
13454 #define ENET_EIMR_RXF_MASK                       0x2000000u
13455 #define ENET_EIMR_RXF_SHIFT                      25
13456 #define ENET_EIMR_TXB_MASK                       0x4000000u
13457 #define ENET_EIMR_TXB_SHIFT                      26
13458 #define ENET_EIMR_TXF_MASK                       0x8000000u
13459 #define ENET_EIMR_TXF_SHIFT                      27
13460 #define ENET_EIMR_GRA_MASK                       0x10000000u
13461 #define ENET_EIMR_GRA_SHIFT                      28
13462 #define ENET_EIMR_BABT_MASK                      0x20000000u
13463 #define ENET_EIMR_BABT_SHIFT                     29
13464 #define ENET_EIMR_BABR_MASK                      0x40000000u
13465 #define ENET_EIMR_BABR_SHIFT                     30
13466 /* RDAR Bit Fields */
13467 #define ENET_RDAR_RDAR_MASK                      0x1000000u
13468 #define ENET_RDAR_RDAR_SHIFT                     24
13469 /* TDAR Bit Fields */
13470 #define ENET_TDAR_TDAR_MASK                      0x1000000u
13471 #define ENET_TDAR_TDAR_SHIFT                     24
13472 /* ECR Bit Fields */
13473 #define ENET_ECR_RESET_MASK                      0x1u
13474 #define ENET_ECR_RESET_SHIFT                     0
13475 #define ENET_ECR_ETHEREN_MASK                    0x2u
13476 #define ENET_ECR_ETHEREN_SHIFT                   1
13477 #define ENET_ECR_MAGICEN_MASK                    0x4u
13478 #define ENET_ECR_MAGICEN_SHIFT                   2
13479 #define ENET_ECR_SLEEP_MASK                      0x8u
13480 #define ENET_ECR_SLEEP_SHIFT                     3
13481 #define ENET_ECR_EN1588_MASK                     0x10u
13482 #define ENET_ECR_EN1588_SHIFT                    4
13483 #define ENET_ECR_SPEED_MASK                      0x20u
13484 #define ENET_ECR_SPEED_SHIFT                     5
13485 #define ENET_ECR_DBGEN_MASK                      0x40u
13486 #define ENET_ECR_DBGEN_SHIFT                     6
13487 #define ENET_ECR_DBSWP_MASK                      0x100u
13488 #define ENET_ECR_DBSWP_SHIFT                     8
13489 #define ENET_ECR_SVLANEN_MASK                    0x200u
13490 #define ENET_ECR_SVLANEN_SHIFT                   9
13491 #define ENET_ECR_VLANUSE2ND_MASK                 0x400u
13492 #define ENET_ECR_VLANUSE2ND_SHIFT                10
13493 #define ENET_ECR_SVLANDBL_MASK                   0x800u
13494 #define ENET_ECR_SVLANDBL_SHIFT                  11
13495 /* MMFR Bit Fields */
13496 #define ENET_MMFR_DATA_MASK                      0xFFFFu
13497 #define ENET_MMFR_DATA_SHIFT                     0
13498 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
13499 #define ENET_MMFR_TA_MASK                        0x30000u
13500 #define ENET_MMFR_TA_SHIFT                       16
13501 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
13502 #define ENET_MMFR_RA_MASK                        0x7C0000u
13503 #define ENET_MMFR_RA_SHIFT                       18
13504 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
13505 #define ENET_MMFR_PA_MASK                        0xF800000u
13506 #define ENET_MMFR_PA_SHIFT                       23
13507 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
13508 #define ENET_MMFR_OP_MASK                        0x30000000u
13509 #define ENET_MMFR_OP_SHIFT                       28
13510 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
13511 #define ENET_MMFR_ST_MASK                        0xC0000000u
13512 #define ENET_MMFR_ST_SHIFT                       30
13513 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
13514 /* MSCR Bit Fields */
13515 #define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
13516 #define ENET_MSCR_MII_SPEED_SHIFT                1
13517 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
13518 #define ENET_MSCR_DIS_PRE_MASK                   0x80u
13519 #define ENET_MSCR_DIS_PRE_SHIFT                  7
13520 #define ENET_MSCR_HOLDTIME_MASK                  0x700u
13521 #define ENET_MSCR_HOLDTIME_SHIFT                 8
13522 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
13523 /* MIBC Bit Fields */
13524 #define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
13525 #define ENET_MIBC_MIB_CLEAR_SHIFT                29
13526 #define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
13527 #define ENET_MIBC_MIB_IDLE_SHIFT                 30
13528 #define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
13529 #define ENET_MIBC_MIB_DIS_SHIFT                  31
13530 /* RCR Bit Fields */
13531 #define ENET_RCR_LOOP_MASK                       0x1u
13532 #define ENET_RCR_LOOP_SHIFT                      0
13533 #define ENET_RCR_DRT_MASK                        0x2u
13534 #define ENET_RCR_DRT_SHIFT                       1
13535 #define ENET_RCR_MII_MODE_MASK                   0x4u
13536 #define ENET_RCR_MII_MODE_SHIFT                  2
13537 #define ENET_RCR_PROM_MASK                       0x8u
13538 #define ENET_RCR_PROM_SHIFT                      3
13539 #define ENET_RCR_BC_REJ_MASK                     0x10u
13540 #define ENET_RCR_BC_REJ_SHIFT                    4
13541 #define ENET_RCR_FCE_MASK                        0x20u
13542 #define ENET_RCR_FCE_SHIFT                       5
13543 #define ENET_RCR_RGMII_EN_MASK                   0x40u
13544 #define ENET_RCR_RGMII_EN_SHIFT                  6
13545 #define ENET_RCR_RMII_MODE_MASK                  0x100u
13546 #define ENET_RCR_RMII_MODE_SHIFT                 8
13547 #define ENET_RCR_RMII_10T_MASK                   0x200u
13548 #define ENET_RCR_RMII_10T_SHIFT                  9
13549 #define ENET_RCR_PADEN_MASK                      0x1000u
13550 #define ENET_RCR_PADEN_SHIFT                     12
13551 #define ENET_RCR_PAUFWD_MASK                     0x2000u
13552 #define ENET_RCR_PAUFWD_SHIFT                    13
13553 #define ENET_RCR_CRCFWD_MASK                     0x4000u
13554 #define ENET_RCR_CRCFWD_SHIFT                    14
13555 #define ENET_RCR_CFEN_MASK                       0x8000u
13556 #define ENET_RCR_CFEN_SHIFT                      15
13557 #define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
13558 #define ENET_RCR_MAX_FL_SHIFT                    16
13559 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
13560 #define ENET_RCR_NLC_MASK                        0x40000000u
13561 #define ENET_RCR_NLC_SHIFT                       30
13562 #define ENET_RCR_GRS_MASK                        0x80000000u
13563 #define ENET_RCR_GRS_SHIFT                       31
13564 /* TCR Bit Fields */
13565 #define ENET_TCR_GTS_MASK                        0x1u
13566 #define ENET_TCR_GTS_SHIFT                       0
13567 #define ENET_TCR_FDEN_MASK                       0x4u
13568 #define ENET_TCR_FDEN_SHIFT                      2
13569 #define ENET_TCR_TFC_PAUSE_MASK                  0x8u
13570 #define ENET_TCR_TFC_PAUSE_SHIFT                 3
13571 #define ENET_TCR_RFC_PAUSE_MASK                  0x10u
13572 #define ENET_TCR_RFC_PAUSE_SHIFT                 4
13573 #define ENET_TCR_ADDSEL_MASK                     0xE0u
13574 #define ENET_TCR_ADDSEL_SHIFT                    5
13575 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
13576 #define ENET_TCR_ADDINS_MASK                     0x100u
13577 #define ENET_TCR_ADDINS_SHIFT                    8
13578 #define ENET_TCR_CRCFWD_MASK                     0x200u
13579 #define ENET_TCR_CRCFWD_SHIFT                    9
13580 /* PALR Bit Fields */
13581 #define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
13582 #define ENET_PALR_PADDR1_SHIFT                   0
13583 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
13584 /* PAUR Bit Fields */
13585 #define ENET_PAUR_TYPE_MASK                      0xFFFFu
13586 #define ENET_PAUR_TYPE_SHIFT                     0
13587 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
13588 #define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
13589 #define ENET_PAUR_PADDR2_SHIFT                   16
13590 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
13591 /* OPD Bit Fields */
13592 #define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
13593 #define ENET_OPD_PAUSE_DUR_SHIFT                 0
13594 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
13595 #define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
13596 #define ENET_OPD_OPCODE_SHIFT                    16
13597 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
13598 /* TXIC Bit Fields */
13599 #define ENET_TXIC_ICTT_MASK                      0xFFFFu
13600 #define ENET_TXIC_ICTT_SHIFT                     0
13601 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICTT_SHIFT))&ENET_TXIC_ICTT_MASK)
13602 #define ENET_TXIC_ICFT_MASK                      0xFF00000u
13603 #define ENET_TXIC_ICFT_SHIFT                     20
13604 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICFT_SHIFT))&ENET_TXIC_ICFT_MASK)
13605 #define ENET_TXIC_ICCS_MASK                      0x40000000u
13606 #define ENET_TXIC_ICCS_SHIFT                     30
13607 #define ENET_TXIC_ICEN_MASK                      0x80000000u
13608 #define ENET_TXIC_ICEN_SHIFT                     31
13609 /* RXIC Bit Fields */
13610 #define ENET_RXIC_ICTT_MASK                      0xFFFFu
13611 #define ENET_RXIC_ICTT_SHIFT                     0
13612 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICTT_SHIFT))&ENET_RXIC_ICTT_MASK)
13613 #define ENET_RXIC_ICFT_MASK                      0xFF00000u
13614 #define ENET_RXIC_ICFT_SHIFT                     20
13615 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICFT_SHIFT))&ENET_RXIC_ICFT_MASK)
13616 #define ENET_RXIC_ICCS_MASK                      0x40000000u
13617 #define ENET_RXIC_ICCS_SHIFT                     30
13618 #define ENET_RXIC_ICEN_MASK                      0x80000000u
13619 #define ENET_RXIC_ICEN_SHIFT                     31
13620 /* IAUR Bit Fields */
13621 #define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
13622 #define ENET_IAUR_IADDR1_SHIFT                   0
13623 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
13624 /* IALR Bit Fields */
13625 #define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
13626 #define ENET_IALR_IADDR2_SHIFT                   0
13627 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
13628 /* GAUR Bit Fields */
13629 #define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
13630 #define ENET_GAUR_GADDR1_SHIFT                   0
13631 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
13632 /* GALR Bit Fields */
13633 #define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
13634 #define ENET_GALR_GADDR2_SHIFT                   0
13635 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
13636 /* TFWR Bit Fields */
13637 #define ENET_TFWR_TFWR_MASK                      0x3Fu
13638 #define ENET_TFWR_TFWR_SHIFT                     0
13639 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
13640 #define ENET_TFWR_STRFWD_MASK                    0x100u
13641 #define ENET_TFWR_STRFWD_SHIFT                   8
13642 /* RDSR1 Bit Fields */
13643 #define ENET_RDSR1_R_DES_START_MASK              0xFFFFFFF8u
13644 #define ENET_RDSR1_R_DES_START_SHIFT             3
13645 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RDSR1_R_DES_START_SHIFT))&ENET_RDSR1_R_DES_START_MASK)
13646 /* TDSR1 Bit Fields */
13647 #define ENET_TDSR1_X_DES_START_MASK              0xFFFFFFF8u
13648 #define ENET_TDSR1_X_DES_START_SHIFT             3
13649 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_TDSR1_X_DES_START_SHIFT))&ENET_TDSR1_X_DES_START_MASK)
13650 /* MRBR1 Bit Fields */
13651 #define ENET_MRBR1_R_BUF_SIZE_MASK               0x7F0u
13652 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              4
13653 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_MRBR1_R_BUF_SIZE_SHIFT))&ENET_MRBR1_R_BUF_SIZE_MASK)
13654 /* RDSR2 Bit Fields */
13655 #define ENET_RDSR2_R_DES_START_MASK              0xFFFFFFF8u
13656 #define ENET_RDSR2_R_DES_START_SHIFT             3
13657 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RDSR2_R_DES_START_SHIFT))&ENET_RDSR2_R_DES_START_MASK)
13658 /* TDSR2 Bit Fields */
13659 #define ENET_TDSR2_X_DES_START_MASK              0xFFFFFFF8u
13660 #define ENET_TDSR2_X_DES_START_SHIFT             3
13661 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_TDSR2_X_DES_START_SHIFT))&ENET_TDSR2_X_DES_START_MASK)
13662 /* MRBR2 Bit Fields */
13663 #define ENET_MRBR2_R_BUF_SIZE_MASK               0x7F0u
13664 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              4
13665 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_MRBR2_R_BUF_SIZE_SHIFT))&ENET_MRBR2_R_BUF_SIZE_MASK)
13666 /* RDSR Bit Fields */
13667 #define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
13668 #define ENET_RDSR_R_DES_START_SHIFT              3
13669 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
13670 /* TDSR Bit Fields */
13671 #define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
13672 #define ENET_TDSR_X_DES_START_SHIFT              3
13673 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
13674 /* MRBR Bit Fields */
13675 #define ENET_MRBR_R_BUF_SIZE_MASK                0x7F0u
13676 #define ENET_MRBR_R_BUF_SIZE_SHIFT               4
13677 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
13678 /* RSFL Bit Fields */
13679 #define ENET_RSFL_RX_SECTION_FULL_MASK           0x3FFu
13680 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
13681 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
13682 /* RSEM Bit Fields */
13683 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          0x3FFu
13684 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
13685 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
13686 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
13687 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
13688 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
13689 /* RAEM Bit Fields */
13690 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0x3FFu
13691 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
13692 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
13693 /* RAFL Bit Fields */
13694 #define ENET_RAFL_RX_ALMOST_FULL_MASK            0x3FFu
13695 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
13696 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
13697 /* TSEM Bit Fields */
13698 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          0x3FFu
13699 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
13700 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
13701 /* TAEM Bit Fields */
13702 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0x3FFu
13703 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
13704 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
13705 /* TAFL Bit Fields */
13706 #define ENET_TAFL_TX_ALMOST_FULL_MASK            0x3FFu
13707 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
13708 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
13709 /* TIPG Bit Fields */
13710 #define ENET_TIPG_IPG_MASK                       0x1Fu
13711 #define ENET_TIPG_IPG_SHIFT                      0
13712 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
13713 /* FTRL Bit Fields */
13714 #define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
13715 #define ENET_FTRL_TRUNC_FL_SHIFT                 0
13716 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
13717 /* TACC Bit Fields */
13718 #define ENET_TACC_SHIFT16_MASK                   0x1u
13719 #define ENET_TACC_SHIFT16_SHIFT                  0
13720 #define ENET_TACC_IPCHK_MASK                     0x8u
13721 #define ENET_TACC_IPCHK_SHIFT                    3
13722 #define ENET_TACC_PROCHK_MASK                    0x10u
13723 #define ENET_TACC_PROCHK_SHIFT                   4
13724 /* RACC Bit Fields */
13725 #define ENET_RACC_PADREM_MASK                    0x1u
13726 #define ENET_RACC_PADREM_SHIFT                   0
13727 #define ENET_RACC_IPDIS_MASK                     0x2u
13728 #define ENET_RACC_IPDIS_SHIFT                    1
13729 #define ENET_RACC_PRODIS_MASK                    0x4u
13730 #define ENET_RACC_PRODIS_SHIFT                   2
13731 #define ENET_RACC_LINEDIS_MASK                   0x40u
13732 #define ENET_RACC_LINEDIS_SHIFT                  6
13733 #define ENET_RACC_SHIFT16_MASK                   0x80u
13734 #define ENET_RACC_SHIFT16_SHIFT                  7
13735 /* RCMR Bit Fields */
13736 #define ENET_RCMR_CMP0_MASK                      0x7u
13737 #define ENET_RCMR_CMP0_SHIFT                     0
13738 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP0_SHIFT))&ENET_RCMR_CMP0_MASK)
13739 #define ENET_RCMR_CMP1_MASK                      0x70u
13740 #define ENET_RCMR_CMP1_SHIFT                     4
13741 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP1_SHIFT))&ENET_RCMR_CMP1_MASK)
13742 #define ENET_RCMR_CMP2_MASK                      0x700u
13743 #define ENET_RCMR_CMP2_SHIFT                     8
13744 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP2_SHIFT))&ENET_RCMR_CMP2_MASK)
13745 #define ENET_RCMR_CMP3_MASK                      0x7000u
13746 #define ENET_RCMR_CMP3_SHIFT                     12
13747 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP3_SHIFT))&ENET_RCMR_CMP3_MASK)
13748 #define ENET_RCMR_MATCHEN_MASK                   0x10000u
13749 #define ENET_RCMR_MATCHEN_SHIFT                  16
13750 /* DMACFG Bit Fields */
13751 #define ENET_DMACFG_IDLE_SLOPE_MASK              0xFFFFu
13752 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             0
13753 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x))<<ENET_DMACFG_IDLE_SLOPE_SHIFT))&ENET_DMACFG_IDLE_SLOPE_MASK)
13754 #define ENET_DMACFG_DMA_CLASS_EN_MASK            0x10000u
13755 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           16
13756 #define ENET_DMACFG_CALC_NOIPG_MASK              0x20000u
13757 #define ENET_DMACFG_CALC_NOIPG_SHIFT             17
13758 /* RDAR1 Bit Fields */
13759 #define ENET_RDAR1_RDAR_MASK                     0x1000000u
13760 #define ENET_RDAR1_RDAR_SHIFT                    24
13761 /* TDAR1 Bit Fields */
13762 #define ENET_TDAR1_TDAR_MASK                     0x1000000u
13763 #define ENET_TDAR1_TDAR_SHIFT                    24
13764 /* RDAR2 Bit Fields */
13765 #define ENET_RDAR2_RDAR_MASK                     0x1000000u
13766 #define ENET_RDAR2_RDAR_SHIFT                    24
13767 /* TDAR2 Bit Fields */
13768 #define ENET_TDAR2_TDAR_MASK                     0x1000000u
13769 #define ENET_TDAR2_TDAR_SHIFT                    24
13770 /* QOS Bit Fields */
13771 #define ENET_QOS_TX_SCHEME_MASK                  0x7u
13772 #define ENET_QOS_TX_SCHEME_SHIFT                 0
13773 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_QOS_TX_SCHEME_SHIFT))&ENET_QOS_TX_SCHEME_MASK)
13774 #define ENET_QOS_RX_FLUSH0_MASK                  0x8u
13775 #define ENET_QOS_RX_FLUSH0_SHIFT                 3
13776 #define ENET_QOS_RX_FLUSH1_MASK                  0x10u
13777 #define ENET_QOS_RX_FLUSH1_SHIFT                 4
13778 #define ENET_QOS_RX_FLUSH2_MASK                  0x20u
13779 #define ENET_QOS_RX_FLUSH2_SHIFT                 5
13780 /* RMON_T_DROP Bit Fields */
13781 /* RMON_T_PACKETS Bit Fields */
13782 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
13783 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
13784 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
13785 /* RMON_T_BC_PKT Bit Fields */
13786 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
13787 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
13788 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
13789 /* RMON_T_MC_PKT Bit Fields */
13790 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
13791 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
13792 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
13793 /* RMON_T_CRC_ALIGN Bit Fields */
13794 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
13795 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
13796 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
13797 /* RMON_T_UNDERSIZE Bit Fields */
13798 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
13799 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
13800 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
13801 /* RMON_T_OVERSIZE Bit Fields */
13802 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
13803 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
13804 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
13805 /* RMON_T_FRAG Bit Fields */
13806 #define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
13807 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
13808 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
13809 /* RMON_T_JAB Bit Fields */
13810 #define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
13811 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
13812 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
13813 /* RMON_T_COL Bit Fields */
13814 #define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
13815 #define ENET_RMON_T_COL_TXPKTS_SHIFT             0
13816 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
13817 /* RMON_T_P64 Bit Fields */
13818 #define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
13819 #define ENET_RMON_T_P64_TXPKTS_SHIFT             0
13820 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
13821 /* RMON_T_P65TO127 Bit Fields */
13822 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
13823 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
13824 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
13825 /* RMON_T_P128TO255 Bit Fields */
13826 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
13827 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
13828 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
13829 /* RMON_T_P256TO511 Bit Fields */
13830 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
13831 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
13832 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
13833 /* RMON_T_P512TO1023 Bit Fields */
13834 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
13835 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
13836 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
13837 /* RMON_T_P1024TO2047 Bit Fields */
13838 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
13839 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
13840 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
13841 /* RMON_T_P_GTE2048 Bit Fields */
13842 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
13843 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
13844 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
13845 /* RMON_T_OCTETS Bit Fields */
13846 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
13847 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
13848 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
13849 /* IEEE_T_DROP Bit Fields */
13850 /* IEEE_T_FRAME_OK Bit Fields */
13851 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
13852 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
13853 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
13854 /* IEEE_T_1COL Bit Fields */
13855 #define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
13856 #define ENET_IEEE_T_1COL_COUNT_SHIFT             0
13857 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
13858 /* IEEE_T_MCOL Bit Fields */
13859 #define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
13860 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
13861 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
13862 /* IEEE_T_DEF Bit Fields */
13863 #define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
13864 #define ENET_IEEE_T_DEF_COUNT_SHIFT              0
13865 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
13866 /* IEEE_T_LCOL Bit Fields */
13867 #define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
13868 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
13869 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
13870 /* IEEE_T_EXCOL Bit Fields */
13871 #define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
13872 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
13873 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
13874 /* IEEE_T_MACERR Bit Fields */
13875 #define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
13876 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
13877 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
13878 /* IEEE_T_CSERR Bit Fields */
13879 #define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
13880 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
13881 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
13882 /* IEEE_T_SQE Bit Fields */
13883 #define ENET_IEEE_T_SQE_COUNT_MASK               0xFFFFu
13884 #define ENET_IEEE_T_SQE_COUNT_SHIFT              0
13885 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK)
13886 /* IEEE_T_FDXFC Bit Fields */
13887 #define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
13888 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
13889 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
13890 /* IEEE_T_OCTETS_OK Bit Fields */
13891 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
13892 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
13893 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
13894 /* RMON_R_PACKETS Bit Fields */
13895 #define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
13896 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
13897 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
13898 /* RMON_R_BC_PKT Bit Fields */
13899 #define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
13900 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
13901 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
13902 /* RMON_R_MC_PKT Bit Fields */
13903 #define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
13904 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
13905 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
13906 /* RMON_R_CRC_ALIGN Bit Fields */
13907 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
13908 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
13909 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
13910 /* RMON_R_UNDERSIZE Bit Fields */
13911 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
13912 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
13913 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
13914 /* RMON_R_OVERSIZE Bit Fields */
13915 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
13916 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
13917 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
13918 /* RMON_R_FRAG Bit Fields */
13919 #define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
13920 #define ENET_RMON_R_FRAG_COUNT_SHIFT             0
13921 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
13922 /* RMON_R_JAB Bit Fields */
13923 #define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
13924 #define ENET_RMON_R_JAB_COUNT_SHIFT              0
13925 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
13926 /* RMON_R_RESVD_0 Bit Fields */
13927 /* RMON_R_P64 Bit Fields */
13928 #define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
13929 #define ENET_RMON_R_P64_COUNT_SHIFT              0
13930 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
13931 /* RMON_R_P65TO127 Bit Fields */
13932 #define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
13933 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
13934 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
13935 /* RMON_R_P128TO255 Bit Fields */
13936 #define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
13937 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
13938 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
13939 /* RMON_R_P256TO511 Bit Fields */
13940 #define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
13941 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
13942 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
13943 /* RMON_R_P512TO1023 Bit Fields */
13944 #define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
13945 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
13946 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
13947 /* RMON_R_P1024TO2047 Bit Fields */
13948 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
13949 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
13950 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
13951 /* RMON_R_P_GTE2048 Bit Fields */
13952 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
13953 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
13954 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
13955 /* RMON_R_OCTETS Bit Fields */
13956 #define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
13957 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
13958 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
13959 /* IEEE_R_DROP Bit Fields */
13960 #define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
13961 #define ENET_IEEE_R_DROP_COUNT_SHIFT             0
13962 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
13963 /* IEEE_R_FRAME_OK Bit Fields */
13964 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
13965 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
13966 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
13967 /* IEEE_R_CRC Bit Fields */
13968 #define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
13969 #define ENET_IEEE_R_CRC_COUNT_SHIFT              0
13970 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
13971 /* IEEE_R_ALIGN Bit Fields */
13972 #define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
13973 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
13974 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
13975 /* IEEE_R_MACERR Bit Fields */
13976 #define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
13977 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
13978 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
13979 /* IEEE_R_FDXFC Bit Fields */
13980 #define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
13981 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
13982 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
13983 /* IEEE_R_OCTETS_OK Bit Fields */
13984 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
13985 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
13986 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
13987 /* ATCR Bit Fields */
13988 #define ENET_ATCR_EN_MASK                        0x1u
13989 #define ENET_ATCR_EN_SHIFT                       0
13990 #define ENET_ATCR_OFFEN_MASK                     0x4u
13991 #define ENET_ATCR_OFFEN_SHIFT                    2
13992 #define ENET_ATCR_OFFRST_MASK                    0x8u
13993 #define ENET_ATCR_OFFRST_SHIFT                   3
13994 #define ENET_ATCR_PEREN_MASK                     0x10u
13995 #define ENET_ATCR_PEREN_SHIFT                    4
13996 #define ENET_ATCR_PINPER_MASK                    0x80u
13997 #define ENET_ATCR_PINPER_SHIFT                   7
13998 #define ENET_ATCR_RESTART_MASK                   0x200u
13999 #define ENET_ATCR_RESTART_SHIFT                  9
14000 #define ENET_ATCR_CAPTURE_MASK                   0x800u
14001 #define ENET_ATCR_CAPTURE_SHIFT                  11
14002 #define ENET_ATCR_SLAVE_MASK                     0x2000u
14003 #define ENET_ATCR_SLAVE_SHIFT                    13
14004 /* ATVR Bit Fields */
14005 #define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
14006 #define ENET_ATVR_ATIME_SHIFT                    0
14007 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
14008 /* ATOFF Bit Fields */
14009 #define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
14010 #define ENET_ATOFF_OFFSET_SHIFT                  0
14011 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
14012 /* ATPER Bit Fields */
14013 #define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
14014 #define ENET_ATPER_PERIOD_SHIFT                  0
14015 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
14016 /* ATCOR Bit Fields */
14017 #define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
14018 #define ENET_ATCOR_COR_SHIFT                     0
14019 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
14020 /* ATINC Bit Fields */
14021 #define ENET_ATINC_INC_MASK                      0x7Fu
14022 #define ENET_ATINC_INC_SHIFT                     0
14023 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
14024 #define ENET_ATINC_INC_CORR_MASK                 0x7F00u
14025 #define ENET_ATINC_INC_CORR_SHIFT                8
14026 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
14027 /* ATSTMP Bit Fields */
14028 #define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
14029 #define ENET_ATSTMP_TIMESTAMP_SHIFT              0
14030 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
14031 /* TGSR Bit Fields */
14032 #define ENET_TGSR_TF0_MASK                       0x1u
14033 #define ENET_TGSR_TF0_SHIFT                      0
14034 #define ENET_TGSR_TF1_MASK                       0x2u
14035 #define ENET_TGSR_TF1_SHIFT                      1
14036 #define ENET_TGSR_TF2_MASK                       0x4u
14037 #define ENET_TGSR_TF2_SHIFT                      2
14038 #define ENET_TGSR_TF3_MASK                       0x8u
14039 #define ENET_TGSR_TF3_SHIFT                      3
14040 /* TCSR Bit Fields */
14041 #define ENET_TCSR_TDRE_MASK                      0x1u
14042 #define ENET_TCSR_TDRE_SHIFT                     0
14043 #define ENET_TCSR_TMODE_MASK                     0x3Cu
14044 #define ENET_TCSR_TMODE_SHIFT                    2
14045 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
14046 #define ENET_TCSR_TIE_MASK                       0x40u
14047 #define ENET_TCSR_TIE_SHIFT                      6
14048 #define ENET_TCSR_TF_MASK                        0x80u
14049 #define ENET_TCSR_TF_SHIFT                       7
14050 /* TCCR Bit Fields */
14051 #define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
14052 #define ENET_TCCR_TCC_SHIFT                      0
14053 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
14054 
14055 /*!
14056  * @}
14057  */ /* end of group ENET_Register_Masks */
14058 
14059 /* ENET - Peripheral instance base addresses */
14060 /** Peripheral ENET1 base address */
14061 #define ENET1_BASE                               (0x30BE0000u)
14062 /** Peripheral ENET1 base pointer */
14063 #define ENET1                                    ((ENET_Type *)ENET1_BASE)
14064 #define ENET1_BASE_PTR                           (ENET1)
14065 /** Peripheral ENET2 base address */
14066 #define ENET2_BASE                               (0x30BF0000u)
14067 /** Peripheral ENET2 base pointer */
14068 #define ENET2                                    ((ENET_Type *)ENET2_BASE)
14069 #define ENET2_BASE_PTR                           (ENET2)
14070 /** Array initializer of ENET peripheral base addresses */
14071 #define ENET_BASE_ADDRS                          { ENET1_BASE, ENET2_BASE }
14072 /** Array initializer of ENET peripheral base pointers */
14073 #define ENET_BASE_PTRS                           { ENET1, ENET2 }
14074 /* ----------------------------------------------------------------------------
14075    -- ENET - Register accessor macros
14076    ---------------------------------------------------------------------------- */
14077 
14078 /*!
14079  * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
14080  * @{
14081  */
14082 
14083 
14084 /* ENET - Register instance definitions */
14085 /* ENET1 */
14086 #define ENET1_EIR                                ENET_EIR_REG(ENET1_BASE_PTR)
14087 #define ENET1_EIMR                               ENET_EIMR_REG(ENET1_BASE_PTR)
14088 #define ENET1_RDAR                               ENET_RDAR_REG(ENET1_BASE_PTR)
14089 #define ENET1_TDAR                               ENET_TDAR_REG(ENET1_BASE_PTR)
14090 #define ENET1_ECR                                ENET_ECR_REG(ENET1_BASE_PTR)
14091 #define ENET1_MMFR                               ENET_MMFR_REG(ENET1_BASE_PTR)
14092 #define ENET1_MSCR                               ENET_MSCR_REG(ENET1_BASE_PTR)
14093 #define ENET1_MIBC                               ENET_MIBC_REG(ENET1_BASE_PTR)
14094 #define ENET1_RCR                                ENET_RCR_REG(ENET1_BASE_PTR)
14095 #define ENET1_TCR                                ENET_TCR_REG(ENET1_BASE_PTR)
14096 #define ENET1_PALR                               ENET_PALR_REG(ENET1_BASE_PTR)
14097 #define ENET1_PAUR                               ENET_PAUR_REG(ENET1_BASE_PTR)
14098 #define ENET1_OPD                                ENET_OPD_REG(ENET1_BASE_PTR)
14099 #define ENET1_TXIC0                              ENET_TXIC_REG(ENET1_BASE_PTR,0)
14100 #define ENET1_TXIC1                              ENET_TXIC_REG(ENET1_BASE_PTR,1)
14101 #define ENET1_TXIC2                              ENET_TXIC_REG(ENET1_BASE_PTR,2)
14102 #define ENET1_RXIC0                              ENET_RXIC_REG(ENET1_BASE_PTR,0)
14103 #define ENET1_RXIC1                              ENET_RXIC_REG(ENET1_BASE_PTR,1)
14104 #define ENET1_RXIC2                              ENET_RXIC_REG(ENET1_BASE_PTR,2)
14105 #define ENET1_IAUR                               ENET_IAUR_REG(ENET1_BASE_PTR)
14106 #define ENET1_IALR                               ENET_IALR_REG(ENET1_BASE_PTR)
14107 #define ENET1_GAUR                               ENET_GAUR_REG(ENET1_BASE_PTR)
14108 #define ENET1_GALR                               ENET_GALR_REG(ENET1_BASE_PTR)
14109 #define ENET1_TFWR                               ENET_TFWR_REG(ENET1_BASE_PTR)
14110 #define ENET1_RDSR1                              ENET_RDSR1_REG(ENET1_BASE_PTR)
14111 #define ENET1_TDSR1                              ENET_TDSR1_REG(ENET1_BASE_PTR)
14112 #define ENET1_MRBR1                              ENET_MRBR1_REG(ENET1_BASE_PTR)
14113 #define ENET1_RDSR2                              ENET_RDSR2_REG(ENET1_BASE_PTR)
14114 #define ENET1_TDSR2                              ENET_TDSR2_REG(ENET1_BASE_PTR)
14115 #define ENET1_MRBR2                              ENET_MRBR2_REG(ENET1_BASE_PTR)
14116 #define ENET1_RDSR                               ENET_RDSR_REG(ENET1_BASE_PTR)
14117 #define ENET1_TDSR                               ENET_TDSR_REG(ENET1_BASE_PTR)
14118 #define ENET1_MRBR                               ENET_MRBR_REG(ENET1_BASE_PTR)
14119 #define ENET1_RSFL                               ENET_RSFL_REG(ENET1_BASE_PTR)
14120 #define ENET1_RSEM                               ENET_RSEM_REG(ENET1_BASE_PTR)
14121 #define ENET1_RAEM                               ENET_RAEM_REG(ENET1_BASE_PTR)
14122 #define ENET1_RAFL                               ENET_RAFL_REG(ENET1_BASE_PTR)
14123 #define ENET1_TSEM                               ENET_TSEM_REG(ENET1_BASE_PTR)
14124 #define ENET1_TAEM                               ENET_TAEM_REG(ENET1_BASE_PTR)
14125 #define ENET1_TAFL                               ENET_TAFL_REG(ENET1_BASE_PTR)
14126 #define ENET1_TIPG                               ENET_TIPG_REG(ENET1_BASE_PTR)
14127 #define ENET1_FTRL                               ENET_FTRL_REG(ENET1_BASE_PTR)
14128 #define ENET1_TACC                               ENET_TACC_REG(ENET1_BASE_PTR)
14129 #define ENET1_RACC                               ENET_RACC_REG(ENET1_BASE_PTR)
14130 #define ENET1_RCMR1                              ENET_RCMR_REG(ENET1_BASE_PTR,0)
14131 #define ENET1_RCMR2                              ENET_RCMR_REG(ENET1_BASE_PTR,1)
14132 #define ENET1_DMA1CFG                            ENET_DMACFG_REG(ENET1_BASE_PTR,0)
14133 #define ENET1_DMA2CFG                            ENET_DMACFG_REG(ENET1_BASE_PTR,1)
14134 #define ENET1_RDAR1                              ENET_RDAR1_REG(ENET1_BASE_PTR)
14135 #define ENET1_TDAR1                              ENET_TDAR1_REG(ENET1_BASE_PTR)
14136 #define ENET1_RDAR2                              ENET_RDAR2_REG(ENET1_BASE_PTR)
14137 #define ENET1_TDAR2                              ENET_TDAR2_REG(ENET1_BASE_PTR)
14138 #define ENET1_QOS                                ENET_QOS_REG(ENET1_BASE_PTR)
14139 #define ENET1_RMON_T_DROP                        ENET_RMON_T_DROP_REG(ENET1_BASE_PTR)
14140 #define ENET1_RMON_T_PACKETS                     ENET_RMON_T_PACKETS_REG(ENET1_BASE_PTR)
14141 #define ENET1_RMON_T_BC_PKT                      ENET_RMON_T_BC_PKT_REG(ENET1_BASE_PTR)
14142 #define ENET1_RMON_T_MC_PKT                      ENET_RMON_T_MC_PKT_REG(ENET1_BASE_PTR)
14143 #define ENET1_RMON_T_CRC_ALIGN                   ENET_RMON_T_CRC_ALIGN_REG(ENET1_BASE_PTR)
14144 #define ENET1_RMON_T_UNDERSIZE                   ENET_RMON_T_UNDERSIZE_REG(ENET1_BASE_PTR)
14145 #define ENET1_RMON_T_OVERSIZE                    ENET_RMON_T_OVERSIZE_REG(ENET1_BASE_PTR)
14146 #define ENET1_RMON_T_FRAG                        ENET_RMON_T_FRAG_REG(ENET1_BASE_PTR)
14147 #define ENET1_RMON_T_JAB                         ENET_RMON_T_JAB_REG(ENET1_BASE_PTR)
14148 #define ENET1_RMON_T_COL                         ENET_RMON_T_COL_REG(ENET1_BASE_PTR)
14149 #define ENET1_RMON_T_P64                         ENET_RMON_T_P64_REG(ENET1_BASE_PTR)
14150 #define ENET1_RMON_T_P65TO127                    ENET_RMON_T_P65TO127_REG(ENET1_BASE_PTR)
14151 #define ENET1_RMON_T_P128TO255                   ENET_RMON_T_P128TO255_REG(ENET1_BASE_PTR)
14152 #define ENET1_RMON_T_P256TO511                   ENET_RMON_T_P256TO511_REG(ENET1_BASE_PTR)
14153 #define ENET1_RMON_T_P512TO1023                  ENET_RMON_T_P512TO1023_REG(ENET1_BASE_PTR)
14154 #define ENET1_RMON_T_P1024TO2047                 ENET_RMON_T_P1024TO2047_REG(ENET1_BASE_PTR)
14155 #define ENET1_RMON_T_P_GTE2048                   ENET_RMON_T_P_GTE2048_REG(ENET1_BASE_PTR)
14156 #define ENET1_RMON_T_OCTETS                      ENET_RMON_T_OCTETS_REG(ENET1_BASE_PTR)
14157 #define ENET1_IEEE_T_DROP                        ENET_IEEE_T_DROP_REG(ENET1_BASE_PTR)
14158 #define ENET1_IEEE_T_FRAME_OK                    ENET_IEEE_T_FRAME_OK_REG(ENET1_BASE_PTR)
14159 #define ENET1_IEEE_T_1COL                        ENET_IEEE_T_1COL_REG(ENET1_BASE_PTR)
14160 #define ENET1_IEEE_T_MCOL                        ENET_IEEE_T_MCOL_REG(ENET1_BASE_PTR)
14161 #define ENET1_IEEE_T_DEF                         ENET_IEEE_T_DEF_REG(ENET1_BASE_PTR)
14162 #define ENET1_IEEE_T_LCOL                        ENET_IEEE_T_LCOL_REG(ENET1_BASE_PTR)
14163 #define ENET1_IEEE_T_EXCOL                       ENET_IEEE_T_EXCOL_REG(ENET1_BASE_PTR)
14164 #define ENET1_IEEE_T_MACERR                      ENET_IEEE_T_MACERR_REG(ENET1_BASE_PTR)
14165 #define ENET1_IEEE_T_CSERR                       ENET_IEEE_T_CSERR_REG(ENET1_BASE_PTR)
14166 #define ENET1_IEEE_T_SQE                         ENET_IEEE_T_SQE_REG(ENET1_BASE_PTR)
14167 #define ENET1_IEEE_T_FDXFC                       ENET_IEEE_T_FDXFC_REG(ENET1_BASE_PTR)
14168 #define ENET1_IEEE_T_OCTETS_OK                   ENET_IEEE_T_OCTETS_OK_REG(ENET1_BASE_PTR)
14169 #define ENET1_RMON_R_PACKETS                     ENET_RMON_R_PACKETS_REG(ENET1_BASE_PTR)
14170 #define ENET1_RMON_R_BC_PKT                      ENET_RMON_R_BC_PKT_REG(ENET1_BASE_PTR)
14171 #define ENET1_RMON_R_MC_PKT                      ENET_RMON_R_MC_PKT_REG(ENET1_BASE_PTR)
14172 #define ENET1_RMON_R_CRC_ALIGN                   ENET_RMON_R_CRC_ALIGN_REG(ENET1_BASE_PTR)
14173 #define ENET1_RMON_R_UNDERSIZE                   ENET_RMON_R_UNDERSIZE_REG(ENET1_BASE_PTR)
14174 #define ENET1_RMON_R_OVERSIZE                    ENET_RMON_R_OVERSIZE_REG(ENET1_BASE_PTR)
14175 #define ENET1_RMON_R_FRAG                        ENET_RMON_R_FRAG_REG(ENET1_BASE_PTR)
14176 #define ENET1_RMON_R_JAB                         ENET_RMON_R_JAB_REG(ENET1_BASE_PTR)
14177 #define ENET1_RMON_R_RESVD_0                     ENET_RMON_R_RESVD_0_REG(ENET1_BASE_PTR)
14178 #define ENET1_RMON_R_P64                         ENET_RMON_R_P64_REG(ENET1_BASE_PTR)
14179 #define ENET1_RMON_R_P65TO127                    ENET_RMON_R_P65TO127_REG(ENET1_BASE_PTR)
14180 #define ENET1_RMON_R_P128TO255                   ENET_RMON_R_P128TO255_REG(ENET1_BASE_PTR)
14181 #define ENET1_RMON_R_P256TO511                   ENET_RMON_R_P256TO511_REG(ENET1_BASE_PTR)
14182 #define ENET1_RMON_R_P512TO1023                  ENET_RMON_R_P512TO1023_REG(ENET1_BASE_PTR)
14183 #define ENET1_RMON_R_P1024TO2047                 ENET_RMON_R_P1024TO2047_REG(ENET1_BASE_PTR)
14184 #define ENET1_RMON_R_P_GTE2048                   ENET_RMON_R_P_GTE2048_REG(ENET1_BASE_PTR)
14185 #define ENET1_RMON_R_OCTETS                      ENET_RMON_R_OCTETS_REG(ENET1_BASE_PTR)
14186 #define ENET1_IEEE_R_DROP                        ENET_IEEE_R_DROP_REG(ENET1_BASE_PTR)
14187 #define ENET1_IEEE_R_FRAME_OK                    ENET_IEEE_R_FRAME_OK_REG(ENET1_BASE_PTR)
14188 #define ENET1_IEEE_R_CRC                         ENET_IEEE_R_CRC_REG(ENET1_BASE_PTR)
14189 #define ENET1_IEEE_R_ALIGN                       ENET_IEEE_R_ALIGN_REG(ENET1_BASE_PTR)
14190 #define ENET1_IEEE_R_MACERR                      ENET_IEEE_R_MACERR_REG(ENET1_BASE_PTR)
14191 #define ENET1_IEEE_R_FDXFC                       ENET_IEEE_R_FDXFC_REG(ENET1_BASE_PTR)
14192 #define ENET1_IEEE_R_OCTETS_OK                   ENET_IEEE_R_OCTETS_OK_REG(ENET1_BASE_PTR)
14193 #define ENET1_ATCR                               ENET_ATCR_REG(ENET1_BASE_PTR)
14194 #define ENET1_ATVR                               ENET_ATVR_REG(ENET1_BASE_PTR)
14195 #define ENET1_ATOFF                              ENET_ATOFF_REG(ENET1_BASE_PTR)
14196 #define ENET1_ATPER                              ENET_ATPER_REG(ENET1_BASE_PTR)
14197 #define ENET1_ATCOR                              ENET_ATCOR_REG(ENET1_BASE_PTR)
14198 #define ENET1_ATINC                              ENET_ATINC_REG(ENET1_BASE_PTR)
14199 #define ENET1_ATSTMP                             ENET_ATSTMP_REG(ENET1_BASE_PTR)
14200 #define ENET1_TGSR                               ENET_TGSR_REG(ENET1_BASE_PTR)
14201 #define ENET1_TCSR0                              ENET_TCSR_REG(ENET1_BASE_PTR,0)
14202 #define ENET1_TCCR0                              ENET_TCCR_REG(ENET1_BASE_PTR,0)
14203 #define ENET1_TCSR1                              ENET_TCSR_REG(ENET1_BASE_PTR,1)
14204 #define ENET1_TCCR1                              ENET_TCCR_REG(ENET1_BASE_PTR,1)
14205 #define ENET1_TCSR2                              ENET_TCSR_REG(ENET1_BASE_PTR,2)
14206 #define ENET1_TCCR2                              ENET_TCCR_REG(ENET1_BASE_PTR,2)
14207 #define ENET1_TCSR3                              ENET_TCSR_REG(ENET1_BASE_PTR,3)
14208 #define ENET1_TCCR3                              ENET_TCCR_REG(ENET1_BASE_PTR,3)
14209 /* ENET2 */
14210 #define ENET2_EIR                                ENET_EIR_REG(ENET2_BASE_PTR)
14211 #define ENET2_EIMR                               ENET_EIMR_REG(ENET2_BASE_PTR)
14212 #define ENET2_RDAR                               ENET_RDAR_REG(ENET2_BASE_PTR)
14213 #define ENET2_TDAR                               ENET_TDAR_REG(ENET2_BASE_PTR)
14214 #define ENET2_ECR                                ENET_ECR_REG(ENET2_BASE_PTR)
14215 #define ENET2_MMFR                               ENET_MMFR_REG(ENET2_BASE_PTR)
14216 #define ENET2_MSCR                               ENET_MSCR_REG(ENET2_BASE_PTR)
14217 #define ENET2_MIBC                               ENET_MIBC_REG(ENET2_BASE_PTR)
14218 #define ENET2_RCR                                ENET_RCR_REG(ENET2_BASE_PTR)
14219 #define ENET2_TCR                                ENET_TCR_REG(ENET2_BASE_PTR)
14220 #define ENET2_PALR                               ENET_PALR_REG(ENET2_BASE_PTR)
14221 #define ENET2_PAUR                               ENET_PAUR_REG(ENET2_BASE_PTR)
14222 #define ENET2_OPD                                ENET_OPD_REG(ENET2_BASE_PTR)
14223 #define ENET2_TXIC0                              ENET_TXIC_REG(ENET2_BASE_PTR,0)
14224 #define ENET2_TXIC1                              ENET_TXIC_REG(ENET2_BASE_PTR,1)
14225 #define ENET2_TXIC2                              ENET_TXIC_REG(ENET2_BASE_PTR,2)
14226 #define ENET2_RXIC0                              ENET_RXIC_REG(ENET2_BASE_PTR,0)
14227 #define ENET2_RXIC1                              ENET_RXIC_REG(ENET2_BASE_PTR,1)
14228 #define ENET2_RXIC2                              ENET_RXIC_REG(ENET2_BASE_PTR,2)
14229 #define ENET2_IAUR                               ENET_IAUR_REG(ENET2_BASE_PTR)
14230 #define ENET2_IALR                               ENET_IALR_REG(ENET2_BASE_PTR)
14231 #define ENET2_GAUR                               ENET_GAUR_REG(ENET2_BASE_PTR)
14232 #define ENET2_GALR                               ENET_GALR_REG(ENET2_BASE_PTR)
14233 #define ENET2_TFWR                               ENET_TFWR_REG(ENET2_BASE_PTR)
14234 #define ENET2_RDSR1                              ENET_RDSR1_REG(ENET2_BASE_PTR)
14235 #define ENET2_TDSR1                              ENET_TDSR1_REG(ENET2_BASE_PTR)
14236 #define ENET2_MRBR1                              ENET_MRBR1_REG(ENET2_BASE_PTR)
14237 #define ENET2_RDSR2                              ENET_RDSR2_REG(ENET2_BASE_PTR)
14238 #define ENET2_TDSR2                              ENET_TDSR2_REG(ENET2_BASE_PTR)
14239 #define ENET2_MRBR2                              ENET_MRBR2_REG(ENET2_BASE_PTR)
14240 #define ENET2_RDSR                               ENET_RDSR_REG(ENET2_BASE_PTR)
14241 #define ENET2_TDSR                               ENET_TDSR_REG(ENET2_BASE_PTR)
14242 #define ENET2_MRBR                               ENET_MRBR_REG(ENET2_BASE_PTR)
14243 #define ENET2_RSFL                               ENET_RSFL_REG(ENET2_BASE_PTR)
14244 #define ENET2_RSEM                               ENET_RSEM_REG(ENET2_BASE_PTR)
14245 #define ENET2_RAEM                               ENET_RAEM_REG(ENET2_BASE_PTR)
14246 #define ENET2_RAFL                               ENET_RAFL_REG(ENET2_BASE_PTR)
14247 #define ENET2_TSEM                               ENET_TSEM_REG(ENET2_BASE_PTR)
14248 #define ENET2_TAEM                               ENET_TAEM_REG(ENET2_BASE_PTR)
14249 #define ENET2_TAFL                               ENET_TAFL_REG(ENET2_BASE_PTR)
14250 #define ENET2_TIPG                               ENET_TIPG_REG(ENET2_BASE_PTR)
14251 #define ENET2_FTRL                               ENET_FTRL_REG(ENET2_BASE_PTR)
14252 #define ENET2_TACC                               ENET_TACC_REG(ENET2_BASE_PTR)
14253 #define ENET2_RACC                               ENET_RACC_REG(ENET2_BASE_PTR)
14254 #define ENET2_RCMR1                              ENET_RCMR_REG(ENET2_BASE_PTR,0)
14255 #define ENET2_RCMR2                              ENET_RCMR_REG(ENET2_BASE_PTR,1)
14256 #define ENET2_DMA1CFG                            ENET_DMACFG_REG(ENET2_BASE_PTR,0)
14257 #define ENET2_DMA2CFG                            ENET_DMACFG_REG(ENET2_BASE_PTR,1)
14258 #define ENET2_RDAR1                              ENET_RDAR1_REG(ENET2_BASE_PTR)
14259 #define ENET2_TDAR1                              ENET_TDAR1_REG(ENET2_BASE_PTR)
14260 #define ENET2_RDAR2                              ENET_RDAR2_REG(ENET2_BASE_PTR)
14261 #define ENET2_TDAR2                              ENET_TDAR2_REG(ENET2_BASE_PTR)
14262 #define ENET2_QOS                                ENET_QOS_REG(ENET2_BASE_PTR)
14263 #define ENET2_RMON_T_DROP                        ENET_RMON_T_DROP_REG(ENET2_BASE_PTR)
14264 #define ENET2_RMON_T_PACKETS                     ENET_RMON_T_PACKETS_REG(ENET2_BASE_PTR)
14265 #define ENET2_RMON_T_BC_PKT                      ENET_RMON_T_BC_PKT_REG(ENET2_BASE_PTR)
14266 #define ENET2_RMON_T_MC_PKT                      ENET_RMON_T_MC_PKT_REG(ENET2_BASE_PTR)
14267 #define ENET2_RMON_T_CRC_ALIGN                   ENET_RMON_T_CRC_ALIGN_REG(ENET2_BASE_PTR)
14268 #define ENET2_RMON_T_UNDERSIZE                   ENET_RMON_T_UNDERSIZE_REG(ENET2_BASE_PTR)
14269 #define ENET2_RMON_T_OVERSIZE                    ENET_RMON_T_OVERSIZE_REG(ENET2_BASE_PTR)
14270 #define ENET2_RMON_T_FRAG                        ENET_RMON_T_FRAG_REG(ENET2_BASE_PTR)
14271 #define ENET2_RMON_T_JAB                         ENET_RMON_T_JAB_REG(ENET2_BASE_PTR)
14272 #define ENET2_RMON_T_COL                         ENET_RMON_T_COL_REG(ENET2_BASE_PTR)
14273 #define ENET2_RMON_T_P64                         ENET_RMON_T_P64_REG(ENET2_BASE_PTR)
14274 #define ENET2_RMON_T_P65TO127                    ENET_RMON_T_P65TO127_REG(ENET2_BASE_PTR)
14275 #define ENET2_RMON_T_P128TO255                   ENET_RMON_T_P128TO255_REG(ENET2_BASE_PTR)
14276 #define ENET2_RMON_T_P256TO511                   ENET_RMON_T_P256TO511_REG(ENET2_BASE_PTR)
14277 #define ENET2_RMON_T_P512TO1023                  ENET_RMON_T_P512TO1023_REG(ENET2_BASE_PTR)
14278 #define ENET2_RMON_T_P1024TO2047                 ENET_RMON_T_P1024TO2047_REG(ENET2_BASE_PTR)
14279 #define ENET2_RMON_T_P_GTE2048                   ENET_RMON_T_P_GTE2048_REG(ENET2_BASE_PTR)
14280 #define ENET2_RMON_T_OCTETS                      ENET_RMON_T_OCTETS_REG(ENET2_BASE_PTR)
14281 #define ENET2_IEEE_T_DROP                        ENET_IEEE_T_DROP_REG(ENET2_BASE_PTR)
14282 #define ENET2_IEEE_T_FRAME_OK                    ENET_IEEE_T_FRAME_OK_REG(ENET2_BASE_PTR)
14283 #define ENET2_IEEE_T_1COL                        ENET_IEEE_T_1COL_REG(ENET2_BASE_PTR)
14284 #define ENET2_IEEE_T_MCOL                        ENET_IEEE_T_MCOL_REG(ENET2_BASE_PTR)
14285 #define ENET2_IEEE_T_DEF                         ENET_IEEE_T_DEF_REG(ENET2_BASE_PTR)
14286 #define ENET2_IEEE_T_LCOL                        ENET_IEEE_T_LCOL_REG(ENET2_BASE_PTR)
14287 #define ENET2_IEEE_T_EXCOL                       ENET_IEEE_T_EXCOL_REG(ENET2_BASE_PTR)
14288 #define ENET2_IEEE_T_MACERR                      ENET_IEEE_T_MACERR_REG(ENET2_BASE_PTR)
14289 #define ENET2_IEEE_T_CSERR                       ENET_IEEE_T_CSERR_REG(ENET2_BASE_PTR)
14290 #define ENET2_IEEE_T_SQE                         ENET_IEEE_T_SQE_REG(ENET2_BASE_PTR)
14291 #define ENET2_IEEE_T_FDXFC                       ENET_IEEE_T_FDXFC_REG(ENET2_BASE_PTR)
14292 #define ENET2_IEEE_T_OCTETS_OK                   ENET_IEEE_T_OCTETS_OK_REG(ENET2_BASE_PTR)
14293 #define ENET2_RMON_R_PACKETS                     ENET_RMON_R_PACKETS_REG(ENET2_BASE_PTR)
14294 #define ENET2_RMON_R_BC_PKT                      ENET_RMON_R_BC_PKT_REG(ENET2_BASE_PTR)
14295 #define ENET2_RMON_R_MC_PKT                      ENET_RMON_R_MC_PKT_REG(ENET2_BASE_PTR)
14296 #define ENET2_RMON_R_CRC_ALIGN                   ENET_RMON_R_CRC_ALIGN_REG(ENET2_BASE_PTR)
14297 #define ENET2_RMON_R_UNDERSIZE                   ENET_RMON_R_UNDERSIZE_REG(ENET2_BASE_PTR)
14298 #define ENET2_RMON_R_OVERSIZE                    ENET_RMON_R_OVERSIZE_REG(ENET2_BASE_PTR)
14299 #define ENET2_RMON_R_FRAG                        ENET_RMON_R_FRAG_REG(ENET2_BASE_PTR)
14300 #define ENET2_RMON_R_JAB                         ENET_RMON_R_JAB_REG(ENET2_BASE_PTR)
14301 #define ENET2_RMON_R_RESVD_0                     ENET_RMON_R_RESVD_0_REG(ENET2_BASE_PTR)
14302 #define ENET2_RMON_R_P64                         ENET_RMON_R_P64_REG(ENET2_BASE_PTR)
14303 #define ENET2_RMON_R_P65TO127                    ENET_RMON_R_P65TO127_REG(ENET2_BASE_PTR)
14304 #define ENET2_RMON_R_P128TO255                   ENET_RMON_R_P128TO255_REG(ENET2_BASE_PTR)
14305 #define ENET2_RMON_R_P256TO511                   ENET_RMON_R_P256TO511_REG(ENET2_BASE_PTR)
14306 #define ENET2_RMON_R_P512TO1023                  ENET_RMON_R_P512TO1023_REG(ENET2_BASE_PTR)
14307 #define ENET2_RMON_R_P1024TO2047                 ENET_RMON_R_P1024TO2047_REG(ENET2_BASE_PTR)
14308 #define ENET2_RMON_R_P_GTE2048                   ENET_RMON_R_P_GTE2048_REG(ENET2_BASE_PTR)
14309 #define ENET2_RMON_R_OCTETS                      ENET_RMON_R_OCTETS_REG(ENET2_BASE_PTR)
14310 #define ENET2_IEEE_R_DROP                        ENET_IEEE_R_DROP_REG(ENET2_BASE_PTR)
14311 #define ENET2_IEEE_R_FRAME_OK                    ENET_IEEE_R_FRAME_OK_REG(ENET2_BASE_PTR)
14312 #define ENET2_IEEE_R_CRC                         ENET_IEEE_R_CRC_REG(ENET2_BASE_PTR)
14313 #define ENET2_IEEE_R_ALIGN                       ENET_IEEE_R_ALIGN_REG(ENET2_BASE_PTR)
14314 #define ENET2_IEEE_R_MACERR                      ENET_IEEE_R_MACERR_REG(ENET2_BASE_PTR)
14315 #define ENET2_IEEE_R_FDXFC                       ENET_IEEE_R_FDXFC_REG(ENET2_BASE_PTR)
14316 #define ENET2_IEEE_R_OCTETS_OK                   ENET_IEEE_R_OCTETS_OK_REG(ENET2_BASE_PTR)
14317 #define ENET2_ATCR                               ENET_ATCR_REG(ENET2_BASE_PTR)
14318 #define ENET2_ATVR                               ENET_ATVR_REG(ENET2_BASE_PTR)
14319 #define ENET2_ATOFF                              ENET_ATOFF_REG(ENET2_BASE_PTR)
14320 #define ENET2_ATPER                              ENET_ATPER_REG(ENET2_BASE_PTR)
14321 #define ENET2_ATCOR                              ENET_ATCOR_REG(ENET2_BASE_PTR)
14322 #define ENET2_ATINC                              ENET_ATINC_REG(ENET2_BASE_PTR)
14323 #define ENET2_ATSTMP                             ENET_ATSTMP_REG(ENET2_BASE_PTR)
14324 #define ENET2_TGSR                               ENET_TGSR_REG(ENET2_BASE_PTR)
14325 #define ENET2_TCSR0                              ENET_TCSR_REG(ENET2_BASE_PTR,0)
14326 #define ENET2_TCCR0                              ENET_TCCR_REG(ENET2_BASE_PTR,0)
14327 #define ENET2_TCSR1                              ENET_TCSR_REG(ENET2_BASE_PTR,1)
14328 #define ENET2_TCCR1                              ENET_TCCR_REG(ENET2_BASE_PTR,1)
14329 #define ENET2_TCSR2                              ENET_TCSR_REG(ENET2_BASE_PTR,2)
14330 #define ENET2_TCCR2                              ENET_TCCR_REG(ENET2_BASE_PTR,2)
14331 #define ENET2_TCSR3                              ENET_TCSR_REG(ENET2_BASE_PTR,3)
14332 #define ENET2_TCCR3                              ENET_TCCR_REG(ENET2_BASE_PTR,3)
14333 /* ENET - Register array accessors */
14334 #define ENET1_TXIC(index)                        ENET_TXIC_REG(ENET1_BASE_PTR,index)
14335 #define ENET2_TXIC(index)                        ENET_TXIC_REG(ENET2_BASE_PTR,index)
14336 #define ENET1_RXIC(index)                        ENET_RXIC_REG(ENET1_BASE_PTR,index)
14337 #define ENET2_RXIC(index)                        ENET_RXIC_REG(ENET2_BASE_PTR,index)
14338 #define ENET1_RCMR(index)                        ENET_RCMR_REG(ENET1_BASE_PTR,index)
14339 #define ENET2_RCMR(index)                        ENET_RCMR_REG(ENET2_BASE_PTR,index)
14340 #define ENET1_DMACFG(index)                      ENET_DMACFG_REG(ENET1_BASE_PTR,index)
14341 #define ENET2_DMACFG(index)                      ENET_DMACFG_REG(ENET2_BASE_PTR,index)
14342 #define ENET1_TCSR(index)                        ENET_TCSR_REG(ENET1_BASE_PTR,index)
14343 #define ENET2_TCSR(index)                        ENET_TCSR_REG(ENET2_BASE_PTR,index)
14344 #define ENET1_TCCR(index)                        ENET_TCCR_REG(ENET1_BASE_PTR,index)
14345 #define ENET2_TCCR(index)                        ENET_TCCR_REG(ENET2_BASE_PTR,index)
14346 /*!
14347  * @}
14348  */ /* end of group ENET_Register_Accessor_Macros */
14349 
14350 
14351 /*!
14352  * @}
14353  */ /* end of group ENET_Peripheral */
14354 
14355 /* ----------------------------------------------------------------------------
14356    -- EPDC Peripheral Access Layer
14357    ---------------------------------------------------------------------------- */
14358 
14359 /*!
14360  * @addtogroup EPDC_Peripheral_Access_Layer EPDC Peripheral Access Layer
14361  * @{
14362  */
14363 
14364 /** EPDC - Register Layout Typedef */
14365 typedef struct {
14366   __IO  uint32_t CTRL;                                   /**< EPDC Control Register, offset: 0x0 */
14367   __IO  uint32_t CTRL_SET;                               /**< EPDC Control Register, offset: 0x4 */
14368   __IO  uint32_t CTRL_CLR;                               /**< EPDC Control Register, offset: 0x8 */
14369   __IO  uint32_t CTRL_TOG;                               /**< EPDC Control Register, offset: 0xC */
14370   __IO  uint32_t WB_ADDR_TCE;                            /**< EPDC Working Buffer Address for TCE, offset: 0x10 */
14371   uint8_t RESERVED_0[12];
14372   __IO  uint32_t WVADDR;                                 /**< EPDC Waveform Address Pointer, offset: 0x20 */
14373   uint8_t RESERVED_1[12];
14374   __IO  uint32_t WB_ADDR;                                /**< EPDC Working Buffer Address, offset: 0x30 */
14375   uint8_t RESERVED_2[12];
14376   __IO  uint32_t RES;                                    /**< EPDC Screen Resolution, offset: 0x40 */
14377   uint8_t RESERVED_3[12];
14378   __IO  uint32_t FORMAT;                                 /**< EPDC Format Control Register, offset: 0x50 */
14379   __IO  uint32_t FORMAT_SET;                             /**< EPDC Format Control Register, offset: 0x54 */
14380   __IO  uint32_t FORMAT_CLR;                             /**< EPDC Format Control Register, offset: 0x58 */
14381   __IO  uint32_t FORMAT_TOG;                             /**< EPDC Format Control Register, offset: 0x5C */
14382   __IO  uint32_t WB_FIELD0;                              /**< Working Buffer Field Setting, offset: 0x60 */
14383   uint8_t RESERVED_4[12];
14384   __IO  uint32_t WB_FIELD1;                              /**< Working Buffer Field Setting, offset: 0x70 */
14385   uint8_t RESERVED_5[12];
14386   __IO  uint32_t WB_FIELD2;                              /**< Working Buffer Field Setting, offset: 0x80 */
14387   uint8_t RESERVED_6[12];
14388   __IO  uint32_t WB_FIELD3;                              /**< Working Buffer Field Setting, offset: 0x90 */
14389   uint8_t RESERVED_7[12];
14390   __IO  uint32_t FIFOCTRL;                               /**< EPDC FIFO control register, offset: 0xA0 */
14391   __IO  uint32_t FIFOCTRL_SET;                           /**< EPDC FIFO control register, offset: 0xA4 */
14392   __IO  uint32_t FIFOCTRL_CLR;                           /**< EPDC FIFO control register, offset: 0xA8 */
14393   __IO  uint32_t FIFOCTRL_TOG;                           /**< EPDC FIFO control register, offset: 0xAC */
14394   uint8_t RESERVED_8[80];
14395   __IO  uint32_t UPD_ADDR;                               /**< EPDC Update Region Address, offset: 0x100 */
14396   uint8_t RESERVED_9[12];
14397   __IO  uint32_t UPD_STRIDE;                             /**< EPDC Update Region Stride, offset: 0x110 */
14398   uint8_t RESERVED_10[12];
14399   __IO  uint32_t UPD_CORD;                               /**< EPDC Update Command Co-ordinate, offset: 0x120 */
14400   uint8_t RESERVED_11[28];
14401   __IO  uint32_t UPD_SIZE;                               /**< EPDC Update Command Size, offset: 0x140 */
14402   uint8_t RESERVED_12[28];
14403   __IO  uint32_t UPD_CTRL;                               /**< EPDC Update Command Control, offset: 0x160 */
14404   __IO  uint32_t UPD_CTRL_SET;                           /**< EPDC Update Command Control, offset: 0x164 */
14405   __IO  uint32_t UPD_CTRL_CLR;                           /**< EPDC Update Command Control, offset: 0x168 */
14406   __IO  uint32_t UPD_CTRL_TOG;                           /**< EPDC Update Command Control, offset: 0x16C */
14407   uint8_t RESERVED_13[16];
14408   __IO  uint32_t UPD_FIXED;                              /**< EPDC Update Fixed Pixel Control, offset: 0x180 */
14409   __IO  uint32_t UPD_FIXED_SET;                          /**< EPDC Update Fixed Pixel Control, offset: 0x184 */
14410   __IO  uint32_t UPD_FIXED_CLR;                          /**< EPDC Update Fixed Pixel Control, offset: 0x188 */
14411   __IO  uint32_t UPD_FIXED_TOG;                          /**< EPDC Update Fixed Pixel Control, offset: 0x18C */
14412   uint8_t RESERVED_14[16];
14413   __IO  uint32_t TEMP;                                   /**< EPDC Temperature Register, offset: 0x1A0 */
14414   uint8_t RESERVED_15[28];
14415   __IO  uint32_t AUTOWV_LUT;                             /**< Waveform Mode Lookup Table Control Register., offset: 0x1C0 */
14416   uint8_t RESERVED_16[28];
14417   __IO  uint32_t LUT_STANDBY1;                           /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1E0 */
14418   __IO  uint32_t LUT_STANDBY1_SET;                       /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1E4 */
14419   __IO  uint32_t LUT_STANDBY1_CLR;                       /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1E8 */
14420   __IO  uint32_t LUT_STANDBY1_TOG;                       /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1EC */
14421   __IO  uint32_t LUT_STANDBY2;                           /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1F0 */
14422   __IO  uint32_t LUT_STANDBY2_SET;                       /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1F4 */
14423   __IO  uint32_t LUT_STANDBY2_CLR;                       /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1F8 */
14424   __IO  uint32_t LUT_STANDBY2_TOG;                       /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1FC */
14425   __IO  uint32_t TCE_CTRL;                               /**< EPDC Timing Control Engine Control Register, offset: 0x200 */
14426   __IO  uint32_t TCE_CTRL_SET;                           /**< EPDC Timing Control Engine Control Register, offset: 0x204 */
14427   __IO  uint32_t TCE_CTRL_CLR;                           /**< EPDC Timing Control Engine Control Register, offset: 0x208 */
14428   __IO  uint32_t TCE_CTRL_TOG;                           /**< EPDC Timing Control Engine Control Register, offset: 0x20C */
14429   uint8_t RESERVED_17[16];
14430   __IO  uint32_t TCE_SDCFG;                              /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x220 */
14431   __IO  uint32_t TCE_SDCFG_SET;                          /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x224 */
14432   __IO  uint32_t TCE_SDCFG_CLR;                          /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x228 */
14433   __IO  uint32_t TCE_SDCFG_TOG;                          /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x22C */
14434   uint8_t RESERVED_18[16];
14435   __IO  uint32_t TCE_GDCFG;                              /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x240 */
14436   __IO  uint32_t TCE_GDCFG_SET;                          /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x244 */
14437   __IO  uint32_t TCE_GDCFG_CLR;                          /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x248 */
14438   __IO  uint32_t TCE_GDCFG_TOG;                          /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x24C */
14439   uint8_t RESERVED_19[16];
14440   __IO  uint32_t TCE_HSCAN1;                             /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x260 */
14441   __IO  uint32_t TCE_HSCAN1_SET;                         /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x264 */
14442   __IO  uint32_t TCE_HSCAN1_CLR;                         /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x268 */
14443   __IO  uint32_t TCE_HSCAN1_TOG;                         /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x26C */
14444   uint8_t RESERVED_20[16];
14445   __IO  uint32_t TCE_HSCAN2;                             /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x280 */
14446   __IO  uint32_t TCE_HSCAN2_SET;                         /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x284 */
14447   __IO  uint32_t TCE_HSCAN2_CLR;                         /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x288 */
14448   __IO  uint32_t TCE_HSCAN2_TOG;                         /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x28C */
14449   uint8_t RESERVED_21[16];
14450   __IO  uint32_t TCE_VSCAN;                              /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A0 */
14451   __IO  uint32_t TCE_VSCAN_SET;                          /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A4 */
14452   __IO  uint32_t TCE_VSCAN_CLR;                          /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A8 */
14453   __IO  uint32_t TCE_VSCAN_TOG;                          /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2AC */
14454   uint8_t RESERVED_22[16];
14455   __IO  uint32_t TCE_OE;                                 /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C0 */
14456   __IO  uint32_t TCE_OE_SET;                             /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C4 */
14457   __IO  uint32_t TCE_OE_CLR;                             /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C8 */
14458   __IO  uint32_t TCE_OE_TOG;                             /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2CC */
14459   uint8_t RESERVED_23[16];
14460   __IO  uint32_t TCE_POLARITY;                           /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E0 */
14461   __IO  uint32_t TCE_POLARITY_SET;                       /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E4 */
14462   __IO  uint32_t TCE_POLARITY_CLR;                       /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E8 */
14463   __IO  uint32_t TCE_POLARITY_TOG;                       /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2EC */
14464   uint8_t RESERVED_24[16];
14465   __IO  uint32_t TCE_TIMING1;                            /**< EPDC Timing Control Engine Timing Register 1, offset: 0x300 */
14466   __IO  uint32_t TCE_TIMING1_SET;                        /**< EPDC Timing Control Engine Timing Register 1, offset: 0x304 */
14467   __IO  uint32_t TCE_TIMING1_CLR;                        /**< EPDC Timing Control Engine Timing Register 1, offset: 0x308 */
14468   __IO  uint32_t TCE_TIMING1_TOG;                        /**< EPDC Timing Control Engine Timing Register 1, offset: 0x30C */
14469   __IO  uint32_t TCE_TIMING2;                            /**< EPDC Timing Control Engine Timing Register 2, offset: 0x310 */
14470   __IO  uint32_t TCE_TIMING2_SET;                        /**< EPDC Timing Control Engine Timing Register 2, offset: 0x314 */
14471   __IO  uint32_t TCE_TIMING2_CLR;                        /**< EPDC Timing Control Engine Timing Register 2, offset: 0x318 */
14472   __IO  uint32_t TCE_TIMING2_TOG;                        /**< EPDC Timing Control Engine Timing Register 2, offset: 0x31C */
14473   __IO  uint32_t TCE_TIMING3;                            /**< EPDC Timing Control Engine Timing Register 3, offset: 0x320 */
14474   __IO  uint32_t TCE_TIMING3_SET;                        /**< EPDC Timing Control Engine Timing Register 3, offset: 0x324 */
14475   __IO  uint32_t TCE_TIMING3_CLR;                        /**< EPDC Timing Control Engine Timing Register 3, offset: 0x328 */
14476   __IO  uint32_t TCE_TIMING3_TOG;                        /**< EPDC Timing Control Engine Timing Register 3, offset: 0x32C */
14477   uint8_t RESERVED_25[80];
14478   __IO  uint32_t PIGEON_CTRL0;                           /**< EPDC Pigeon Mode Control Register 0, offset: 0x380 */
14479   __IO  uint32_t PIGEON_CTRL0_SET;                       /**< EPDC Pigeon Mode Control Register 0, offset: 0x384 */
14480   __IO  uint32_t PIGEON_CTRL0_CLR;                       /**< EPDC Pigeon Mode Control Register 0, offset: 0x388 */
14481   __IO  uint32_t PIGEON_CTRL0_TOG;                       /**< EPDC Pigeon Mode Control Register 0, offset: 0x38C */
14482   __IO  uint32_t PIGEON_CTRL1;                           /**< EPDC Pigeon Mode Control Register 1, offset: 0x390 */
14483   __IO  uint32_t PIGEON_CTRL1_SET;                       /**< EPDC Pigeon Mode Control Register 1, offset: 0x394 */
14484   __IO  uint32_t PIGEON_CTRL1_CLR;                       /**< EPDC Pigeon Mode Control Register 1, offset: 0x398 */
14485   __IO  uint32_t PIGEON_CTRL1_TOG;                       /**< EPDC Pigeon Mode Control Register 1, offset: 0x39C */
14486   uint8_t RESERVED_26[32];
14487   __IO  uint32_t IRQ_MASK1;                              /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C0 */
14488   __IO  uint32_t IRQ_MASK1_SET;                          /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C4 */
14489   __IO  uint32_t IRQ_MASK1_CLR;                          /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C8 */
14490   __IO  uint32_t IRQ_MASK1_TOG;                          /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3CC */
14491   __IO  uint32_t IRQ_MASK2;                              /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3D0 */
14492   __IO  uint32_t IRQ_MASK2_SET;                          /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3D4 */
14493   __IO  uint32_t IRQ_MASK2_CLR;                          /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3D8 */
14494   __IO  uint32_t IRQ_MASK2_TOG;                          /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3DC */
14495   __IO  uint32_t IRQ1;                                   /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3E0 */
14496   __IO  uint32_t IRQ1_SET;                               /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3E4 */
14497   __IO  uint32_t IRQ1_CLR;                               /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3E8 */
14498   __IO  uint32_t IRQ1_TOG;                               /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3EC */
14499   __IO  uint32_t IRQ2;                                   /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3F0 */
14500   __IO  uint32_t IRQ2_SET;                               /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3F4 */
14501   __IO  uint32_t IRQ2_CLR;                               /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3F8 */
14502   __IO  uint32_t IRQ2_TOG;                               /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3FC */
14503   __IO  uint32_t IRQ_MASK;                               /**< EPDC IRQ Mask Register, offset: 0x400 */
14504   __IO  uint32_t IRQ_MASK_SET;                           /**< EPDC IRQ Mask Register, offset: 0x404 */
14505   __IO  uint32_t IRQ_MASK_CLR;                           /**< EPDC IRQ Mask Register, offset: 0x408 */
14506   __IO  uint32_t IRQ_MASK_TOG;                           /**< EPDC IRQ Mask Register, offset: 0x40C */
14507   uint8_t RESERVED_27[16];
14508   __IO  uint32_t IRQ;                                    /**< EPDC Interrupt Register, offset: 0x420 */
14509   __IO  uint32_t IRQ_SET;                                /**< EPDC Interrupt Register, offset: 0x424 */
14510   __IO  uint32_t IRQ_CLR;                                /**< EPDC Interrupt Register, offset: 0x428 */
14511   __IO  uint32_t IRQ_TOG;                                /**< EPDC Interrupt Register, offset: 0x42C */
14512   uint8_t RESERVED_28[16];
14513   __IO  uint32_t STATUS_LUTS1;                           /**< EPDC Status Register - LUTs, offset: 0x440 */
14514   __IO  uint32_t STATUS_LUTS1_SET;                       /**< EPDC Status Register - LUTs, offset: 0x444 */
14515   __IO  uint32_t STATUS_LUTS1_CLR;                       /**< EPDC Status Register - LUTs, offset: 0x448 */
14516   __IO  uint32_t STATUS_LUTS1_TOG;                       /**< EPDC Status Register - LUTs, offset: 0x44C */
14517   __IO  uint32_t STATUS_LUTS2;                           /**< EPDC Status Register - LUTs, offset: 0x450 */
14518   __IO  uint32_t STATUS_LUTS2_SET;                       /**< EPDC Status Register - LUTs, offset: 0x454 */
14519   __IO  uint32_t STATUS_LUTS2_CLR;                       /**< EPDC Status Register - LUTs, offset: 0x458 */
14520   __IO  uint32_t STATUS_LUTS2_TOG;                       /**< EPDC Status Register - LUTs, offset: 0x45C */
14521   __IO  uint32_t STATUS_NEXTLUT;                         /**< EPDC Status Register - Next Available LUT, offset: 0x460 */
14522   uint8_t RESERVED_29[28];
14523   __IO  uint32_t STATUS_COL1;                            /**< EPDC LUT Collision Status, offset: 0x480 */
14524   __IO  uint32_t STATUS_COL1_SET;                        /**< EPDC LUT Collision Status, offset: 0x484 */
14525   __IO  uint32_t STATUS_COL1_CLR;                        /**< EPDC LUT Collision Status, offset: 0x488 */
14526   __IO  uint32_t STATUS_COL1_TOG;                        /**< EPDC LUT Collision Status, offset: 0x48C */
14527   __IO  uint32_t STATUS_COL2;                            /**< EPDC LUT Collision Status, offset: 0x490 */
14528   __IO  uint32_t STATUS_COL2_SET;                        /**< EPDC LUT Collision Status, offset: 0x494 */
14529   __IO  uint32_t STATUS_COL2_CLR;                        /**< EPDC LUT Collision Status, offset: 0x498 */
14530   __IO  uint32_t STATUS_COL2_TOG;                        /**< EPDC LUT Collision Status, offset: 0x49C */
14531   __I   uint32_t STATUS;                                 /**< EPDC General Status Register, offset: 0x4A0 */
14532   __I   uint32_t STATUS_SET;                             /**< EPDC General Status Register, offset: 0x4A4 */
14533   __I   uint32_t STATUS_CLR;                             /**< EPDC General Status Register, offset: 0x4A8 */
14534   __I   uint32_t STATUS_TOG;                             /**< EPDC General Status Register, offset: 0x4AC */
14535   uint8_t RESERVED_30[16];
14536   __IO  uint32_t UPD_COL_CORD;                           /**< EPDC Collision Region Co-ordinate, offset: 0x4C0 */
14537   uint8_t RESERVED_31[28];
14538   __IO  uint32_t UPD_COL_SIZE;                           /**< EPDC Collision Region Size, offset: 0x4E0 */
14539   uint8_t RESERVED_32[284];
14540   __IO  uint32_t HIST1_PARAM;                            /**< 1-level Histogram Parameter Register., offset: 0x600 */
14541   uint8_t RESERVED_33[12];
14542   __IO  uint32_t HIST2_PARAM;                            /**< 2-level Histogram Parameter Register., offset: 0x610 */
14543   uint8_t RESERVED_34[12];
14544   __IO  uint32_t HIST4_PARAM;                            /**< 4-level Histogram Parameter Register., offset: 0x620 */
14545   uint8_t RESERVED_35[12];
14546   __IO  uint32_t HIST8_PARAM0;                           /**< 8-level Histogram Parameter 0 Register., offset: 0x630 */
14547   uint8_t RESERVED_36[12];
14548   __IO  uint32_t HIST8_PARAM1;                           /**< 8-level Histogram Parameter 1 Register., offset: 0x640 */
14549   uint8_t RESERVED_37[12];
14550   __IO  uint32_t HIST16_PARAM0;                          /**< 16-level Histogram Parameter 0 Register., offset: 0x650 */
14551   uint8_t RESERVED_38[12];
14552   __IO  uint32_t HIST16_PARAM1;                          /**< 16-level Histogram Parameter Register., offset: 0x660 */
14553   uint8_t RESERVED_39[12];
14554   __IO  uint32_t HIST16_PARAM2;                          /**< 16-level Histogram Parameter Register., offset: 0x670 */
14555   uint8_t RESERVED_40[12];
14556   __IO  uint32_t HIST16_PARAM3;                          /**< 16-level Histogram Parameter Register., offset: 0x680 */
14557   uint8_t RESERVED_41[124];
14558   __IO  uint32_t GPIO;                                   /**< EPDC General Purpose I/O Debug register, offset: 0x700 */
14559   __IO  uint32_t GPIO_SET;                               /**< EPDC General Purpose I/O Debug register, offset: 0x704 */
14560   __IO  uint32_t GPIO_CLR;                               /**< EPDC General Purpose I/O Debug register, offset: 0x708 */
14561   __IO  uint32_t GPIO_TOG;                               /**< EPDC General Purpose I/O Debug register, offset: 0x70C */
14562   uint8_t RESERVED_42[224];
14563   __IO  uint32_t VERSION;                                /**< EPDC Version Register, offset: 0x7F0 */
14564   uint8_t RESERVED_43[12];
14565   __IO  uint32_t PIGEON_0_0;                             /**< Panel Interface Signal Generator Register 0_0, offset: 0x800 */
14566   uint8_t RESERVED_44[12];
14567   __IO  uint32_t PIGEON_0_1;                             /**< Panel Interface Signal Generator Register 0_1, offset: 0x810 */
14568   uint8_t RESERVED_45[12];
14569   __IO  uint32_t PIGEON_0_2;                             /**< Panel Interface Signal Generator Register 0_1, offset: 0x820 */
14570   uint8_t RESERVED_46[28];
14571   __IO  uint32_t PIGEON_1_0;                             /**< Panel Interface Signal Generator Register 1_0, offset: 0x840 */
14572   uint8_t RESERVED_47[12];
14573   __IO  uint32_t PIGEON_1_1;                             /**< Panel Interface Signal Generator Register 1_1, offset: 0x850 */
14574   uint8_t RESERVED_48[12];
14575   __IO  uint32_t PIGEON_1_2;                             /**< Panel Interface Signal Generator Register 1_1, offset: 0x860 */
14576   uint8_t RESERVED_49[28];
14577   __IO  uint32_t PIGEON_2_0;                             /**< Panel Interface Signal Generator Register 2_0, offset: 0x880 */
14578   uint8_t RESERVED_50[12];
14579   __IO  uint32_t PIGEON_2_1;                             /**< Panel Interface Signal Generator Register 2_1, offset: 0x890 */
14580   uint8_t RESERVED_51[12];
14581   __IO  uint32_t PIGEON_2_2;                             /**< Panel Interface Signal Generator Register 2_1, offset: 0x8A0 */
14582   uint8_t RESERVED_52[28];
14583   __IO  uint32_t PIGEON_3_0;                             /**< Panel Interface Signal Generator Register 3_0, offset: 0x8C0 */
14584   uint8_t RESERVED_53[12];
14585   __IO  uint32_t PIGEON_3_1;                             /**< Panel Interface Signal Generator Register 3_1, offset: 0x8D0 */
14586   uint8_t RESERVED_54[12];
14587   __IO  uint32_t PIGEON_3_2;                             /**< Panel Interface Signal Generator Register 3_1, offset: 0x8E0 */
14588   uint8_t RESERVED_55[28];
14589   __IO  uint32_t PIGEON_4_0;                             /**< Panel Interface Signal Generator Register 4_0, offset: 0x900 */
14590   uint8_t RESERVED_56[12];
14591   __IO  uint32_t PIGEON_4_1;                             /**< Panel Interface Signal Generator Register 4_1, offset: 0x910 */
14592   uint8_t RESERVED_57[12];
14593   __IO  uint32_t PIGEON_4_2;                             /**< Panel Interface Signal Generator Register 4_1, offset: 0x920 */
14594   uint8_t RESERVED_58[28];
14595   __IO  uint32_t PIGEON_5_0;                             /**< Panel Interface Signal Generator Register 5_0, offset: 0x940 */
14596   uint8_t RESERVED_59[12];
14597   __IO  uint32_t PIGEON_5_1;                             /**< Panel Interface Signal Generator Register 5_1, offset: 0x950 */
14598   uint8_t RESERVED_60[12];
14599   __IO  uint32_t PIGEON_5_2;                             /**< Panel Interface Signal Generator Register 5_1, offset: 0x960 */
14600   uint8_t RESERVED_61[28];
14601   __IO  uint32_t PIGEON_6_0;                             /**< Panel Interface Signal Generator Register 6_0, offset: 0x980 */
14602   uint8_t RESERVED_62[12];
14603   __IO  uint32_t PIGEON_6_1;                             /**< Panel Interface Signal Generator Register 6_1, offset: 0x990 */
14604   uint8_t RESERVED_63[12];
14605   __IO  uint32_t PIGEON_6_2;                             /**< Panel Interface Signal Generator Register 6_1, offset: 0x9A0 */
14606   uint8_t RESERVED_64[28];
14607   __IO  uint32_t PIGEON_7_0;                             /**< Panel Interface Signal Generator Register 7_0, offset: 0x9C0 */
14608   uint8_t RESERVED_65[12];
14609   __IO  uint32_t PIGEON_7_1;                             /**< Panel Interface Signal Generator Register 7_1, offset: 0x9D0 */
14610   uint8_t RESERVED_66[12];
14611   __IO  uint32_t PIGEON_7_2;                             /**< Panel Interface Signal Generator Register 7_1, offset: 0x9E0 */
14612   uint8_t RESERVED_67[28];
14613   __IO  uint32_t PIGEON_8_0;                             /**< Panel Interface Signal Generator Register 8_0, offset: 0xA00 */
14614   uint8_t RESERVED_68[12];
14615   __IO  uint32_t PIGEON_8_1;                             /**< Panel Interface Signal Generator Register 8_1, offset: 0xA10 */
14616   uint8_t RESERVED_69[12];
14617   __IO  uint32_t PIGEON_8_2;                             /**< Panel Interface Signal Generator Register 8_1, offset: 0xA20 */
14618   uint8_t RESERVED_70[28];
14619   __IO  uint32_t PIGEON_9_0;                             /**< Panel Interface Signal Generator Register 9_0, offset: 0xA40 */
14620   uint8_t RESERVED_71[12];
14621   __IO  uint32_t PIGEON_9_1;                             /**< Panel Interface Signal Generator Register 9_1, offset: 0xA50 */
14622   uint8_t RESERVED_72[12];
14623   __IO  uint32_t PIGEON_9_2;                             /**< Panel Interface Signal Generator Register 9_1, offset: 0xA60 */
14624   uint8_t RESERVED_73[28];
14625   __IO  uint32_t PIGEON_10_0;                            /**< Panel Interface Signal Generator Register 10_0, offset: 0xA80 */
14626   uint8_t RESERVED_74[12];
14627   __IO  uint32_t PIGEON_10_1;                            /**< Panel Interface Signal Generator Register 10_1, offset: 0xA90 */
14628   uint8_t RESERVED_75[12];
14629   __IO  uint32_t PIGEON_10_2;                            /**< Panel Interface Signal Generator Register 10_1, offset: 0xAA0 */
14630   uint8_t RESERVED_76[28];
14631   __IO  uint32_t PIGEON_11_0;                            /**< Panel Interface Signal Generator Register 11_0, offset: 0xAC0 */
14632   uint8_t RESERVED_77[12];
14633   __IO  uint32_t PIGEON_11_1;                            /**< Panel Interface Signal Generator Register 11_1, offset: 0xAD0 */
14634   uint8_t RESERVED_78[12];
14635   __IO  uint32_t PIGEON_11_2;                            /**< Panel Interface Signal Generator Register 11_1, offset: 0xAE0 */
14636   uint8_t RESERVED_79[28];
14637   __IO  uint32_t PIGEON_12_0;                            /**< Panel Interface Signal Generator Register 12_0, offset: 0xB00 */
14638   uint8_t RESERVED_80[12];
14639   __IO  uint32_t PIGEON_12_1;                            /**< Panel Interface Signal Generator Register 12_1, offset: 0xB10 */
14640   uint8_t RESERVED_81[12];
14641   __IO  uint32_t PIGEON_12_2;                            /**< Panel Interface Signal Generator Register 12_1, offset: 0xB20 */
14642   uint8_t RESERVED_82[28];
14643   __IO  uint32_t PIGEON_13_0;                            /**< Panel Interface Signal Generator Register 13_0, offset: 0xB40 */
14644   uint8_t RESERVED_83[12];
14645   __IO  uint32_t PIGEON_13_1;                            /**< Panel Interface Signal Generator Register 13_1, offset: 0xB50 */
14646   uint8_t RESERVED_84[12];
14647   __IO  uint32_t PIGEON_13_2;                            /**< Panel Interface Signal Generator Register 13_1, offset: 0xB60 */
14648   uint8_t RESERVED_85[28];
14649   __IO  uint32_t PIGEON_14_0;                            /**< Panel Interface Signal Generator Register 14_0, offset: 0xB80 */
14650   uint8_t RESERVED_86[12];
14651   __IO  uint32_t PIGEON_14_1;                            /**< Panel Interface Signal Generator Register 14_1, offset: 0xB90 */
14652   uint8_t RESERVED_87[12];
14653   __IO  uint32_t PIGEON_14_2;                            /**< Panel Interface Signal Generator Register 14_1, offset: 0xBA0 */
14654   uint8_t RESERVED_88[28];
14655   __IO  uint32_t PIGEON_15_0;                            /**< Panel Interface Signal Generator Register 15_0, offset: 0xBC0 */
14656   uint8_t RESERVED_89[12];
14657   __IO  uint32_t PIGEON_15_1;                            /**< Panel Interface Signal Generator Register 15_1, offset: 0xBD0 */
14658   uint8_t RESERVED_90[12];
14659   __IO  uint32_t PIGEON_15_2;                            /**< Panel Interface Signal Generator Register 15_1, offset: 0xBE0 */
14660   uint8_t RESERVED_91[28];
14661   __IO  uint32_t PIGEON_16_0;                            /**< Panel Interface Signal Generator Register 16_0, offset: 0xC00 */
14662   uint8_t RESERVED_92[12];
14663   __IO  uint32_t PIGEON_16_1;                            /**< Panel Interface Signal Generator Register 16_1, offset: 0xC10 */
14664   uint8_t RESERVED_93[12];
14665   __IO  uint32_t PIGEON_16_2;                            /**< Panel Interface Signal Generator Register 16_1, offset: 0xC20 */
14666 } EPDC_Type, *EPDC_MemMapPtr;
14667 /* ----------------------------------------------------------------------------
14668    -- EPDC - Register accessor macros
14669    ---------------------------------------------------------------------------- */
14670 
14671 /*!
14672  * @addtogroup EPDC_Register_Accessor_Macros EPDC - Register accessor macros
14673  * @{
14674  */
14675 
14676 
14677 /* EPDC - Register accessors */
14678 #define EPDC_CTRL_REG(base)                      ((base)->CTRL)
14679 #define EPDC_CTRL_SET_REG(base)                  ((base)->CTRL_SET)
14680 #define EPDC_CTRL_CLR_REG(base)                  ((base)->CTRL_CLR)
14681 #define EPDC_CTRL_TOG_REG(base)                  ((base)->CTRL_TOG)
14682 #define EPDC_WB_ADDR_TCE_REG(base)               ((base)->WB_ADDR_TCE)
14683 #define EPDC_WVADDR_REG(base)                    ((base)->WVADDR)
14684 #define EPDC_WB_ADDR_REG(base)                   ((base)->WB_ADDR)
14685 #define EPDC_RES_REG(base)                       ((base)->RES)
14686 #define EPDC_FORMAT_REG(base)                    ((base)->FORMAT)
14687 #define EPDC_FORMAT_SET_REG(base)                ((base)->FORMAT_SET)
14688 #define EPDC_FORMAT_CLR_REG(base)                ((base)->FORMAT_CLR)
14689 #define EPDC_FORMAT_TOG_REG(base)                ((base)->FORMAT_TOG)
14690 #define EPDC_WB_FIELD0_REG(base)                 ((base)->WB_FIELD0)
14691 #define EPDC_WB_FIELD1_REG(base)                 ((base)->WB_FIELD1)
14692 #define EPDC_WB_FIELD2_REG(base)                 ((base)->WB_FIELD2)
14693 #define EPDC_WB_FIELD3_REG(base)                 ((base)->WB_FIELD3)
14694 #define EPDC_FIFOCTRL_REG(base)                  ((base)->FIFOCTRL)
14695 #define EPDC_FIFOCTRL_SET_REG(base)              ((base)->FIFOCTRL_SET)
14696 #define EPDC_FIFOCTRL_CLR_REG(base)              ((base)->FIFOCTRL_CLR)
14697 #define EPDC_FIFOCTRL_TOG_REG(base)              ((base)->FIFOCTRL_TOG)
14698 #define EPDC_UPD_ADDR_REG(base)                  ((base)->UPD_ADDR)
14699 #define EPDC_UPD_STRIDE_REG(base)                ((base)->UPD_STRIDE)
14700 #define EPDC_UPD_CORD_REG(base)                  ((base)->UPD_CORD)
14701 #define EPDC_UPD_SIZE_REG(base)                  ((base)->UPD_SIZE)
14702 #define EPDC_UPD_CTRL_REG(base)                  ((base)->UPD_CTRL)
14703 #define EPDC_UPD_CTRL_SET_REG(base)              ((base)->UPD_CTRL_SET)
14704 #define EPDC_UPD_CTRL_CLR_REG(base)              ((base)->UPD_CTRL_CLR)
14705 #define EPDC_UPD_CTRL_TOG_REG(base)              ((base)->UPD_CTRL_TOG)
14706 #define EPDC_UPD_FIXED_REG(base)                 ((base)->UPD_FIXED)
14707 #define EPDC_UPD_FIXED_SET_REG(base)             ((base)->UPD_FIXED_SET)
14708 #define EPDC_UPD_FIXED_CLR_REG(base)             ((base)->UPD_FIXED_CLR)
14709 #define EPDC_UPD_FIXED_TOG_REG(base)             ((base)->UPD_FIXED_TOG)
14710 #define EPDC_TEMP_REG(base)                      ((base)->TEMP)
14711 #define EPDC_AUTOWV_LUT_REG(base)                ((base)->AUTOWV_LUT)
14712 #define EPDC_LUT_STANDBY1_REG(base)              ((base)->LUT_STANDBY1)
14713 #define EPDC_LUT_STANDBY1_SET_REG(base)          ((base)->LUT_STANDBY1_SET)
14714 #define EPDC_LUT_STANDBY1_CLR_REG(base)          ((base)->LUT_STANDBY1_CLR)
14715 #define EPDC_LUT_STANDBY1_TOG_REG(base)          ((base)->LUT_STANDBY1_TOG)
14716 #define EPDC_LUT_STANDBY2_REG(base)              ((base)->LUT_STANDBY2)
14717 #define EPDC_LUT_STANDBY2_SET_REG(base)          ((base)->LUT_STANDBY2_SET)
14718 #define EPDC_LUT_STANDBY2_CLR_REG(base)          ((base)->LUT_STANDBY2_CLR)
14719 #define EPDC_LUT_STANDBY2_TOG_REG(base)          ((base)->LUT_STANDBY2_TOG)
14720 #define EPDC_TCE_CTRL_REG(base)                  ((base)->TCE_CTRL)
14721 #define EPDC_TCE_CTRL_SET_REG(base)              ((base)->TCE_CTRL_SET)
14722 #define EPDC_TCE_CTRL_CLR_REG(base)              ((base)->TCE_CTRL_CLR)
14723 #define EPDC_TCE_CTRL_TOG_REG(base)              ((base)->TCE_CTRL_TOG)
14724 #define EPDC_TCE_SDCFG_REG(base)                 ((base)->TCE_SDCFG)
14725 #define EPDC_TCE_SDCFG_SET_REG(base)             ((base)->TCE_SDCFG_SET)
14726 #define EPDC_TCE_SDCFG_CLR_REG(base)             ((base)->TCE_SDCFG_CLR)
14727 #define EPDC_TCE_SDCFG_TOG_REG(base)             ((base)->TCE_SDCFG_TOG)
14728 #define EPDC_TCE_GDCFG_REG(base)                 ((base)->TCE_GDCFG)
14729 #define EPDC_TCE_GDCFG_SET_REG(base)             ((base)->TCE_GDCFG_SET)
14730 #define EPDC_TCE_GDCFG_CLR_REG(base)             ((base)->TCE_GDCFG_CLR)
14731 #define EPDC_TCE_GDCFG_TOG_REG(base)             ((base)->TCE_GDCFG_TOG)
14732 #define EPDC_TCE_HSCAN1_REG(base)                ((base)->TCE_HSCAN1)
14733 #define EPDC_TCE_HSCAN1_SET_REG(base)            ((base)->TCE_HSCAN1_SET)
14734 #define EPDC_TCE_HSCAN1_CLR_REG(base)            ((base)->TCE_HSCAN1_CLR)
14735 #define EPDC_TCE_HSCAN1_TOG_REG(base)            ((base)->TCE_HSCAN1_TOG)
14736 #define EPDC_TCE_HSCAN2_REG(base)                ((base)->TCE_HSCAN2)
14737 #define EPDC_TCE_HSCAN2_SET_REG(base)            ((base)->TCE_HSCAN2_SET)
14738 #define EPDC_TCE_HSCAN2_CLR_REG(base)            ((base)->TCE_HSCAN2_CLR)
14739 #define EPDC_TCE_HSCAN2_TOG_REG(base)            ((base)->TCE_HSCAN2_TOG)
14740 #define EPDC_TCE_VSCAN_REG(base)                 ((base)->TCE_VSCAN)
14741 #define EPDC_TCE_VSCAN_SET_REG(base)             ((base)->TCE_VSCAN_SET)
14742 #define EPDC_TCE_VSCAN_CLR_REG(base)             ((base)->TCE_VSCAN_CLR)
14743 #define EPDC_TCE_VSCAN_TOG_REG(base)             ((base)->TCE_VSCAN_TOG)
14744 #define EPDC_TCE_OE_REG(base)                    ((base)->TCE_OE)
14745 #define EPDC_TCE_OE_SET_REG(base)                ((base)->TCE_OE_SET)
14746 #define EPDC_TCE_OE_CLR_REG(base)                ((base)->TCE_OE_CLR)
14747 #define EPDC_TCE_OE_TOG_REG(base)                ((base)->TCE_OE_TOG)
14748 #define EPDC_TCE_POLARITY_REG(base)              ((base)->TCE_POLARITY)
14749 #define EPDC_TCE_POLARITY_SET_REG(base)          ((base)->TCE_POLARITY_SET)
14750 #define EPDC_TCE_POLARITY_CLR_REG(base)          ((base)->TCE_POLARITY_CLR)
14751 #define EPDC_TCE_POLARITY_TOG_REG(base)          ((base)->TCE_POLARITY_TOG)
14752 #define EPDC_TCE_TIMING1_REG(base)               ((base)->TCE_TIMING1)
14753 #define EPDC_TCE_TIMING1_SET_REG(base)           ((base)->TCE_TIMING1_SET)
14754 #define EPDC_TCE_TIMING1_CLR_REG(base)           ((base)->TCE_TIMING1_CLR)
14755 #define EPDC_TCE_TIMING1_TOG_REG(base)           ((base)->TCE_TIMING1_TOG)
14756 #define EPDC_TCE_TIMING2_REG(base)               ((base)->TCE_TIMING2)
14757 #define EPDC_TCE_TIMING2_SET_REG(base)           ((base)->TCE_TIMING2_SET)
14758 #define EPDC_TCE_TIMING2_CLR_REG(base)           ((base)->TCE_TIMING2_CLR)
14759 #define EPDC_TCE_TIMING2_TOG_REG(base)           ((base)->TCE_TIMING2_TOG)
14760 #define EPDC_TCE_TIMING3_REG(base)               ((base)->TCE_TIMING3)
14761 #define EPDC_TCE_TIMING3_SET_REG(base)           ((base)->TCE_TIMING3_SET)
14762 #define EPDC_TCE_TIMING3_CLR_REG(base)           ((base)->TCE_TIMING3_CLR)
14763 #define EPDC_TCE_TIMING3_TOG_REG(base)           ((base)->TCE_TIMING3_TOG)
14764 #define EPDC_PIGEON_CTRL0_REG(base)              ((base)->PIGEON_CTRL0)
14765 #define EPDC_PIGEON_CTRL0_SET_REG(base)          ((base)->PIGEON_CTRL0_SET)
14766 #define EPDC_PIGEON_CTRL0_CLR_REG(base)          ((base)->PIGEON_CTRL0_CLR)
14767 #define EPDC_PIGEON_CTRL0_TOG_REG(base)          ((base)->PIGEON_CTRL0_TOG)
14768 #define EPDC_PIGEON_CTRL1_REG(base)              ((base)->PIGEON_CTRL1)
14769 #define EPDC_PIGEON_CTRL1_SET_REG(base)          ((base)->PIGEON_CTRL1_SET)
14770 #define EPDC_PIGEON_CTRL1_CLR_REG(base)          ((base)->PIGEON_CTRL1_CLR)
14771 #define EPDC_PIGEON_CTRL1_TOG_REG(base)          ((base)->PIGEON_CTRL1_TOG)
14772 #define EPDC_IRQ_MASK1_REG(base)                 ((base)->IRQ_MASK1)
14773 #define EPDC_IRQ_MASK1_SET_REG(base)             ((base)->IRQ_MASK1_SET)
14774 #define EPDC_IRQ_MASK1_CLR_REG(base)             ((base)->IRQ_MASK1_CLR)
14775 #define EPDC_IRQ_MASK1_TOG_REG(base)             ((base)->IRQ_MASK1_TOG)
14776 #define EPDC_IRQ_MASK2_REG(base)                 ((base)->IRQ_MASK2)
14777 #define EPDC_IRQ_MASK2_SET_REG(base)             ((base)->IRQ_MASK2_SET)
14778 #define EPDC_IRQ_MASK2_CLR_REG(base)             ((base)->IRQ_MASK2_CLR)
14779 #define EPDC_IRQ_MASK2_TOG_REG(base)             ((base)->IRQ_MASK2_TOG)
14780 #define EPDC_IRQ1_REG(base)                      ((base)->IRQ1)
14781 #define EPDC_IRQ1_SET_REG(base)                  ((base)->IRQ1_SET)
14782 #define EPDC_IRQ1_CLR_REG(base)                  ((base)->IRQ1_CLR)
14783 #define EPDC_IRQ1_TOG_REG(base)                  ((base)->IRQ1_TOG)
14784 #define EPDC_IRQ2_REG(base)                      ((base)->IRQ2)
14785 #define EPDC_IRQ2_SET_REG(base)                  ((base)->IRQ2_SET)
14786 #define EPDC_IRQ2_CLR_REG(base)                  ((base)->IRQ2_CLR)
14787 #define EPDC_IRQ2_TOG_REG(base)                  ((base)->IRQ2_TOG)
14788 #define EPDC_IRQ_MASK_REG(base)                  ((base)->IRQ_MASK)
14789 #define EPDC_IRQ_MASK_SET_REG(base)              ((base)->IRQ_MASK_SET)
14790 #define EPDC_IRQ_MASK_CLR_REG(base)              ((base)->IRQ_MASK_CLR)
14791 #define EPDC_IRQ_MASK_TOG_REG(base)              ((base)->IRQ_MASK_TOG)
14792 #define EPDC_IRQ_REG(base)                       ((base)->IRQ)
14793 #define EPDC_IRQ_SET_REG(base)                   ((base)->IRQ_SET)
14794 #define EPDC_IRQ_CLR_REG(base)                   ((base)->IRQ_CLR)
14795 #define EPDC_IRQ_TOG_REG(base)                   ((base)->IRQ_TOG)
14796 #define EPDC_STATUS_LUTS1_REG(base)              ((base)->STATUS_LUTS1)
14797 #define EPDC_STATUS_LUTS1_SET_REG(base)          ((base)->STATUS_LUTS1_SET)
14798 #define EPDC_STATUS_LUTS1_CLR_REG(base)          ((base)->STATUS_LUTS1_CLR)
14799 #define EPDC_STATUS_LUTS1_TOG_REG(base)          ((base)->STATUS_LUTS1_TOG)
14800 #define EPDC_STATUS_LUTS2_REG(base)              ((base)->STATUS_LUTS2)
14801 #define EPDC_STATUS_LUTS2_SET_REG(base)          ((base)->STATUS_LUTS2_SET)
14802 #define EPDC_STATUS_LUTS2_CLR_REG(base)          ((base)->STATUS_LUTS2_CLR)
14803 #define EPDC_STATUS_LUTS2_TOG_REG(base)          ((base)->STATUS_LUTS2_TOG)
14804 #define EPDC_STATUS_NEXTLUT_REG(base)            ((base)->STATUS_NEXTLUT)
14805 #define EPDC_STATUS_COL1_REG(base)               ((base)->STATUS_COL1)
14806 #define EPDC_STATUS_COL1_SET_REG(base)           ((base)->STATUS_COL1_SET)
14807 #define EPDC_STATUS_COL1_CLR_REG(base)           ((base)->STATUS_COL1_CLR)
14808 #define EPDC_STATUS_COL1_TOG_REG(base)           ((base)->STATUS_COL1_TOG)
14809 #define EPDC_STATUS_COL2_REG(base)               ((base)->STATUS_COL2)
14810 #define EPDC_STATUS_COL2_SET_REG(base)           ((base)->STATUS_COL2_SET)
14811 #define EPDC_STATUS_COL2_CLR_REG(base)           ((base)->STATUS_COL2_CLR)
14812 #define EPDC_STATUS_COL2_TOG_REG(base)           ((base)->STATUS_COL2_TOG)
14813 #define EPDC_STATUS_REG(base)                    ((base)->STATUS)
14814 #define EPDC_STATUS_SET_REG(base)                ((base)->STATUS_SET)
14815 #define EPDC_STATUS_CLR_REG(base)                ((base)->STATUS_CLR)
14816 #define EPDC_STATUS_TOG_REG(base)                ((base)->STATUS_TOG)
14817 #define EPDC_UPD_COL_CORD_REG(base)              ((base)->UPD_COL_CORD)
14818 #define EPDC_UPD_COL_SIZE_REG(base)              ((base)->UPD_COL_SIZE)
14819 #define EPDC_HIST1_PARAM_REG(base)               ((base)->HIST1_PARAM)
14820 #define EPDC_HIST2_PARAM_REG(base)               ((base)->HIST2_PARAM)
14821 #define EPDC_HIST4_PARAM_REG(base)               ((base)->HIST4_PARAM)
14822 #define EPDC_HIST8_PARAM0_REG(base)              ((base)->HIST8_PARAM0)
14823 #define EPDC_HIST8_PARAM1_REG(base)              ((base)->HIST8_PARAM1)
14824 #define EPDC_HIST16_PARAM0_REG(base)             ((base)->HIST16_PARAM0)
14825 #define EPDC_HIST16_PARAM1_REG(base)             ((base)->HIST16_PARAM1)
14826 #define EPDC_HIST16_PARAM2_REG(base)             ((base)->HIST16_PARAM2)
14827 #define EPDC_HIST16_PARAM3_REG(base)             ((base)->HIST16_PARAM3)
14828 #define EPDC_GPIO_REG(base)                      ((base)->GPIO)
14829 #define EPDC_GPIO_SET_REG(base)                  ((base)->GPIO_SET)
14830 #define EPDC_GPIO_CLR_REG(base)                  ((base)->GPIO_CLR)
14831 #define EPDC_GPIO_TOG_REG(base)                  ((base)->GPIO_TOG)
14832 #define EPDC_VERSION_REG(base)                   ((base)->VERSION)
14833 #define EPDC_PIGEON_0_0_REG(base)                ((base)->PIGEON_0_0)
14834 #define EPDC_PIGEON_0_1_REG(base)                ((base)->PIGEON_0_1)
14835 #define EPDC_PIGEON_0_2_REG(base)                ((base)->PIGEON_0_2)
14836 #define EPDC_PIGEON_1_0_REG(base)                ((base)->PIGEON_1_0)
14837 #define EPDC_PIGEON_1_1_REG(base)                ((base)->PIGEON_1_1)
14838 #define EPDC_PIGEON_1_2_REG(base)                ((base)->PIGEON_1_2)
14839 #define EPDC_PIGEON_2_0_REG(base)                ((base)->PIGEON_2_0)
14840 #define EPDC_PIGEON_2_1_REG(base)                ((base)->PIGEON_2_1)
14841 #define EPDC_PIGEON_2_2_REG(base)                ((base)->PIGEON_2_2)
14842 #define EPDC_PIGEON_3_0_REG(base)                ((base)->PIGEON_3_0)
14843 #define EPDC_PIGEON_3_1_REG(base)                ((base)->PIGEON_3_1)
14844 #define EPDC_PIGEON_3_2_REG(base)                ((base)->PIGEON_3_2)
14845 #define EPDC_PIGEON_4_0_REG(base)                ((base)->PIGEON_4_0)
14846 #define EPDC_PIGEON_4_1_REG(base)                ((base)->PIGEON_4_1)
14847 #define EPDC_PIGEON_4_2_REG(base)                ((base)->PIGEON_4_2)
14848 #define EPDC_PIGEON_5_0_REG(base)                ((base)->PIGEON_5_0)
14849 #define EPDC_PIGEON_5_1_REG(base)                ((base)->PIGEON_5_1)
14850 #define EPDC_PIGEON_5_2_REG(base)                ((base)->PIGEON_5_2)
14851 #define EPDC_PIGEON_6_0_REG(base)                ((base)->PIGEON_6_0)
14852 #define EPDC_PIGEON_6_1_REG(base)                ((base)->PIGEON_6_1)
14853 #define EPDC_PIGEON_6_2_REG(base)                ((base)->PIGEON_6_2)
14854 #define EPDC_PIGEON_7_0_REG(base)                ((base)->PIGEON_7_0)
14855 #define EPDC_PIGEON_7_1_REG(base)                ((base)->PIGEON_7_1)
14856 #define EPDC_PIGEON_7_2_REG(base)                ((base)->PIGEON_7_2)
14857 #define EPDC_PIGEON_8_0_REG(base)                ((base)->PIGEON_8_0)
14858 #define EPDC_PIGEON_8_1_REG(base)                ((base)->PIGEON_8_1)
14859 #define EPDC_PIGEON_8_2_REG(base)                ((base)->PIGEON_8_2)
14860 #define EPDC_PIGEON_9_0_REG(base)                ((base)->PIGEON_9_0)
14861 #define EPDC_PIGEON_9_1_REG(base)                ((base)->PIGEON_9_1)
14862 #define EPDC_PIGEON_9_2_REG(base)                ((base)->PIGEON_9_2)
14863 #define EPDC_PIGEON_10_0_REG(base)               ((base)->PIGEON_10_0)
14864 #define EPDC_PIGEON_10_1_REG(base)               ((base)->PIGEON_10_1)
14865 #define EPDC_PIGEON_10_2_REG(base)               ((base)->PIGEON_10_2)
14866 #define EPDC_PIGEON_11_0_REG(base)               ((base)->PIGEON_11_0)
14867 #define EPDC_PIGEON_11_1_REG(base)               ((base)->PIGEON_11_1)
14868 #define EPDC_PIGEON_11_2_REG(base)               ((base)->PIGEON_11_2)
14869 #define EPDC_PIGEON_12_0_REG(base)               ((base)->PIGEON_12_0)
14870 #define EPDC_PIGEON_12_1_REG(base)               ((base)->PIGEON_12_1)
14871 #define EPDC_PIGEON_12_2_REG(base)               ((base)->PIGEON_12_2)
14872 #define EPDC_PIGEON_13_0_REG(base)               ((base)->PIGEON_13_0)
14873 #define EPDC_PIGEON_13_1_REG(base)               ((base)->PIGEON_13_1)
14874 #define EPDC_PIGEON_13_2_REG(base)               ((base)->PIGEON_13_2)
14875 #define EPDC_PIGEON_14_0_REG(base)               ((base)->PIGEON_14_0)
14876 #define EPDC_PIGEON_14_1_REG(base)               ((base)->PIGEON_14_1)
14877 #define EPDC_PIGEON_14_2_REG(base)               ((base)->PIGEON_14_2)
14878 #define EPDC_PIGEON_15_0_REG(base)               ((base)->PIGEON_15_0)
14879 #define EPDC_PIGEON_15_1_REG(base)               ((base)->PIGEON_15_1)
14880 #define EPDC_PIGEON_15_2_REG(base)               ((base)->PIGEON_15_2)
14881 #define EPDC_PIGEON_16_0_REG(base)               ((base)->PIGEON_16_0)
14882 #define EPDC_PIGEON_16_1_REG(base)               ((base)->PIGEON_16_1)
14883 #define EPDC_PIGEON_16_2_REG(base)               ((base)->PIGEON_16_2)
14884 
14885 /*!
14886  * @}
14887  */ /* end of group EPDC_Register_Accessor_Macros */
14888 /* ----------------------------------------------------------------------------
14889    -- EPDC Register Masks
14890    ---------------------------------------------------------------------------- */
14891 
14892 /*!
14893  * @addtogroup EPDC_Register_Masks EPDC Register Masks
14894  * @{
14895  */
14896 
14897 /* CTRL Bit Fields */
14898 #define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK          0x30u
14899 #define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT         4
14900 #define EPDC_CTRL_LUT_DATA_SWIZZLE(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_LUT_DATA_SWIZZLE_MASK)
14901 #define EPDC_CTRL_UPD_DATA_SWIZZLE_MASK          0xC0u
14902 #define EPDC_CTRL_UPD_DATA_SWIZZLE_SHIFT         6
14903 #define EPDC_CTRL_UPD_DATA_SWIZZLE(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_UPD_DATA_SWIZZLE_MASK)
14904 #define EPDC_CTRL_CLKGATE_MASK                   0x40000000u
14905 #define EPDC_CTRL_CLKGATE_SHIFT                  30
14906 #define EPDC_CTRL_SFTRST_MASK                    0x80000000u
14907 #define EPDC_CTRL_SFTRST_SHIFT                   31
14908 /* CTRL_SET Bit Fields */
14909 #define EPDC_CTRL_SET_LUT_DATA_SWIZZLE_MASK      0x30u
14910 #define EPDC_CTRL_SET_LUT_DATA_SWIZZLE_SHIFT     4
14911 #define EPDC_CTRL_SET_LUT_DATA_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_SET_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_SET_LUT_DATA_SWIZZLE_MASK)
14912 #define EPDC_CTRL_SET_UPD_DATA_SWIZZLE_MASK      0xC0u
14913 #define EPDC_CTRL_SET_UPD_DATA_SWIZZLE_SHIFT     6
14914 #define EPDC_CTRL_SET_UPD_DATA_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_SET_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_SET_UPD_DATA_SWIZZLE_MASK)
14915 #define EPDC_CTRL_SET_CLKGATE_MASK               0x40000000u
14916 #define EPDC_CTRL_SET_CLKGATE_SHIFT              30
14917 #define EPDC_CTRL_SET_SFTRST_MASK                0x80000000u
14918 #define EPDC_CTRL_SET_SFTRST_SHIFT               31
14919 /* CTRL_CLR Bit Fields */
14920 #define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_MASK      0x30u
14921 #define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_SHIFT     4
14922 #define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_MASK)
14923 #define EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_MASK      0xC0u
14924 #define EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_SHIFT     6
14925 #define EPDC_CTRL_CLR_UPD_DATA_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_MASK)
14926 #define EPDC_CTRL_CLR_CLKGATE_MASK               0x40000000u
14927 #define EPDC_CTRL_CLR_CLKGATE_SHIFT              30
14928 #define EPDC_CTRL_CLR_SFTRST_MASK                0x80000000u
14929 #define EPDC_CTRL_CLR_SFTRST_SHIFT               31
14930 /* CTRL_TOG Bit Fields */
14931 #define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_MASK      0x30u
14932 #define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_SHIFT     4
14933 #define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_MASK)
14934 #define EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_MASK      0xC0u
14935 #define EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_SHIFT     6
14936 #define EPDC_CTRL_TOG_UPD_DATA_SWIZZLE(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_MASK)
14937 #define EPDC_CTRL_TOG_CLKGATE_MASK               0x40000000u
14938 #define EPDC_CTRL_TOG_CLKGATE_SHIFT              30
14939 #define EPDC_CTRL_TOG_SFTRST_MASK                0x80000000u
14940 #define EPDC_CTRL_TOG_SFTRST_SHIFT               31
14941 /* WB_ADDR_TCE Bit Fields */
14942 #define EPDC_WB_ADDR_TCE_ADDR_MASK               0xFFFFFFFFu
14943 #define EPDC_WB_ADDR_TCE_ADDR_SHIFT              0
14944 #define EPDC_WB_ADDR_TCE_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_WB_ADDR_TCE_ADDR_SHIFT))&EPDC_WB_ADDR_TCE_ADDR_MASK)
14945 /* WVADDR Bit Fields */
14946 #define EPDC_WVADDR_ADDR_MASK                    0xFFFFFFFFu
14947 #define EPDC_WVADDR_ADDR_SHIFT                   0
14948 #define EPDC_WVADDR_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<EPDC_WVADDR_ADDR_SHIFT))&EPDC_WVADDR_ADDR_MASK)
14949 /* WB_ADDR Bit Fields */
14950 #define EPDC_WB_ADDR_ADDR_MASK                   0xFFFFFFFFu
14951 #define EPDC_WB_ADDR_ADDR_SHIFT                  0
14952 #define EPDC_WB_ADDR_ADDR(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_WB_ADDR_ADDR_SHIFT))&EPDC_WB_ADDR_ADDR_MASK)
14953 /* RES Bit Fields */
14954 #define EPDC_RES_HORIZONTAL_MASK                 0x1FFFu
14955 #define EPDC_RES_HORIZONTAL_SHIFT                0
14956 #define EPDC_RES_HORIZONTAL(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_RES_HORIZONTAL_SHIFT))&EPDC_RES_HORIZONTAL_MASK)
14957 #define EPDC_RES_VERTICAL_MASK                   0x1FFF0000u
14958 #define EPDC_RES_VERTICAL_SHIFT                  16
14959 #define EPDC_RES_VERTICAL(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_RES_VERTICAL_SHIFT))&EPDC_RES_VERTICAL_MASK)
14960 /* FORMAT Bit Fields */
14961 #define EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK        0x3u
14962 #define EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT       0
14963 #define EPDC_FORMAT_TFT_PIXEL_FORMAT(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK)
14964 #define EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK        0x700u
14965 #define EPDC_FORMAT_BUF_PIXEL_FORMAT_SHIFT       8
14966 #define EPDC_FORMAT_BUF_PIXEL_FORMAT(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK)
14967 #define EPDC_FORMAT_WB_COMPRESS_MASK             0x800u
14968 #define EPDC_FORMAT_WB_COMPRESS_SHIFT            11
14969 #define EPDC_FORMAT_WB_TYPE_MASK                 0x3000u
14970 #define EPDC_FORMAT_WB_TYPE_SHIFT                12
14971 #define EPDC_FORMAT_WB_TYPE(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_WB_TYPE_SHIFT))&EPDC_FORMAT_WB_TYPE_MASK)
14972 #define EPDC_FORMAT_WB_ADDR_NO_COPY_MASK         0x4000u
14973 #define EPDC_FORMAT_WB_ADDR_NO_COPY_SHIFT        14
14974 #define EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK       0xFF0000u
14975 #define EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT      16
14976 #define EPDC_FORMAT_DEFAULT_TFT_PIXEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK)
14977 #define EPDC_FORMAT_BUF_PIXEL_SCALE_MASK         0x1000000u
14978 #define EPDC_FORMAT_BUF_PIXEL_SCALE_SHIFT        24
14979 /* FORMAT_SET Bit Fields */
14980 #define EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_MASK    0x3u
14981 #define EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_SHIFT   0
14982 #define EPDC_FORMAT_SET_TFT_PIXEL_FORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_MASK)
14983 #define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_MASK    0x700u
14984 #define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_SHIFT   8
14985 #define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_MASK)
14986 #define EPDC_FORMAT_SET_WB_COMPRESS_MASK         0x800u
14987 #define EPDC_FORMAT_SET_WB_COMPRESS_SHIFT        11
14988 #define EPDC_FORMAT_SET_WB_TYPE_MASK             0x3000u
14989 #define EPDC_FORMAT_SET_WB_TYPE_SHIFT            12
14990 #define EPDC_FORMAT_SET_WB_TYPE(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_WB_TYPE_SHIFT))&EPDC_FORMAT_SET_WB_TYPE_MASK)
14991 #define EPDC_FORMAT_SET_WB_ADDR_NO_COPY_MASK     0x4000u
14992 #define EPDC_FORMAT_SET_WB_ADDR_NO_COPY_SHIFT    14
14993 #define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_MASK   0xFF0000u
14994 #define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_SHIFT  16
14995 #define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_MASK)
14996 #define EPDC_FORMAT_SET_BUF_PIXEL_SCALE_MASK     0x1000000u
14997 #define EPDC_FORMAT_SET_BUF_PIXEL_SCALE_SHIFT    24
14998 /* FORMAT_CLR Bit Fields */
14999 #define EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_MASK    0x3u
15000 #define EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_SHIFT   0
15001 #define EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_MASK)
15002 #define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_MASK    0x700u
15003 #define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_SHIFT   8
15004 #define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_MASK)
15005 #define EPDC_FORMAT_CLR_WB_COMPRESS_MASK         0x800u
15006 #define EPDC_FORMAT_CLR_WB_COMPRESS_SHIFT        11
15007 #define EPDC_FORMAT_CLR_WB_TYPE_MASK             0x3000u
15008 #define EPDC_FORMAT_CLR_WB_TYPE_SHIFT            12
15009 #define EPDC_FORMAT_CLR_WB_TYPE(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_WB_TYPE_SHIFT))&EPDC_FORMAT_CLR_WB_TYPE_MASK)
15010 #define EPDC_FORMAT_CLR_WB_ADDR_NO_COPY_MASK     0x4000u
15011 #define EPDC_FORMAT_CLR_WB_ADDR_NO_COPY_SHIFT    14
15012 #define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_MASK   0xFF0000u
15013 #define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_SHIFT  16
15014 #define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_MASK)
15015 #define EPDC_FORMAT_CLR_BUF_PIXEL_SCALE_MASK     0x1000000u
15016 #define EPDC_FORMAT_CLR_BUF_PIXEL_SCALE_SHIFT    24
15017 /* FORMAT_TOG Bit Fields */
15018 #define EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_MASK    0x3u
15019 #define EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_SHIFT   0
15020 #define EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_MASK)
15021 #define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_MASK    0x700u
15022 #define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_SHIFT   8
15023 #define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_MASK)
15024 #define EPDC_FORMAT_TOG_WB_COMPRESS_MASK         0x800u
15025 #define EPDC_FORMAT_TOG_WB_COMPRESS_SHIFT        11
15026 #define EPDC_FORMAT_TOG_WB_TYPE_MASK             0x3000u
15027 #define EPDC_FORMAT_TOG_WB_TYPE_SHIFT            12
15028 #define EPDC_FORMAT_TOG_WB_TYPE(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_WB_TYPE_SHIFT))&EPDC_FORMAT_TOG_WB_TYPE_MASK)
15029 #define EPDC_FORMAT_TOG_WB_ADDR_NO_COPY_MASK     0x4000u
15030 #define EPDC_FORMAT_TOG_WB_ADDR_NO_COPY_SHIFT    14
15031 #define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_MASK   0xFF0000u
15032 #define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_SHIFT  16
15033 #define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_MASK)
15034 #define EPDC_FORMAT_TOG_BUF_PIXEL_SCALE_MASK     0x1000000u
15035 #define EPDC_FORMAT_TOG_BUF_PIXEL_SCALE_SHIFT    24
15036 /* WB_FIELD0 Bit Fields */
15037 #define EPDC_WB_FIELD0_LEN_MASK                  0xFu
15038 #define EPDC_WB_FIELD0_LEN_SHIFT                 0
15039 #define EPDC_WB_FIELD0_LEN(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_LEN_SHIFT))&EPDC_WB_FIELD0_LEN_MASK)
15040 #define EPDC_WB_FIELD0_TO_MASK                   0xF0u
15041 #define EPDC_WB_FIELD0_TO_SHIFT                  4
15042 #define EPDC_WB_FIELD0_TO(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_TO_SHIFT))&EPDC_WB_FIELD0_TO_MASK)
15043 #define EPDC_WB_FIELD0_FROM_MASK                 0x1F00u
15044 #define EPDC_WB_FIELD0_FROM_SHIFT                8
15045 #define EPDC_WB_FIELD0_FROM(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_FROM_SHIFT))&EPDC_WB_FIELD0_FROM_MASK)
15046 #define EPDC_WB_FIELD0_USAGE_MASK                0xE000u
15047 #define EPDC_WB_FIELD0_USAGE_SHIFT               13
15048 #define EPDC_WB_FIELD0_USAGE(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_USAGE_SHIFT))&EPDC_WB_FIELD0_USAGE_MASK)
15049 #define EPDC_WB_FIELD0_USE_FIXED_MASK            0x30000u
15050 #define EPDC_WB_FIELD0_USE_FIXED_SHIFT           16
15051 #define EPDC_WB_FIELD0_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_USE_FIXED_SHIFT))&EPDC_WB_FIELD0_USE_FIXED_MASK)
15052 #define EPDC_WB_FIELD0_FIXED_MASK                0xFF000000u
15053 #define EPDC_WB_FIELD0_FIXED_SHIFT               24
15054 #define EPDC_WB_FIELD0_FIXED(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_FIXED_SHIFT))&EPDC_WB_FIELD0_FIXED_MASK)
15055 /* WB_FIELD1 Bit Fields */
15056 #define EPDC_WB_FIELD1_LEN_MASK                  0xFu
15057 #define EPDC_WB_FIELD1_LEN_SHIFT                 0
15058 #define EPDC_WB_FIELD1_LEN(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_LEN_SHIFT))&EPDC_WB_FIELD1_LEN_MASK)
15059 #define EPDC_WB_FIELD1_TO_MASK                   0xF0u
15060 #define EPDC_WB_FIELD1_TO_SHIFT                  4
15061 #define EPDC_WB_FIELD1_TO(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_TO_SHIFT))&EPDC_WB_FIELD1_TO_MASK)
15062 #define EPDC_WB_FIELD1_FROM_MASK                 0x1F00u
15063 #define EPDC_WB_FIELD1_FROM_SHIFT                8
15064 #define EPDC_WB_FIELD1_FROM(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_FROM_SHIFT))&EPDC_WB_FIELD1_FROM_MASK)
15065 #define EPDC_WB_FIELD1_USAGE_MASK                0xE000u
15066 #define EPDC_WB_FIELD1_USAGE_SHIFT               13
15067 #define EPDC_WB_FIELD1_USAGE(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_USAGE_SHIFT))&EPDC_WB_FIELD1_USAGE_MASK)
15068 #define EPDC_WB_FIELD1_USE_FIXED_MASK            0x30000u
15069 #define EPDC_WB_FIELD1_USE_FIXED_SHIFT           16
15070 #define EPDC_WB_FIELD1_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_USE_FIXED_SHIFT))&EPDC_WB_FIELD1_USE_FIXED_MASK)
15071 #define EPDC_WB_FIELD1_FIXED_MASK                0xFF000000u
15072 #define EPDC_WB_FIELD1_FIXED_SHIFT               24
15073 #define EPDC_WB_FIELD1_FIXED(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_FIXED_SHIFT))&EPDC_WB_FIELD1_FIXED_MASK)
15074 /* WB_FIELD2 Bit Fields */
15075 #define EPDC_WB_FIELD2_LEN_MASK                  0xFu
15076 #define EPDC_WB_FIELD2_LEN_SHIFT                 0
15077 #define EPDC_WB_FIELD2_LEN(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_LEN_SHIFT))&EPDC_WB_FIELD2_LEN_MASK)
15078 #define EPDC_WB_FIELD2_TO_MASK                   0xF0u
15079 #define EPDC_WB_FIELD2_TO_SHIFT                  4
15080 #define EPDC_WB_FIELD2_TO(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_TO_SHIFT))&EPDC_WB_FIELD2_TO_MASK)
15081 #define EPDC_WB_FIELD2_FROM_MASK                 0x1F00u
15082 #define EPDC_WB_FIELD2_FROM_SHIFT                8
15083 #define EPDC_WB_FIELD2_FROM(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_FROM_SHIFT))&EPDC_WB_FIELD2_FROM_MASK)
15084 #define EPDC_WB_FIELD2_USAGE_MASK                0xE000u
15085 #define EPDC_WB_FIELD2_USAGE_SHIFT               13
15086 #define EPDC_WB_FIELD2_USAGE(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_USAGE_SHIFT))&EPDC_WB_FIELD2_USAGE_MASK)
15087 #define EPDC_WB_FIELD2_USE_FIXED_MASK            0x30000u
15088 #define EPDC_WB_FIELD2_USE_FIXED_SHIFT           16
15089 #define EPDC_WB_FIELD2_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_USE_FIXED_SHIFT))&EPDC_WB_FIELD2_USE_FIXED_MASK)
15090 #define EPDC_WB_FIELD2_FIXED_MASK                0xFF000000u
15091 #define EPDC_WB_FIELD2_FIXED_SHIFT               24
15092 #define EPDC_WB_FIELD2_FIXED(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_FIXED_SHIFT))&EPDC_WB_FIELD2_FIXED_MASK)
15093 /* WB_FIELD3 Bit Fields */
15094 #define EPDC_WB_FIELD3_LEN_MASK                  0xFu
15095 #define EPDC_WB_FIELD3_LEN_SHIFT                 0
15096 #define EPDC_WB_FIELD3_LEN(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_LEN_SHIFT))&EPDC_WB_FIELD3_LEN_MASK)
15097 #define EPDC_WB_FIELD3_TO_MASK                   0xF0u
15098 #define EPDC_WB_FIELD3_TO_SHIFT                  4
15099 #define EPDC_WB_FIELD3_TO(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_TO_SHIFT))&EPDC_WB_FIELD3_TO_MASK)
15100 #define EPDC_WB_FIELD3_FROM_MASK                 0x1F00u
15101 #define EPDC_WB_FIELD3_FROM_SHIFT                8
15102 #define EPDC_WB_FIELD3_FROM(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_FROM_SHIFT))&EPDC_WB_FIELD3_FROM_MASK)
15103 #define EPDC_WB_FIELD3_USAGE_MASK                0xE000u
15104 #define EPDC_WB_FIELD3_USAGE_SHIFT               13
15105 #define EPDC_WB_FIELD3_USAGE(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_USAGE_SHIFT))&EPDC_WB_FIELD3_USAGE_MASK)
15106 #define EPDC_WB_FIELD3_USE_FIXED_MASK            0x30000u
15107 #define EPDC_WB_FIELD3_USE_FIXED_SHIFT           16
15108 #define EPDC_WB_FIELD3_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_USE_FIXED_SHIFT))&EPDC_WB_FIELD3_USE_FIXED_MASK)
15109 #define EPDC_WB_FIELD3_FIXED_MASK                0xFF000000u
15110 #define EPDC_WB_FIELD3_FIXED_SHIFT               24
15111 #define EPDC_WB_FIELD3_FIXED(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_FIXED_SHIFT))&EPDC_WB_FIELD3_FIXED_MASK)
15112 /* FIFOCTRL Bit Fields */
15113 #define EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK          0xFFu
15114 #define EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT         0
15115 #define EPDC_FIFOCTRL_FIFO_L_LEVEL(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK)
15116 #define EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK          0xFF00u
15117 #define EPDC_FIFOCTRL_FIFO_H_LEVEL_SHIFT         8
15118 #define EPDC_FIFOCTRL_FIFO_H_LEVEL(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
15119 #define EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK       0xFF0000u
15120 #define EPDC_FIFOCTRL_FIFO_INIT_LEVEL_SHIFT      16
15121 #define EPDC_FIFOCTRL_FIFO_INIT_LEVEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
15122 #define EPDC_FIFOCTRL_ENABLE_PRIORITY_MASK       0x80000000u
15123 #define EPDC_FIFOCTRL_ENABLE_PRIORITY_SHIFT      31
15124 /* FIFOCTRL_SET Bit Fields */
15125 #define EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_MASK      0xFFu
15126 #define EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_SHIFT     0
15127 #define EPDC_FIFOCTRL_SET_FIFO_L_LEVEL(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_MASK)
15128 #define EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_MASK      0xFF00u
15129 #define EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_SHIFT     8
15130 #define EPDC_FIFOCTRL_SET_FIFO_H_LEVEL(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_MASK)
15131 #define EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_MASK   0xFF0000u
15132 #define EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_SHIFT  16
15133 #define EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_MASK)
15134 #define EPDC_FIFOCTRL_SET_ENABLE_PRIORITY_MASK   0x80000000u
15135 #define EPDC_FIFOCTRL_SET_ENABLE_PRIORITY_SHIFT  31
15136 /* FIFOCTRL_CLR Bit Fields */
15137 #define EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_MASK      0xFFu
15138 #define EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_SHIFT     0
15139 #define EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_MASK)
15140 #define EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_MASK      0xFF00u
15141 #define EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_SHIFT     8
15142 #define EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_MASK)
15143 #define EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_MASK   0xFF0000u
15144 #define EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_SHIFT  16
15145 #define EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_MASK)
15146 #define EPDC_FIFOCTRL_CLR_ENABLE_PRIORITY_MASK   0x80000000u
15147 #define EPDC_FIFOCTRL_CLR_ENABLE_PRIORITY_SHIFT  31
15148 /* FIFOCTRL_TOG Bit Fields */
15149 #define EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_MASK      0xFFu
15150 #define EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_SHIFT     0
15151 #define EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_MASK)
15152 #define EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_MASK      0xFF00u
15153 #define EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_SHIFT     8
15154 #define EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_MASK)
15155 #define EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_MASK   0xFF0000u
15156 #define EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_SHIFT  16
15157 #define EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_MASK)
15158 #define EPDC_FIFOCTRL_TOG_ENABLE_PRIORITY_MASK   0x80000000u
15159 #define EPDC_FIFOCTRL_TOG_ENABLE_PRIORITY_SHIFT  31
15160 /* UPD_ADDR Bit Fields */
15161 #define EPDC_UPD_ADDR_ADDR_MASK                  0xFFFFFFFFu
15162 #define EPDC_UPD_ADDR_ADDR_SHIFT                 0
15163 #define EPDC_UPD_ADDR_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_ADDR_ADDR_SHIFT))&EPDC_UPD_ADDR_ADDR_MASK)
15164 /* UPD_STRIDE Bit Fields */
15165 #define EPDC_UPD_STRIDE_STRIDE_MASK              0xFFFFFFFFu
15166 #define EPDC_UPD_STRIDE_STRIDE_SHIFT             0
15167 #define EPDC_UPD_STRIDE_STRIDE(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_STRIDE_STRIDE_SHIFT))&EPDC_UPD_STRIDE_STRIDE_MASK)
15168 /* UPD_CORD Bit Fields */
15169 #define EPDC_UPD_CORD_XCORD_MASK                 0x1FFFu
15170 #define EPDC_UPD_CORD_XCORD_SHIFT                0
15171 #define EPDC_UPD_CORD_XCORD(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CORD_XCORD_SHIFT))&EPDC_UPD_CORD_XCORD_MASK)
15172 #define EPDC_UPD_CORD_YCORD_MASK                 0x1FFF0000u
15173 #define EPDC_UPD_CORD_YCORD_SHIFT                16
15174 #define EPDC_UPD_CORD_YCORD(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CORD_YCORD_SHIFT))&EPDC_UPD_CORD_YCORD_MASK)
15175 /* UPD_SIZE Bit Fields */
15176 #define EPDC_UPD_SIZE_WIDTH_MASK                 0x1FFFu
15177 #define EPDC_UPD_SIZE_WIDTH_SHIFT                0
15178 #define EPDC_UPD_SIZE_WIDTH(x)                   (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_SIZE_WIDTH_SHIFT))&EPDC_UPD_SIZE_WIDTH_MASK)
15179 #define EPDC_UPD_SIZE_HEIGHT_MASK                0x1FFF0000u
15180 #define EPDC_UPD_SIZE_HEIGHT_SHIFT               16
15181 #define EPDC_UPD_SIZE_HEIGHT(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_SIZE_HEIGHT_SHIFT))&EPDC_UPD_SIZE_HEIGHT_MASK)
15182 /* UPD_CTRL Bit Fields */
15183 #define EPDC_UPD_CTRL_UPDATE_MODE_MASK           0x1u
15184 #define EPDC_UPD_CTRL_UPDATE_MODE_SHIFT          0
15185 #define EPDC_UPD_CTRL_DRY_RUN_MASK               0x2u
15186 #define EPDC_UPD_CTRL_DRY_RUN_SHIFT              1
15187 #define EPDC_UPD_CTRL_AUTOWV_MASK                0x4u
15188 #define EPDC_UPD_CTRL_AUTOWV_SHIFT               2
15189 #define EPDC_UPD_CTRL_PAUSE_MASK                 0x8u
15190 #define EPDC_UPD_CTRL_PAUSE_SHIFT                3
15191 #define EPDC_UPD_CTRL_NO_LUT_CANCEL_MASK         0x10u
15192 #define EPDC_UPD_CTRL_NO_LUT_CANCEL_SHIFT        4
15193 #define EPDC_UPD_CTRL_STANDBY_MASK               0x20u
15194 #define EPDC_UPD_CTRL_STANDBY_SHIFT              5
15195 #define EPDC_UPD_CTRL_WAVEFORM_MODE_MASK         0xFF00u
15196 #define EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT        8
15197 #define EPDC_UPD_CTRL_WAVEFORM_MODE(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_WAVEFORM_MODE_MASK)
15198 #define EPDC_UPD_CTRL_LUT_SEL_MASK               0x3F0000u
15199 #define EPDC_UPD_CTRL_LUT_SEL_SHIFT              16
15200 #define EPDC_UPD_CTRL_LUT_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_LUT_SEL_MASK)
15201 #define EPDC_UPD_CTRL_USE_FIXED_MASK             0x80000000u
15202 #define EPDC_UPD_CTRL_USE_FIXED_SHIFT            31
15203 /* UPD_CTRL_SET Bit Fields */
15204 #define EPDC_UPD_CTRL_SET_UPDATE_MODE_MASK       0x1u
15205 #define EPDC_UPD_CTRL_SET_UPDATE_MODE_SHIFT      0
15206 #define EPDC_UPD_CTRL_SET_DRY_RUN_MASK           0x2u
15207 #define EPDC_UPD_CTRL_SET_DRY_RUN_SHIFT          1
15208 #define EPDC_UPD_CTRL_SET_AUTOWV_MASK            0x4u
15209 #define EPDC_UPD_CTRL_SET_AUTOWV_SHIFT           2
15210 #define EPDC_UPD_CTRL_SET_PAUSE_MASK             0x8u
15211 #define EPDC_UPD_CTRL_SET_PAUSE_SHIFT            3
15212 #define EPDC_UPD_CTRL_SET_NO_LUT_CANCEL_MASK     0x10u
15213 #define EPDC_UPD_CTRL_SET_NO_LUT_CANCEL_SHIFT    4
15214 #define EPDC_UPD_CTRL_SET_STANDBY_MASK           0x20u
15215 #define EPDC_UPD_CTRL_SET_STANDBY_SHIFT          5
15216 #define EPDC_UPD_CTRL_SET_WAVEFORM_MODE_MASK     0xFF00u
15217 #define EPDC_UPD_CTRL_SET_WAVEFORM_MODE_SHIFT    8
15218 #define EPDC_UPD_CTRL_SET_WAVEFORM_MODE(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_SET_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_SET_WAVEFORM_MODE_MASK)
15219 #define EPDC_UPD_CTRL_SET_LUT_SEL_MASK           0x3F0000u
15220 #define EPDC_UPD_CTRL_SET_LUT_SEL_SHIFT          16
15221 #define EPDC_UPD_CTRL_SET_LUT_SEL(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_SET_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_SET_LUT_SEL_MASK)
15222 #define EPDC_UPD_CTRL_SET_USE_FIXED_MASK         0x80000000u
15223 #define EPDC_UPD_CTRL_SET_USE_FIXED_SHIFT        31
15224 /* UPD_CTRL_CLR Bit Fields */
15225 #define EPDC_UPD_CTRL_CLR_UPDATE_MODE_MASK       0x1u
15226 #define EPDC_UPD_CTRL_CLR_UPDATE_MODE_SHIFT      0
15227 #define EPDC_UPD_CTRL_CLR_DRY_RUN_MASK           0x2u
15228 #define EPDC_UPD_CTRL_CLR_DRY_RUN_SHIFT          1
15229 #define EPDC_UPD_CTRL_CLR_AUTOWV_MASK            0x4u
15230 #define EPDC_UPD_CTRL_CLR_AUTOWV_SHIFT           2
15231 #define EPDC_UPD_CTRL_CLR_PAUSE_MASK             0x8u
15232 #define EPDC_UPD_CTRL_CLR_PAUSE_SHIFT            3
15233 #define EPDC_UPD_CTRL_CLR_NO_LUT_CANCEL_MASK     0x10u
15234 #define EPDC_UPD_CTRL_CLR_NO_LUT_CANCEL_SHIFT    4
15235 #define EPDC_UPD_CTRL_CLR_STANDBY_MASK           0x20u
15236 #define EPDC_UPD_CTRL_CLR_STANDBY_SHIFT          5
15237 #define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_MASK     0xFF00u
15238 #define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_SHIFT    8
15239 #define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_MASK)
15240 #define EPDC_UPD_CTRL_CLR_LUT_SEL_MASK           0x3F0000u
15241 #define EPDC_UPD_CTRL_CLR_LUT_SEL_SHIFT          16
15242 #define EPDC_UPD_CTRL_CLR_LUT_SEL(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_CLR_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_CLR_LUT_SEL_MASK)
15243 #define EPDC_UPD_CTRL_CLR_USE_FIXED_MASK         0x80000000u
15244 #define EPDC_UPD_CTRL_CLR_USE_FIXED_SHIFT        31
15245 /* UPD_CTRL_TOG Bit Fields */
15246 #define EPDC_UPD_CTRL_TOG_UPDATE_MODE_MASK       0x1u
15247 #define EPDC_UPD_CTRL_TOG_UPDATE_MODE_SHIFT      0
15248 #define EPDC_UPD_CTRL_TOG_DRY_RUN_MASK           0x2u
15249 #define EPDC_UPD_CTRL_TOG_DRY_RUN_SHIFT          1
15250 #define EPDC_UPD_CTRL_TOG_AUTOWV_MASK            0x4u
15251 #define EPDC_UPD_CTRL_TOG_AUTOWV_SHIFT           2
15252 #define EPDC_UPD_CTRL_TOG_PAUSE_MASK             0x8u
15253 #define EPDC_UPD_CTRL_TOG_PAUSE_SHIFT            3
15254 #define EPDC_UPD_CTRL_TOG_NO_LUT_CANCEL_MASK     0x10u
15255 #define EPDC_UPD_CTRL_TOG_NO_LUT_CANCEL_SHIFT    4
15256 #define EPDC_UPD_CTRL_TOG_STANDBY_MASK           0x20u
15257 #define EPDC_UPD_CTRL_TOG_STANDBY_SHIFT          5
15258 #define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_MASK     0xFF00u
15259 #define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_SHIFT    8
15260 #define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_MASK)
15261 #define EPDC_UPD_CTRL_TOG_LUT_SEL_MASK           0x3F0000u
15262 #define EPDC_UPD_CTRL_TOG_LUT_SEL_SHIFT          16
15263 #define EPDC_UPD_CTRL_TOG_LUT_SEL(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_TOG_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_TOG_LUT_SEL_MASK)
15264 #define EPDC_UPD_CTRL_TOG_USE_FIXED_MASK         0x80000000u
15265 #define EPDC_UPD_CTRL_TOG_USE_FIXED_SHIFT        31
15266 /* UPD_FIXED Bit Fields */
15267 #define EPDC_UPD_FIXED_FIXCP_MASK                0xFFu
15268 #define EPDC_UPD_FIXED_FIXCP_SHIFT               0
15269 #define EPDC_UPD_FIXED_FIXCP(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_FIXCP_SHIFT))&EPDC_UPD_FIXED_FIXCP_MASK)
15270 #define EPDC_UPD_FIXED_FIXNP_MASK                0xFF00u
15271 #define EPDC_UPD_FIXED_FIXNP_SHIFT               8
15272 #define EPDC_UPD_FIXED_FIXNP(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_FIXNP_SHIFT))&EPDC_UPD_FIXED_FIXNP_MASK)
15273 #define EPDC_UPD_FIXED_FIXCP_EN_MASK             0x40000000u
15274 #define EPDC_UPD_FIXED_FIXCP_EN_SHIFT            30
15275 #define EPDC_UPD_FIXED_FIXNP_EN_MASK             0x80000000u
15276 #define EPDC_UPD_FIXED_FIXNP_EN_SHIFT            31
15277 /* UPD_FIXED_SET Bit Fields */
15278 #define EPDC_UPD_FIXED_SET_FIXCP_MASK            0xFFu
15279 #define EPDC_UPD_FIXED_SET_FIXCP_SHIFT           0
15280 #define EPDC_UPD_FIXED_SET_FIXCP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_SET_FIXCP_SHIFT))&EPDC_UPD_FIXED_SET_FIXCP_MASK)
15281 #define EPDC_UPD_FIXED_SET_FIXNP_MASK            0xFF00u
15282 #define EPDC_UPD_FIXED_SET_FIXNP_SHIFT           8
15283 #define EPDC_UPD_FIXED_SET_FIXNP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_SET_FIXNP_SHIFT))&EPDC_UPD_FIXED_SET_FIXNP_MASK)
15284 #define EPDC_UPD_FIXED_SET_FIXCP_EN_MASK         0x40000000u
15285 #define EPDC_UPD_FIXED_SET_FIXCP_EN_SHIFT        30
15286 #define EPDC_UPD_FIXED_SET_FIXNP_EN_MASK         0x80000000u
15287 #define EPDC_UPD_FIXED_SET_FIXNP_EN_SHIFT        31
15288 /* UPD_FIXED_CLR Bit Fields */
15289 #define EPDC_UPD_FIXED_CLR_FIXCP_MASK            0xFFu
15290 #define EPDC_UPD_FIXED_CLR_FIXCP_SHIFT           0
15291 #define EPDC_UPD_FIXED_CLR_FIXCP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_CLR_FIXCP_SHIFT))&EPDC_UPD_FIXED_CLR_FIXCP_MASK)
15292 #define EPDC_UPD_FIXED_CLR_FIXNP_MASK            0xFF00u
15293 #define EPDC_UPD_FIXED_CLR_FIXNP_SHIFT           8
15294 #define EPDC_UPD_FIXED_CLR_FIXNP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_CLR_FIXNP_SHIFT))&EPDC_UPD_FIXED_CLR_FIXNP_MASK)
15295 #define EPDC_UPD_FIXED_CLR_FIXCP_EN_MASK         0x40000000u
15296 #define EPDC_UPD_FIXED_CLR_FIXCP_EN_SHIFT        30
15297 #define EPDC_UPD_FIXED_CLR_FIXNP_EN_MASK         0x80000000u
15298 #define EPDC_UPD_FIXED_CLR_FIXNP_EN_SHIFT        31
15299 /* UPD_FIXED_TOG Bit Fields */
15300 #define EPDC_UPD_FIXED_TOG_FIXCP_MASK            0xFFu
15301 #define EPDC_UPD_FIXED_TOG_FIXCP_SHIFT           0
15302 #define EPDC_UPD_FIXED_TOG_FIXCP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_TOG_FIXCP_SHIFT))&EPDC_UPD_FIXED_TOG_FIXCP_MASK)
15303 #define EPDC_UPD_FIXED_TOG_FIXNP_MASK            0xFF00u
15304 #define EPDC_UPD_FIXED_TOG_FIXNP_SHIFT           8
15305 #define EPDC_UPD_FIXED_TOG_FIXNP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_TOG_FIXNP_SHIFT))&EPDC_UPD_FIXED_TOG_FIXNP_MASK)
15306 #define EPDC_UPD_FIXED_TOG_FIXCP_EN_MASK         0x40000000u
15307 #define EPDC_UPD_FIXED_TOG_FIXCP_EN_SHIFT        30
15308 #define EPDC_UPD_FIXED_TOG_FIXNP_EN_MASK         0x80000000u
15309 #define EPDC_UPD_FIXED_TOG_FIXNP_EN_SHIFT        31
15310 /* TEMP Bit Fields */
15311 #define EPDC_TEMP_TEMPERATURE_MASK               0xFFFFFFFFu
15312 #define EPDC_TEMP_TEMPERATURE_SHIFT              0
15313 #define EPDC_TEMP_TEMPERATURE(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_TEMP_TEMPERATURE_SHIFT))&EPDC_TEMP_TEMPERATURE_MASK)
15314 /* AUTOWV_LUT Bit Fields */
15315 #define EPDC_AUTOWV_LUT_ADDR_MASK                0x7u
15316 #define EPDC_AUTOWV_LUT_ADDR_SHIFT               0
15317 #define EPDC_AUTOWV_LUT_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_AUTOWV_LUT_ADDR_SHIFT))&EPDC_AUTOWV_LUT_ADDR_MASK)
15318 #define EPDC_AUTOWV_LUT_DATA_MASK                0xFF0000u
15319 #define EPDC_AUTOWV_LUT_DATA_SHIFT               16
15320 #define EPDC_AUTOWV_LUT_DATA(x)                  (((uint32_t)(((uint32_t)(x))<<EPDC_AUTOWV_LUT_DATA_SHIFT))&EPDC_AUTOWV_LUT_DATA_MASK)
15321 /* LUT_STANDBY1 Bit Fields */
15322 #define EPDC_LUT_STANDBY1_LUTN_MASK              0xFFFFFFFFu
15323 #define EPDC_LUT_STANDBY1_LUTN_SHIFT             0
15324 #define EPDC_LUT_STANDBY1_LUTN(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_LUTN_SHIFT))&EPDC_LUT_STANDBY1_LUTN_MASK)
15325 /* LUT_STANDBY1_SET Bit Fields */
15326 #define EPDC_LUT_STANDBY1_SET_LUTN_MASK          0xFFFFFFFFu
15327 #define EPDC_LUT_STANDBY1_SET_LUTN_SHIFT         0
15328 #define EPDC_LUT_STANDBY1_SET_LUTN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_SET_LUTN_SHIFT))&EPDC_LUT_STANDBY1_SET_LUTN_MASK)
15329 /* LUT_STANDBY1_CLR Bit Fields */
15330 #define EPDC_LUT_STANDBY1_CLR_LUTN_MASK          0xFFFFFFFFu
15331 #define EPDC_LUT_STANDBY1_CLR_LUTN_SHIFT         0
15332 #define EPDC_LUT_STANDBY1_CLR_LUTN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_CLR_LUTN_SHIFT))&EPDC_LUT_STANDBY1_CLR_LUTN_MASK)
15333 /* LUT_STANDBY1_TOG Bit Fields */
15334 #define EPDC_LUT_STANDBY1_TOG_LUTN_MASK          0xFFFFFFFFu
15335 #define EPDC_LUT_STANDBY1_TOG_LUTN_SHIFT         0
15336 #define EPDC_LUT_STANDBY1_TOG_LUTN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_TOG_LUTN_SHIFT))&EPDC_LUT_STANDBY1_TOG_LUTN_MASK)
15337 /* LUT_STANDBY2 Bit Fields */
15338 #define EPDC_LUT_STANDBY2_LUTN_MASK              0xFFFFFFFFu
15339 #define EPDC_LUT_STANDBY2_LUTN_SHIFT             0
15340 #define EPDC_LUT_STANDBY2_LUTN(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_LUTN_SHIFT))&EPDC_LUT_STANDBY2_LUTN_MASK)
15341 /* LUT_STANDBY2_SET Bit Fields */
15342 #define EPDC_LUT_STANDBY2_SET_LUTN_MASK          0xFFFFFFFFu
15343 #define EPDC_LUT_STANDBY2_SET_LUTN_SHIFT         0
15344 #define EPDC_LUT_STANDBY2_SET_LUTN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_SET_LUTN_SHIFT))&EPDC_LUT_STANDBY2_SET_LUTN_MASK)
15345 /* LUT_STANDBY2_CLR Bit Fields */
15346 #define EPDC_LUT_STANDBY2_CLR_LUTN_MASK          0xFFFFFFFFu
15347 #define EPDC_LUT_STANDBY2_CLR_LUTN_SHIFT         0
15348 #define EPDC_LUT_STANDBY2_CLR_LUTN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_CLR_LUTN_SHIFT))&EPDC_LUT_STANDBY2_CLR_LUTN_MASK)
15349 /* LUT_STANDBY2_TOG Bit Fields */
15350 #define EPDC_LUT_STANDBY2_TOG_LUTN_MASK          0xFFFFFFFFu
15351 #define EPDC_LUT_STANDBY2_TOG_LUTN_SHIFT         0
15352 #define EPDC_LUT_STANDBY2_TOG_LUTN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_TOG_LUTN_SHIFT))&EPDC_LUT_STANDBY2_TOG_LUTN_MASK)
15353 /* TCE_CTRL Bit Fields */
15354 #define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK      0x3u
15355 #define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT     0
15356 #define EPDC_TCE_CTRL_PIXELS_PER_SDCLK(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK)
15357 #define EPDC_TCE_CTRL_SDDO_WIDTH_MASK            0x4u
15358 #define EPDC_TCE_CTRL_SDDO_WIDTH_SHIFT           2
15359 #define EPDC_TCE_CTRL_DUAL_SCAN_MASK             0x8u
15360 #define EPDC_TCE_CTRL_DUAL_SCAN_SHIFT            3
15361 #define EPDC_TCE_CTRL_SCAN_DIR_0_MASK            0x10u
15362 #define EPDC_TCE_CTRL_SCAN_DIR_0_SHIFT           4
15363 #define EPDC_TCE_CTRL_SCAN_DIR_1_MASK            0x20u
15364 #define EPDC_TCE_CTRL_SCAN_DIR_1_SHIFT           5
15365 #define EPDC_TCE_CTRL_LVDS_MODE_MASK             0x40u
15366 #define EPDC_TCE_CTRL_LVDS_MODE_SHIFT            6
15367 #define EPDC_TCE_CTRL_LVDS_MODE_CE_MASK          0x80u
15368 #define EPDC_TCE_CTRL_LVDS_MODE_CE_SHIFT         7
15369 #define EPDC_TCE_CTRL_DDR_MODE_MASK              0x100u
15370 #define EPDC_TCE_CTRL_DDR_MODE_SHIFT             8
15371 #define EPDC_TCE_CTRL_VCOM_MODE_MASK             0x200u
15372 #define EPDC_TCE_CTRL_VCOM_MODE_SHIFT            9
15373 #define EPDC_TCE_CTRL_VCOM_VAL_MASK              0xC00u
15374 #define EPDC_TCE_CTRL_VCOM_VAL_SHIFT             10
15375 #define EPDC_TCE_CTRL_VCOM_VAL(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_VCOM_VAL_MASK)
15376 #define EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK         0x1FF0000u
15377 #define EPDC_TCE_CTRL_VSCAN_HOLDOFF_SHIFT        16
15378 #define EPDC_TCE_CTRL_VSCAN_HOLDOFF(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
15379 /* TCE_CTRL_SET Bit Fields */
15380 #define EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_MASK  0x3u
15381 #define EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_SHIFT 0
15382 #define EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK(x)    (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_MASK)
15383 #define EPDC_TCE_CTRL_SET_SDDO_WIDTH_MASK        0x4u
15384 #define EPDC_TCE_CTRL_SET_SDDO_WIDTH_SHIFT       2
15385 #define EPDC_TCE_CTRL_SET_DUAL_SCAN_MASK         0x8u
15386 #define EPDC_TCE_CTRL_SET_DUAL_SCAN_SHIFT        3
15387 #define EPDC_TCE_CTRL_SET_SCAN_DIR_0_MASK        0x10u
15388 #define EPDC_TCE_CTRL_SET_SCAN_DIR_0_SHIFT       4
15389 #define EPDC_TCE_CTRL_SET_SCAN_DIR_1_MASK        0x20u
15390 #define EPDC_TCE_CTRL_SET_SCAN_DIR_1_SHIFT       5
15391 #define EPDC_TCE_CTRL_SET_LVDS_MODE_MASK         0x40u
15392 #define EPDC_TCE_CTRL_SET_LVDS_MODE_SHIFT        6
15393 #define EPDC_TCE_CTRL_SET_LVDS_MODE_CE_MASK      0x80u
15394 #define EPDC_TCE_CTRL_SET_LVDS_MODE_CE_SHIFT     7
15395 #define EPDC_TCE_CTRL_SET_DDR_MODE_MASK          0x100u
15396 #define EPDC_TCE_CTRL_SET_DDR_MODE_SHIFT         8
15397 #define EPDC_TCE_CTRL_SET_VCOM_MODE_MASK         0x200u
15398 #define EPDC_TCE_CTRL_SET_VCOM_MODE_SHIFT        9
15399 #define EPDC_TCE_CTRL_SET_VCOM_VAL_MASK          0xC00u
15400 #define EPDC_TCE_CTRL_SET_VCOM_VAL_SHIFT         10
15401 #define EPDC_TCE_CTRL_SET_VCOM_VAL(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_SET_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_SET_VCOM_VAL_MASK)
15402 #define EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_MASK     0x1FF0000u
15403 #define EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_SHIFT    16
15404 #define EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_MASK)
15405 /* TCE_CTRL_CLR Bit Fields */
15406 #define EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_MASK  0x3u
15407 #define EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_SHIFT 0
15408 #define EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK(x)    (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_MASK)
15409 #define EPDC_TCE_CTRL_CLR_SDDO_WIDTH_MASK        0x4u
15410 #define EPDC_TCE_CTRL_CLR_SDDO_WIDTH_SHIFT       2
15411 #define EPDC_TCE_CTRL_CLR_DUAL_SCAN_MASK         0x8u
15412 #define EPDC_TCE_CTRL_CLR_DUAL_SCAN_SHIFT        3
15413 #define EPDC_TCE_CTRL_CLR_SCAN_DIR_0_MASK        0x10u
15414 #define EPDC_TCE_CTRL_CLR_SCAN_DIR_0_SHIFT       4
15415 #define EPDC_TCE_CTRL_CLR_SCAN_DIR_1_MASK        0x20u
15416 #define EPDC_TCE_CTRL_CLR_SCAN_DIR_1_SHIFT       5
15417 #define EPDC_TCE_CTRL_CLR_LVDS_MODE_MASK         0x40u
15418 #define EPDC_TCE_CTRL_CLR_LVDS_MODE_SHIFT        6
15419 #define EPDC_TCE_CTRL_CLR_LVDS_MODE_CE_MASK      0x80u
15420 #define EPDC_TCE_CTRL_CLR_LVDS_MODE_CE_SHIFT     7
15421 #define EPDC_TCE_CTRL_CLR_DDR_MODE_MASK          0x100u
15422 #define EPDC_TCE_CTRL_CLR_DDR_MODE_SHIFT         8
15423 #define EPDC_TCE_CTRL_CLR_VCOM_MODE_MASK         0x200u
15424 #define EPDC_TCE_CTRL_CLR_VCOM_MODE_SHIFT        9
15425 #define EPDC_TCE_CTRL_CLR_VCOM_VAL_MASK          0xC00u
15426 #define EPDC_TCE_CTRL_CLR_VCOM_VAL_SHIFT         10
15427 #define EPDC_TCE_CTRL_CLR_VCOM_VAL(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_CLR_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_CLR_VCOM_VAL_MASK)
15428 #define EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_MASK     0x1FF0000u
15429 #define EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_SHIFT    16
15430 #define EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_MASK)
15431 /* TCE_CTRL_TOG Bit Fields */
15432 #define EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_MASK  0x3u
15433 #define EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_SHIFT 0
15434 #define EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK(x)    (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_MASK)
15435 #define EPDC_TCE_CTRL_TOG_SDDO_WIDTH_MASK        0x4u
15436 #define EPDC_TCE_CTRL_TOG_SDDO_WIDTH_SHIFT       2
15437 #define EPDC_TCE_CTRL_TOG_DUAL_SCAN_MASK         0x8u
15438 #define EPDC_TCE_CTRL_TOG_DUAL_SCAN_SHIFT        3
15439 #define EPDC_TCE_CTRL_TOG_SCAN_DIR_0_MASK        0x10u
15440 #define EPDC_TCE_CTRL_TOG_SCAN_DIR_0_SHIFT       4
15441 #define EPDC_TCE_CTRL_TOG_SCAN_DIR_1_MASK        0x20u
15442 #define EPDC_TCE_CTRL_TOG_SCAN_DIR_1_SHIFT       5
15443 #define EPDC_TCE_CTRL_TOG_LVDS_MODE_MASK         0x40u
15444 #define EPDC_TCE_CTRL_TOG_LVDS_MODE_SHIFT        6
15445 #define EPDC_TCE_CTRL_TOG_LVDS_MODE_CE_MASK      0x80u
15446 #define EPDC_TCE_CTRL_TOG_LVDS_MODE_CE_SHIFT     7
15447 #define EPDC_TCE_CTRL_TOG_DDR_MODE_MASK          0x100u
15448 #define EPDC_TCE_CTRL_TOG_DDR_MODE_SHIFT         8
15449 #define EPDC_TCE_CTRL_TOG_VCOM_MODE_MASK         0x200u
15450 #define EPDC_TCE_CTRL_TOG_VCOM_MODE_SHIFT        9
15451 #define EPDC_TCE_CTRL_TOG_VCOM_VAL_MASK          0xC00u
15452 #define EPDC_TCE_CTRL_TOG_VCOM_VAL_SHIFT         10
15453 #define EPDC_TCE_CTRL_TOG_VCOM_VAL(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_TOG_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_TOG_VCOM_VAL_MASK)
15454 #define EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_MASK     0x1FF0000u
15455 #define EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_SHIFT    16
15456 #define EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_MASK)
15457 /* TCE_SDCFG Bit Fields */
15458 #define EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK        0x1FFFu
15459 #define EPDC_TCE_SDCFG_PIXELS_PER_CE_SHIFT       0
15460 #define EPDC_TCE_SDCFG_PIXELS_PER_CE(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK)
15461 #define EPDC_TCE_SDCFG_SDDO_INVERT_MASK          0x2000u
15462 #define EPDC_TCE_SDCFG_SDDO_INVERT_SHIFT         13
15463 #define EPDC_TCE_SDCFG_SDDO_REFORMAT_MASK        0xC000u
15464 #define EPDC_TCE_SDCFG_SDDO_REFORMAT_SHIFT       14
15465 #define EPDC_TCE_SDCFG_SDDO_REFORMAT(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_SDDO_REFORMAT_MASK)
15466 #define EPDC_TCE_SDCFG_NUM_CE_MASK               0xF0000u
15467 #define EPDC_TCE_SDCFG_NUM_CE_SHIFT              16
15468 #define EPDC_TCE_SDCFG_NUM_CE(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_NUM_CE_MASK)
15469 #define EPDC_TCE_SDCFG_SDSHR_MASK                0x100000u
15470 #define EPDC_TCE_SDCFG_SDSHR_SHIFT               20
15471 #define EPDC_TCE_SDCFG_SDCLK_HOLD_MASK           0x200000u
15472 #define EPDC_TCE_SDCFG_SDCLK_HOLD_SHIFT          21
15473 /* TCE_SDCFG_SET Bit Fields */
15474 #define EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_MASK    0x1FFFu
15475 #define EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_SHIFT   0
15476 #define EPDC_TCE_SDCFG_SET_PIXELS_PER_CE(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_MASK)
15477 #define EPDC_TCE_SDCFG_SET_SDDO_INVERT_MASK      0x2000u
15478 #define EPDC_TCE_SDCFG_SET_SDDO_INVERT_SHIFT     13
15479 #define EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_MASK    0xC000u
15480 #define EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_SHIFT   14
15481 #define EPDC_TCE_SDCFG_SET_SDDO_REFORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_MASK)
15482 #define EPDC_TCE_SDCFG_SET_NUM_CE_MASK           0xF0000u
15483 #define EPDC_TCE_SDCFG_SET_NUM_CE_SHIFT          16
15484 #define EPDC_TCE_SDCFG_SET_NUM_CE(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SET_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_SET_NUM_CE_MASK)
15485 #define EPDC_TCE_SDCFG_SET_SDSHR_MASK            0x100000u
15486 #define EPDC_TCE_SDCFG_SET_SDSHR_SHIFT           20
15487 #define EPDC_TCE_SDCFG_SET_SDCLK_HOLD_MASK       0x200000u
15488 #define EPDC_TCE_SDCFG_SET_SDCLK_HOLD_SHIFT      21
15489 /* TCE_SDCFG_CLR Bit Fields */
15490 #define EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_MASK    0x1FFFu
15491 #define EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_SHIFT   0
15492 #define EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_MASK)
15493 #define EPDC_TCE_SDCFG_CLR_SDDO_INVERT_MASK      0x2000u
15494 #define EPDC_TCE_SDCFG_CLR_SDDO_INVERT_SHIFT     13
15495 #define EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_MASK    0xC000u
15496 #define EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_SHIFT   14
15497 #define EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_MASK)
15498 #define EPDC_TCE_SDCFG_CLR_NUM_CE_MASK           0xF0000u
15499 #define EPDC_TCE_SDCFG_CLR_NUM_CE_SHIFT          16
15500 #define EPDC_TCE_SDCFG_CLR_NUM_CE(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_CLR_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_CLR_NUM_CE_MASK)
15501 #define EPDC_TCE_SDCFG_CLR_SDSHR_MASK            0x100000u
15502 #define EPDC_TCE_SDCFG_CLR_SDSHR_SHIFT           20
15503 #define EPDC_TCE_SDCFG_CLR_SDCLK_HOLD_MASK       0x200000u
15504 #define EPDC_TCE_SDCFG_CLR_SDCLK_HOLD_SHIFT      21
15505 /* TCE_SDCFG_TOG Bit Fields */
15506 #define EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_MASK    0x1FFFu
15507 #define EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_SHIFT   0
15508 #define EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_MASK)
15509 #define EPDC_TCE_SDCFG_TOG_SDDO_INVERT_MASK      0x2000u
15510 #define EPDC_TCE_SDCFG_TOG_SDDO_INVERT_SHIFT     13
15511 #define EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_MASK    0xC000u
15512 #define EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_SHIFT   14
15513 #define EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_MASK)
15514 #define EPDC_TCE_SDCFG_TOG_NUM_CE_MASK           0xF0000u
15515 #define EPDC_TCE_SDCFG_TOG_NUM_CE_SHIFT          16
15516 #define EPDC_TCE_SDCFG_TOG_NUM_CE(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_TOG_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_TOG_NUM_CE_MASK)
15517 #define EPDC_TCE_SDCFG_TOG_SDSHR_MASK            0x100000u
15518 #define EPDC_TCE_SDCFG_TOG_SDSHR_SHIFT           20
15519 #define EPDC_TCE_SDCFG_TOG_SDCLK_HOLD_MASK       0x200000u
15520 #define EPDC_TCE_SDCFG_TOG_SDCLK_HOLD_SHIFT      21
15521 /* TCE_GDCFG Bit Fields */
15522 #define EPDC_TCE_GDCFG_GDSP_MODE_MASK            0x1u
15523 #define EPDC_TCE_GDCFG_GDSP_MODE_SHIFT           0
15524 #define EPDC_TCE_GDCFG_GDOE_MODE_MASK            0x2u
15525 #define EPDC_TCE_GDCFG_GDOE_MODE_SHIFT           1
15526 #define EPDC_TCE_GDCFG_GDRL_MASK                 0x10u
15527 #define EPDC_TCE_GDCFG_GDRL_SHIFT                4
15528 #define EPDC_TCE_GDCFG_PERIOD_VSCAN_MASK         0xFFFF0000u
15529 #define EPDC_TCE_GDCFG_PERIOD_VSCAN_SHIFT        16
15530 #define EPDC_TCE_GDCFG_PERIOD_VSCAN(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_PERIOD_VSCAN_MASK)
15531 /* TCE_GDCFG_SET Bit Fields */
15532 #define EPDC_TCE_GDCFG_SET_GDSP_MODE_MASK        0x1u
15533 #define EPDC_TCE_GDCFG_SET_GDSP_MODE_SHIFT       0
15534 #define EPDC_TCE_GDCFG_SET_GDOE_MODE_MASK        0x2u
15535 #define EPDC_TCE_GDCFG_SET_GDOE_MODE_SHIFT       1
15536 #define EPDC_TCE_GDCFG_SET_GDRL_MASK             0x10u
15537 #define EPDC_TCE_GDCFG_SET_GDRL_SHIFT            4
15538 #define EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_MASK     0xFFFF0000u
15539 #define EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_SHIFT    16
15540 #define EPDC_TCE_GDCFG_SET_PERIOD_VSCAN(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_MASK)
15541 /* TCE_GDCFG_CLR Bit Fields */
15542 #define EPDC_TCE_GDCFG_CLR_GDSP_MODE_MASK        0x1u
15543 #define EPDC_TCE_GDCFG_CLR_GDSP_MODE_SHIFT       0
15544 #define EPDC_TCE_GDCFG_CLR_GDOE_MODE_MASK        0x2u
15545 #define EPDC_TCE_GDCFG_CLR_GDOE_MODE_SHIFT       1
15546 #define EPDC_TCE_GDCFG_CLR_GDRL_MASK             0x10u
15547 #define EPDC_TCE_GDCFG_CLR_GDRL_SHIFT            4
15548 #define EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_MASK     0xFFFF0000u
15549 #define EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_SHIFT    16
15550 #define EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_MASK)
15551 /* TCE_GDCFG_TOG Bit Fields */
15552 #define EPDC_TCE_GDCFG_TOG_GDSP_MODE_MASK        0x1u
15553 #define EPDC_TCE_GDCFG_TOG_GDSP_MODE_SHIFT       0
15554 #define EPDC_TCE_GDCFG_TOG_GDOE_MODE_MASK        0x2u
15555 #define EPDC_TCE_GDCFG_TOG_GDOE_MODE_SHIFT       1
15556 #define EPDC_TCE_GDCFG_TOG_GDRL_MASK             0x10u
15557 #define EPDC_TCE_GDCFG_TOG_GDRL_SHIFT            4
15558 #define EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_MASK     0xFFFF0000u
15559 #define EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_SHIFT    16
15560 #define EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_MASK)
15561 /* TCE_HSCAN1 Bit Fields */
15562 #define EPDC_TCE_HSCAN1_LINE_SYNC_MASK           0xFFFu
15563 #define EPDC_TCE_HSCAN1_LINE_SYNC_SHIFT          0
15564 #define EPDC_TCE_HSCAN1_LINE_SYNC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_LINE_SYNC_MASK)
15565 #define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK     0xFFF0000u
15566 #define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_SHIFT    16
15567 #define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
15568 /* TCE_HSCAN1_SET Bit Fields */
15569 #define EPDC_TCE_HSCAN1_SET_LINE_SYNC_MASK       0xFFFu
15570 #define EPDC_TCE_HSCAN1_SET_LINE_SYNC_SHIFT      0
15571 #define EPDC_TCE_HSCAN1_SET_LINE_SYNC(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_SET_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_SET_LINE_SYNC_MASK)
15572 #define EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_MASK 0xFFF0000u
15573 #define EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_SHIFT 16
15574 #define EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_MASK)
15575 /* TCE_HSCAN1_CLR Bit Fields */
15576 #define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_MASK       0xFFFu
15577 #define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_SHIFT      0
15578 #define EPDC_TCE_HSCAN1_CLR_LINE_SYNC(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_CLR_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_CLR_LINE_SYNC_MASK)
15579 #define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_MASK 0xFFF0000u
15580 #define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_SHIFT 16
15581 #define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_MASK)
15582 /* TCE_HSCAN1_TOG Bit Fields */
15583 #define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_MASK       0xFFFu
15584 #define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_SHIFT      0
15585 #define EPDC_TCE_HSCAN1_TOG_LINE_SYNC(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_TOG_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_TOG_LINE_SYNC_MASK)
15586 #define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_MASK 0xFFF0000u
15587 #define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_SHIFT 16
15588 #define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_MASK)
15589 /* TCE_HSCAN2 Bit Fields */
15590 #define EPDC_TCE_HSCAN2_LINE_BEGIN_MASK          0xFFFu
15591 #define EPDC_TCE_HSCAN2_LINE_BEGIN_SHIFT         0
15592 #define EPDC_TCE_HSCAN2_LINE_BEGIN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
15593 #define EPDC_TCE_HSCAN2_LINE_END_MASK            0xFFF0000u
15594 #define EPDC_TCE_HSCAN2_LINE_END_SHIFT           16
15595 #define EPDC_TCE_HSCAN2_LINE_END(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_LINE_END_MASK)
15596 /* TCE_HSCAN2_SET Bit Fields */
15597 #define EPDC_TCE_HSCAN2_SET_LINE_BEGIN_MASK      0xFFFu
15598 #define EPDC_TCE_HSCAN2_SET_LINE_BEGIN_SHIFT     0
15599 #define EPDC_TCE_HSCAN2_SET_LINE_BEGIN(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_SET_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_SET_LINE_BEGIN_MASK)
15600 #define EPDC_TCE_HSCAN2_SET_LINE_END_MASK        0xFFF0000u
15601 #define EPDC_TCE_HSCAN2_SET_LINE_END_SHIFT       16
15602 #define EPDC_TCE_HSCAN2_SET_LINE_END(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_SET_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_SET_LINE_END_MASK)
15603 /* TCE_HSCAN2_CLR Bit Fields */
15604 #define EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_MASK      0xFFFu
15605 #define EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_SHIFT     0
15606 #define EPDC_TCE_HSCAN2_CLR_LINE_BEGIN(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_MASK)
15607 #define EPDC_TCE_HSCAN2_CLR_LINE_END_MASK        0xFFF0000u
15608 #define EPDC_TCE_HSCAN2_CLR_LINE_END_SHIFT       16
15609 #define EPDC_TCE_HSCAN2_CLR_LINE_END(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_CLR_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_CLR_LINE_END_MASK)
15610 /* TCE_HSCAN2_TOG Bit Fields */
15611 #define EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_MASK      0xFFFu
15612 #define EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_SHIFT     0
15613 #define EPDC_TCE_HSCAN2_TOG_LINE_BEGIN(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_MASK)
15614 #define EPDC_TCE_HSCAN2_TOG_LINE_END_MASK        0xFFF0000u
15615 #define EPDC_TCE_HSCAN2_TOG_LINE_END_SHIFT       16
15616 #define EPDC_TCE_HSCAN2_TOG_LINE_END(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_TOG_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_TOG_LINE_END_MASK)
15617 /* TCE_VSCAN Bit Fields */
15618 #define EPDC_TCE_VSCAN_FRAME_SYNC_MASK           0xFFu
15619 #define EPDC_TCE_VSCAN_FRAME_SYNC_SHIFT          0
15620 #define EPDC_TCE_VSCAN_FRAME_SYNC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_FRAME_SYNC_MASK)
15621 #define EPDC_TCE_VSCAN_FRAME_BEGIN_MASK          0xFF00u
15622 #define EPDC_TCE_VSCAN_FRAME_BEGIN_SHIFT         8
15623 #define EPDC_TCE_VSCAN_FRAME_BEGIN(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
15624 #define EPDC_TCE_VSCAN_FRAME_END_MASK            0xFF0000u
15625 #define EPDC_TCE_VSCAN_FRAME_END_SHIFT           16
15626 #define EPDC_TCE_VSCAN_FRAME_END(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_FRAME_END_MASK)
15627 /* TCE_VSCAN_SET Bit Fields */
15628 #define EPDC_TCE_VSCAN_SET_FRAME_SYNC_MASK       0xFFu
15629 #define EPDC_TCE_VSCAN_SET_FRAME_SYNC_SHIFT      0
15630 #define EPDC_TCE_VSCAN_SET_FRAME_SYNC(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_SET_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_SET_FRAME_SYNC_MASK)
15631 #define EPDC_TCE_VSCAN_SET_FRAME_BEGIN_MASK      0xFF00u
15632 #define EPDC_TCE_VSCAN_SET_FRAME_BEGIN_SHIFT     8
15633 #define EPDC_TCE_VSCAN_SET_FRAME_BEGIN(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_SET_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_SET_FRAME_BEGIN_MASK)
15634 #define EPDC_TCE_VSCAN_SET_FRAME_END_MASK        0xFF0000u
15635 #define EPDC_TCE_VSCAN_SET_FRAME_END_SHIFT       16
15636 #define EPDC_TCE_VSCAN_SET_FRAME_END(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_SET_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_SET_FRAME_END_MASK)
15637 /* TCE_VSCAN_CLR Bit Fields */
15638 #define EPDC_TCE_VSCAN_CLR_FRAME_SYNC_MASK       0xFFu
15639 #define EPDC_TCE_VSCAN_CLR_FRAME_SYNC_SHIFT      0
15640 #define EPDC_TCE_VSCAN_CLR_FRAME_SYNC(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_CLR_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_CLR_FRAME_SYNC_MASK)
15641 #define EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_MASK      0xFF00u
15642 #define EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_SHIFT     8
15643 #define EPDC_TCE_VSCAN_CLR_FRAME_BEGIN(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_MASK)
15644 #define EPDC_TCE_VSCAN_CLR_FRAME_END_MASK        0xFF0000u
15645 #define EPDC_TCE_VSCAN_CLR_FRAME_END_SHIFT       16
15646 #define EPDC_TCE_VSCAN_CLR_FRAME_END(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_CLR_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_CLR_FRAME_END_MASK)
15647 /* TCE_VSCAN_TOG Bit Fields */
15648 #define EPDC_TCE_VSCAN_TOG_FRAME_SYNC_MASK       0xFFu
15649 #define EPDC_TCE_VSCAN_TOG_FRAME_SYNC_SHIFT      0
15650 #define EPDC_TCE_VSCAN_TOG_FRAME_SYNC(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_TOG_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_TOG_FRAME_SYNC_MASK)
15651 #define EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_MASK      0xFF00u
15652 #define EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_SHIFT     8
15653 #define EPDC_TCE_VSCAN_TOG_FRAME_BEGIN(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_MASK)
15654 #define EPDC_TCE_VSCAN_TOG_FRAME_END_MASK        0xFF0000u
15655 #define EPDC_TCE_VSCAN_TOG_FRAME_END_SHIFT       16
15656 #define EPDC_TCE_VSCAN_TOG_FRAME_END(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_TOG_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_TOG_FRAME_END_MASK)
15657 /* TCE_OE Bit Fields */
15658 #define EPDC_TCE_OE_SDOEZ_DLY_MASK               0xFFu
15659 #define EPDC_TCE_OE_SDOEZ_DLY_SHIFT              0
15660 #define EPDC_TCE_OE_SDOEZ_DLY(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_SDOEZ_DLY_MASK)
15661 #define EPDC_TCE_OE_SDOEZ_WIDTH_MASK             0xFF00u
15662 #define EPDC_TCE_OE_SDOEZ_WIDTH_SHIFT            8
15663 #define EPDC_TCE_OE_SDOEZ_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
15664 #define EPDC_TCE_OE_SDOED_DLY_MASK               0xFF0000u
15665 #define EPDC_TCE_OE_SDOED_DLY_SHIFT              16
15666 #define EPDC_TCE_OE_SDOED_DLY(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOED_DLY_SHIFT))&EPDC_TCE_OE_SDOED_DLY_MASK)
15667 #define EPDC_TCE_OE_SDOED_WIDTH_MASK             0xFF000000u
15668 #define EPDC_TCE_OE_SDOED_WIDTH_SHIFT            24
15669 #define EPDC_TCE_OE_SDOED_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_SDOED_WIDTH_MASK)
15670 /* TCE_OE_SET Bit Fields */
15671 #define EPDC_TCE_OE_SET_SDOEZ_DLY_MASK           0xFFu
15672 #define EPDC_TCE_OE_SET_SDOEZ_DLY_SHIFT          0
15673 #define EPDC_TCE_OE_SET_SDOEZ_DLY(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_SET_SDOEZ_DLY_MASK)
15674 #define EPDC_TCE_OE_SET_SDOEZ_WIDTH_MASK         0xFF00u
15675 #define EPDC_TCE_OE_SET_SDOEZ_WIDTH_SHIFT        8
15676 #define EPDC_TCE_OE_SET_SDOEZ_WIDTH(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_SET_SDOEZ_WIDTH_MASK)
15677 #define EPDC_TCE_OE_SET_SDOED_DLY_MASK           0xFF0000u
15678 #define EPDC_TCE_OE_SET_SDOED_DLY_SHIFT          16
15679 #define EPDC_TCE_OE_SET_SDOED_DLY(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOED_DLY_SHIFT))&EPDC_TCE_OE_SET_SDOED_DLY_MASK)
15680 #define EPDC_TCE_OE_SET_SDOED_WIDTH_MASK         0xFF000000u
15681 #define EPDC_TCE_OE_SET_SDOED_WIDTH_SHIFT        24
15682 #define EPDC_TCE_OE_SET_SDOED_WIDTH(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_SET_SDOED_WIDTH_MASK)
15683 /* TCE_OE_CLR Bit Fields */
15684 #define EPDC_TCE_OE_CLR_SDOEZ_DLY_MASK           0xFFu
15685 #define EPDC_TCE_OE_CLR_SDOEZ_DLY_SHIFT          0
15686 #define EPDC_TCE_OE_CLR_SDOEZ_DLY(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_CLR_SDOEZ_DLY_MASK)
15687 #define EPDC_TCE_OE_CLR_SDOEZ_WIDTH_MASK         0xFF00u
15688 #define EPDC_TCE_OE_CLR_SDOEZ_WIDTH_SHIFT        8
15689 #define EPDC_TCE_OE_CLR_SDOEZ_WIDTH(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_CLR_SDOEZ_WIDTH_MASK)
15690 #define EPDC_TCE_OE_CLR_SDOED_DLY_MASK           0xFF0000u
15691 #define EPDC_TCE_OE_CLR_SDOED_DLY_SHIFT          16
15692 #define EPDC_TCE_OE_CLR_SDOED_DLY(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOED_DLY_SHIFT))&EPDC_TCE_OE_CLR_SDOED_DLY_MASK)
15693 #define EPDC_TCE_OE_CLR_SDOED_WIDTH_MASK         0xFF000000u
15694 #define EPDC_TCE_OE_CLR_SDOED_WIDTH_SHIFT        24
15695 #define EPDC_TCE_OE_CLR_SDOED_WIDTH(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_CLR_SDOED_WIDTH_MASK)
15696 /* TCE_OE_TOG Bit Fields */
15697 #define EPDC_TCE_OE_TOG_SDOEZ_DLY_MASK           0xFFu
15698 #define EPDC_TCE_OE_TOG_SDOEZ_DLY_SHIFT          0
15699 #define EPDC_TCE_OE_TOG_SDOEZ_DLY(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_TOG_SDOEZ_DLY_MASK)
15700 #define EPDC_TCE_OE_TOG_SDOEZ_WIDTH_MASK         0xFF00u
15701 #define EPDC_TCE_OE_TOG_SDOEZ_WIDTH_SHIFT        8
15702 #define EPDC_TCE_OE_TOG_SDOEZ_WIDTH(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_TOG_SDOEZ_WIDTH_MASK)
15703 #define EPDC_TCE_OE_TOG_SDOED_DLY_MASK           0xFF0000u
15704 #define EPDC_TCE_OE_TOG_SDOED_DLY_SHIFT          16
15705 #define EPDC_TCE_OE_TOG_SDOED_DLY(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOED_DLY_SHIFT))&EPDC_TCE_OE_TOG_SDOED_DLY_MASK)
15706 #define EPDC_TCE_OE_TOG_SDOED_WIDTH_MASK         0xFF000000u
15707 #define EPDC_TCE_OE_TOG_SDOED_WIDTH_SHIFT        24
15708 #define EPDC_TCE_OE_TOG_SDOED_WIDTH(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_TOG_SDOED_WIDTH_MASK)
15709 /* TCE_POLARITY Bit Fields */
15710 #define EPDC_TCE_POLARITY_SDCE_POL_MASK          0x1u
15711 #define EPDC_TCE_POLARITY_SDCE_POL_SHIFT         0
15712 #define EPDC_TCE_POLARITY_SDLE_POL_MASK          0x2u
15713 #define EPDC_TCE_POLARITY_SDLE_POL_SHIFT         1
15714 #define EPDC_TCE_POLARITY_SDOE_POL_MASK          0x4u
15715 #define EPDC_TCE_POLARITY_SDOE_POL_SHIFT         2
15716 #define EPDC_TCE_POLARITY_GDOE_POL_MASK          0x8u
15717 #define EPDC_TCE_POLARITY_GDOE_POL_SHIFT         3
15718 #define EPDC_TCE_POLARITY_GDSP_POL_MASK          0x10u
15719 #define EPDC_TCE_POLARITY_GDSP_POL_SHIFT         4
15720 /* TCE_POLARITY_SET Bit Fields */
15721 #define EPDC_TCE_POLARITY_SET_SDCE_POL_MASK      0x1u
15722 #define EPDC_TCE_POLARITY_SET_SDCE_POL_SHIFT     0
15723 #define EPDC_TCE_POLARITY_SET_SDLE_POL_MASK      0x2u
15724 #define EPDC_TCE_POLARITY_SET_SDLE_POL_SHIFT     1
15725 #define EPDC_TCE_POLARITY_SET_SDOE_POL_MASK      0x4u
15726 #define EPDC_TCE_POLARITY_SET_SDOE_POL_SHIFT     2
15727 #define EPDC_TCE_POLARITY_SET_GDOE_POL_MASK      0x8u
15728 #define EPDC_TCE_POLARITY_SET_GDOE_POL_SHIFT     3
15729 #define EPDC_TCE_POLARITY_SET_GDSP_POL_MASK      0x10u
15730 #define EPDC_TCE_POLARITY_SET_GDSP_POL_SHIFT     4
15731 /* TCE_POLARITY_CLR Bit Fields */
15732 #define EPDC_TCE_POLARITY_CLR_SDCE_POL_MASK      0x1u
15733 #define EPDC_TCE_POLARITY_CLR_SDCE_POL_SHIFT     0
15734 #define EPDC_TCE_POLARITY_CLR_SDLE_POL_MASK      0x2u
15735 #define EPDC_TCE_POLARITY_CLR_SDLE_POL_SHIFT     1
15736 #define EPDC_TCE_POLARITY_CLR_SDOE_POL_MASK      0x4u
15737 #define EPDC_TCE_POLARITY_CLR_SDOE_POL_SHIFT     2
15738 #define EPDC_TCE_POLARITY_CLR_GDOE_POL_MASK      0x8u
15739 #define EPDC_TCE_POLARITY_CLR_GDOE_POL_SHIFT     3
15740 #define EPDC_TCE_POLARITY_CLR_GDSP_POL_MASK      0x10u
15741 #define EPDC_TCE_POLARITY_CLR_GDSP_POL_SHIFT     4
15742 /* TCE_POLARITY_TOG Bit Fields */
15743 #define EPDC_TCE_POLARITY_TOG_SDCE_POL_MASK      0x1u
15744 #define EPDC_TCE_POLARITY_TOG_SDCE_POL_SHIFT     0
15745 #define EPDC_TCE_POLARITY_TOG_SDLE_POL_MASK      0x2u
15746 #define EPDC_TCE_POLARITY_TOG_SDLE_POL_SHIFT     1
15747 #define EPDC_TCE_POLARITY_TOG_SDOE_POL_MASK      0x4u
15748 #define EPDC_TCE_POLARITY_TOG_SDOE_POL_SHIFT     2
15749 #define EPDC_TCE_POLARITY_TOG_GDOE_POL_MASK      0x8u
15750 #define EPDC_TCE_POLARITY_TOG_GDOE_POL_SHIFT     3
15751 #define EPDC_TCE_POLARITY_TOG_GDSP_POL_MASK      0x10u
15752 #define EPDC_TCE_POLARITY_TOG_GDSP_POL_SHIFT     4
15753 /* TCE_TIMING1 Bit Fields */
15754 #define EPDC_TCE_TIMING1_SDCLK_SHIFT_MASK        0x3u
15755 #define EPDC_TCE_TIMING1_SDCLK_SHIFT_SHIFT       0
15756 #define EPDC_TCE_TIMING1_SDCLK_SHIFT(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SDCLK_SHIFT_MASK)
15757 #define EPDC_TCE_TIMING1_SDCLK_INVERT_MASK       0x8u
15758 #define EPDC_TCE_TIMING1_SDCLK_INVERT_SHIFT      3
15759 #define EPDC_TCE_TIMING1_SDLE_SHIFT_MASK         0x30u
15760 #define EPDC_TCE_TIMING1_SDLE_SHIFT_SHIFT        4
15761 #define EPDC_TCE_TIMING1_SDLE_SHIFT(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SDLE_SHIFT_MASK)
15762 /* TCE_TIMING1_SET Bit Fields */
15763 #define EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_MASK    0x3u
15764 #define EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_SHIFT   0
15765 #define EPDC_TCE_TIMING1_SET_SDCLK_SHIFT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_MASK)
15766 #define EPDC_TCE_TIMING1_SET_SDCLK_INVERT_MASK   0x8u
15767 #define EPDC_TCE_TIMING1_SET_SDCLK_INVERT_SHIFT  3
15768 #define EPDC_TCE_TIMING1_SET_SDLE_SHIFT_MASK     0x30u
15769 #define EPDC_TCE_TIMING1_SET_SDLE_SHIFT_SHIFT    4
15770 #define EPDC_TCE_TIMING1_SET_SDLE_SHIFT(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SET_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SET_SDLE_SHIFT_MASK)
15771 /* TCE_TIMING1_CLR Bit Fields */
15772 #define EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_MASK    0x3u
15773 #define EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_SHIFT   0
15774 #define EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_MASK)
15775 #define EPDC_TCE_TIMING1_CLR_SDCLK_INVERT_MASK   0x8u
15776 #define EPDC_TCE_TIMING1_CLR_SDCLK_INVERT_SHIFT  3
15777 #define EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_MASK     0x30u
15778 #define EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_SHIFT    4
15779 #define EPDC_TCE_TIMING1_CLR_SDLE_SHIFT(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_MASK)
15780 /* TCE_TIMING1_TOG Bit Fields */
15781 #define EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_MASK    0x3u
15782 #define EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_SHIFT   0
15783 #define EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_MASK)
15784 #define EPDC_TCE_TIMING1_TOG_SDCLK_INVERT_MASK   0x8u
15785 #define EPDC_TCE_TIMING1_TOG_SDCLK_INVERT_SHIFT  3
15786 #define EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_MASK     0x30u
15787 #define EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_SHIFT    4
15788 #define EPDC_TCE_TIMING1_TOG_SDLE_SHIFT(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_MASK)
15789 /* TCE_TIMING2 Bit Fields */
15790 #define EPDC_TCE_TIMING2_GDSP_OFFSET_MASK        0xFFFFu
15791 #define EPDC_TCE_TIMING2_GDSP_OFFSET_SHIFT       0
15792 #define EPDC_TCE_TIMING2_GDSP_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_GDSP_OFFSET_MASK)
15793 #define EPDC_TCE_TIMING2_GDCLK_HP_MASK           0xFFFF0000u
15794 #define EPDC_TCE_TIMING2_GDCLK_HP_SHIFT          16
15795 #define EPDC_TCE_TIMING2_GDCLK_HP(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_GDCLK_HP_MASK)
15796 /* TCE_TIMING2_SET Bit Fields */
15797 #define EPDC_TCE_TIMING2_SET_GDSP_OFFSET_MASK    0xFFFFu
15798 #define EPDC_TCE_TIMING2_SET_GDSP_OFFSET_SHIFT   0
15799 #define EPDC_TCE_TIMING2_SET_GDSP_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_SET_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_SET_GDSP_OFFSET_MASK)
15800 #define EPDC_TCE_TIMING2_SET_GDCLK_HP_MASK       0xFFFF0000u
15801 #define EPDC_TCE_TIMING2_SET_GDCLK_HP_SHIFT      16
15802 #define EPDC_TCE_TIMING2_SET_GDCLK_HP(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_SET_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_SET_GDCLK_HP_MASK)
15803 /* TCE_TIMING2_CLR Bit Fields */
15804 #define EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_MASK    0xFFFFu
15805 #define EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_SHIFT   0
15806 #define EPDC_TCE_TIMING2_CLR_GDSP_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_MASK)
15807 #define EPDC_TCE_TIMING2_CLR_GDCLK_HP_MASK       0xFFFF0000u
15808 #define EPDC_TCE_TIMING2_CLR_GDCLK_HP_SHIFT      16
15809 #define EPDC_TCE_TIMING2_CLR_GDCLK_HP(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_CLR_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_CLR_GDCLK_HP_MASK)
15810 /* TCE_TIMING2_TOG Bit Fields */
15811 #define EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_MASK    0xFFFFu
15812 #define EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_SHIFT   0
15813 #define EPDC_TCE_TIMING2_TOG_GDSP_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_MASK)
15814 #define EPDC_TCE_TIMING2_TOG_GDCLK_HP_MASK       0xFFFF0000u
15815 #define EPDC_TCE_TIMING2_TOG_GDCLK_HP_SHIFT      16
15816 #define EPDC_TCE_TIMING2_TOG_GDCLK_HP(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_TOG_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_TOG_GDCLK_HP_MASK)
15817 /* TCE_TIMING3 Bit Fields */
15818 #define EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK       0xFFFFu
15819 #define EPDC_TCE_TIMING3_GDCLK_OFFSET_SHIFT      0
15820 #define EPDC_TCE_TIMING3_GDCLK_OFFSET(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK)
15821 #define EPDC_TCE_TIMING3_GDOE_OFFSET_MASK        0xFFFF0000u
15822 #define EPDC_TCE_TIMING3_GDOE_OFFSET_SHIFT       16
15823 #define EPDC_TCE_TIMING3_GDOE_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
15824 /* TCE_TIMING3_SET Bit Fields */
15825 #define EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_MASK   0xFFFFu
15826 #define EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_SHIFT  0
15827 #define EPDC_TCE_TIMING3_SET_GDCLK_OFFSET(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_MASK)
15828 #define EPDC_TCE_TIMING3_SET_GDOE_OFFSET_MASK    0xFFFF0000u
15829 #define EPDC_TCE_TIMING3_SET_GDOE_OFFSET_SHIFT   16
15830 #define EPDC_TCE_TIMING3_SET_GDOE_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_SET_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_SET_GDOE_OFFSET_MASK)
15831 /* TCE_TIMING3_CLR Bit Fields */
15832 #define EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_MASK   0xFFFFu
15833 #define EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_SHIFT  0
15834 #define EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_MASK)
15835 #define EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_MASK    0xFFFF0000u
15836 #define EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_SHIFT   16
15837 #define EPDC_TCE_TIMING3_CLR_GDOE_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_MASK)
15838 /* TCE_TIMING3_TOG Bit Fields */
15839 #define EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_MASK   0xFFFFu
15840 #define EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_SHIFT  0
15841 #define EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_MASK)
15842 #define EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_MASK    0xFFFF0000u
15843 #define EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_SHIFT   16
15844 #define EPDC_TCE_TIMING3_TOG_GDOE_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_MASK)
15845 /* PIGEON_CTRL0 Bit Fields */
15846 #define EPDC_PIGEON_CTRL0_FD_PERIOD_MASK         0xFFFu
15847 #define EPDC_PIGEON_CTRL0_FD_PERIOD_SHIFT        0
15848 #define EPDC_PIGEON_CTRL0_FD_PERIOD(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_FD_PERIOD_MASK)
15849 #define EPDC_PIGEON_CTRL0_LD_PERIOD_MASK         0xFFF0000u
15850 #define EPDC_PIGEON_CTRL0_LD_PERIOD_SHIFT        16
15851 #define EPDC_PIGEON_CTRL0_LD_PERIOD(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_LD_PERIOD_MASK)
15852 /* PIGEON_CTRL0_SET Bit Fields */
15853 #define EPDC_PIGEON_CTRL0_SET_FD_PERIOD_MASK     0xFFFu
15854 #define EPDC_PIGEON_CTRL0_SET_FD_PERIOD_SHIFT    0
15855 #define EPDC_PIGEON_CTRL0_SET_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_SET_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_SET_FD_PERIOD_MASK)
15856 #define EPDC_PIGEON_CTRL0_SET_LD_PERIOD_MASK     0xFFF0000u
15857 #define EPDC_PIGEON_CTRL0_SET_LD_PERIOD_SHIFT    16
15858 #define EPDC_PIGEON_CTRL0_SET_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_SET_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_SET_LD_PERIOD_MASK)
15859 /* PIGEON_CTRL0_CLR Bit Fields */
15860 #define EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_MASK     0xFFFu
15861 #define EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_SHIFT    0
15862 #define EPDC_PIGEON_CTRL0_CLR_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_MASK)
15863 #define EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_MASK     0xFFF0000u
15864 #define EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_SHIFT    16
15865 #define EPDC_PIGEON_CTRL0_CLR_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_MASK)
15866 /* PIGEON_CTRL0_TOG Bit Fields */
15867 #define EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_MASK     0xFFFu
15868 #define EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_SHIFT    0
15869 #define EPDC_PIGEON_CTRL0_TOG_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_MASK)
15870 #define EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_MASK     0xFFF0000u
15871 #define EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_SHIFT    16
15872 #define EPDC_PIGEON_CTRL0_TOG_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_MASK)
15873 /* PIGEON_CTRL1 Bit Fields */
15874 #define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_MASK  0xFFFu
15875 #define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_SHIFT 0
15876 #define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD(x)    (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_MASK)
15877 #define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_MASK  0xFFF0000u
15878 #define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_SHIFT 16
15879 #define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES(x)    (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_MASK)
15880 /* PIGEON_CTRL1_SET Bit Fields */
15881 #define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_MASK 0xFFFu
15882 #define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_SHIFT 0
15883 #define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_MASK)
15884 #define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_MASK 0xFFF0000u
15885 #define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_SHIFT 16
15886 #define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_MASK)
15887 /* PIGEON_CTRL1_CLR Bit Fields */
15888 #define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_MASK 0xFFFu
15889 #define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_SHIFT 0
15890 #define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_MASK)
15891 #define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_MASK 0xFFF0000u
15892 #define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_SHIFT 16
15893 #define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_MASK)
15894 /* PIGEON_CTRL1_TOG Bit Fields */
15895 #define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_MASK 0xFFFu
15896 #define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_SHIFT 0
15897 #define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_MASK)
15898 #define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_MASK 0xFFF0000u
15899 #define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_SHIFT 16
15900 #define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_MASK)
15901 /* IRQ_MASK1 Bit Fields */
15902 #define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_MASK    0xFFFFFFFFu
15903 #define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_SHIFT   0
15904 #define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_MASK)
15905 /* IRQ_MASK1_SET Bit Fields */
15906 #define EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu
15907 #define EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_SHIFT 0
15908 #define EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_MASK)
15909 /* IRQ_MASK1_CLR Bit Fields */
15910 #define EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu
15911 #define EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_SHIFT 0
15912 #define EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_MASK)
15913 /* IRQ_MASK1_TOG Bit Fields */
15914 #define EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu
15915 #define EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_SHIFT 0
15916 #define EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_MASK)
15917 /* IRQ_MASK2 Bit Fields */
15918 #define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_MASK    0xFFFFFFFFu
15919 #define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_SHIFT   0
15920 #define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_MASK)
15921 /* IRQ_MASK2_SET Bit Fields */
15922 #define EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu
15923 #define EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_SHIFT 0
15924 #define EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_MASK)
15925 /* IRQ_MASK2_CLR Bit Fields */
15926 #define EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu
15927 #define EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_SHIFT 0
15928 #define EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_MASK)
15929 /* IRQ_MASK2_TOG Bit Fields */
15930 #define EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu
15931 #define EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_SHIFT 0
15932 #define EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_MASK)
15933 /* IRQ1 Bit Fields */
15934 #define EPDC_IRQ1_LUTN_CMPLT_IRQ_MASK            0xFFFFFFFFu
15935 #define EPDC_IRQ1_LUTN_CMPLT_IRQ_SHIFT           0
15936 #define EPDC_IRQ1_LUTN_CMPLT_IRQ(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_LUTN_CMPLT_IRQ_MASK)
15937 /* IRQ1_SET Bit Fields */
15938 #define EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_MASK        0xFFFFFFFFu
15939 #define EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_SHIFT       0
15940 #define EPDC_IRQ1_SET_LUTN_CMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_MASK)
15941 /* IRQ1_CLR Bit Fields */
15942 #define EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_MASK        0xFFFFFFFFu
15943 #define EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_SHIFT       0
15944 #define EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_MASK)
15945 /* IRQ1_TOG Bit Fields */
15946 #define EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_MASK        0xFFFFFFFFu
15947 #define EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_SHIFT       0
15948 #define EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_MASK)
15949 /* IRQ2 Bit Fields */
15950 #define EPDC_IRQ2_LUTN_CMPLT_IRQ_MASK            0xFFFFFFFFu
15951 #define EPDC_IRQ2_LUTN_CMPLT_IRQ_SHIFT           0
15952 #define EPDC_IRQ2_LUTN_CMPLT_IRQ(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_LUTN_CMPLT_IRQ_MASK)
15953 /* IRQ2_SET Bit Fields */
15954 #define EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_MASK        0xFFFFFFFFu
15955 #define EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_SHIFT       0
15956 #define EPDC_IRQ2_SET_LUTN_CMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_MASK)
15957 /* IRQ2_CLR Bit Fields */
15958 #define EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_MASK        0xFFFFFFFFu
15959 #define EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_SHIFT       0
15960 #define EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_MASK)
15961 /* IRQ2_TOG Bit Fields */
15962 #define EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_MASK        0xFFFFFFFFu
15963 #define EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_SHIFT       0
15964 #define EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_MASK)
15965 /* IRQ_MASK Bit Fields */
15966 #define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_MASK       0x10000u
15967 #define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_SHIFT      16
15968 #define EPDC_IRQ_MASK_COL_IRQ_EN_MASK            0x20000u
15969 #define EPDC_IRQ_MASK_COL_IRQ_EN_SHIFT           17
15970 #define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_MASK   0x40000u
15971 #define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_SHIFT  18
15972 #define EPDC_IRQ_MASK_FRAME_END_IRQ_EN_MASK      0x80000u
15973 #define EPDC_IRQ_MASK_FRAME_END_IRQ_EN_SHIFT     19
15974 #define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_MASK      0x100000u
15975 #define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_SHIFT     20
15976 #define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_MASK       0x200000u
15977 #define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_SHIFT      21
15978 #define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_MASK       0x400000u
15979 #define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_SHIFT      22
15980 #define EPDC_IRQ_MASK_PWR_IRQ_EN_MASK            0x800000u
15981 #define EPDC_IRQ_MASK_PWR_IRQ_EN_SHIFT           23
15982 /* IRQ_MASK_SET Bit Fields */
15983 #define EPDC_IRQ_MASK_SET_WB_CMPLT_IRQ_EN_MASK   0x10000u
15984 #define EPDC_IRQ_MASK_SET_WB_CMPLT_IRQ_EN_SHIFT  16
15985 #define EPDC_IRQ_MASK_SET_COL_IRQ_EN_MASK        0x20000u
15986 #define EPDC_IRQ_MASK_SET_COL_IRQ_EN_SHIFT       17
15987 #define EPDC_IRQ_MASK_SET_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u
15988 #define EPDC_IRQ_MASK_SET_TCE_UNDERRUN_IRQ_EN_SHIFT 18
15989 #define EPDC_IRQ_MASK_SET_FRAME_END_IRQ_EN_MASK  0x80000u
15990 #define EPDC_IRQ_MASK_SET_FRAME_END_IRQ_EN_SHIFT 19
15991 #define EPDC_IRQ_MASK_SET_BUS_ERROR_IRQ_EN_MASK  0x100000u
15992 #define EPDC_IRQ_MASK_SET_BUS_ERROR_IRQ_EN_SHIFT 20
15993 #define EPDC_IRQ_MASK_SET_TCE_IDLE_IRQ_EN_MASK   0x200000u
15994 #define EPDC_IRQ_MASK_SET_TCE_IDLE_IRQ_EN_SHIFT  21
15995 #define EPDC_IRQ_MASK_SET_UPD_DONE_IRQ_EN_MASK   0x400000u
15996 #define EPDC_IRQ_MASK_SET_UPD_DONE_IRQ_EN_SHIFT  22
15997 #define EPDC_IRQ_MASK_SET_PWR_IRQ_EN_MASK        0x800000u
15998 #define EPDC_IRQ_MASK_SET_PWR_IRQ_EN_SHIFT       23
15999 /* IRQ_MASK_CLR Bit Fields */
16000 #define EPDC_IRQ_MASK_CLR_WB_CMPLT_IRQ_EN_MASK   0x10000u
16001 #define EPDC_IRQ_MASK_CLR_WB_CMPLT_IRQ_EN_SHIFT  16
16002 #define EPDC_IRQ_MASK_CLR_COL_IRQ_EN_MASK        0x20000u
16003 #define EPDC_IRQ_MASK_CLR_COL_IRQ_EN_SHIFT       17
16004 #define EPDC_IRQ_MASK_CLR_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u
16005 #define EPDC_IRQ_MASK_CLR_TCE_UNDERRUN_IRQ_EN_SHIFT 18
16006 #define EPDC_IRQ_MASK_CLR_FRAME_END_IRQ_EN_MASK  0x80000u
16007 #define EPDC_IRQ_MASK_CLR_FRAME_END_IRQ_EN_SHIFT 19
16008 #define EPDC_IRQ_MASK_CLR_BUS_ERROR_IRQ_EN_MASK  0x100000u
16009 #define EPDC_IRQ_MASK_CLR_BUS_ERROR_IRQ_EN_SHIFT 20
16010 #define EPDC_IRQ_MASK_CLR_TCE_IDLE_IRQ_EN_MASK   0x200000u
16011 #define EPDC_IRQ_MASK_CLR_TCE_IDLE_IRQ_EN_SHIFT  21
16012 #define EPDC_IRQ_MASK_CLR_UPD_DONE_IRQ_EN_MASK   0x400000u
16013 #define EPDC_IRQ_MASK_CLR_UPD_DONE_IRQ_EN_SHIFT  22
16014 #define EPDC_IRQ_MASK_CLR_PWR_IRQ_EN_MASK        0x800000u
16015 #define EPDC_IRQ_MASK_CLR_PWR_IRQ_EN_SHIFT       23
16016 /* IRQ_MASK_TOG Bit Fields */
16017 #define EPDC_IRQ_MASK_TOG_WB_CMPLT_IRQ_EN_MASK   0x10000u
16018 #define EPDC_IRQ_MASK_TOG_WB_CMPLT_IRQ_EN_SHIFT  16
16019 #define EPDC_IRQ_MASK_TOG_COL_IRQ_EN_MASK        0x20000u
16020 #define EPDC_IRQ_MASK_TOG_COL_IRQ_EN_SHIFT       17
16021 #define EPDC_IRQ_MASK_TOG_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u
16022 #define EPDC_IRQ_MASK_TOG_TCE_UNDERRUN_IRQ_EN_SHIFT 18
16023 #define EPDC_IRQ_MASK_TOG_FRAME_END_IRQ_EN_MASK  0x80000u
16024 #define EPDC_IRQ_MASK_TOG_FRAME_END_IRQ_EN_SHIFT 19
16025 #define EPDC_IRQ_MASK_TOG_BUS_ERROR_IRQ_EN_MASK  0x100000u
16026 #define EPDC_IRQ_MASK_TOG_BUS_ERROR_IRQ_EN_SHIFT 20
16027 #define EPDC_IRQ_MASK_TOG_TCE_IDLE_IRQ_EN_MASK   0x200000u
16028 #define EPDC_IRQ_MASK_TOG_TCE_IDLE_IRQ_EN_SHIFT  21
16029 #define EPDC_IRQ_MASK_TOG_UPD_DONE_IRQ_EN_MASK   0x400000u
16030 #define EPDC_IRQ_MASK_TOG_UPD_DONE_IRQ_EN_SHIFT  22
16031 #define EPDC_IRQ_MASK_TOG_PWR_IRQ_EN_MASK        0x800000u
16032 #define EPDC_IRQ_MASK_TOG_PWR_IRQ_EN_SHIFT       23
16033 /* IRQ Bit Fields */
16034 #define EPDC_IRQ_WB_CMPLT_IRQ_MASK               0x10000u
16035 #define EPDC_IRQ_WB_CMPLT_IRQ_SHIFT              16
16036 #define EPDC_IRQ_LUT_COL_IRQ_MASK                0x20000u
16037 #define EPDC_IRQ_LUT_COL_IRQ_SHIFT               17
16038 #define EPDC_IRQ_TCE_UNDERRUN_IRQ_MASK           0x40000u
16039 #define EPDC_IRQ_TCE_UNDERRUN_IRQ_SHIFT          18
16040 #define EPDC_IRQ_FRAME_END_IRQ_MASK              0x80000u
16041 #define EPDC_IRQ_FRAME_END_IRQ_SHIFT             19
16042 #define EPDC_IRQ_BUS_ERROR_IRQ_MASK              0x100000u
16043 #define EPDC_IRQ_BUS_ERROR_IRQ_SHIFT             20
16044 #define EPDC_IRQ_TCE_IDLE_IRQ_MASK               0x200000u
16045 #define EPDC_IRQ_TCE_IDLE_IRQ_SHIFT              21
16046 #define EPDC_IRQ_UPD_DONE_IRQ_MASK               0x400000u
16047 #define EPDC_IRQ_UPD_DONE_IRQ_SHIFT              22
16048 #define EPDC_IRQ_PWR_IRQ_MASK                    0x800000u
16049 #define EPDC_IRQ_PWR_IRQ_SHIFT                   23
16050 /* IRQ_SET Bit Fields */
16051 #define EPDC_IRQ_SET_WB_CMPLT_IRQ_MASK           0x10000u
16052 #define EPDC_IRQ_SET_WB_CMPLT_IRQ_SHIFT          16
16053 #define EPDC_IRQ_SET_LUT_COL_IRQ_MASK            0x20000u
16054 #define EPDC_IRQ_SET_LUT_COL_IRQ_SHIFT           17
16055 #define EPDC_IRQ_SET_TCE_UNDERRUN_IRQ_MASK       0x40000u
16056 #define EPDC_IRQ_SET_TCE_UNDERRUN_IRQ_SHIFT      18
16057 #define EPDC_IRQ_SET_FRAME_END_IRQ_MASK          0x80000u
16058 #define EPDC_IRQ_SET_FRAME_END_IRQ_SHIFT         19
16059 #define EPDC_IRQ_SET_BUS_ERROR_IRQ_MASK          0x100000u
16060 #define EPDC_IRQ_SET_BUS_ERROR_IRQ_SHIFT         20
16061 #define EPDC_IRQ_SET_TCE_IDLE_IRQ_MASK           0x200000u
16062 #define EPDC_IRQ_SET_TCE_IDLE_IRQ_SHIFT          21
16063 #define EPDC_IRQ_SET_UPD_DONE_IRQ_MASK           0x400000u
16064 #define EPDC_IRQ_SET_UPD_DONE_IRQ_SHIFT          22
16065 #define EPDC_IRQ_SET_PWR_IRQ_MASK                0x800000u
16066 #define EPDC_IRQ_SET_PWR_IRQ_SHIFT               23
16067 /* IRQ_CLR Bit Fields */
16068 #define EPDC_IRQ_CLR_WB_CMPLT_IRQ_MASK           0x10000u
16069 #define EPDC_IRQ_CLR_WB_CMPLT_IRQ_SHIFT          16
16070 #define EPDC_IRQ_CLR_LUT_COL_IRQ_MASK            0x20000u
16071 #define EPDC_IRQ_CLR_LUT_COL_IRQ_SHIFT           17
16072 #define EPDC_IRQ_CLR_TCE_UNDERRUN_IRQ_MASK       0x40000u
16073 #define EPDC_IRQ_CLR_TCE_UNDERRUN_IRQ_SHIFT      18
16074 #define EPDC_IRQ_CLR_FRAME_END_IRQ_MASK          0x80000u
16075 #define EPDC_IRQ_CLR_FRAME_END_IRQ_SHIFT         19
16076 #define EPDC_IRQ_CLR_BUS_ERROR_IRQ_MASK          0x100000u
16077 #define EPDC_IRQ_CLR_BUS_ERROR_IRQ_SHIFT         20
16078 #define EPDC_IRQ_CLR_TCE_IDLE_IRQ_MASK           0x200000u
16079 #define EPDC_IRQ_CLR_TCE_IDLE_IRQ_SHIFT          21
16080 #define EPDC_IRQ_CLR_UPD_DONE_IRQ_MASK           0x400000u
16081 #define EPDC_IRQ_CLR_UPD_DONE_IRQ_SHIFT          22
16082 #define EPDC_IRQ_CLR_PWR_IRQ_MASK                0x800000u
16083 #define EPDC_IRQ_CLR_PWR_IRQ_SHIFT               23
16084 /* IRQ_TOG Bit Fields */
16085 #define EPDC_IRQ_TOG_WB_CMPLT_IRQ_MASK           0x10000u
16086 #define EPDC_IRQ_TOG_WB_CMPLT_IRQ_SHIFT          16
16087 #define EPDC_IRQ_TOG_LUT_COL_IRQ_MASK            0x20000u
16088 #define EPDC_IRQ_TOG_LUT_COL_IRQ_SHIFT           17
16089 #define EPDC_IRQ_TOG_TCE_UNDERRUN_IRQ_MASK       0x40000u
16090 #define EPDC_IRQ_TOG_TCE_UNDERRUN_IRQ_SHIFT      18
16091 #define EPDC_IRQ_TOG_FRAME_END_IRQ_MASK          0x80000u
16092 #define EPDC_IRQ_TOG_FRAME_END_IRQ_SHIFT         19
16093 #define EPDC_IRQ_TOG_BUS_ERROR_IRQ_MASK          0x100000u
16094 #define EPDC_IRQ_TOG_BUS_ERROR_IRQ_SHIFT         20
16095 #define EPDC_IRQ_TOG_TCE_IDLE_IRQ_MASK           0x200000u
16096 #define EPDC_IRQ_TOG_TCE_IDLE_IRQ_SHIFT          21
16097 #define EPDC_IRQ_TOG_UPD_DONE_IRQ_MASK           0x400000u
16098 #define EPDC_IRQ_TOG_UPD_DONE_IRQ_SHIFT          22
16099 #define EPDC_IRQ_TOG_PWR_IRQ_MASK                0x800000u
16100 #define EPDC_IRQ_TOG_PWR_IRQ_SHIFT               23
16101 /* STATUS_LUTS1 Bit Fields */
16102 #define EPDC_STATUS_LUTS1_LUTN_STS_MASK          0xFFFFFFFFu
16103 #define EPDC_STATUS_LUTS1_LUTN_STS_SHIFT         0
16104 #define EPDC_STATUS_LUTS1_LUTN_STS(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_LUTN_STS_MASK)
16105 /* STATUS_LUTS1_SET Bit Fields */
16106 #define EPDC_STATUS_LUTS1_SET_LUTN_STS_MASK      0xFFFFFFFFu
16107 #define EPDC_STATUS_LUTS1_SET_LUTN_STS_SHIFT     0
16108 #define EPDC_STATUS_LUTS1_SET_LUTN_STS(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_SET_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_SET_LUTN_STS_MASK)
16109 /* STATUS_LUTS1_CLR Bit Fields */
16110 #define EPDC_STATUS_LUTS1_CLR_LUTN_STS_MASK      0xFFFFFFFFu
16111 #define EPDC_STATUS_LUTS1_CLR_LUTN_STS_SHIFT     0
16112 #define EPDC_STATUS_LUTS1_CLR_LUTN_STS(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_CLR_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_CLR_LUTN_STS_MASK)
16113 /* STATUS_LUTS1_TOG Bit Fields */
16114 #define EPDC_STATUS_LUTS1_TOG_LUTN_STS_MASK      0xFFFFFFFFu
16115 #define EPDC_STATUS_LUTS1_TOG_LUTN_STS_SHIFT     0
16116 #define EPDC_STATUS_LUTS1_TOG_LUTN_STS(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_TOG_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_TOG_LUTN_STS_MASK)
16117 /* STATUS_LUTS2 Bit Fields */
16118 #define EPDC_STATUS_LUTS2_LUTN_STS_MASK          0xFFFFFFFFu
16119 #define EPDC_STATUS_LUTS2_LUTN_STS_SHIFT         0
16120 #define EPDC_STATUS_LUTS2_LUTN_STS(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_LUTN_STS_MASK)
16121 /* STATUS_LUTS2_SET Bit Fields */
16122 #define EPDC_STATUS_LUTS2_SET_LUTN_STS_MASK      0xFFFFFFFFu
16123 #define EPDC_STATUS_LUTS2_SET_LUTN_STS_SHIFT     0
16124 #define EPDC_STATUS_LUTS2_SET_LUTN_STS(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_SET_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_SET_LUTN_STS_MASK)
16125 /* STATUS_LUTS2_CLR Bit Fields */
16126 #define EPDC_STATUS_LUTS2_CLR_LUTN_STS_MASK      0xFFFFFFFFu
16127 #define EPDC_STATUS_LUTS2_CLR_LUTN_STS_SHIFT     0
16128 #define EPDC_STATUS_LUTS2_CLR_LUTN_STS(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_CLR_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_CLR_LUTN_STS_MASK)
16129 /* STATUS_LUTS2_TOG Bit Fields */
16130 #define EPDC_STATUS_LUTS2_TOG_LUTN_STS_MASK      0xFFFFFFFFu
16131 #define EPDC_STATUS_LUTS2_TOG_LUTN_STS_SHIFT     0
16132 #define EPDC_STATUS_LUTS2_TOG_LUTN_STS(x)        (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_TOG_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_TOG_LUTN_STS_MASK)
16133 /* STATUS_NEXTLUT Bit Fields */
16134 #define EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK        0x3Fu
16135 #define EPDC_STATUS_NEXTLUT_NEXT_LUT_SHIFT       0
16136 #define EPDC_STATUS_NEXTLUT_NEXT_LUT(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_NEXTLUT_NEXT_LUT_SHIFT))&EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK)
16137 #define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_MASK  0x100u
16138 #define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_SHIFT 8
16139 /* STATUS_COL1 Bit Fields */
16140 #define EPDC_STATUS_COL1_LUTN_COL_STS_MASK       0xFFFFFFFFu
16141 #define EPDC_STATUS_COL1_LUTN_COL_STS_SHIFT      0
16142 #define EPDC_STATUS_COL1_LUTN_COL_STS(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_LUTN_COL_STS_MASK)
16143 /* STATUS_COL1_SET Bit Fields */
16144 #define EPDC_STATUS_COL1_SET_LUTN_COL_STS_MASK   0xFFFFFFFFu
16145 #define EPDC_STATUS_COL1_SET_LUTN_COL_STS_SHIFT  0
16146 #define EPDC_STATUS_COL1_SET_LUTN_COL_STS(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_SET_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_SET_LUTN_COL_STS_MASK)
16147 /* STATUS_COL1_CLR Bit Fields */
16148 #define EPDC_STATUS_COL1_CLR_LUTN_COL_STS_MASK   0xFFFFFFFFu
16149 #define EPDC_STATUS_COL1_CLR_LUTN_COL_STS_SHIFT  0
16150 #define EPDC_STATUS_COL1_CLR_LUTN_COL_STS(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_CLR_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_CLR_LUTN_COL_STS_MASK)
16151 /* STATUS_COL1_TOG Bit Fields */
16152 #define EPDC_STATUS_COL1_TOG_LUTN_COL_STS_MASK   0xFFFFFFFFu
16153 #define EPDC_STATUS_COL1_TOG_LUTN_COL_STS_SHIFT  0
16154 #define EPDC_STATUS_COL1_TOG_LUTN_COL_STS(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_TOG_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_TOG_LUTN_COL_STS_MASK)
16155 /* STATUS_COL2 Bit Fields */
16156 #define EPDC_STATUS_COL2_LUTN_COL_STS_MASK       0xFFFFFFFFu
16157 #define EPDC_STATUS_COL2_LUTN_COL_STS_SHIFT      0
16158 #define EPDC_STATUS_COL2_LUTN_COL_STS(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_LUTN_COL_STS_MASK)
16159 /* STATUS_COL2_SET Bit Fields */
16160 #define EPDC_STATUS_COL2_SET_LUTN_COL_STS_MASK   0xFFFFFFFFu
16161 #define EPDC_STATUS_COL2_SET_LUTN_COL_STS_SHIFT  0
16162 #define EPDC_STATUS_COL2_SET_LUTN_COL_STS(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_SET_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_SET_LUTN_COL_STS_MASK)
16163 /* STATUS_COL2_CLR Bit Fields */
16164 #define EPDC_STATUS_COL2_CLR_LUTN_COL_STS_MASK   0xFFFFFFFFu
16165 #define EPDC_STATUS_COL2_CLR_LUTN_COL_STS_SHIFT  0
16166 #define EPDC_STATUS_COL2_CLR_LUTN_COL_STS(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_CLR_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_CLR_LUTN_COL_STS_MASK)
16167 /* STATUS_COL2_TOG Bit Fields */
16168 #define EPDC_STATUS_COL2_TOG_LUTN_COL_STS_MASK   0xFFFFFFFFu
16169 #define EPDC_STATUS_COL2_TOG_LUTN_COL_STS_SHIFT  0
16170 #define EPDC_STATUS_COL2_TOG_LUTN_COL_STS(x)     (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_TOG_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_TOG_LUTN_COL_STS_MASK)
16171 /* STATUS Bit Fields */
16172 #define EPDC_STATUS_WB_BUSY_MASK                 0x1u
16173 #define EPDC_STATUS_WB_BUSY_SHIFT                0
16174 #define EPDC_STATUS_LUTS_BUSY_MASK               0x2u
16175 #define EPDC_STATUS_LUTS_BUSY_SHIFT              1
16176 #define EPDC_STATUS_LUTS_UNDERRUN_MASK           0x4u
16177 #define EPDC_STATUS_LUTS_UNDERRUN_SHIFT          2
16178 #define EPDC_STATUS_UPD_VOID_MASK                0x8u
16179 #define EPDC_STATUS_UPD_VOID_SHIFT               3
16180 #define EPDC_STATUS_HISTOGRAM_NP_MASK            0x1F00u
16181 #define EPDC_STATUS_HISTOGRAM_NP_SHIFT           8
16182 #define EPDC_STATUS_HISTOGRAM_NP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_HISTOGRAM_NP_MASK)
16183 #define EPDC_STATUS_HISTOGRAM_CP_MASK            0x1F0000u
16184 #define EPDC_STATUS_HISTOGRAM_CP_SHIFT           16
16185 #define EPDC_STATUS_HISTOGRAM_CP(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_HISTOGRAM_CP_MASK)
16186 /* STATUS_SET Bit Fields */
16187 #define EPDC_STATUS_SET_WB_BUSY_MASK             0x1u
16188 #define EPDC_STATUS_SET_WB_BUSY_SHIFT            0
16189 #define EPDC_STATUS_SET_LUTS_BUSY_MASK           0x2u
16190 #define EPDC_STATUS_SET_LUTS_BUSY_SHIFT          1
16191 #define EPDC_STATUS_SET_LUTS_UNDERRUN_MASK       0x4u
16192 #define EPDC_STATUS_SET_LUTS_UNDERRUN_SHIFT      2
16193 #define EPDC_STATUS_SET_UPD_VOID_MASK            0x8u
16194 #define EPDC_STATUS_SET_UPD_VOID_SHIFT           3
16195 #define EPDC_STATUS_SET_HISTOGRAM_NP_MASK        0x1F00u
16196 #define EPDC_STATUS_SET_HISTOGRAM_NP_SHIFT       8
16197 #define EPDC_STATUS_SET_HISTOGRAM_NP(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_SET_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_SET_HISTOGRAM_NP_MASK)
16198 #define EPDC_STATUS_SET_HISTOGRAM_CP_MASK        0x1F0000u
16199 #define EPDC_STATUS_SET_HISTOGRAM_CP_SHIFT       16
16200 #define EPDC_STATUS_SET_HISTOGRAM_CP(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_SET_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_SET_HISTOGRAM_CP_MASK)
16201 /* STATUS_CLR Bit Fields */
16202 #define EPDC_STATUS_CLR_WB_BUSY_MASK             0x1u
16203 #define EPDC_STATUS_CLR_WB_BUSY_SHIFT            0
16204 #define EPDC_STATUS_CLR_LUTS_BUSY_MASK           0x2u
16205 #define EPDC_STATUS_CLR_LUTS_BUSY_SHIFT          1
16206 #define EPDC_STATUS_CLR_LUTS_UNDERRUN_MASK       0x4u
16207 #define EPDC_STATUS_CLR_LUTS_UNDERRUN_SHIFT      2
16208 #define EPDC_STATUS_CLR_UPD_VOID_MASK            0x8u
16209 #define EPDC_STATUS_CLR_UPD_VOID_SHIFT           3
16210 #define EPDC_STATUS_CLR_HISTOGRAM_NP_MASK        0x1F00u
16211 #define EPDC_STATUS_CLR_HISTOGRAM_NP_SHIFT       8
16212 #define EPDC_STATUS_CLR_HISTOGRAM_NP(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_CLR_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_CLR_HISTOGRAM_NP_MASK)
16213 #define EPDC_STATUS_CLR_HISTOGRAM_CP_MASK        0x1F0000u
16214 #define EPDC_STATUS_CLR_HISTOGRAM_CP_SHIFT       16
16215 #define EPDC_STATUS_CLR_HISTOGRAM_CP(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_CLR_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_CLR_HISTOGRAM_CP_MASK)
16216 /* STATUS_TOG Bit Fields */
16217 #define EPDC_STATUS_TOG_WB_BUSY_MASK             0x1u
16218 #define EPDC_STATUS_TOG_WB_BUSY_SHIFT            0
16219 #define EPDC_STATUS_TOG_LUTS_BUSY_MASK           0x2u
16220 #define EPDC_STATUS_TOG_LUTS_BUSY_SHIFT          1
16221 #define EPDC_STATUS_TOG_LUTS_UNDERRUN_MASK       0x4u
16222 #define EPDC_STATUS_TOG_LUTS_UNDERRUN_SHIFT      2
16223 #define EPDC_STATUS_TOG_UPD_VOID_MASK            0x8u
16224 #define EPDC_STATUS_TOG_UPD_VOID_SHIFT           3
16225 #define EPDC_STATUS_TOG_HISTOGRAM_NP_MASK        0x1F00u
16226 #define EPDC_STATUS_TOG_HISTOGRAM_NP_SHIFT       8
16227 #define EPDC_STATUS_TOG_HISTOGRAM_NP(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_TOG_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_TOG_HISTOGRAM_NP_MASK)
16228 #define EPDC_STATUS_TOG_HISTOGRAM_CP_MASK        0x1F0000u
16229 #define EPDC_STATUS_TOG_HISTOGRAM_CP_SHIFT       16
16230 #define EPDC_STATUS_TOG_HISTOGRAM_CP(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_TOG_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_TOG_HISTOGRAM_CP_MASK)
16231 /* UPD_COL_CORD Bit Fields */
16232 #define EPDC_UPD_COL_CORD_XCORD_MASK             0x1FFFu
16233 #define EPDC_UPD_COL_CORD_XCORD_SHIFT            0
16234 #define EPDC_UPD_COL_CORD_XCORD(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_CORD_XCORD_SHIFT))&EPDC_UPD_COL_CORD_XCORD_MASK)
16235 #define EPDC_UPD_COL_CORD_YCORD_MASK             0x1FFF0000u
16236 #define EPDC_UPD_COL_CORD_YCORD_SHIFT            16
16237 #define EPDC_UPD_COL_CORD_YCORD(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_CORD_YCORD_SHIFT))&EPDC_UPD_COL_CORD_YCORD_MASK)
16238 /* UPD_COL_SIZE Bit Fields */
16239 #define EPDC_UPD_COL_SIZE_WIDTH_MASK             0x1FFFu
16240 #define EPDC_UPD_COL_SIZE_WIDTH_SHIFT            0
16241 #define EPDC_UPD_COL_SIZE_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_SIZE_WIDTH_SHIFT))&EPDC_UPD_COL_SIZE_WIDTH_MASK)
16242 #define EPDC_UPD_COL_SIZE_HEIGHT_MASK            0x1FFF0000u
16243 #define EPDC_UPD_COL_SIZE_HEIGHT_SHIFT           16
16244 #define EPDC_UPD_COL_SIZE_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_SIZE_HEIGHT_SHIFT))&EPDC_UPD_COL_SIZE_HEIGHT_MASK)
16245 /* HIST1_PARAM Bit Fields */
16246 #define EPDC_HIST1_PARAM_VALUE0_MASK             0x1Fu
16247 #define EPDC_HIST1_PARAM_VALUE0_SHIFT            0
16248 #define EPDC_HIST1_PARAM_VALUE0(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST1_PARAM_VALUE0_SHIFT))&EPDC_HIST1_PARAM_VALUE0_MASK)
16249 #define EPDC_HIST1_PARAM_RSVD_MASK               0xFFFFFFE0u
16250 #define EPDC_HIST1_PARAM_RSVD_SHIFT              5
16251 #define EPDC_HIST1_PARAM_RSVD(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_HIST1_PARAM_RSVD_SHIFT))&EPDC_HIST1_PARAM_RSVD_MASK)
16252 /* HIST2_PARAM Bit Fields */
16253 #define EPDC_HIST2_PARAM_VALUE0_MASK             0x1Fu
16254 #define EPDC_HIST2_PARAM_VALUE0_SHIFT            0
16255 #define EPDC_HIST2_PARAM_VALUE0(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST2_PARAM_VALUE0_SHIFT))&EPDC_HIST2_PARAM_VALUE0_MASK)
16256 #define EPDC_HIST2_PARAM_VALUE1_MASK             0x1F00u
16257 #define EPDC_HIST2_PARAM_VALUE1_SHIFT            8
16258 #define EPDC_HIST2_PARAM_VALUE1(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST2_PARAM_VALUE1_SHIFT))&EPDC_HIST2_PARAM_VALUE1_MASK)
16259 #define EPDC_HIST2_PARAM_RSVD_MASK               0xFFFF0000u
16260 #define EPDC_HIST2_PARAM_RSVD_SHIFT              16
16261 #define EPDC_HIST2_PARAM_RSVD(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_HIST2_PARAM_RSVD_SHIFT))&EPDC_HIST2_PARAM_RSVD_MASK)
16262 /* HIST4_PARAM Bit Fields */
16263 #define EPDC_HIST4_PARAM_VALUE0_MASK             0x1Fu
16264 #define EPDC_HIST4_PARAM_VALUE0_SHIFT            0
16265 #define EPDC_HIST4_PARAM_VALUE0(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE0_SHIFT))&EPDC_HIST4_PARAM_VALUE0_MASK)
16266 #define EPDC_HIST4_PARAM_VALUE1_MASK             0x1F00u
16267 #define EPDC_HIST4_PARAM_VALUE1_SHIFT            8
16268 #define EPDC_HIST4_PARAM_VALUE1(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE1_SHIFT))&EPDC_HIST4_PARAM_VALUE1_MASK)
16269 #define EPDC_HIST4_PARAM_VALUE2_MASK             0x1F0000u
16270 #define EPDC_HIST4_PARAM_VALUE2_SHIFT            16
16271 #define EPDC_HIST4_PARAM_VALUE2(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE2_SHIFT))&EPDC_HIST4_PARAM_VALUE2_MASK)
16272 #define EPDC_HIST4_PARAM_VALUE3_MASK             0x1F000000u
16273 #define EPDC_HIST4_PARAM_VALUE3_SHIFT            24
16274 #define EPDC_HIST4_PARAM_VALUE3(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE3_SHIFT))&EPDC_HIST4_PARAM_VALUE3_MASK)
16275 /* HIST8_PARAM0 Bit Fields */
16276 #define EPDC_HIST8_PARAM0_VALUE0_MASK            0x1Fu
16277 #define EPDC_HIST8_PARAM0_VALUE0_SHIFT           0
16278 #define EPDC_HIST8_PARAM0_VALUE0(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE0_SHIFT))&EPDC_HIST8_PARAM0_VALUE0_MASK)
16279 #define EPDC_HIST8_PARAM0_VALUE1_MASK            0x1F00u
16280 #define EPDC_HIST8_PARAM0_VALUE1_SHIFT           8
16281 #define EPDC_HIST8_PARAM0_VALUE1(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE1_SHIFT))&EPDC_HIST8_PARAM0_VALUE1_MASK)
16282 #define EPDC_HIST8_PARAM0_VALUE2_MASK            0x1F0000u
16283 #define EPDC_HIST8_PARAM0_VALUE2_SHIFT           16
16284 #define EPDC_HIST8_PARAM0_VALUE2(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE2_SHIFT))&EPDC_HIST8_PARAM0_VALUE2_MASK)
16285 #define EPDC_HIST8_PARAM0_VALUE3_MASK            0x1F000000u
16286 #define EPDC_HIST8_PARAM0_VALUE3_SHIFT           24
16287 #define EPDC_HIST8_PARAM0_VALUE3(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE3_SHIFT))&EPDC_HIST8_PARAM0_VALUE3_MASK)
16288 /* HIST8_PARAM1 Bit Fields */
16289 #define EPDC_HIST8_PARAM1_VALUE4_MASK            0x1Fu
16290 #define EPDC_HIST8_PARAM1_VALUE4_SHIFT           0
16291 #define EPDC_HIST8_PARAM1_VALUE4(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE4_SHIFT))&EPDC_HIST8_PARAM1_VALUE4_MASK)
16292 #define EPDC_HIST8_PARAM1_VALUE5_MASK            0x1F00u
16293 #define EPDC_HIST8_PARAM1_VALUE5_SHIFT           8
16294 #define EPDC_HIST8_PARAM1_VALUE5(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE5_SHIFT))&EPDC_HIST8_PARAM1_VALUE5_MASK)
16295 #define EPDC_HIST8_PARAM1_VALUE6_MASK            0x1F0000u
16296 #define EPDC_HIST8_PARAM1_VALUE6_SHIFT           16
16297 #define EPDC_HIST8_PARAM1_VALUE6(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE6_SHIFT))&EPDC_HIST8_PARAM1_VALUE6_MASK)
16298 #define EPDC_HIST8_PARAM1_VALUE7_MASK            0x1F000000u
16299 #define EPDC_HIST8_PARAM1_VALUE7_SHIFT           24
16300 #define EPDC_HIST8_PARAM1_VALUE7(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE7_SHIFT))&EPDC_HIST8_PARAM1_VALUE7_MASK)
16301 /* HIST16_PARAM0 Bit Fields */
16302 #define EPDC_HIST16_PARAM0_VALUE0_MASK           0x1Fu
16303 #define EPDC_HIST16_PARAM0_VALUE0_SHIFT          0
16304 #define EPDC_HIST16_PARAM0_VALUE0(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE0_SHIFT))&EPDC_HIST16_PARAM0_VALUE0_MASK)
16305 #define EPDC_HIST16_PARAM0_VALUE1_MASK           0x1F00u
16306 #define EPDC_HIST16_PARAM0_VALUE1_SHIFT          8
16307 #define EPDC_HIST16_PARAM0_VALUE1(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE1_SHIFT))&EPDC_HIST16_PARAM0_VALUE1_MASK)
16308 #define EPDC_HIST16_PARAM0_VALUE2_MASK           0x1F0000u
16309 #define EPDC_HIST16_PARAM0_VALUE2_SHIFT          16
16310 #define EPDC_HIST16_PARAM0_VALUE2(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE2_SHIFT))&EPDC_HIST16_PARAM0_VALUE2_MASK)
16311 #define EPDC_HIST16_PARAM0_VALUE3_MASK           0x1F000000u
16312 #define EPDC_HIST16_PARAM0_VALUE3_SHIFT          24
16313 #define EPDC_HIST16_PARAM0_VALUE3(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE3_SHIFT))&EPDC_HIST16_PARAM0_VALUE3_MASK)
16314 /* HIST16_PARAM1 Bit Fields */
16315 #define EPDC_HIST16_PARAM1_VALUE4_MASK           0x1Fu
16316 #define EPDC_HIST16_PARAM1_VALUE4_SHIFT          0
16317 #define EPDC_HIST16_PARAM1_VALUE4(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE4_SHIFT))&EPDC_HIST16_PARAM1_VALUE4_MASK)
16318 #define EPDC_HIST16_PARAM1_VALUE5_MASK           0x1F00u
16319 #define EPDC_HIST16_PARAM1_VALUE5_SHIFT          8
16320 #define EPDC_HIST16_PARAM1_VALUE5(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE5_SHIFT))&EPDC_HIST16_PARAM1_VALUE5_MASK)
16321 #define EPDC_HIST16_PARAM1_VALUE6_MASK           0x1F0000u
16322 #define EPDC_HIST16_PARAM1_VALUE6_SHIFT          16
16323 #define EPDC_HIST16_PARAM1_VALUE6(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE6_SHIFT))&EPDC_HIST16_PARAM1_VALUE6_MASK)
16324 #define EPDC_HIST16_PARAM1_VALUE7_MASK           0x1F000000u
16325 #define EPDC_HIST16_PARAM1_VALUE7_SHIFT          24
16326 #define EPDC_HIST16_PARAM1_VALUE7(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE7_SHIFT))&EPDC_HIST16_PARAM1_VALUE7_MASK)
16327 /* HIST16_PARAM2 Bit Fields */
16328 #define EPDC_HIST16_PARAM2_VALUE8_MASK           0x1Fu
16329 #define EPDC_HIST16_PARAM2_VALUE8_SHIFT          0
16330 #define EPDC_HIST16_PARAM2_VALUE8(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE8_SHIFT))&EPDC_HIST16_PARAM2_VALUE8_MASK)
16331 #define EPDC_HIST16_PARAM2_VALUE9_MASK           0x1F00u
16332 #define EPDC_HIST16_PARAM2_VALUE9_SHIFT          8
16333 #define EPDC_HIST16_PARAM2_VALUE9(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE9_SHIFT))&EPDC_HIST16_PARAM2_VALUE9_MASK)
16334 #define EPDC_HIST16_PARAM2_VALUE10_MASK          0x1F0000u
16335 #define EPDC_HIST16_PARAM2_VALUE10_SHIFT         16
16336 #define EPDC_HIST16_PARAM2_VALUE10(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE10_SHIFT))&EPDC_HIST16_PARAM2_VALUE10_MASK)
16337 #define EPDC_HIST16_PARAM2_VALUE11_MASK          0x1F000000u
16338 #define EPDC_HIST16_PARAM2_VALUE11_SHIFT         24
16339 #define EPDC_HIST16_PARAM2_VALUE11(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE11_SHIFT))&EPDC_HIST16_PARAM2_VALUE11_MASK)
16340 /* HIST16_PARAM3 Bit Fields */
16341 #define EPDC_HIST16_PARAM3_VALUE12_MASK          0x1Fu
16342 #define EPDC_HIST16_PARAM3_VALUE12_SHIFT         0
16343 #define EPDC_HIST16_PARAM3_VALUE12(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE12_SHIFT))&EPDC_HIST16_PARAM3_VALUE12_MASK)
16344 #define EPDC_HIST16_PARAM3_VALUE13_MASK          0x1F00u
16345 #define EPDC_HIST16_PARAM3_VALUE13_SHIFT         8
16346 #define EPDC_HIST16_PARAM3_VALUE13(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE13_SHIFT))&EPDC_HIST16_PARAM3_VALUE13_MASK)
16347 #define EPDC_HIST16_PARAM3_VALUE14_MASK          0x1F0000u
16348 #define EPDC_HIST16_PARAM3_VALUE14_SHIFT         16
16349 #define EPDC_HIST16_PARAM3_VALUE14(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE14_SHIFT))&EPDC_HIST16_PARAM3_VALUE14_MASK)
16350 #define EPDC_HIST16_PARAM3_VALUE15_MASK          0x1F000000u
16351 #define EPDC_HIST16_PARAM3_VALUE15_SHIFT         24
16352 #define EPDC_HIST16_PARAM3_VALUE15(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE15_SHIFT))&EPDC_HIST16_PARAM3_VALUE15_MASK)
16353 /* GPIO Bit Fields */
16354 #define EPDC_GPIO_BDR_MASK                       0x3u
16355 #define EPDC_GPIO_BDR_SHIFT                      0
16356 #define EPDC_GPIO_BDR(x)                         (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_BDR_SHIFT))&EPDC_GPIO_BDR_MASK)
16357 #define EPDC_GPIO_PWRCTRL_MASK                   0x3Cu
16358 #define EPDC_GPIO_PWRCTRL_SHIFT                  2
16359 #define EPDC_GPIO_PWRCTRL(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_PWRCTRL_SHIFT))&EPDC_GPIO_PWRCTRL_MASK)
16360 #define EPDC_GPIO_PWRCOM_MASK                    0x40u
16361 #define EPDC_GPIO_PWRCOM_SHIFT                   6
16362 #define EPDC_GPIO_PWRWAKE_MASK                   0x80u
16363 #define EPDC_GPIO_PWRWAKE_SHIFT                  7
16364 #define EPDC_GPIO_PWRSTAT_MASK                   0x100u
16365 #define EPDC_GPIO_PWRSTAT_SHIFT                  8
16366 /* GPIO_SET Bit Fields */
16367 #define EPDC_GPIO_SET_BDR_MASK                   0x3u
16368 #define EPDC_GPIO_SET_BDR_SHIFT                  0
16369 #define EPDC_GPIO_SET_BDR(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_SET_BDR_SHIFT))&EPDC_GPIO_SET_BDR_MASK)
16370 #define EPDC_GPIO_SET_PWRCTRL_MASK               0x3Cu
16371 #define EPDC_GPIO_SET_PWRCTRL_SHIFT              2
16372 #define EPDC_GPIO_SET_PWRCTRL(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_SET_PWRCTRL_SHIFT))&EPDC_GPIO_SET_PWRCTRL_MASK)
16373 #define EPDC_GPIO_SET_PWRCOM_MASK                0x40u
16374 #define EPDC_GPIO_SET_PWRCOM_SHIFT               6
16375 #define EPDC_GPIO_SET_PWRWAKE_MASK               0x80u
16376 #define EPDC_GPIO_SET_PWRWAKE_SHIFT              7
16377 #define EPDC_GPIO_SET_PWRSTAT_MASK               0x100u
16378 #define EPDC_GPIO_SET_PWRSTAT_SHIFT              8
16379 /* GPIO_CLR Bit Fields */
16380 #define EPDC_GPIO_CLR_BDR_MASK                   0x3u
16381 #define EPDC_GPIO_CLR_BDR_SHIFT                  0
16382 #define EPDC_GPIO_CLR_BDR(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_CLR_BDR_SHIFT))&EPDC_GPIO_CLR_BDR_MASK)
16383 #define EPDC_GPIO_CLR_PWRCTRL_MASK               0x3Cu
16384 #define EPDC_GPIO_CLR_PWRCTRL_SHIFT              2
16385 #define EPDC_GPIO_CLR_PWRCTRL(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_CLR_PWRCTRL_SHIFT))&EPDC_GPIO_CLR_PWRCTRL_MASK)
16386 #define EPDC_GPIO_CLR_PWRCOM_MASK                0x40u
16387 #define EPDC_GPIO_CLR_PWRCOM_SHIFT               6
16388 #define EPDC_GPIO_CLR_PWRWAKE_MASK               0x80u
16389 #define EPDC_GPIO_CLR_PWRWAKE_SHIFT              7
16390 #define EPDC_GPIO_CLR_PWRSTAT_MASK               0x100u
16391 #define EPDC_GPIO_CLR_PWRSTAT_SHIFT              8
16392 /* GPIO_TOG Bit Fields */
16393 #define EPDC_GPIO_TOG_BDR_MASK                   0x3u
16394 #define EPDC_GPIO_TOG_BDR_SHIFT                  0
16395 #define EPDC_GPIO_TOG_BDR(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_TOG_BDR_SHIFT))&EPDC_GPIO_TOG_BDR_MASK)
16396 #define EPDC_GPIO_TOG_PWRCTRL_MASK               0x3Cu
16397 #define EPDC_GPIO_TOG_PWRCTRL_SHIFT              2
16398 #define EPDC_GPIO_TOG_PWRCTRL(x)                 (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_TOG_PWRCTRL_SHIFT))&EPDC_GPIO_TOG_PWRCTRL_MASK)
16399 #define EPDC_GPIO_TOG_PWRCOM_MASK                0x40u
16400 #define EPDC_GPIO_TOG_PWRCOM_SHIFT               6
16401 #define EPDC_GPIO_TOG_PWRWAKE_MASK               0x80u
16402 #define EPDC_GPIO_TOG_PWRWAKE_SHIFT              7
16403 #define EPDC_GPIO_TOG_PWRSTAT_MASK               0x100u
16404 #define EPDC_GPIO_TOG_PWRSTAT_SHIFT              8
16405 /* VERSION Bit Fields */
16406 #define EPDC_VERSION_STEP_MASK                   0xFFFFu
16407 #define EPDC_VERSION_STEP_SHIFT                  0
16408 #define EPDC_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x))<<EPDC_VERSION_STEP_SHIFT))&EPDC_VERSION_STEP_MASK)
16409 #define EPDC_VERSION_MINOR_MASK                  0xFF0000u
16410 #define EPDC_VERSION_MINOR_SHIFT                 16
16411 #define EPDC_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_VERSION_MINOR_SHIFT))&EPDC_VERSION_MINOR_MASK)
16412 #define EPDC_VERSION_MAJOR_MASK                  0xFF000000u
16413 #define EPDC_VERSION_MAJOR_SHIFT                 24
16414 #define EPDC_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x))<<EPDC_VERSION_MAJOR_SHIFT))&EPDC_VERSION_MAJOR_MASK)
16415 /* PIGEON_0_0 Bit Fields */
16416 #define EPDC_PIGEON_0_0_EN_MASK                  0x1u
16417 #define EPDC_PIGEON_0_0_EN_SHIFT                 0
16418 #define EPDC_PIGEON_0_0_POL_MASK                 0x2u
16419 #define EPDC_PIGEON_0_0_POL_SHIFT                1
16420 #define EPDC_PIGEON_0_0_INC_SEL_MASK             0xCu
16421 #define EPDC_PIGEON_0_0_INC_SEL_SHIFT            2
16422 #define EPDC_PIGEON_0_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_INC_SEL_SHIFT))&EPDC_PIGEON_0_0_INC_SEL_MASK)
16423 #define EPDC_PIGEON_0_0_OFFSET_MASK              0xF0u
16424 #define EPDC_PIGEON_0_0_OFFSET_SHIFT             4
16425 #define EPDC_PIGEON_0_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_OFFSET_SHIFT))&EPDC_PIGEON_0_0_OFFSET_MASK)
16426 #define EPDC_PIGEON_0_0_MASK_CNT_SEL_MASK        0xF00u
16427 #define EPDC_PIGEON_0_0_MASK_CNT_SEL_SHIFT       8
16428 #define EPDC_PIGEON_0_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_0_0_MASK_CNT_SEL_MASK)
16429 #define EPDC_PIGEON_0_0_MASK_CNT_MASK            0xFFF000u
16430 #define EPDC_PIGEON_0_0_MASK_CNT_SHIFT           12
16431 #define EPDC_PIGEON_0_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_MASK_CNT_SHIFT))&EPDC_PIGEON_0_0_MASK_CNT_MASK)
16432 #define EPDC_PIGEON_0_0_STATE_MASK_MASK          0xFF000000u
16433 #define EPDC_PIGEON_0_0_STATE_MASK_SHIFT         24
16434 #define EPDC_PIGEON_0_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_STATE_MASK_SHIFT))&EPDC_PIGEON_0_0_STATE_MASK_MASK)
16435 /* PIGEON_0_1 Bit Fields */
16436 #define EPDC_PIGEON_0_1_SET_CNT_MASK             0xFFFFu
16437 #define EPDC_PIGEON_0_1_SET_CNT_SHIFT            0
16438 #define EPDC_PIGEON_0_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_1_SET_CNT_SHIFT))&EPDC_PIGEON_0_1_SET_CNT_MASK)
16439 #define EPDC_PIGEON_0_1_CLR_CNT_MASK             0xFFFF0000u
16440 #define EPDC_PIGEON_0_1_CLR_CNT_SHIFT            16
16441 #define EPDC_PIGEON_0_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_1_CLR_CNT_SHIFT))&EPDC_PIGEON_0_1_CLR_CNT_MASK)
16442 /* PIGEON_0_2 Bit Fields */
16443 #define EPDC_PIGEON_0_2_SIG_LOGIC_MASK           0xFu
16444 #define EPDC_PIGEON_0_2_SIG_LOGIC_SHIFT          0
16445 #define EPDC_PIGEON_0_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_0_2_SIG_LOGIC_MASK)
16446 #define EPDC_PIGEON_0_2_SIG_ANOTHER_MASK         0x1F0u
16447 #define EPDC_PIGEON_0_2_SIG_ANOTHER_SHIFT        4
16448 #define EPDC_PIGEON_0_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_0_2_SIG_ANOTHER_MASK)
16449 /* PIGEON_1_0 Bit Fields */
16450 #define EPDC_PIGEON_1_0_EN_MASK                  0x1u
16451 #define EPDC_PIGEON_1_0_EN_SHIFT                 0
16452 #define EPDC_PIGEON_1_0_POL_MASK                 0x2u
16453 #define EPDC_PIGEON_1_0_POL_SHIFT                1
16454 #define EPDC_PIGEON_1_0_INC_SEL_MASK             0xCu
16455 #define EPDC_PIGEON_1_0_INC_SEL_SHIFT            2
16456 #define EPDC_PIGEON_1_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_INC_SEL_SHIFT))&EPDC_PIGEON_1_0_INC_SEL_MASK)
16457 #define EPDC_PIGEON_1_0_OFFSET_MASK              0xF0u
16458 #define EPDC_PIGEON_1_0_OFFSET_SHIFT             4
16459 #define EPDC_PIGEON_1_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_OFFSET_SHIFT))&EPDC_PIGEON_1_0_OFFSET_MASK)
16460 #define EPDC_PIGEON_1_0_MASK_CNT_SEL_MASK        0xF00u
16461 #define EPDC_PIGEON_1_0_MASK_CNT_SEL_SHIFT       8
16462 #define EPDC_PIGEON_1_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_1_0_MASK_CNT_SEL_MASK)
16463 #define EPDC_PIGEON_1_0_MASK_CNT_MASK            0xFFF000u
16464 #define EPDC_PIGEON_1_0_MASK_CNT_SHIFT           12
16465 #define EPDC_PIGEON_1_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_MASK_CNT_SHIFT))&EPDC_PIGEON_1_0_MASK_CNT_MASK)
16466 #define EPDC_PIGEON_1_0_STATE_MASK_MASK          0xFF000000u
16467 #define EPDC_PIGEON_1_0_STATE_MASK_SHIFT         24
16468 #define EPDC_PIGEON_1_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_STATE_MASK_SHIFT))&EPDC_PIGEON_1_0_STATE_MASK_MASK)
16469 /* PIGEON_1_1 Bit Fields */
16470 #define EPDC_PIGEON_1_1_SET_CNT_MASK             0xFFFFu
16471 #define EPDC_PIGEON_1_1_SET_CNT_SHIFT            0
16472 #define EPDC_PIGEON_1_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_1_SET_CNT_SHIFT))&EPDC_PIGEON_1_1_SET_CNT_MASK)
16473 #define EPDC_PIGEON_1_1_CLR_CNT_MASK             0xFFFF0000u
16474 #define EPDC_PIGEON_1_1_CLR_CNT_SHIFT            16
16475 #define EPDC_PIGEON_1_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_1_CLR_CNT_SHIFT))&EPDC_PIGEON_1_1_CLR_CNT_MASK)
16476 /* PIGEON_1_2 Bit Fields */
16477 #define EPDC_PIGEON_1_2_SIG_LOGIC_MASK           0xFu
16478 #define EPDC_PIGEON_1_2_SIG_LOGIC_SHIFT          0
16479 #define EPDC_PIGEON_1_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_1_2_SIG_LOGIC_MASK)
16480 #define EPDC_PIGEON_1_2_SIG_ANOTHER_MASK         0x1F0u
16481 #define EPDC_PIGEON_1_2_SIG_ANOTHER_SHIFT        4
16482 #define EPDC_PIGEON_1_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_1_2_SIG_ANOTHER_MASK)
16483 /* PIGEON_2_0 Bit Fields */
16484 #define EPDC_PIGEON_2_0_EN_MASK                  0x1u
16485 #define EPDC_PIGEON_2_0_EN_SHIFT                 0
16486 #define EPDC_PIGEON_2_0_POL_MASK                 0x2u
16487 #define EPDC_PIGEON_2_0_POL_SHIFT                1
16488 #define EPDC_PIGEON_2_0_INC_SEL_MASK             0xCu
16489 #define EPDC_PIGEON_2_0_INC_SEL_SHIFT            2
16490 #define EPDC_PIGEON_2_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_INC_SEL_SHIFT))&EPDC_PIGEON_2_0_INC_SEL_MASK)
16491 #define EPDC_PIGEON_2_0_OFFSET_MASK              0xF0u
16492 #define EPDC_PIGEON_2_0_OFFSET_SHIFT             4
16493 #define EPDC_PIGEON_2_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_OFFSET_SHIFT))&EPDC_PIGEON_2_0_OFFSET_MASK)
16494 #define EPDC_PIGEON_2_0_MASK_CNT_SEL_MASK        0xF00u
16495 #define EPDC_PIGEON_2_0_MASK_CNT_SEL_SHIFT       8
16496 #define EPDC_PIGEON_2_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_2_0_MASK_CNT_SEL_MASK)
16497 #define EPDC_PIGEON_2_0_MASK_CNT_MASK            0xFFF000u
16498 #define EPDC_PIGEON_2_0_MASK_CNT_SHIFT           12
16499 #define EPDC_PIGEON_2_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_MASK_CNT_SHIFT))&EPDC_PIGEON_2_0_MASK_CNT_MASK)
16500 #define EPDC_PIGEON_2_0_STATE_MASK_MASK          0xFF000000u
16501 #define EPDC_PIGEON_2_0_STATE_MASK_SHIFT         24
16502 #define EPDC_PIGEON_2_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_STATE_MASK_SHIFT))&EPDC_PIGEON_2_0_STATE_MASK_MASK)
16503 /* PIGEON_2_1 Bit Fields */
16504 #define EPDC_PIGEON_2_1_SET_CNT_MASK             0xFFFFu
16505 #define EPDC_PIGEON_2_1_SET_CNT_SHIFT            0
16506 #define EPDC_PIGEON_2_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_1_SET_CNT_SHIFT))&EPDC_PIGEON_2_1_SET_CNT_MASK)
16507 #define EPDC_PIGEON_2_1_CLR_CNT_MASK             0xFFFF0000u
16508 #define EPDC_PIGEON_2_1_CLR_CNT_SHIFT            16
16509 #define EPDC_PIGEON_2_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_1_CLR_CNT_SHIFT))&EPDC_PIGEON_2_1_CLR_CNT_MASK)
16510 /* PIGEON_2_2 Bit Fields */
16511 #define EPDC_PIGEON_2_2_SIG_LOGIC_MASK           0xFu
16512 #define EPDC_PIGEON_2_2_SIG_LOGIC_SHIFT          0
16513 #define EPDC_PIGEON_2_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_2_2_SIG_LOGIC_MASK)
16514 #define EPDC_PIGEON_2_2_SIG_ANOTHER_MASK         0x1F0u
16515 #define EPDC_PIGEON_2_2_SIG_ANOTHER_SHIFT        4
16516 #define EPDC_PIGEON_2_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_2_2_SIG_ANOTHER_MASK)
16517 /* PIGEON_3_0 Bit Fields */
16518 #define EPDC_PIGEON_3_0_EN_MASK                  0x1u
16519 #define EPDC_PIGEON_3_0_EN_SHIFT                 0
16520 #define EPDC_PIGEON_3_0_POL_MASK                 0x2u
16521 #define EPDC_PIGEON_3_0_POL_SHIFT                1
16522 #define EPDC_PIGEON_3_0_INC_SEL_MASK             0xCu
16523 #define EPDC_PIGEON_3_0_INC_SEL_SHIFT            2
16524 #define EPDC_PIGEON_3_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_INC_SEL_SHIFT))&EPDC_PIGEON_3_0_INC_SEL_MASK)
16525 #define EPDC_PIGEON_3_0_OFFSET_MASK              0xF0u
16526 #define EPDC_PIGEON_3_0_OFFSET_SHIFT             4
16527 #define EPDC_PIGEON_3_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_OFFSET_SHIFT))&EPDC_PIGEON_3_0_OFFSET_MASK)
16528 #define EPDC_PIGEON_3_0_MASK_CNT_SEL_MASK        0xF00u
16529 #define EPDC_PIGEON_3_0_MASK_CNT_SEL_SHIFT       8
16530 #define EPDC_PIGEON_3_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_3_0_MASK_CNT_SEL_MASK)
16531 #define EPDC_PIGEON_3_0_MASK_CNT_MASK            0xFFF000u
16532 #define EPDC_PIGEON_3_0_MASK_CNT_SHIFT           12
16533 #define EPDC_PIGEON_3_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_MASK_CNT_SHIFT))&EPDC_PIGEON_3_0_MASK_CNT_MASK)
16534 #define EPDC_PIGEON_3_0_STATE_MASK_MASK          0xFF000000u
16535 #define EPDC_PIGEON_3_0_STATE_MASK_SHIFT         24
16536 #define EPDC_PIGEON_3_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_STATE_MASK_SHIFT))&EPDC_PIGEON_3_0_STATE_MASK_MASK)
16537 /* PIGEON_3_1 Bit Fields */
16538 #define EPDC_PIGEON_3_1_SET_CNT_MASK             0xFFFFu
16539 #define EPDC_PIGEON_3_1_SET_CNT_SHIFT            0
16540 #define EPDC_PIGEON_3_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_1_SET_CNT_SHIFT))&EPDC_PIGEON_3_1_SET_CNT_MASK)
16541 #define EPDC_PIGEON_3_1_CLR_CNT_MASK             0xFFFF0000u
16542 #define EPDC_PIGEON_3_1_CLR_CNT_SHIFT            16
16543 #define EPDC_PIGEON_3_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_1_CLR_CNT_SHIFT))&EPDC_PIGEON_3_1_CLR_CNT_MASK)
16544 /* PIGEON_3_2 Bit Fields */
16545 #define EPDC_PIGEON_3_2_SIG_LOGIC_MASK           0xFu
16546 #define EPDC_PIGEON_3_2_SIG_LOGIC_SHIFT          0
16547 #define EPDC_PIGEON_3_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_3_2_SIG_LOGIC_MASK)
16548 #define EPDC_PIGEON_3_2_SIG_ANOTHER_MASK         0x1F0u
16549 #define EPDC_PIGEON_3_2_SIG_ANOTHER_SHIFT        4
16550 #define EPDC_PIGEON_3_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_3_2_SIG_ANOTHER_MASK)
16551 /* PIGEON_4_0 Bit Fields */
16552 #define EPDC_PIGEON_4_0_EN_MASK                  0x1u
16553 #define EPDC_PIGEON_4_0_EN_SHIFT                 0
16554 #define EPDC_PIGEON_4_0_POL_MASK                 0x2u
16555 #define EPDC_PIGEON_4_0_POL_SHIFT                1
16556 #define EPDC_PIGEON_4_0_INC_SEL_MASK             0xCu
16557 #define EPDC_PIGEON_4_0_INC_SEL_SHIFT            2
16558 #define EPDC_PIGEON_4_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_INC_SEL_SHIFT))&EPDC_PIGEON_4_0_INC_SEL_MASK)
16559 #define EPDC_PIGEON_4_0_OFFSET_MASK              0xF0u
16560 #define EPDC_PIGEON_4_0_OFFSET_SHIFT             4
16561 #define EPDC_PIGEON_4_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_OFFSET_SHIFT))&EPDC_PIGEON_4_0_OFFSET_MASK)
16562 #define EPDC_PIGEON_4_0_MASK_CNT_SEL_MASK        0xF00u
16563 #define EPDC_PIGEON_4_0_MASK_CNT_SEL_SHIFT       8
16564 #define EPDC_PIGEON_4_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_4_0_MASK_CNT_SEL_MASK)
16565 #define EPDC_PIGEON_4_0_MASK_CNT_MASK            0xFFF000u
16566 #define EPDC_PIGEON_4_0_MASK_CNT_SHIFT           12
16567 #define EPDC_PIGEON_4_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_MASK_CNT_SHIFT))&EPDC_PIGEON_4_0_MASK_CNT_MASK)
16568 #define EPDC_PIGEON_4_0_STATE_MASK_MASK          0xFF000000u
16569 #define EPDC_PIGEON_4_0_STATE_MASK_SHIFT         24
16570 #define EPDC_PIGEON_4_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_STATE_MASK_SHIFT))&EPDC_PIGEON_4_0_STATE_MASK_MASK)
16571 /* PIGEON_4_1 Bit Fields */
16572 #define EPDC_PIGEON_4_1_SET_CNT_MASK             0xFFFFu
16573 #define EPDC_PIGEON_4_1_SET_CNT_SHIFT            0
16574 #define EPDC_PIGEON_4_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_1_SET_CNT_SHIFT))&EPDC_PIGEON_4_1_SET_CNT_MASK)
16575 #define EPDC_PIGEON_4_1_CLR_CNT_MASK             0xFFFF0000u
16576 #define EPDC_PIGEON_4_1_CLR_CNT_SHIFT            16
16577 #define EPDC_PIGEON_4_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_1_CLR_CNT_SHIFT))&EPDC_PIGEON_4_1_CLR_CNT_MASK)
16578 /* PIGEON_4_2 Bit Fields */
16579 #define EPDC_PIGEON_4_2_SIG_LOGIC_MASK           0xFu
16580 #define EPDC_PIGEON_4_2_SIG_LOGIC_SHIFT          0
16581 #define EPDC_PIGEON_4_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_4_2_SIG_LOGIC_MASK)
16582 #define EPDC_PIGEON_4_2_SIG_ANOTHER_MASK         0x1F0u
16583 #define EPDC_PIGEON_4_2_SIG_ANOTHER_SHIFT        4
16584 #define EPDC_PIGEON_4_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_4_2_SIG_ANOTHER_MASK)
16585 /* PIGEON_5_0 Bit Fields */
16586 #define EPDC_PIGEON_5_0_EN_MASK                  0x1u
16587 #define EPDC_PIGEON_5_0_EN_SHIFT                 0
16588 #define EPDC_PIGEON_5_0_POL_MASK                 0x2u
16589 #define EPDC_PIGEON_5_0_POL_SHIFT                1
16590 #define EPDC_PIGEON_5_0_INC_SEL_MASK             0xCu
16591 #define EPDC_PIGEON_5_0_INC_SEL_SHIFT            2
16592 #define EPDC_PIGEON_5_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_INC_SEL_SHIFT))&EPDC_PIGEON_5_0_INC_SEL_MASK)
16593 #define EPDC_PIGEON_5_0_OFFSET_MASK              0xF0u
16594 #define EPDC_PIGEON_5_0_OFFSET_SHIFT             4
16595 #define EPDC_PIGEON_5_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_OFFSET_SHIFT))&EPDC_PIGEON_5_0_OFFSET_MASK)
16596 #define EPDC_PIGEON_5_0_MASK_CNT_SEL_MASK        0xF00u
16597 #define EPDC_PIGEON_5_0_MASK_CNT_SEL_SHIFT       8
16598 #define EPDC_PIGEON_5_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_5_0_MASK_CNT_SEL_MASK)
16599 #define EPDC_PIGEON_5_0_MASK_CNT_MASK            0xFFF000u
16600 #define EPDC_PIGEON_5_0_MASK_CNT_SHIFT           12
16601 #define EPDC_PIGEON_5_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_MASK_CNT_SHIFT))&EPDC_PIGEON_5_0_MASK_CNT_MASK)
16602 #define EPDC_PIGEON_5_0_STATE_MASK_MASK          0xFF000000u
16603 #define EPDC_PIGEON_5_0_STATE_MASK_SHIFT         24
16604 #define EPDC_PIGEON_5_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_STATE_MASK_SHIFT))&EPDC_PIGEON_5_0_STATE_MASK_MASK)
16605 /* PIGEON_5_1 Bit Fields */
16606 #define EPDC_PIGEON_5_1_SET_CNT_MASK             0xFFFFu
16607 #define EPDC_PIGEON_5_1_SET_CNT_SHIFT            0
16608 #define EPDC_PIGEON_5_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_1_SET_CNT_SHIFT))&EPDC_PIGEON_5_1_SET_CNT_MASK)
16609 #define EPDC_PIGEON_5_1_CLR_CNT_MASK             0xFFFF0000u
16610 #define EPDC_PIGEON_5_1_CLR_CNT_SHIFT            16
16611 #define EPDC_PIGEON_5_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_1_CLR_CNT_SHIFT))&EPDC_PIGEON_5_1_CLR_CNT_MASK)
16612 /* PIGEON_5_2 Bit Fields */
16613 #define EPDC_PIGEON_5_2_SIG_LOGIC_MASK           0xFu
16614 #define EPDC_PIGEON_5_2_SIG_LOGIC_SHIFT          0
16615 #define EPDC_PIGEON_5_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_5_2_SIG_LOGIC_MASK)
16616 #define EPDC_PIGEON_5_2_SIG_ANOTHER_MASK         0x1F0u
16617 #define EPDC_PIGEON_5_2_SIG_ANOTHER_SHIFT        4
16618 #define EPDC_PIGEON_5_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_5_2_SIG_ANOTHER_MASK)
16619 /* PIGEON_6_0 Bit Fields */
16620 #define EPDC_PIGEON_6_0_EN_MASK                  0x1u
16621 #define EPDC_PIGEON_6_0_EN_SHIFT                 0
16622 #define EPDC_PIGEON_6_0_POL_MASK                 0x2u
16623 #define EPDC_PIGEON_6_0_POL_SHIFT                1
16624 #define EPDC_PIGEON_6_0_INC_SEL_MASK             0xCu
16625 #define EPDC_PIGEON_6_0_INC_SEL_SHIFT            2
16626 #define EPDC_PIGEON_6_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_INC_SEL_SHIFT))&EPDC_PIGEON_6_0_INC_SEL_MASK)
16627 #define EPDC_PIGEON_6_0_OFFSET_MASK              0xF0u
16628 #define EPDC_PIGEON_6_0_OFFSET_SHIFT             4
16629 #define EPDC_PIGEON_6_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_OFFSET_SHIFT))&EPDC_PIGEON_6_0_OFFSET_MASK)
16630 #define EPDC_PIGEON_6_0_MASK_CNT_SEL_MASK        0xF00u
16631 #define EPDC_PIGEON_6_0_MASK_CNT_SEL_SHIFT       8
16632 #define EPDC_PIGEON_6_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_6_0_MASK_CNT_SEL_MASK)
16633 #define EPDC_PIGEON_6_0_MASK_CNT_MASK            0xFFF000u
16634 #define EPDC_PIGEON_6_0_MASK_CNT_SHIFT           12
16635 #define EPDC_PIGEON_6_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_MASK_CNT_SHIFT))&EPDC_PIGEON_6_0_MASK_CNT_MASK)
16636 #define EPDC_PIGEON_6_0_STATE_MASK_MASK          0xFF000000u
16637 #define EPDC_PIGEON_6_0_STATE_MASK_SHIFT         24
16638 #define EPDC_PIGEON_6_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_STATE_MASK_SHIFT))&EPDC_PIGEON_6_0_STATE_MASK_MASK)
16639 /* PIGEON_6_1 Bit Fields */
16640 #define EPDC_PIGEON_6_1_SET_CNT_MASK             0xFFFFu
16641 #define EPDC_PIGEON_6_1_SET_CNT_SHIFT            0
16642 #define EPDC_PIGEON_6_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_1_SET_CNT_SHIFT))&EPDC_PIGEON_6_1_SET_CNT_MASK)
16643 #define EPDC_PIGEON_6_1_CLR_CNT_MASK             0xFFFF0000u
16644 #define EPDC_PIGEON_6_1_CLR_CNT_SHIFT            16
16645 #define EPDC_PIGEON_6_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_1_CLR_CNT_SHIFT))&EPDC_PIGEON_6_1_CLR_CNT_MASK)
16646 /* PIGEON_6_2 Bit Fields */
16647 #define EPDC_PIGEON_6_2_SIG_LOGIC_MASK           0xFu
16648 #define EPDC_PIGEON_6_2_SIG_LOGIC_SHIFT          0
16649 #define EPDC_PIGEON_6_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_6_2_SIG_LOGIC_MASK)
16650 #define EPDC_PIGEON_6_2_SIG_ANOTHER_MASK         0x1F0u
16651 #define EPDC_PIGEON_6_2_SIG_ANOTHER_SHIFT        4
16652 #define EPDC_PIGEON_6_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_6_2_SIG_ANOTHER_MASK)
16653 /* PIGEON_7_0 Bit Fields */
16654 #define EPDC_PIGEON_7_0_EN_MASK                  0x1u
16655 #define EPDC_PIGEON_7_0_EN_SHIFT                 0
16656 #define EPDC_PIGEON_7_0_POL_MASK                 0x2u
16657 #define EPDC_PIGEON_7_0_POL_SHIFT                1
16658 #define EPDC_PIGEON_7_0_INC_SEL_MASK             0xCu
16659 #define EPDC_PIGEON_7_0_INC_SEL_SHIFT            2
16660 #define EPDC_PIGEON_7_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_INC_SEL_SHIFT))&EPDC_PIGEON_7_0_INC_SEL_MASK)
16661 #define EPDC_PIGEON_7_0_OFFSET_MASK              0xF0u
16662 #define EPDC_PIGEON_7_0_OFFSET_SHIFT             4
16663 #define EPDC_PIGEON_7_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_OFFSET_SHIFT))&EPDC_PIGEON_7_0_OFFSET_MASK)
16664 #define EPDC_PIGEON_7_0_MASK_CNT_SEL_MASK        0xF00u
16665 #define EPDC_PIGEON_7_0_MASK_CNT_SEL_SHIFT       8
16666 #define EPDC_PIGEON_7_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_7_0_MASK_CNT_SEL_MASK)
16667 #define EPDC_PIGEON_7_0_MASK_CNT_MASK            0xFFF000u
16668 #define EPDC_PIGEON_7_0_MASK_CNT_SHIFT           12
16669 #define EPDC_PIGEON_7_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_MASK_CNT_SHIFT))&EPDC_PIGEON_7_0_MASK_CNT_MASK)
16670 #define EPDC_PIGEON_7_0_STATE_MASK_MASK          0xFF000000u
16671 #define EPDC_PIGEON_7_0_STATE_MASK_SHIFT         24
16672 #define EPDC_PIGEON_7_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_STATE_MASK_SHIFT))&EPDC_PIGEON_7_0_STATE_MASK_MASK)
16673 /* PIGEON_7_1 Bit Fields */
16674 #define EPDC_PIGEON_7_1_SET_CNT_MASK             0xFFFFu
16675 #define EPDC_PIGEON_7_1_SET_CNT_SHIFT            0
16676 #define EPDC_PIGEON_7_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_1_SET_CNT_SHIFT))&EPDC_PIGEON_7_1_SET_CNT_MASK)
16677 #define EPDC_PIGEON_7_1_CLR_CNT_MASK             0xFFFF0000u
16678 #define EPDC_PIGEON_7_1_CLR_CNT_SHIFT            16
16679 #define EPDC_PIGEON_7_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_1_CLR_CNT_SHIFT))&EPDC_PIGEON_7_1_CLR_CNT_MASK)
16680 /* PIGEON_7_2 Bit Fields */
16681 #define EPDC_PIGEON_7_2_SIG_LOGIC_MASK           0xFu
16682 #define EPDC_PIGEON_7_2_SIG_LOGIC_SHIFT          0
16683 #define EPDC_PIGEON_7_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_7_2_SIG_LOGIC_MASK)
16684 #define EPDC_PIGEON_7_2_SIG_ANOTHER_MASK         0x1F0u
16685 #define EPDC_PIGEON_7_2_SIG_ANOTHER_SHIFT        4
16686 #define EPDC_PIGEON_7_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_7_2_SIG_ANOTHER_MASK)
16687 /* PIGEON_8_0 Bit Fields */
16688 #define EPDC_PIGEON_8_0_EN_MASK                  0x1u
16689 #define EPDC_PIGEON_8_0_EN_SHIFT                 0
16690 #define EPDC_PIGEON_8_0_POL_MASK                 0x2u
16691 #define EPDC_PIGEON_8_0_POL_SHIFT                1
16692 #define EPDC_PIGEON_8_0_INC_SEL_MASK             0xCu
16693 #define EPDC_PIGEON_8_0_INC_SEL_SHIFT            2
16694 #define EPDC_PIGEON_8_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_INC_SEL_SHIFT))&EPDC_PIGEON_8_0_INC_SEL_MASK)
16695 #define EPDC_PIGEON_8_0_OFFSET_MASK              0xF0u
16696 #define EPDC_PIGEON_8_0_OFFSET_SHIFT             4
16697 #define EPDC_PIGEON_8_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_OFFSET_SHIFT))&EPDC_PIGEON_8_0_OFFSET_MASK)
16698 #define EPDC_PIGEON_8_0_MASK_CNT_SEL_MASK        0xF00u
16699 #define EPDC_PIGEON_8_0_MASK_CNT_SEL_SHIFT       8
16700 #define EPDC_PIGEON_8_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_8_0_MASK_CNT_SEL_MASK)
16701 #define EPDC_PIGEON_8_0_MASK_CNT_MASK            0xFFF000u
16702 #define EPDC_PIGEON_8_0_MASK_CNT_SHIFT           12
16703 #define EPDC_PIGEON_8_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_MASK_CNT_SHIFT))&EPDC_PIGEON_8_0_MASK_CNT_MASK)
16704 #define EPDC_PIGEON_8_0_STATE_MASK_MASK          0xFF000000u
16705 #define EPDC_PIGEON_8_0_STATE_MASK_SHIFT         24
16706 #define EPDC_PIGEON_8_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_STATE_MASK_SHIFT))&EPDC_PIGEON_8_0_STATE_MASK_MASK)
16707 /* PIGEON_8_1 Bit Fields */
16708 #define EPDC_PIGEON_8_1_SET_CNT_MASK             0xFFFFu
16709 #define EPDC_PIGEON_8_1_SET_CNT_SHIFT            0
16710 #define EPDC_PIGEON_8_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_1_SET_CNT_SHIFT))&EPDC_PIGEON_8_1_SET_CNT_MASK)
16711 #define EPDC_PIGEON_8_1_CLR_CNT_MASK             0xFFFF0000u
16712 #define EPDC_PIGEON_8_1_CLR_CNT_SHIFT            16
16713 #define EPDC_PIGEON_8_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_1_CLR_CNT_SHIFT))&EPDC_PIGEON_8_1_CLR_CNT_MASK)
16714 /* PIGEON_8_2 Bit Fields */
16715 #define EPDC_PIGEON_8_2_SIG_LOGIC_MASK           0xFu
16716 #define EPDC_PIGEON_8_2_SIG_LOGIC_SHIFT          0
16717 #define EPDC_PIGEON_8_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_8_2_SIG_LOGIC_MASK)
16718 #define EPDC_PIGEON_8_2_SIG_ANOTHER_MASK         0x1F0u
16719 #define EPDC_PIGEON_8_2_SIG_ANOTHER_SHIFT        4
16720 #define EPDC_PIGEON_8_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_8_2_SIG_ANOTHER_MASK)
16721 /* PIGEON_9_0 Bit Fields */
16722 #define EPDC_PIGEON_9_0_EN_MASK                  0x1u
16723 #define EPDC_PIGEON_9_0_EN_SHIFT                 0
16724 #define EPDC_PIGEON_9_0_POL_MASK                 0x2u
16725 #define EPDC_PIGEON_9_0_POL_SHIFT                1
16726 #define EPDC_PIGEON_9_0_INC_SEL_MASK             0xCu
16727 #define EPDC_PIGEON_9_0_INC_SEL_SHIFT            2
16728 #define EPDC_PIGEON_9_0_INC_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_INC_SEL_SHIFT))&EPDC_PIGEON_9_0_INC_SEL_MASK)
16729 #define EPDC_PIGEON_9_0_OFFSET_MASK              0xF0u
16730 #define EPDC_PIGEON_9_0_OFFSET_SHIFT             4
16731 #define EPDC_PIGEON_9_0_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_OFFSET_SHIFT))&EPDC_PIGEON_9_0_OFFSET_MASK)
16732 #define EPDC_PIGEON_9_0_MASK_CNT_SEL_MASK        0xF00u
16733 #define EPDC_PIGEON_9_0_MASK_CNT_SEL_SHIFT       8
16734 #define EPDC_PIGEON_9_0_MASK_CNT_SEL(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_9_0_MASK_CNT_SEL_MASK)
16735 #define EPDC_PIGEON_9_0_MASK_CNT_MASK            0xFFF000u
16736 #define EPDC_PIGEON_9_0_MASK_CNT_SHIFT           12
16737 #define EPDC_PIGEON_9_0_MASK_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_MASK_CNT_SHIFT))&EPDC_PIGEON_9_0_MASK_CNT_MASK)
16738 #define EPDC_PIGEON_9_0_STATE_MASK_MASK          0xFF000000u
16739 #define EPDC_PIGEON_9_0_STATE_MASK_SHIFT         24
16740 #define EPDC_PIGEON_9_0_STATE_MASK(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_STATE_MASK_SHIFT))&EPDC_PIGEON_9_0_STATE_MASK_MASK)
16741 /* PIGEON_9_1 Bit Fields */
16742 #define EPDC_PIGEON_9_1_SET_CNT_MASK             0xFFFFu
16743 #define EPDC_PIGEON_9_1_SET_CNT_SHIFT            0
16744 #define EPDC_PIGEON_9_1_SET_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_1_SET_CNT_SHIFT))&EPDC_PIGEON_9_1_SET_CNT_MASK)
16745 #define EPDC_PIGEON_9_1_CLR_CNT_MASK             0xFFFF0000u
16746 #define EPDC_PIGEON_9_1_CLR_CNT_SHIFT            16
16747 #define EPDC_PIGEON_9_1_CLR_CNT(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_1_CLR_CNT_SHIFT))&EPDC_PIGEON_9_1_CLR_CNT_MASK)
16748 /* PIGEON_9_2 Bit Fields */
16749 #define EPDC_PIGEON_9_2_SIG_LOGIC_MASK           0xFu
16750 #define EPDC_PIGEON_9_2_SIG_LOGIC_SHIFT          0
16751 #define EPDC_PIGEON_9_2_SIG_LOGIC(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_9_2_SIG_LOGIC_MASK)
16752 #define EPDC_PIGEON_9_2_SIG_ANOTHER_MASK         0x1F0u
16753 #define EPDC_PIGEON_9_2_SIG_ANOTHER_SHIFT        4
16754 #define EPDC_PIGEON_9_2_SIG_ANOTHER(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_9_2_SIG_ANOTHER_MASK)
16755 /* PIGEON_10_0 Bit Fields */
16756 #define EPDC_PIGEON_10_0_EN_MASK                 0x1u
16757 #define EPDC_PIGEON_10_0_EN_SHIFT                0
16758 #define EPDC_PIGEON_10_0_POL_MASK                0x2u
16759 #define EPDC_PIGEON_10_0_POL_SHIFT               1
16760 #define EPDC_PIGEON_10_0_INC_SEL_MASK            0xCu
16761 #define EPDC_PIGEON_10_0_INC_SEL_SHIFT           2
16762 #define EPDC_PIGEON_10_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_INC_SEL_SHIFT))&EPDC_PIGEON_10_0_INC_SEL_MASK)
16763 #define EPDC_PIGEON_10_0_OFFSET_MASK             0xF0u
16764 #define EPDC_PIGEON_10_0_OFFSET_SHIFT            4
16765 #define EPDC_PIGEON_10_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_OFFSET_SHIFT))&EPDC_PIGEON_10_0_OFFSET_MASK)
16766 #define EPDC_PIGEON_10_0_MASK_CNT_SEL_MASK       0xF00u
16767 #define EPDC_PIGEON_10_0_MASK_CNT_SEL_SHIFT      8
16768 #define EPDC_PIGEON_10_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_10_0_MASK_CNT_SEL_MASK)
16769 #define EPDC_PIGEON_10_0_MASK_CNT_MASK           0xFFF000u
16770 #define EPDC_PIGEON_10_0_MASK_CNT_SHIFT          12
16771 #define EPDC_PIGEON_10_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_MASK_CNT_SHIFT))&EPDC_PIGEON_10_0_MASK_CNT_MASK)
16772 #define EPDC_PIGEON_10_0_STATE_MASK_MASK         0xFF000000u
16773 #define EPDC_PIGEON_10_0_STATE_MASK_SHIFT        24
16774 #define EPDC_PIGEON_10_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_STATE_MASK_SHIFT))&EPDC_PIGEON_10_0_STATE_MASK_MASK)
16775 /* PIGEON_10_1 Bit Fields */
16776 #define EPDC_PIGEON_10_1_SET_CNT_MASK            0xFFFFu
16777 #define EPDC_PIGEON_10_1_SET_CNT_SHIFT           0
16778 #define EPDC_PIGEON_10_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_1_SET_CNT_SHIFT))&EPDC_PIGEON_10_1_SET_CNT_MASK)
16779 #define EPDC_PIGEON_10_1_CLR_CNT_MASK            0xFFFF0000u
16780 #define EPDC_PIGEON_10_1_CLR_CNT_SHIFT           16
16781 #define EPDC_PIGEON_10_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_1_CLR_CNT_SHIFT))&EPDC_PIGEON_10_1_CLR_CNT_MASK)
16782 /* PIGEON_10_2 Bit Fields */
16783 #define EPDC_PIGEON_10_2_SIG_LOGIC_MASK          0xFu
16784 #define EPDC_PIGEON_10_2_SIG_LOGIC_SHIFT         0
16785 #define EPDC_PIGEON_10_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_10_2_SIG_LOGIC_MASK)
16786 #define EPDC_PIGEON_10_2_SIG_ANOTHER_MASK        0x1F0u
16787 #define EPDC_PIGEON_10_2_SIG_ANOTHER_SHIFT       4
16788 #define EPDC_PIGEON_10_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_10_2_SIG_ANOTHER_MASK)
16789 /* PIGEON_11_0 Bit Fields */
16790 #define EPDC_PIGEON_11_0_EN_MASK                 0x1u
16791 #define EPDC_PIGEON_11_0_EN_SHIFT                0
16792 #define EPDC_PIGEON_11_0_POL_MASK                0x2u
16793 #define EPDC_PIGEON_11_0_POL_SHIFT               1
16794 #define EPDC_PIGEON_11_0_INC_SEL_MASK            0xCu
16795 #define EPDC_PIGEON_11_0_INC_SEL_SHIFT           2
16796 #define EPDC_PIGEON_11_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_INC_SEL_SHIFT))&EPDC_PIGEON_11_0_INC_SEL_MASK)
16797 #define EPDC_PIGEON_11_0_OFFSET_MASK             0xF0u
16798 #define EPDC_PIGEON_11_0_OFFSET_SHIFT            4
16799 #define EPDC_PIGEON_11_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_OFFSET_SHIFT))&EPDC_PIGEON_11_0_OFFSET_MASK)
16800 #define EPDC_PIGEON_11_0_MASK_CNT_SEL_MASK       0xF00u
16801 #define EPDC_PIGEON_11_0_MASK_CNT_SEL_SHIFT      8
16802 #define EPDC_PIGEON_11_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_11_0_MASK_CNT_SEL_MASK)
16803 #define EPDC_PIGEON_11_0_MASK_CNT_MASK           0xFFF000u
16804 #define EPDC_PIGEON_11_0_MASK_CNT_SHIFT          12
16805 #define EPDC_PIGEON_11_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_MASK_CNT_SHIFT))&EPDC_PIGEON_11_0_MASK_CNT_MASK)
16806 #define EPDC_PIGEON_11_0_STATE_MASK_MASK         0xFF000000u
16807 #define EPDC_PIGEON_11_0_STATE_MASK_SHIFT        24
16808 #define EPDC_PIGEON_11_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_STATE_MASK_SHIFT))&EPDC_PIGEON_11_0_STATE_MASK_MASK)
16809 /* PIGEON_11_1 Bit Fields */
16810 #define EPDC_PIGEON_11_1_SET_CNT_MASK            0xFFFFu
16811 #define EPDC_PIGEON_11_1_SET_CNT_SHIFT           0
16812 #define EPDC_PIGEON_11_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_1_SET_CNT_SHIFT))&EPDC_PIGEON_11_1_SET_CNT_MASK)
16813 #define EPDC_PIGEON_11_1_CLR_CNT_MASK            0xFFFF0000u
16814 #define EPDC_PIGEON_11_1_CLR_CNT_SHIFT           16
16815 #define EPDC_PIGEON_11_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_1_CLR_CNT_SHIFT))&EPDC_PIGEON_11_1_CLR_CNT_MASK)
16816 /* PIGEON_11_2 Bit Fields */
16817 #define EPDC_PIGEON_11_2_SIG_LOGIC_MASK          0xFu
16818 #define EPDC_PIGEON_11_2_SIG_LOGIC_SHIFT         0
16819 #define EPDC_PIGEON_11_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_11_2_SIG_LOGIC_MASK)
16820 #define EPDC_PIGEON_11_2_SIG_ANOTHER_MASK        0x1F0u
16821 #define EPDC_PIGEON_11_2_SIG_ANOTHER_SHIFT       4
16822 #define EPDC_PIGEON_11_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_11_2_SIG_ANOTHER_MASK)
16823 /* PIGEON_12_0 Bit Fields */
16824 #define EPDC_PIGEON_12_0_EN_MASK                 0x1u
16825 #define EPDC_PIGEON_12_0_EN_SHIFT                0
16826 #define EPDC_PIGEON_12_0_POL_MASK                0x2u
16827 #define EPDC_PIGEON_12_0_POL_SHIFT               1
16828 #define EPDC_PIGEON_12_0_INC_SEL_MASK            0xCu
16829 #define EPDC_PIGEON_12_0_INC_SEL_SHIFT           2
16830 #define EPDC_PIGEON_12_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_INC_SEL_SHIFT))&EPDC_PIGEON_12_0_INC_SEL_MASK)
16831 #define EPDC_PIGEON_12_0_OFFSET_MASK             0xF0u
16832 #define EPDC_PIGEON_12_0_OFFSET_SHIFT            4
16833 #define EPDC_PIGEON_12_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_OFFSET_SHIFT))&EPDC_PIGEON_12_0_OFFSET_MASK)
16834 #define EPDC_PIGEON_12_0_MASK_CNT_SEL_MASK       0xF00u
16835 #define EPDC_PIGEON_12_0_MASK_CNT_SEL_SHIFT      8
16836 #define EPDC_PIGEON_12_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_12_0_MASK_CNT_SEL_MASK)
16837 #define EPDC_PIGEON_12_0_MASK_CNT_MASK           0xFFF000u
16838 #define EPDC_PIGEON_12_0_MASK_CNT_SHIFT          12
16839 #define EPDC_PIGEON_12_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_MASK_CNT_SHIFT))&EPDC_PIGEON_12_0_MASK_CNT_MASK)
16840 #define EPDC_PIGEON_12_0_STATE_MASK_MASK         0xFF000000u
16841 #define EPDC_PIGEON_12_0_STATE_MASK_SHIFT        24
16842 #define EPDC_PIGEON_12_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_STATE_MASK_SHIFT))&EPDC_PIGEON_12_0_STATE_MASK_MASK)
16843 /* PIGEON_12_1 Bit Fields */
16844 #define EPDC_PIGEON_12_1_SET_CNT_MASK            0xFFFFu
16845 #define EPDC_PIGEON_12_1_SET_CNT_SHIFT           0
16846 #define EPDC_PIGEON_12_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_1_SET_CNT_SHIFT))&EPDC_PIGEON_12_1_SET_CNT_MASK)
16847 #define EPDC_PIGEON_12_1_CLR_CNT_MASK            0xFFFF0000u
16848 #define EPDC_PIGEON_12_1_CLR_CNT_SHIFT           16
16849 #define EPDC_PIGEON_12_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_1_CLR_CNT_SHIFT))&EPDC_PIGEON_12_1_CLR_CNT_MASK)
16850 /* PIGEON_12_2 Bit Fields */
16851 #define EPDC_PIGEON_12_2_SIG_LOGIC_MASK          0xFu
16852 #define EPDC_PIGEON_12_2_SIG_LOGIC_SHIFT         0
16853 #define EPDC_PIGEON_12_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_12_2_SIG_LOGIC_MASK)
16854 #define EPDC_PIGEON_12_2_SIG_ANOTHER_MASK        0x1F0u
16855 #define EPDC_PIGEON_12_2_SIG_ANOTHER_SHIFT       4
16856 #define EPDC_PIGEON_12_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_12_2_SIG_ANOTHER_MASK)
16857 /* PIGEON_13_0 Bit Fields */
16858 #define EPDC_PIGEON_13_0_EN_MASK                 0x1u
16859 #define EPDC_PIGEON_13_0_EN_SHIFT                0
16860 #define EPDC_PIGEON_13_0_POL_MASK                0x2u
16861 #define EPDC_PIGEON_13_0_POL_SHIFT               1
16862 #define EPDC_PIGEON_13_0_INC_SEL_MASK            0xCu
16863 #define EPDC_PIGEON_13_0_INC_SEL_SHIFT           2
16864 #define EPDC_PIGEON_13_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_INC_SEL_SHIFT))&EPDC_PIGEON_13_0_INC_SEL_MASK)
16865 #define EPDC_PIGEON_13_0_OFFSET_MASK             0xF0u
16866 #define EPDC_PIGEON_13_0_OFFSET_SHIFT            4
16867 #define EPDC_PIGEON_13_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_OFFSET_SHIFT))&EPDC_PIGEON_13_0_OFFSET_MASK)
16868 #define EPDC_PIGEON_13_0_MASK_CNT_SEL_MASK       0xF00u
16869 #define EPDC_PIGEON_13_0_MASK_CNT_SEL_SHIFT      8
16870 #define EPDC_PIGEON_13_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_13_0_MASK_CNT_SEL_MASK)
16871 #define EPDC_PIGEON_13_0_MASK_CNT_MASK           0xFFF000u
16872 #define EPDC_PIGEON_13_0_MASK_CNT_SHIFT          12
16873 #define EPDC_PIGEON_13_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_MASK_CNT_SHIFT))&EPDC_PIGEON_13_0_MASK_CNT_MASK)
16874 #define EPDC_PIGEON_13_0_STATE_MASK_MASK         0xFF000000u
16875 #define EPDC_PIGEON_13_0_STATE_MASK_SHIFT        24
16876 #define EPDC_PIGEON_13_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_STATE_MASK_SHIFT))&EPDC_PIGEON_13_0_STATE_MASK_MASK)
16877 /* PIGEON_13_1 Bit Fields */
16878 #define EPDC_PIGEON_13_1_SET_CNT_MASK            0xFFFFu
16879 #define EPDC_PIGEON_13_1_SET_CNT_SHIFT           0
16880 #define EPDC_PIGEON_13_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_1_SET_CNT_SHIFT))&EPDC_PIGEON_13_1_SET_CNT_MASK)
16881 #define EPDC_PIGEON_13_1_CLR_CNT_MASK            0xFFFF0000u
16882 #define EPDC_PIGEON_13_1_CLR_CNT_SHIFT           16
16883 #define EPDC_PIGEON_13_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_1_CLR_CNT_SHIFT))&EPDC_PIGEON_13_1_CLR_CNT_MASK)
16884 /* PIGEON_13_2 Bit Fields */
16885 #define EPDC_PIGEON_13_2_SIG_LOGIC_MASK          0xFu
16886 #define EPDC_PIGEON_13_2_SIG_LOGIC_SHIFT         0
16887 #define EPDC_PIGEON_13_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_13_2_SIG_LOGIC_MASK)
16888 #define EPDC_PIGEON_13_2_SIG_ANOTHER_MASK        0x1F0u
16889 #define EPDC_PIGEON_13_2_SIG_ANOTHER_SHIFT       4
16890 #define EPDC_PIGEON_13_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_13_2_SIG_ANOTHER_MASK)
16891 /* PIGEON_14_0 Bit Fields */
16892 #define EPDC_PIGEON_14_0_EN_MASK                 0x1u
16893 #define EPDC_PIGEON_14_0_EN_SHIFT                0
16894 #define EPDC_PIGEON_14_0_POL_MASK                0x2u
16895 #define EPDC_PIGEON_14_0_POL_SHIFT               1
16896 #define EPDC_PIGEON_14_0_INC_SEL_MASK            0xCu
16897 #define EPDC_PIGEON_14_0_INC_SEL_SHIFT           2
16898 #define EPDC_PIGEON_14_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_INC_SEL_SHIFT))&EPDC_PIGEON_14_0_INC_SEL_MASK)
16899 #define EPDC_PIGEON_14_0_OFFSET_MASK             0xF0u
16900 #define EPDC_PIGEON_14_0_OFFSET_SHIFT            4
16901 #define EPDC_PIGEON_14_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_OFFSET_SHIFT))&EPDC_PIGEON_14_0_OFFSET_MASK)
16902 #define EPDC_PIGEON_14_0_MASK_CNT_SEL_MASK       0xF00u
16903 #define EPDC_PIGEON_14_0_MASK_CNT_SEL_SHIFT      8
16904 #define EPDC_PIGEON_14_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_14_0_MASK_CNT_SEL_MASK)
16905 #define EPDC_PIGEON_14_0_MASK_CNT_MASK           0xFFF000u
16906 #define EPDC_PIGEON_14_0_MASK_CNT_SHIFT          12
16907 #define EPDC_PIGEON_14_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_MASK_CNT_SHIFT))&EPDC_PIGEON_14_0_MASK_CNT_MASK)
16908 #define EPDC_PIGEON_14_0_STATE_MASK_MASK         0xFF000000u
16909 #define EPDC_PIGEON_14_0_STATE_MASK_SHIFT        24
16910 #define EPDC_PIGEON_14_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_STATE_MASK_SHIFT))&EPDC_PIGEON_14_0_STATE_MASK_MASK)
16911 /* PIGEON_14_1 Bit Fields */
16912 #define EPDC_PIGEON_14_1_SET_CNT_MASK            0xFFFFu
16913 #define EPDC_PIGEON_14_1_SET_CNT_SHIFT           0
16914 #define EPDC_PIGEON_14_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_1_SET_CNT_SHIFT))&EPDC_PIGEON_14_1_SET_CNT_MASK)
16915 #define EPDC_PIGEON_14_1_CLR_CNT_MASK            0xFFFF0000u
16916 #define EPDC_PIGEON_14_1_CLR_CNT_SHIFT           16
16917 #define EPDC_PIGEON_14_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_1_CLR_CNT_SHIFT))&EPDC_PIGEON_14_1_CLR_CNT_MASK)
16918 /* PIGEON_14_2 Bit Fields */
16919 #define EPDC_PIGEON_14_2_SIG_LOGIC_MASK          0xFu
16920 #define EPDC_PIGEON_14_2_SIG_LOGIC_SHIFT         0
16921 #define EPDC_PIGEON_14_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_14_2_SIG_LOGIC_MASK)
16922 #define EPDC_PIGEON_14_2_SIG_ANOTHER_MASK        0x1F0u
16923 #define EPDC_PIGEON_14_2_SIG_ANOTHER_SHIFT       4
16924 #define EPDC_PIGEON_14_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_14_2_SIG_ANOTHER_MASK)
16925 /* PIGEON_15_0 Bit Fields */
16926 #define EPDC_PIGEON_15_0_EN_MASK                 0x1u
16927 #define EPDC_PIGEON_15_0_EN_SHIFT                0
16928 #define EPDC_PIGEON_15_0_POL_MASK                0x2u
16929 #define EPDC_PIGEON_15_0_POL_SHIFT               1
16930 #define EPDC_PIGEON_15_0_INC_SEL_MASK            0xCu
16931 #define EPDC_PIGEON_15_0_INC_SEL_SHIFT           2
16932 #define EPDC_PIGEON_15_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_INC_SEL_SHIFT))&EPDC_PIGEON_15_0_INC_SEL_MASK)
16933 #define EPDC_PIGEON_15_0_OFFSET_MASK             0xF0u
16934 #define EPDC_PIGEON_15_0_OFFSET_SHIFT            4
16935 #define EPDC_PIGEON_15_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_OFFSET_SHIFT))&EPDC_PIGEON_15_0_OFFSET_MASK)
16936 #define EPDC_PIGEON_15_0_MASK_CNT_SEL_MASK       0xF00u
16937 #define EPDC_PIGEON_15_0_MASK_CNT_SEL_SHIFT      8
16938 #define EPDC_PIGEON_15_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_15_0_MASK_CNT_SEL_MASK)
16939 #define EPDC_PIGEON_15_0_MASK_CNT_MASK           0xFFF000u
16940 #define EPDC_PIGEON_15_0_MASK_CNT_SHIFT          12
16941 #define EPDC_PIGEON_15_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_MASK_CNT_SHIFT))&EPDC_PIGEON_15_0_MASK_CNT_MASK)
16942 #define EPDC_PIGEON_15_0_STATE_MASK_MASK         0xFF000000u
16943 #define EPDC_PIGEON_15_0_STATE_MASK_SHIFT        24
16944 #define EPDC_PIGEON_15_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_STATE_MASK_SHIFT))&EPDC_PIGEON_15_0_STATE_MASK_MASK)
16945 /* PIGEON_15_1 Bit Fields */
16946 #define EPDC_PIGEON_15_1_SET_CNT_MASK            0xFFFFu
16947 #define EPDC_PIGEON_15_1_SET_CNT_SHIFT           0
16948 #define EPDC_PIGEON_15_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_1_SET_CNT_SHIFT))&EPDC_PIGEON_15_1_SET_CNT_MASK)
16949 #define EPDC_PIGEON_15_1_CLR_CNT_MASK            0xFFFF0000u
16950 #define EPDC_PIGEON_15_1_CLR_CNT_SHIFT           16
16951 #define EPDC_PIGEON_15_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_1_CLR_CNT_SHIFT))&EPDC_PIGEON_15_1_CLR_CNT_MASK)
16952 /* PIGEON_15_2 Bit Fields */
16953 #define EPDC_PIGEON_15_2_SIG_LOGIC_MASK          0xFu
16954 #define EPDC_PIGEON_15_2_SIG_LOGIC_SHIFT         0
16955 #define EPDC_PIGEON_15_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_15_2_SIG_LOGIC_MASK)
16956 #define EPDC_PIGEON_15_2_SIG_ANOTHER_MASK        0x1F0u
16957 #define EPDC_PIGEON_15_2_SIG_ANOTHER_SHIFT       4
16958 #define EPDC_PIGEON_15_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_15_2_SIG_ANOTHER_MASK)
16959 /* PIGEON_16_0 Bit Fields */
16960 #define EPDC_PIGEON_16_0_EN_MASK                 0x1u
16961 #define EPDC_PIGEON_16_0_EN_SHIFT                0
16962 #define EPDC_PIGEON_16_0_POL_MASK                0x2u
16963 #define EPDC_PIGEON_16_0_POL_SHIFT               1
16964 #define EPDC_PIGEON_16_0_INC_SEL_MASK            0xCu
16965 #define EPDC_PIGEON_16_0_INC_SEL_SHIFT           2
16966 #define EPDC_PIGEON_16_0_INC_SEL(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_INC_SEL_SHIFT))&EPDC_PIGEON_16_0_INC_SEL_MASK)
16967 #define EPDC_PIGEON_16_0_OFFSET_MASK             0xF0u
16968 #define EPDC_PIGEON_16_0_OFFSET_SHIFT            4
16969 #define EPDC_PIGEON_16_0_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_OFFSET_SHIFT))&EPDC_PIGEON_16_0_OFFSET_MASK)
16970 #define EPDC_PIGEON_16_0_MASK_CNT_SEL_MASK       0xF00u
16971 #define EPDC_PIGEON_16_0_MASK_CNT_SEL_SHIFT      8
16972 #define EPDC_PIGEON_16_0_MASK_CNT_SEL(x)         (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_16_0_MASK_CNT_SEL_MASK)
16973 #define EPDC_PIGEON_16_0_MASK_CNT_MASK           0xFFF000u
16974 #define EPDC_PIGEON_16_0_MASK_CNT_SHIFT          12
16975 #define EPDC_PIGEON_16_0_MASK_CNT(x)             (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_MASK_CNT_SHIFT))&EPDC_PIGEON_16_0_MASK_CNT_MASK)
16976 #define EPDC_PIGEON_16_0_STATE_MASK_MASK         0xFF000000u
16977 #define EPDC_PIGEON_16_0_STATE_MASK_SHIFT        24
16978 #define EPDC_PIGEON_16_0_STATE_MASK(x)           (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_STATE_MASK_SHIFT))&EPDC_PIGEON_16_0_STATE_MASK_MASK)
16979 /* PIGEON_16_1 Bit Fields */
16980 #define EPDC_PIGEON_16_1_SET_CNT_MASK            0xFFFFu
16981 #define EPDC_PIGEON_16_1_SET_CNT_SHIFT           0
16982 #define EPDC_PIGEON_16_1_SET_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_1_SET_CNT_SHIFT))&EPDC_PIGEON_16_1_SET_CNT_MASK)
16983 #define EPDC_PIGEON_16_1_CLR_CNT_MASK            0xFFFF0000u
16984 #define EPDC_PIGEON_16_1_CLR_CNT_SHIFT           16
16985 #define EPDC_PIGEON_16_1_CLR_CNT(x)              (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_1_CLR_CNT_SHIFT))&EPDC_PIGEON_16_1_CLR_CNT_MASK)
16986 /* PIGEON_16_2 Bit Fields */
16987 #define EPDC_PIGEON_16_2_SIG_LOGIC_MASK          0xFu
16988 #define EPDC_PIGEON_16_2_SIG_LOGIC_SHIFT         0
16989 #define EPDC_PIGEON_16_2_SIG_LOGIC(x)            (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_16_2_SIG_LOGIC_MASK)
16990 #define EPDC_PIGEON_16_2_SIG_ANOTHER_MASK        0x1F0u
16991 #define EPDC_PIGEON_16_2_SIG_ANOTHER_SHIFT       4
16992 #define EPDC_PIGEON_16_2_SIG_ANOTHER(x)          (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_16_2_SIG_ANOTHER_MASK)
16993 
16994 /*!
16995  * @}
16996  */ /* end of group EPDC_Register_Masks */
16997 
16998 /* EPDC - Peripheral instance base addresses */
16999 /** Peripheral EPDC base address */
17000 #define EPDC_BASE                                (0x306F0000u)
17001 /** Peripheral EPDC base pointer */
17002 #define EPDC                                     ((EPDC_Type *)EPDC_BASE)
17003 #define EPDC_BASE_PTR                            (EPDC)
17004 /** Array initializer of EPDC peripheral base addresses */
17005 #define EPDC_BASE_ADDRS                          { EPDC_BASE }
17006 /** Array initializer of EPDC peripheral base pointers */
17007 #define EPDC_BASE_PTRS                           { EPDC }
17008 /** Interrupt vectors for the EPDC peripheral type */
17009 #define EPDC_IRQS                                { EPDC_IRQn }
17010 /* ----------------------------------------------------------------------------
17011    -- EPDC - Register accessor macros
17012    ---------------------------------------------------------------------------- */
17013 
17014 /*!
17015  * @addtogroup EPDC_Register_Accessor_Macros EPDC - Register accessor macros
17016  * @{
17017  */
17018 
17019 
17020 /* EPDC - Register instance definitions */
17021 /* EPDC */
17022 #define EPDC_CTRL                                EPDC_CTRL_REG(EPDC_BASE_PTR)
17023 #define EPDC_CTRL_SET                            EPDC_CTRL_SET_REG(EPDC_BASE_PTR)
17024 #define EPDC_CTRL_CLR                            EPDC_CTRL_CLR_REG(EPDC_BASE_PTR)
17025 #define EPDC_CTRL_TOG                            EPDC_CTRL_TOG_REG(EPDC_BASE_PTR)
17026 #define EPDC_WB_ADDR_TCE                         EPDC_WB_ADDR_TCE_REG(EPDC_BASE_PTR)
17027 #define EPDC_WVADDR                              EPDC_WVADDR_REG(EPDC_BASE_PTR)
17028 #define EPDC_WB_ADDR                             EPDC_WB_ADDR_REG(EPDC_BASE_PTR)
17029 #define EPDC_RES                                 EPDC_RES_REG(EPDC_BASE_PTR)
17030 #define EPDC_FORMAT                              EPDC_FORMAT_REG(EPDC_BASE_PTR)
17031 #define EPDC_FORMAT_SET                          EPDC_FORMAT_SET_REG(EPDC_BASE_PTR)
17032 #define EPDC_FORMAT_CLR                          EPDC_FORMAT_CLR_REG(EPDC_BASE_PTR)
17033 #define EPDC_FORMAT_TOG                          EPDC_FORMAT_TOG_REG(EPDC_BASE_PTR)
17034 #define EPDC_WB_FIELD0                           EPDC_WB_FIELD0_REG(EPDC_BASE_PTR)
17035 #define EPDC_WB_FIELD1                           EPDC_WB_FIELD1_REG(EPDC_BASE_PTR)
17036 #define EPDC_WB_FIELD2                           EPDC_WB_FIELD2_REG(EPDC_BASE_PTR)
17037 #define EPDC_WB_FIELD3                           EPDC_WB_FIELD3_REG(EPDC_BASE_PTR)
17038 #define EPDC_FIFOCTRL                            EPDC_FIFOCTRL_REG(EPDC_BASE_PTR)
17039 #define EPDC_FIFOCTRL_SET                        EPDC_FIFOCTRL_SET_REG(EPDC_BASE_PTR)
17040 #define EPDC_FIFOCTRL_CLR                        EPDC_FIFOCTRL_CLR_REG(EPDC_BASE_PTR)
17041 #define EPDC_FIFOCTRL_TOG                        EPDC_FIFOCTRL_TOG_REG(EPDC_BASE_PTR)
17042 #define EPDC_UPD_ADDR                            EPDC_UPD_ADDR_REG(EPDC_BASE_PTR)
17043 #define EPDC_UPD_STRIDE                          EPDC_UPD_STRIDE_REG(EPDC_BASE_PTR)
17044 #define EPDC_UPD_CORD                            EPDC_UPD_CORD_REG(EPDC_BASE_PTR)
17045 #define EPDC_UPD_SIZE                            EPDC_UPD_SIZE_REG(EPDC_BASE_PTR)
17046 #define EPDC_UPD_CTRL                            EPDC_UPD_CTRL_REG(EPDC_BASE_PTR)
17047 #define EPDC_UPD_CTRL_SET                        EPDC_UPD_CTRL_SET_REG(EPDC_BASE_PTR)
17048 #define EPDC_UPD_CTRL_CLR                        EPDC_UPD_CTRL_CLR_REG(EPDC_BASE_PTR)
17049 #define EPDC_UPD_CTRL_TOG                        EPDC_UPD_CTRL_TOG_REG(EPDC_BASE_PTR)
17050 #define EPDC_UPD_FIXED                           EPDC_UPD_FIXED_REG(EPDC_BASE_PTR)
17051 #define EPDC_UPD_FIXED_SET                       EPDC_UPD_FIXED_SET_REG(EPDC_BASE_PTR)
17052 #define EPDC_UPD_FIXED_CLR                       EPDC_UPD_FIXED_CLR_REG(EPDC_BASE_PTR)
17053 #define EPDC_UPD_FIXED_TOG                       EPDC_UPD_FIXED_TOG_REG(EPDC_BASE_PTR)
17054 #define EPDC_TEMP                                EPDC_TEMP_REG(EPDC_BASE_PTR)
17055 #define EPDC_AUTOWV_LUT                          EPDC_AUTOWV_LUT_REG(EPDC_BASE_PTR)
17056 #define EPDC_LUT_STANDBY1                        EPDC_LUT_STANDBY1_REG(EPDC_BASE_PTR)
17057 #define EPDC_LUT_STANDBY1_SET                    EPDC_LUT_STANDBY1_SET_REG(EPDC_BASE_PTR)
17058 #define EPDC_LUT_STANDBY1_CLR                    EPDC_LUT_STANDBY1_CLR_REG(EPDC_BASE_PTR)
17059 #define EPDC_LUT_STANDBY1_TOG                    EPDC_LUT_STANDBY1_TOG_REG(EPDC_BASE_PTR)
17060 #define EPDC_LUT_STANDBY2                        EPDC_LUT_STANDBY2_REG(EPDC_BASE_PTR)
17061 #define EPDC_LUT_STANDBY2_SET                    EPDC_LUT_STANDBY2_SET_REG(EPDC_BASE_PTR)
17062 #define EPDC_LUT_STANDBY2_CLR                    EPDC_LUT_STANDBY2_CLR_REG(EPDC_BASE_PTR)
17063 #define EPDC_LUT_STANDBY2_TOG                    EPDC_LUT_STANDBY2_TOG_REG(EPDC_BASE_PTR)
17064 #define EPDC_TCE_CTRL                            EPDC_TCE_CTRL_REG(EPDC_BASE_PTR)
17065 #define EPDC_TCE_CTRL_SET                        EPDC_TCE_CTRL_SET_REG(EPDC_BASE_PTR)
17066 #define EPDC_TCE_CTRL_CLR                        EPDC_TCE_CTRL_CLR_REG(EPDC_BASE_PTR)
17067 #define EPDC_TCE_CTRL_TOG                        EPDC_TCE_CTRL_TOG_REG(EPDC_BASE_PTR)
17068 #define EPDC_TCE_SDCFG                           EPDC_TCE_SDCFG_REG(EPDC_BASE_PTR)
17069 #define EPDC_TCE_SDCFG_SET                       EPDC_TCE_SDCFG_SET_REG(EPDC_BASE_PTR)
17070 #define EPDC_TCE_SDCFG_CLR                       EPDC_TCE_SDCFG_CLR_REG(EPDC_BASE_PTR)
17071 #define EPDC_TCE_SDCFG_TOG                       EPDC_TCE_SDCFG_TOG_REG(EPDC_BASE_PTR)
17072 #define EPDC_TCE_GDCFG                           EPDC_TCE_GDCFG_REG(EPDC_BASE_PTR)
17073 #define EPDC_TCE_GDCFG_SET                       EPDC_TCE_GDCFG_SET_REG(EPDC_BASE_PTR)
17074 #define EPDC_TCE_GDCFG_CLR                       EPDC_TCE_GDCFG_CLR_REG(EPDC_BASE_PTR)
17075 #define EPDC_TCE_GDCFG_TOG                       EPDC_TCE_GDCFG_TOG_REG(EPDC_BASE_PTR)
17076 #define EPDC_TCE_HSCAN1                          EPDC_TCE_HSCAN1_REG(EPDC_BASE_PTR)
17077 #define EPDC_TCE_HSCAN1_SET                      EPDC_TCE_HSCAN1_SET_REG(EPDC_BASE_PTR)
17078 #define EPDC_TCE_HSCAN1_CLR                      EPDC_TCE_HSCAN1_CLR_REG(EPDC_BASE_PTR)
17079 #define EPDC_TCE_HSCAN1_TOG                      EPDC_TCE_HSCAN1_TOG_REG(EPDC_BASE_PTR)
17080 #define EPDC_TCE_HSCAN2                          EPDC_TCE_HSCAN2_REG(EPDC_BASE_PTR)
17081 #define EPDC_TCE_HSCAN2_SET                      EPDC_TCE_HSCAN2_SET_REG(EPDC_BASE_PTR)
17082 #define EPDC_TCE_HSCAN2_CLR                      EPDC_TCE_HSCAN2_CLR_REG(EPDC_BASE_PTR)
17083 #define EPDC_TCE_HSCAN2_TOG                      EPDC_TCE_HSCAN2_TOG_REG(EPDC_BASE_PTR)
17084 #define EPDC_TCE_VSCAN                           EPDC_TCE_VSCAN_REG(EPDC_BASE_PTR)
17085 #define EPDC_TCE_VSCAN_SET                       EPDC_TCE_VSCAN_SET_REG(EPDC_BASE_PTR)
17086 #define EPDC_TCE_VSCAN_CLR                       EPDC_TCE_VSCAN_CLR_REG(EPDC_BASE_PTR)
17087 #define EPDC_TCE_VSCAN_TOG                       EPDC_TCE_VSCAN_TOG_REG(EPDC_BASE_PTR)
17088 #define EPDC_TCE_OE                              EPDC_TCE_OE_REG(EPDC_BASE_PTR)
17089 #define EPDC_TCE_OE_SET                          EPDC_TCE_OE_SET_REG(EPDC_BASE_PTR)
17090 #define EPDC_TCE_OE_CLR                          EPDC_TCE_OE_CLR_REG(EPDC_BASE_PTR)
17091 #define EPDC_TCE_OE_TOG                          EPDC_TCE_OE_TOG_REG(EPDC_BASE_PTR)
17092 #define EPDC_TCE_POLARITY                        EPDC_TCE_POLARITY_REG(EPDC_BASE_PTR)
17093 #define EPDC_TCE_POLARITY_SET                    EPDC_TCE_POLARITY_SET_REG(EPDC_BASE_PTR)
17094 #define EPDC_TCE_POLARITY_CLR                    EPDC_TCE_POLARITY_CLR_REG(EPDC_BASE_PTR)
17095 #define EPDC_TCE_POLARITY_TOG                    EPDC_TCE_POLARITY_TOG_REG(EPDC_BASE_PTR)
17096 #define EPDC_TCE_TIMING1                         EPDC_TCE_TIMING1_REG(EPDC_BASE_PTR)
17097 #define EPDC_TCE_TIMING1_SET                     EPDC_TCE_TIMING1_SET_REG(EPDC_BASE_PTR)
17098 #define EPDC_TCE_TIMING1_CLR                     EPDC_TCE_TIMING1_CLR_REG(EPDC_BASE_PTR)
17099 #define EPDC_TCE_TIMING1_TOG                     EPDC_TCE_TIMING1_TOG_REG(EPDC_BASE_PTR)
17100 #define EPDC_TCE_TIMING2                         EPDC_TCE_TIMING2_REG(EPDC_BASE_PTR)
17101 #define EPDC_TCE_TIMING2_SET                     EPDC_TCE_TIMING2_SET_REG(EPDC_BASE_PTR)
17102 #define EPDC_TCE_TIMING2_CLR                     EPDC_TCE_TIMING2_CLR_REG(EPDC_BASE_PTR)
17103 #define EPDC_TCE_TIMING2_TOG                     EPDC_TCE_TIMING2_TOG_REG(EPDC_BASE_PTR)
17104 #define EPDC_TCE_TIMING3                         EPDC_TCE_TIMING3_REG(EPDC_BASE_PTR)
17105 #define EPDC_TCE_TIMING3_SET                     EPDC_TCE_TIMING3_SET_REG(EPDC_BASE_PTR)
17106 #define EPDC_TCE_TIMING3_CLR                     EPDC_TCE_TIMING3_CLR_REG(EPDC_BASE_PTR)
17107 #define EPDC_TCE_TIMING3_TOG                     EPDC_TCE_TIMING3_TOG_REG(EPDC_BASE_PTR)
17108 #define EPDC_PIGEON_CTRL0                        EPDC_PIGEON_CTRL0_REG(EPDC_BASE_PTR)
17109 #define EPDC_PIGEON_CTRL0_SET                    EPDC_PIGEON_CTRL0_SET_REG(EPDC_BASE_PTR)
17110 #define EPDC_PIGEON_CTRL0_CLR                    EPDC_PIGEON_CTRL0_CLR_REG(EPDC_BASE_PTR)
17111 #define EPDC_PIGEON_CTRL0_TOG                    EPDC_PIGEON_CTRL0_TOG_REG(EPDC_BASE_PTR)
17112 #define EPDC_PIGEON_CTRL1                        EPDC_PIGEON_CTRL1_REG(EPDC_BASE_PTR)
17113 #define EPDC_PIGEON_CTRL1_SET                    EPDC_PIGEON_CTRL1_SET_REG(EPDC_BASE_PTR)
17114 #define EPDC_PIGEON_CTRL1_CLR                    EPDC_PIGEON_CTRL1_CLR_REG(EPDC_BASE_PTR)
17115 #define EPDC_PIGEON_CTRL1_TOG                    EPDC_PIGEON_CTRL1_TOG_REG(EPDC_BASE_PTR)
17116 #define EPDC_IRQ_MASK1                           EPDC_IRQ_MASK1_REG(EPDC_BASE_PTR)
17117 #define EPDC_IRQ_MASK1_SET                       EPDC_IRQ_MASK1_SET_REG(EPDC_BASE_PTR)
17118 #define EPDC_IRQ_MASK1_CLR                       EPDC_IRQ_MASK1_CLR_REG(EPDC_BASE_PTR)
17119 #define EPDC_IRQ_MASK1_TOG                       EPDC_IRQ_MASK1_TOG_REG(EPDC_BASE_PTR)
17120 #define EPDC_IRQ_MASK2                           EPDC_IRQ_MASK2_REG(EPDC_BASE_PTR)
17121 #define EPDC_IRQ_MASK2_SET                       EPDC_IRQ_MASK2_SET_REG(EPDC_BASE_PTR)
17122 #define EPDC_IRQ_MASK2_CLR                       EPDC_IRQ_MASK2_CLR_REG(EPDC_BASE_PTR)
17123 #define EPDC_IRQ_MASK2_TOG                       EPDC_IRQ_MASK2_TOG_REG(EPDC_BASE_PTR)
17124 #define EPDC_IRQ1                                EPDC_IRQ1_REG(EPDC_BASE_PTR)
17125 #define EPDC_IRQ1_SET                            EPDC_IRQ1_SET_REG(EPDC_BASE_PTR)
17126 #define EPDC_IRQ1_CLR                            EPDC_IRQ1_CLR_REG(EPDC_BASE_PTR)
17127 #define EPDC_IRQ1_TOG                            EPDC_IRQ1_TOG_REG(EPDC_BASE_PTR)
17128 #define EPDC_IRQ2                                EPDC_IRQ2_REG(EPDC_BASE_PTR)
17129 #define EPDC_IRQ2_SET                            EPDC_IRQ2_SET_REG(EPDC_BASE_PTR)
17130 #define EPDC_IRQ2_CLR                            EPDC_IRQ2_CLR_REG(EPDC_BASE_PTR)
17131 #define EPDC_IRQ2_TOG                            EPDC_IRQ2_TOG_REG(EPDC_BASE_PTR)
17132 #define EPDC_IRQ_MASK                            EPDC_IRQ_MASK_REG(EPDC_BASE_PTR)
17133 #define EPDC_IRQ_MASK_SET                        EPDC_IRQ_MASK_SET_REG(EPDC_BASE_PTR)
17134 #define EPDC_IRQ_MASK_CLR                        EPDC_IRQ_MASK_CLR_REG(EPDC_BASE_PTR)
17135 #define EPDC_IRQ_MASK_TOG                        EPDC_IRQ_MASK_TOG_REG(EPDC_BASE_PTR)
17136 #define EPDC_IRQ                                 EPDC_IRQ_REG(EPDC_BASE_PTR)
17137 #define EPDC_IRQ_SET                             EPDC_IRQ_SET_REG(EPDC_BASE_PTR)
17138 #define EPDC_IRQ_CLR                             EPDC_IRQ_CLR_REG(EPDC_BASE_PTR)
17139 #define EPDC_IRQ_TOG                             EPDC_IRQ_TOG_REG(EPDC_BASE_PTR)
17140 #define EPDC_STATUS_LUTS1                        EPDC_STATUS_LUTS1_REG(EPDC_BASE_PTR)
17141 #define EPDC_STATUS_LUTS1_SET                    EPDC_STATUS_LUTS1_SET_REG(EPDC_BASE_PTR)
17142 #define EPDC_STATUS_LUTS1_CLR                    EPDC_STATUS_LUTS1_CLR_REG(EPDC_BASE_PTR)
17143 #define EPDC_STATUS_LUTS1_TOG                    EPDC_STATUS_LUTS1_TOG_REG(EPDC_BASE_PTR)
17144 #define EPDC_STATUS_LUTS2                        EPDC_STATUS_LUTS2_REG(EPDC_BASE_PTR)
17145 #define EPDC_STATUS_LUTS2_SET                    EPDC_STATUS_LUTS2_SET_REG(EPDC_BASE_PTR)
17146 #define EPDC_STATUS_LUTS2_CLR                    EPDC_STATUS_LUTS2_CLR_REG(EPDC_BASE_PTR)
17147 #define EPDC_STATUS_LUTS2_TOG                    EPDC_STATUS_LUTS2_TOG_REG(EPDC_BASE_PTR)
17148 #define EPDC_STATUS_NEXTLUT                      EPDC_STATUS_NEXTLUT_REG(EPDC_BASE_PTR)
17149 #define EPDC_STATUS_COL1                         EPDC_STATUS_COL1_REG(EPDC_BASE_PTR)
17150 #define EPDC_STATUS_COL1_SET                     EPDC_STATUS_COL1_SET_REG(EPDC_BASE_PTR)
17151 #define EPDC_STATUS_COL1_CLR                     EPDC_STATUS_COL1_CLR_REG(EPDC_BASE_PTR)
17152 #define EPDC_STATUS_COL1_TOG                     EPDC_STATUS_COL1_TOG_REG(EPDC_BASE_PTR)
17153 #define EPDC_STATUS_COL2                         EPDC_STATUS_COL2_REG(EPDC_BASE_PTR)
17154 #define EPDC_STATUS_COL2_SET                     EPDC_STATUS_COL2_SET_REG(EPDC_BASE_PTR)
17155 #define EPDC_STATUS_COL2_CLR                     EPDC_STATUS_COL2_CLR_REG(EPDC_BASE_PTR)
17156 #define EPDC_STATUS_COL2_TOG                     EPDC_STATUS_COL2_TOG_REG(EPDC_BASE_PTR)
17157 #define EPDC_STATUS                              EPDC_STATUS_REG(EPDC_BASE_PTR)
17158 #define EPDC_STATUS_SET                          EPDC_STATUS_SET_REG(EPDC_BASE_PTR)
17159 #define EPDC_STATUS_CLR                          EPDC_STATUS_CLR_REG(EPDC_BASE_PTR)
17160 #define EPDC_STATUS_TOG                          EPDC_STATUS_TOG_REG(EPDC_BASE_PTR)
17161 #define EPDC_UPD_COL_CORD                        EPDC_UPD_COL_CORD_REG(EPDC_BASE_PTR)
17162 #define EPDC_UPD_COL_SIZE                        EPDC_UPD_COL_SIZE_REG(EPDC_BASE_PTR)
17163 #define EPDC_HIST1_PARAM                         EPDC_HIST1_PARAM_REG(EPDC_BASE_PTR)
17164 #define EPDC_HIST2_PARAM                         EPDC_HIST2_PARAM_REG(EPDC_BASE_PTR)
17165 #define EPDC_HIST4_PARAM                         EPDC_HIST4_PARAM_REG(EPDC_BASE_PTR)
17166 #define EPDC_HIST8_PARAM0                        EPDC_HIST8_PARAM0_REG(EPDC_BASE_PTR)
17167 #define EPDC_HIST8_PARAM1                        EPDC_HIST8_PARAM1_REG(EPDC_BASE_PTR)
17168 #define EPDC_HIST16_PARAM0                       EPDC_HIST16_PARAM0_REG(EPDC_BASE_PTR)
17169 #define EPDC_HIST16_PARAM1                       EPDC_HIST16_PARAM1_REG(EPDC_BASE_PTR)
17170 #define EPDC_HIST16_PARAM2                       EPDC_HIST16_PARAM2_REG(EPDC_BASE_PTR)
17171 #define EPDC_HIST16_PARAM3                       EPDC_HIST16_PARAM3_REG(EPDC_BASE_PTR)
17172 #define EPDC_GPIO                                EPDC_GPIO_REG(EPDC_BASE_PTR)
17173 #define EPDC_GPIO_SET                            EPDC_GPIO_SET_REG(EPDC_BASE_PTR)
17174 #define EPDC_GPIO_CLR                            EPDC_GPIO_CLR_REG(EPDC_BASE_PTR)
17175 #define EPDC_GPIO_TOG                            EPDC_GPIO_TOG_REG(EPDC_BASE_PTR)
17176 #define EPDC_VERSION                             EPDC_VERSION_REG(EPDC_BASE_PTR)
17177 #define EPDC_PIGEON_0_0                          EPDC_PIGEON_0_0_REG(EPDC_BASE_PTR)
17178 #define EPDC_PIGEON_0_1                          EPDC_PIGEON_0_1_REG(EPDC_BASE_PTR)
17179 #define EPDC_PIGEON_0_2                          EPDC_PIGEON_0_2_REG(EPDC_BASE_PTR)
17180 #define EPDC_PIGEON_1_0                          EPDC_PIGEON_1_0_REG(EPDC_BASE_PTR)
17181 #define EPDC_PIGEON_1_1                          EPDC_PIGEON_1_1_REG(EPDC_BASE_PTR)
17182 #define EPDC_PIGEON_1_2                          EPDC_PIGEON_1_2_REG(EPDC_BASE_PTR)
17183 #define EPDC_PIGEON_2_0                          EPDC_PIGEON_2_0_REG(EPDC_BASE_PTR)
17184 #define EPDC_PIGEON_2_1                          EPDC_PIGEON_2_1_REG(EPDC_BASE_PTR)
17185 #define EPDC_PIGEON_2_2                          EPDC_PIGEON_2_2_REG(EPDC_BASE_PTR)
17186 #define EPDC_PIGEON_3_0                          EPDC_PIGEON_3_0_REG(EPDC_BASE_PTR)
17187 #define EPDC_PIGEON_3_1                          EPDC_PIGEON_3_1_REG(EPDC_BASE_PTR)
17188 #define EPDC_PIGEON_3_2                          EPDC_PIGEON_3_2_REG(EPDC_BASE_PTR)
17189 #define EPDC_PIGEON_4_0                          EPDC_PIGEON_4_0_REG(EPDC_BASE_PTR)
17190 #define EPDC_PIGEON_4_1                          EPDC_PIGEON_4_1_REG(EPDC_BASE_PTR)
17191 #define EPDC_PIGEON_4_2                          EPDC_PIGEON_4_2_REG(EPDC_BASE_PTR)
17192 #define EPDC_PIGEON_5_0                          EPDC_PIGEON_5_0_REG(EPDC_BASE_PTR)
17193 #define EPDC_PIGEON_5_1                          EPDC_PIGEON_5_1_REG(EPDC_BASE_PTR)
17194 #define EPDC_PIGEON_5_2                          EPDC_PIGEON_5_2_REG(EPDC_BASE_PTR)
17195 #define EPDC_PIGEON_6_0                          EPDC_PIGEON_6_0_REG(EPDC_BASE_PTR)
17196 #define EPDC_PIGEON_6_1                          EPDC_PIGEON_6_1_REG(EPDC_BASE_PTR)
17197 #define EPDC_PIGEON_6_2                          EPDC_PIGEON_6_2_REG(EPDC_BASE_PTR)
17198 #define EPDC_PIGEON_7_0                          EPDC_PIGEON_7_0_REG(EPDC_BASE_PTR)
17199 #define EPDC_PIGEON_7_1                          EPDC_PIGEON_7_1_REG(EPDC_BASE_PTR)
17200 #define EPDC_PIGEON_7_2                          EPDC_PIGEON_7_2_REG(EPDC_BASE_PTR)
17201 #define EPDC_PIGEON_8_0                          EPDC_PIGEON_8_0_REG(EPDC_BASE_PTR)
17202 #define EPDC_PIGEON_8_1                          EPDC_PIGEON_8_1_REG(EPDC_BASE_PTR)
17203 #define EPDC_PIGEON_8_2                          EPDC_PIGEON_8_2_REG(EPDC_BASE_PTR)
17204 #define EPDC_PIGEON_9_0                          EPDC_PIGEON_9_0_REG(EPDC_BASE_PTR)
17205 #define EPDC_PIGEON_9_1                          EPDC_PIGEON_9_1_REG(EPDC_BASE_PTR)
17206 #define EPDC_PIGEON_9_2                          EPDC_PIGEON_9_2_REG(EPDC_BASE_PTR)
17207 #define EPDC_PIGEON_10_0                         EPDC_PIGEON_10_0_REG(EPDC_BASE_PTR)
17208 #define EPDC_PIGEON_10_1                         EPDC_PIGEON_10_1_REG(EPDC_BASE_PTR)
17209 #define EPDC_PIGEON_10_2                         EPDC_PIGEON_10_2_REG(EPDC_BASE_PTR)
17210 #define EPDC_PIGEON_11_0                         EPDC_PIGEON_11_0_REG(EPDC_BASE_PTR)
17211 #define EPDC_PIGEON_11_1                         EPDC_PIGEON_11_1_REG(EPDC_BASE_PTR)
17212 #define EPDC_PIGEON_11_2                         EPDC_PIGEON_11_2_REG(EPDC_BASE_PTR)
17213 #define EPDC_PIGEON_12_0                         EPDC_PIGEON_12_0_REG(EPDC_BASE_PTR)
17214 #define EPDC_PIGEON_12_1                         EPDC_PIGEON_12_1_REG(EPDC_BASE_PTR)
17215 #define EPDC_PIGEON_12_2                         EPDC_PIGEON_12_2_REG(EPDC_BASE_PTR)
17216 #define EPDC_PIGEON_13_0                         EPDC_PIGEON_13_0_REG(EPDC_BASE_PTR)
17217 #define EPDC_PIGEON_13_1                         EPDC_PIGEON_13_1_REG(EPDC_BASE_PTR)
17218 #define EPDC_PIGEON_13_2                         EPDC_PIGEON_13_2_REG(EPDC_BASE_PTR)
17219 #define EPDC_PIGEON_14_0                         EPDC_PIGEON_14_0_REG(EPDC_BASE_PTR)
17220 #define EPDC_PIGEON_14_1                         EPDC_PIGEON_14_1_REG(EPDC_BASE_PTR)
17221 #define EPDC_PIGEON_14_2                         EPDC_PIGEON_14_2_REG(EPDC_BASE_PTR)
17222 #define EPDC_PIGEON_15_0                         EPDC_PIGEON_15_0_REG(EPDC_BASE_PTR)
17223 #define EPDC_PIGEON_15_1                         EPDC_PIGEON_15_1_REG(EPDC_BASE_PTR)
17224 #define EPDC_PIGEON_15_2                         EPDC_PIGEON_15_2_REG(EPDC_BASE_PTR)
17225 #define EPDC_PIGEON_16_0                         EPDC_PIGEON_16_0_REG(EPDC_BASE_PTR)
17226 #define EPDC_PIGEON_16_1                         EPDC_PIGEON_16_1_REG(EPDC_BASE_PTR)
17227 #define EPDC_PIGEON_16_2                         EPDC_PIGEON_16_2_REG(EPDC_BASE_PTR)
17228 /*!
17229  * @}
17230  */ /* end of group EPDC_Register_Accessor_Macros */
17231 
17232 
17233 /*!
17234  * @}
17235  */ /* end of group EPDC_Peripheral */
17236 
17237 /* ----------------------------------------------------------------------------
17238    -- SIM Peripheral Access Layer
17239    ---------------------------------------------------------------------------- */
17240 
17241 /*!
17242  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
17243  * @{
17244  */
17245 
17246 /** SIM - Register Layout Typedef */
17247 typedef struct {
17248   __IO  uint32_t PORT1_CNTL;                             /**< SIM Port1 Control Register, offset: 0x0 */
17249   __IO  uint32_t SETUP;                                  /**< SIM Setup Register, offset: 0x4 */
17250   __IO  uint32_t PORT1_DETECT;                           /**< SIM Port 1 Detect Register, offset: 0x8 */
17251   __IO  uint32_t XMT_BUF;                                /**< SIM Transmit Buffer Register, offset: 0xC */
17252   __I   uint32_t RCV_BUF;                                /**< SIM Receive Buffer Register, offset: 0x10 */
17253   __IO  uint32_t PORT0_CNTL;                             /**< SIM Port0 Control Register, offset: 0x14 */
17254   __IO  uint32_t CNTL;                                   /**< SIM Control Register, offset: 0x18 */
17255   __IO  uint32_t CLK_PRESCALER;                          /**< SIM Clock Prescaler Register, offset: 0x1C */
17256   __IO  uint32_t RCV_THRESHOLD;                          /**< SIM Receive Threshold Register, offset: 0x20 */
17257   __IO  uint32_t ENABLE;                                 /**< SIM Enable Register, offset: 0x24 */
17258   __IO  uint32_t XMT_STATUS;                             /**< SIM Transmit Status Register, offset: 0x28 */
17259   __IO  uint32_t RCV_STATUS;                             /**< SIM Receive Status Register, offset: 0x2C */
17260   __IO  uint32_t INT_MASK;                               /**< SIM Interrupt Mask Register, offset: 0x30 */
17261   uint8_t RESERVED_0[8];
17262   __IO  uint32_t PORT0_DETECT;                           /**< SIM Port0 Detect Register, offset: 0x3C */
17263   __IO  uint32_t DATA_FORMAT;                            /**< SIM Data Format Register, offset: 0x40 */
17264   __IO  uint32_t XMT_THRESHOLD;                          /**< SIM Transmit Threshold Register, offset: 0x44 */
17265   __IO  uint32_t GUARD_CNTL;                             /**< SIM Transmit Guard Control Register, offset: 0x48 */
17266   __IO  uint32_t OD_CONFIG;                              /**< SIM Open Drain Configuration Control Register, offset: 0x4C */
17267   __IO  uint32_t RESET_CNTL;                             /**< SIM Reset Control Register, offset: 0x50 */
17268   __IO  uint32_t CHAR_WAIT;                              /**< SIM Character Wait Time Register, offset: 0x54 */
17269   __IO  uint32_t GPCNT;                                  /**< SIM General Purpose Counter Register, offset: 0x58 */
17270   __IO  uint32_t DIVISOR;                                /**< SIM Divisor Register, offset: 0x5C */
17271   __IO  uint32_t BWT;                                    /**< SIM Block Wait Time Register, offset: 0x60 */
17272   __IO  uint32_t BGT;                                    /**< SIM Block Guard Time Register, offset: 0x64 */
17273   __IO  uint32_t BWT_H;                                  /**< SIM Block Wait Time Register HIGH, offset: 0x68 */
17274   __I   uint32_t XMT_FIFO_STAT;                          /**< SIM Transmit FIFO Status Register, offset: 0x6C */
17275   __I   uint32_t RCV_FIFO_CNT;                           /**< SIM Receive FIFO Counter Register, offset: 0x70 */
17276   __I   uint32_t RCV_FIFO_WPTR;                          /**< SIM Receive FIFO Write Pointer Register, offset: 0x74 */
17277   __I   uint32_t RCV_FIFO_RPTR;                          /**< SIM Receive FIFO Read Pointer Register, offset: 0x78 */
17278 } SIM_Type, *SIM_MemMapPtr;
17279 /* ----------------------------------------------------------------------------
17280    -- SIM - Register accessor macros
17281    ---------------------------------------------------------------------------- */
17282 
17283 /*!
17284  * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
17285  * @{
17286  */
17287 
17288 
17289 /* SIM - Register accessors */
17290 #define SIM_PORT1_CNTL_REG(base)                 ((base)->PORT1_CNTL)
17291 #define SIM_SETUP_REG(base)                      ((base)->SETUP)
17292 #define SIM_PORT1_DETECT_REG(base)               ((base)->PORT1_DETECT)
17293 #define SIM_XMT_BUF_REG(base)                    ((base)->XMT_BUF)
17294 #define SIM_RCV_BUF_REG(base)                    ((base)->RCV_BUF)
17295 #define SIM_PORT0_CNTL_REG(base)                 ((base)->PORT0_CNTL)
17296 #define SIM_CNTL_REG(base)                       ((base)->CNTL)
17297 #define SIM_CLK_PRESCALER_REG(base)              ((base)->CLK_PRESCALER)
17298 #define SIM_RCV_THRESHOLD_REG(base)              ((base)->RCV_THRESHOLD)
17299 #define SIM_ENABLE_REG(base)                     ((base)->ENABLE)
17300 #define SIM_XMT_STATUS_REG(base)                 ((base)->XMT_STATUS)
17301 #define SIM_RCV_STATUS_REG(base)                 ((base)->RCV_STATUS)
17302 #define SIM_INT_MASK_REG(base)                   ((base)->INT_MASK)
17303 #define SIM_PORT0_DETECT_REG(base)               ((base)->PORT0_DETECT)
17304 #define SIM_DATA_FORMAT_REG(base)                ((base)->DATA_FORMAT)
17305 #define SIM_XMT_THRESHOLD_REG(base)              ((base)->XMT_THRESHOLD)
17306 #define SIM_GUARD_CNTL_REG(base)                 ((base)->GUARD_CNTL)
17307 #define SIM_OD_CONFIG_REG(base)                  ((base)->OD_CONFIG)
17308 #define SIM_RESET_CNTL_REG(base)                 ((base)->RESET_CNTL)
17309 #define SIM_CHAR_WAIT_REG(base)                  ((base)->CHAR_WAIT)
17310 #define SIM_GPCNT_REG(base)                      ((base)->GPCNT)
17311 #define SIM_DIVISOR_REG(base)                    ((base)->DIVISOR)
17312 #define SIM_BWT_REG(base)                        ((base)->BWT)
17313 #define SIM_BGT_REG(base)                        ((base)->BGT)
17314 #define SIM_BWT_H_REG(base)                      ((base)->BWT_H)
17315 #define SIM_XMT_FIFO_STAT_REG(base)              ((base)->XMT_FIFO_STAT)
17316 #define SIM_RCV_FIFO_CNT_REG(base)               ((base)->RCV_FIFO_CNT)
17317 #define SIM_RCV_FIFO_WPTR_REG(base)              ((base)->RCV_FIFO_WPTR)
17318 #define SIM_RCV_FIFO_RPTR_REG(base)              ((base)->RCV_FIFO_RPTR)
17319 
17320 /*!
17321  * @}
17322  */ /* end of group SIM_Register_Accessor_Macros */
17323 /* ----------------------------------------------------------------------------
17324    -- SIM Register Masks
17325    ---------------------------------------------------------------------------- */
17326 
17327 /*!
17328  * @addtogroup SIM_Register_Masks SIM Register Masks
17329  * @{
17330  */
17331 
17332 /* PORT1_CNTL Bit Fields */
17333 #define SIM_PORT1_CNTL_SAPD1_MASK                0x1u
17334 #define SIM_PORT1_CNTL_SAPD1_SHIFT               0
17335 #define SIM_PORT1_CNTL_SVEN1_MASK                0x2u
17336 #define SIM_PORT1_CNTL_SVEN1_SHIFT               1
17337 #define SIM_PORT1_CNTL_STEN1_MASK                0x4u
17338 #define SIM_PORT1_CNTL_STEN1_SHIFT               2
17339 #define SIM_PORT1_CNTL_SRST1_MASK                0x8u
17340 #define SIM_PORT1_CNTL_SRST1_SHIFT               3
17341 #define SIM_PORT1_CNTL_SCEN1_MASK                0x10u
17342 #define SIM_PORT1_CNTL_SCEN1_SHIFT               4
17343 #define SIM_PORT1_CNTL_SCSP1_MASK                0x20u
17344 #define SIM_PORT1_CNTL_SCSP1_SHIFT               5
17345 #define SIM_PORT1_CNTL_VOLT3_1_MASK              0x40u
17346 #define SIM_PORT1_CNTL_VOLT3_1_SHIFT             6
17347 #define SIM_PORT1_CNTL_SFPD1_MASK                0x80u
17348 #define SIM_PORT1_CNTL_SFPD1_SHIFT               7
17349 /* SETUP Bit Fields */
17350 #define SIM_SETUP_AMODE_MASK                     0x1u
17351 #define SIM_SETUP_AMODE_SHIFT                    0
17352 #define SIM_SETUP_SPS_MASK                       0x2u
17353 #define SIM_SETUP_SPS_SHIFT                      1
17354 /* PORT1_DETECT Bit Fields */
17355 #define SIM_PORT1_DETECT_SDIM1_MASK              0x1u
17356 #define SIM_PORT1_DETECT_SDIM1_SHIFT             0
17357 #define SIM_PORT1_DETECT_SDI1_MASK               0x2u
17358 #define SIM_PORT1_DETECT_SDI1_SHIFT              1
17359 #define SIM_PORT1_DETECT_SPDP1_MASK              0x4u
17360 #define SIM_PORT1_DETECT_SPDP1_SHIFT             2
17361 #define SIM_PORT1_DETECT_SPDS1_MASK              0x8u
17362 #define SIM_PORT1_DETECT_SPDS1_SHIFT             3
17363 /* XMT_BUF Bit Fields */
17364 #define SIM_XMT_BUF_XMT_MASK                     0xFFu
17365 #define SIM_XMT_BUF_XMT_SHIFT                    0
17366 #define SIM_XMT_BUF_XMT(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_XMT_BUF_XMT_SHIFT))&SIM_XMT_BUF_XMT_MASK)
17367 /* RCV_BUF Bit Fields */
17368 #define SIM_RCV_BUF_RCV_MASK                     0xFFu
17369 #define SIM_RCV_BUF_RCV_SHIFT                    0
17370 #define SIM_RCV_BUF_RCV(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_RCV_BUF_RCV_SHIFT))&SIM_RCV_BUF_RCV_MASK)
17371 #define SIM_RCV_BUF_PE_MASK                      0x100u
17372 #define SIM_RCV_BUF_PE_SHIFT                     8
17373 #define SIM_RCV_BUF_FE_MASK                      0x200u
17374 #define SIM_RCV_BUF_FE_SHIFT                     9
17375 #define SIM_RCV_BUF_CWT_MASK                     0x400u
17376 #define SIM_RCV_BUF_CWT_SHIFT                    10
17377 /* PORT0_CNTL Bit Fields */
17378 #define SIM_PORT0_CNTL_SAPD0_MASK                0x1u
17379 #define SIM_PORT0_CNTL_SAPD0_SHIFT               0
17380 #define SIM_PORT0_CNTL_SVEN0_MASK                0x2u
17381 #define SIM_PORT0_CNTL_SVEN0_SHIFT               1
17382 #define SIM_PORT0_CNTL_STEN0_MASK                0x4u
17383 #define SIM_PORT0_CNTL_STEN0_SHIFT               2
17384 #define SIM_PORT0_CNTL_SRST0_MASK                0x8u
17385 #define SIM_PORT0_CNTL_SRST0_SHIFT               3
17386 #define SIM_PORT0_CNTL_SCEN0_MASK                0x10u
17387 #define SIM_PORT0_CNTL_SCEN0_SHIFT               4
17388 #define SIM_PORT0_CNTL_SCSP0_MASK                0x20u
17389 #define SIM_PORT0_CNTL_SCSP0_SHIFT               5
17390 #define SIM_PORT0_CNTL_VOLT3_0_MASK              0x40u
17391 #define SIM_PORT0_CNTL_VOLT3_0_SHIFT             6
17392 #define SIM_PORT0_CNTL_SFPD0_MASK                0x80u
17393 #define SIM_PORT0_CNTL_SFPD0_SHIFT               7
17394 /* CNTL Bit Fields */
17395 #define SIM_CNTL_ICM_MASK                        0x2u
17396 #define SIM_CNTL_ICM_SHIFT                       1
17397 #define SIM_CNTL_ANACK_MASK                      0x4u
17398 #define SIM_CNTL_ANACK_SHIFT                     2
17399 #define SIM_CNTL_ONACK_MASK                      0x8u
17400 #define SIM_CNTL_ONACK_SHIFT                     3
17401 #define SIM_CNTL_Sample12_MASK                   0x20u
17402 #define SIM_CNTL_Sample12_SHIFT                  5
17403 #define SIM_CNTL_baud_sel_MASK                   0x1C0u
17404 #define SIM_CNTL_baud_sel_SHIFT                  6
17405 #define SIM_CNTL_baud_sel(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_CNTL_baud_sel_SHIFT))&SIM_CNTL_baud_sel_MASK)
17406 #define SIM_CNTL_gpcnt_clk_sel_MASK              0x600u
17407 #define SIM_CNTL_gpcnt_clk_sel_SHIFT             9
17408 #define SIM_CNTL_gpcnt_clk_sel(x)                (((uint32_t)(((uint32_t)(x))<<SIM_CNTL_gpcnt_clk_sel_SHIFT))&SIM_CNTL_gpcnt_clk_sel_MASK)
17409 #define SIM_CNTL_CWTEN_MASK                      0x800u
17410 #define SIM_CNTL_CWTEN_SHIFT                     11
17411 #define SIM_CNTL_LRCEN_MASK                      0x1000u
17412 #define SIM_CNTL_LRCEN_SHIFT                     12
17413 #define SIM_CNTL_CRCEN_MASK                      0x2000u
17414 #define SIM_CNTL_CRCEN_SHIFT                     13
17415 #define SIM_CNTL_xmt_crc_lrc_MASK                0x4000u
17416 #define SIM_CNTL_xmt_crc_lrc_SHIFT               14
17417 #define SIM_CNTL_BWTEN_MASK                      0x8000u
17418 #define SIM_CNTL_BWTEN_SHIFT                     15
17419 /* CLK_PRESCALER Bit Fields */
17420 #define SIM_CLK_PRESCALER_CLK_PRESCALER_MASK     0xFFu
17421 #define SIM_CLK_PRESCALER_CLK_PRESCALER_SHIFT    0
17422 #define SIM_CLK_PRESCALER_CLK_PRESCALER(x)       (((uint32_t)(((uint32_t)(x))<<SIM_CLK_PRESCALER_CLK_PRESCALER_SHIFT))&SIM_CLK_PRESCALER_CLK_PRESCALER_MASK)
17423 /* RCV_THRESHOLD Bit Fields */
17424 #define SIM_RCV_THRESHOLD_RDT_MASK               0x1FFu
17425 #define SIM_RCV_THRESHOLD_RDT_SHIFT              0
17426 #define SIM_RCV_THRESHOLD_RDT(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_RCV_THRESHOLD_RDT_SHIFT))&SIM_RCV_THRESHOLD_RDT_MASK)
17427 #define SIM_RCV_THRESHOLD_RTH_MASK               0x1E00u
17428 #define SIM_RCV_THRESHOLD_RTH_SHIFT              9
17429 #define SIM_RCV_THRESHOLD_RTH(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_RCV_THRESHOLD_RTH_SHIFT))&SIM_RCV_THRESHOLD_RTH_MASK)
17430 /* ENABLE Bit Fields */
17431 #define SIM_ENABLE_RCV_EN_MASK                   0x1u
17432 #define SIM_ENABLE_RCV_EN_SHIFT                  0
17433 #define SIM_ENABLE_XMT_EN_MASK                   0x2u
17434 #define SIM_ENABLE_XMT_EN_SHIFT                  1
17435 #define SIM_ENABLE_RXDMA_EN_MASK                 0x4u
17436 #define SIM_ENABLE_RXDMA_EN_SHIFT                2
17437 #define SIM_ENABLE_TXDMA_EN_MASK                 0x8u
17438 #define SIM_ENABLE_TXDMA_EN_SHIFT                3
17439 #define SIM_ENABLE_NACK_DD_EN_MASK               0x10u
17440 #define SIM_ENABLE_NACK_DD_EN_SHIFT              4
17441 #define SIM_ENABLE_ESTOP_EN_MASK                 0x20u
17442 #define SIM_ENABLE_ESTOP_EN_SHIFT                5
17443 #define SIM_ENABLE_ESTOP_EXE_MASK                0x40u
17444 #define SIM_ENABLE_ESTOP_EXE_SHIFT               6
17445 #define SIM_ENABLE_RXCL_MASK                     0x80u
17446 #define SIM_ENABLE_RXCL_SHIFT                    7
17447 /* XMT_STATUS Bit Fields */
17448 #define SIM_XMT_STATUS_XTE_MASK                  0x1u
17449 #define SIM_XMT_STATUS_XTE_SHIFT                 0
17450 #define SIM_XMT_STATUS_TFE_MASK                  0x8u
17451 #define SIM_XMT_STATUS_TFE_SHIFT                 3
17452 #define SIM_XMT_STATUS_ETC_MASK                  0x10u
17453 #define SIM_XMT_STATUS_ETC_SHIFT                 4
17454 #define SIM_XMT_STATUS_TC_MASK                   0x20u
17455 #define SIM_XMT_STATUS_TC_SHIFT                  5
17456 #define SIM_XMT_STATUS_TFO_MASK                  0x40u
17457 #define SIM_XMT_STATUS_TFO_SHIFT                 6
17458 #define SIM_XMT_STATUS_TDTF_MASK                 0x80u
17459 #define SIM_XMT_STATUS_TDTF_SHIFT                7
17460 #define SIM_XMT_STATUS_GPCNT_MASK                0x100u
17461 #define SIM_XMT_STATUS_GPCNT_SHIFT               8
17462 /* RCV_STATUS Bit Fields */
17463 #define SIM_RCV_STATUS_OEF_MASK                  0x1u
17464 #define SIM_RCV_STATUS_OEF_SHIFT                 0
17465 #define SIM_RCV_STATUS_RFE_MASK                  0x2u
17466 #define SIM_RCV_STATUS_RFE_SHIFT                 1
17467 #define SIM_RCV_STATUS_RFD_MASK                  0x10u
17468 #define SIM_RCV_STATUS_RFD_SHIFT                 4
17469 #define SIM_RCV_STATUS_RDRF_MASK                 0x20u
17470 #define SIM_RCV_STATUS_RDRF_SHIFT                5
17471 #define SIM_RCV_STATUS_LRCOK_MASK                0x40u
17472 #define SIM_RCV_STATUS_LRCOK_SHIFT               6
17473 #define SIM_RCV_STATUS_CRCOK_MASK                0x80u
17474 #define SIM_RCV_STATUS_CRCOK_SHIFT               7
17475 #define SIM_RCV_STATUS_CWT_MASK                  0x100u
17476 #define SIM_RCV_STATUS_CWT_SHIFT                 8
17477 #define SIM_RCV_STATUS_RTE_MASK                  0x200u
17478 #define SIM_RCV_STATUS_RTE_SHIFT                 9
17479 #define SIM_RCV_STATUS_BWT_MASK                  0x400u
17480 #define SIM_RCV_STATUS_BWT_SHIFT                 10
17481 #define SIM_RCV_STATUS_BGT_MASK                  0x800u
17482 #define SIM_RCV_STATUS_BGT_SHIFT                 11
17483 /* INT_MASK Bit Fields */
17484 #define SIM_INT_MASK_RIM_MASK                    0x1u
17485 #define SIM_INT_MASK_RIM_SHIFT                   0
17486 #define SIM_INT_MASK_TCIM_MASK                   0x2u
17487 #define SIM_INT_MASK_TCIM_SHIFT                  1
17488 #define SIM_INT_MASK_OIM_MASK                    0x4u
17489 #define SIM_INT_MASK_OIM_SHIFT                   2
17490 #define SIM_INT_MASK_ETCIM_MASK                  0x8u
17491 #define SIM_INT_MASK_ETCIM_SHIFT                 3
17492 #define SIM_INT_MASK_TFEIM_MASK                  0x10u
17493 #define SIM_INT_MASK_TFEIM_SHIFT                 4
17494 #define SIM_INT_MASK_XTM_MASK                    0x20u
17495 #define SIM_INT_MASK_XTM_SHIFT                   5
17496 #define SIM_INT_MASK_TFOM_MASK                   0x40u
17497 #define SIM_INT_MASK_TFOM_SHIFT                  6
17498 #define SIM_INT_MASK_TDTFM_MASK                  0x80u
17499 #define SIM_INT_MASK_TDTFM_SHIFT                 7
17500 #define SIM_INT_MASK_GPCNTM_MASK                 0x100u
17501 #define SIM_INT_MASK_GPCNTM_SHIFT                8
17502 #define SIM_INT_MASK_CWTM_MASK                   0x200u
17503 #define SIM_INT_MASK_CWTM_SHIFT                  9
17504 #define SIM_INT_MASK_RTM_MASK                    0x400u
17505 #define SIM_INT_MASK_RTM_SHIFT                   10
17506 #define SIM_INT_MASK_BWTM_MASK                   0x800u
17507 #define SIM_INT_MASK_BWTM_SHIFT                  11
17508 #define SIM_INT_MASK_BGTM_MASK                   0x1000u
17509 #define SIM_INT_MASK_BGTM_SHIFT                  12
17510 #define SIM_INT_MASK_RFEM_MASK                   0x2000u
17511 #define SIM_INT_MASK_RFEM_SHIFT                  13
17512 /* PORT0_DETECT Bit Fields */
17513 #define SIM_PORT0_DETECT_SDIM0_MASK              0x1u
17514 #define SIM_PORT0_DETECT_SDIM0_SHIFT             0
17515 #define SIM_PORT0_DETECT_SDI0_MASK               0x2u
17516 #define SIM_PORT0_DETECT_SDI0_SHIFT              1
17517 #define SIM_PORT0_DETECT_SPDP0_MASK              0x4u
17518 #define SIM_PORT0_DETECT_SPDP0_SHIFT             2
17519 #define SIM_PORT0_DETECT_SPDS0_MASK              0x8u
17520 #define SIM_PORT0_DETECT_SPDS0_SHIFT             3
17521 /* DATA_FORMAT Bit Fields */
17522 #define SIM_DATA_FORMAT_IC_MASK                  0x1u
17523 #define SIM_DATA_FORMAT_IC_SHIFT                 0
17524 /* XMT_THRESHOLD Bit Fields */
17525 #define SIM_XMT_THRESHOLD_TDT_MASK               0xFu
17526 #define SIM_XMT_THRESHOLD_TDT_SHIFT              0
17527 #define SIM_XMT_THRESHOLD_TDT(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_XMT_THRESHOLD_TDT_SHIFT))&SIM_XMT_THRESHOLD_TDT_MASK)
17528 #define SIM_XMT_THRESHOLD_XTH_MASK               0xF0u
17529 #define SIM_XMT_THRESHOLD_XTH_SHIFT              4
17530 #define SIM_XMT_THRESHOLD_XTH(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_XMT_THRESHOLD_XTH_SHIFT))&SIM_XMT_THRESHOLD_XTH_MASK)
17531 /* GUARD_CNTL Bit Fields */
17532 #define SIM_GUARD_CNTL_GETU_MASK                 0xFFu
17533 #define SIM_GUARD_CNTL_GETU_SHIFT                0
17534 #define SIM_GUARD_CNTL_GETU(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_GUARD_CNTL_GETU_SHIFT))&SIM_GUARD_CNTL_GETU_MASK)
17535 #define SIM_GUARD_CNTL_RCVR11_MASK               0x100u
17536 #define SIM_GUARD_CNTL_RCVR11_SHIFT              8
17537 /* OD_CONFIG Bit Fields */
17538 #define SIM_OD_CONFIG_OD_P0_MASK                 0x1u
17539 #define SIM_OD_CONFIG_OD_P0_SHIFT                0
17540 #define SIM_OD_CONFIG_OD_P1_MASK                 0x2u
17541 #define SIM_OD_CONFIG_OD_P1_SHIFT                1
17542 /* RESET_CNTL Bit Fields */
17543 #define SIM_RESET_CNTL_FLUSH_RCV_MASK            0x1u
17544 #define SIM_RESET_CNTL_FLUSH_RCV_SHIFT           0
17545 #define SIM_RESET_CNTL_FLUSH_XMT_MASK            0x2u
17546 #define SIM_RESET_CNTL_FLUSH_XMT_SHIFT           1
17547 #define SIM_RESET_CNTL_SOFT_RST_MASK             0x4u
17548 #define SIM_RESET_CNTL_SOFT_RST_SHIFT            2
17549 #define SIM_RESET_CNTL_KILL_CLOCK_MASK           0x8u
17550 #define SIM_RESET_CNTL_KILL_CLOCK_SHIFT          3
17551 #define SIM_RESET_CNTL_DOZE_MASK                 0x10u
17552 #define SIM_RESET_CNTL_DOZE_SHIFT                4
17553 #define SIM_RESET_CNTL_STOP_MASK                 0x20u
17554 #define SIM_RESET_CNTL_STOP_SHIFT                5
17555 /* CHAR_WAIT Bit Fields */
17556 #define SIM_CHAR_WAIT_CWT_MASK                   0xFFFFu
17557 #define SIM_CHAR_WAIT_CWT_SHIFT                  0
17558 #define SIM_CHAR_WAIT_CWT(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_CHAR_WAIT_CWT_SHIFT))&SIM_CHAR_WAIT_CWT_MASK)
17559 /* GPCNT Bit Fields */
17560 #define SIM_GPCNT_GPCNT_MASK                     0xFFFFu
17561 #define SIM_GPCNT_GPCNT_SHIFT                    0
17562 #define SIM_GPCNT_GPCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_GPCNT_GPCNT_SHIFT))&SIM_GPCNT_GPCNT_MASK)
17563 /* DIVISOR Bit Fields */
17564 #define SIM_DIVISOR_DIVISOR_MASK                 0xFFu
17565 #define SIM_DIVISOR_DIVISOR_SHIFT                0
17566 #define SIM_DIVISOR_DIVISOR(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_DIVISOR_DIVISOR_SHIFT))&SIM_DIVISOR_DIVISOR_MASK)
17567 /* BWT Bit Fields */
17568 #define SIM_BWT_BWT_MASK                         0xFFFFu
17569 #define SIM_BWT_BWT_SHIFT                        0
17570 #define SIM_BWT_BWT(x)                           (((uint32_t)(((uint32_t)(x))<<SIM_BWT_BWT_SHIFT))&SIM_BWT_BWT_MASK)
17571 /* BGT Bit Fields */
17572 #define SIM_BGT_BGT_MASK                         0xFFFFu
17573 #define SIM_BGT_BGT_SHIFT                        0
17574 #define SIM_BGT_BGT(x)                           (((uint32_t)(((uint32_t)(x))<<SIM_BGT_BGT_SHIFT))&SIM_BGT_BGT_MASK)
17575 /* BWT_H Bit Fields */
17576 #define SIM_BWT_H_BWT_H_MASK                     0xFFFFu
17577 #define SIM_BWT_H_BWT_H_SHIFT                    0
17578 #define SIM_BWT_H_BWT_H(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_BWT_H_BWT_H_SHIFT))&SIM_BWT_H_BWT_H_MASK)
17579 /* XMT_FIFO_STAT Bit Fields */
17580 #define SIM_XMT_FIFO_STAT_XMT_RPTR_MASK          0xFu
17581 #define SIM_XMT_FIFO_STAT_XMT_RPTR_SHIFT         0
17582 #define SIM_XMT_FIFO_STAT_XMT_RPTR(x)            (((uint32_t)(((uint32_t)(x))<<SIM_XMT_FIFO_STAT_XMT_RPTR_SHIFT))&SIM_XMT_FIFO_STAT_XMT_RPTR_MASK)
17583 #define SIM_XMT_FIFO_STAT_XMT_WPTR_MASK          0xF0u
17584 #define SIM_XMT_FIFO_STAT_XMT_WPTR_SHIFT         4
17585 #define SIM_XMT_FIFO_STAT_XMT_WPTR(x)            (((uint32_t)(((uint32_t)(x))<<SIM_XMT_FIFO_STAT_XMT_WPTR_SHIFT))&SIM_XMT_FIFO_STAT_XMT_WPTR_MASK)
17586 #define SIM_XMT_FIFO_STAT_XMT_CNT_MASK           0xF00u
17587 #define SIM_XMT_FIFO_STAT_XMT_CNT_SHIFT          8
17588 #define SIM_XMT_FIFO_STAT_XMT_CNT(x)             (((uint32_t)(((uint32_t)(x))<<SIM_XMT_FIFO_STAT_XMT_CNT_SHIFT))&SIM_XMT_FIFO_STAT_XMT_CNT_MASK)
17589 /* RCV_FIFO_CNT Bit Fields */
17590 #define SIM_RCV_FIFO_CNT_RCV_CNT_MASK            0x1FFu
17591 #define SIM_RCV_FIFO_CNT_RCV_CNT_SHIFT           0
17592 #define SIM_RCV_FIFO_CNT_RCV_CNT(x)              (((uint32_t)(((uint32_t)(x))<<SIM_RCV_FIFO_CNT_RCV_CNT_SHIFT))&SIM_RCV_FIFO_CNT_RCV_CNT_MASK)
17593 /* RCV_FIFO_WPTR Bit Fields */
17594 #define SIM_RCV_FIFO_WPTR_RCV_WPTR_MASK          0x1FFu
17595 #define SIM_RCV_FIFO_WPTR_RCV_WPTR_SHIFT         0
17596 #define SIM_RCV_FIFO_WPTR_RCV_WPTR(x)            (((uint32_t)(((uint32_t)(x))<<SIM_RCV_FIFO_WPTR_RCV_WPTR_SHIFT))&SIM_RCV_FIFO_WPTR_RCV_WPTR_MASK)
17597 /* RCV_FIFO_RPTR Bit Fields */
17598 #define SIM_RCV_FIFO_RPTR_RCV_RPTR_MASK          0x1FFu
17599 #define SIM_RCV_FIFO_RPTR_RCV_RPTR_SHIFT         0
17600 #define SIM_RCV_FIFO_RPTR_RCV_RPTR(x)            (((uint32_t)(((uint32_t)(x))<<SIM_RCV_FIFO_RPTR_RCV_RPTR_SHIFT))&SIM_RCV_FIFO_RPTR_RCV_RPTR_MASK)
17601 
17602 /*!
17603  * @}
17604  */ /* end of group SIM_Register_Masks */
17605 
17606 /* SIM - Peripheral instance base addresses */
17607 /** Peripheral SIM1 base address */
17608 #define SIM1_BASE                                (0x30B90000u)
17609 /** Peripheral SIM1 base pointer */
17610 #define SIM1                                     ((SIM_Type *)SIM1_BASE)
17611 #define SIM1_BASE_PTR                            (SIM1)
17612 /** Peripheral SIM2 base address */
17613 #define SIM2_BASE                                (0x30BA0000u)
17614 /** Peripheral SIM2 base pointer */
17615 #define SIM2                                     ((SIM_Type *)SIM2_BASE)
17616 #define SIM2_BASE_PTR                            (SIM2)
17617 /** Array initializer of SIM peripheral base addresses */
17618 #define SIM_BASE_ADDRS                           { SIM1_BASE, SIM2_BASE }
17619 /** Array initializer of SIM peripheral base pointers */
17620 #define SIM_BASE_PTRS                            { SIM1, SIM2 }
17621 /** Interrupt vectors for the SIM peripheral type */
17622 #define SCTR_IRQS                                { SCTR1_IRQn, SCTR2_IRQn }
17623 #define SIM_IRQS                                 { SIM1_IRQn, SIM2_IRQn }
17624 /* ----------------------------------------------------------------------------
17625    -- SIM - Register accessor macros
17626    ---------------------------------------------------------------------------- */
17627 
17628 /*!
17629  * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
17630  * @{
17631  */
17632 
17633 
17634 /* SIM - Register instance definitions */
17635 /* SIM1 */
17636 #define SIM1_PORT1_CNTL                          SIM_PORT1_CNTL_REG(SIM1_BASE_PTR)
17637 #define SIM1_SETUP                               SIM_SETUP_REG(SIM1_BASE_PTR)
17638 #define SIM1_PORT1_DETECT                        SIM_PORT1_DETECT_REG(SIM1_BASE_PTR)
17639 #define SIM1_XMT_BUF                             SIM_XMT_BUF_REG(SIM1_BASE_PTR)
17640 #define SIM1_RCV_BUF                             SIM_RCV_BUF_REG(SIM1_BASE_PTR)
17641 #define SIM1_PORT0_CNTL                          SIM_PORT0_CNTL_REG(SIM1_BASE_PTR)
17642 #define SIM1_CNTL                                SIM_CNTL_REG(SIM1_BASE_PTR)
17643 #define SIM1_CLK_PRESCALER                       SIM_CLK_PRESCALER_REG(SIM1_BASE_PTR)
17644 #define SIM1_RCV_THRESHOLD                       SIM_RCV_THRESHOLD_REG(SIM1_BASE_PTR)
17645 #define SIM1_ENABLE                              SIM_ENABLE_REG(SIM1_BASE_PTR)
17646 #define SIM1_XMT_STATUS                          SIM_XMT_STATUS_REG(SIM1_BASE_PTR)
17647 #define SIM1_RCV_STATUS                          SIM_RCV_STATUS_REG(SIM1_BASE_PTR)
17648 #define SIM1_INT_MASK                            SIM_INT_MASK_REG(SIM1_BASE_PTR)
17649 #define SIM1_PORT0_DETECT                        SIM_PORT0_DETECT_REG(SIM1_BASE_PTR)
17650 #define SIM1_DATA_FORMAT                         SIM_DATA_FORMAT_REG(SIM1_BASE_PTR)
17651 #define SIM1_XMT_THRESHOLD                       SIM_XMT_THRESHOLD_REG(SIM1_BASE_PTR)
17652 #define SIM1_GUARD_CNTL                          SIM_GUARD_CNTL_REG(SIM1_BASE_PTR)
17653 #define SIM1_OD_CONFIG                           SIM_OD_CONFIG_REG(SIM1_BASE_PTR)
17654 #define SIM1_RESET_CNTL                          SIM_RESET_CNTL_REG(SIM1_BASE_PTR)
17655 #define SIM1_CHAR_WAIT                           SIM_CHAR_WAIT_REG(SIM1_BASE_PTR)
17656 #define SIM1_GPCNT                               SIM_GPCNT_REG(SIM1_BASE_PTR)
17657 #define SIM1_DIVISOR                             SIM_DIVISOR_REG(SIM1_BASE_PTR)
17658 #define SIM1_BWT                                 SIM_BWT_REG(SIM1_BASE_PTR)
17659 #define SIM1_BGT                                 SIM_BGT_REG(SIM1_BASE_PTR)
17660 #define SIM1_BWT_H                               SIM_BWT_H_REG(SIM1_BASE_PTR)
17661 #define SIM1_XMT_FIFO_STAT                       SIM_XMT_FIFO_STAT_REG(SIM1_BASE_PTR)
17662 #define SIM1_RCV_FIFO_CNT                        SIM_RCV_FIFO_CNT_REG(SIM1_BASE_PTR)
17663 #define SIM1_RCV_FIFO_WPTR                       SIM_RCV_FIFO_WPTR_REG(SIM1_BASE_PTR)
17664 #define SIM1_RCV_FIFO_RPTR                       SIM_RCV_FIFO_RPTR_REG(SIM1_BASE_PTR)
17665 /* SIM2 */
17666 #define SIM2_PORT1_CNTL                          SIM_PORT1_CNTL_REG(SIM2_BASE_PTR)
17667 #define SIM2_SETUP                               SIM_SETUP_REG(SIM2_BASE_PTR)
17668 #define SIM2_PORT1_DETECT                        SIM_PORT1_DETECT_REG(SIM2_BASE_PTR)
17669 #define SIM2_XMT_BUF                             SIM_XMT_BUF_REG(SIM2_BASE_PTR)
17670 #define SIM2_RCV_BUF                             SIM_RCV_BUF_REG(SIM2_BASE_PTR)
17671 #define SIM2_PORT0_CNTL                          SIM_PORT0_CNTL_REG(SIM2_BASE_PTR)
17672 #define SIM2_CNTL                                SIM_CNTL_REG(SIM2_BASE_PTR)
17673 #define SIM2_CLK_PRESCALER                       SIM_CLK_PRESCALER_REG(SIM2_BASE_PTR)
17674 #define SIM2_RCV_THRESHOLD                       SIM_RCV_THRESHOLD_REG(SIM2_BASE_PTR)
17675 #define SIM2_ENABLE                              SIM_ENABLE_REG(SIM2_BASE_PTR)
17676 #define SIM2_XMT_STATUS                          SIM_XMT_STATUS_REG(SIM2_BASE_PTR)
17677 #define SIM2_RCV_STATUS                          SIM_RCV_STATUS_REG(SIM2_BASE_PTR)
17678 #define SIM2_INT_MASK                            SIM_INT_MASK_REG(SIM2_BASE_PTR)
17679 #define SIM2_PORT0_DETECT                        SIM_PORT0_DETECT_REG(SIM2_BASE_PTR)
17680 #define SIM2_DATA_FORMAT                         SIM_DATA_FORMAT_REG(SIM2_BASE_PTR)
17681 #define SIM2_XMT_THRESHOLD                       SIM_XMT_THRESHOLD_REG(SIM2_BASE_PTR)
17682 #define SIM2_GUARD_CNTL                          SIM_GUARD_CNTL_REG(SIM2_BASE_PTR)
17683 #define SIM2_OD_CONFIG                           SIM_OD_CONFIG_REG(SIM2_BASE_PTR)
17684 #define SIM2_RESET_CNTL                          SIM_RESET_CNTL_REG(SIM2_BASE_PTR)
17685 #define SIM2_CHAR_WAIT                           SIM_CHAR_WAIT_REG(SIM2_BASE_PTR)
17686 #define SIM2_GPCNT                               SIM_GPCNT_REG(SIM2_BASE_PTR)
17687 #define SIM2_DIVISOR                             SIM_DIVISOR_REG(SIM2_BASE_PTR)
17688 #define SIM2_BWT                                 SIM_BWT_REG(SIM2_BASE_PTR)
17689 #define SIM2_BGT                                 SIM_BGT_REG(SIM2_BASE_PTR)
17690 #define SIM2_BWT_H                               SIM_BWT_H_REG(SIM2_BASE_PTR)
17691 #define SIM2_XMT_FIFO_STAT                       SIM_XMT_FIFO_STAT_REG(SIM2_BASE_PTR)
17692 #define SIM2_RCV_FIFO_CNT                        SIM_RCV_FIFO_CNT_REG(SIM2_BASE_PTR)
17693 #define SIM2_RCV_FIFO_WPTR                       SIM_RCV_FIFO_WPTR_REG(SIM2_BASE_PTR)
17694 #define SIM2_RCV_FIFO_RPTR                       SIM_RCV_FIFO_RPTR_REG(SIM2_BASE_PTR)
17695 /*!
17696  * @}
17697  */ /* end of group SIM_Register_Accessor_Macros */
17698 
17699 
17700 /*!
17701  * @}
17702  */ /* end of group SIM_Peripheral */
17703 
17704 /* ----------------------------------------------------------------------------
17705    -- FTM Peripheral Access Layer
17706    ---------------------------------------------------------------------------- */
17707 
17708 /*!
17709  * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
17710  * @{
17711  */
17712 
17713 /** FTM - Register Layout Typedef */
17714 typedef struct {
17715   __IO  uint32_t SC;                                     /**< Status And Control, offset: 0x0 */
17716   __IO  uint32_t CNT;                                    /**< Counter, offset: 0x4 */
17717   __IO  uint32_t MOD;                                    /**< Modulo, offset: 0x8 */
17718   struct {                                         /* offset: 0xC, array step: 0x8 */
17719   __IO    uint32_t CSC;                                    /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
17720   __IO    uint32_t CV;                                     /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
17721  } C[8];
17722   __IO  uint32_t CNTIN;                                  /**< Counter Initial Value, offset: 0x4C */
17723   __IO  uint32_t STATUS;                                 /**< Capture And Compare Status, offset: 0x50 */
17724   __IO  uint32_t MODE;                                   /**< Features Mode Selection, offset: 0x54 */
17725   __IO  uint32_t SYNC;                                   /**< Synchronization, offset: 0x58 */
17726   __IO  uint32_t OUTINIT;                                /**< Initial State For Channels Output, offset: 0x5C */
17727   __IO  uint32_t OUTMASK;                                /**< Output Mask, offset: 0x60 */
17728   __IO  uint32_t COMBINE;                                /**< Function For Linked Channels, offset: 0x64 */
17729   __IO  uint32_t DEADTIME;                               /**< Deadtime Insertion Control, offset: 0x68 */
17730   __IO  uint32_t EXTTRIG;                                /**< FTM External Trigger, offset: 0x6C */
17731   __IO  uint32_t POL;                                    /**< Channels Polarity, offset: 0x70 */
17732   uint8_t RESERVED_0[4];
17733   __IO  uint32_t FILTER;                                 /**< Input Capture Filter Control, offset: 0x78 */
17734   uint8_t RESERVED_1[4];
17735   __IO  uint32_t QDCTRL;                                 /**< Quadrature Decoder Control And Status, offset: 0x80 */
17736   __IO  uint32_t CONF;                                   /**< Configuration, offset: 0x84 */
17737   uint8_t RESERVED_2[4];
17738   __IO  uint32_t SYNCONF;                                /**< Synchronization Configuration, offset: 0x8C */
17739   __IO  uint32_t INVCTRL;                                /**< FTM Inverting Control, offset: 0x90 */
17740   __IO  uint32_t SWOCTRL;                                /**< FTM Software Output Control, offset: 0x94 */
17741   __IO  uint32_t PWMLOAD;                                /**< FTM PWM Load, offset: 0x98 */
17742 } FTM_Type, *FTM_MemMapPtr;
17743 /* ----------------------------------------------------------------------------
17744    -- FTM - Register accessor macros
17745    ---------------------------------------------------------------------------- */
17746 
17747 /*!
17748  * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
17749  * @{
17750  */
17751 
17752 
17753 /* FTM - Register accessors */
17754 #define FTM_SC_REG(base)                         ((base)->SC)
17755 #define FTM_CNT_REG(base)                        ((base)->CNT)
17756 #define FTM_MOD_REG(base)                        ((base)->MOD)
17757 #define FTM_CSC_REG(base,index)                  ((base)->C[index].CSC)
17758 #define FTM_CV_REG(base,index)                   ((base)->C[index].CV)
17759 #define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
17760 #define FTM_STATUS_REG(base)                     ((base)->STATUS)
17761 #define FTM_MODE_REG(base)                       ((base)->MODE)
17762 #define FTM_SYNC_REG(base)                       ((base)->SYNC)
17763 #define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
17764 #define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
17765 #define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
17766 #define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
17767 #define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
17768 #define FTM_POL_REG(base)                        ((base)->POL)
17769 #define FTM_FILTER_REG(base)                     ((base)->FILTER)
17770 #define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
17771 #define FTM_CONF_REG(base)                       ((base)->CONF)
17772 #define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
17773 #define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
17774 #define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
17775 #define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
17776 
17777 /*!
17778  * @}
17779  */ /* end of group FTM_Register_Accessor_Macros */
17780 /* ----------------------------------------------------------------------------
17781    -- FTM Register Masks
17782    ---------------------------------------------------------------------------- */
17783 
17784 /*!
17785  * @addtogroup FTM_Register_Masks FTM Register Masks
17786  * @{
17787  */
17788 
17789 /* SC Bit Fields */
17790 #define FTM_SC_PS_MASK                           0x7u
17791 #define FTM_SC_PS_SHIFT                          0
17792 #define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
17793 #define FTM_SC_CLKS_MASK                         0x18u
17794 #define FTM_SC_CLKS_SHIFT                        3
17795 #define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
17796 #define FTM_SC_CPWMS_MASK                        0x20u
17797 #define FTM_SC_CPWMS_SHIFT                       5
17798 #define FTM_SC_TOIE_MASK                         0x40u
17799 #define FTM_SC_TOIE_SHIFT                        6
17800 #define FTM_SC_TOF_MASK                          0x80u
17801 #define FTM_SC_TOF_SHIFT                         7
17802 /* CNT Bit Fields */
17803 #define FTM_CNT_COUNT_MASK                       0xFFFFu
17804 #define FTM_CNT_COUNT_SHIFT                      0
17805 #define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
17806 /* MOD Bit Fields */
17807 #define FTM_MOD_MOD_MASK                         0xFFFFu
17808 #define FTM_MOD_MOD_SHIFT                        0
17809 #define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
17810 /* CSC Bit Fields */
17811 #define FTM_CSC_DMA_MASK                         0x1u
17812 #define FTM_CSC_DMA_SHIFT                        0
17813 #define FTM_CSC_ICRST_MASK                       0x2u
17814 #define FTM_CSC_ICRST_SHIFT                      1
17815 #define FTM_CSC_ELSA_MASK                        0x4u
17816 #define FTM_CSC_ELSA_SHIFT                       2
17817 #define FTM_CSC_ELSB_MASK                        0x8u
17818 #define FTM_CSC_ELSB_SHIFT                       3
17819 #define FTM_CSC_MSA_MASK                         0x10u
17820 #define FTM_CSC_MSA_SHIFT                        4
17821 #define FTM_CSC_MSB_MASK                         0x20u
17822 #define FTM_CSC_MSB_SHIFT                        5
17823 #define FTM_CSC_CHIE_MASK                        0x40u
17824 #define FTM_CSC_CHIE_SHIFT                       6
17825 #define FTM_CSC_CHF_MASK                         0x80u
17826 #define FTM_CSC_CHF_SHIFT                        7
17827 /* CV Bit Fields */
17828 #define FTM_CV_VAL_MASK                          0xFFFFu
17829 #define FTM_CV_VAL_SHIFT                         0
17830 #define FTM_CV_VAL(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_CV_VAL_SHIFT))&FTM_CV_VAL_MASK)
17831 /* CNTIN Bit Fields */
17832 #define FTM_CNTIN_INIT_MASK                      0xFFFFu
17833 #define FTM_CNTIN_INIT_SHIFT                     0
17834 #define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
17835 /* STATUS Bit Fields */
17836 #define FTM_STATUS_CH0F_MASK                     0x1u
17837 #define FTM_STATUS_CH0F_SHIFT                    0
17838 #define FTM_STATUS_CH1F_MASK                     0x2u
17839 #define FTM_STATUS_CH1F_SHIFT                    1
17840 #define FTM_STATUS_CH2F_MASK                     0x4u
17841 #define FTM_STATUS_CH2F_SHIFT                    2
17842 #define FTM_STATUS_CH3F_MASK                     0x8u
17843 #define FTM_STATUS_CH3F_SHIFT                    3
17844 #define FTM_STATUS_CH4F_MASK                     0x10u
17845 #define FTM_STATUS_CH4F_SHIFT                    4
17846 #define FTM_STATUS_CH5F_MASK                     0x20u
17847 #define FTM_STATUS_CH5F_SHIFT                    5
17848 #define FTM_STATUS_CH6F_MASK                     0x40u
17849 #define FTM_STATUS_CH6F_SHIFT                    6
17850 #define FTM_STATUS_CH7F_MASK                     0x80u
17851 #define FTM_STATUS_CH7F_SHIFT                    7
17852 /* MODE Bit Fields */
17853 #define FTM_MODE_FTMEN_MASK                      0x1u
17854 #define FTM_MODE_FTMEN_SHIFT                     0
17855 #define FTM_MODE_INIT_MASK                       0x2u
17856 #define FTM_MODE_INIT_SHIFT                      1
17857 #define FTM_MODE_WPDIS_MASK                      0x4u
17858 #define FTM_MODE_WPDIS_SHIFT                     2
17859 #define FTM_MODE_PWMSYNC_MASK                    0x8u
17860 #define FTM_MODE_PWMSYNC_SHIFT                   3
17861 #define FTM_MODE_CAPTEST_MASK                    0x10u
17862 #define FTM_MODE_CAPTEST_SHIFT                   4
17863 /* SYNC Bit Fields */
17864 #define FTM_SYNC_CNTMIN_MASK                     0x1u
17865 #define FTM_SYNC_CNTMIN_SHIFT                    0
17866 #define FTM_SYNC_CNTMAX_MASK                     0x2u
17867 #define FTM_SYNC_CNTMAX_SHIFT                    1
17868 #define FTM_SYNC_REINIT_MASK                     0x4u
17869 #define FTM_SYNC_REINIT_SHIFT                    2
17870 #define FTM_SYNC_SYNCHOM_MASK                    0x8u
17871 #define FTM_SYNC_SYNCHOM_SHIFT                   3
17872 #define FTM_SYNC_TRIG0_MASK                      0x10u
17873 #define FTM_SYNC_TRIG0_SHIFT                     4
17874 #define FTM_SYNC_TRIG1_MASK                      0x20u
17875 #define FTM_SYNC_TRIG1_SHIFT                     5
17876 #define FTM_SYNC_TRIG2_MASK                      0x40u
17877 #define FTM_SYNC_TRIG2_SHIFT                     6
17878 #define FTM_SYNC_SWSYNC_MASK                     0x80u
17879 #define FTM_SYNC_SWSYNC_SHIFT                    7
17880 /* OUTINIT Bit Fields */
17881 #define FTM_OUTINIT_CH0OI_MASK                   0x1u
17882 #define FTM_OUTINIT_CH0OI_SHIFT                  0
17883 #define FTM_OUTINIT_CH1OI_MASK                   0x2u
17884 #define FTM_OUTINIT_CH1OI_SHIFT                  1
17885 #define FTM_OUTINIT_CH2OI_MASK                   0x4u
17886 #define FTM_OUTINIT_CH2OI_SHIFT                  2
17887 #define FTM_OUTINIT_CH3OI_MASK                   0x8u
17888 #define FTM_OUTINIT_CH3OI_SHIFT                  3
17889 #define FTM_OUTINIT_CH4OI_MASK                   0x10u
17890 #define FTM_OUTINIT_CH4OI_SHIFT                  4
17891 #define FTM_OUTINIT_CH5OI_MASK                   0x20u
17892 #define FTM_OUTINIT_CH5OI_SHIFT                  5
17893 #define FTM_OUTINIT_CH6OI_MASK                   0x40u
17894 #define FTM_OUTINIT_CH6OI_SHIFT                  6
17895 #define FTM_OUTINIT_CH7OI_MASK                   0x80u
17896 #define FTM_OUTINIT_CH7OI_SHIFT                  7
17897 /* OUTMASK Bit Fields */
17898 #define FTM_OUTMASK_CH0OM_MASK                   0x1u
17899 #define FTM_OUTMASK_CH0OM_SHIFT                  0
17900 #define FTM_OUTMASK_CH1OM_MASK                   0x2u
17901 #define FTM_OUTMASK_CH1OM_SHIFT                  1
17902 #define FTM_OUTMASK_CH2OM_MASK                   0x4u
17903 #define FTM_OUTMASK_CH2OM_SHIFT                  2
17904 #define FTM_OUTMASK_CH3OM_MASK                   0x8u
17905 #define FTM_OUTMASK_CH3OM_SHIFT                  3
17906 #define FTM_OUTMASK_CH4OM_MASK                   0x10u
17907 #define FTM_OUTMASK_CH4OM_SHIFT                  4
17908 #define FTM_OUTMASK_CH5OM_MASK                   0x20u
17909 #define FTM_OUTMASK_CH5OM_SHIFT                  5
17910 #define FTM_OUTMASK_CH6OM_MASK                   0x40u
17911 #define FTM_OUTMASK_CH6OM_SHIFT                  6
17912 #define FTM_OUTMASK_CH7OM_MASK                   0x80u
17913 #define FTM_OUTMASK_CH7OM_SHIFT                  7
17914 /* COMBINE Bit Fields */
17915 #define FTM_COMBINE_COMBINE0_MASK                0x1u
17916 #define FTM_COMBINE_COMBINE0_SHIFT               0
17917 #define FTM_COMBINE_COMP0_MASK                   0x2u
17918 #define FTM_COMBINE_COMP0_SHIFT                  1
17919 #define FTM_COMBINE_DECAPEN0_MASK                0x4u
17920 #define FTM_COMBINE_DECAPEN0_SHIFT               2
17921 #define FTM_COMBINE_DECAP0_MASK                  0x8u
17922 #define FTM_COMBINE_DECAP0_SHIFT                 3
17923 #define FTM_COMBINE_DTEN0_MASK                   0x10u
17924 #define FTM_COMBINE_DTEN0_SHIFT                  4
17925 #define FTM_COMBINE_SYNCEN0_MASK                 0x20u
17926 #define FTM_COMBINE_SYNCEN0_SHIFT                5
17927 #define FTM_COMBINE_COMBINE1_MASK                0x100u
17928 #define FTM_COMBINE_COMBINE1_SHIFT               8
17929 #define FTM_COMBINE_COMP1_MASK                   0x200u
17930 #define FTM_COMBINE_COMP1_SHIFT                  9
17931 #define FTM_COMBINE_DECAPEN1_MASK                0x400u
17932 #define FTM_COMBINE_DECAPEN1_SHIFT               10
17933 #define FTM_COMBINE_DECAP1_MASK                  0x800u
17934 #define FTM_COMBINE_DECAP1_SHIFT                 11
17935 #define FTM_COMBINE_DTEN1_MASK                   0x1000u
17936 #define FTM_COMBINE_DTEN1_SHIFT                  12
17937 #define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
17938 #define FTM_COMBINE_SYNCEN1_SHIFT                13
17939 #define FTM_COMBINE_COMBINE2_MASK                0x10000u
17940 #define FTM_COMBINE_COMBINE2_SHIFT               16
17941 #define FTM_COMBINE_COMP2_MASK                   0x20000u
17942 #define FTM_COMBINE_COMP2_SHIFT                  17
17943 #define FTM_COMBINE_DECAPEN2_MASK                0x40000u
17944 #define FTM_COMBINE_DECAPEN2_SHIFT               18
17945 #define FTM_COMBINE_DECAP2_MASK                  0x80000u
17946 #define FTM_COMBINE_DECAP2_SHIFT                 19
17947 #define FTM_COMBINE_DTEN2_MASK                   0x100000u
17948 #define FTM_COMBINE_DTEN2_SHIFT                  20
17949 #define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
17950 #define FTM_COMBINE_SYNCEN2_SHIFT                21
17951 #define FTM_COMBINE_COMBINE3_MASK                0x1000000u
17952 #define FTM_COMBINE_COMBINE3_SHIFT               24
17953 #define FTM_COMBINE_COMP3_MASK                   0x2000000u
17954 #define FTM_COMBINE_COMP3_SHIFT                  25
17955 #define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
17956 #define FTM_COMBINE_DECAPEN3_SHIFT               26
17957 #define FTM_COMBINE_DECAP3_MASK                  0x8000000u
17958 #define FTM_COMBINE_DECAP3_SHIFT                 27
17959 #define FTM_COMBINE_DTEN3_MASK                   0x10000000u
17960 #define FTM_COMBINE_DTEN3_SHIFT                  28
17961 #define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
17962 #define FTM_COMBINE_SYNCEN3_SHIFT                29
17963 /* DEADTIME Bit Fields */
17964 #define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
17965 #define FTM_DEADTIME_DTVAL_SHIFT                 0
17966 #define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
17967 #define FTM_DEADTIME_DTPS_MASK                   0xC0u
17968 #define FTM_DEADTIME_DTPS_SHIFT                  6
17969 #define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
17970 /* EXTTRIG Bit Fields */
17971 #define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
17972 #define FTM_EXTTRIG_CH2TRIG_SHIFT                0
17973 #define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
17974 #define FTM_EXTTRIG_CH3TRIG_SHIFT                1
17975 #define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
17976 #define FTM_EXTTRIG_CH4TRIG_SHIFT                2
17977 #define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
17978 #define FTM_EXTTRIG_CH5TRIG_SHIFT                3
17979 #define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
17980 #define FTM_EXTTRIG_CH0TRIG_SHIFT                4
17981 #define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
17982 #define FTM_EXTTRIG_CH1TRIG_SHIFT                5
17983 #define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
17984 #define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
17985 #define FTM_EXTTRIG_TRIGF_MASK                   0x80u
17986 #define FTM_EXTTRIG_TRIGF_SHIFT                  7
17987 /* POL Bit Fields */
17988 #define FTM_POL_POL0_MASK                        0x1u
17989 #define FTM_POL_POL0_SHIFT                       0
17990 #define FTM_POL_POL1_MASK                        0x2u
17991 #define FTM_POL_POL1_SHIFT                       1
17992 #define FTM_POL_POL2_MASK                        0x4u
17993 #define FTM_POL_POL2_SHIFT                       2
17994 #define FTM_POL_POL3_MASK                        0x8u
17995 #define FTM_POL_POL3_SHIFT                       3
17996 #define FTM_POL_POL4_MASK                        0x10u
17997 #define FTM_POL_POL4_SHIFT                       4
17998 #define FTM_POL_POL5_MASK                        0x20u
17999 #define FTM_POL_POL5_SHIFT                       5
18000 #define FTM_POL_POL6_MASK                        0x40u
18001 #define FTM_POL_POL6_SHIFT                       6
18002 #define FTM_POL_POL7_MASK                        0x80u
18003 #define FTM_POL_POL7_SHIFT                       7
18004 /* FILTER Bit Fields */
18005 #define FTM_FILTER_CH0FVAL_MASK                  0xFu
18006 #define FTM_FILTER_CH0FVAL_SHIFT                 0
18007 #define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
18008 #define FTM_FILTER_CH1FVAL_MASK                  0xF0u
18009 #define FTM_FILTER_CH1FVAL_SHIFT                 4
18010 #define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
18011 #define FTM_FILTER_CH2FVAL_MASK                  0xF00u
18012 #define FTM_FILTER_CH2FVAL_SHIFT                 8
18013 #define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
18014 #define FTM_FILTER_CH3FVAL_MASK                  0xF000u
18015 #define FTM_FILTER_CH3FVAL_SHIFT                 12
18016 #define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
18017 /* QDCTRL Bit Fields */
18018 #define FTM_QDCTRL_QUADEN_MASK                   0x1u
18019 #define FTM_QDCTRL_QUADEN_SHIFT                  0
18020 #define FTM_QDCTRL_TOFDIR_MASK                   0x2u
18021 #define FTM_QDCTRL_TOFDIR_SHIFT                  1
18022 #define FTM_QDCTRL_QUADIR_MASK                   0x4u
18023 #define FTM_QDCTRL_QUADIR_SHIFT                  2
18024 #define FTM_QDCTRL_QUADMODE_MASK                 0x8u
18025 #define FTM_QDCTRL_QUADMODE_SHIFT                3
18026 #define FTM_QDCTRL_PHBPOL_MASK                   0x10u
18027 #define FTM_QDCTRL_PHBPOL_SHIFT                  4
18028 #define FTM_QDCTRL_PHAPOL_MASK                   0x20u
18029 #define FTM_QDCTRL_PHAPOL_SHIFT                  5
18030 #define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
18031 #define FTM_QDCTRL_PHBFLTREN_SHIFT               6
18032 #define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
18033 #define FTM_QDCTRL_PHAFLTREN_SHIFT               7
18034 /* CONF Bit Fields */
18035 #define FTM_CONF_NUMTOF_MASK                     0x1Fu
18036 #define FTM_CONF_NUMTOF_SHIFT                    0
18037 #define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
18038 #define FTM_CONF_BDMMODE_MASK                    0xC0u
18039 #define FTM_CONF_BDMMODE_SHIFT                   6
18040 #define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
18041 #define FTM_CONF_GTBEEN_MASK                     0x200u
18042 #define FTM_CONF_GTBEEN_SHIFT                    9
18043 #define FTM_CONF_GTBEOUT_MASK                    0x400u
18044 #define FTM_CONF_GTBEOUT_SHIFT                   10
18045 /* SYNCONF Bit Fields */
18046 #define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
18047 #define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
18048 #define FTM_SYNCONF_CNTINC_MASK                  0x4u
18049 #define FTM_SYNCONF_CNTINC_SHIFT                 2
18050 #define FTM_SYNCONF_INVC_MASK                    0x10u
18051 #define FTM_SYNCONF_INVC_SHIFT                   4
18052 #define FTM_SYNCONF_SWOC_MASK                    0x20u
18053 #define FTM_SYNCONF_SWOC_SHIFT                   5
18054 #define FTM_SYNCONF_SYNCMODE_MASK                0x80u
18055 #define FTM_SYNCONF_SYNCMODE_SHIFT               7
18056 #define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
18057 #define FTM_SYNCONF_SWRSTCNT_SHIFT               8
18058 #define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
18059 #define FTM_SYNCONF_SWWRBUF_SHIFT                9
18060 #define FTM_SYNCONF_SWOM_MASK                    0x400u
18061 #define FTM_SYNCONF_SWOM_SHIFT                   10
18062 #define FTM_SYNCONF_SWINVC_MASK                  0x800u
18063 #define FTM_SYNCONF_SWINVC_SHIFT                 11
18064 #define FTM_SYNCONF_SWSOC_MASK                   0x1000u
18065 #define FTM_SYNCONF_SWSOC_SHIFT                  12
18066 #define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
18067 #define FTM_SYNCONF_HWRSTCNT_SHIFT               16
18068 #define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
18069 #define FTM_SYNCONF_HWWRBUF_SHIFT                17
18070 #define FTM_SYNCONF_HWOM_MASK                    0x40000u
18071 #define FTM_SYNCONF_HWOM_SHIFT                   18
18072 #define FTM_SYNCONF_HWINVC_MASK                  0x80000u
18073 #define FTM_SYNCONF_HWINVC_SHIFT                 19
18074 #define FTM_SYNCONF_HWSOC_MASK                   0x100000u
18075 #define FTM_SYNCONF_HWSOC_SHIFT                  20
18076 /* INVCTRL Bit Fields */
18077 #define FTM_INVCTRL_INV0EN_MASK                  0x1u
18078 #define FTM_INVCTRL_INV0EN_SHIFT                 0
18079 #define FTM_INVCTRL_INV1EN_MASK                  0x2u
18080 #define FTM_INVCTRL_INV1EN_SHIFT                 1
18081 #define FTM_INVCTRL_INV2EN_MASK                  0x4u
18082 #define FTM_INVCTRL_INV2EN_SHIFT                 2
18083 #define FTM_INVCTRL_INV3EN_MASK                  0x8u
18084 #define FTM_INVCTRL_INV3EN_SHIFT                 3
18085 /* SWOCTRL Bit Fields */
18086 #define FTM_SWOCTRL_CH0OC_MASK                   0x1u
18087 #define FTM_SWOCTRL_CH0OC_SHIFT                  0
18088 #define FTM_SWOCTRL_CH1OC_MASK                   0x2u
18089 #define FTM_SWOCTRL_CH1OC_SHIFT                  1
18090 #define FTM_SWOCTRL_CH2OC_MASK                   0x4u
18091 #define FTM_SWOCTRL_CH2OC_SHIFT                  2
18092 #define FTM_SWOCTRL_CH3OC_MASK                   0x8u
18093 #define FTM_SWOCTRL_CH3OC_SHIFT                  3
18094 #define FTM_SWOCTRL_CH4OC_MASK                   0x10u
18095 #define FTM_SWOCTRL_CH4OC_SHIFT                  4
18096 #define FTM_SWOCTRL_CH5OC_MASK                   0x20u
18097 #define FTM_SWOCTRL_CH5OC_SHIFT                  5
18098 #define FTM_SWOCTRL_CH6OC_MASK                   0x40u
18099 #define FTM_SWOCTRL_CH6OC_SHIFT                  6
18100 #define FTM_SWOCTRL_CH7OC_MASK                   0x80u
18101 #define FTM_SWOCTRL_CH7OC_SHIFT                  7
18102 #define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
18103 #define FTM_SWOCTRL_CH0OCV_SHIFT                 8
18104 #define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
18105 #define FTM_SWOCTRL_CH1OCV_SHIFT                 9
18106 #define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
18107 #define FTM_SWOCTRL_CH2OCV_SHIFT                 10
18108 #define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
18109 #define FTM_SWOCTRL_CH3OCV_SHIFT                 11
18110 #define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
18111 #define FTM_SWOCTRL_CH4OCV_SHIFT                 12
18112 #define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
18113 #define FTM_SWOCTRL_CH5OCV_SHIFT                 13
18114 #define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
18115 #define FTM_SWOCTRL_CH6OCV_SHIFT                 14
18116 #define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
18117 #define FTM_SWOCTRL_CH7OCV_SHIFT                 15
18118 /* PWMLOAD Bit Fields */
18119 #define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
18120 #define FTM_PWMLOAD_CH0SEL_SHIFT                 0
18121 #define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
18122 #define FTM_PWMLOAD_CH1SEL_SHIFT                 1
18123 #define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
18124 #define FTM_PWMLOAD_CH2SEL_SHIFT                 2
18125 #define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
18126 #define FTM_PWMLOAD_CH3SEL_SHIFT                 3
18127 #define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
18128 #define FTM_PWMLOAD_CH4SEL_SHIFT                 4
18129 #define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
18130 #define FTM_PWMLOAD_CH5SEL_SHIFT                 5
18131 #define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
18132 #define FTM_PWMLOAD_CH6SEL_SHIFT                 6
18133 #define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
18134 #define FTM_PWMLOAD_CH7SEL_SHIFT                 7
18135 #define FTM_PWMLOAD_LDOK_MASK                    0x200u
18136 #define FTM_PWMLOAD_LDOK_SHIFT                   9
18137 
18138 /*!
18139  * @}
18140  */ /* end of group FTM_Register_Masks */
18141 
18142 /* FTM - Peripheral instance base addresses */
18143 /** Peripheral FTM1 base address */
18144 #define FTM1_BASE                                (0x30640000u)
18145 /** Peripheral FTM1 base pointer */
18146 #define FTM1                                     ((FTM_Type *)FTM1_BASE)
18147 #define FTM1_BASE_PTR                            (FTM1)
18148 /** Peripheral FTM2 base address */
18149 #define FTM2_BASE                                (0x30650000u)
18150 /** Peripheral FTM2 base pointer */
18151 #define FTM2                                     ((FTM_Type *)FTM2_BASE)
18152 #define FTM2_BASE_PTR                            (FTM2)
18153 /** Array initializer of FTM peripheral base addresses */
18154 #define FTM_BASE_ADDRS                           { FTM1_BASE, FTM2_BASE }
18155 /** Array initializer of FTM peripheral base pointers */
18156 #define FTM_BASE_PTRS                            { FTM1, FTM2 }
18157 /** Interrupt vectors for the FTM peripheral type */
18158 #define FTM_IRQS                                 { FTM1_IRQn, FTM2_IRQn }
18159 /* ----------------------------------------------------------------------------
18160    -- FTM - Register accessor macros
18161    ---------------------------------------------------------------------------- */
18162 
18163 /*!
18164  * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
18165  * @{
18166  */
18167 
18168 
18169 /* FTM - Register instance definitions */
18170 /* FTM1 */
18171 #define FTM1_SC                                  FTM_SC_REG(FTM1_BASE_PTR)
18172 #define FTM1_CNT                                 FTM_CNT_REG(FTM1_BASE_PTR)
18173 #define FTM1_MOD                                 FTM_MOD_REG(FTM1_BASE_PTR)
18174 #define FTM1_C0SC                                FTM_CSC_REG(FTM1_BASE_PTR,0)
18175 #define FTM1_C0V                                 FTM_CV_REG(FTM1_BASE_PTR,0)
18176 #define FTM1_C1SC                                FTM_CSC_REG(FTM1_BASE_PTR,1)
18177 #define FTM1_C1V                                 FTM_CV_REG(FTM1_BASE_PTR,1)
18178 #define FTM1_C2SC                                FTM_CSC_REG(FTM1_BASE_PTR,2)
18179 #define FTM1_C2V                                 FTM_CV_REG(FTM1_BASE_PTR,2)
18180 #define FTM1_C3SC                                FTM_CSC_REG(FTM1_BASE_PTR,3)
18181 #define FTM1_C3V                                 FTM_CV_REG(FTM1_BASE_PTR,3)
18182 #define FTM1_C4SC                                FTM_CSC_REG(FTM1_BASE_PTR,4)
18183 #define FTM1_C4V                                 FTM_CV_REG(FTM1_BASE_PTR,4)
18184 #define FTM1_C5SC                                FTM_CSC_REG(FTM1_BASE_PTR,5)
18185 #define FTM1_C5V                                 FTM_CV_REG(FTM1_BASE_PTR,5)
18186 #define FTM1_C6SC                                FTM_CSC_REG(FTM1_BASE_PTR,6)
18187 #define FTM1_C6V                                 FTM_CV_REG(FTM1_BASE_PTR,6)
18188 #define FTM1_C7SC                                FTM_CSC_REG(FTM1_BASE_PTR,7)
18189 #define FTM1_C7V                                 FTM_CV_REG(FTM1_BASE_PTR,7)
18190 #define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1_BASE_PTR)
18191 #define FTM1_STATUS                              FTM_STATUS_REG(FTM1_BASE_PTR)
18192 #define FTM1_MODE                                FTM_MODE_REG(FTM1_BASE_PTR)
18193 #define FTM1_SYNC                                FTM_SYNC_REG(FTM1_BASE_PTR)
18194 #define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1_BASE_PTR)
18195 #define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1_BASE_PTR)
18196 #define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1_BASE_PTR)
18197 #define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1_BASE_PTR)
18198 #define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1_BASE_PTR)
18199 #define FTM1_POL                                 FTM_POL_REG(FTM1_BASE_PTR)
18200 #define FTM1_FILTER                              FTM_FILTER_REG(FTM1_BASE_PTR)
18201 #define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1_BASE_PTR)
18202 #define FTM1_CONF                                FTM_CONF_REG(FTM1_BASE_PTR)
18203 #define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1_BASE_PTR)
18204 #define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1_BASE_PTR)
18205 #define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1_BASE_PTR)
18206 #define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1_BASE_PTR)
18207 /* FTM2 */
18208 #define FTM2_SC                                  FTM_SC_REG(FTM2_BASE_PTR)
18209 #define FTM2_CNT                                 FTM_CNT_REG(FTM2_BASE_PTR)
18210 #define FTM2_MOD                                 FTM_MOD_REG(FTM2_BASE_PTR)
18211 #define FTM2_C0SC                                FTM_CSC_REG(FTM2_BASE_PTR,0)
18212 #define FTM2_C0V                                 FTM_CV_REG(FTM2_BASE_PTR,0)
18213 #define FTM2_C1SC                                FTM_CSC_REG(FTM2_BASE_PTR,1)
18214 #define FTM2_C1V                                 FTM_CV_REG(FTM2_BASE_PTR,1)
18215 #define FTM2_C2SC                                FTM_CSC_REG(FTM2_BASE_PTR,2)
18216 #define FTM2_C2V                                 FTM_CV_REG(FTM2_BASE_PTR,2)
18217 #define FTM2_C3SC                                FTM_CSC_REG(FTM2_BASE_PTR,3)
18218 #define FTM2_C3V                                 FTM_CV_REG(FTM2_BASE_PTR,3)
18219 #define FTM2_C4SC                                FTM_CSC_REG(FTM2_BASE_PTR,4)
18220 #define FTM2_C4V                                 FTM_CV_REG(FTM2_BASE_PTR,4)
18221 #define FTM2_C5SC                                FTM_CSC_REG(FTM2_BASE_PTR,5)
18222 #define FTM2_C5V                                 FTM_CV_REG(FTM2_BASE_PTR,5)
18223 #define FTM2_C6SC                                FTM_CSC_REG(FTM2_BASE_PTR,6)
18224 #define FTM2_C6V                                 FTM_CV_REG(FTM2_BASE_PTR,6)
18225 #define FTM2_C7SC                                FTM_CSC_REG(FTM2_BASE_PTR,7)
18226 #define FTM2_C7V                                 FTM_CV_REG(FTM2_BASE_PTR,7)
18227 #define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2_BASE_PTR)
18228 #define FTM2_STATUS                              FTM_STATUS_REG(FTM2_BASE_PTR)
18229 #define FTM2_MODE                                FTM_MODE_REG(FTM2_BASE_PTR)
18230 #define FTM2_SYNC                                FTM_SYNC_REG(FTM2_BASE_PTR)
18231 #define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2_BASE_PTR)
18232 #define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2_BASE_PTR)
18233 #define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2_BASE_PTR)
18234 #define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2_BASE_PTR)
18235 #define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2_BASE_PTR)
18236 #define FTM2_POL                                 FTM_POL_REG(FTM2_BASE_PTR)
18237 #define FTM2_FILTER                              FTM_FILTER_REG(FTM2_BASE_PTR)
18238 #define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2_BASE_PTR)
18239 #define FTM2_CONF                                FTM_CONF_REG(FTM2_BASE_PTR)
18240 #define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2_BASE_PTR)
18241 #define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2_BASE_PTR)
18242 #define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2_BASE_PTR)
18243 #define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2_BASE_PTR)
18244 /* FTM - Register array accessors */
18245 #define FTM1_CSC(index)                          FTM_CSC_REG(FTM1_BASE_PTR,index)
18246 #define FTM2_CSC(index)                          FTM_CSC_REG(FTM2_BASE_PTR,index)
18247 #define FTM1_CV(index)                           FTM_CV_REG(FTM1_BASE_PTR,index)
18248 #define FTM2_CV(index)                           FTM_CV_REG(FTM2_BASE_PTR,index)
18249 /*!
18250  * @}
18251  */ /* end of group FTM_Register_Accessor_Macros */
18252 
18253 
18254 /*!
18255  * @}
18256  */ /* end of group FTM_Peripheral */
18257 
18258 /* ----------------------------------------------------------------------------
18259    -- GPC Peripheral Access Layer
18260    ---------------------------------------------------------------------------- */
18261 
18262 /*!
18263  * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
18264  * @{
18265  */
18266 
18267 /** GPC - Register Layout Typedef */
18268 typedef struct {
18269   __IO  uint32_t LPCR_A7_BSC;                            /**< Basic Low power control register of A7 platform, offset: 0x0 */
18270   __IO  uint32_t LPCR_A7_AD;                             /**< Advanced Low power control register of A7 platform, offset: 0x4 */
18271   __IO  uint32_t LPCR_M4;                                /**< Low power control register of CPU1, offset: 0x8 */
18272   uint8_t RESERVED_0[8];
18273   __IO  uint32_t SLPCR;                                  /**< System low power control register, offset: 0x14 */
18274   uint8_t RESERVED_1[8];
18275   __IO  uint32_t MLPCR;                                  /**< Memory low power control register, offset: 0x20 */
18276   __IO  uint32_t PGC_ACK_SEL_A7;                         /**< PGC acknowledge signal selection of A7 platform, offset: 0x24 */
18277   __IO  uint32_t PGC_ACK_SEL_M4;                         /**< PGC acknowledge signal selection of M4 platform, offset: 0x28 */
18278   __IO  uint32_t MISC;                                   /**< GPC Miscellaneous register, offset: 0x2C */
18279   __IO  uint32_t IMR1_CORE0_A7;                          /**< IRQ masking register 1 of A7 core0, offset: 0x30 */
18280   __IO  uint32_t IMR2_CORE0_A7;                          /**< IRQ masking register 2 of A7 core0, offset: 0x34 */
18281   __IO  uint32_t IMR3_CORE0_A7;                          /**< IRQ masking register 3 of A7 core0, offset: 0x38 */
18282   __IO  uint32_t IMR4_CORE0_A7;                          /**< IRQ masking register 4 of A7 core0, offset: 0x3C */
18283   __IO  uint32_t IMR1_CORE1_A7;                          /**< IRQ masking register 1 of A7 core1, offset: 0x40 */
18284   __IO  uint32_t IMR2_CORE1_A7;                          /**< IRQ masking register 2 of A7 core1, offset: 0x44 */
18285   __IO  uint32_t IMR3_CORE1_A7;                          /**< IRQ masking register 3 of A7 core1, offset: 0x48 */
18286   __IO  uint32_t IMR4_CORE1_A7;                          /**< IRQ masking register 4 of A7 core1, offset: 0x4C */
18287   __IO  uint32_t IMR1_M4;                                /**< IRQ masking register 1 of M4, offset: 0x50 */
18288   __IO  uint32_t IMR2_M4;                                /**< IRQ masking register 2 of M4, offset: 0x54 */
18289   __IO  uint32_t IMR3_M4;                                /**< IRQ masking register 3 of M4, offset: 0x58 */
18290   __IO  uint32_t IMR4_M4;                                /**< IRQ masking register 4 of M4, offset: 0x5C */
18291   uint8_t RESERVED_2[16];
18292   __I   uint32_t ISR1_A7;                                /**< IRQ status register 1 of A7, offset: 0x70 */
18293   __I   uint32_t ISR2_A7;                                /**< IRQ status register 2 of A7, offset: 0x74 */
18294   __I   uint32_t ISR3_A7;                                /**< IRQ status register 3 of A7, offset: 0x78 */
18295   __I   uint32_t ISR4_A7;                                /**< IRQ status register 4 of A7, offset: 0x7C */
18296   __I   uint32_t ISR1_M4;                                /**< IRQ status register 1 of M4, offset: 0x80 */
18297   __I   uint32_t ISR2_M4;                                /**< IRQ status register 2 of M4, offset: 0x84 */
18298   __I   uint32_t ISR3_M4;                                /**< IRQ status register 3 of M4, offset: 0x88 */
18299   __I   uint32_t ISR4_M4;                                /**< IRQ status register 4 of M4, offset: 0x8C */
18300   uint8_t RESERVED_3[32];
18301   __IO  uint32_t SLT_CFG[10];                            /**< Slot configure register, array offset: 0xB0, array step: 0x4 */
18302   uint8_t RESERVED_4[20];
18303   __IO  uint32_t PGC_CPU_MAPPING;                        /**< PGC CPU mapping, offset: 0xEC */
18304   __IO  uint32_t CPU_PGC_SW_PUP_REQ;                     /**< CPU PGC software up trigger, offset: 0xF0 */
18305   uint8_t RESERVED_5[4];
18306   __IO  uint32_t PU_PGC_SW_PUP_REQ;                      /**< PU PGC software up trigger, offset: 0xF8 */
18307   __IO  uint32_t CPU_PGC_SW_PDN_REQ;                     /**< CPU PGC software down trigger, offset: 0xFC */
18308   uint8_t RESERVED_6[4];
18309   __IO  uint32_t PU_PGC_SW_PDN_REQ;                      /**< PU PGC software down trigger, offset: 0x104 */
18310   uint8_t RESERVED_7[8];
18311   __I   uint32_t LPS_A7;                                 /**< Low power status of A7 platform, offset: 0x110 */
18312   __IO  uint32_t LPS_M4;                                 /**< Low power status of M4 platform, offset: 0x114 */
18313   uint8_t RESERVED_8[8];
18314   __IO  uint32_t GPC_GPR;                                /**< GPC general purpose register , offset: 0x120 */
18315   __IO  uint32_t GTOR;                                   /**< GPC testing observe register, offset: 0x124 */
18316   __I   uint32_t DEBUG_ADDR1;                            /**< DEBUG ADDR1, offset: 0x128 */
18317   __I   uint32_t DEBUG_ADDR2;                            /**< DEBUG ADDR2, offset: 0x12C */
18318   __I   uint32_t CPU_PGC_PUP_STATUS1;                    /**< CPU PGC software up trigger status1, offset: 0x130 */
18319   __I   uint32_t A7_PU_PGC_PUP_STATUS[3];                /**< A7 PU software up trigger status register, array offset: 0x134, array step: 0x4 */
18320   __I   uint32_t M4_PU_PGC_PUP_STATUS[3];                /**< A7 MIX PGC software up trigger status1, array offset: 0x140, array step: 0x4 */
18321   uint8_t RESERVED_9[36];
18322   __I   uint32_t CPU_PGC_PDN_STATUS1;                    /**< CPU PGC software dn trigger status1, offset: 0x170 */
18323   uint8_t RESERVED_10[24];
18324   __I   uint32_t A7_PU_PGC_PDN_STATUS[3];                /**< A7 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */
18325   __I   uint32_t M4_PU_PGC_PDN_STATUS[3];                /**< M4 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */
18326   uint8_t RESERVED_11[12];
18327   __IO  uint32_t A7_MIX_PDN_FLG;                         /**< A7 MIX PDN FLG, offset: 0x1B0 */
18328   __I   uint32_t A7_PU_PDN_FLG;                          /**< A7 PU PDN FLG, offset: 0x1B4 */
18329   __IO  uint32_t M4_MIX_PDN_FLG;                         /**< M4 MIX PDN FLG, offset: 0x1B8 */
18330   __I   uint32_t M4_PU_PDN_FLG;                          /**< M4 PU PDN FLG, offset: 0x1BC */
18331 } GPC_Type, *GPC_MemMapPtr;
18332 /* ----------------------------------------------------------------------------
18333    -- GPC - Register accessor macros
18334    ---------------------------------------------------------------------------- */
18335 
18336 /*!
18337  * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros
18338  * @{
18339  */
18340 
18341 
18342 /* GPC - Register accessors */
18343 #define GPC_LPCR_A7_BSC_REG(base)                ((base)->LPCR_A7_BSC)
18344 #define GPC_LPCR_A7_AD_REG(base)                 ((base)->LPCR_A7_AD)
18345 #define GPC_LPCR_M4_REG(base)                    ((base)->LPCR_M4)
18346 #define GPC_SLPCR_REG(base)                      ((base)->SLPCR)
18347 #define GPC_MLPCR_REG(base)                      ((base)->MLPCR)
18348 #define GPC_PGC_ACK_SEL_A7_REG(base)             ((base)->PGC_ACK_SEL_A7)
18349 #define GPC_PGC_ACK_SEL_M4_REG(base)             ((base)->PGC_ACK_SEL_M4)
18350 #define GPC_MISC_REG(base)                       ((base)->MISC)
18351 #define GPC_IMR1_CORE0_A7_REG(base)              ((base)->IMR1_CORE0_A7)
18352 #define GPC_IMR2_CORE0_A7_REG(base)              ((base)->IMR2_CORE0_A7)
18353 #define GPC_IMR3_CORE0_A7_REG(base)              ((base)->IMR3_CORE0_A7)
18354 #define GPC_IMR4_CORE0_A7_REG(base)              ((base)->IMR4_CORE0_A7)
18355 #define GPC_IMR1_CORE1_A7_REG(base)              ((base)->IMR1_CORE1_A7)
18356 #define GPC_IMR2_CORE1_A7_REG(base)              ((base)->IMR2_CORE1_A7)
18357 #define GPC_IMR3_CORE1_A7_REG(base)              ((base)->IMR3_CORE1_A7)
18358 #define GPC_IMR4_CORE1_A7_REG(base)              ((base)->IMR4_CORE1_A7)
18359 #define GPC_IMR1_M4_REG(base)                    ((base)->IMR1_M4)
18360 #define GPC_IMR2_M4_REG(base)                    ((base)->IMR2_M4)
18361 #define GPC_IMR3_M4_REG(base)                    ((base)->IMR3_M4)
18362 #define GPC_IMR4_M4_REG(base)                    ((base)->IMR4_M4)
18363 #define GPC_ISR1_A7_REG(base)                    ((base)->ISR1_A7)
18364 #define GPC_ISR2_A7_REG(base)                    ((base)->ISR2_A7)
18365 #define GPC_ISR3_A7_REG(base)                    ((base)->ISR3_A7)
18366 #define GPC_ISR4_A7_REG(base)                    ((base)->ISR4_A7)
18367 #define GPC_ISR1_M4_REG(base)                    ((base)->ISR1_M4)
18368 #define GPC_ISR2_M4_REG(base)                    ((base)->ISR2_M4)
18369 #define GPC_ISR3_M4_REG(base)                    ((base)->ISR3_M4)
18370 #define GPC_ISR4_M4_REG(base)                    ((base)->ISR4_M4)
18371 #define GPC_SLT_CFG_REG(base,index)              ((base)->SLT_CFG[index])
18372 #define GPC_PGC_CPU_MAPPING_REG(base)            ((base)->PGC_CPU_MAPPING)
18373 #define GPC_CPU_PGC_SW_PUP_REQ_REG(base)         ((base)->CPU_PGC_SW_PUP_REQ)
18374 #define GPC_PU_PGC_SW_PUP_REQ_REG(base)          ((base)->PU_PGC_SW_PUP_REQ)
18375 #define GPC_CPU_PGC_SW_PDN_REQ_REG(base)         ((base)->CPU_PGC_SW_PDN_REQ)
18376 #define GPC_PU_PGC_SW_PDN_REQ_REG(base)          ((base)->PU_PGC_SW_PDN_REQ)
18377 #define GPC_LPS_A7_REG(base)                     ((base)->LPS_A7)
18378 #define GPC_LPS_M4_REG(base)                     ((base)->LPS_M4)
18379 #define GPC_GPC_GPR_REG(base)                    ((base)->GPC_GPR)
18380 #define GPC_GTOR_REG(base)                       ((base)->GTOR)
18381 #define GPC_DEBUG_ADDR1_REG(base)                ((base)->DEBUG_ADDR1)
18382 #define GPC_DEBUG_ADDR2_REG(base)                ((base)->DEBUG_ADDR2)
18383 #define GPC_CPU_PGC_PUP_STATUS1_REG(base)        ((base)->CPU_PGC_PUP_STATUS1)
18384 #define GPC_A7_PU_PGC_PUP_STATUS_REG(base,index) ((base)->A7_PU_PGC_PUP_STATUS[index])
18385 #define GPC_M4_PU_PGC_PUP_STATUS_REG(base,index) ((base)->M4_PU_PGC_PUP_STATUS[index])
18386 #define GPC_CPU_PGC_PDN_STATUS1_REG(base)        ((base)->CPU_PGC_PDN_STATUS1)
18387 #define GPC_A7_PU_PGC_PDN_STATUS_REG(base,index) ((base)->A7_PU_PGC_PDN_STATUS[index])
18388 #define GPC_M4_PU_PGC_PDN_STATUS_REG(base,index) ((base)->M4_PU_PGC_PDN_STATUS[index])
18389 #define GPC_A7_MIX_PDN_FLG_REG(base)             ((base)->A7_MIX_PDN_FLG)
18390 #define GPC_A7_PU_PDN_FLG_REG(base)              ((base)->A7_PU_PDN_FLG)
18391 #define GPC_M4_MIX_PDN_FLG_REG(base)             ((base)->M4_MIX_PDN_FLG)
18392 #define GPC_M4_PU_PDN_FLG_REG(base)              ((base)->M4_PU_PDN_FLG)
18393 
18394 /*!
18395  * @}
18396  */ /* end of group GPC_Register_Accessor_Macros */
18397 /* ----------------------------------------------------------------------------
18398    -- GPC Register Masks
18399    ---------------------------------------------------------------------------- */
18400 
18401 /*!
18402  * @addtogroup GPC_Register_Masks GPC Register Masks
18403  * @{
18404  */
18405 
18406 /* LPCR_A7_BSC Bit Fields */
18407 #define GPC_LPCR_A7_BSC_LPM0_MASK                0x3u
18408 #define GPC_LPCR_A7_BSC_LPM0_SHIFT               0
18409 #define GPC_LPCR_A7_BSC_LPM0(x)                  (((uint32_t)(((uint32_t)(x))<<GPC_LPCR_A7_BSC_LPM0_SHIFT))&GPC_LPCR_A7_BSC_LPM0_MASK)
18410 #define GPC_LPCR_A7_BSC_LPM1_MASK                0xCu
18411 #define GPC_LPCR_A7_BSC_LPM1_SHIFT               2
18412 #define GPC_LPCR_A7_BSC_LPM1(x)                  (((uint32_t)(((uint32_t)(x))<<GPC_LPCR_A7_BSC_LPM1_SHIFT))&GPC_LPCR_A7_BSC_LPM1_MASK)
18413 #define GPC_LPCR_A7_BSC_CPU_CLK_ON_LPM_MASK      0x4000u
18414 #define GPC_LPCR_A7_BSC_CPU_CLK_ON_LPM_SHIFT     14
18415 #define GPC_LPCR_A7_BSC_MASK_CORE0_WFI_MASK      0x10000u
18416 #define GPC_LPCR_A7_BSC_MASK_CORE0_WFI_SHIFT     16
18417 #define GPC_LPCR_A7_BSC_MASK_CORE1_WFI_MASK      0x20000u
18418 #define GPC_LPCR_A7_BSC_MASK_CORE1_WFI_SHIFT     17
18419 #define GPC_LPCR_A7_BSC_MASK_L2CC_WFI_MASK       0x4000000u
18420 #define GPC_LPCR_A7_BSC_MASK_L2CC_WFI_SHIFT      26
18421 #define GPC_LPCR_A7_BSC_IRQ_SRC_C0_MASK          0x10000000u
18422 #define GPC_LPCR_A7_BSC_IRQ_SRC_C0_SHIFT         28
18423 #define GPC_LPCR_A7_BSC_IRQ_SRC_C1_MASK          0x20000000u
18424 #define GPC_LPCR_A7_BSC_IRQ_SRC_C1_SHIFT         29
18425 #define GPC_LPCR_A7_BSC_IRQ_SRC_A7_WUP_MASK      0x40000000u
18426 #define GPC_LPCR_A7_BSC_IRQ_SRC_A7_WUP_SHIFT     30
18427 #define GPC_LPCR_A7_BSC_MASK_DSM_TRIGGER_MASK    0x80000000u
18428 #define GPC_LPCR_A7_BSC_MASK_DSM_TRIGGER_SHIFT   31
18429 /* LPCR_A7_AD Bit Fields */
18430 #define GPC_LPCR_A7_AD_EN_C0_WFI_PDN_MASK        0x1u
18431 #define GPC_LPCR_A7_AD_EN_C0_WFI_PDN_SHIFT       0
18432 #define GPC_LPCR_A7_AD_EN_C0_PDN_MASK            0x2u
18433 #define GPC_LPCR_A7_AD_EN_C0_PDN_SHIFT           1
18434 #define GPC_LPCR_A7_AD_EN_C1_WFI_PDN_MASK        0x4u
18435 #define GPC_LPCR_A7_AD_EN_C1_WFI_PDN_SHIFT       2
18436 #define GPC_LPCR_A7_AD_EN_C1_PDN_MASK            0x8u
18437 #define GPC_LPCR_A7_AD_EN_C1_PDN_SHIFT           3
18438 #define GPC_LPCR_A7_AD_EN_PLAT_PDN_MASK          0x10u
18439 #define GPC_LPCR_A7_AD_EN_PLAT_PDN_SHIFT         4
18440 #define GPC_LPCR_A7_AD_EN_C0_IRQ_PUP_MASK        0x100u
18441 #define GPC_LPCR_A7_AD_EN_C0_IRQ_PUP_SHIFT       8
18442 #define GPC_LPCR_A7_AD_EN_C0_PUP_MASK            0x200u
18443 #define GPC_LPCR_A7_AD_EN_C0_PUP_SHIFT           9
18444 #define GPC_LPCR_A7_AD_EN_C1_IRQ_PUP_MASK        0x400u
18445 #define GPC_LPCR_A7_AD_EN_C1_IRQ_PUP_SHIFT       10
18446 #define GPC_LPCR_A7_AD_EN_C1_PUP_MASK            0x800u
18447 #define GPC_LPCR_A7_AD_EN_C1_PUP_SHIFT           11
18448 #define GPC_LPCR_A7_AD_L2_PGE_MASK               0x10000u
18449 #define GPC_LPCR_A7_AD_L2_PGE_SHIFT              16
18450 /* LPCR_M4 Bit Fields */
18451 #define GPC_LPCR_M4_LPM0_MASK                    0x3u
18452 #define GPC_LPCR_M4_LPM0_SHIFT                   0
18453 #define GPC_LPCR_M4_LPM0(x)                      (((uint32_t)(((uint32_t)(x))<<GPC_LPCR_M4_LPM0_SHIFT))&GPC_LPCR_M4_LPM0_MASK)
18454 #define GPC_LPCR_M4_EN_M4_PDN_MASK               0x4u
18455 #define GPC_LPCR_M4_EN_M4_PDN_SHIFT              2
18456 #define GPC_LPCR_M4_EN_M4_PUP_MASK               0x8u
18457 #define GPC_LPCR_M4_EN_M4_PUP_SHIFT              3
18458 #define GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK          0x4000u
18459 #define GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT         14
18460 #define GPC_LPCR_M4_MASK_M4_WFI_MASK             0x10000u
18461 #define GPC_LPCR_M4_MASK_M4_WFI_SHIFT            16
18462 #define GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK        0x80000000u
18463 #define GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT       31
18464 /* SLPCR Bit Fields */
18465 #define GPC_SLPCR_BYPASS_PMIC_READY_MASK         0x1u
18466 #define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT        0
18467 #define GPC_SLPCR_SBYOS_MASK                     0x2u
18468 #define GPC_SLPCR_SBYOS_SHIFT                    1
18469 #define GPC_SLPCR_VSTBY_MASK                     0x4u
18470 #define GPC_SLPCR_VSTBY_SHIFT                    2
18471 #define GPC_SLPCR_STBY_COUNT_MASK                0x38u
18472 #define GPC_SLPCR_STBY_COUNT_SHIFT               3
18473 #define GPC_SLPCR_STBY_COUNT(x)                  (((uint32_t)(((uint32_t)(x))<<GPC_SLPCR_STBY_COUNT_SHIFT))&GPC_SLPCR_STBY_COUNT_MASK)
18474 #define GPC_SLPCR_COSC_PWRDOWN_MASK              0x40u
18475 #define GPC_SLPCR_COSC_PWRDOWN_SHIFT             6
18476 #define GPC_SLPCR_COSC_EN_MASK                   0x80u
18477 #define GPC_SLPCR_COSC_EN_SHIFT                  7
18478 #define GPC_SLPCR_OSCCNT_MASK                    0xFF00u
18479 #define GPC_SLPCR_OSCCNT_SHIFT                   8
18480 #define GPC_SLPCR_OSCCNT(x)                      (((uint32_t)(((uint32_t)(x))<<GPC_SLPCR_OSCCNT_SHIFT))&GPC_SLPCR_OSCCNT_MASK)
18481 #define GPC_SLPCR_EN_A7_FASTWUP_WAIT_MODE_MASK   0x10000u
18482 #define GPC_SLPCR_EN_A7_FASTWUP_WAIT_MODE_SHIFT  16
18483 #define GPC_SLPCR_EN_A7_FASTWUP_STOP_MODE_MASK   0x20000u
18484 #define GPC_SLPCR_EN_A7_FASTWUP_STOP_MODE_SHIFT  17
18485 #define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK   0x40000u
18486 #define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT  18
18487 #define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK   0x80000u
18488 #define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT  19
18489 #define GPC_SLPCR_DISABLE_A7_IS_DSM_MASK         0x800000u
18490 #define GPC_SLPCR_DISABLE_A7_IS_DSM_SHIFT        23
18491 #define GPC_SLPCR_REG_BYPASS_COUNT_MASK          0x3F000000u
18492 #define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT         24
18493 #define GPC_SLPCR_REG_BYPASS_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<GPC_SLPCR_REG_BYPASS_COUNT_SHIFT))&GPC_SLPCR_REG_BYPASS_COUNT_MASK)
18494 #define GPC_SLPCR_RBC_EN_MASK                    0x40000000u
18495 #define GPC_SLPCR_RBC_EN_SHIFT                   30
18496 #define GPC_SLPCR_EN_DSM_MASK                    0x80000000u
18497 #define GPC_SLPCR_EN_DSM_SHIFT                   31
18498 /* MLPCR Bit Fields */
18499 #define GPC_MLPCR_MEMLP_CTL_DIS_MASK             0x1u
18500 #define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT            0
18501 #define GPC_MLPCR_MEMLP_RET_SEL_MASK             0x2u
18502 #define GPC_MLPCR_MEMLP_RET_SEL_SHIFT            1
18503 #define GPC_MLPCR_ROMLP_PDN_DIS_MASK             0x4u
18504 #define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT            2
18505 #define GPC_MLPCR_MEMLP_ENT_CNT_MASK             0xFF00u
18506 #define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT            8
18507 #define GPC_MLPCR_MEMLP_ENT_CNT(x)               (((uint32_t)(((uint32_t)(x))<<GPC_MLPCR_MEMLP_ENT_CNT_SHIFT))&GPC_MLPCR_MEMLP_ENT_CNT_MASK)
18508 #define GPC_MLPCR_MEM_EXT_CNT_MASK               0xFF0000u
18509 #define GPC_MLPCR_MEM_EXT_CNT_SHIFT              16
18510 #define GPC_MLPCR_MEM_EXT_CNT(x)                 (((uint32_t)(((uint32_t)(x))<<GPC_MLPCR_MEM_EXT_CNT_SHIFT))&GPC_MLPCR_MEM_EXT_CNT_MASK)
18511 #define GPC_MLPCR_MEMLP_RET_PGEN_MASK            0xFF000000u
18512 #define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT           24
18513 #define GPC_MLPCR_MEMLP_RET_PGEN(x)              (((uint32_t)(((uint32_t)(x))<<GPC_MLPCR_MEMLP_RET_PGEN_SHIFT))&GPC_MLPCR_MEMLP_RET_PGEN_MASK)
18514 /* PGC_ACK_SEL_A7 Bit Fields */
18515 #define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PDN_ACK_MASK 0x1u
18516 #define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PDN_ACK_SHIFT 0
18517 #define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PDN_ACK_MASK 0x2u
18518 #define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PDN_ACK_SHIFT 1
18519 #define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PDN_ACK_MASK 0x4u
18520 #define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PDN_ACK_SHIFT 2
18521 #define GPC_PGC_ACK_SEL_A7_MF_PGC_PDN_ACK_MASK   0x8u
18522 #define GPC_PGC_ACK_SEL_A7_MF_PGC_PDN_ACK_SHIFT  3
18523 #define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PDN_ACK_MASK 0x10u
18524 #define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PDN_ACK_SHIFT 4
18525 #define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PDN_ACK_MASK 0x20u
18526 #define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PDN_ACK_SHIFT 5
18527 #define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PDN_ACK_MASK 0x40u
18528 #define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PDN_ACK_SHIFT 6
18529 #define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PDN_ACK_MASK 0x80u
18530 #define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PDN_ACK_SHIFT 7
18531 #define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PDN_ACK_MASK 0x100u
18532 #define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PDN_ACK_SHIFT 8
18533 #define GPC_PGC_ACK_SEL_A7_A7_PGC_PDN_ACK_MASK   0x8000u
18534 #define GPC_PGC_ACK_SEL_A7_A7_PGC_PDN_ACK_SHIFT  15
18535 #define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PUP_ACK_MASK 0x10000u
18536 #define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PUP_ACK_SHIFT 16
18537 #define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PUP_ACK_MASK 0x20000u
18538 #define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PUP_ACK_SHIFT 17
18539 #define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PUP_ACK_MASK 0x40000u
18540 #define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PUP_ACK_SHIFT 18
18541 #define GPC_PGC_ACK_SEL_A7_MF_PGC_PUP_ACK_MASK   0x80000u
18542 #define GPC_PGC_ACK_SEL_A7_MF_PGC_PUP_ACK_SHIFT  19
18543 #define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PUP_ACK_MASK 0x100000u
18544 #define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PUP_ACK_SHIFT 20
18545 #define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PUP_ACK_MASK 0x200000u
18546 #define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PUP_ACK_SHIFT 21
18547 #define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PUP_ACK_MASK 0x400000u
18548 #define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PUP_ACK_SHIFT 22
18549 #define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PUP_ACK_MASK 0x800000u
18550 #define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PUP_ACK_SHIFT 23
18551 #define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PUP_ACK_MASK 0x1000000u
18552 #define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PUP_ACK_SHIFT 24
18553 #define GPC_PGC_ACK_SEL_A7_A7_PGC_PUP_ACK_MASK   0x80000000u
18554 #define GPC_PGC_ACK_SEL_A7_A7_PGC_PUP_ACK_SHIFT  31
18555 /* PGC_ACK_SEL_M4 Bit Fields */
18556 #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK 0x1u
18557 #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT 0
18558 #define GPC_PGC_ACK_SEL_M4_MF_PGC_PDN_ACK_MASK   0x8u
18559 #define GPC_PGC_ACK_SEL_M4_MF_PGC_PDN_ACK_SHIFT  3
18560 #define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PDN_ACK_MASK 0x10u
18561 #define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PDN_ACK_SHIFT 4
18562 #define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PDN_ACK_MASK 0x20u
18563 #define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PDN_ACK_SHIFT 5
18564 #define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PDN_ACK_MASK 0x40u
18565 #define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PDN_ACK_SHIFT 6
18566 #define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PDN_ACK_MASK 0x80u
18567 #define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PDN_ACK_SHIFT 7
18568 #define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PDN_ACK_MASK 0x100u
18569 #define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PDN_ACK_SHIFT 8
18570 #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK 0x8000u
18571 #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT 15
18572 #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK 0x10000u
18573 #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT 16
18574 #define GPC_PGC_ACK_SEL_M4_MF_PGC_PUP_ACK_MASK   0x80000u
18575 #define GPC_PGC_ACK_SEL_M4_MF_PGC_PUP_ACK_SHIFT  19
18576 #define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PUP_ACK_MASK 0x100000u
18577 #define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PUP_ACK_SHIFT 20
18578 #define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PUP_ACK_MASK 0x200000u
18579 #define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PUP_ACK_SHIFT 21
18580 #define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PUP_ACK_MASK 0x400000u
18581 #define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PUP_ACK_SHIFT 22
18582 #define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PUP_ACK_MASK 0x800000u
18583 #define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PUP_ACK_SHIFT 23
18584 #define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PUP_ACK_MASK 0x1000000u
18585 #define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PUP_ACK_SHIFT 24
18586 #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK 0x80000000u
18587 #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT 31
18588 /* MISC Bit Fields */
18589 #define GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK        0x1u
18590 #define GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT       0
18591 #define GPC_MISC_GPC_IRQ_MASK_MASK               0x20u
18592 #define GPC_MISC_GPC_IRQ_MASK_SHIFT              5
18593 #define GPC_MISC_M4_PDN_REQ_MASK_MASK            0x100u
18594 #define GPC_MISC_M4_PDN_REQ_MASK_SHIFT           8
18595 /* IMR1_CORE0_A7 Bit Fields */
18596 #define GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_MASK     0xFFFFFFFFu
18597 #define GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_SHIFT    0
18598 #define GPC_IMR1_CORE0_A7_IMR1_CORE0_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_SHIFT))&GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_MASK)
18599 /* IMR2_CORE0_A7 Bit Fields */
18600 #define GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_MASK     0xFFFFFFFFu
18601 #define GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_SHIFT    0
18602 #define GPC_IMR2_CORE0_A7_IMR2_CORE0_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_SHIFT))&GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_MASK)
18603 /* IMR3_CORE0_A7 Bit Fields */
18604 #define GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_MASK     0xFFFFFFFFu
18605 #define GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_SHIFT    0
18606 #define GPC_IMR3_CORE0_A7_IMR3_CORE0_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_SHIFT))&GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_MASK)
18607 /* IMR4_CORE0_A7 Bit Fields */
18608 #define GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_MASK     0xFFFFFFFFu
18609 #define GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_SHIFT    0
18610 #define GPC_IMR4_CORE0_A7_IMR4_CORE0_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_SHIFT))&GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_MASK)
18611 /* IMR1_CORE1_A7 Bit Fields */
18612 #define GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_MASK     0xFFFFFFFFu
18613 #define GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_SHIFT    0
18614 #define GPC_IMR1_CORE1_A7_IMR1_CORE1_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_SHIFT))&GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_MASK)
18615 /* IMR2_CORE1_A7 Bit Fields */
18616 #define GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_MASK     0xFFFFFFFFu
18617 #define GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_SHIFT    0
18618 #define GPC_IMR2_CORE1_A7_IMR2_CORE1_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_SHIFT))&GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_MASK)
18619 /* IMR3_CORE1_A7 Bit Fields */
18620 #define GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_MASK     0xFFFFFFFFu
18621 #define GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_SHIFT    0
18622 #define GPC_IMR3_CORE1_A7_IMR3_CORE1_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_SHIFT))&GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_MASK)
18623 /* IMR4_CORE1_A7 Bit Fields */
18624 #define GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_MASK     0xFFFFFFFFu
18625 #define GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_SHIFT    0
18626 #define GPC_IMR4_CORE1_A7_IMR4_CORE1_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_SHIFT))&GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_MASK)
18627 /* IMR1_M4 Bit Fields */
18628 #define GPC_IMR1_M4_IMR1_M4_MASK                 0xFFFFFFFFu
18629 #define GPC_IMR1_M4_IMR1_M4_SHIFT                0
18630 #define GPC_IMR1_M4_IMR1_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_M4_IMR1_M4_SHIFT))&GPC_IMR1_M4_IMR1_M4_MASK)
18631 /* IMR2_M4 Bit Fields */
18632 #define GPC_IMR2_M4_IMR2_M4_MASK                 0xFFFFFFFFu
18633 #define GPC_IMR2_M4_IMR2_M4_SHIFT                0
18634 #define GPC_IMR2_M4_IMR2_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_M4_IMR2_M4_SHIFT))&GPC_IMR2_M4_IMR2_M4_MASK)
18635 /* IMR3_M4 Bit Fields */
18636 #define GPC_IMR3_M4_IMR3_M4_MASK                 0xFFFFFFFFu
18637 #define GPC_IMR3_M4_IMR3_M4_SHIFT                0
18638 #define GPC_IMR3_M4_IMR3_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_M4_IMR3_M4_SHIFT))&GPC_IMR3_M4_IMR3_M4_MASK)
18639 /* IMR4_M4 Bit Fields */
18640 #define GPC_IMR4_M4_IMR4_M4_MASK                 0xFFFFFFFFu
18641 #define GPC_IMR4_M4_IMR4_M4_SHIFT                0
18642 #define GPC_IMR4_M4_IMR4_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_M4_IMR4_M4_SHIFT))&GPC_IMR4_M4_IMR4_M4_MASK)
18643 /* ISR1_A7 Bit Fields */
18644 #define GPC_ISR1_A7_ISR1_A7_MASK                 0xFFFFFFFFu
18645 #define GPC_ISR1_A7_ISR1_A7_SHIFT                0
18646 #define GPC_ISR1_A7_ISR1_A7(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_A7_ISR1_A7_SHIFT))&GPC_ISR1_A7_ISR1_A7_MASK)
18647 /* ISR2_A7 Bit Fields */
18648 #define GPC_ISR2_A7_ISR2_A7_MASK                 0xFFFFFFFFu
18649 #define GPC_ISR2_A7_ISR2_A7_SHIFT                0
18650 #define GPC_ISR2_A7_ISR2_A7(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_A7_ISR2_A7_SHIFT))&GPC_ISR2_A7_ISR2_A7_MASK)
18651 /* ISR3_A7 Bit Fields */
18652 #define GPC_ISR3_A7_ISR3_A7_MASK                 0xFFFFFFFFu
18653 #define GPC_ISR3_A7_ISR3_A7_SHIFT                0
18654 #define GPC_ISR3_A7_ISR3_A7(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_A7_ISR3_A7_SHIFT))&GPC_ISR3_A7_ISR3_A7_MASK)
18655 /* ISR4_A7 Bit Fields */
18656 #define GPC_ISR4_A7_ISR4_A7_MASK                 0xFFFFFFFFu
18657 #define GPC_ISR4_A7_ISR4_A7_SHIFT                0
18658 #define GPC_ISR4_A7_ISR4_A7(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_A7_ISR4_A7_SHIFT))&GPC_ISR4_A7_ISR4_A7_MASK)
18659 /* ISR1_M4 Bit Fields */
18660 #define GPC_ISR1_M4_ISR1_M4_MASK                 0xFFFFFFFFu
18661 #define GPC_ISR1_M4_ISR1_M4_SHIFT                0
18662 #define GPC_ISR1_M4_ISR1_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_M4_ISR1_M4_SHIFT))&GPC_ISR1_M4_ISR1_M4_MASK)
18663 /* ISR2_M4 Bit Fields */
18664 #define GPC_ISR2_M4_ISR2_M4_MASK                 0xFFFFFFFFu
18665 #define GPC_ISR2_M4_ISR2_M4_SHIFT                0
18666 #define GPC_ISR2_M4_ISR2_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_M4_ISR2_M4_SHIFT))&GPC_ISR2_M4_ISR2_M4_MASK)
18667 /* ISR3_M4 Bit Fields */
18668 #define GPC_ISR3_M4_ISR3_M4_MASK                 0xFFFFFFFFu
18669 #define GPC_ISR3_M4_ISR3_M4_SHIFT                0
18670 #define GPC_ISR3_M4_ISR3_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_M4_ISR3_M4_SHIFT))&GPC_ISR3_M4_ISR3_M4_MASK)
18671 /* ISR4_M4 Bit Fields */
18672 #define GPC_ISR4_M4_ISR4_M4_MASK                 0xFFFFFFFFu
18673 #define GPC_ISR4_M4_ISR4_M4_SHIFT                0
18674 #define GPC_ISR4_M4_ISR4_M4(x)                   (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_M4_ISR4_M4_SHIFT))&GPC_ISR4_M4_ISR4_M4_MASK)
18675 /* SLT_CFG Bit Fields */
18676 #define GPC_SLT_CFG_CORE0_A7_PDN_SLOT_CONTROL_MASK 0x1u
18677 #define GPC_SLT_CFG_CORE0_A7_PDN_SLOT_CONTROL_SHIFT 0
18678 #define GPC_SLT_CFG_CORE0_A7_PUP_SLOT_CONTROL_MASK 0x2u
18679 #define GPC_SLT_CFG_CORE0_A7_PUP_SLOT_CONTROL_SHIFT 1
18680 #define GPC_SLT_CFG_CORE1_A7_PDN_SLOT_CONTROL_MASK 0x4u
18681 #define GPC_SLT_CFG_CORE1_A7_PDN_SLOT_CONTROL_SHIFT 2
18682 #define GPC_SLT_CFG_CORE1_A7_PUP_SLOT_CONTROL_MASK 0x8u
18683 #define GPC_SLT_CFG_CORE1_A7_PUP_SLOT_CONTROL_SHIFT 3
18684 #define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_MASK    0x10u
18685 #define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_SHIFT   4
18686 #define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_MASK    0x20u
18687 #define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_SHIFT   5
18688 #define GPC_SLT_CFG_FASTMEGA_PDN_SLOT_CONTROL_MASK 0x40u
18689 #define GPC_SLT_CFG_FASTMEGA_PDN_SLOT_CONTROL_SHIFT 6
18690 #define GPC_SLT_CFG_FASTMEGA_PUP_SLOT_CONTROL_MASK 0x80u
18691 #define GPC_SLT_CFG_FASTMEGA_PUP_SLOT_CONTROL_SHIFT 7
18692 #define GPC_SLT_CFG_MIPI_PHY_PDN_SLOT_CONTROL_MASK 0x100u
18693 #define GPC_SLT_CFG_MIPI_PHY_PDN_SLOT_CONTROL_SHIFT 8
18694 #define GPC_SLT_CFG_MIPI_PHY_PUP_SLOT_CONTROL_MASK 0x200u
18695 #define GPC_SLT_CFG_MIPI_PHY_PUP_SLOT_CONTROL_SHIFT 9
18696 #define GPC_SLT_CFG_PCIE_PHY_PDN_SLOT_CONTROL_MASK 0x400u
18697 #define GPC_SLT_CFG_PCIE_PHY_PDN_SLOT_CONTROL_SHIFT 10
18698 #define GPC_SLT_CFG_PCIE_PHY_PUP_SLOT_CONTROL_MASK 0x800u
18699 #define GPC_SLT_CFG_PCIE_PHY_PUP_SLOT_CONTROL_SHIFT 11
18700 #define GPC_SLT_CFG_USB_OTG1_PDN_SLOT_CONTROL_MASK 0x1000u
18701 #define GPC_SLT_CFG_USB_OTG1_PDN_SLOT_CONTROL_SHIFT 12
18702 #define GPC_SLT_CFG_USB_OTG1_PUP_SLOT_CONTROL_MASK 0x2000u
18703 #define GPC_SLT_CFG_USB_OTG1_PUP_SLOT_CONTROL_SHIFT 13
18704 #define GPC_SLT_CFG_USB_OTG2_PDN_SLOT_CONTROL_MASK 0x4000u
18705 #define GPC_SLT_CFG_USB_OTG2_PDN_SLOT_CONTROL_SHIFT 14
18706 #define GPC_SLT_CFG_USB_OTG2_PUP_SLOT_CONTROL_MASK 0x8000u
18707 #define GPC_SLT_CFG_USB_OTG2_PUP_SLOT_CONTROL_SHIFT 15
18708 #define GPC_SLT_CFG_USB_HSIC_PDN_SLOT_CONTROL_MASK 0x10000u
18709 #define GPC_SLT_CFG_USB_HSIC_PDN_SLOT_CONTROL_SHIFT 16
18710 #define GPC_SLT_CFG_USB_HSIC_PUP_SLOT_CONTROL_MASK 0x20000u
18711 #define GPC_SLT_CFG_USB_HSIC_PUP_SLOT_CONTROL_SHIFT 17
18712 #define GPC_SLT_CFG_M4_VIRTUAL_PDN_SLOT_CONTROL_MASK 0x40000u
18713 #define GPC_SLT_CFG_M4_VIRTUAL_PDN_SLOT_CONTROL_SHIFT 18
18714 #define GPC_SLT_CFG_M4_VIRTUAL_PUP_SLOT_CONTROL_MASK 0x80000u
18715 #define GPC_SLT_CFG_M4_VIRTUAL_PUP_SLOT_CONTROL_SHIFT 19
18716 /* PGC_CPU_MAPPING Bit Fields */
18717 #define GPC_PGC_CPU_MAPPING_FASTMEGA_A7_DOMAIN_MASK 0x1u
18718 #define GPC_PGC_CPU_MAPPING_FASTMEGA_A7_DOMAIN_SHIFT 0
18719 #define GPC_PGC_CPU_MAPPING_MIPI_PHY_A7_DOMAIN_MASK 0x4u
18720 #define GPC_PGC_CPU_MAPPING_MIPI_PHY_A7_DOMAIN_SHIFT 2
18721 #define GPC_PGC_CPU_MAPPING_PCIE_PHY_A7_DOMAIN_MASK 0x8u
18722 #define GPC_PGC_CPU_MAPPING_PCIE_PHY_A7_DOMAIN_SHIFT 3
18723 #define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_A7_DOMAIN_MASK 0x10u
18724 #define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_A7_DOMAIN_SHIFT 4
18725 #define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_A7_DOMAIN_MASK 0x20u
18726 #define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_A7_DOMAIN_SHIFT 5
18727 #define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_A7_DOMAIN_MASK 0x40u
18728 #define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_A7_DOMAIN_SHIFT 6
18729 #define GPC_PGC_CPU_MAPPING_FASTMEGA_M4_DOMAIN_MASK 0x100u
18730 #define GPC_PGC_CPU_MAPPING_FASTMEGA_M4_DOMAIN_SHIFT 8
18731 #define GPC_PGC_CPU_MAPPING_MIPI_PHY_M4_DOMAIN_MASK 0x400u
18732 #define GPC_PGC_CPU_MAPPING_MIPI_PHY_M4_DOMAIN_SHIFT 10
18733 #define GPC_PGC_CPU_MAPPING_PCIE_PHY_M4_DOMAIN_MASK 0x800u
18734 #define GPC_PGC_CPU_MAPPING_PCIE_PHY_M4_DOMAIN_SHIFT 11
18735 #define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_M4_DOMAIN_MASK 0x1000u
18736 #define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_M4_DOMAIN_SHIFT 12
18737 #define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_M4_DOMAIN_MASK 0x2000u
18738 #define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_M4_DOMAIN_SHIFT 13
18739 #define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_M4_DOMAIN_MASK 0x4000u
18740 #define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_M4_DOMAIN_SHIFT 14
18741 /* CPU_PGC_SW_PUP_REQ Bit Fields */
18742 #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A7_SW_PUP_REQ_MASK 0x1u
18743 #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A7_SW_PUP_REQ_SHIFT 0
18744 #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ_MASK 0x2u
18745 #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ_SHIFT 1
18746 #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A7_SW_PUP_REQ_MASK 0x4u
18747 #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A7_SW_PUP_REQ_SHIFT 2
18748 /* PU_PGC_SW_PUP_REQ Bit Fields */
18749 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY_SW_PUP_REQ_MASK 0x1u
18750 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY_SW_PUP_REQ_SHIFT 0
18751 #define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_MASK 0x2u
18752 #define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_SHIFT 1
18753 #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_PHY_SW_PUP_REQ_MASK 0x4u
18754 #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_PHY_SW_PUP_REQ_SHIFT 2
18755 #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_PHY_SW_PUP_REQ_MASK 0x8u
18756 #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_PHY_SW_PUP_REQ_SHIFT 3
18757 #define GPC_PU_PGC_SW_PUP_REQ_USB_HSIC_PHY_SW_PUP_REQ_MASK 0x10u
18758 #define GPC_PU_PGC_SW_PUP_REQ_USB_HSIC_PHY_SW_PUP_REQ_SHIFT 4
18759 /* CPU_PGC_SW_PDN_REQ Bit Fields */
18760 #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A7_SW_PDN_REQ_MASK 0x1u
18761 #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A7_SW_PDN_REQ_SHIFT 0
18762 #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A7_SW_PDN_REQ_MASK 0x2u
18763 #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A7_SW_PDN_REQ_SHIFT 1
18764 #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A7_SW_PDN_REQ_MASK 0x4u
18765 #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A7_SW_PDN_REQ_SHIFT 2
18766 /* PU_PGC_SW_PDN_REQ Bit Fields */
18767 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY_SW_PDN_REQ_MASK 0x1u
18768 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY_SW_PDN_REQ_SHIFT 0
18769 #define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_MASK 0x2u
18770 #define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_SHIFT 1
18771 #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_PHY_SW_PDN_REQ_MASK 0x4u
18772 #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_PHY_SW_PDN_REQ_SHIFT 2
18773 #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_PHY_SW_PDN_REQ_MASK 0x8u
18774 #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_PHY_SW_PDN_REQ_SHIFT 3
18775 #define GPC_PU_PGC_SW_PDN_REQ_USB_HSIC_PHY_SW_PDN_REQ_MASK 0x10u
18776 #define GPC_PU_PGC_SW_PDN_REQ_USB_HSIC_PHY_SW_PDN_REQ_SHIFT 4
18777 /* LPS_A7 Bit Fields */
18778 #define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE0_MASK 0x1u
18779 #define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE0_SHIFT 0
18780 #define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE1_MASK 0x2u
18781 #define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE1_SHIFT 1
18782 #define GPC_LPS_A7_SRC_GPC_ARM_CPU0_RST_SYS_N_MASK 0x4u
18783 #define GPC_LPS_A7_SRC_GPC_ARM_CPU0_RST_SYS_N_SHIFT 2
18784 #define GPC_LPS_A7_SRC_GPC_ARM_CPU1_RST_SYS_N_MASK 0x8u
18785 #define GPC_LPS_A7_SRC_GPC_ARM_CPU1_RST_SYS_N_SHIFT 3
18786 #define GPC_LPS_A7_A7_START_ARM_RESET0_MASK      0x10u
18787 #define GPC_LPS_A7_A7_START_ARM_RESET0_SHIFT     4
18788 #define GPC_LPS_A7_A7_START_ARM_RESET2_MASK      0x20u
18789 #define GPC_LPS_A7_A7_START_ARM_RESET2_SHIFT     5
18790 #define GPC_LPS_A7_GPC_CA7_C0_ISO_MASK           0x40u
18791 #define GPC_LPS_A7_GPC_CA7_C0_ISO_SHIFT          6
18792 #define GPC_LPS_A7_GPC_CA7_C1_ISO_MASK           0x80u
18793 #define GPC_LPS_A7_GPC_CA7_C1_ISO_SHIFT          7
18794 #define GPC_LPS_A7_GPC_CA7_C0_SWITCH_B_MASK      0x100u
18795 #define GPC_LPS_A7_GPC_CA7_C0_SWITCH_B_SHIFT     8
18796 #define GPC_LPS_A7_GPC_CA7_C1_SWITCH_B_MASK      0x200u
18797 #define GPC_LPS_A7_GPC_CA7_C1_SWITCH_B_SHIFT     9
18798 #define GPC_LPS_A7_SRC_CA7_L2_RESET_N_MASK       0x400u
18799 #define GPC_LPS_A7_SRC_CA7_L2_RESET_N_SHIFT      10
18800 #define GPC_LPS_A7_SRC_A7_PLATFORM_SW_RESET_DONE_MASK 0x800u
18801 #define GPC_LPS_A7_SRC_A7_PLATFORM_SW_RESET_DONE_SHIFT 11
18802 #define GPC_LPS_A7_GPC_DAP_PUP_REQ_MASK          0x1000u
18803 #define GPC_LPS_A7_GPC_DAP_PUP_REQ_SHIFT         12
18804 #define GPC_LPS_A7_START_SCU_RESET_MASK          0x2000u
18805 #define GPC_LPS_A7_START_SCU_RESET_SHIFT         13
18806 #define GPC_LPS_A7_GPC_CA7_SCU_ISO_MASK          0x4000u
18807 #define GPC_LPS_A7_GPC_CA7_SCU_ISO_SHIFT         14
18808 #define GPC_LPS_A7_GPC_CA7_SCU_SWITCH_B_MASK     0x8000u
18809 #define GPC_LPS_A7_GPC_CA7_SCU_SWITCH_B_SHIFT    15
18810 #define GPC_LPS_A7_GPC_CA7_ACINACTM_MASK         0x10000u
18811 #define GPC_LPS_A7_GPC_CA7_ACINACTM_SHIFT        16
18812 #define GPC_LPS_A7_GPC_CA7_L2RETENTION_MASK      0x20000u
18813 #define GPC_LPS_A7_GPC_CA7_L2RETENTION_SHIFT     17
18814 #define GPC_LPS_A7_GPC_CA7_L2STDISABLE_MASK      0x40000u
18815 #define GPC_LPS_A7_GPC_CA7_L2STDISABLE_SHIFT     18
18816 #define GPC_LPS_A7_GPC_CA7_L2_SWITCH_B_MASK      0x80000u
18817 #define GPC_LPS_A7_GPC_CA7_L2_SWITCH_B_SHIFT     19
18818 #define GPC_LPS_A7_LPG_WAIT_MASK                 0x1000000u
18819 #define GPC_LPS_A7_LPG_WAIT_SHIFT                24
18820 #define GPC_LPS_A7_LPG_STOP_MASK                 0x2000000u
18821 #define GPC_LPS_A7_LPG_STOP_SHIFT                25
18822 #define GPC_LPS_A7_SHD_CURRENT_STATE_A7_MASK     0xC000000u
18823 #define GPC_LPS_A7_SHD_CURRENT_STATE_A7_SHIFT    26
18824 #define GPC_LPS_A7_SHD_CURRENT_STATE_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_LPS_A7_SHD_CURRENT_STATE_A7_SHIFT))&GPC_LPS_A7_SHD_CURRENT_STATE_A7_MASK)
18825 #define GPC_LPS_A7_LPM_CURRENT_STATE_A7_MASK     0x70000000u
18826 #define GPC_LPS_A7_LPM_CURRENT_STATE_A7_SHIFT    28
18827 #define GPC_LPS_A7_LPM_CURRENT_STATE_A7(x)       (((uint32_t)(((uint32_t)(x))<<GPC_LPS_A7_LPM_CURRENT_STATE_A7_SHIFT))&GPC_LPS_A7_LPM_CURRENT_STATE_A7_MASK)
18828 /* LPS_M4 Bit Fields */
18829 #define GPC_LPS_M4_LOW_POWER_CTRL_M4_MASK        0x1u
18830 #define GPC_LPS_M4_LOW_POWER_CTRL_M4_SHIFT       0
18831 #define GPC_LPS_M4_CM4_SLEEP_HOLD_ACK_B_MASK     0x2u
18832 #define GPC_LPS_M4_CM4_SLEEP_HOLD_ACK_B_SHIFT    1
18833 #define GPC_LPS_M4_CM4_GATE_HCLK_MASK            0x4u
18834 #define GPC_LPS_M4_CM4_GATE_HCLK_SHIFT           2
18835 #define GPC_LPS_M4_CM4_SLEEP_DEEP_MASK           0x8u
18836 #define GPC_LPS_M4_CM4_SLEEP_DEEP_SHIFT          3
18837 #define GPC_LPS_M4_CM4_SLEEP_MASK                0x10u
18838 #define GPC_LPS_M4_CM4_SLEEP_SHIFT               4
18839 #define GPC_LPS_M4_CM4_LOCKUP_MASK               0x20u
18840 #define GPC_LPS_M4_CM4_LOCKUP_SHIFT              5
18841 #define GPC_LPS_M4_CM4_HALTED_MASK               0x40u
18842 #define GPC_LPS_M4_CM4_HALTED_SHIFT              6
18843 #define GPC_LPS_M4_M4_PLATFORM_RESET_B_MASK      0x80u
18844 #define GPC_LPS_M4_M4_PLATFORM_RESET_B_SHIFT     7
18845 #define GPC_LPS_M4_M4_CORE_RESET_B_MASK          0x100u
18846 #define GPC_LPS_M4_M4_CORE_RESET_B_SHIFT         8
18847 #define GPC_LPS_M4_LPG_WAIT_MASK                 0x1000000u
18848 #define GPC_LPS_M4_LPG_WAIT_SHIFT                24
18849 #define GPC_LPS_M4_LPG_STOP_MASK                 0x2000000u
18850 #define GPC_LPS_M4_LPG_STOP_SHIFT                25
18851 #define GPC_LPS_M4_SHD_CURRENT_STATE_M4_MASK     0xC000000u
18852 #define GPC_LPS_M4_SHD_CURRENT_STATE_M4_SHIFT    26
18853 #define GPC_LPS_M4_SHD_CURRENT_STATE_M4(x)       (((uint32_t)(((uint32_t)(x))<<GPC_LPS_M4_SHD_CURRENT_STATE_M4_SHIFT))&GPC_LPS_M4_SHD_CURRENT_STATE_M4_MASK)
18854 #define GPC_LPS_M4_LPM_CURRENT_STATE_M4_MASK     0x70000000u
18855 #define GPC_LPS_M4_LPM_CURRENT_STATE_M4_SHIFT    28
18856 #define GPC_LPS_M4_LPM_CURRENT_STATE_M4(x)       (((uint32_t)(((uint32_t)(x))<<GPC_LPS_M4_LPM_CURRENT_STATE_M4_SHIFT))&GPC_LPS_M4_LPM_CURRENT_STATE_M4_MASK)
18857 /* GPC_GPR Bit Fields */
18858 #define GPC_GPC_GPR_A7_CORE_DBG_RST_MSK_PG_MASK  0x10000u
18859 #define GPC_GPC_GPR_A7_CORE_DBG_RST_MSK_PG_SHIFT 16
18860 /* GTOR Bit Fields */
18861 #define GPC_GTOR_OBS_OUTPUT_0_SEL_MASK           0x1Fu
18862 #define GPC_GTOR_OBS_OUTPUT_0_SEL_SHIFT          0
18863 #define GPC_GTOR_OBS_OUTPUT_0_SEL(x)             (((uint32_t)(((uint32_t)(x))<<GPC_GTOR_OBS_OUTPUT_0_SEL_SHIFT))&GPC_GTOR_OBS_OUTPUT_0_SEL_MASK)
18864 #define GPC_GTOR_OBS_OUTPUT_1_SEL_MASK           0x1F00u
18865 #define GPC_GTOR_OBS_OUTPUT_1_SEL_SHIFT          8
18866 #define GPC_GTOR_OBS_OUTPUT_1_SEL(x)             (((uint32_t)(((uint32_t)(x))<<GPC_GTOR_OBS_OUTPUT_1_SEL_SHIFT))&GPC_GTOR_OBS_OUTPUT_1_SEL_MASK)
18867 #define GPC_GTOR_OBS_OUTPUT_2_SEL_MASK           0x1F0000u
18868 #define GPC_GTOR_OBS_OUTPUT_2_SEL_SHIFT          16
18869 #define GPC_GTOR_OBS_OUTPUT_2_SEL(x)             (((uint32_t)(((uint32_t)(x))<<GPC_GTOR_OBS_OUTPUT_2_SEL_SHIFT))&GPC_GTOR_OBS_OUTPUT_2_SEL_MASK)
18870 #define GPC_GTOR_OBS_EN_MASK                     0x80000000u
18871 #define GPC_GTOR_OBS_EN_SHIFT                    31
18872 /* DEBUG_ADDR1 Bit Fields */
18873 #define GPC_DEBUG_ADDR1_GPC_INT_MASK             0x1u
18874 #define GPC_DEBUG_ADDR1_GPC_INT_SHIFT            0
18875 #define GPC_DEBUG_ADDR1_WFI_A7_CORE0_MASK        0x10u
18876 #define GPC_DEBUG_ADDR1_WFI_A7_CORE0_SHIFT       4
18877 #define GPC_DEBUG_ADDR1_WFI_A7_CORE1_MASK        0x20u
18878 #define GPC_DEBUG_ADDR1_WFI_A7_CORE1_SHIFT       5
18879 #define GPC_DEBUG_ADDR1_WFI_A7_SCU_MASK          0x40u
18880 #define GPC_DEBUG_ADDR1_WFI_A7_SCU_SHIFT         6
18881 #define GPC_DEBUG_ADDR1_WFI_M4_MASK              0x100u
18882 #define GPC_DEBUG_ADDR1_WFI_M4_SHIFT             8
18883 #define GPC_DEBUG_ADDR1_nFIQ0_MASK               0x10000u
18884 #define GPC_DEBUG_ADDR1_nFIQ0_SHIFT              16
18885 #define GPC_DEBUG_ADDR1_nFIQ1_MASK               0x20000u
18886 #define GPC_DEBUG_ADDR1_nFIQ1_SHIFT              17
18887 #define GPC_DEBUG_ADDR1_nFIQ2_MASK               0x40000u
18888 #define GPC_DEBUG_ADDR1_nFIQ2_SHIFT              18
18889 #define GPC_DEBUG_ADDR1_nFIQ3_MASK               0x80000u
18890 #define GPC_DEBUG_ADDR1_nFIQ3_SHIFT              19
18891 #define GPC_DEBUG_ADDR1_nIRQ0_MASK               0x100000u
18892 #define GPC_DEBUG_ADDR1_nIRQ0_SHIFT              20
18893 #define GPC_DEBUG_ADDR1_nIRQ1_MASK               0x200000u
18894 #define GPC_DEBUG_ADDR1_nIRQ1_SHIFT              21
18895 #define GPC_DEBUG_ADDR1_nIRQ2_MASK               0x400000u
18896 #define GPC_DEBUG_ADDR1_nIRQ2_SHIFT              22
18897 #define GPC_DEBUG_ADDR1_nIRQ3_MASK               0x800000u
18898 #define GPC_DEBUG_ADDR1_nIRQ3_SHIFT              23
18899 /* DEBUG_ADDR2 Bit Fields */
18900 #define GPC_DEBUG_ADDR2_MIX_RESET_PENETRATED_MASK 0x1u
18901 #define GPC_DEBUG_ADDR2_MIX_RESET_PENETRATED_SHIFT 0
18902 #define GPC_DEBUG_ADDR2_GPC_MIX_ISO_MASK         0x2u
18903 #define GPC_DEBUG_ADDR2_GPC_MIX_ISO_SHIFT        1
18904 #define GPC_DEBUG_ADDR2_GPC_MIX_SWITCH_B_MASK    0x4u
18905 #define GPC_DEBUG_ADDR2_GPC_MIX_SWITCH_B_SHIFT   2
18906 #define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT0_MASK  0x8u
18907 #define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT0_SHIFT 3
18908 #define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT1_MASK  0x10u
18909 #define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT1_SHIFT 4
18910 #define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_MASK       0x20u
18911 #define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_SHIFT      5
18912 #define GPC_DEBUG_ADDR2_GPC_MIX_RESET_B_MASK     0x40u
18913 #define GPC_DEBUG_ADDR2_GPC_MIX_RESET_B_SHIFT    6
18914 #define GPC_DEBUG_ADDR2_SRC_EN_MIX_CLK_MASK      0x80u
18915 #define GPC_DEBUG_ADDR2_SRC_EN_MIX_CLK_SHIFT     7
18916 #define GPC_DEBUG_ADDR2_GPC_MIX_RDY_MASK         0x100u
18917 #define GPC_DEBUG_ADDR2_GPC_MIX_RDY_SHIFT        8
18918 #define GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_MASK 0x1F000u
18919 #define GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_SHIFT 12
18920 #define GPC_DEBUG_ADDR2_PU_RESET_PENETRATED(x)   (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_SHIFT))&GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_MASK)
18921 #define GPC_DEBUG_ADDR2_GPC_PU_ISO_MASK          0x3E0000u
18922 #define GPC_DEBUG_ADDR2_GPC_PU_ISO_SHIFT         17
18923 #define GPC_DEBUG_ADDR2_GPC_PU_ISO(x)            (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_GPC_PU_ISO_SHIFT))&GPC_DEBUG_ADDR2_GPC_PU_ISO_MASK)
18924 #define GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_MASK     0x7C00000u
18925 #define GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_SHIFT    22
18926 #define GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B(x)       (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_SHIFT))&GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_MASK)
18927 #define GPC_DEBUG_ADDR2_GPC_PU_RESET_B_MASK      0xF8000000u
18928 #define GPC_DEBUG_ADDR2_GPC_PU_RESET_B_SHIFT     27
18929 #define GPC_DEBUG_ADDR2_GPC_PU_RESET_B(x)        (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_GPC_PU_RESET_B_SHIFT))&GPC_DEBUG_ADDR2_GPC_PU_RESET_B_MASK)
18930 /* CPU_PGC_PUP_STATUS1 Bit Fields */
18931 #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A7_PUP_STATUS_MASK 0x1u
18932 #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A7_PUP_STATUS_SHIFT 0
18933 #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A7_PUP_STATUS_MASK 0x2u
18934 #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A7_PUP_STATUS_SHIFT 1
18935 #define GPC_CPU_PGC_PUP_STATUS1_SCU_A7_PUP_STATUS_MASK 0x4u
18936 #define GPC_CPU_PGC_PUP_STATUS1_SCU_A7_PUP_STATUS_SHIFT 2
18937 /* A7_PU_PGC_PUP_STATUS Bit Fields */
18938 #define GPC_A7_PU_PGC_PUP_STATUS_A7_MIPI_PHY_PGC_PUP_STATUS_MASK 0x1u
18939 #define GPC_A7_PU_PGC_PUP_STATUS_A7_MIPI_PHY_PGC_PUP_STATUS_SHIFT 0
18940 #define GPC_A7_PU_PGC_PUP_STATUS_A7_PCIE_PHY_PGC_PUP_STATUS_MASK 0x2u
18941 #define GPC_A7_PU_PGC_PUP_STATUS_A7_PCIE_PHY_PGC_PUP_STATUS_SHIFT 1
18942 #define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG1_PHY_PGC_PUP_STATUS_MASK 0x4u
18943 #define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG1_PHY_PGC_PUP_STATUS_SHIFT 2
18944 #define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG2_PHY_PGC_PUP_STATUS_MASK 0x8u
18945 #define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG2_PHY_PGC_PUP_STATUS_SHIFT 3
18946 #define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_HSIC_PHY_PGC_PUP_STATUS_MASK 0x10u
18947 #define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_HSIC_PHY_PGC_PUP_STATUS_SHIFT 4
18948 /* M4_PU_PGC_PUP_STATUS Bit Fields */
18949 #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PHY_PGC_PUP_STATUS_MASK 0x1u
18950 #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PHY_PGC_PUP_STATUS_SHIFT 0
18951 #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PHY_PGC_PUP_STATUS_MASK 0x2u
18952 #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PHY_PGC_PUP_STATUS_SHIFT 1
18953 #define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG1_PHY_PGC_PUP_STATUS_MASK 0x4u
18954 #define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG1_PHY_PGC_PUP_STATUS_SHIFT 2
18955 #define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG2_PHY_PGC_PUP_STATUS_MASK 0x8u
18956 #define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG2_PHY_PGC_PUP_STATUS_SHIFT 3
18957 #define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_HSIC_PHY_PGC_PUP_STATUS_MASK 0x10u
18958 #define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_HSIC_PHY_PGC_PUP_STATUS_SHIFT 4
18959 /* CPU_PGC_PDN_STATUS1 Bit Fields */
18960 #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A7_PDN_STATUS_MASK 0x1u
18961 #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A7_PDN_STATUS_SHIFT 0
18962 #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A7_PDN_STATUS_MASK 0x2u
18963 #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A7_PDN_STATUS_SHIFT 1
18964 #define GPC_CPU_PGC_PDN_STATUS1_SCU_A7_PDN_STATUS_MASK 0x4u
18965 #define GPC_CPU_PGC_PDN_STATUS1_SCU_A7_PDN_STATUS_SHIFT 2
18966 /* A7_PU_PGC_PDN_STATUS Bit Fields */
18967 #define GPC_A7_PU_PGC_PDN_STATUS_CORE0_A7_PDN_STATUS_MASK 0x1u
18968 #define GPC_A7_PU_PGC_PDN_STATUS_CORE0_A7_PDN_STATUS_SHIFT 0
18969 #define GPC_A7_PU_PGC_PDN_STATUS_CORE1_A7_PDN_STATUS_MASK 0x2u
18970 #define GPC_A7_PU_PGC_PDN_STATUS_CORE1_A7_PDN_STATUS_SHIFT 1
18971 #define GPC_A7_PU_PGC_PDN_STATUS_SCU_A7_PDN_STATUS_MASK 0x4u
18972 #define GPC_A7_PU_PGC_PDN_STATUS_SCU_A7_PDN_STATUS_SHIFT 2
18973 /* M4_PU_PGC_PDN_STATUS Bit Fields */
18974 #define GPC_M4_PU_PGC_PDN_STATUS_A7_MIPI_PHY_PGC_PDN_STATUS_MASK 0x1u
18975 #define GPC_M4_PU_PGC_PDN_STATUS_A7_MIPI_PHY_PGC_PDN_STATUS_SHIFT 0
18976 #define GPC_M4_PU_PGC_PDN_STATUS_A7_PCIE_PHY_PGC_PDN_STATUS_MASK 0x2u
18977 #define GPC_M4_PU_PGC_PDN_STATUS_A7_PCIE_PHY_PGC_PDN_STATUS_SHIFT 1
18978 #define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG1_PHY_PGC_PDN_STATUS_MASK 0x4u
18979 #define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG1_PHY_PGC_PDN_STATUS_SHIFT 2
18980 #define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG2_PHY_PGC_PDN_STATUS_MASK 0x8u
18981 #define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG2_PHY_PGC_PDN_STATUS_SHIFT 3
18982 #define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_HSIC_PHY_PGC_PDN_STATUS_MASK 0x10u
18983 #define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_HSIC_PHY_PGC_PDN_STATUS_SHIFT 4
18984 /* A7_MIX_PDN_FLG Bit Fields */
18985 #define GPC_A7_MIX_PDN_FLG_A7_MIX_PDN_FLAG_MASK  0x1u
18986 #define GPC_A7_MIX_PDN_FLG_A7_MIX_PDN_FLAG_SHIFT 0
18987 /* A7_PU_PDN_FLG Bit Fields */
18988 #define GPC_A7_PU_PDN_FLG_A7_MIPI_PHY_PGC_PDN_FLG_MASK 0x1u
18989 #define GPC_A7_PU_PDN_FLG_A7_MIPI_PHY_PGC_PDN_FLG_SHIFT 0
18990 #define GPC_A7_PU_PDN_FLG_A7_PCIE_PHY_PGC_PDN_FLG_MASK 0x2u
18991 #define GPC_A7_PU_PDN_FLG_A7_PCIE_PHY_PGC_PDN_FLG_SHIFT 1
18992 #define GPC_A7_PU_PDN_FLG_A7_USB_OTG1_PHY_PGC_PDN_FLG_MASK 0x4u
18993 #define GPC_A7_PU_PDN_FLG_A7_USB_OTG1_PHY_PGC_PDN_FLG_SHIFT 2
18994 #define GPC_A7_PU_PDN_FLG_A7_USB_OTG2_PHY_PGC_PDN_FLG_MASK 0x8u
18995 #define GPC_A7_PU_PDN_FLG_A7_USB_OTG2_PHY_PGC_PDN_FLG_SHIFT 3
18996 #define GPC_A7_PU_PDN_FLG_A7_USB_HSIC_PHY_PGC_PDN_FLG_MASK 0x10u
18997 #define GPC_A7_PU_PDN_FLG_A7_USB_HSIC_PHY_PGC_PDN_FLG_SHIFT 4
18998 /* M4_MIX_PDN_FLG Bit Fields */
18999 #define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK  0x1u
19000 #define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT 0
19001 /* M4_PU_PDN_FLG Bit Fields */
19002 #define GPC_M4_PU_PDN_FLG_M4_MIPI_PHY_PGC_PDN_FLG_MASK 0x1u
19003 #define GPC_M4_PU_PDN_FLG_M4_MIPI_PHY_PGC_PDN_FLG_SHIFT 0
19004 #define GPC_M4_PU_PDN_FLG_M4_PCIE_PHY_PGC_PDN_FLG_MASK 0x2u
19005 #define GPC_M4_PU_PDN_FLG_M4_PCIE_PHY_PGC_PDN_FLG_SHIFT 1
19006 #define GPC_M4_PU_PDN_FLG_M4_USB_OTG1_PHY_PGC_PDN_FLG_MASK 0x4u
19007 #define GPC_M4_PU_PDN_FLG_M4_USB_OTG1_PHY_PGC_PDN_FLG_SHIFT 2
19008 #define GPC_M4_PU_PDN_FLG_M4_USB_OTG2_PHY_PGC_PDN_FLG_MASK 0x8u
19009 #define GPC_M4_PU_PDN_FLG_M4_USB_OTG2_PHY_PGC_PDN_FLG_SHIFT 3
19010 #define GPC_M4_PU_PDN_FLG_M4_USB_HSIC_PHY_PGC_PDN_FLG_MASK 0x10u
19011 #define GPC_M4_PU_PDN_FLG_M4_USB_HSIC_PHY_PGC_PDN_FLG_SHIFT 4
19012 
19013 /*!
19014  * @}
19015  */ /* end of group GPC_Register_Masks */
19016 
19017 /* GPC - Peripheral instance base addresses */
19018 /** Peripheral GPC base address */
19019 #define GPC_BASE                                 (0x303A0000u)
19020 /** Peripheral GPC base pointer */
19021 #define GPC                                      ((GPC_Type *)GPC_BASE)
19022 #define GPC_BASE_PTR                             (GPC)
19023 /** Array initializer of GPC peripheral base addresses */
19024 #define GPC_BASE_ADDRS                           { GPC_BASE }
19025 /** Array initializer of GPC peripheral base pointers */
19026 #define GPC_BASE_PTRS                            { GPC }
19027 /** Interrupt vectors for the GPC peripheral type */
19028 #define GPC_IRQS                                 { GPC_IRQn }
19029 /* ----------------------------------------------------------------------------
19030    -- GPC - Register accessor macros
19031    ---------------------------------------------------------------------------- */
19032 
19033 /*!
19034  * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros
19035  * @{
19036  */
19037 
19038 
19039 /* GPC - Register instance definitions */
19040 /* GPC */
19041 #define GPC_LPCR_A7_BSC                          GPC_LPCR_A7_BSC_REG(GPC_BASE_PTR)
19042 #define GPC_LPCR_A7_AD                           GPC_LPCR_A7_AD_REG(GPC_BASE_PTR)
19043 #define GPC_LPCR_M4                              GPC_LPCR_M4_REG(GPC_BASE_PTR)
19044 #define GPC_SLPCR                                GPC_SLPCR_REG(GPC_BASE_PTR)
19045 #define GPC_MLPCR                                GPC_MLPCR_REG(GPC_BASE_PTR)
19046 #define GPC_PGC_ACK_SEL_A7                       GPC_PGC_ACK_SEL_A7_REG(GPC_BASE_PTR)
19047 #define GPC_PGC_ACK_SEL_M4                       GPC_PGC_ACK_SEL_M4_REG(GPC_BASE_PTR)
19048 #define GPC_MISC                                 GPC_MISC_REG(GPC_BASE_PTR)
19049 #define GPC_IMR1_CORE0_A7                        GPC_IMR1_CORE0_A7_REG(GPC_BASE_PTR)
19050 #define GPC_IMR2_CORE0_A7                        GPC_IMR2_CORE0_A7_REG(GPC_BASE_PTR)
19051 #define GPC_IMR3_CORE0_A7                        GPC_IMR3_CORE0_A7_REG(GPC_BASE_PTR)
19052 #define GPC_IMR4_CORE0_A7                        GPC_IMR4_CORE0_A7_REG(GPC_BASE_PTR)
19053 #define GPC_IMR1_CORE1_A7                        GPC_IMR1_CORE1_A7_REG(GPC_BASE_PTR)
19054 #define GPC_IMR2_CORE1_A7                        GPC_IMR2_CORE1_A7_REG(GPC_BASE_PTR)
19055 #define GPC_IMR3_CORE1_A7                        GPC_IMR3_CORE1_A7_REG(GPC_BASE_PTR)
19056 #define GPC_IMR4_CORE1_A7                        GPC_IMR4_CORE1_A7_REG(GPC_BASE_PTR)
19057 #define GPC_IMR1_M4                              GPC_IMR1_M4_REG(GPC_BASE_PTR)
19058 #define GPC_IMR2_M4                              GPC_IMR2_M4_REG(GPC_BASE_PTR)
19059 #define GPC_IMR3_M4                              GPC_IMR3_M4_REG(GPC_BASE_PTR)
19060 #define GPC_IMR4_M4                              GPC_IMR4_M4_REG(GPC_BASE_PTR)
19061 #define GPC_ISR1_A7                              GPC_ISR1_A7_REG(GPC_BASE_PTR)
19062 #define GPC_ISR2_A7                              GPC_ISR2_A7_REG(GPC_BASE_PTR)
19063 #define GPC_ISR3_A7                              GPC_ISR3_A7_REG(GPC_BASE_PTR)
19064 #define GPC_ISR4_A7                              GPC_ISR4_A7_REG(GPC_BASE_PTR)
19065 #define GPC_ISR1_M4                              GPC_ISR1_M4_REG(GPC_BASE_PTR)
19066 #define GPC_ISR2_M4                              GPC_ISR2_M4_REG(GPC_BASE_PTR)
19067 #define GPC_ISR3_M4                              GPC_ISR3_M4_REG(GPC_BASE_PTR)
19068 #define GPC_ISR4_M4                              GPC_ISR4_M4_REG(GPC_BASE_PTR)
19069 #define GPC_SLT0_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,0)
19070 #define GPC_SLT1_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,1)
19071 #define GPC_SLT2_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,2)
19072 #define GPC_SLT3_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,3)
19073 #define GPC_SLT4_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,4)
19074 #define GPC_SLT5_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,5)
19075 #define GPC_SLT6_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,6)
19076 #define GPC_SLT7_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,7)
19077 #define GPC_SLT8_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,8)
19078 #define GPC_SLT9_CFG                             GPC_SLT_CFG_REG(GPC_BASE_PTR,9)
19079 #define GPC_PGC_CPU_MAPPING                      GPC_PGC_CPU_MAPPING_REG(GPC_BASE_PTR)
19080 #define GPC_CPU_PGC_SW_PUP_REQ                   GPC_CPU_PGC_SW_PUP_REQ_REG(GPC_BASE_PTR)
19081 #define GPC_PU_PGC_SW_PUP_REQ                    GPC_PU_PGC_SW_PUP_REQ_REG(GPC_BASE_PTR)
19082 #define GPC_CPU_PGC_SW_PDN_REQ                   GPC_CPU_PGC_SW_PDN_REQ_REG(GPC_BASE_PTR)
19083 #define GPC_PU_PGC_SW_PDN_REQ                    GPC_PU_PGC_SW_PDN_REQ_REG(GPC_BASE_PTR)
19084 #define GPC_LPS_A7                               GPC_LPS_A7_REG(GPC_BASE_PTR)
19085 #define GPC_LPS_M4                               GPC_LPS_M4_REG(GPC_BASE_PTR)
19086 #define GPC_GPC_GPR                              GPC_GPC_GPR_REG(GPC_BASE_PTR)
19087 #define GPC_GTOR                                 GPC_GTOR_REG(GPC_BASE_PTR)
19088 #define GPC_DEBUG_ADDR1                          GPC_DEBUG_ADDR1_REG(GPC_BASE_PTR)
19089 #define GPC_DEBUG_ADDR2                          GPC_DEBUG_ADDR2_REG(GPC_BASE_PTR)
19090 #define GPC_CPU_PGC_PUP_STATUS1                  GPC_CPU_PGC_PUP_STATUS1_REG(GPC_BASE_PTR)
19091 #define GPC_A7_PU_PGC_PUP_STATUS0                GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,0)
19092 #define GPC_A7_PU_PGC_PUP_STATUS1                GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,1)
19093 #define GPC_A7_PU_PGC_PUP_STATUS2                GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,2)
19094 #define GPC_M4_PU_PGC_PUP_STATUS0                GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,0)
19095 #define GPC_M4_PU_PGC_PUP_STATUS1                GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,1)
19096 #define GPC_M4_PU_PGC_PUP_STATUS2                GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,2)
19097 #define GPC_CPU_PGC_PDN_STATUS1                  GPC_CPU_PGC_PDN_STATUS1_REG(GPC_BASE_PTR)
19098 #define GPC_A7_PU_PGC_PDN_STATUS0                GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,0)
19099 #define GPC_A7_PU_PGC_PDN_STATUS1                GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,1)
19100 #define GPC_A7_PU_PGC_PDN_STATUS2                GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,2)
19101 #define GPC_M4_PU_PGC_PDN_STATUS0                GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,0)
19102 #define GPC_M4_PU_PGC_PDN_STATUS1                GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,1)
19103 #define GPC_M4_PU_PGC_PDN_STATUS2                GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,2)
19104 #define GPC_A7_MIX_PDN_FLG                       GPC_A7_MIX_PDN_FLG_REG(GPC_BASE_PTR)
19105 #define GPC_A7_PU_PDN_FLG                        GPC_A7_PU_PDN_FLG_REG(GPC_BASE_PTR)
19106 #define GPC_M4_MIX_PDN_FLG                       GPC_M4_MIX_PDN_FLG_REG(GPC_BASE_PTR)
19107 #define GPC_M4_PU_PDN_FLG                        GPC_M4_PU_PDN_FLG_REG(GPC_BASE_PTR)
19108 /* GPC - Register array accessors */
19109 #define GPC_SLT_CFG(index)                       GPC_SLT_CFG_REG(GPC_BASE_PTR,index)
19110 #define GPC_A7_PU_PGC_PUP_STATUS(index)          GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,index)
19111 #define GPC_M4_PU_PGC_PUP_STATUS(index)          GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,index)
19112 #define GPC_A7_PU_PGC_PDN_STATUS(index)          GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,index)
19113 #define GPC_M4_PU_PGC_PDN_STATUS(index)          GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,index)
19114 /*!
19115  * @}
19116  */ /* end of group GPC_Register_Accessor_Macros */
19117 
19118 
19119 /*!
19120  * @}
19121  */ /* end of group GPC_Peripheral */
19122 
19123 /* ----------------------------------------------------------------------------
19124    -- GPC_PGC Peripheral Access Layer
19125    ---------------------------------------------------------------------------- */
19126 
19127 /*!
19128  * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer
19129  * @{
19130  */
19131 
19132 /** GPC_PGC - Register Layout Typedef */
19133 typedef struct {
19134   uint8_t RESERVED_0[2048];
19135   __IO  uint32_t A7CORE0_CTRL;                           /**< GPC PGC Control Register, offset: 0x800 */
19136   __IO  uint32_t A7CORE0_PUPSCR;                         /**< GPC PGC Up Sequence Control Register, offset: 0x804 */
19137   __IO  uint32_t A7CORE0_PDNSCR;                         /**< GPC PGC Down Sequence Control Register, offset: 0x808 */
19138   __IO  uint32_t A7CORE0_SR;                             /**< GPC PGC Status Register, offset: 0x80C */
19139   uint8_t RESERVED_1[48];
19140   __IO  uint32_t A7CORE1_CTRL;                           /**< GPC PGC Control Register, offset: 0x840 */
19141   __IO  uint32_t A7CORE1_PUPSCR;                         /**< GPC PGC Up Sequence Control Register, offset: 0x844 */
19142   __IO  uint32_t A7CORE1_PDNSCR;                         /**< GPC PGC Down Sequence Control Register, offset: 0x848 */
19143   __IO  uint32_t A7CORE1_SR;                             /**< GPC PGC Status Register, offset: 0x84C */
19144   uint8_t RESERVED_2[48];
19145   __IO  uint32_t A7SCU_CTRL;                             /**< GPC PGC Control Register, offset: 0x880 */
19146   __IO  uint32_t A7SCU_PUPSCR;                           /**< GPC PGC Up Sequence Control Register, offset: 0x884 */
19147   __IO  uint32_t A7SCU_PDNSCR;                           /**< GPC PGC Down Sequence Control Register, offset: 0x888 */
19148   __IO  uint32_t A7SCU_SR;                               /**< GPC PGC Status Register, offset: 0x88C */
19149   __IO  uint32_t SCU_AUXSW;                              /**< GPC PGC Auxiliary Power Switch SCU Control Register, offset: 0x890 */
19150   uint8_t RESERVED_3[364];
19151   __IO  uint32_t MIX_CTRL;                               /**< GPC PGC Control Register, offset: 0xA00 */
19152   __IO  uint32_t MIX_PUPSCR;                             /**< GPC PGC Up Sequence Control Register, offset: 0xA04 */
19153   __IO  uint32_t MIX_PDNSCR;                             /**< GPC PGC Down Sequence Control Register, offset: 0xA08 */
19154   __IO  uint32_t MIX_SR;                                 /**< GPC PGC Status Register, offset: 0xA0C */
19155   uint8_t RESERVED_4[496];
19156   __IO  uint32_t MIPI_CTRL;                              /**< GPC PGC Control Register, offset: 0xC00 */
19157   __IO  uint32_t MIPI_PUPSCR;                            /**< GPC PGC Up Sequence Control Register, offset: 0xC04 */
19158   __IO  uint32_t MIPI_PDNSCR;                            /**< GPC PGC Down Sequence Control Register, offset: 0xC08 */
19159   __IO  uint32_t MIPI_SR;                                /**< GPC PGC Status Register, offset: 0xC0C */
19160   __IO  uint32_t MIPI_AUXSW;                             /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xC10 */
19161   uint8_t RESERVED_5[44];
19162   __IO  uint32_t PCIE_CTRL;                              /**< GPC PGC Control Register, offset: 0xC40 */
19163   __IO  uint32_t PCIE_PUPSCR;                            /**< GPC PGC Up Sequence Control Register, offset: 0xC44 */
19164   __IO  uint32_t PCIE_PDNSCR;                            /**< GPC PGC Down Sequence Control Register, offset: 0xC48 */
19165   __IO  uint32_t PCIE_SR;                                /**< GPC PGC Status Register, offset: 0xC4C */
19166   __IO  uint32_t PCIE_AUXSW;                             /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xC50 */
19167   uint8_t RESERVED_6[172];
19168   __IO  uint32_t HSIC_CTRL;                              /**< GPC PGC Control Register, offset: 0xD00 */
19169   __IO  uint32_t HSIC_PUPSCR;                            /**< GPC PGC Up Sequence Control Register, offset: 0xD04 */
19170   __IO  uint32_t HSIC_PDNSCR;                            /**< GPC PGC Down Sequence Control Register, offset: 0xD08 */
19171   __IO  uint32_t HSIC_SR;                                /**< GPC PGC Status Register, offset: 0xD0C */
19172 } GPC_PGC_Type, *GPC_PGC_MemMapPtr;
19173 /* ----------------------------------------------------------------------------
19174    -- GPC_PGC - Register accessor macros
19175    ---------------------------------------------------------------------------- */
19176 
19177 /*!
19178  * @addtogroup GPC_PGC_Register_Accessor_Macros GPC_PGC - Register accessor macros
19179  * @{
19180  */
19181 
19182 
19183 /* GPC_PGC - Register accessors */
19184 #define GPC_PGC_A7CORE0_CTRL_REG(base)           ((base)->A7CORE0_CTRL)
19185 #define GPC_PGC_A7CORE0_PUPSCR_REG(base)         ((base)->A7CORE0_PUPSCR)
19186 #define GPC_PGC_A7CORE0_PDNSCR_REG(base)         ((base)->A7CORE0_PDNSCR)
19187 #define GPC_PGC_A7CORE0_SR_REG(base)             ((base)->A7CORE0_SR)
19188 #define GPC_PGC_A7CORE1_CTRL_REG(base)           ((base)->A7CORE1_CTRL)
19189 #define GPC_PGC_A7CORE1_PUPSCR_REG(base)         ((base)->A7CORE1_PUPSCR)
19190 #define GPC_PGC_A7CORE1_PDNSCR_REG(base)         ((base)->A7CORE1_PDNSCR)
19191 #define GPC_PGC_A7CORE1_SR_REG(base)             ((base)->A7CORE1_SR)
19192 #define GPC_PGC_A7SCU_CTRL_REG(base)             ((base)->A7SCU_CTRL)
19193 #define GPC_PGC_A7SCU_PUPSCR_REG(base)           ((base)->A7SCU_PUPSCR)
19194 #define GPC_PGC_A7SCU_PDNSCR_REG(base)           ((base)->A7SCU_PDNSCR)
19195 #define GPC_PGC_A7SCU_SR_REG(base)               ((base)->A7SCU_SR)
19196 #define GPC_PGC_SCU_AUXSW_REG(base)              ((base)->SCU_AUXSW)
19197 #define GPC_PGC_MIX_CTRL_REG(base)               ((base)->MIX_CTRL)
19198 #define GPC_PGC_MIX_PUPSCR_REG(base)             ((base)->MIX_PUPSCR)
19199 #define GPC_PGC_MIX_PDNSCR_REG(base)             ((base)->MIX_PDNSCR)
19200 #define GPC_PGC_MIX_SR_REG(base)                 ((base)->MIX_SR)
19201 #define GPC_PGC_MIPI_CTRL_REG(base)              ((base)->MIPI_CTRL)
19202 #define GPC_PGC_MIPI_PUPSCR_REG(base)            ((base)->MIPI_PUPSCR)
19203 #define GPC_PGC_MIPI_PDNSCR_REG(base)            ((base)->MIPI_PDNSCR)
19204 #define GPC_PGC_MIPI_SR_REG(base)                ((base)->MIPI_SR)
19205 #define GPC_PGC_MIPI_AUXSW_REG(base)             ((base)->MIPI_AUXSW)
19206 #define GPC_PGC_PCIE_CTRL_REG(base)              ((base)->PCIE_CTRL)
19207 #define GPC_PGC_PCIE_PUPSCR_REG(base)            ((base)->PCIE_PUPSCR)
19208 #define GPC_PGC_PCIE_PDNSCR_REG(base)            ((base)->PCIE_PDNSCR)
19209 #define GPC_PGC_PCIE_SR_REG(base)                ((base)->PCIE_SR)
19210 #define GPC_PGC_PCIE_AUXSW_REG(base)             ((base)->PCIE_AUXSW)
19211 #define GPC_PGC_HSIC_CTRL_REG(base)              ((base)->HSIC_CTRL)
19212 #define GPC_PGC_HSIC_PUPSCR_REG(base)            ((base)->HSIC_PUPSCR)
19213 #define GPC_PGC_HSIC_PDNSCR_REG(base)            ((base)->HSIC_PDNSCR)
19214 #define GPC_PGC_HSIC_SR_REG(base)                ((base)->HSIC_SR)
19215 
19216 /*!
19217  * @}
19218  */ /* end of group GPC_PGC_Register_Accessor_Macros */
19219 /* ----------------------------------------------------------------------------
19220    -- GPC_PGC Register Masks
19221    ---------------------------------------------------------------------------- */
19222 
19223 /*!
19224  * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks
19225  * @{
19226  */
19227 
19228 /* A7CORE0_CTRL Bit Fields */
19229 #define GPC_PGC_A7CORE0_CTRL_PCR_MASK            0x1u
19230 #define GPC_PGC_A7CORE0_CTRL_PCR_SHIFT           0
19231 #define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_MASK       0x7Eu
19232 #define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_SHIFT      1
19233 #define GPC_PGC_A7CORE0_CTRL_L2RSTDIS(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_A7CORE0_CTRL_L2RSTDIS_MASK)
19234 #define GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_MASK    0x3F00u
19235 #define GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_SHIFT   8
19236 #define GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1(x)      (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_MASK)
19237 #define GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u
19238 #define GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT 16
19239 #define GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_MASK)
19240 #define GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19241 #define GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19242 #define GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19243 /* A7CORE0_PUPSCR Bit Fields */
19244 #define GPC_PGC_A7CORE0_PUPSCR_SW_MASK           0x3Fu
19245 #define GPC_PGC_A7CORE0_PUPSCR_SW_SHIFT          0
19246 #define GPC_PGC_A7CORE0_PUPSCR_SW(x)             (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PUPSCR_SW_SHIFT))&GPC_PGC_A7CORE0_PUPSCR_SW_MASK)
19247 #define GPC_PGC_A7CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19248 #define GPC_PGC_A7CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19249 #define GPC_PGC_A7CORE0_PUPSCR_SW2ISO_MASK       0x7FFF80u
19250 #define GPC_PGC_A7CORE0_PUPSCR_SW2ISO_SHIFT      7
19251 #define GPC_PGC_A7CORE0_PUPSCR_SW2ISO(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_A7CORE0_PUPSCR_SW2ISO_MASK)
19252 #define GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19253 #define GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19254 #define GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19255 /* A7CORE0_PDNSCR Bit Fields */
19256 #define GPC_PGC_A7CORE0_PDNSCR_ISO_MASK          0x3Fu
19257 #define GPC_PGC_A7CORE0_PDNSCR_ISO_SHIFT         0
19258 #define GPC_PGC_A7CORE0_PDNSCR_ISO(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_ISO_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_ISO_MASK)
19259 #define GPC_PGC_A7CORE0_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19260 #define GPC_PGC_A7CORE0_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19261 #define GPC_PGC_A7CORE0_PDNSCR_ISO2SW_MASK       0x3F00u
19262 #define GPC_PGC_A7CORE0_PDNSCR_ISO2SW_SHIFT      8
19263 #define GPC_PGC_A7CORE0_PDNSCR_ISO2SW(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_ISO2SW_MASK)
19264 #define GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19265 #define GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19266 #define GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19267 #define GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19268 #define GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19269 #define GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19270 /* A7CORE0_SR Bit Fields */
19271 #define GPC_PGC_A7CORE0_SR_PSR_MASK              0x1u
19272 #define GPC_PGC_A7CORE0_SR_PSR_SHIFT             0
19273 #define GPC_PGC_A7CORE0_SR_L2RETN_FLAG_MASK      0x2u
19274 #define GPC_PGC_A7CORE0_SR_L2RETN_FLAG_SHIFT     1
19275 #define GPC_PGC_A7CORE0_SR_ALLOFF_FLAG_MASK      0x4u
19276 #define GPC_PGC_A7CORE0_SR_ALLOFF_FLAG_SHIFT     2
19277 #define GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_MASK  0x78u
19278 #define GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_SHIFT 3
19279 #define GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL(x)    (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_MASK)
19280 #define GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19281 #define GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19282 #define GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19283 /* A7CORE1_CTRL Bit Fields */
19284 #define GPC_PGC_A7CORE1_CTRL_PCR_MASK            0x1u
19285 #define GPC_PGC_A7CORE1_CTRL_PCR_SHIFT           0
19286 #define GPC_PGC_A7CORE1_CTRL_L2RSTDIS_MASK       0x7Eu
19287 #define GPC_PGC_A7CORE1_CTRL_L2RSTDIS_SHIFT      1
19288 #define GPC_PGC_A7CORE1_CTRL_L2RSTDIS(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_A7CORE1_CTRL_L2RSTDIS_MASK)
19289 #define GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_MASK    0x3F00u
19290 #define GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_SHIFT   8
19291 #define GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1(x)      (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_MASK)
19292 #define GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u
19293 #define GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT 16
19294 #define GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_MASK)
19295 #define GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19296 #define GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19297 #define GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19298 /* A7CORE1_PUPSCR Bit Fields */
19299 #define GPC_PGC_A7CORE1_PUPSCR_SW_MASK           0x3Fu
19300 #define GPC_PGC_A7CORE1_PUPSCR_SW_SHIFT          0
19301 #define GPC_PGC_A7CORE1_PUPSCR_SW(x)             (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PUPSCR_SW_SHIFT))&GPC_PGC_A7CORE1_PUPSCR_SW_MASK)
19302 #define GPC_PGC_A7CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19303 #define GPC_PGC_A7CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19304 #define GPC_PGC_A7CORE1_PUPSCR_SW2ISO_MASK       0x7FFF80u
19305 #define GPC_PGC_A7CORE1_PUPSCR_SW2ISO_SHIFT      7
19306 #define GPC_PGC_A7CORE1_PUPSCR_SW2ISO(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_A7CORE1_PUPSCR_SW2ISO_MASK)
19307 #define GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19308 #define GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19309 #define GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19310 /* A7CORE1_PDNSCR Bit Fields */
19311 #define GPC_PGC_A7CORE1_PDNSCR_ISO_MASK          0x3Fu
19312 #define GPC_PGC_A7CORE1_PDNSCR_ISO_SHIFT         0
19313 #define GPC_PGC_A7CORE1_PDNSCR_ISO(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_ISO_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_ISO_MASK)
19314 #define GPC_PGC_A7CORE1_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19315 #define GPC_PGC_A7CORE1_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19316 #define GPC_PGC_A7CORE1_PDNSCR_ISO2SW_MASK       0x3F00u
19317 #define GPC_PGC_A7CORE1_PDNSCR_ISO2SW_SHIFT      8
19318 #define GPC_PGC_A7CORE1_PDNSCR_ISO2SW(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_ISO2SW_MASK)
19319 #define GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19320 #define GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19321 #define GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19322 #define GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19323 #define GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19324 #define GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19325 /* A7CORE1_SR Bit Fields */
19326 #define GPC_PGC_A7CORE1_SR_PSR_MASK              0x1u
19327 #define GPC_PGC_A7CORE1_SR_PSR_SHIFT             0
19328 #define GPC_PGC_A7CORE1_SR_L2RETN_FLAG_MASK      0x2u
19329 #define GPC_PGC_A7CORE1_SR_L2RETN_FLAG_SHIFT     1
19330 #define GPC_PGC_A7CORE1_SR_ALLOFF_FLAG_MASK      0x4u
19331 #define GPC_PGC_A7CORE1_SR_ALLOFF_FLAG_SHIFT     2
19332 #define GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_MASK  0x78u
19333 #define GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_SHIFT 3
19334 #define GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL(x)    (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_MASK)
19335 #define GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19336 #define GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19337 #define GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19338 /* A7SCU_CTRL Bit Fields */
19339 #define GPC_PGC_A7SCU_CTRL_PCR_MASK              0x1u
19340 #define GPC_PGC_A7SCU_CTRL_PCR_SHIFT             0
19341 #define GPC_PGC_A7SCU_CTRL_L2RSTDIS_MASK         0x7Eu
19342 #define GPC_PGC_A7SCU_CTRL_L2RSTDIS_SHIFT        1
19343 #define GPC_PGC_A7SCU_CTRL_L2RSTDIS(x)           (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_A7SCU_CTRL_L2RSTDIS_MASK)
19344 #define GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_MASK      0x3F00u
19345 #define GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_SHIFT     8
19346 #define GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1(x)        (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_MASK)
19347 #define GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_MASK  0x3F0000u
19348 #define GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_SHIFT 16
19349 #define GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR(x)    (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_MASK)
19350 #define GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19351 #define GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19352 #define GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19353 /* A7SCU_PUPSCR Bit Fields */
19354 #define GPC_PGC_A7SCU_PUPSCR_SW_MASK             0x3Fu
19355 #define GPC_PGC_A7SCU_PUPSCR_SW_SHIFT            0
19356 #define GPC_PGC_A7SCU_PUPSCR_SW(x)               (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PUPSCR_SW_SHIFT))&GPC_PGC_A7SCU_PUPSCR_SW_MASK)
19357 #define GPC_PGC_A7SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19358 #define GPC_PGC_A7SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19359 #define GPC_PGC_A7SCU_PUPSCR_SW2ISO_MASK         0x7FFF80u
19360 #define GPC_PGC_A7SCU_PUPSCR_SW2ISO_SHIFT        7
19361 #define GPC_PGC_A7SCU_PUPSCR_SW2ISO(x)           (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_A7SCU_PUPSCR_SW2ISO_MASK)
19362 #define GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19363 #define GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19364 #define GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19365 /* A7SCU_PDNSCR Bit Fields */
19366 #define GPC_PGC_A7SCU_PDNSCR_ISO_MASK            0x3Fu
19367 #define GPC_PGC_A7SCU_PDNSCR_ISO_SHIFT           0
19368 #define GPC_PGC_A7SCU_PDNSCR_ISO(x)              (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_ISO_SHIFT))&GPC_PGC_A7SCU_PDNSCR_ISO_MASK)
19369 #define GPC_PGC_A7SCU_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19370 #define GPC_PGC_A7SCU_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19371 #define GPC_PGC_A7SCU_PDNSCR_ISO2SW_MASK         0x3F00u
19372 #define GPC_PGC_A7SCU_PDNSCR_ISO2SW_SHIFT        8
19373 #define GPC_PGC_A7SCU_PDNSCR_ISO2SW(x)           (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_A7SCU_PDNSCR_ISO2SW_MASK)
19374 #define GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19375 #define GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19376 #define GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19377 #define GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19378 #define GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19379 #define GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19380 /* A7SCU_SR Bit Fields */
19381 #define GPC_PGC_A7SCU_SR_PSR_MASK                0x1u
19382 #define GPC_PGC_A7SCU_SR_PSR_SHIFT               0
19383 #define GPC_PGC_A7SCU_SR_L2RETN_FLAG_MASK        0x2u
19384 #define GPC_PGC_A7SCU_SR_L2RETN_FLAG_SHIFT       1
19385 #define GPC_PGC_A7SCU_SR_ALLOFF_FLAG_MASK        0x4u
19386 #define GPC_PGC_A7SCU_SR_ALLOFF_FLAG_SHIFT       2
19387 #define GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_MASK    0x78u
19388 #define GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_SHIFT   3
19389 #define GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL(x)      (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_MASK)
19390 #define GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19391 #define GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19392 #define GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19393 /* SCU_AUXSW Bit Fields */
19394 #define GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK 0x3FFu
19395 #define GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT 0
19396 #define GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT))&GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK)
19397 #define GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_MASK 0xFFC00u
19398 #define GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_SHIFT 10
19399 #define GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_SHIFT))&GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_MASK)
19400 #define GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_MASK   0x3FF00000u
19401 #define GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT  20
19402 #define GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC(x)     (((uint32_t)(((uint32_t)(x))<<GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT))&GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_MASK)
19403 /* MIX_CTRL Bit Fields */
19404 #define GPC_PGC_MIX_CTRL_PCR_MASK                0x1u
19405 #define GPC_PGC_MIX_CTRL_PCR_SHIFT               0
19406 #define GPC_PGC_MIX_CTRL_L2RSTDIS_MASK           0x7Eu
19407 #define GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT          1
19408 #define GPC_PGC_MIX_CTRL_L2RSTDIS(x)             (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_MIX_CTRL_L2RSTDIS_MASK)
19409 #define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK        0x3F00u
19410 #define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT       8
19411 #define GPC_PGC_MIX_CTRL_DFTRAM_TCD1(x)          (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK)
19412 #define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK    0x3F0000u
19413 #define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT   16
19414 #define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR(x)      (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK)
19415 #define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19416 #define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19417 #define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19418 /* MIX_PUPSCR Bit Fields */
19419 #define GPC_PGC_MIX_PUPSCR_SW_MASK               0x3Fu
19420 #define GPC_PGC_MIX_PUPSCR_SW_SHIFT              0
19421 #define GPC_PGC_MIX_PUPSCR_SW(x)                 (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PUPSCR_SW_SHIFT))&GPC_PGC_MIX_PUPSCR_SW_MASK)
19422 #define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19423 #define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19424 #define GPC_PGC_MIX_PUPSCR_SW2ISO_MASK           0x7FFF80u
19425 #define GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT          7
19426 #define GPC_PGC_MIX_PUPSCR_SW2ISO(x)             (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_MIX_PUPSCR_SW2ISO_MASK)
19427 #define GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19428 #define GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19429 #define GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT(x)   (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19430 /* MIX_PDNSCR Bit Fields */
19431 #define GPC_PGC_MIX_PDNSCR_ISO_MASK              0x3Fu
19432 #define GPC_PGC_MIX_PDNSCR_ISO_SHIFT             0
19433 #define GPC_PGC_MIX_PDNSCR_ISO(x)                (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_ISO_SHIFT))&GPC_PGC_MIX_PDNSCR_ISO_MASK)
19434 #define GPC_PGC_MIX_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19435 #define GPC_PGC_MIX_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19436 #define GPC_PGC_MIX_PDNSCR_ISO2SW_MASK           0x3F00u
19437 #define GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT          8
19438 #define GPC_PGC_MIX_PDNSCR_ISO2SW(x)             (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_MIX_PDNSCR_ISO2SW_MASK)
19439 #define GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19440 #define GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19441 #define GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT(x)   (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19442 #define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19443 #define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19444 #define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19445 /* MIX_SR Bit Fields */
19446 #define GPC_PGC_MIX_SR_PSR_MASK                  0x1u
19447 #define GPC_PGC_MIX_SR_PSR_SHIFT                 0
19448 #define GPC_PGC_MIX_SR_L2RETN_FLAG_MASK          0x2u
19449 #define GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT         1
19450 #define GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK          0x4u
19451 #define GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT         2
19452 #define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK      0x78u
19453 #define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT     3
19454 #define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK)
19455 #define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19456 #define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19457 #define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19458 /* MIPI_CTRL Bit Fields */
19459 #define GPC_PGC_MIPI_CTRL_PCR_MASK               0x1u
19460 #define GPC_PGC_MIPI_CTRL_PCR_SHIFT              0
19461 #define GPC_PGC_MIPI_CTRL_L2RSTDIS_MASK          0x7Eu
19462 #define GPC_PGC_MIPI_CTRL_L2RSTDIS_SHIFT         1
19463 #define GPC_PGC_MIPI_CTRL_L2RSTDIS(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_MIPI_CTRL_L2RSTDIS_MASK)
19464 #define GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_MASK       0x3F00u
19465 #define GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_SHIFT      8
19466 #define GPC_PGC_MIPI_CTRL_DFTRAM_TCD1(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_MASK)
19467 #define GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_MASK   0x3F0000u
19468 #define GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_SHIFT  16
19469 #define GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR(x)     (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_MASK)
19470 #define GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19471 #define GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19472 #define GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19473 /* MIPI_PUPSCR Bit Fields */
19474 #define GPC_PGC_MIPI_PUPSCR_SW_MASK              0x3Fu
19475 #define GPC_PGC_MIPI_PUPSCR_SW_SHIFT             0
19476 #define GPC_PGC_MIPI_PUPSCR_SW(x)                (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PUPSCR_SW_SHIFT))&GPC_PGC_MIPI_PUPSCR_SW_MASK)
19477 #define GPC_PGC_MIPI_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19478 #define GPC_PGC_MIPI_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19479 #define GPC_PGC_MIPI_PUPSCR_SW2ISO_MASK          0x7FFF80u
19480 #define GPC_PGC_MIPI_PUPSCR_SW2ISO_SHIFT         7
19481 #define GPC_PGC_MIPI_PUPSCR_SW2ISO(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_MIPI_PUPSCR_SW2ISO_MASK)
19482 #define GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19483 #define GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19484 #define GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19485 /* MIPI_PDNSCR Bit Fields */
19486 #define GPC_PGC_MIPI_PDNSCR_ISO_MASK             0x3Fu
19487 #define GPC_PGC_MIPI_PDNSCR_ISO_SHIFT            0
19488 #define GPC_PGC_MIPI_PDNSCR_ISO(x)               (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_ISO_SHIFT))&GPC_PGC_MIPI_PDNSCR_ISO_MASK)
19489 #define GPC_PGC_MIPI_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19490 #define GPC_PGC_MIPI_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19491 #define GPC_PGC_MIPI_PDNSCR_ISO2SW_MASK          0x3F00u
19492 #define GPC_PGC_MIPI_PDNSCR_ISO2SW_SHIFT         8
19493 #define GPC_PGC_MIPI_PDNSCR_ISO2SW(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_MIPI_PDNSCR_ISO2SW_MASK)
19494 #define GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19495 #define GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19496 #define GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19497 #define GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19498 #define GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19499 #define GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19500 /* MIPI_SR Bit Fields */
19501 #define GPC_PGC_MIPI_SR_PSR_MASK                 0x1u
19502 #define GPC_PGC_MIPI_SR_PSR_SHIFT                0
19503 #define GPC_PGC_MIPI_SR_L2RETN_FLAG_MASK         0x2u
19504 #define GPC_PGC_MIPI_SR_L2RETN_FLAG_SHIFT        1
19505 #define GPC_PGC_MIPI_SR_ALLOFF_FLAG_MASK         0x4u
19506 #define GPC_PGC_MIPI_SR_ALLOFF_FLAG_SHIFT        2
19507 #define GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_MASK     0x78u
19508 #define GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_SHIFT    3
19509 #define GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL(x)       (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_MASK)
19510 #define GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19511 #define GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19512 #define GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19513 /* MIPI_AUXSW Bit Fields */
19514 #define GPC_PGC_MIPI_AUXSW_SW2_MASK              0x3Fu
19515 #define GPC_PGC_MIPI_AUXSW_SW2_SHIFT             0
19516 #define GPC_PGC_MIPI_AUXSW_SW2(x)                (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_AUXSW_SW2_SHIFT))&GPC_PGC_MIPI_AUXSW_SW2_MASK)
19517 #define GPC_PGC_MIPI_AUXSW_ISO2SW2_MASK          0x3F00u
19518 #define GPC_PGC_MIPI_AUXSW_ISO2SW2_SHIFT         8
19519 #define GPC_PGC_MIPI_AUXSW_ISO2SW2(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_AUXSW_ISO2SW2_SHIFT))&GPC_PGC_MIPI_AUXSW_ISO2SW2_MASK)
19520 #define GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_MASK  0xF0000u
19521 #define GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_SHIFT 16
19522 #define GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL(x)    (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_SHIFT))&GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_MASK)
19523 /* PCIE_CTRL Bit Fields */
19524 #define GPC_PGC_PCIE_CTRL_PCR_MASK               0x1u
19525 #define GPC_PGC_PCIE_CTRL_PCR_SHIFT              0
19526 #define GPC_PGC_PCIE_CTRL_L2RSTDIS_MASK          0x7Eu
19527 #define GPC_PGC_PCIE_CTRL_L2RSTDIS_SHIFT         1
19528 #define GPC_PGC_PCIE_CTRL_L2RSTDIS(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_PCIE_CTRL_L2RSTDIS_MASK)
19529 #define GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_MASK       0x3F00u
19530 #define GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_SHIFT      8
19531 #define GPC_PGC_PCIE_CTRL_DFTRAM_TCD1(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_MASK)
19532 #define GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_MASK   0x3F0000u
19533 #define GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_SHIFT  16
19534 #define GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR(x)     (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_MASK)
19535 #define GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19536 #define GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19537 #define GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19538 /* PCIE_PUPSCR Bit Fields */
19539 #define GPC_PGC_PCIE_PUPSCR_SW_MASK              0x3Fu
19540 #define GPC_PGC_PCIE_PUPSCR_SW_SHIFT             0
19541 #define GPC_PGC_PCIE_PUPSCR_SW(x)                (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PUPSCR_SW_SHIFT))&GPC_PGC_PCIE_PUPSCR_SW_MASK)
19542 #define GPC_PGC_PCIE_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19543 #define GPC_PGC_PCIE_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19544 #define GPC_PGC_PCIE_PUPSCR_SW2ISO_MASK          0x7FFF80u
19545 #define GPC_PGC_PCIE_PUPSCR_SW2ISO_SHIFT         7
19546 #define GPC_PGC_PCIE_PUPSCR_SW2ISO(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_PCIE_PUPSCR_SW2ISO_MASK)
19547 #define GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19548 #define GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19549 #define GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19550 /* PCIE_PDNSCR Bit Fields */
19551 #define GPC_PGC_PCIE_PDNSCR_ISO_MASK             0x3Fu
19552 #define GPC_PGC_PCIE_PDNSCR_ISO_SHIFT            0
19553 #define GPC_PGC_PCIE_PDNSCR_ISO(x)               (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_ISO_SHIFT))&GPC_PGC_PCIE_PDNSCR_ISO_MASK)
19554 #define GPC_PGC_PCIE_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19555 #define GPC_PGC_PCIE_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19556 #define GPC_PGC_PCIE_PDNSCR_ISO2SW_MASK          0x3F00u
19557 #define GPC_PGC_PCIE_PDNSCR_ISO2SW_SHIFT         8
19558 #define GPC_PGC_PCIE_PDNSCR_ISO2SW(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_PCIE_PDNSCR_ISO2SW_MASK)
19559 #define GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19560 #define GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19561 #define GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19562 #define GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19563 #define GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19564 #define GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19565 /* PCIE_SR Bit Fields */
19566 #define GPC_PGC_PCIE_SR_PSR_MASK                 0x1u
19567 #define GPC_PGC_PCIE_SR_PSR_SHIFT                0
19568 #define GPC_PGC_PCIE_SR_L2RETN_FLAG_MASK         0x2u
19569 #define GPC_PGC_PCIE_SR_L2RETN_FLAG_SHIFT        1
19570 #define GPC_PGC_PCIE_SR_ALLOFF_FLAG_MASK         0x4u
19571 #define GPC_PGC_PCIE_SR_ALLOFF_FLAG_SHIFT        2
19572 #define GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_MASK     0x78u
19573 #define GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_SHIFT    3
19574 #define GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL(x)       (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_MASK)
19575 #define GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19576 #define GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19577 #define GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19578 /* PCIE_AUXSW Bit Fields */
19579 #define GPC_PGC_PCIE_AUXSW_SW2_MASK              0x3Fu
19580 #define GPC_PGC_PCIE_AUXSW_SW2_SHIFT             0
19581 #define GPC_PGC_PCIE_AUXSW_SW2(x)                (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_AUXSW_SW2_SHIFT))&GPC_PGC_PCIE_AUXSW_SW2_MASK)
19582 #define GPC_PGC_PCIE_AUXSW_ISO2SW2_MASK          0x3F00u
19583 #define GPC_PGC_PCIE_AUXSW_ISO2SW2_SHIFT         8
19584 #define GPC_PGC_PCIE_AUXSW_ISO2SW2(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_AUXSW_ISO2SW2_SHIFT))&GPC_PGC_PCIE_AUXSW_ISO2SW2_MASK)
19585 #define GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_MASK  0xF0000u
19586 #define GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_SHIFT 16
19587 #define GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL(x)    (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_SHIFT))&GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_MASK)
19588 /* HSIC_CTRL Bit Fields */
19589 #define GPC_PGC_HSIC_CTRL_PCR_MASK               0x1u
19590 #define GPC_PGC_HSIC_CTRL_PCR_SHIFT              0
19591 #define GPC_PGC_HSIC_CTRL_L2RSTDIS_MASK          0x7Eu
19592 #define GPC_PGC_HSIC_CTRL_L2RSTDIS_SHIFT         1
19593 #define GPC_PGC_HSIC_CTRL_L2RSTDIS(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_HSIC_CTRL_L2RSTDIS_MASK)
19594 #define GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_MASK       0x3F00u
19595 #define GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_SHIFT      8
19596 #define GPC_PGC_HSIC_CTRL_DFTRAM_TCD1(x)         (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_MASK)
19597 #define GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_MASK   0x3F0000u
19598 #define GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_SHIFT  16
19599 #define GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR(x)     (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_MASK)
19600 #define GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u
19601 #define GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24
19602 #define GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19603 /* HSIC_PUPSCR Bit Fields */
19604 #define GPC_PGC_HSIC_PUPSCR_SW_MASK              0x3Fu
19605 #define GPC_PGC_HSIC_PUPSCR_SW_SHIFT             0
19606 #define GPC_PGC_HSIC_PUPSCR_SW(x)                (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PUPSCR_SW_SHIFT))&GPC_PGC_HSIC_PUPSCR_SW_MASK)
19607 #define GPC_PGC_HSIC_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u
19608 #define GPC_PGC_HSIC_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6
19609 #define GPC_PGC_HSIC_PUPSCR_SW2ISO_MASK          0x7FFF80u
19610 #define GPC_PGC_HSIC_PUPSCR_SW2ISO_SHIFT         7
19611 #define GPC_PGC_HSIC_PUPSCR_SW2ISO(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_HSIC_PUPSCR_SW2ISO_MASK)
19612 #define GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u
19613 #define GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23
19614 #define GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_MASK)
19615 /* HSIC_PDNSCR Bit Fields */
19616 #define GPC_PGC_HSIC_PDNSCR_ISO_MASK             0x3Fu
19617 #define GPC_PGC_HSIC_PDNSCR_ISO_SHIFT            0
19618 #define GPC_PGC_HSIC_PDNSCR_ISO(x)               (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_ISO_SHIFT))&GPC_PGC_HSIC_PDNSCR_ISO_MASK)
19619 #define GPC_PGC_HSIC_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u
19620 #define GPC_PGC_HSIC_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7
19621 #define GPC_PGC_HSIC_PDNSCR_ISO2SW_MASK          0x3F00u
19622 #define GPC_PGC_HSIC_PDNSCR_ISO2SW_SHIFT         8
19623 #define GPC_PGC_HSIC_PDNSCR_ISO2SW(x)            (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_HSIC_PDNSCR_ISO2SW_MASK)
19624 #define GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u
19625 #define GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16
19626 #define GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT(x)  (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_MASK)
19627 #define GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u
19628 #define GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24
19629 #define GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19630 /* HSIC_SR Bit Fields */
19631 #define GPC_PGC_HSIC_SR_PSR_MASK                 0x1u
19632 #define GPC_PGC_HSIC_SR_PSR_SHIFT                0
19633 #define GPC_PGC_HSIC_SR_L2RETN_FLAG_MASK         0x2u
19634 #define GPC_PGC_HSIC_SR_L2RETN_FLAG_SHIFT        1
19635 #define GPC_PGC_HSIC_SR_ALLOFF_FLAG_MASK         0x4u
19636 #define GPC_PGC_HSIC_SR_ALLOFF_FLAG_SHIFT        2
19637 #define GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_MASK     0x78u
19638 #define GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_SHIFT    3
19639 #define GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL(x)       (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_MASK)
19640 #define GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u
19641 #define GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8
19642 #define GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19643 
19644 /*!
19645  * @}
19646  */ /* end of group GPC_PGC_Register_Masks */
19647 
19648 /* GPC_PGC - Peripheral instance base addresses */
19649 /** Peripheral GPC_PGC base address */
19650 #define GPC_PGC_BASE                             (0x303A0000u)
19651 /** Peripheral GPC_PGC base pointer */
19652 #define GPC_PGC                                  ((GPC_PGC_Type *)GPC_PGC_BASE)
19653 #define GPC_PGC_BASE_PTR                         (GPC_PGC)
19654 /** Array initializer of GPC_PGC peripheral base addresses */
19655 #define GPC_PGC_BASE_ADDRS                       { GPC_PGC_BASE }
19656 /** Array initializer of GPC_PGC peripheral base pointers */
19657 #define GPC_PGC_BASE_PTRS                        { GPC_PGC }
19658 /* ----------------------------------------------------------------------------
19659    -- GPC_PGC - Register accessor macros
19660    ---------------------------------------------------------------------------- */
19661 
19662 /*!
19663  * @addtogroup GPC_PGC_Register_Accessor_Macros GPC_PGC - Register accessor macros
19664  * @{
19665  */
19666 
19667 
19668 /* GPC_PGC - Register instance definitions */
19669 /* GPC_PGC */
19670 #define GPC_PGC_A7CORE0_CTRL                     GPC_PGC_A7CORE0_CTRL_REG(GPC_PGC_BASE_PTR)
19671 #define GPC_PGC_A7CORE0_PUPSCR                   GPC_PGC_A7CORE0_PUPSCR_REG(GPC_PGC_BASE_PTR)
19672 #define GPC_PGC_A7CORE0_PDNSCR                   GPC_PGC_A7CORE0_PDNSCR_REG(GPC_PGC_BASE_PTR)
19673 #define GPC_PGC_A7CORE0_SR                       GPC_PGC_A7CORE0_SR_REG(GPC_PGC_BASE_PTR)
19674 #define GPC_PGC_A7CORE1_CTRL                     GPC_PGC_A7CORE1_CTRL_REG(GPC_PGC_BASE_PTR)
19675 #define GPC_PGC_A7CORE1_PUPSCR                   GPC_PGC_A7CORE1_PUPSCR_REG(GPC_PGC_BASE_PTR)
19676 #define GPC_PGC_A7CORE1_PDNSCR                   GPC_PGC_A7CORE1_PDNSCR_REG(GPC_PGC_BASE_PTR)
19677 #define GPC_PGC_A7CORE1_SR                       GPC_PGC_A7CORE1_SR_REG(GPC_PGC_BASE_PTR)
19678 #define GPC_PGC_A7SCU_CTRL                       GPC_PGC_A7SCU_CTRL_REG(GPC_PGC_BASE_PTR)
19679 #define GPC_PGC_A7SCU_PUPSCR                     GPC_PGC_A7SCU_PUPSCR_REG(GPC_PGC_BASE_PTR)
19680 #define GPC_PGC_A7SCU_PDNSCR                     GPC_PGC_A7SCU_PDNSCR_REG(GPC_PGC_BASE_PTR)
19681 #define GPC_PGC_A7SCU_SR                         GPC_PGC_A7SCU_SR_REG(GPC_PGC_BASE_PTR)
19682 #define GPC_PGC_SCU_AUXSW                        GPC_PGC_SCU_AUXSW_REG(GPC_PGC_BASE_PTR)
19683 #define GPC_PGC_MIX_CTRL                         GPC_PGC_MIX_CTRL_REG(GPC_PGC_BASE_PTR)
19684 #define GPC_PGC_MIX_PUPSCR                       GPC_PGC_MIX_PUPSCR_REG(GPC_PGC_BASE_PTR)
19685 #define GPC_PGC_MIX_PDNSCR                       GPC_PGC_MIX_PDNSCR_REG(GPC_PGC_BASE_PTR)
19686 #define GPC_PGC_MIX_SR                           GPC_PGC_MIX_SR_REG(GPC_PGC_BASE_PTR)
19687 #define GPC_PGC_MIPI_CTRL                        GPC_PGC_MIPI_CTRL_REG(GPC_PGC_BASE_PTR)
19688 #define GPC_PGC_MIPI_PUPSCR                      GPC_PGC_MIPI_PUPSCR_REG(GPC_PGC_BASE_PTR)
19689 #define GPC_PGC_MIPI_PDNSCR                      GPC_PGC_MIPI_PDNSCR_REG(GPC_PGC_BASE_PTR)
19690 #define GPC_PGC_MIPI_SR                          GPC_PGC_MIPI_SR_REG(GPC_PGC_BASE_PTR)
19691 #define GPC_PGC_MIPI_AUXSW                       GPC_PGC_MIPI_AUXSW_REG(GPC_PGC_BASE_PTR)
19692 #define GPC_PGC_PCIE_CTRL                        GPC_PGC_PCIE_CTRL_REG(GPC_PGC_BASE_PTR)
19693 #define GPC_PGC_PCIE_PUPSCR                      GPC_PGC_PCIE_PUPSCR_REG(GPC_PGC_BASE_PTR)
19694 #define GPC_PGC_PCIE_PDNSCR                      GPC_PGC_PCIE_PDNSCR_REG(GPC_PGC_BASE_PTR)
19695 #define GPC_PGC_PCIE_SR                          GPC_PGC_PCIE_SR_REG(GPC_PGC_BASE_PTR)
19696 #define GPC_PGC_PCIE_AUXSW                       GPC_PGC_PCIE_AUXSW_REG(GPC_PGC_BASE_PTR)
19697 #define GPC_PGC_HSIC_CTRL                        GPC_PGC_HSIC_CTRL_REG(GPC_PGC_BASE_PTR)
19698 #define GPC_PGC_HSIC_PUPSCR                      GPC_PGC_HSIC_PUPSCR_REG(GPC_PGC_BASE_PTR)
19699 #define GPC_PGC_HSIC_PDNSCR                      GPC_PGC_HSIC_PDNSCR_REG(GPC_PGC_BASE_PTR)
19700 #define GPC_PGC_HSIC_SR                          GPC_PGC_HSIC_SR_REG(GPC_PGC_BASE_PTR)
19701 /*!
19702  * @}
19703  */ /* end of group GPC_PGC_Register_Accessor_Macros */
19704 
19705 
19706 /*!
19707  * @}
19708  */ /* end of group GPC_PGC_Peripheral */
19709 
19710 /* ----------------------------------------------------------------------------
19711    -- GPIO Peripheral Access Layer
19712    ---------------------------------------------------------------------------- */
19713 
19714 /*!
19715  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
19716  * @{
19717  */
19718 
19719 /** GPIO - Register Layout Typedef */
19720 typedef struct {
19721   __IO  uint32_t DR;                                     /**< GPIO data register, offset: 0x0 */
19722   __IO  uint32_t GDIR;                                   /**< GPIO direction register, offset: 0x4 */
19723   __I   uint32_t PSR;                                    /**< GPIO pad status register, offset: 0x8 */
19724   __IO  uint32_t ICR1;                                   /**< GPIO interrupt configuration register1, offset: 0xC */
19725   __IO  uint32_t ICR2;                                   /**< GPIO interrupt configuration register2, offset: 0x10 */
19726   __IO  uint32_t IMR;                                    /**< GPIO interrupt mask register, offset: 0x14 */
19727   __IO  uint32_t ISR;                                    /**< GPIO interrupt status register, offset: 0x18 */
19728   __IO  uint32_t EDGE_SEL;                               /**< GPIO edge select register, offset: 0x1C */
19729 } GPIO_Type, *GPIO_MemMapPtr;
19730 /* ----------------------------------------------------------------------------
19731    -- GPIO - Register accessor macros
19732    ---------------------------------------------------------------------------- */
19733 
19734 /*!
19735  * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
19736  * @{
19737  */
19738 
19739 
19740 /* GPIO - Register accessors */
19741 #define GPIO_DR_REG(base)                        ((base)->DR)
19742 #define GPIO_GDIR_REG(base)                      ((base)->GDIR)
19743 #define GPIO_PSR_REG(base)                       ((base)->PSR)
19744 #define GPIO_ICR1_REG(base)                      ((base)->ICR1)
19745 #define GPIO_ICR2_REG(base)                      ((base)->ICR2)
19746 #define GPIO_IMR_REG(base)                       ((base)->IMR)
19747 #define GPIO_ISR_REG(base)                       ((base)->ISR)
19748 #define GPIO_EDGE_SEL_REG(base)                  ((base)->EDGE_SEL)
19749 
19750 /*!
19751  * @}
19752  */ /* end of group GPIO_Register_Accessor_Macros */
19753 /* ----------------------------------------------------------------------------
19754    -- GPIO Register Masks
19755    ---------------------------------------------------------------------------- */
19756 
19757 /*!
19758  * @addtogroup GPIO_Register_Masks GPIO Register Masks
19759  * @{
19760  */
19761 
19762 /* DR Bit Fields */
19763 #define GPIO_DR_DR_MASK                          0xFFFFFFFFu
19764 #define GPIO_DR_DR_SHIFT                         0
19765 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x))<<GPIO_DR_DR_SHIFT))&GPIO_DR_DR_MASK)
19766 /* GDIR Bit Fields */
19767 #define GPIO_GDIR_GDIR_MASK                      0xFFFFFFFFu
19768 #define GPIO_GDIR_GDIR_SHIFT                     0
19769 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_GDIR_GDIR_SHIFT))&GPIO_GDIR_GDIR_MASK)
19770 /* PSR Bit Fields */
19771 #define GPIO_PSR_PSR_MASK                        0xFFFFFFFFu
19772 #define GPIO_PSR_PSR_SHIFT                       0
19773 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x))<<GPIO_PSR_PSR_SHIFT))&GPIO_PSR_PSR_MASK)
19774 /* ICR1 Bit Fields */
19775 #define GPIO_ICR1_ICR0_MASK                      0x3u
19776 #define GPIO_ICR1_ICR0_SHIFT                     0
19777 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR0_SHIFT))&GPIO_ICR1_ICR0_MASK)
19778 #define GPIO_ICR1_ICR1_MASK                      0xCu
19779 #define GPIO_ICR1_ICR1_SHIFT                     2
19780 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR1_SHIFT))&GPIO_ICR1_ICR1_MASK)
19781 #define GPIO_ICR1_ICR2_MASK                      0x30u
19782 #define GPIO_ICR1_ICR2_SHIFT                     4
19783 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR2_SHIFT))&GPIO_ICR1_ICR2_MASK)
19784 #define GPIO_ICR1_ICR3_MASK                      0xC0u
19785 #define GPIO_ICR1_ICR3_SHIFT                     6
19786 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR3_SHIFT))&GPIO_ICR1_ICR3_MASK)
19787 #define GPIO_ICR1_ICR4_MASK                      0x300u
19788 #define GPIO_ICR1_ICR4_SHIFT                     8
19789 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR4_SHIFT))&GPIO_ICR1_ICR4_MASK)
19790 #define GPIO_ICR1_ICR5_MASK                      0xC00u
19791 #define GPIO_ICR1_ICR5_SHIFT                     10
19792 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR5_SHIFT))&GPIO_ICR1_ICR5_MASK)
19793 #define GPIO_ICR1_ICR6_MASK                      0x3000u
19794 #define GPIO_ICR1_ICR6_SHIFT                     12
19795 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR6_SHIFT))&GPIO_ICR1_ICR6_MASK)
19796 #define GPIO_ICR1_ICR7_MASK                      0xC000u
19797 #define GPIO_ICR1_ICR7_SHIFT                     14
19798 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR7_SHIFT))&GPIO_ICR1_ICR7_MASK)
19799 #define GPIO_ICR1_ICR8_MASK                      0x30000u
19800 #define GPIO_ICR1_ICR8_SHIFT                     16
19801 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR8_SHIFT))&GPIO_ICR1_ICR8_MASK)
19802 #define GPIO_ICR1_ICR9_MASK                      0xC0000u
19803 #define GPIO_ICR1_ICR9_SHIFT                     18
19804 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR9_SHIFT))&GPIO_ICR1_ICR9_MASK)
19805 #define GPIO_ICR1_ICR10_MASK                     0x300000u
19806 #define GPIO_ICR1_ICR10_SHIFT                    20
19807 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR10_SHIFT))&GPIO_ICR1_ICR10_MASK)
19808 #define GPIO_ICR1_ICR11_MASK                     0xC00000u
19809 #define GPIO_ICR1_ICR11_SHIFT                    22
19810 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR11_SHIFT))&GPIO_ICR1_ICR11_MASK)
19811 #define GPIO_ICR1_ICR12_MASK                     0x3000000u
19812 #define GPIO_ICR1_ICR12_SHIFT                    24
19813 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR12_SHIFT))&GPIO_ICR1_ICR12_MASK)
19814 #define GPIO_ICR1_ICR13_MASK                     0xC000000u
19815 #define GPIO_ICR1_ICR13_SHIFT                    26
19816 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR13_SHIFT))&GPIO_ICR1_ICR13_MASK)
19817 #define GPIO_ICR1_ICR14_MASK                     0x30000000u
19818 #define GPIO_ICR1_ICR14_SHIFT                    28
19819 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR14_SHIFT))&GPIO_ICR1_ICR14_MASK)
19820 #define GPIO_ICR1_ICR15_MASK                     0xC0000000u
19821 #define GPIO_ICR1_ICR15_SHIFT                    30
19822 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR15_SHIFT))&GPIO_ICR1_ICR15_MASK)
19823 /* ICR2 Bit Fields */
19824 #define GPIO_ICR2_ICR16_MASK                     0x3u
19825 #define GPIO_ICR2_ICR16_SHIFT                    0
19826 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR16_SHIFT))&GPIO_ICR2_ICR16_MASK)
19827 #define GPIO_ICR2_ICR17_MASK                     0xCu
19828 #define GPIO_ICR2_ICR17_SHIFT                    2
19829 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR17_SHIFT))&GPIO_ICR2_ICR17_MASK)
19830 #define GPIO_ICR2_ICR18_MASK                     0x30u
19831 #define GPIO_ICR2_ICR18_SHIFT                    4
19832 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR18_SHIFT))&GPIO_ICR2_ICR18_MASK)
19833 #define GPIO_ICR2_ICR19_MASK                     0xC0u
19834 #define GPIO_ICR2_ICR19_SHIFT                    6
19835 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR19_SHIFT))&GPIO_ICR2_ICR19_MASK)
19836 #define GPIO_ICR2_ICR20_MASK                     0x300u
19837 #define GPIO_ICR2_ICR20_SHIFT                    8
19838 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR20_SHIFT))&GPIO_ICR2_ICR20_MASK)
19839 #define GPIO_ICR2_ICR21_MASK                     0xC00u
19840 #define GPIO_ICR2_ICR21_SHIFT                    10
19841 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR21_SHIFT))&GPIO_ICR2_ICR21_MASK)
19842 #define GPIO_ICR2_ICR22_MASK                     0x3000u
19843 #define GPIO_ICR2_ICR22_SHIFT                    12
19844 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR22_SHIFT))&GPIO_ICR2_ICR22_MASK)
19845 #define GPIO_ICR2_ICR23_MASK                     0xC000u
19846 #define GPIO_ICR2_ICR23_SHIFT                    14
19847 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR23_SHIFT))&GPIO_ICR2_ICR23_MASK)
19848 #define GPIO_ICR2_ICR24_MASK                     0x30000u
19849 #define GPIO_ICR2_ICR24_SHIFT                    16
19850 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR24_SHIFT))&GPIO_ICR2_ICR24_MASK)
19851 #define GPIO_ICR2_ICR25_MASK                     0xC0000u
19852 #define GPIO_ICR2_ICR25_SHIFT                    18
19853 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR25_SHIFT))&GPIO_ICR2_ICR25_MASK)
19854 #define GPIO_ICR2_ICR26_MASK                     0x300000u
19855 #define GPIO_ICR2_ICR26_SHIFT                    20
19856 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR26_SHIFT))&GPIO_ICR2_ICR26_MASK)
19857 #define GPIO_ICR2_ICR27_MASK                     0xC00000u
19858 #define GPIO_ICR2_ICR27_SHIFT                    22
19859 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR27_SHIFT))&GPIO_ICR2_ICR27_MASK)
19860 #define GPIO_ICR2_ICR28_MASK                     0x3000000u
19861 #define GPIO_ICR2_ICR28_SHIFT                    24
19862 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR28_SHIFT))&GPIO_ICR2_ICR28_MASK)
19863 #define GPIO_ICR2_ICR29_MASK                     0xC000000u
19864 #define GPIO_ICR2_ICR29_SHIFT                    26
19865 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR29_SHIFT))&GPIO_ICR2_ICR29_MASK)
19866 #define GPIO_ICR2_ICR30_MASK                     0x30000000u
19867 #define GPIO_ICR2_ICR30_SHIFT                    28
19868 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR30_SHIFT))&GPIO_ICR2_ICR30_MASK)
19869 #define GPIO_ICR2_ICR31_MASK                     0xC0000000u
19870 #define GPIO_ICR2_ICR31_SHIFT                    30
19871 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR31_SHIFT))&GPIO_ICR2_ICR31_MASK)
19872 /* IMR Bit Fields */
19873 #define GPIO_IMR_IMR_MASK                        0xFFFFFFFFu
19874 #define GPIO_IMR_IMR_SHIFT                       0
19875 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x))<<GPIO_IMR_IMR_SHIFT))&GPIO_IMR_IMR_MASK)
19876 /* ISR Bit Fields */
19877 #define GPIO_ISR_ISR_MASK                        0xFFFFFFFFu
19878 #define GPIO_ISR_ISR_SHIFT                       0
19879 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x))<<GPIO_ISR_ISR_SHIFT))&GPIO_ISR_ISR_MASK)
19880 /* EDGE_SEL Bit Fields */
19881 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         0xFFFFFFFFu
19882 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        0
19883 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x))<<GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT))&GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
19884 
19885 /*!
19886  * @}
19887  */ /* end of group GPIO_Register_Masks */
19888 
19889 /* GPIO - Peripheral instance base addresses */
19890 /** Peripheral GPIO1 base address */
19891 #define GPIO1_BASE                               (0x30200000u)
19892 /** Peripheral GPIO1 base pointer */
19893 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
19894 #define GPIO1_BASE_PTR                           (GPIO1)
19895 /** Peripheral GPIO2 base address */
19896 #define GPIO2_BASE                               (0x30210000u)
19897 /** Peripheral GPIO2 base pointer */
19898 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
19899 #define GPIO2_BASE_PTR                           (GPIO2)
19900 /** Peripheral GPIO3 base address */
19901 #define GPIO3_BASE                               (0x30220000u)
19902 /** Peripheral GPIO3 base pointer */
19903 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
19904 #define GPIO3_BASE_PTR                           (GPIO3)
19905 /** Peripheral GPIO4 base address */
19906 #define GPIO4_BASE                               (0x30230000u)
19907 /** Peripheral GPIO4 base pointer */
19908 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
19909 #define GPIO4_BASE_PTR                           (GPIO4)
19910 /** Peripheral GPIO5 base address */
19911 #define GPIO5_BASE                               (0x30240000u)
19912 /** Peripheral GPIO5 base pointer */
19913 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
19914 #define GPIO5_BASE_PTR                           (GPIO5)
19915 /** Peripheral GPIO6 base address */
19916 #define GPIO6_BASE                               (0x30250000u)
19917 /** Peripheral GPIO6 base pointer */
19918 #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
19919 #define GPIO6_BASE_PTR                           (GPIO6)
19920 /** Peripheral GPIO7 base address */
19921 #define GPIO7_BASE                               (0x30260000u)
19922 /** Peripheral GPIO7 base pointer */
19923 #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
19924 #define GPIO7_BASE_PTR                           (GPIO7)
19925 /** Array initializer of GPIO peripheral base addresses */
19926 #define GPIO_BASE_ADDRS                          { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE }
19927 /** Array initializer of GPIO peripheral base pointers */
19928 #define GPIO_BASE_PTRS                           { GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7 }
19929 /* ----------------------------------------------------------------------------
19930    -- GPIO - Register accessor macros
19931    ---------------------------------------------------------------------------- */
19932 
19933 /*!
19934  * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
19935  * @{
19936  */
19937 
19938 
19939 /* GPIO - Register instance definitions */
19940 /* GPIO1 */
19941 #define GPIO1_DR                                 GPIO_DR_REG(GPIO1_BASE_PTR)
19942 #define GPIO1_GDIR                               GPIO_GDIR_REG(GPIO1_BASE_PTR)
19943 #define GPIO1_PSR                                GPIO_PSR_REG(GPIO1_BASE_PTR)
19944 #define GPIO1_ICR1                               GPIO_ICR1_REG(GPIO1_BASE_PTR)
19945 #define GPIO1_ICR2                               GPIO_ICR2_REG(GPIO1_BASE_PTR)
19946 #define GPIO1_IMR                                GPIO_IMR_REG(GPIO1_BASE_PTR)
19947 #define GPIO1_ISR                                GPIO_ISR_REG(GPIO1_BASE_PTR)
19948 #define GPIO1_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO1_BASE_PTR)
19949 /* GPIO2 */
19950 #define GPIO2_DR                                 GPIO_DR_REG(GPIO2_BASE_PTR)
19951 #define GPIO2_GDIR                               GPIO_GDIR_REG(GPIO2_BASE_PTR)
19952 #define GPIO2_PSR                                GPIO_PSR_REG(GPIO2_BASE_PTR)
19953 #define GPIO2_ICR1                               GPIO_ICR1_REG(GPIO2_BASE_PTR)
19954 #define GPIO2_ICR2                               GPIO_ICR2_REG(GPIO2_BASE_PTR)
19955 #define GPIO2_IMR                                GPIO_IMR_REG(GPIO2_BASE_PTR)
19956 #define GPIO2_ISR                                GPIO_ISR_REG(GPIO2_BASE_PTR)
19957 #define GPIO2_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO2_BASE_PTR)
19958 /* GPIO3 */
19959 #define GPIO3_DR                                 GPIO_DR_REG(GPIO3_BASE_PTR)
19960 #define GPIO3_GDIR                               GPIO_GDIR_REG(GPIO3_BASE_PTR)
19961 #define GPIO3_PSR                                GPIO_PSR_REG(GPIO3_BASE_PTR)
19962 #define GPIO3_ICR1                               GPIO_ICR1_REG(GPIO3_BASE_PTR)
19963 #define GPIO3_ICR2                               GPIO_ICR2_REG(GPIO3_BASE_PTR)
19964 #define GPIO3_IMR                                GPIO_IMR_REG(GPIO3_BASE_PTR)
19965 #define GPIO3_ISR                                GPIO_ISR_REG(GPIO3_BASE_PTR)
19966 #define GPIO3_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO3_BASE_PTR)
19967 /* GPIO4 */
19968 #define GPIO4_DR                                 GPIO_DR_REG(GPIO4_BASE_PTR)
19969 #define GPIO4_GDIR                               GPIO_GDIR_REG(GPIO4_BASE_PTR)
19970 #define GPIO4_PSR                                GPIO_PSR_REG(GPIO4_BASE_PTR)
19971 #define GPIO4_ICR1                               GPIO_ICR1_REG(GPIO4_BASE_PTR)
19972 #define GPIO4_ICR2                               GPIO_ICR2_REG(GPIO4_BASE_PTR)
19973 #define GPIO4_IMR                                GPIO_IMR_REG(GPIO4_BASE_PTR)
19974 #define GPIO4_ISR                                GPIO_ISR_REG(GPIO4_BASE_PTR)
19975 #define GPIO4_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO4_BASE_PTR)
19976 /* GPIO5 */
19977 #define GPIO5_DR                                 GPIO_DR_REG(GPIO5_BASE_PTR)
19978 #define GPIO5_GDIR                               GPIO_GDIR_REG(GPIO5_BASE_PTR)
19979 #define GPIO5_PSR                                GPIO_PSR_REG(GPIO5_BASE_PTR)
19980 #define GPIO5_ICR1                               GPIO_ICR1_REG(GPIO5_BASE_PTR)
19981 #define GPIO5_ICR2                               GPIO_ICR2_REG(GPIO5_BASE_PTR)
19982 #define GPIO5_IMR                                GPIO_IMR_REG(GPIO5_BASE_PTR)
19983 #define GPIO5_ISR                                GPIO_ISR_REG(GPIO5_BASE_PTR)
19984 #define GPIO5_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO5_BASE_PTR)
19985 /* GPIO6 */
19986 #define GPIO6_DR                                 GPIO_DR_REG(GPIO6_BASE_PTR)
19987 #define GPIO6_GDIR                               GPIO_GDIR_REG(GPIO6_BASE_PTR)
19988 #define GPIO6_PSR                                GPIO_PSR_REG(GPIO6_BASE_PTR)
19989 #define GPIO6_ICR1                               GPIO_ICR1_REG(GPIO6_BASE_PTR)
19990 #define GPIO6_ICR2                               GPIO_ICR2_REG(GPIO6_BASE_PTR)
19991 #define GPIO6_IMR                                GPIO_IMR_REG(GPIO6_BASE_PTR)
19992 #define GPIO6_ISR                                GPIO_ISR_REG(GPIO6_BASE_PTR)
19993 #define GPIO6_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO6_BASE_PTR)
19994 /* GPIO7 */
19995 #define GPIO7_DR                                 GPIO_DR_REG(GPIO7_BASE_PTR)
19996 #define GPIO7_GDIR                               GPIO_GDIR_REG(GPIO7_BASE_PTR)
19997 #define GPIO7_PSR                                GPIO_PSR_REG(GPIO7_BASE_PTR)
19998 #define GPIO7_ICR1                               GPIO_ICR1_REG(GPIO7_BASE_PTR)
19999 #define GPIO7_ICR2                               GPIO_ICR2_REG(GPIO7_BASE_PTR)
20000 #define GPIO7_IMR                                GPIO_IMR_REG(GPIO7_BASE_PTR)
20001 #define GPIO7_ISR                                GPIO_ISR_REG(GPIO7_BASE_PTR)
20002 #define GPIO7_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO7_BASE_PTR)
20003 /*!
20004  * @}
20005  */ /* end of group GPIO_Register_Accessor_Macros */
20006 
20007 
20008 /*!
20009  * @}
20010  */ /* end of group GPIO_Peripheral */
20011 
20012 /* ----------------------------------------------------------------------------
20013    -- GPMI Peripheral Access Layer
20014    ---------------------------------------------------------------------------- */
20015 
20016 /*!
20017  * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
20018  * @{
20019  */
20020 
20021 /** GPMI - Register Layout Typedef */
20022 typedef struct {
20023   __IO  uint32_t CTRL0;                                  /**< GPMI Control Register 0 Description, offset: 0x0 */
20024   __IO  uint32_t CTRL0_SET;                              /**< GPMI Control Register 0 Description, offset: 0x4 */
20025   __IO  uint32_t CTRL0_CLR;                              /**< GPMI Control Register 0 Description, offset: 0x8 */
20026   __IO  uint32_t CTRL0_TOG;                              /**< GPMI Control Register 0 Description, offset: 0xC */
20027   __IO  uint32_t COMPARE;                                /**< GPMI Compare Register Description, offset: 0x10 */
20028   uint8_t RESERVED_0[12];
20029   __IO  uint32_t ECCCTRL;                                /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
20030   __IO  uint32_t ECCCTRL_SET;                            /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
20031   __IO  uint32_t ECCCTRL_CLR;                            /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
20032   __IO  uint32_t ECCCTRL_TOG;                            /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
20033   __IO  uint32_t ECCCOUNT;                               /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
20034   uint8_t RESERVED_1[12];
20035   __IO  uint32_t PAYLOAD;                                /**< GPMI Payload Address Register Description, offset: 0x40 */
20036   uint8_t RESERVED_2[12];
20037   __IO  uint32_t AUXILIARY;                              /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
20038   uint8_t RESERVED_3[12];
20039   __IO  uint32_t CTRL1;                                  /**< GPMI Control Register 1 Description, offset: 0x60 */
20040   __IO  uint32_t CTRL1_SET;                              /**< GPMI Control Register 1 Description, offset: 0x64 */
20041   __IO  uint32_t CTRL1_CLR;                              /**< GPMI Control Register 1 Description, offset: 0x68 */
20042   __IO  uint32_t CTRL1_TOG;                              /**< GPMI Control Register 1 Description, offset: 0x6C */
20043   __IO  uint32_t TIMING0;                                /**< GPMI Timing Register 0 Description, offset: 0x70 */
20044   uint8_t RESERVED_4[12];
20045   __IO  uint32_t TIMING1;                                /**< GPMI Timing Register 1 Description, offset: 0x80 */
20046   uint8_t RESERVED_5[12];
20047   __IO  uint32_t TIMING2;                                /**< GPMI Timing Register 2 Description, offset: 0x90 */
20048   uint8_t RESERVED_6[12];
20049   __IO  uint32_t DATA;                                   /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
20050   uint8_t RESERVED_7[12];
20051   __I   uint32_t STAT;                                   /**< GPMI Status Register Description, offset: 0xB0 */
20052   uint8_t RESERVED_8[12];
20053   __I   uint32_t DEBUG;                                  /**< GPMI Debug Information Register Description, offset: 0xC0 */
20054   uint8_t RESERVED_9[12];
20055   __I   uint32_t VERSION;                                /**< GPMI Version Register Description, offset: 0xD0 */
20056   uint8_t RESERVED_10[12];
20057   __IO  uint32_t DEBUG2;                                 /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
20058   uint8_t RESERVED_11[12];
20059   __I   uint32_t DEBUG3;                                 /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
20060   uint8_t RESERVED_12[12];
20061   __IO  uint32_t READ_DDR_DLL_CTRL;                      /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
20062   uint8_t RESERVED_13[28];
20063   __I   uint32_t READ_DDR_DLL_STS;                       /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
20064 } GPMI_Type, *GPMI_MemMapPtr;
20065 /* ----------------------------------------------------------------------------
20066    -- GPMI - Register accessor macros
20067    ---------------------------------------------------------------------------- */
20068 
20069 /*!
20070  * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros
20071  * @{
20072  */
20073 
20074 
20075 /* GPMI - Register accessors */
20076 #define GPMI_CTRL0_REG(base)                     ((base)->CTRL0)
20077 #define GPMI_CTRL0_SET_REG(base)                 ((base)->CTRL0_SET)
20078 #define GPMI_CTRL0_CLR_REG(base)                 ((base)->CTRL0_CLR)
20079 #define GPMI_CTRL0_TOG_REG(base)                 ((base)->CTRL0_TOG)
20080 #define GPMI_COMPARE_REG(base)                   ((base)->COMPARE)
20081 #define GPMI_ECCCTRL_REG(base)                   ((base)->ECCCTRL)
20082 #define GPMI_ECCCTRL_SET_REG(base)               ((base)->ECCCTRL_SET)
20083 #define GPMI_ECCCTRL_CLR_REG(base)               ((base)->ECCCTRL_CLR)
20084 #define GPMI_ECCCTRL_TOG_REG(base)               ((base)->ECCCTRL_TOG)
20085 #define GPMI_ECCCOUNT_REG(base)                  ((base)->ECCCOUNT)
20086 #define GPMI_PAYLOAD_REG(base)                   ((base)->PAYLOAD)
20087 #define GPMI_AUXILIARY_REG(base)                 ((base)->AUXILIARY)
20088 #define GPMI_CTRL1_REG(base)                     ((base)->CTRL1)
20089 #define GPMI_CTRL1_SET_REG(base)                 ((base)->CTRL1_SET)
20090 #define GPMI_CTRL1_CLR_REG(base)                 ((base)->CTRL1_CLR)
20091 #define GPMI_CTRL1_TOG_REG(base)                 ((base)->CTRL1_TOG)
20092 #define GPMI_TIMING0_REG(base)                   ((base)->TIMING0)
20093 #define GPMI_TIMING1_REG(base)                   ((base)->TIMING1)
20094 #define GPMI_TIMING2_REG(base)                   ((base)->TIMING2)
20095 #define GPMI_DATA_REG(base)                      ((base)->DATA)
20096 #define GPMI_STAT_REG(base)                      ((base)->STAT)
20097 #define GPMI_DEBUG_REG(base)                     ((base)->DEBUG)
20098 #define GPMI_VERSION_REG(base)                   ((base)->VERSION)
20099 #define GPMI_DEBUG2_REG(base)                    ((base)->DEBUG2)
20100 #define GPMI_DEBUG3_REG(base)                    ((base)->DEBUG3)
20101 #define GPMI_READ_DDR_DLL_CTRL_REG(base)         ((base)->READ_DDR_DLL_CTRL)
20102 #define GPMI_READ_DDR_DLL_STS_REG(base)          ((base)->READ_DDR_DLL_STS)
20103 
20104 /*!
20105  * @}
20106  */ /* end of group GPMI_Register_Accessor_Macros */
20107 /* ----------------------------------------------------------------------------
20108    -- GPMI Register Masks
20109    ---------------------------------------------------------------------------- */
20110 
20111 /*!
20112  * @addtogroup GPMI_Register_Masks GPMI Register Masks
20113  * @{
20114  */
20115 
20116 /* CTRL0 Bit Fields */
20117 #define GPMI_CTRL0_XFER_COUNT_MASK               0xFFFFu
20118 #define GPMI_CTRL0_XFER_COUNT_SHIFT              0
20119 #define GPMI_CTRL0_XFER_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_XFER_COUNT_SHIFT))&GPMI_CTRL0_XFER_COUNT_MASK)
20120 #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK        0x10000u
20121 #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT       16
20122 #define GPMI_CTRL0_ADDRESS_MASK                  0xE0000u
20123 #define GPMI_CTRL0_ADDRESS_SHIFT                 17
20124 #define GPMI_CTRL0_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_ADDRESS_SHIFT))&GPMI_CTRL0_ADDRESS_MASK)
20125 #define GPMI_CTRL0_CS_MASK                       0x700000u
20126 #define GPMI_CTRL0_CS_SHIFT                      20
20127 #define GPMI_CTRL0_CS(x)                         (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CS_SHIFT))&GPMI_CTRL0_CS_MASK)
20128 #define GPMI_CTRL0_WORD_LENGTH_MASK              0x800000u
20129 #define GPMI_CTRL0_WORD_LENGTH_SHIFT             23
20130 #define GPMI_CTRL0_COMMAND_MODE_MASK             0x3000000u
20131 #define GPMI_CTRL0_COMMAND_MODE_SHIFT            24
20132 #define GPMI_CTRL0_COMMAND_MODE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_COMMAND_MODE_SHIFT))&GPMI_CTRL0_COMMAND_MODE_MASK)
20133 #define GPMI_CTRL0_UDMA_MASK                     0x4000000u
20134 #define GPMI_CTRL0_UDMA_SHIFT                    26
20135 #define GPMI_CTRL0_LOCK_CS_MASK                  0x8000000u
20136 #define GPMI_CTRL0_LOCK_CS_SHIFT                 27
20137 #define GPMI_CTRL0_DEV_IRQ_EN_MASK               0x10000000u
20138 #define GPMI_CTRL0_DEV_IRQ_EN_SHIFT              28
20139 #define GPMI_CTRL0_RUN_MASK                      0x20000000u
20140 #define GPMI_CTRL0_RUN_SHIFT                     29
20141 #define GPMI_CTRL0_CLKGATE_MASK                  0x40000000u
20142 #define GPMI_CTRL0_CLKGATE_SHIFT                 30
20143 #define GPMI_CTRL0_SFTRST_MASK                   0x80000000u
20144 #define GPMI_CTRL0_SFTRST_SHIFT                  31
20145 /* CTRL0_SET Bit Fields */
20146 #define GPMI_CTRL0_SET_XFER_COUNT_MASK           0xFFFFu
20147 #define GPMI_CTRL0_SET_XFER_COUNT_SHIFT          0
20148 #define GPMI_CTRL0_SET_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_XFER_COUNT_SHIFT))&GPMI_CTRL0_SET_XFER_COUNT_MASK)
20149 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK    0x10000u
20150 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT   16
20151 #define GPMI_CTRL0_SET_ADDRESS_MASK              0xE0000u
20152 #define GPMI_CTRL0_SET_ADDRESS_SHIFT             17
20153 #define GPMI_CTRL0_SET_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_ADDRESS_SHIFT))&GPMI_CTRL0_SET_ADDRESS_MASK)
20154 #define GPMI_CTRL0_SET_CS_MASK                   0x700000u
20155 #define GPMI_CTRL0_SET_CS_SHIFT                  20
20156 #define GPMI_CTRL0_SET_CS(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_CS_SHIFT))&GPMI_CTRL0_SET_CS_MASK)
20157 #define GPMI_CTRL0_SET_WORD_LENGTH_MASK          0x800000u
20158 #define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT         23
20159 #define GPMI_CTRL0_SET_COMMAND_MODE_MASK         0x3000000u
20160 #define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT        24
20161 #define GPMI_CTRL0_SET_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_COMMAND_MODE_SHIFT))&GPMI_CTRL0_SET_COMMAND_MODE_MASK)
20162 #define GPMI_CTRL0_SET_UDMA_MASK                 0x4000000u
20163 #define GPMI_CTRL0_SET_UDMA_SHIFT                26
20164 #define GPMI_CTRL0_SET_LOCK_CS_MASK              0x8000000u
20165 #define GPMI_CTRL0_SET_LOCK_CS_SHIFT             27
20166 #define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK           0x10000000u
20167 #define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT          28
20168 #define GPMI_CTRL0_SET_RUN_MASK                  0x20000000u
20169 #define GPMI_CTRL0_SET_RUN_SHIFT                 29
20170 #define GPMI_CTRL0_SET_CLKGATE_MASK              0x40000000u
20171 #define GPMI_CTRL0_SET_CLKGATE_SHIFT             30
20172 #define GPMI_CTRL0_SET_SFTRST_MASK               0x80000000u
20173 #define GPMI_CTRL0_SET_SFTRST_SHIFT              31
20174 /* CTRL0_CLR Bit Fields */
20175 #define GPMI_CTRL0_CLR_XFER_COUNT_MASK           0xFFFFu
20176 #define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT          0
20177 #define GPMI_CTRL0_CLR_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_XFER_COUNT_SHIFT))&GPMI_CTRL0_CLR_XFER_COUNT_MASK)
20178 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK    0x10000u
20179 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT   16
20180 #define GPMI_CTRL0_CLR_ADDRESS_MASK              0xE0000u
20181 #define GPMI_CTRL0_CLR_ADDRESS_SHIFT             17
20182 #define GPMI_CTRL0_CLR_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_ADDRESS_SHIFT))&GPMI_CTRL0_CLR_ADDRESS_MASK)
20183 #define GPMI_CTRL0_CLR_CS_MASK                   0x700000u
20184 #define GPMI_CTRL0_CLR_CS_SHIFT                  20
20185 #define GPMI_CTRL0_CLR_CS(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_CS_SHIFT))&GPMI_CTRL0_CLR_CS_MASK)
20186 #define GPMI_CTRL0_CLR_WORD_LENGTH_MASK          0x800000u
20187 #define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT         23
20188 #define GPMI_CTRL0_CLR_COMMAND_MODE_MASK         0x3000000u
20189 #define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT        24
20190 #define GPMI_CTRL0_CLR_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT))&GPMI_CTRL0_CLR_COMMAND_MODE_MASK)
20191 #define GPMI_CTRL0_CLR_UDMA_MASK                 0x4000000u
20192 #define GPMI_CTRL0_CLR_UDMA_SHIFT                26
20193 #define GPMI_CTRL0_CLR_LOCK_CS_MASK              0x8000000u
20194 #define GPMI_CTRL0_CLR_LOCK_CS_SHIFT             27
20195 #define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK           0x10000000u
20196 #define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT          28
20197 #define GPMI_CTRL0_CLR_RUN_MASK                  0x20000000u
20198 #define GPMI_CTRL0_CLR_RUN_SHIFT                 29
20199 #define GPMI_CTRL0_CLR_CLKGATE_MASK              0x40000000u
20200 #define GPMI_CTRL0_CLR_CLKGATE_SHIFT             30
20201 #define GPMI_CTRL0_CLR_SFTRST_MASK               0x80000000u
20202 #define GPMI_CTRL0_CLR_SFTRST_SHIFT              31
20203 /* CTRL0_TOG Bit Fields */
20204 #define GPMI_CTRL0_TOG_XFER_COUNT_MASK           0xFFFFu
20205 #define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT          0
20206 #define GPMI_CTRL0_TOG_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_XFER_COUNT_SHIFT))&GPMI_CTRL0_TOG_XFER_COUNT_MASK)
20207 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK    0x10000u
20208 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT   16
20209 #define GPMI_CTRL0_TOG_ADDRESS_MASK              0xE0000u
20210 #define GPMI_CTRL0_TOG_ADDRESS_SHIFT             17
20211 #define GPMI_CTRL0_TOG_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_ADDRESS_SHIFT))&GPMI_CTRL0_TOG_ADDRESS_MASK)
20212 #define GPMI_CTRL0_TOG_CS_MASK                   0x700000u
20213 #define GPMI_CTRL0_TOG_CS_SHIFT                  20
20214 #define GPMI_CTRL0_TOG_CS(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_CS_SHIFT))&GPMI_CTRL0_TOG_CS_MASK)
20215 #define GPMI_CTRL0_TOG_WORD_LENGTH_MASK          0x800000u
20216 #define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT         23
20217 #define GPMI_CTRL0_TOG_COMMAND_MODE_MASK         0x3000000u
20218 #define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT        24
20219 #define GPMI_CTRL0_TOG_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT))&GPMI_CTRL0_TOG_COMMAND_MODE_MASK)
20220 #define GPMI_CTRL0_TOG_UDMA_MASK                 0x4000000u
20221 #define GPMI_CTRL0_TOG_UDMA_SHIFT                26
20222 #define GPMI_CTRL0_TOG_LOCK_CS_MASK              0x8000000u
20223 #define GPMI_CTRL0_TOG_LOCK_CS_SHIFT             27
20224 #define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK           0x10000000u
20225 #define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT          28
20226 #define GPMI_CTRL0_TOG_RUN_MASK                  0x20000000u
20227 #define GPMI_CTRL0_TOG_RUN_SHIFT                 29
20228 #define GPMI_CTRL0_TOG_CLKGATE_MASK              0x40000000u
20229 #define GPMI_CTRL0_TOG_CLKGATE_SHIFT             30
20230 #define GPMI_CTRL0_TOG_SFTRST_MASK               0x80000000u
20231 #define GPMI_CTRL0_TOG_SFTRST_SHIFT              31
20232 /* COMPARE Bit Fields */
20233 #define GPMI_COMPARE_REFERENCE_MASK              0xFFFFu
20234 #define GPMI_COMPARE_REFERENCE_SHIFT             0
20235 #define GPMI_COMPARE_REFERENCE(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_REFERENCE_SHIFT))&GPMI_COMPARE_REFERENCE_MASK)
20236 #define GPMI_COMPARE_MASK_MASK                   0xFFFF0000u
20237 #define GPMI_COMPARE_MASK_SHIFT                  16
20238 #define GPMI_COMPARE_MASK(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_MASK_SHIFT))&GPMI_COMPARE_MASK_MASK)
20239 /* ECCCTRL Bit Fields */
20240 #define GPMI_ECCCTRL_BUFFER_MASK_MASK            0x1FFu
20241 #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT           0
20242 #define GPMI_ECCCTRL_BUFFER_MASK(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_BUFFER_MASK_MASK)
20243 #define GPMI_ECCCTRL_RSVD1_MASK                  0xE00u
20244 #define GPMI_ECCCTRL_RSVD1_SHIFT                 9
20245 #define GPMI_ECCCTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_RSVD1_SHIFT))&GPMI_ECCCTRL_RSVD1_MASK)
20246 #define GPMI_ECCCTRL_ENABLE_ECC_MASK             0x1000u
20247 #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT            12
20248 #define GPMI_ECCCTRL_ECC_CMD_MASK                0x6000u
20249 #define GPMI_ECCCTRL_ECC_CMD_SHIFT               13
20250 #define GPMI_ECCCTRL_ECC_CMD(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_ECC_CMD_SHIFT))&GPMI_ECCCTRL_ECC_CMD_MASK)
20251 #define GPMI_ECCCTRL_RSVD2_MASK                  0x8000u
20252 #define GPMI_ECCCTRL_RSVD2_SHIFT                 15
20253 #define GPMI_ECCCTRL_HANDLE_MASK                 0xFFFF0000u
20254 #define GPMI_ECCCTRL_HANDLE_SHIFT                16
20255 #define GPMI_ECCCTRL_HANDLE(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_HANDLE_SHIFT))&GPMI_ECCCTRL_HANDLE_MASK)
20256 /* ECCCTRL_SET Bit Fields */
20257 #define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK        0x1FFu
20258 #define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT       0
20259 #define GPMI_ECCCTRL_SET_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_SET_BUFFER_MASK_MASK)
20260 #define GPMI_ECCCTRL_SET_RSVD1_MASK              0xE00u
20261 #define GPMI_ECCCTRL_SET_RSVD1_SHIFT             9
20262 #define GPMI_ECCCTRL_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_RSVD1_SHIFT))&GPMI_ECCCTRL_SET_RSVD1_MASK)
20263 #define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK         0x1000u
20264 #define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT        12
20265 #define GPMI_ECCCTRL_SET_ECC_CMD_MASK            0x6000u
20266 #define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT           13
20267 #define GPMI_ECCCTRL_SET_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_ECC_CMD_SHIFT))&GPMI_ECCCTRL_SET_ECC_CMD_MASK)
20268 #define GPMI_ECCCTRL_SET_RSVD2_MASK              0x8000u
20269 #define GPMI_ECCCTRL_SET_RSVD2_SHIFT             15
20270 #define GPMI_ECCCTRL_SET_HANDLE_MASK             0xFFFF0000u
20271 #define GPMI_ECCCTRL_SET_HANDLE_SHIFT            16
20272 #define GPMI_ECCCTRL_SET_HANDLE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_HANDLE_SHIFT))&GPMI_ECCCTRL_SET_HANDLE_MASK)
20273 /* ECCCTRL_CLR Bit Fields */
20274 #define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK        0x1FFu
20275 #define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT       0
20276 #define GPMI_ECCCTRL_CLR_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK)
20277 #define GPMI_ECCCTRL_CLR_RSVD1_MASK              0xE00u
20278 #define GPMI_ECCCTRL_CLR_RSVD1_SHIFT             9
20279 #define GPMI_ECCCTRL_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_RSVD1_SHIFT))&GPMI_ECCCTRL_CLR_RSVD1_MASK)
20280 #define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK         0x1000u
20281 #define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT        12
20282 #define GPMI_ECCCTRL_CLR_ECC_CMD_MASK            0x6000u
20283 #define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT           13
20284 #define GPMI_ECCCTRL_CLR_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT))&GPMI_ECCCTRL_CLR_ECC_CMD_MASK)
20285 #define GPMI_ECCCTRL_CLR_RSVD2_MASK              0x8000u
20286 #define GPMI_ECCCTRL_CLR_RSVD2_SHIFT             15
20287 #define GPMI_ECCCTRL_CLR_HANDLE_MASK             0xFFFF0000u
20288 #define GPMI_ECCCTRL_CLR_HANDLE_SHIFT            16
20289 #define GPMI_ECCCTRL_CLR_HANDLE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_HANDLE_SHIFT))&GPMI_ECCCTRL_CLR_HANDLE_MASK)
20290 /* ECCCTRL_TOG Bit Fields */
20291 #define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK        0x1FFu
20292 #define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT       0
20293 #define GPMI_ECCCTRL_TOG_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK)
20294 #define GPMI_ECCCTRL_TOG_RSVD1_MASK              0xE00u
20295 #define GPMI_ECCCTRL_TOG_RSVD1_SHIFT             9
20296 #define GPMI_ECCCTRL_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_RSVD1_SHIFT))&GPMI_ECCCTRL_TOG_RSVD1_MASK)
20297 #define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK         0x1000u
20298 #define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT        12
20299 #define GPMI_ECCCTRL_TOG_ECC_CMD_MASK            0x6000u
20300 #define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT           13
20301 #define GPMI_ECCCTRL_TOG_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT))&GPMI_ECCCTRL_TOG_ECC_CMD_MASK)
20302 #define GPMI_ECCCTRL_TOG_RSVD2_MASK              0x8000u
20303 #define GPMI_ECCCTRL_TOG_RSVD2_SHIFT             15
20304 #define GPMI_ECCCTRL_TOG_HANDLE_MASK             0xFFFF0000u
20305 #define GPMI_ECCCTRL_TOG_HANDLE_SHIFT            16
20306 #define GPMI_ECCCTRL_TOG_HANDLE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_HANDLE_SHIFT))&GPMI_ECCCTRL_TOG_HANDLE_MASK)
20307 /* ECCCOUNT Bit Fields */
20308 #define GPMI_ECCCOUNT_COUNT_MASK                 0xFFFFu
20309 #define GPMI_ECCCOUNT_COUNT_SHIFT                0
20310 #define GPMI_ECCCOUNT_COUNT(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCOUNT_COUNT_SHIFT))&GPMI_ECCCOUNT_COUNT_MASK)
20311 /* PAYLOAD Bit Fields */
20312 #define GPMI_PAYLOAD_RSVD0_MASK                  0x3u
20313 #define GPMI_PAYLOAD_RSVD0_SHIFT                 0
20314 #define GPMI_PAYLOAD_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_RSVD0_SHIFT))&GPMI_PAYLOAD_RSVD0_MASK)
20315 #define GPMI_PAYLOAD_ADDRESS_MASK                0xFFFFFFFCu
20316 #define GPMI_PAYLOAD_ADDRESS_SHIFT               2
20317 #define GPMI_PAYLOAD_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_ADDRESS_SHIFT))&GPMI_PAYLOAD_ADDRESS_MASK)
20318 /* AUXILIARY Bit Fields */
20319 #define GPMI_AUXILIARY_RSVD0_MASK                0x3u
20320 #define GPMI_AUXILIARY_RSVD0_SHIFT               0
20321 #define GPMI_AUXILIARY_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_RSVD0_SHIFT))&GPMI_AUXILIARY_RSVD0_MASK)
20322 #define GPMI_AUXILIARY_ADDRESS_MASK              0xFFFFFFFCu
20323 #define GPMI_AUXILIARY_ADDRESS_SHIFT             2
20324 #define GPMI_AUXILIARY_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_ADDRESS_SHIFT))&GPMI_AUXILIARY_ADDRESS_MASK)
20325 /* CTRL1 Bit Fields */
20326 #define GPMI_CTRL1_GPMI_MODE_MASK                0x1u
20327 #define GPMI_CTRL1_GPMI_MODE_SHIFT               0
20328 #define GPMI_CTRL1_CAMERA_MODE_MASK              0x2u
20329 #define GPMI_CTRL1_CAMERA_MODE_SHIFT             1
20330 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK      0x4u
20331 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT     2
20332 #define GPMI_CTRL1_DEV_RESET_MASK                0x8u
20333 #define GPMI_CTRL1_DEV_RESET_SHIFT               3
20334 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
20335 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
20336 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
20337 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK       0x80u
20338 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT      7
20339 #define GPMI_CTRL1_BURST_EN_MASK                 0x100u
20340 #define GPMI_CTRL1_BURST_EN_SHIFT                8
20341 #define GPMI_CTRL1_TIMEOUT_IRQ_MASK              0x200u
20342 #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT             9
20343 #define GPMI_CTRL1_DEV_IRQ_MASK                  0x400u
20344 #define GPMI_CTRL1_DEV_IRQ_SHIFT                 10
20345 #define GPMI_CTRL1_DMA2ECC_MODE_MASK             0x800u
20346 #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT            11
20347 #define GPMI_CTRL1_RDN_DELAY_MASK                0xF000u
20348 #define GPMI_CTRL1_RDN_DELAY_SHIFT               12
20349 #define GPMI_CTRL1_RDN_DELAY(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_RDN_DELAY_SHIFT))&GPMI_CTRL1_RDN_DELAY_MASK)
20350 #define GPMI_CTRL1_HALF_PERIOD_MASK              0x10000u
20351 #define GPMI_CTRL1_HALF_PERIOD_SHIFT             16
20352 #define GPMI_CTRL1_DLL_ENABLE_MASK               0x20000u
20353 #define GPMI_CTRL1_DLL_ENABLE_SHIFT              17
20354 #define GPMI_CTRL1_BCH_MODE_MASK                 0x40000u
20355 #define GPMI_CTRL1_BCH_MODE_SHIFT                18
20356 #define GPMI_CTRL1_GANGED_RDYBUSY_MASK           0x80000u
20357 #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT          19
20358 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK           0x100000u
20359 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT          20
20360 #define GPMI_CTRL1_TEST_TRIGGER_MASK             0x200000u
20361 #define GPMI_CTRL1_TEST_TRIGGER_SHIFT            21
20362 #define GPMI_CTRL1_WRN_DLY_SEL_MASK              0xC00000u
20363 #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT             22
20364 #define GPMI_CTRL1_WRN_DLY_SEL(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_WRN_DLY_SEL_MASK)
20365 #define GPMI_CTRL1_DECOUPLE_CS_MASK              0x1000000u
20366 #define GPMI_CTRL1_DECOUPLE_CS_SHIFT             24
20367 #define GPMI_CTRL1_SSYNCMODE_MASK                0x2000000u
20368 #define GPMI_CTRL1_SSYNCMODE_SHIFT               25
20369 #define GPMI_CTRL1_UPDATE_CS_MASK                0x4000000u
20370 #define GPMI_CTRL1_UPDATE_CS_SHIFT               26
20371 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK         0x8000000u
20372 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT        27
20373 #define GPMI_CTRL1_TOGGLE_MODE_MASK              0x10000000u
20374 #define GPMI_CTRL1_TOGGLE_MODE_SHIFT             28
20375 #define GPMI_CTRL1_WRITE_CLK_STOP_MASK           0x20000000u
20376 #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT          29
20377 #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK           0x40000000u
20378 #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT          30
20379 #define GPMI_CTRL1_DEV_CLK_STOP_MASK             0x80000000u
20380 #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT            31
20381 /* CTRL1_SET Bit Fields */
20382 #define GPMI_CTRL1_SET_GPMI_MODE_MASK            0x1u
20383 #define GPMI_CTRL1_SET_GPMI_MODE_SHIFT           0
20384 #define GPMI_CTRL1_SET_CAMERA_MODE_MASK          0x2u
20385 #define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT         1
20386 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK  0x4u
20387 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT 2
20388 #define GPMI_CTRL1_SET_DEV_RESET_MASK            0x8u
20389 #define GPMI_CTRL1_SET_DEV_RESET_SHIFT           3
20390 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
20391 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
20392 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
20393 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK   0x80u
20394 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT  7
20395 #define GPMI_CTRL1_SET_BURST_EN_MASK             0x100u
20396 #define GPMI_CTRL1_SET_BURST_EN_SHIFT            8
20397 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK          0x200u
20398 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT         9
20399 #define GPMI_CTRL1_SET_DEV_IRQ_MASK              0x400u
20400 #define GPMI_CTRL1_SET_DEV_IRQ_SHIFT             10
20401 #define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK         0x800u
20402 #define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT        11
20403 #define GPMI_CTRL1_SET_RDN_DELAY_MASK            0xF000u
20404 #define GPMI_CTRL1_SET_RDN_DELAY_SHIFT           12
20405 #define GPMI_CTRL1_SET_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_RDN_DELAY_SHIFT))&GPMI_CTRL1_SET_RDN_DELAY_MASK)
20406 #define GPMI_CTRL1_SET_HALF_PERIOD_MASK          0x10000u
20407 #define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT         16
20408 #define GPMI_CTRL1_SET_DLL_ENABLE_MASK           0x20000u
20409 #define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT          17
20410 #define GPMI_CTRL1_SET_BCH_MODE_MASK             0x40000u
20411 #define GPMI_CTRL1_SET_BCH_MODE_SHIFT            18
20412 #define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK       0x80000u
20413 #define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT      19
20414 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK       0x100000u
20415 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT      20
20416 #define GPMI_CTRL1_SET_TEST_TRIGGER_MASK         0x200000u
20417 #define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT        21
20418 #define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK          0xC00000u
20419 #define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT         22
20420 #define GPMI_CTRL1_SET_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_SET_WRN_DLY_SEL_MASK)
20421 #define GPMI_CTRL1_SET_DECOUPLE_CS_MASK          0x1000000u
20422 #define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT         24
20423 #define GPMI_CTRL1_SET_SSYNCMODE_MASK            0x2000000u
20424 #define GPMI_CTRL1_SET_SSYNCMODE_SHIFT           25
20425 #define GPMI_CTRL1_SET_UPDATE_CS_MASK            0x4000000u
20426 #define GPMI_CTRL1_SET_UPDATE_CS_SHIFT           26
20427 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK     0x8000000u
20428 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT    27
20429 #define GPMI_CTRL1_SET_TOGGLE_MODE_MASK          0x10000000u
20430 #define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT         28
20431 #define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK       0x20000000u
20432 #define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT      29
20433 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK       0x40000000u
20434 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT      30
20435 #define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK         0x80000000u
20436 #define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT        31
20437 /* CTRL1_CLR Bit Fields */
20438 #define GPMI_CTRL1_CLR_GPMI_MODE_MASK            0x1u
20439 #define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT           0
20440 #define GPMI_CTRL1_CLR_CAMERA_MODE_MASK          0x2u
20441 #define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT         1
20442 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK  0x4u
20443 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT 2
20444 #define GPMI_CTRL1_CLR_DEV_RESET_MASK            0x8u
20445 #define GPMI_CTRL1_CLR_DEV_RESET_SHIFT           3
20446 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
20447 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
20448 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
20449 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK   0x80u
20450 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT  7
20451 #define GPMI_CTRL1_CLR_BURST_EN_MASK             0x100u
20452 #define GPMI_CTRL1_CLR_BURST_EN_SHIFT            8
20453 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK          0x200u
20454 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT         9
20455 #define GPMI_CTRL1_CLR_DEV_IRQ_MASK              0x400u
20456 #define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT             10
20457 #define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK         0x800u
20458 #define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT        11
20459 #define GPMI_CTRL1_CLR_RDN_DELAY_MASK            0xF000u
20460 #define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT           12
20461 #define GPMI_CTRL1_CLR_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_RDN_DELAY_SHIFT))&GPMI_CTRL1_CLR_RDN_DELAY_MASK)
20462 #define GPMI_CTRL1_CLR_HALF_PERIOD_MASK          0x10000u
20463 #define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT         16
20464 #define GPMI_CTRL1_CLR_DLL_ENABLE_MASK           0x20000u
20465 #define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT          17
20466 #define GPMI_CTRL1_CLR_BCH_MODE_MASK             0x40000u
20467 #define GPMI_CTRL1_CLR_BCH_MODE_SHIFT            18
20468 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK       0x80000u
20469 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT      19
20470 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK       0x100000u
20471 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT      20
20472 #define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK         0x200000u
20473 #define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT        21
20474 #define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK          0xC00000u
20475 #define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT         22
20476 #define GPMI_CTRL1_CLR_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK)
20477 #define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK          0x1000000u
20478 #define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT         24
20479 #define GPMI_CTRL1_CLR_SSYNCMODE_MASK            0x2000000u
20480 #define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT           25
20481 #define GPMI_CTRL1_CLR_UPDATE_CS_MASK            0x4000000u
20482 #define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT           26
20483 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK     0x8000000u
20484 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT    27
20485 #define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK          0x10000000u
20486 #define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT         28
20487 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK       0x20000000u
20488 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT      29
20489 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK       0x40000000u
20490 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT      30
20491 #define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK         0x80000000u
20492 #define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT        31
20493 /* CTRL1_TOG Bit Fields */
20494 #define GPMI_CTRL1_TOG_GPMI_MODE_MASK            0x1u
20495 #define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT           0
20496 #define GPMI_CTRL1_TOG_CAMERA_MODE_MASK          0x2u
20497 #define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT         1
20498 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK  0x4u
20499 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT 2
20500 #define GPMI_CTRL1_TOG_DEV_RESET_MASK            0x8u
20501 #define GPMI_CTRL1_TOG_DEV_RESET_SHIFT           3
20502 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
20503 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
20504 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
20505 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK   0x80u
20506 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT  7
20507 #define GPMI_CTRL1_TOG_BURST_EN_MASK             0x100u
20508 #define GPMI_CTRL1_TOG_BURST_EN_SHIFT            8
20509 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK          0x200u
20510 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT         9
20511 #define GPMI_CTRL1_TOG_DEV_IRQ_MASK              0x400u
20512 #define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT             10
20513 #define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK         0x800u
20514 #define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT        11
20515 #define GPMI_CTRL1_TOG_RDN_DELAY_MASK            0xF000u
20516 #define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT           12
20517 #define GPMI_CTRL1_TOG_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_RDN_DELAY_SHIFT))&GPMI_CTRL1_TOG_RDN_DELAY_MASK)
20518 #define GPMI_CTRL1_TOG_HALF_PERIOD_MASK          0x10000u
20519 #define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT         16
20520 #define GPMI_CTRL1_TOG_DLL_ENABLE_MASK           0x20000u
20521 #define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT          17
20522 #define GPMI_CTRL1_TOG_BCH_MODE_MASK             0x40000u
20523 #define GPMI_CTRL1_TOG_BCH_MODE_SHIFT            18
20524 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK       0x80000u
20525 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT      19
20526 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK       0x100000u
20527 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT      20
20528 #define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK         0x200000u
20529 #define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT        21
20530 #define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK          0xC00000u
20531 #define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT         22
20532 #define GPMI_CTRL1_TOG_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK)
20533 #define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK          0x1000000u
20534 #define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT         24
20535 #define GPMI_CTRL1_TOG_SSYNCMODE_MASK            0x2000000u
20536 #define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT           25
20537 #define GPMI_CTRL1_TOG_UPDATE_CS_MASK            0x4000000u
20538 #define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT           26
20539 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK     0x8000000u
20540 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT    27
20541 #define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK          0x10000000u
20542 #define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT         28
20543 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK       0x20000000u
20544 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT      29
20545 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK       0x40000000u
20546 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT      30
20547 #define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK         0x80000000u
20548 #define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT        31
20549 /* TIMING0 Bit Fields */
20550 #define GPMI_TIMING0_DATA_SETUP_MASK             0xFFu
20551 #define GPMI_TIMING0_DATA_SETUP_SHIFT            0
20552 #define GPMI_TIMING0_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_SETUP_SHIFT))&GPMI_TIMING0_DATA_SETUP_MASK)
20553 #define GPMI_TIMING0_DATA_HOLD_MASK              0xFF00u
20554 #define GPMI_TIMING0_DATA_HOLD_SHIFT             8
20555 #define GPMI_TIMING0_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_HOLD_SHIFT))&GPMI_TIMING0_DATA_HOLD_MASK)
20556 #define GPMI_TIMING0_ADDRESS_SETUP_MASK          0xFF0000u
20557 #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT         16
20558 #define GPMI_TIMING0_ADDRESS_SETUP(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_ADDRESS_SETUP_SHIFT))&GPMI_TIMING0_ADDRESS_SETUP_MASK)
20559 #define GPMI_TIMING0_RSVD1_MASK                  0xFF000000u
20560 #define GPMI_TIMING0_RSVD1_SHIFT                 24
20561 #define GPMI_TIMING0_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_RSVD1_SHIFT))&GPMI_TIMING0_RSVD1_MASK)
20562 /* TIMING1 Bit Fields */
20563 #define GPMI_TIMING1_RSVD1_MASK                  0xFFFFu
20564 #define GPMI_TIMING1_RSVD1_SHIFT                 0
20565 #define GPMI_TIMING1_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_RSVD1_SHIFT))&GPMI_TIMING1_RSVD1_MASK)
20566 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK    0xFFFF0000u
20567 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT   16
20568 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT))&GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
20569 /* TIMING2 Bit Fields */
20570 #define GPMI_TIMING2_DATA_PAUSE_MASK             0xFu
20571 #define GPMI_TIMING2_DATA_PAUSE_SHIFT            0
20572 #define GPMI_TIMING2_DATA_PAUSE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_DATA_PAUSE_SHIFT))&GPMI_TIMING2_DATA_PAUSE_MASK)
20573 #define GPMI_TIMING2_CMDADD_PAUSE_MASK           0xF0u
20574 #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT          4
20575 #define GPMI_TIMING2_CMDADD_PAUSE(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CMDADD_PAUSE_SHIFT))&GPMI_TIMING2_CMDADD_PAUSE_MASK)
20576 #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK        0xF00u
20577 #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT       8
20578 #define GPMI_TIMING2_POSTAMBLE_DELAY(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT))&GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
20579 #define GPMI_TIMING2_PREAMBLE_DELAY_MASK         0xF000u
20580 #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT        12
20581 #define GPMI_TIMING2_PREAMBLE_DELAY(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_PREAMBLE_DELAY_SHIFT))&GPMI_TIMING2_PREAMBLE_DELAY_MASK)
20582 #define GPMI_TIMING2_CE_DELAY_MASK               0x1F0000u
20583 #define GPMI_TIMING2_CE_DELAY_SHIFT              16
20584 #define GPMI_TIMING2_CE_DELAY(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CE_DELAY_SHIFT))&GPMI_TIMING2_CE_DELAY_MASK)
20585 #define GPMI_TIMING2_RSVD0_MASK                  0xE00000u
20586 #define GPMI_TIMING2_RSVD0_SHIFT                 21
20587 #define GPMI_TIMING2_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_RSVD0_SHIFT))&GPMI_TIMING2_RSVD0_MASK)
20588 #define GPMI_TIMING2_READ_LATENCY_MASK           0x7000000u
20589 #define GPMI_TIMING2_READ_LATENCY_SHIFT          24
20590 #define GPMI_TIMING2_READ_LATENCY(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_READ_LATENCY_SHIFT))&GPMI_TIMING2_READ_LATENCY_MASK)
20591 #define GPMI_TIMING2_TCR_MASK                    0x18000000u
20592 #define GPMI_TIMING2_TCR_SHIFT                   27
20593 #define GPMI_TIMING2_TCR(x)                      (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TCR_SHIFT))&GPMI_TIMING2_TCR_MASK)
20594 #define GPMI_TIMING2_TRPSTH_MASK                 0xE0000000u
20595 #define GPMI_TIMING2_TRPSTH_SHIFT                29
20596 #define GPMI_TIMING2_TRPSTH(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TRPSTH_SHIFT))&GPMI_TIMING2_TRPSTH_MASK)
20597 /* DATA Bit Fields */
20598 #define GPMI_DATA_DATA_MASK                      0xFFFFFFFFu
20599 #define GPMI_DATA_DATA_SHIFT                     0
20600 #define GPMI_DATA_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<GPMI_DATA_DATA_SHIFT))&GPMI_DATA_DATA_MASK)
20601 /* STAT Bit Fields */
20602 #define GPMI_STAT_PRESENT_MASK                   0x1u
20603 #define GPMI_STAT_PRESENT_SHIFT                  0
20604 #define GPMI_STAT_FIFO_FULL_MASK                 0x2u
20605 #define GPMI_STAT_FIFO_FULL_SHIFT                1
20606 #define GPMI_STAT_FIFO_EMPTY_MASK                0x4u
20607 #define GPMI_STAT_FIFO_EMPTY_SHIFT               2
20608 #define GPMI_STAT_INVALID_BUFFER_MASK_MASK       0x8u
20609 #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT      3
20610 #define GPMI_STAT_ATA_IRQ_MASK                   0x10u
20611 #define GPMI_STAT_ATA_IRQ_SHIFT                  4
20612 #define GPMI_STAT_RSVD1_MASK                     0xE0u
20613 #define GPMI_STAT_RSVD1_SHIFT                    5
20614 #define GPMI_STAT_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RSVD1_SHIFT))&GPMI_STAT_RSVD1_MASK)
20615 #define GPMI_STAT_DEV0_ERROR_MASK                0x100u
20616 #define GPMI_STAT_DEV0_ERROR_SHIFT               8
20617 #define GPMI_STAT_DEV1_ERROR_MASK                0x200u
20618 #define GPMI_STAT_DEV1_ERROR_SHIFT               9
20619 #define GPMI_STAT_DEV2_ERROR_MASK                0x400u
20620 #define GPMI_STAT_DEV2_ERROR_SHIFT               10
20621 #define GPMI_STAT_DEV3_ERROR_MASK                0x800u
20622 #define GPMI_STAT_DEV3_ERROR_SHIFT               11
20623 #define GPMI_STAT_DEV4_ERROR_MASK                0x1000u
20624 #define GPMI_STAT_DEV4_ERROR_SHIFT               12
20625 #define GPMI_STAT_DEV5_ERROR_MASK                0x2000u
20626 #define GPMI_STAT_DEV5_ERROR_SHIFT               13
20627 #define GPMI_STAT_DEV6_ERROR_MASK                0x4000u
20628 #define GPMI_STAT_DEV6_ERROR_SHIFT               14
20629 #define GPMI_STAT_DEV7_ERROR_MASK                0x8000u
20630 #define GPMI_STAT_DEV7_ERROR_SHIFT               15
20631 #define GPMI_STAT_RDY_TIMEOUT_MASK               0xFF0000u
20632 #define GPMI_STAT_RDY_TIMEOUT_SHIFT              16
20633 #define GPMI_STAT_RDY_TIMEOUT(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RDY_TIMEOUT_SHIFT))&GPMI_STAT_RDY_TIMEOUT_MASK)
20634 #define GPMI_STAT_READY_BUSY_MASK                0xFF000000u
20635 #define GPMI_STAT_READY_BUSY_SHIFT               24
20636 #define GPMI_STAT_READY_BUSY(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_READY_BUSY_SHIFT))&GPMI_STAT_READY_BUSY_MASK)
20637 /* DEBUG Bit Fields */
20638 #define GPMI_DEBUG_CMD_END_MASK                  0xFFu
20639 #define GPMI_DEBUG_CMD_END_SHIFT                 0
20640 #define GPMI_DEBUG_CMD_END(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_CMD_END_SHIFT))&GPMI_DEBUG_CMD_END_MASK)
20641 #define GPMI_DEBUG_DMAREQ_MASK                   0xFF00u
20642 #define GPMI_DEBUG_DMAREQ_SHIFT                  8
20643 #define GPMI_DEBUG_DMAREQ(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMAREQ_SHIFT))&GPMI_DEBUG_DMAREQ_MASK)
20644 #define GPMI_DEBUG_DMA_SENSE_MASK                0xFF0000u
20645 #define GPMI_DEBUG_DMA_SENSE_SHIFT               16
20646 #define GPMI_DEBUG_DMA_SENSE(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMA_SENSE_SHIFT))&GPMI_DEBUG_DMA_SENSE_MASK)
20647 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK       0xFF000000u
20648 #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT      24
20649 #define GPMI_DEBUG_WAIT_FOR_READY_END(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT))&GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
20650 /* VERSION Bit Fields */
20651 #define GPMI_VERSION_STEP_MASK                   0xFFFFu
20652 #define GPMI_VERSION_STEP_SHIFT                  0
20653 #define GPMI_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_STEP_SHIFT))&GPMI_VERSION_STEP_MASK)
20654 #define GPMI_VERSION_MINOR_MASK                  0xFF0000u
20655 #define GPMI_VERSION_MINOR_SHIFT                 16
20656 #define GPMI_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MINOR_SHIFT))&GPMI_VERSION_MINOR_MASK)
20657 #define GPMI_VERSION_MAJOR_MASK                  0xFF000000u
20658 #define GPMI_VERSION_MAJOR_SHIFT                 24
20659 #define GPMI_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MAJOR_SHIFT))&GPMI_VERSION_MAJOR_MASK)
20660 /* DEBUG2 Bit Fields */
20661 #define GPMI_DEBUG2_RDN_TAP_MASK                 0x3Fu
20662 #define GPMI_DEBUG2_RDN_TAP_SHIFT                0
20663 #define GPMI_DEBUG2_RDN_TAP(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RDN_TAP_SHIFT))&GPMI_DEBUG2_RDN_TAP_MASK)
20664 #define GPMI_DEBUG2_UPDATE_WINDOW_MASK           0x40u
20665 #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT          6
20666 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK        0x80u
20667 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT       7
20668 #define GPMI_DEBUG2_SYND2GPMI_READY_MASK         0x100u
20669 #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT        8
20670 #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK         0x200u
20671 #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT        9
20672 #define GPMI_DEBUG2_GPMI2SYND_READY_MASK         0x400u
20673 #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT        10
20674 #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK         0x800u
20675 #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT        11
20676 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK            0xF000u
20677 #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT           12
20678 #define GPMI_DEBUG2_SYND2GPMI_BE(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_SYND2GPMI_BE_SHIFT))&GPMI_DEBUG2_SYND2GPMI_BE_MASK)
20679 #define GPMI_DEBUG2_MAIN_STATE_MASK              0xF0000u
20680 #define GPMI_DEBUG2_MAIN_STATE_SHIFT             16
20681 #define GPMI_DEBUG2_MAIN_STATE(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_MAIN_STATE_SHIFT))&GPMI_DEBUG2_MAIN_STATE_MASK)
20682 #define GPMI_DEBUG2_PIN_STATE_MASK               0x700000u
20683 #define GPMI_DEBUG2_PIN_STATE_SHIFT              20
20684 #define GPMI_DEBUG2_PIN_STATE(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_PIN_STATE_SHIFT))&GPMI_DEBUG2_PIN_STATE_MASK)
20685 #define GPMI_DEBUG2_BUSY_MASK                    0x800000u
20686 #define GPMI_DEBUG2_BUSY_SHIFT                   23
20687 #define GPMI_DEBUG2_UDMA_STATE_MASK              0xF000000u
20688 #define GPMI_DEBUG2_UDMA_STATE_SHIFT             24
20689 #define GPMI_DEBUG2_UDMA_STATE(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_UDMA_STATE_SHIFT))&GPMI_DEBUG2_UDMA_STATE_MASK)
20690 #define GPMI_DEBUG2_RSVD1_MASK                   0xF0000000u
20691 #define GPMI_DEBUG2_RSVD1_SHIFT                  28
20692 #define GPMI_DEBUG2_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RSVD1_SHIFT))&GPMI_DEBUG2_RSVD1_MASK)
20693 /* DEBUG3 Bit Fields */
20694 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK           0xFFFFu
20695 #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT          0
20696 #define GPMI_DEBUG3_DEV_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT))&GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
20697 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK           0xFFFF0000u
20698 #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT          16
20699 #define GPMI_DEBUG3_APB_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_APB_WORD_CNTR_SHIFT))&GPMI_DEBUG3_APB_WORD_CNTR_MASK)
20700 /* READ_DDR_DLL_CTRL Bit Fields */
20701 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK       0x1u
20702 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT      0
20703 #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK        0x2u
20704 #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT       1
20705 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u
20706 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2
20707 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK 0x78u
20708 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
20709 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
20710 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK  0x80u
20711 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT 7
20712 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK    0x100u
20713 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT   8
20714 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK 0x200u
20715 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT 9
20716 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0x3FC00u
20717 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 10
20718 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
20719 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK        0xC0000u
20720 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT       18
20721 #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
20722 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u
20723 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20
20724 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
20725 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u
20726 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28
20727 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
20728 /* READ_DDR_DLL_STS Bit Fields */
20729 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK      0x1u
20730 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT     0
20731 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK       0x1FEu
20732 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT      1
20733 #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
20734 #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK         0xFE00u
20735 #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT        9
20736 #define GPMI_READ_DDR_DLL_STS_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
20737 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK      0x10000u
20738 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT     16
20739 #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK       0x1FE0000u
20740 #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT      17
20741 #define GPMI_READ_DDR_DLL_STS_REF_SEL(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
20742 #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK         0xFE000000u
20743 #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT        25
20744 #define GPMI_READ_DDR_DLL_STS_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
20745 
20746 /*!
20747  * @}
20748  */ /* end of group GPMI_Register_Masks */
20749 
20750 /* GPMI - Peripheral instance base addresses */
20751 /** Peripheral GPMI base address */
20752 #define GPMI_BASE                                (0x33002000u)
20753 /** Peripheral GPMI base pointer */
20754 #define GPMI                                     ((GPMI_Type *)GPMI_BASE)
20755 #define GPMI_BASE_PTR                            (GPMI)
20756 /** Array initializer of GPMI peripheral base addresses */
20757 #define GPMI_BASE_ADDRS                          { GPMI_BASE }
20758 /** Array initializer of GPMI peripheral base pointers */
20759 #define GPMI_BASE_PTRS                           { GPMI }
20760 /** Interrupt vectors for the GPMI peripheral type */
20761 #define GPMI_IRQS                                { GPMI_IRQn }
20762 /* ----------------------------------------------------------------------------
20763    -- GPMI - Register accessor macros
20764    ---------------------------------------------------------------------------- */
20765 
20766 /*!
20767  * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros
20768  * @{
20769  */
20770 
20771 
20772 /* GPMI - Register instance definitions */
20773 /* GPMI */
20774 #define GPMI_CTRL0                               GPMI_CTRL0_REG(GPMI_BASE_PTR)
20775 #define GPMI_CTRL0_SET                           GPMI_CTRL0_SET_REG(GPMI_BASE_PTR)
20776 #define GPMI_CTRL0_CLR                           GPMI_CTRL0_CLR_REG(GPMI_BASE_PTR)
20777 #define GPMI_CTRL0_TOG                           GPMI_CTRL0_TOG_REG(GPMI_BASE_PTR)
20778 #define GPMI_COMPARE                             GPMI_COMPARE_REG(GPMI_BASE_PTR)
20779 #define GPMI_ECCCTRL                             GPMI_ECCCTRL_REG(GPMI_BASE_PTR)
20780 #define GPMI_ECCCTRL_SET                         GPMI_ECCCTRL_SET_REG(GPMI_BASE_PTR)
20781 #define GPMI_ECCCTRL_CLR                         GPMI_ECCCTRL_CLR_REG(GPMI_BASE_PTR)
20782 #define GPMI_ECCCTRL_TOG                         GPMI_ECCCTRL_TOG_REG(GPMI_BASE_PTR)
20783 #define GPMI_ECCCOUNT                            GPMI_ECCCOUNT_REG(GPMI_BASE_PTR)
20784 #define GPMI_PAYLOAD                             GPMI_PAYLOAD_REG(GPMI_BASE_PTR)
20785 #define GPMI_AUXILIARY                           GPMI_AUXILIARY_REG(GPMI_BASE_PTR)
20786 #define GPMI_CTRL1                               GPMI_CTRL1_REG(GPMI_BASE_PTR)
20787 #define GPMI_CTRL1_SET                           GPMI_CTRL1_SET_REG(GPMI_BASE_PTR)
20788 #define GPMI_CTRL1_CLR                           GPMI_CTRL1_CLR_REG(GPMI_BASE_PTR)
20789 #define GPMI_CTRL1_TOG                           GPMI_CTRL1_TOG_REG(GPMI_BASE_PTR)
20790 #define GPMI_TIMING0                             GPMI_TIMING0_REG(GPMI_BASE_PTR)
20791 #define GPMI_TIMING1                             GPMI_TIMING1_REG(GPMI_BASE_PTR)
20792 #define GPMI_TIMING2                             GPMI_TIMING2_REG(GPMI_BASE_PTR)
20793 #define GPMI_DATA                                GPMI_DATA_REG(GPMI_BASE_PTR)
20794 #define GPMI_STAT                                GPMI_STAT_REG(GPMI_BASE_PTR)
20795 #define GPMI_DEBUG                               GPMI_DEBUG_REG(GPMI_BASE_PTR)
20796 #define GPMI_VERSION                             GPMI_VERSION_REG(GPMI_BASE_PTR)
20797 #define GPMI_DEBUG2                              GPMI_DEBUG2_REG(GPMI_BASE_PTR)
20798 #define GPMI_DEBUG3                              GPMI_DEBUG3_REG(GPMI_BASE_PTR)
20799 #define GPMI_READ_DDR_DLL_CTRL                   GPMI_READ_DDR_DLL_CTRL_REG(GPMI_BASE_PTR)
20800 #define GPMI_READ_DDR_DLL_STS                    GPMI_READ_DDR_DLL_STS_REG(GPMI_BASE_PTR)
20801 /*!
20802  * @}
20803  */ /* end of group GPMI_Register_Accessor_Macros */
20804 
20805 
20806 /*!
20807  * @}
20808  */ /* end of group GPMI_Peripheral */
20809 
20810 /* ----------------------------------------------------------------------------
20811    -- GPT Peripheral Access Layer
20812    ---------------------------------------------------------------------------- */
20813 
20814 /*!
20815  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
20816  * @{
20817  */
20818 
20819 /** GPT - Register Layout Typedef */
20820 typedef struct {
20821   __IO  uint32_t CR;                                     /**< GPT Control Register, offset: 0x0 */
20822   __IO  uint32_t PR;                                     /**< GPT Prescaler Register, offset: 0x4 */
20823   __IO  uint32_t SR;                                     /**< GPT Status Register, offset: 0x8 */
20824   __IO  uint32_t IR;                                     /**< GPT Interrupt Register, offset: 0xC */
20825   __IO  uint32_t OCR1;                                   /**< GPT Output Compare Register 1, offset: 0x10 */
20826   __IO  uint32_t OCR2;                                   /**< GPT Output Compare Register 2, offset: 0x14 */
20827   __IO  uint32_t OCR3;                                   /**< GPT Output Compare Register 3, offset: 0x18 */
20828   __I   uint32_t ICR1;                                   /**< GPT Input Capture Register 1, offset: 0x1C */
20829   __I   uint32_t ICR2;                                   /**< GPT Input Capture Register 2, offset: 0x20 */
20830   __I   uint32_t CNT;                                    /**< GPT Counter Register, offset: 0x24 */
20831 } GPT_Type, *GPT_MemMapPtr;
20832 /* ----------------------------------------------------------------------------
20833    -- GPT - Register accessor macros
20834    ---------------------------------------------------------------------------- */
20835 
20836 /*!
20837  * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros
20838  * @{
20839  */
20840 
20841 
20842 /* GPT - Register accessors */
20843 #define GPT_CR_REG(base)                         ((base)->CR)
20844 #define GPT_PR_REG(base)                         ((base)->PR)
20845 #define GPT_SR_REG(base)                         ((base)->SR)
20846 #define GPT_IR_REG(base)                         ((base)->IR)
20847 #define GPT_OCR1_REG(base)                       ((base)->OCR1)
20848 #define GPT_OCR2_REG(base)                       ((base)->OCR2)
20849 #define GPT_OCR3_REG(base)                       ((base)->OCR3)
20850 #define GPT_ICR1_REG(base)                       ((base)->ICR1)
20851 #define GPT_ICR2_REG(base)                       ((base)->ICR2)
20852 #define GPT_CNT_REG(base)                        ((base)->CNT)
20853 
20854 /*!
20855  * @}
20856  */ /* end of group GPT_Register_Accessor_Macros */
20857 /* ----------------------------------------------------------------------------
20858    -- GPT Register Masks
20859    ---------------------------------------------------------------------------- */
20860 
20861 /*!
20862  * @addtogroup GPT_Register_Masks GPT Register Masks
20863  * @{
20864  */
20865 
20866 /* CR Bit Fields */
20867 #define GPT_CR_EN_MASK                           0x1u
20868 #define GPT_CR_EN_SHIFT                          0
20869 #define GPT_CR_ENMOD_MASK                        0x2u
20870 #define GPT_CR_ENMOD_SHIFT                       1
20871 #define GPT_CR_DBGEN_MASK                        0x4u
20872 #define GPT_CR_DBGEN_SHIFT                       2
20873 #define GPT_CR_WAITEN_MASK                       0x8u
20874 #define GPT_CR_WAITEN_SHIFT                      3
20875 #define GPT_CR_DOZEEN_MASK                       0x10u
20876 #define GPT_CR_DOZEEN_SHIFT                      4
20877 #define GPT_CR_STOPEN_MASK                       0x20u
20878 #define GPT_CR_STOPEN_SHIFT                      5
20879 #define GPT_CR_CLKSRC_MASK                       0x1C0u
20880 #define GPT_CR_CLKSRC_SHIFT                      6
20881 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_CR_CLKSRC_SHIFT))&GPT_CR_CLKSRC_MASK)
20882 #define GPT_CR_FRR_MASK                          0x200u
20883 #define GPT_CR_FRR_SHIFT                         9
20884 #define GPT_CR_EN_24M_MASK                       0x400u
20885 #define GPT_CR_EN_24M_SHIFT                      10
20886 #define GPT_CR_SWR_MASK                          0x8000u
20887 #define GPT_CR_SWR_SHIFT                         15
20888 #define GPT_CR_IM1_MASK                          0x30000u
20889 #define GPT_CR_IM1_SHIFT                         16
20890 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM1_SHIFT))&GPT_CR_IM1_MASK)
20891 #define GPT_CR_IM2_MASK                          0xC0000u
20892 #define GPT_CR_IM2_SHIFT                         18
20893 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM2_SHIFT))&GPT_CR_IM2_MASK)
20894 #define GPT_CR_OM1_MASK                          0x700000u
20895 #define GPT_CR_OM1_SHIFT                         20
20896 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM1_SHIFT))&GPT_CR_OM1_MASK)
20897 #define GPT_CR_OM2_MASK                          0x3800000u
20898 #define GPT_CR_OM2_SHIFT                         23
20899 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM2_SHIFT))&GPT_CR_OM2_MASK)
20900 #define GPT_CR_OM3_MASK                          0x1C000000u
20901 #define GPT_CR_OM3_SHIFT                         26
20902 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM3_SHIFT))&GPT_CR_OM3_MASK)
20903 #define GPT_CR_FO1_MASK                          0x20000000u
20904 #define GPT_CR_FO1_SHIFT                         29
20905 #define GPT_CR_FO2_MASK                          0x40000000u
20906 #define GPT_CR_FO2_SHIFT                         30
20907 #define GPT_CR_FO3_MASK                          0x80000000u
20908 #define GPT_CR_FO3_SHIFT                         31
20909 /* PR Bit Fields */
20910 #define GPT_PR_PRESCALER_MASK                    0xFFFu
20911 #define GPT_PR_PRESCALER_SHIFT                   0
20912 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER_SHIFT))&GPT_PR_PRESCALER_MASK)
20913 #define GPT_PR_PRESCALER24M_MASK                 0xF000u
20914 #define GPT_PR_PRESCALER24M_SHIFT                12
20915 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER24M_SHIFT))&GPT_PR_PRESCALER24M_MASK)
20916 /* SR Bit Fields */
20917 #define GPT_SR_OF1_MASK                          0x1u
20918 #define GPT_SR_OF1_SHIFT                         0
20919 #define GPT_SR_OF2_MASK                          0x2u
20920 #define GPT_SR_OF2_SHIFT                         1
20921 #define GPT_SR_OF3_MASK                          0x4u
20922 #define GPT_SR_OF3_SHIFT                         2
20923 #define GPT_SR_IF1_MASK                          0x8u
20924 #define GPT_SR_IF1_SHIFT                         3
20925 #define GPT_SR_IF2_MASK                          0x10u
20926 #define GPT_SR_IF2_SHIFT                         4
20927 #define GPT_SR_ROV_MASK                          0x20u
20928 #define GPT_SR_ROV_SHIFT                         5
20929 /* IR Bit Fields */
20930 #define GPT_IR_OF1IE_MASK                        0x1u
20931 #define GPT_IR_OF1IE_SHIFT                       0
20932 #define GPT_IR_OF2IE_MASK                        0x2u
20933 #define GPT_IR_OF2IE_SHIFT                       1
20934 #define GPT_IR_OF3IE_MASK                        0x4u
20935 #define GPT_IR_OF3IE_SHIFT                       2
20936 #define GPT_IR_IF1IE_MASK                        0x8u
20937 #define GPT_IR_IF1IE_SHIFT                       3
20938 #define GPT_IR_IF2IE_MASK                        0x10u
20939 #define GPT_IR_IF2IE_SHIFT                       4
20940 #define GPT_IR_ROVIE_MASK                        0x20u
20941 #define GPT_IR_ROVIE_SHIFT                       5
20942 /* OCR1 Bit Fields */
20943 #define GPT_OCR1_COMP_MASK                       0xFFFFFFFFu
20944 #define GPT_OCR1_COMP_SHIFT                      0
20945 #define GPT_OCR1_COMP(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_OCR1_COMP_SHIFT))&GPT_OCR1_COMP_MASK)
20946 /* OCR2 Bit Fields */
20947 #define GPT_OCR2_COMP_MASK                       0xFFFFFFFFu
20948 #define GPT_OCR2_COMP_SHIFT                      0
20949 #define GPT_OCR2_COMP(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_OCR2_COMP_SHIFT))&GPT_OCR2_COMP_MASK)
20950 /* OCR3 Bit Fields */
20951 #define GPT_OCR3_COMP_MASK                       0xFFFFFFFFu
20952 #define GPT_OCR3_COMP_SHIFT                      0
20953 #define GPT_OCR3_COMP(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_OCR3_COMP_SHIFT))&GPT_OCR3_COMP_MASK)
20954 /* ICR1 Bit Fields */
20955 #define GPT_ICR1_CAPT_MASK                       0xFFFFFFFFu
20956 #define GPT_ICR1_CAPT_SHIFT                      0
20957 #define GPT_ICR1_CAPT(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_ICR1_CAPT_SHIFT))&GPT_ICR1_CAPT_MASK)
20958 /* ICR2 Bit Fields */
20959 #define GPT_ICR2_CAPT_MASK                       0xFFFFFFFFu
20960 #define GPT_ICR2_CAPT_SHIFT                      0
20961 #define GPT_ICR2_CAPT(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_ICR2_CAPT_SHIFT))&GPT_ICR2_CAPT_MASK)
20962 /* CNT Bit Fields */
20963 #define GPT_CNT_COUNT_MASK                       0xFFFFFFFFu
20964 #define GPT_CNT_COUNT_SHIFT                      0
20965 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_CNT_COUNT_SHIFT))&GPT_CNT_COUNT_MASK)
20966 
20967 /*!
20968  * @}
20969  */ /* end of group GPT_Register_Masks */
20970 
20971 /* GPT - Peripheral instance base addresses */
20972 /** Peripheral GPT1 base address */
20973 #define GPT1_BASE                                (0x302D0000u)
20974 /** Peripheral GPT1 base pointer */
20975 #define GPT1                                     ((GPT_Type *)GPT1_BASE)
20976 #define GPT1_BASE_PTR                            (GPT1)
20977 /** Peripheral GPT2 base address */
20978 #define GPT2_BASE                                (0x302E0000u)
20979 /** Peripheral GPT2 base pointer */
20980 #define GPT2                                     ((GPT_Type *)GPT2_BASE)
20981 #define GPT2_BASE_PTR                            (GPT2)
20982 /** Peripheral GPT3 base address */
20983 #define GPT3_BASE                                (0x302F0000u)
20984 /** Peripheral GPT3 base pointer */
20985 #define GPT3                                     ((GPT_Type *)GPT3_BASE)
20986 #define GPT3_BASE_PTR                            (GPT3)
20987 /** Peripheral GPT4 base address */
20988 #define GPT4_BASE                                (0x30300000u)
20989 /** Peripheral GPT4 base pointer */
20990 #define GPT4                                     ((GPT_Type *)GPT4_BASE)
20991 #define GPT4_BASE_PTR                            (GPT4)
20992 /** Array initializer of GPT peripheral base addresses */
20993 #define GPT_BASE_ADDRS                           { GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE }
20994 /** Array initializer of GPT peripheral base pointers */
20995 #define GPT_BASE_PTRS                            { GPT1, GPT2, GPT3, GPT4 }
20996 /** Interrupt vectors for the GPT peripheral type */
20997 #define GPT_IRQS                                 { GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn }
20998 /* ----------------------------------------------------------------------------
20999    -- GPT - Register accessor macros
21000    ---------------------------------------------------------------------------- */
21001 
21002 /*!
21003  * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros
21004  * @{
21005  */
21006 
21007 
21008 /* GPT - Register instance definitions */
21009 /* GPT1 */
21010 #define GPT1_CR                                  GPT_CR_REG(GPT1_BASE_PTR)
21011 #define GPT1_PR                                  GPT_PR_REG(GPT1_BASE_PTR)
21012 #define GPT1_SR                                  GPT_SR_REG(GPT1_BASE_PTR)
21013 #define GPT1_IR                                  GPT_IR_REG(GPT1_BASE_PTR)
21014 #define GPT1_OCR1                                GPT_OCR1_REG(GPT1_BASE_PTR)
21015 #define GPT1_OCR2                                GPT_OCR2_REG(GPT1_BASE_PTR)
21016 #define GPT1_OCR3                                GPT_OCR3_REG(GPT1_BASE_PTR)
21017 #define GPT1_ICR1                                GPT_ICR1_REG(GPT1_BASE_PTR)
21018 #define GPT1_ICR2                                GPT_ICR2_REG(GPT1_BASE_PTR)
21019 #define GPT1_CNT                                 GPT_CNT_REG(GPT1_BASE_PTR)
21020 /* GPT2 */
21021 #define GPT2_CR                                  GPT_CR_REG(GPT2_BASE_PTR)
21022 #define GPT2_PR                                  GPT_PR_REG(GPT2_BASE_PTR)
21023 #define GPT2_SR                                  GPT_SR_REG(GPT2_BASE_PTR)
21024 #define GPT2_IR                                  GPT_IR_REG(GPT2_BASE_PTR)
21025 #define GPT2_OCR1                                GPT_OCR1_REG(GPT2_BASE_PTR)
21026 #define GPT2_OCR2                                GPT_OCR2_REG(GPT2_BASE_PTR)
21027 #define GPT2_OCR3                                GPT_OCR3_REG(GPT2_BASE_PTR)
21028 #define GPT2_ICR1                                GPT_ICR1_REG(GPT2_BASE_PTR)
21029 #define GPT2_ICR2                                GPT_ICR2_REG(GPT2_BASE_PTR)
21030 #define GPT2_CNT                                 GPT_CNT_REG(GPT2_BASE_PTR)
21031 /* GPT3 */
21032 #define GPT3_CR                                  GPT_CR_REG(GPT3_BASE_PTR)
21033 #define GPT3_PR                                  GPT_PR_REG(GPT3_BASE_PTR)
21034 #define GPT3_SR                                  GPT_SR_REG(GPT3_BASE_PTR)
21035 #define GPT3_IR                                  GPT_IR_REG(GPT3_BASE_PTR)
21036 #define GPT3_OCR1                                GPT_OCR1_REG(GPT3_BASE_PTR)
21037 #define GPT3_OCR2                                GPT_OCR2_REG(GPT3_BASE_PTR)
21038 #define GPT3_OCR3                                GPT_OCR3_REG(GPT3_BASE_PTR)
21039 #define GPT3_ICR1                                GPT_ICR1_REG(GPT3_BASE_PTR)
21040 #define GPT3_ICR2                                GPT_ICR2_REG(GPT3_BASE_PTR)
21041 #define GPT3_CNT                                 GPT_CNT_REG(GPT3_BASE_PTR)
21042 /* GPT4 */
21043 #define GPT4_CR                                  GPT_CR_REG(GPT4_BASE_PTR)
21044 #define GPT4_PR                                  GPT_PR_REG(GPT4_BASE_PTR)
21045 #define GPT4_SR                                  GPT_SR_REG(GPT4_BASE_PTR)
21046 #define GPT4_IR                                  GPT_IR_REG(GPT4_BASE_PTR)
21047 #define GPT4_OCR1                                GPT_OCR1_REG(GPT4_BASE_PTR)
21048 #define GPT4_OCR2                                GPT_OCR2_REG(GPT4_BASE_PTR)
21049 #define GPT4_OCR3                                GPT_OCR3_REG(GPT4_BASE_PTR)
21050 #define GPT4_ICR1                                GPT_ICR1_REG(GPT4_BASE_PTR)
21051 #define GPT4_ICR2                                GPT_ICR2_REG(GPT4_BASE_PTR)
21052 #define GPT4_CNT                                 GPT_CNT_REG(GPT4_BASE_PTR)
21053 /*!
21054  * @}
21055  */ /* end of group GPT_Register_Accessor_Macros */
21056 
21057 
21058 /*!
21059  * @}
21060  */ /* end of group GPT_Peripheral */
21061 
21062 /* ----------------------------------------------------------------------------
21063    -- I2C Peripheral Access Layer
21064    ---------------------------------------------------------------------------- */
21065 
21066 /*!
21067  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
21068  * @{
21069  */
21070 
21071 /** I2C - Register Layout Typedef */
21072 typedef struct {
21073   __IO  uint16_t IADR;                                   /**< I2C Address Register, offset: 0x0 */
21074   uint8_t RESERVED_0[2];
21075   __IO  uint16_t IFDR;                                   /**< I2C Frequency Divider Register, offset: 0x4 */
21076   uint8_t RESERVED_1[2];
21077   __IO  uint16_t I2CR;                                   /**< I2C Control Register, offset: 0x8 */
21078   uint8_t RESERVED_2[2];
21079   __IO  uint16_t I2SR;                                   /**< I2C Status Register, offset: 0xC */
21080   uint8_t RESERVED_3[2];
21081   __IO  uint16_t I2DR;                                   /**< I2C Data I/O Register, offset: 0x10 */
21082 } I2C_Type, *I2C_MemMapPtr;
21083 /* ----------------------------------------------------------------------------
21084    -- I2C - Register accessor macros
21085    ---------------------------------------------------------------------------- */
21086 
21087 /*!
21088  * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
21089  * @{
21090  */
21091 
21092 
21093 /* I2C - Register accessors */
21094 #define I2C_IADR_REG(base)                       ((base)->IADR)
21095 #define I2C_IFDR_REG(base)                       ((base)->IFDR)
21096 #define I2C_I2CR_REG(base)                       ((base)->I2CR)
21097 #define I2C_I2SR_REG(base)                       ((base)->I2SR)
21098 #define I2C_I2DR_REG(base)                       ((base)->I2DR)
21099 
21100 /*!
21101  * @}
21102  */ /* end of group I2C_Register_Accessor_Macros */
21103 /* ----------------------------------------------------------------------------
21104    -- I2C Register Masks
21105    ---------------------------------------------------------------------------- */
21106 
21107 /*!
21108  * @addtogroup I2C_Register_Masks I2C Register Masks
21109  * @{
21110  */
21111 
21112 /* IADR Bit Fields */
21113 #define I2C_IADR_ADR_MASK                        0xFEu
21114 #define I2C_IADR_ADR_SHIFT                       1
21115 #define I2C_IADR_ADR(x)                          (((uint16_t)(((uint16_t)(x))<<I2C_IADR_ADR_SHIFT))&I2C_IADR_ADR_MASK)
21116 /* IFDR Bit Fields */
21117 #define I2C_IFDR_IC_MASK                         0x3Fu
21118 #define I2C_IFDR_IC_SHIFT                        0
21119 #define I2C_IFDR_IC(x)                           (((uint16_t)(((uint16_t)(x))<<I2C_IFDR_IC_SHIFT))&I2C_IFDR_IC_MASK)
21120 /* I2CR Bit Fields */
21121 #define I2C_I2CR_RSTA_MASK                       0x4u
21122 #define I2C_I2CR_RSTA_SHIFT                      2
21123 #define I2C_I2CR_TXAK_MASK                       0x8u
21124 #define I2C_I2CR_TXAK_SHIFT                      3
21125 #define I2C_I2CR_MTX_MASK                        0x10u
21126 #define I2C_I2CR_MTX_SHIFT                       4
21127 #define I2C_I2CR_MSTA_MASK                       0x20u
21128 #define I2C_I2CR_MSTA_SHIFT                      5
21129 #define I2C_I2CR_IIEN_MASK                       0x40u
21130 #define I2C_I2CR_IIEN_SHIFT                      6
21131 #define I2C_I2CR_IEN_MASK                        0x80u
21132 #define I2C_I2CR_IEN_SHIFT                       7
21133 /* I2SR Bit Fields */
21134 #define I2C_I2SR_RXAK_MASK                       0x1u
21135 #define I2C_I2SR_RXAK_SHIFT                      0
21136 #define I2C_I2SR_IIF_MASK                        0x2u
21137 #define I2C_I2SR_IIF_SHIFT                       1
21138 #define I2C_I2SR_SRW_MASK                        0x4u
21139 #define I2C_I2SR_SRW_SHIFT                       2
21140 #define I2C_I2SR_IAL_MASK                        0x10u
21141 #define I2C_I2SR_IAL_SHIFT                       4
21142 #define I2C_I2SR_IBB_MASK                        0x20u
21143 #define I2C_I2SR_IBB_SHIFT                       5
21144 #define I2C_I2SR_IAAS_MASK                       0x40u
21145 #define I2C_I2SR_IAAS_SHIFT                      6
21146 #define I2C_I2SR_ICF_MASK                        0x80u
21147 #define I2C_I2SR_ICF_SHIFT                       7
21148 /* I2DR Bit Fields */
21149 #define I2C_I2DR_DATA_MASK                       0xFFu
21150 #define I2C_I2DR_DATA_SHIFT                      0
21151 #define I2C_I2DR_DATA(x)                         (((uint16_t)(((uint16_t)(x))<<I2C_I2DR_DATA_SHIFT))&I2C_I2DR_DATA_MASK)
21152 
21153 /*!
21154  * @}
21155  */ /* end of group I2C_Register_Masks */
21156 
21157 /* I2C - Peripheral instance base addresses */
21158 /** Peripheral I2C1 base address */
21159 #define I2C1_BASE                                (0x30A20000u)
21160 /** Peripheral I2C1 base pointer */
21161 #define I2C1                                     ((I2C_Type *)I2C1_BASE)
21162 #define I2C1_BASE_PTR                            (I2C1)
21163 /** Peripheral I2C2 base address */
21164 #define I2C2_BASE                                (0x30A30000u)
21165 /** Peripheral I2C2 base pointer */
21166 #define I2C2                                     ((I2C_Type *)I2C2_BASE)
21167 #define I2C2_BASE_PTR                            (I2C2)
21168 /** Peripheral I2C3 base address */
21169 #define I2C3_BASE                                (0x30A40000u)
21170 /** Peripheral I2C3 base pointer */
21171 #define I2C3                                     ((I2C_Type *)I2C3_BASE)
21172 #define I2C3_BASE_PTR                            (I2C3)
21173 /** Peripheral I2C4 base address */
21174 #define I2C4_BASE                                (0x30A50000u)
21175 /** Peripheral I2C4 base pointer */
21176 #define I2C4                                     ((I2C_Type *)I2C4_BASE)
21177 #define I2C4_BASE_PTR                            (I2C4)
21178 /** Array initializer of I2C peripheral base addresses */
21179 #define I2C_BASE_ADDRS                           { I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE }
21180 /** Array initializer of I2C peripheral base pointers */
21181 #define I2C_BASE_PTRS                            { I2C1, I2C2, I2C3, I2C4 }
21182 /** Interrupt vectors for the I2C peripheral type */
21183 #define I2C_IRQS                                 { I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn }
21184 /* ----------------------------------------------------------------------------
21185    -- I2C - Register accessor macros
21186    ---------------------------------------------------------------------------- */
21187 
21188 /*!
21189  * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
21190  * @{
21191  */
21192 
21193 
21194 /* I2C - Register instance definitions */
21195 /* I2C1 */
21196 #define I2C1_IADR                                I2C_IADR_REG(I2C1_BASE_PTR)
21197 #define I2C1_IFDR                                I2C_IFDR_REG(I2C1_BASE_PTR)
21198 #define I2C1_I2CR                                I2C_I2CR_REG(I2C1_BASE_PTR)
21199 #define I2C1_I2SR                                I2C_I2SR_REG(I2C1_BASE_PTR)
21200 #define I2C1_I2DR                                I2C_I2DR_REG(I2C1_BASE_PTR)
21201 /* I2C2 */
21202 #define I2C2_IADR                                I2C_IADR_REG(I2C2_BASE_PTR)
21203 #define I2C2_IFDR                                I2C_IFDR_REG(I2C2_BASE_PTR)
21204 #define I2C2_I2CR                                I2C_I2CR_REG(I2C2_BASE_PTR)
21205 #define I2C2_I2SR                                I2C_I2SR_REG(I2C2_BASE_PTR)
21206 #define I2C2_I2DR                                I2C_I2DR_REG(I2C2_BASE_PTR)
21207 /* I2C3 */
21208 #define I2C3_IADR                                I2C_IADR_REG(I2C3_BASE_PTR)
21209 #define I2C3_IFDR                                I2C_IFDR_REG(I2C3_BASE_PTR)
21210 #define I2C3_I2CR                                I2C_I2CR_REG(I2C3_BASE_PTR)
21211 #define I2C3_I2SR                                I2C_I2SR_REG(I2C3_BASE_PTR)
21212 #define I2C3_I2DR                                I2C_I2DR_REG(I2C3_BASE_PTR)
21213 /* I2C4 */
21214 #define I2C4_IADR                                I2C_IADR_REG(I2C4_BASE_PTR)
21215 #define I2C4_IFDR                                I2C_IFDR_REG(I2C4_BASE_PTR)
21216 #define I2C4_I2CR                                I2C_I2CR_REG(I2C4_BASE_PTR)
21217 #define I2C4_I2SR                                I2C_I2SR_REG(I2C4_BASE_PTR)
21218 #define I2C4_I2DR                                I2C_I2DR_REG(I2C4_BASE_PTR)
21219 /*!
21220  * @}
21221  */ /* end of group I2C_Register_Accessor_Macros */
21222 
21223 
21224 /*!
21225  * @}
21226  */ /* end of group I2C_Peripheral */
21227 
21228 /* ----------------------------------------------------------------------------
21229    -- I2S Peripheral Access Layer
21230    ---------------------------------------------------------------------------- */
21231 
21232 /*!
21233  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
21234  * @{
21235  */
21236 
21237 /** I2S - Register Layout Typedef */
21238 typedef struct {
21239   __IO  uint32_t TCSR;                                   /**< SAI Transmit Control Register, offset: 0x0 */
21240   __IO  uint32_t TCR1;                                   /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
21241   __IO  uint32_t TCR2;                                   /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
21242   __IO  uint32_t TCR3;                                   /**< SAI Transmit Configuration 3 Register, offset: 0xC */
21243   __IO  uint32_t TCR4;                                   /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
21244   __IO  uint32_t TCR5;                                   /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
21245   uint8_t RESERVED_0[8];
21246   __O     uint32_t TDR[1];                                 /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
21247   uint8_t RESERVED_1[28];
21248   __I     uint32_t TFR[1];                                 /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
21249   uint8_t RESERVED_2[28];
21250   __IO  uint32_t TMR;                                    /**< SAI Transmit Mask Register, offset: 0x60 */
21251   uint8_t RESERVED_3[28];
21252   __IO  uint32_t RCSR;                                   /**< SAI Receive Control Register, offset: 0x80 */
21253   __IO  uint32_t RCR1;                                   /**< SAI Receive Configuration 1 Register, offset: 0x84 */
21254   __IO  uint32_t RCR2;                                   /**< SAI Receive Configuration 2 Register, offset: 0x88 */
21255   __IO  uint32_t RCR3;                                   /**< SAI Receive Configuration 3 Register, offset: 0x8C */
21256   __IO  uint32_t RCR4;                                   /**< SAI Receive Configuration 4 Register, offset: 0x90 */
21257   __IO  uint32_t RCR5;                                   /**< SAI Receive Configuration 5 Register, offset: 0x94 */
21258   uint8_t RESERVED_4[8];
21259   __I     uint32_t RDR[1];                                 /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
21260   uint8_t RESERVED_5[28];
21261   __I     uint32_t RFR[1];                                 /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
21262   uint8_t RESERVED_6[28];
21263   __IO  uint32_t RMR;                                    /**< SAI Receive Mask Register, offset: 0xE0 */
21264 } I2S_Type, *I2S_MemMapPtr;
21265 /* ----------------------------------------------------------------------------
21266    -- I2S - Register accessor macros
21267    ---------------------------------------------------------------------------- */
21268 
21269 /*!
21270  * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
21271  * @{
21272  */
21273 
21274 
21275 /* I2S - Register accessors */
21276 #define I2S_TCSR_REG(base)                       ((base)->TCSR)
21277 #define I2S_TCR1_REG(base)                       ((base)->TCR1)
21278 #define I2S_TCR2_REG(base)                       ((base)->TCR2)
21279 #define I2S_TCR3_REG(base)                       ((base)->TCR3)
21280 #define I2S_TCR4_REG(base)                       ((base)->TCR4)
21281 #define I2S_TCR5_REG(base)                       ((base)->TCR5)
21282 #define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
21283 #define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
21284 #define I2S_TMR_REG(base)                        ((base)->TMR)
21285 #define I2S_RCSR_REG(base)                       ((base)->RCSR)
21286 #define I2S_RCR1_REG(base)                       ((base)->RCR1)
21287 #define I2S_RCR2_REG(base)                       ((base)->RCR2)
21288 #define I2S_RCR3_REG(base)                       ((base)->RCR3)
21289 #define I2S_RCR4_REG(base)                       ((base)->RCR4)
21290 #define I2S_RCR5_REG(base)                       ((base)->RCR5)
21291 #define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
21292 #define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
21293 #define I2S_RMR_REG(base)                        ((base)->RMR)
21294 
21295 /*!
21296  * @}
21297  */ /* end of group I2S_Register_Accessor_Macros */
21298 /* ----------------------------------------------------------------------------
21299    -- I2S Register Masks
21300    ---------------------------------------------------------------------------- */
21301 
21302 /*!
21303  * @addtogroup I2S_Register_Masks I2S Register Masks
21304  * @{
21305  */
21306 
21307 /* TCSR Bit Fields */
21308 #define I2S_TCSR_FRDE_MASK                       0x1u
21309 #define I2S_TCSR_FRDE_SHIFT                      0
21310 #define I2S_TCSR_FWDE_MASK                       0x2u
21311 #define I2S_TCSR_FWDE_SHIFT                      1
21312 #define I2S_TCSR_FRIE_MASK                       0x100u
21313 #define I2S_TCSR_FRIE_SHIFT                      8
21314 #define I2S_TCSR_FWIE_MASK                       0x200u
21315 #define I2S_TCSR_FWIE_SHIFT                      9
21316 #define I2S_TCSR_FEIE_MASK                       0x400u
21317 #define I2S_TCSR_FEIE_SHIFT                      10
21318 #define I2S_TCSR_SEIE_MASK                       0x800u
21319 #define I2S_TCSR_SEIE_SHIFT                      11
21320 #define I2S_TCSR_WSIE_MASK                       0x1000u
21321 #define I2S_TCSR_WSIE_SHIFT                      12
21322 #define I2S_TCSR_FRF_MASK                        0x10000u
21323 #define I2S_TCSR_FRF_SHIFT                       16
21324 #define I2S_TCSR_FWF_MASK                        0x20000u
21325 #define I2S_TCSR_FWF_SHIFT                       17
21326 #define I2S_TCSR_FEF_MASK                        0x40000u
21327 #define I2S_TCSR_FEF_SHIFT                       18
21328 #define I2S_TCSR_SEF_MASK                        0x80000u
21329 #define I2S_TCSR_SEF_SHIFT                       19
21330 #define I2S_TCSR_WSF_MASK                        0x100000u
21331 #define I2S_TCSR_WSF_SHIFT                       20
21332 #define I2S_TCSR_SR_MASK                         0x1000000u
21333 #define I2S_TCSR_SR_SHIFT                        24
21334 #define I2S_TCSR_FR_MASK                         0x2000000u
21335 #define I2S_TCSR_FR_SHIFT                        25
21336 #define I2S_TCSR_BCE_MASK                        0x10000000u
21337 #define I2S_TCSR_BCE_SHIFT                       28
21338 #define I2S_TCSR_DBGE_MASK                       0x20000000u
21339 #define I2S_TCSR_DBGE_SHIFT                      29
21340 #define I2S_TCSR_STOPE_MASK                      0x40000000u
21341 #define I2S_TCSR_STOPE_SHIFT                     30
21342 #define I2S_TCSR_TE_MASK                         0x80000000u
21343 #define I2S_TCSR_TE_SHIFT                        31
21344 /* TCR1 Bit Fields */
21345 #define I2S_TCR1_TFW_MASK                        0x1Fu
21346 #define I2S_TCR1_TFW_SHIFT                       0
21347 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
21348 /* TCR2 Bit Fields */
21349 #define I2S_TCR2_DIV_MASK                        0xFFu
21350 #define I2S_TCR2_DIV_SHIFT                       0
21351 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
21352 #define I2S_TCR2_BCD_MASK                        0x1000000u
21353 #define I2S_TCR2_BCD_SHIFT                       24
21354 #define I2S_TCR2_BCP_MASK                        0x2000000u
21355 #define I2S_TCR2_BCP_SHIFT                       25
21356 #define I2S_TCR2_MSEL_MASK                       0xC000000u
21357 #define I2S_TCR2_MSEL_SHIFT                      26
21358 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
21359 #define I2S_TCR2_BCI_MASK                        0x10000000u
21360 #define I2S_TCR2_BCI_SHIFT                       28
21361 #define I2S_TCR2_BCS_MASK                        0x20000000u
21362 #define I2S_TCR2_BCS_SHIFT                       29
21363 #define I2S_TCR2_SYNC_MASK                       0xC0000000u
21364 #define I2S_TCR2_SYNC_SHIFT                      30
21365 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
21366 /* TCR3 Bit Fields */
21367 #define I2S_TCR3_WDFL_MASK                       0x1Fu
21368 #define I2S_TCR3_WDFL_SHIFT                      0
21369 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
21370 #define I2S_TCR3_TCE_MASK                        0x10000u
21371 #define I2S_TCR3_TCE_SHIFT                       16
21372 /* TCR4 Bit Fields */
21373 #define I2S_TCR4_FSD_MASK                        0x1u
21374 #define I2S_TCR4_FSD_SHIFT                       0
21375 #define I2S_TCR4_FSP_MASK                        0x2u
21376 #define I2S_TCR4_FSP_SHIFT                       1
21377 #define I2S_TCR4_FSE_MASK                        0x8u
21378 #define I2S_TCR4_FSE_SHIFT                       3
21379 #define I2S_TCR4_MF_MASK                         0x10u
21380 #define I2S_TCR4_MF_SHIFT                        4
21381 #define I2S_TCR4_SYWD_MASK                       0x1F00u
21382 #define I2S_TCR4_SYWD_SHIFT                      8
21383 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
21384 #define I2S_TCR4_FRSZ_MASK                       0x1F0000u
21385 #define I2S_TCR4_FRSZ_SHIFT                      16
21386 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
21387 /* TCR5 Bit Fields */
21388 #define I2S_TCR5_FBT_MASK                        0x1F00u
21389 #define I2S_TCR5_FBT_SHIFT                       8
21390 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
21391 #define I2S_TCR5_W0W_MASK                        0x1F0000u
21392 #define I2S_TCR5_W0W_SHIFT                       16
21393 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
21394 #define I2S_TCR5_WNW_MASK                        0x1F000000u
21395 #define I2S_TCR5_WNW_SHIFT                       24
21396 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
21397 /* TDR Bit Fields */
21398 #define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
21399 #define I2S_TDR_TDR_SHIFT                        0
21400 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
21401 /* TFR Bit Fields */
21402 #define I2S_TFR_RFP_MASK                         0x3Fu
21403 #define I2S_TFR_RFP_SHIFT                        0
21404 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
21405 #define I2S_TFR_WFP_MASK                         0x3F0000u
21406 #define I2S_TFR_WFP_SHIFT                        16
21407 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
21408 /* TMR Bit Fields */
21409 #define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
21410 #define I2S_TMR_TWM_SHIFT                        0
21411 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
21412 /* RCSR Bit Fields */
21413 #define I2S_RCSR_FRDE_MASK                       0x1u
21414 #define I2S_RCSR_FRDE_SHIFT                      0
21415 #define I2S_RCSR_FWDE_MASK                       0x2u
21416 #define I2S_RCSR_FWDE_SHIFT                      1
21417 #define I2S_RCSR_FRIE_MASK                       0x100u
21418 #define I2S_RCSR_FRIE_SHIFT                      8
21419 #define I2S_RCSR_FWIE_MASK                       0x200u
21420 #define I2S_RCSR_FWIE_SHIFT                      9
21421 #define I2S_RCSR_FEIE_MASK                       0x400u
21422 #define I2S_RCSR_FEIE_SHIFT                      10
21423 #define I2S_RCSR_SEIE_MASK                       0x800u
21424 #define I2S_RCSR_SEIE_SHIFT                      11
21425 #define I2S_RCSR_WSIE_MASK                       0x1000u
21426 #define I2S_RCSR_WSIE_SHIFT                      12
21427 #define I2S_RCSR_FRF_MASK                        0x10000u
21428 #define I2S_RCSR_FRF_SHIFT                       16
21429 #define I2S_RCSR_FWF_MASK                        0x20000u
21430 #define I2S_RCSR_FWF_SHIFT                       17
21431 #define I2S_RCSR_FEF_MASK                        0x40000u
21432 #define I2S_RCSR_FEF_SHIFT                       18
21433 #define I2S_RCSR_SEF_MASK                        0x80000u
21434 #define I2S_RCSR_SEF_SHIFT                       19
21435 #define I2S_RCSR_WSF_MASK                        0x100000u
21436 #define I2S_RCSR_WSF_SHIFT                       20
21437 #define I2S_RCSR_SR_MASK                         0x1000000u
21438 #define I2S_RCSR_SR_SHIFT                        24
21439 #define I2S_RCSR_FR_MASK                         0x2000000u
21440 #define I2S_RCSR_FR_SHIFT                        25
21441 #define I2S_RCSR_BCE_MASK                        0x10000000u
21442 #define I2S_RCSR_BCE_SHIFT                       28
21443 #define I2S_RCSR_DBGE_MASK                       0x20000000u
21444 #define I2S_RCSR_DBGE_SHIFT                      29
21445 #define I2S_RCSR_STOPE_MASK                      0x40000000u
21446 #define I2S_RCSR_STOPE_SHIFT                     30
21447 #define I2S_RCSR_RE_MASK                         0x80000000u
21448 #define I2S_RCSR_RE_SHIFT                        31
21449 /* RCR1 Bit Fields */
21450 #define I2S_RCR1_RFW_MASK                        0x1Fu
21451 #define I2S_RCR1_RFW_SHIFT                       0
21452 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
21453 /* RCR2 Bit Fields */
21454 #define I2S_RCR2_DIV_MASK                        0xFFu
21455 #define I2S_RCR2_DIV_SHIFT                       0
21456 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
21457 #define I2S_RCR2_BCD_MASK                        0x1000000u
21458 #define I2S_RCR2_BCD_SHIFT                       24
21459 #define I2S_RCR2_BCP_MASK                        0x2000000u
21460 #define I2S_RCR2_BCP_SHIFT                       25
21461 #define I2S_RCR2_MSEL_MASK                       0xC000000u
21462 #define I2S_RCR2_MSEL_SHIFT                      26
21463 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
21464 #define I2S_RCR2_BCI_MASK                        0x10000000u
21465 #define I2S_RCR2_BCI_SHIFT                       28
21466 #define I2S_RCR2_BCS_MASK                        0x20000000u
21467 #define I2S_RCR2_BCS_SHIFT                       29
21468 #define I2S_RCR2_SYNC_MASK                       0xC0000000u
21469 #define I2S_RCR2_SYNC_SHIFT                      30
21470 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
21471 /* RCR3 Bit Fields */
21472 #define I2S_RCR3_WDFL_MASK                       0x1Fu
21473 #define I2S_RCR3_WDFL_SHIFT                      0
21474 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
21475 #define I2S_RCR3_RCE_MASK                        0x10000u
21476 #define I2S_RCR3_RCE_SHIFT                       16
21477 /* RCR4 Bit Fields */
21478 #define I2S_RCR4_FSD_MASK                        0x1u
21479 #define I2S_RCR4_FSD_SHIFT                       0
21480 #define I2S_RCR4_FSP_MASK                        0x2u
21481 #define I2S_RCR4_FSP_SHIFT                       1
21482 #define I2S_RCR4_FSE_MASK                        0x8u
21483 #define I2S_RCR4_FSE_SHIFT                       3
21484 #define I2S_RCR4_MF_MASK                         0x10u
21485 #define I2S_RCR4_MF_SHIFT                        4
21486 #define I2S_RCR4_SYWD_MASK                       0x1F00u
21487 #define I2S_RCR4_SYWD_SHIFT                      8
21488 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
21489 #define I2S_RCR4_FRSZ_MASK                       0x1F0000u
21490 #define I2S_RCR4_FRSZ_SHIFT                      16
21491 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
21492 /* RCR5 Bit Fields */
21493 #define I2S_RCR5_FBT_MASK                        0x1F00u
21494 #define I2S_RCR5_FBT_SHIFT                       8
21495 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
21496 #define I2S_RCR5_W0W_MASK                        0x1F0000u
21497 #define I2S_RCR5_W0W_SHIFT                       16
21498 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
21499 #define I2S_RCR5_WNW_MASK                        0x1F000000u
21500 #define I2S_RCR5_WNW_SHIFT                       24
21501 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
21502 /* RDR Bit Fields */
21503 #define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
21504 #define I2S_RDR_RDR_SHIFT                        0
21505 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
21506 /* RFR Bit Fields */
21507 #define I2S_RFR_RFP_MASK                         0x3Fu
21508 #define I2S_RFR_RFP_SHIFT                        0
21509 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
21510 #define I2S_RFR_WFP_MASK                         0x3F0000u
21511 #define I2S_RFR_WFP_SHIFT                        16
21512 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
21513 /* RMR Bit Fields */
21514 #define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
21515 #define I2S_RMR_RWM_SHIFT                        0
21516 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
21517 
21518 /*!
21519  * @}
21520  */ /* end of group I2S_Register_Masks */
21521 
21522 /* I2S - Peripheral instance base addresses */
21523 /** Peripheral I2S1 base address */
21524 #define I2S1_BASE                                (0x308A0000u)
21525 /** Peripheral I2S1 base pointer */
21526 #define I2S1                                     ((I2S_Type *)I2S1_BASE)
21527 #define I2S1_BASE_PTR                            (I2S1)
21528 /** Peripheral I2S2 base address */
21529 #define I2S2_BASE                                (0x308B0000u)
21530 /** Peripheral I2S2 base pointer */
21531 #define I2S2                                     ((I2S_Type *)I2S2_BASE)
21532 #define I2S2_BASE_PTR                            (I2S2)
21533 /** Peripheral I2S3 base address */
21534 #define I2S3_BASE                                (0x308C0000u)
21535 /** Peripheral I2S3 base pointer */
21536 #define I2S3                                     ((I2S_Type *)I2S3_BASE)
21537 #define I2S3_BASE_PTR                            (I2S3)
21538 /** Array initializer of I2S peripheral base addresses */
21539 #define I2S_BASE_ADDRS                           { I2S1_BASE, I2S2_BASE, I2S3_BASE }
21540 /** Array initializer of I2S peripheral base pointers */
21541 #define I2S_BASE_PTRS                            { I2S1, I2S2, I2S3 }
21542 /** Interrupt vectors for the I2S peripheral type */
21543 #define SAI_IRQS                                 { SAI1_IRQn, SAI2_IRQn, SAI3_IRQn }
21544 /* ----------------------------------------------------------------------------
21545    -- I2S - Register accessor macros
21546    ---------------------------------------------------------------------------- */
21547 
21548 /*!
21549  * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
21550  * @{
21551  */
21552 
21553 
21554 /* I2S - Register instance definitions */
21555 /* I2S1 */
21556 #define I2S1_TCSR                                I2S_TCSR_REG(I2S1_BASE_PTR)
21557 #define I2S1_TCR1                                I2S_TCR1_REG(I2S1_BASE_PTR)
21558 #define I2S1_TCR2                                I2S_TCR2_REG(I2S1_BASE_PTR)
21559 #define I2S1_TCR3                                I2S_TCR3_REG(I2S1_BASE_PTR)
21560 #define I2S1_TCR4                                I2S_TCR4_REG(I2S1_BASE_PTR)
21561 #define I2S1_TCR5                                I2S_TCR5_REG(I2S1_BASE_PTR)
21562 #define I2S1_TDR0                                I2S_TDR_REG(I2S1_BASE_PTR,0)
21563 #define I2S1_TFR0                                I2S_TFR_REG(I2S1_BASE_PTR,0)
21564 #define I2S1_TMR                                 I2S_TMR_REG(I2S1_BASE_PTR)
21565 #define I2S1_RCSR                                I2S_RCSR_REG(I2S1_BASE_PTR)
21566 #define I2S1_RCR1                                I2S_RCR1_REG(I2S1_BASE_PTR)
21567 #define I2S1_RCR2                                I2S_RCR2_REG(I2S1_BASE_PTR)
21568 #define I2S1_RCR3                                I2S_RCR3_REG(I2S1_BASE_PTR)
21569 #define I2S1_RCR4                                I2S_RCR4_REG(I2S1_BASE_PTR)
21570 #define I2S1_RCR5                                I2S_RCR5_REG(I2S1_BASE_PTR)
21571 #define I2S1_RDR0                                I2S_RDR_REG(I2S1_BASE_PTR,0)
21572 #define I2S1_RFR0                                I2S_RFR_REG(I2S1_BASE_PTR,0)
21573 #define I2S1_RMR                                 I2S_RMR_REG(I2S1_BASE_PTR)
21574 /* I2S2 */
21575 #define I2S2_TCSR                                I2S_TCSR_REG(I2S2_BASE_PTR)
21576 #define I2S2_TCR1                                I2S_TCR1_REG(I2S2_BASE_PTR)
21577 #define I2S2_TCR2                                I2S_TCR2_REG(I2S2_BASE_PTR)
21578 #define I2S2_TCR3                                I2S_TCR3_REG(I2S2_BASE_PTR)
21579 #define I2S2_TCR4                                I2S_TCR4_REG(I2S2_BASE_PTR)
21580 #define I2S2_TCR5                                I2S_TCR5_REG(I2S2_BASE_PTR)
21581 #define I2S2_TDR0                                I2S_TDR_REG(I2S2_BASE_PTR,0)
21582 #define I2S2_TFR0                                I2S_TFR_REG(I2S2_BASE_PTR,0)
21583 #define I2S2_TMR                                 I2S_TMR_REG(I2S2_BASE_PTR)
21584 #define I2S2_RCSR                                I2S_RCSR_REG(I2S2_BASE_PTR)
21585 #define I2S2_RCR1                                I2S_RCR1_REG(I2S2_BASE_PTR)
21586 #define I2S2_RCR2                                I2S_RCR2_REG(I2S2_BASE_PTR)
21587 #define I2S2_RCR3                                I2S_RCR3_REG(I2S2_BASE_PTR)
21588 #define I2S2_RCR4                                I2S_RCR4_REG(I2S2_BASE_PTR)
21589 #define I2S2_RCR5                                I2S_RCR5_REG(I2S2_BASE_PTR)
21590 #define I2S2_RDR0                                I2S_RDR_REG(I2S2_BASE_PTR,0)
21591 #define I2S2_RFR0                                I2S_RFR_REG(I2S2_BASE_PTR,0)
21592 #define I2S2_RMR                                 I2S_RMR_REG(I2S2_BASE_PTR)
21593 /* I2S3 */
21594 #define I2S3_TCSR                                I2S_TCSR_REG(I2S3_BASE_PTR)
21595 #define I2S3_TCR1                                I2S_TCR1_REG(I2S3_BASE_PTR)
21596 #define I2S3_TCR2                                I2S_TCR2_REG(I2S3_BASE_PTR)
21597 #define I2S3_TCR3                                I2S_TCR3_REG(I2S3_BASE_PTR)
21598 #define I2S3_TCR4                                I2S_TCR4_REG(I2S3_BASE_PTR)
21599 #define I2S3_TCR5                                I2S_TCR5_REG(I2S3_BASE_PTR)
21600 #define I2S3_TDR0                                I2S_TDR_REG(I2S3_BASE_PTR,0)
21601 #define I2S3_TFR0                                I2S_TFR_REG(I2S3_BASE_PTR,0)
21602 #define I2S3_TMR                                 I2S_TMR_REG(I2S3_BASE_PTR)
21603 #define I2S3_RCSR                                I2S_RCSR_REG(I2S3_BASE_PTR)
21604 #define I2S3_RCR1                                I2S_RCR1_REG(I2S3_BASE_PTR)
21605 #define I2S3_RCR2                                I2S_RCR2_REG(I2S3_BASE_PTR)
21606 #define I2S3_RCR3                                I2S_RCR3_REG(I2S3_BASE_PTR)
21607 #define I2S3_RCR4                                I2S_RCR4_REG(I2S3_BASE_PTR)
21608 #define I2S3_RCR5                                I2S_RCR5_REG(I2S3_BASE_PTR)
21609 #define I2S3_RDR0                                I2S_RDR_REG(I2S3_BASE_PTR,0)
21610 #define I2S3_RFR0                                I2S_RFR_REG(I2S3_BASE_PTR,0)
21611 #define I2S3_RMR                                 I2S_RMR_REG(I2S3_BASE_PTR)
21612 /* I2S - Register array accessors */
21613 #define I2S1_TDR(index)                          I2S_TDR_REG(I2S1_BASE_PTR,index)
21614 #define I2S2_TDR(index)                          I2S_TDR_REG(I2S2_BASE_PTR,index)
21615 #define I2S3_TDR(index)                          I2S_TDR_REG(I2S3_BASE_PTR,index)
21616 #define I2S1_TFR(index)                          I2S_TFR_REG(I2S1_BASE_PTR,index)
21617 #define I2S2_TFR(index)                          I2S_TFR_REG(I2S2_BASE_PTR,index)
21618 #define I2S3_TFR(index)                          I2S_TFR_REG(I2S3_BASE_PTR,index)
21619 #define I2S1_RDR(index)                          I2S_RDR_REG(I2S1_BASE_PTR,index)
21620 #define I2S2_RDR(index)                          I2S_RDR_REG(I2S2_BASE_PTR,index)
21621 #define I2S3_RDR(index)                          I2S_RDR_REG(I2S3_BASE_PTR,index)
21622 #define I2S1_RFR(index)                          I2S_RFR_REG(I2S1_BASE_PTR,index)
21623 #define I2S2_RFR(index)                          I2S_RFR_REG(I2S2_BASE_PTR,index)
21624 #define I2S3_RFR(index)                          I2S_RFR_REG(I2S3_BASE_PTR,index)
21625 /*!
21626  * @}
21627  */ /* end of group I2S_Register_Accessor_Macros */
21628 
21629 
21630 /*!
21631  * @}
21632  */ /* end of group I2S_Peripheral */
21633 
21634 /* ----------------------------------------------------------------------------
21635    -- IOMUXC Peripheral Access Layer
21636    ---------------------------------------------------------------------------- */
21637 
21638 /*!
21639  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
21640  * @{
21641  */
21642 
21643 /** IOMUXC - Register Layout Typedef */
21644 typedef struct {
21645   uint8_t RESERVED_0[20];
21646   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO08;              /**< SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register, offset: 0x14 */
21647   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO09;              /**< SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register, offset: 0x18 */
21648   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO10;              /**< SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register, offset: 0x1C */
21649   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO11;              /**< SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register, offset: 0x20 */
21650   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO12;              /**< SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register, offset: 0x24 */
21651   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO13;              /**< SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register, offset: 0x28 */
21652   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO14;              /**< SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register, offset: 0x2C */
21653   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO15;              /**< SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register, offset: 0x30 */
21654   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA00;             /**< SW_MUX_CTL_PAD_EPDC_DATA00 SW MUX Control Register, offset: 0x34 */
21655   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA01;             /**< SW_MUX_CTL_PAD_EPDC_DATA01 SW MUX Control Register, offset: 0x38 */
21656   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA02;             /**< SW_MUX_CTL_PAD_EPDC_DATA02 SW MUX Control Register, offset: 0x3C */
21657   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA03;             /**< SW_MUX_CTL_PAD_EPDC_DATA03 SW MUX Control Register, offset: 0x40 */
21658   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA04;             /**< SW_MUX_CTL_PAD_EPDC_DATA04 SW MUX Control Register, offset: 0x44 */
21659   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA05;             /**< SW_MUX_CTL_PAD_EPDC_DATA05 SW MUX Control Register, offset: 0x48 */
21660   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA06;             /**< SW_MUX_CTL_PAD_EPDC_DATA06 SW MUX Control Register, offset: 0x4C */
21661   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA07;             /**< SW_MUX_CTL_PAD_EPDC_DATA07 SW MUX Control Register, offset: 0x50 */
21662   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA08;             /**< SW_MUX_CTL_PAD_EPDC_DATA08 SW MUX Control Register, offset: 0x54 */
21663   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA09;             /**< SW_MUX_CTL_PAD_EPDC_DATA09 SW MUX Control Register, offset: 0x58 */
21664   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA10;             /**< SW_MUX_CTL_PAD_EPDC_DATA10 SW MUX Control Register, offset: 0x5C */
21665   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA11;             /**< SW_MUX_CTL_PAD_EPDC_DATA11 SW MUX Control Register, offset: 0x60 */
21666   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA12;             /**< SW_MUX_CTL_PAD_EPDC_DATA12 SW MUX Control Register, offset: 0x64 */
21667   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA13;             /**< SW_MUX_CTL_PAD_EPDC_DATA13 SW MUX Control Register, offset: 0x68 */
21668   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA14;             /**< SW_MUX_CTL_PAD_EPDC_DATA14 SW MUX Control Register, offset: 0x6C */
21669   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_DATA15;             /**< SW_MUX_CTL_PAD_EPDC_DATA15 SW MUX Control Register, offset: 0x70 */
21670   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDCLK;              /**< SW_MUX_CTL_PAD_EPDC_SDCLK SW MUX Control Register, offset: 0x74 */
21671   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDLE;               /**< SW_MUX_CTL_PAD_EPDC_SDLE SW MUX Control Register, offset: 0x78 */
21672   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDOE;               /**< SW_MUX_CTL_PAD_EPDC_SDOE SW MUX Control Register, offset: 0x7C */
21673   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDSHR;              /**< SW_MUX_CTL_PAD_EPDC_SDSHR SW MUX Control Register, offset: 0x80 */
21674   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDCE0;              /**< SW_MUX_CTL_PAD_EPDC_SDCE0 SW MUX Control Register, offset: 0x84 */
21675   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDCE1;              /**< SW_MUX_CTL_PAD_EPDC_SDCE1 SW MUX Control Register, offset: 0x88 */
21676   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDCE2;              /**< SW_MUX_CTL_PAD_EPDC_SDCE2 SW MUX Control Register, offset: 0x8C */
21677   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_SDCE3;              /**< SW_MUX_CTL_PAD_EPDC_SDCE3 SW MUX Control Register, offset: 0x90 */
21678   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_GDCLK;              /**< SW_MUX_CTL_PAD_EPDC_GDCLK SW MUX Control Register, offset: 0x94 */
21679   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_GDOE;               /**< SW_MUX_CTL_PAD_EPDC_GDOE SW MUX Control Register, offset: 0x98 */
21680   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_GDRL;               /**< SW_MUX_CTL_PAD_EPDC_GDRL SW MUX Control Register, offset: 0x9C */
21681   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_GDSP;               /**< SW_MUX_CTL_PAD_EPDC_GDSP SW MUX Control Register, offset: 0xA0 */
21682   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_BDR0;               /**< SW_MUX_CTL_PAD_EPDC_BDR0 SW MUX Control Register, offset: 0xA4 */
21683   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_BDR1;               /**< SW_MUX_CTL_PAD_EPDC_BDR1 SW MUX Control Register, offset: 0xA8 */
21684   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_PWR_COM;            /**< SW_MUX_CTL_PAD_EPDC_PWR_COM SW MUX Control Register, offset: 0xAC */
21685   __IO  uint32_t SW_MUX_CTL_PAD_EPDC_PWR_STAT;           /**< SW_MUX_CTL_PAD_EPDC_PWR_STAT SW MUX Control Register, offset: 0xB0 */
21686   __IO  uint32_t SW_MUX_CTL_PAD_LCD_CLK;                 /**< SW_MUX_CTL_PAD_LCD_CLK SW MUX Control Register, offset: 0xB4 */
21687   __IO  uint32_t SW_MUX_CTL_PAD_LCD_ENABLE;              /**< SW_MUX_CTL_PAD_LCD_ENABLE SW MUX Control Register, offset: 0xB8 */
21688   __IO  uint32_t SW_MUX_CTL_PAD_LCD_HSYNC;               /**< SW_MUX_CTL_PAD_LCD_HSYNC SW MUX Control Register, offset: 0xBC */
21689   __IO  uint32_t SW_MUX_CTL_PAD_LCD_VSYNC;               /**< SW_MUX_CTL_PAD_LCD_VSYNC SW MUX Control Register, offset: 0xC0 */
21690   __IO  uint32_t SW_MUX_CTL_PAD_LCD_RESET;               /**< SW_MUX_CTL_PAD_LCD_RESET SW MUX Control Register, offset: 0xC4 */
21691   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA00;              /**< SW_MUX_CTL_PAD_LCD_DATA00 SW MUX Control Register, offset: 0xC8 */
21692   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA01;              /**< SW_MUX_CTL_PAD_LCD_DATA01 SW MUX Control Register, offset: 0xCC */
21693   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA02;              /**< SW_MUX_CTL_PAD_LCD_DATA02 SW MUX Control Register, offset: 0xD0 */
21694   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA03;              /**< SW_MUX_CTL_PAD_LCD_DATA03 SW MUX Control Register, offset: 0xD4 */
21695   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA04;              /**< SW_MUX_CTL_PAD_LCD_DATA04 SW MUX Control Register, offset: 0xD8 */
21696   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA05;              /**< SW_MUX_CTL_PAD_LCD_DATA05 SW MUX Control Register, offset: 0xDC */
21697   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA06;              /**< SW_MUX_CTL_PAD_LCD_DATA06 SW MUX Control Register, offset: 0xE0 */
21698   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA07;              /**< SW_MUX_CTL_PAD_LCD_DATA07 SW MUX Control Register, offset: 0xE4 */
21699   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA08;              /**< SW_MUX_CTL_PAD_LCD_DATA08 SW MUX Control Register, offset: 0xE8 */
21700   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA09;              /**< SW_MUX_CTL_PAD_LCD_DATA09 SW MUX Control Register, offset: 0xEC */
21701   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA10;              /**< SW_MUX_CTL_PAD_LCD_DATA10 SW MUX Control Register, offset: 0xF0 */
21702   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA11;              /**< SW_MUX_CTL_PAD_LCD_DATA11 SW MUX Control Register, offset: 0xF4 */
21703   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA12;              /**< SW_MUX_CTL_PAD_LCD_DATA12 SW MUX Control Register, offset: 0xF8 */
21704   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA13;              /**< SW_MUX_CTL_PAD_LCD_DATA13 SW MUX Control Register, offset: 0xFC */
21705   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA14;              /**< SW_MUX_CTL_PAD_LCD_DATA14 SW MUX Control Register, offset: 0x100 */
21706   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA15;              /**< SW_MUX_CTL_PAD_LCD_DATA15 SW MUX Control Register, offset: 0x104 */
21707   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA16;              /**< SW_MUX_CTL_PAD_LCD_DATA16 SW MUX Control Register, offset: 0x108 */
21708   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA17;              /**< SW_MUX_CTL_PAD_LCD_DATA17 SW MUX Control Register, offset: 0x10C */
21709   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA18;              /**< SW_MUX_CTL_PAD_LCD_DATA18 SW MUX Control Register, offset: 0x110 */
21710   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA19;              /**< SW_MUX_CTL_PAD_LCD_DATA19 SW MUX Control Register, offset: 0x114 */
21711   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA20;              /**< SW_MUX_CTL_PAD_LCD_DATA20 SW MUX Control Register, offset: 0x118 */
21712   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA21;              /**< SW_MUX_CTL_PAD_LCD_DATA21 SW MUX Control Register, offset: 0x11C */
21713   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA22;              /**< SW_MUX_CTL_PAD_LCD_DATA22 SW MUX Control Register, offset: 0x120 */
21714   __IO  uint32_t SW_MUX_CTL_PAD_LCD_DATA23;              /**< SW_MUX_CTL_PAD_LCD_DATA23 SW MUX Control Register, offset: 0x124 */
21715   __IO  uint32_t SW_MUX_CTL_PAD_UART1_RX_DATA;           /**< SW_MUX_CTL_PAD_UART1_RX_DATA SW MUX Control Register, offset: 0x128 */
21716   __IO  uint32_t SW_MUX_CTL_PAD_UART1_TX_DATA;           /**< SW_MUX_CTL_PAD_UART1_TX_DATA SW MUX Control Register, offset: 0x12C */
21717   __IO  uint32_t SW_MUX_CTL_PAD_UART2_RX_DATA;           /**< SW_MUX_CTL_PAD_UART2_RX_DATA SW MUX Control Register, offset: 0x130 */
21718   __IO  uint32_t SW_MUX_CTL_PAD_UART2_TX_DATA;           /**< SW_MUX_CTL_PAD_UART2_TX_DATA SW MUX Control Register, offset: 0x134 */
21719   __IO  uint32_t SW_MUX_CTL_PAD_UART3_RX_DATA;           /**< SW_MUX_CTL_PAD_UART3_RX_DATA SW MUX Control Register, offset: 0x138 */
21720   __IO  uint32_t SW_MUX_CTL_PAD_UART3_TX_DATA;           /**< SW_MUX_CTL_PAD_UART3_TX_DATA SW MUX Control Register, offset: 0x13C */
21721   __IO  uint32_t SW_MUX_CTL_PAD_UART3_RTS_B;             /**< SW_MUX_CTL_PAD_UART3_RTS_B SW MUX Control Register, offset: 0x140 */
21722   __IO  uint32_t SW_MUX_CTL_PAD_UART3_CTS_B;             /**< SW_MUX_CTL_PAD_UART3_CTS_B SW MUX Control Register, offset: 0x144 */
21723   __IO  uint32_t SW_MUX_CTL_PAD_I2C1_SCL;                /**< SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register, offset: 0x148 */
21724   __IO  uint32_t SW_MUX_CTL_PAD_I2C1_SDA;                /**< SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register, offset: 0x14C */
21725   __IO  uint32_t SW_MUX_CTL_PAD_I2C2_SCL;                /**< SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register, offset: 0x150 */
21726   __IO  uint32_t SW_MUX_CTL_PAD_I2C2_SDA;                /**< SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register, offset: 0x154 */
21727   __IO  uint32_t SW_MUX_CTL_PAD_I2C3_SCL;                /**< SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register, offset: 0x158 */
21728   __IO  uint32_t SW_MUX_CTL_PAD_I2C3_SDA;                /**< SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register, offset: 0x15C */
21729   __IO  uint32_t SW_MUX_CTL_PAD_I2C4_SCL;                /**< SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register, offset: 0x160 */
21730   __IO  uint32_t SW_MUX_CTL_PAD_I2C4_SDA;                /**< SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register, offset: 0x164 */
21731   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI1_SCLK;             /**< SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register, offset: 0x168 */
21732   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI1_MOSI;             /**< SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register, offset: 0x16C */
21733   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI1_MISO;             /**< SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register, offset: 0x170 */
21734   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI1_SS0;              /**< SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register, offset: 0x174 */
21735   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI2_SCLK;             /**< SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register, offset: 0x178 */
21736   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI2_MOSI;             /**< SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register, offset: 0x17C */
21737   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI2_MISO;             /**< SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register, offset: 0x180 */
21738   __IO  uint32_t SW_MUX_CTL_PAD_ECSPI2_SS0;              /**< SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register, offset: 0x184 */
21739   __IO  uint32_t SW_MUX_CTL_PAD_SD1_CD_B;                /**< SW_MUX_CTL_PAD_SD1_CD_B SW MUX Control Register, offset: 0x188 */
21740   __IO  uint32_t SW_MUX_CTL_PAD_SD1_WP;                  /**< SW_MUX_CTL_PAD_SD1_WP SW MUX Control Register, offset: 0x18C */
21741   __IO  uint32_t SW_MUX_CTL_PAD_SD1_RESET_B;             /**< SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register, offset: 0x190 */
21742   __IO  uint32_t SW_MUX_CTL_PAD_SD1_CLK;                 /**< SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register, offset: 0x194 */
21743   __IO  uint32_t SW_MUX_CTL_PAD_SD1_CMD;                 /**< SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register, offset: 0x198 */
21744   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA0;               /**< SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register, offset: 0x19C */
21745   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA1;               /**< SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register, offset: 0x1A0 */
21746   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA2;               /**< SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register, offset: 0x1A4 */
21747   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA3;               /**< SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register, offset: 0x1A8 */
21748   __IO  uint32_t SW_MUX_CTL_PAD_SD2_CD_B;                /**< SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register, offset: 0x1AC */
21749   __IO  uint32_t SW_MUX_CTL_PAD_SD2_WP;                  /**< SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register, offset: 0x1B0 */
21750   __IO  uint32_t SW_MUX_CTL_PAD_SD2_RESET_B;             /**< SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register, offset: 0x1B4 */
21751   __IO  uint32_t SW_MUX_CTL_PAD_SD2_CLK;                 /**< SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register, offset: 0x1B8 */
21752   __IO  uint32_t SW_MUX_CTL_PAD_SD2_CMD;                 /**< SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register, offset: 0x1BC */
21753   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA0;               /**< SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register, offset: 0x1C0 */
21754   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA1;               /**< SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register, offset: 0x1C4 */
21755   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA2;               /**< SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register, offset: 0x1C8 */
21756   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA3;               /**< SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register, offset: 0x1CC */
21757   __IO  uint32_t SW_MUX_CTL_PAD_SD3_CLK;                 /**< SW_MUX_CTL_PAD_SD3_CLK SW MUX Control Register, offset: 0x1D0 */
21758   __IO  uint32_t SW_MUX_CTL_PAD_SD3_CMD;                 /**< SW_MUX_CTL_PAD_SD3_CMD SW MUX Control Register, offset: 0x1D4 */
21759   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA0;               /**< SW_MUX_CTL_PAD_SD3_DATA0 SW MUX Control Register, offset: 0x1D8 */
21760   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA1;               /**< SW_MUX_CTL_PAD_SD3_DATA1 SW MUX Control Register, offset: 0x1DC */
21761   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA2;               /**< SW_MUX_CTL_PAD_SD3_DATA2 SW MUX Control Register, offset: 0x1E0 */
21762   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA3;               /**< SW_MUX_CTL_PAD_SD3_DATA3 SW MUX Control Register, offset: 0x1E4 */
21763   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA4;               /**< SW_MUX_CTL_PAD_SD3_DATA4 SW MUX Control Register, offset: 0x1E8 */
21764   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA5;               /**< SW_MUX_CTL_PAD_SD3_DATA5 SW MUX Control Register, offset: 0x1EC */
21765   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA6;               /**< SW_MUX_CTL_PAD_SD3_DATA6 SW MUX Control Register, offset: 0x1F0 */
21766   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA7;               /**< SW_MUX_CTL_PAD_SD3_DATA7 SW MUX Control Register, offset: 0x1F4 */
21767   __IO  uint32_t SW_MUX_CTL_PAD_SD3_STROBE;              /**< SW_MUX_CTL_PAD_SD3_STROBE SW MUX Control Register, offset: 0x1F8 */
21768   __IO  uint32_t SW_MUX_CTL_PAD_SD3_RESET_B;             /**< SW_MUX_CTL_PAD_SD3_RESET_B SW MUX Control Register, offset: 0x1FC */
21769   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_RX_DATA;            /**< SW_MUX_CTL_PAD_SAI1_RX_DATA SW MUX Control Register, offset: 0x200 */
21770   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_TX_BCLK;            /**< SW_MUX_CTL_PAD_SAI1_TX_BCLK SW MUX Control Register, offset: 0x204 */
21771   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_TX_SYNC;            /**< SW_MUX_CTL_PAD_SAI1_TX_SYNC SW MUX Control Register, offset: 0x208 */
21772   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_TX_DATA;            /**< SW_MUX_CTL_PAD_SAI1_TX_DATA SW MUX Control Register, offset: 0x20C */
21773   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_RX_SYNC;            /**< SW_MUX_CTL_PAD_SAI1_RX_SYNC SW MUX Control Register, offset: 0x210 */
21774   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_RX_BCLK;            /**< SW_MUX_CTL_PAD_SAI1_RX_BCLK SW MUX Control Register, offset: 0x214 */
21775   __IO  uint32_t SW_MUX_CTL_PAD_SAI1_MCLK;               /**< SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register, offset: 0x218 */
21776   __IO  uint32_t SW_MUX_CTL_PAD_SAI2_TX_SYNC;            /**< SW_MUX_CTL_PAD_SAI2_TX_SYNC SW MUX Control Register, offset: 0x21C */
21777   __IO  uint32_t SW_MUX_CTL_PAD_SAI2_TX_BCLK;            /**< SW_MUX_CTL_PAD_SAI2_TX_BCLK SW MUX Control Register, offset: 0x220 */
21778   __IO  uint32_t SW_MUX_CTL_PAD_SAI2_RX_DATA;            /**< SW_MUX_CTL_PAD_SAI2_RX_DATA SW MUX Control Register, offset: 0x224 */
21779   __IO  uint32_t SW_MUX_CTL_PAD_SAI2_TX_DATA;            /**< SW_MUX_CTL_PAD_SAI2_TX_DATA SW MUX Control Register, offset: 0x228 */
21780   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD0;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD0 SW MUX Control Register, offset: 0x22C */
21781   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD1;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD1 SW MUX Control Register, offset: 0x230 */
21782   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD2;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD2 SW MUX Control Register, offset: 0x234 */
21783   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD3;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD3 SW MUX Control Register, offset: 0x238 */
21784   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL;      /**< SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL SW MUX Control Register, offset: 0x23C */
21785   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RXC;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_RXC SW MUX Control Register, offset: 0x240 */
21786   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD0;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD0 SW MUX Control Register, offset: 0x244 */
21787   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD1;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD1 SW MUX Control Register, offset: 0x248 */
21788   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD2;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD2 SW MUX Control Register, offset: 0x24C */
21789   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD3;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD3 SW MUX Control Register, offset: 0x250 */
21790   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL;      /**< SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL SW MUX Control Register, offset: 0x254 */
21791   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TXC;         /**< SW_MUX_CTL_PAD_ENET1_RGMII_TXC SW MUX Control Register, offset: 0x258 */
21792   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_TX_CLK;            /**< SW_MUX_CTL_PAD_ENET1_TX_CLK SW MUX Control Register, offset: 0x25C */
21793   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RX_CLK;            /**< SW_MUX_CTL_PAD_ENET1_RX_CLK SW MUX Control Register, offset: 0x260 */
21794   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_CRS;               /**< SW_MUX_CTL_PAD_ENET1_CRS SW MUX Control Register, offset: 0x264 */
21795   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_COL;               /**< SW_MUX_CTL_PAD_ENET1_COL SW MUX Control Register, offset: 0x268 */
21796   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO08;              /**< SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register, offset: 0x26C */
21797   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO09;              /**< SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register, offset: 0x270 */
21798   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO10;              /**< SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register, offset: 0x274 */
21799   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO11;              /**< SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register, offset: 0x278 */
21800   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO12;              /**< SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register, offset: 0x27C */
21801   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO13;              /**< SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register, offset: 0x280 */
21802   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO14;              /**< SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register, offset: 0x284 */
21803   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO15;              /**< SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register, offset: 0x288 */
21804   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_MOD;                /**< SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register, offset: 0x28C */
21805   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TCK;                /**< SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register, offset: 0x290 */
21806   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TDI;                /**< SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register, offset: 0x294 */
21807   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TDO;                /**< SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register, offset: 0x298 */
21808   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TMS;                /**< SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register, offset: 0x29C */
21809   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TRST_B;             /**< SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register, offset: 0x2A0 */
21810   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA00;             /**< SW_PAD_CTL_PAD_EPDC_DATA00 SW PAD Control Register, offset: 0x2A4 */
21811   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA01;             /**< SW_PAD_CTL_PAD_EPDC_DATA01 SW PAD Control Register, offset: 0x2A8 */
21812   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA02;             /**< SW_PAD_CTL_PAD_EPDC_DATA02 SW PAD Control Register, offset: 0x2AC */
21813   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA03;             /**< SW_PAD_CTL_PAD_EPDC_DATA03 SW PAD Control Register, offset: 0x2B0 */
21814   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA04;             /**< SW_PAD_CTL_PAD_EPDC_DATA04 SW PAD Control Register, offset: 0x2B4 */
21815   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA05;             /**< SW_PAD_CTL_PAD_EPDC_DATA05 SW PAD Control Register, offset: 0x2B8 */
21816   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA06;             /**< SW_PAD_CTL_PAD_EPDC_DATA06 SW PAD Control Register, offset: 0x2BC */
21817   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA07;             /**< SW_PAD_CTL_PAD_EPDC_DATA07 SW PAD Control Register, offset: 0x2C0 */
21818   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA08;             /**< SW_PAD_CTL_PAD_EPDC_DATA08 SW PAD Control Register, offset: 0x2C4 */
21819   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA09;             /**< SW_PAD_CTL_PAD_EPDC_DATA09 SW PAD Control Register, offset: 0x2C8 */
21820   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA10;             /**< SW_PAD_CTL_PAD_EPDC_DATA10 SW PAD Control Register, offset: 0x2CC */
21821   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA11;             /**< SW_PAD_CTL_PAD_EPDC_DATA11 SW PAD Control Register, offset: 0x2D0 */
21822   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA12;             /**< SW_PAD_CTL_PAD_EPDC_DATA12 SW PAD Control Register, offset: 0x2D4 */
21823   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA13;             /**< SW_PAD_CTL_PAD_EPDC_DATA13 SW PAD Control Register, offset: 0x2D8 */
21824   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA14;             /**< SW_PAD_CTL_PAD_EPDC_DATA14 SW PAD Control Register, offset: 0x2DC */
21825   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_DATA15;             /**< SW_PAD_CTL_PAD_EPDC_DATA15 SW PAD Control Register, offset: 0x2E0 */
21826   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDCLK;              /**< SW_PAD_CTL_PAD_EPDC_SDCLK SW PAD Control Register, offset: 0x2E4 */
21827   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDLE;               /**< SW_PAD_CTL_PAD_EPDC_SDLE SW PAD Control Register, offset: 0x2E8 */
21828   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDOE;               /**< SW_PAD_CTL_PAD_EPDC_SDOE SW PAD Control Register, offset: 0x2EC */
21829   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDSHR;              /**< SW_PAD_CTL_PAD_EPDC_SDSHR SW PAD Control Register, offset: 0x2F0 */
21830   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDCE0;              /**< SW_PAD_CTL_PAD_EPDC_SDCE0 SW PAD Control Register, offset: 0x2F4 */
21831   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDCE1;              /**< SW_PAD_CTL_PAD_EPDC_SDCE1 SW PAD Control Register, offset: 0x2F8 */
21832   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDCE2;              /**< SW_PAD_CTL_PAD_EPDC_SDCE2 SW PAD Control Register, offset: 0x2FC */
21833   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_SDCE3;              /**< SW_PAD_CTL_PAD_EPDC_SDCE3 SW PAD Control Register, offset: 0x300 */
21834   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_GDCLK;              /**< SW_PAD_CTL_PAD_EPDC_GDCLK SW PAD Control Register, offset: 0x304 */
21835   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_GDOE;               /**< SW_PAD_CTL_PAD_EPDC_GDOE SW PAD Control Register, offset: 0x308 */
21836   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_GDRL;               /**< SW_PAD_CTL_PAD_EPDC_GDRL SW PAD Control Register, offset: 0x30C */
21837   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_GDSP;               /**< SW_PAD_CTL_PAD_EPDC_GDSP SW PAD Control Register, offset: 0x310 */
21838   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_BDR0;               /**< SW_PAD_CTL_PAD_EPDC_BDR0 SW PAD Control Register, offset: 0x314 */
21839   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_BDR1;               /**< SW_PAD_CTL_PAD_EPDC_BDR1 SW PAD Control Register, offset: 0x318 */
21840   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_PWR_COM;            /**< SW_PAD_CTL_PAD_EPDC_PWR_COM SW PAD Control Register, offset: 0x31C */
21841   __IO  uint32_t SW_PAD_CTL_PAD_EPDC_PWR_STAT;           /**< SW_PAD_CTL_PAD_EPDC_PWR_STAT SW PAD Control Register, offset: 0x320 */
21842   __IO  uint32_t SW_PAD_CTL_PAD_LCD_CLK;                 /**< SW_PAD_CTL_PAD_LCD_CLK SW PAD Control Register, offset: 0x324 */
21843   __IO  uint32_t SW_PAD_CTL_PAD_LCD_ENABLE;              /**< SW_PAD_CTL_PAD_LCD_ENABLE SW PAD Control Register, offset: 0x328 */
21844   __IO  uint32_t SW_PAD_CTL_PAD_LCD_HSYNC;               /**< SW_PAD_CTL_PAD_LCD_HSYNC SW PAD Control Register, offset: 0x32C */
21845   __IO  uint32_t SW_PAD_CTL_PAD_LCD_VSYNC;               /**< SW_PAD_CTL_PAD_LCD_VSYNC SW PAD Control Register, offset: 0x330 */
21846   __IO  uint32_t SW_PAD_CTL_PAD_LCD_RESET;               /**< SW_PAD_CTL_PAD_LCD_RESET SW PAD Control Register, offset: 0x334 */
21847   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA00;              /**< SW_PAD_CTL_PAD_LCD_DATA00 SW PAD Control Register, offset: 0x338 */
21848   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA01;              /**< SW_PAD_CTL_PAD_LCD_DATA01 SW PAD Control Register, offset: 0x33C */
21849   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA02;              /**< SW_PAD_CTL_PAD_LCD_DATA02 SW PAD Control Register, offset: 0x340 */
21850   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA03;              /**< SW_PAD_CTL_PAD_LCD_DATA03 SW PAD Control Register, offset: 0x344 */
21851   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA04;              /**< SW_PAD_CTL_PAD_LCD_DATA04 SW PAD Control Register, offset: 0x348 */
21852   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA05;              /**< SW_PAD_CTL_PAD_LCD_DATA05 SW PAD Control Register, offset: 0x34C */
21853   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA06;              /**< SW_PAD_CTL_PAD_LCD_DATA06 SW PAD Control Register, offset: 0x350 */
21854   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA07;              /**< SW_PAD_CTL_PAD_LCD_DATA07 SW PAD Control Register, offset: 0x354 */
21855   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA08;              /**< SW_PAD_CTL_PAD_LCD_DATA08 SW PAD Control Register, offset: 0x358 */
21856   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA09;              /**< SW_PAD_CTL_PAD_LCD_DATA09 SW PAD Control Register, offset: 0x35C */
21857   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA10;              /**< SW_PAD_CTL_PAD_LCD_DATA10 SW PAD Control Register, offset: 0x360 */
21858   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA11;              /**< SW_PAD_CTL_PAD_LCD_DATA11 SW PAD Control Register, offset: 0x364 */
21859   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA12;              /**< SW_PAD_CTL_PAD_LCD_DATA12 SW PAD Control Register, offset: 0x368 */
21860   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA13;              /**< SW_PAD_CTL_PAD_LCD_DATA13 SW PAD Control Register, offset: 0x36C */
21861   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA14;              /**< SW_PAD_CTL_PAD_LCD_DATA14 SW PAD Control Register, offset: 0x370 */
21862   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA15;              /**< SW_PAD_CTL_PAD_LCD_DATA15 SW PAD Control Register, offset: 0x374 */
21863   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA16;              /**< SW_PAD_CTL_PAD_LCD_DATA16 SW PAD Control Register, offset: 0x378 */
21864   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA17;              /**< SW_PAD_CTL_PAD_LCD_DATA17 SW PAD Control Register, offset: 0x37C */
21865   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA18;              /**< SW_PAD_CTL_PAD_LCD_DATA18 SW PAD Control Register, offset: 0x380 */
21866   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA19;              /**< SW_PAD_CTL_PAD_LCD_DATA19 SW PAD Control Register, offset: 0x384 */
21867   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA20;              /**< SW_PAD_CTL_PAD_LCD_DATA20 SW PAD Control Register, offset: 0x388 */
21868   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA21;              /**< SW_PAD_CTL_PAD_LCD_DATA21 SW PAD Control Register, offset: 0x38C */
21869   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA22;              /**< SW_PAD_CTL_PAD_LCD_DATA22 SW PAD Control Register, offset: 0x390 */
21870   __IO  uint32_t SW_PAD_CTL_PAD_LCD_DATA23;              /**< SW_PAD_CTL_PAD_LCD_DATA23 SW PAD Control Register, offset: 0x394 */
21871   __IO  uint32_t SW_PAD_CTL_PAD_UART1_RX_DATA;           /**< SW_PAD_CTL_PAD_UART1_RX_DATA SW PAD Control Register, offset: 0x398 */
21872   __IO  uint32_t SW_PAD_CTL_PAD_UART1_TX_DATA;           /**< SW_PAD_CTL_PAD_UART1_TX_DATA SW PAD Control Register, offset: 0x39C */
21873   __IO  uint32_t SW_PAD_CTL_PAD_UART2_RX_DATA;           /**< SW_PAD_CTL_PAD_UART2_RX_DATA SW PAD Control Register, offset: 0x3A0 */
21874   __IO  uint32_t SW_PAD_CTL_PAD_UART2_TX_DATA;           /**< SW_PAD_CTL_PAD_UART2_TX_DATA SW PAD Control Register, offset: 0x3A4 */
21875   __IO  uint32_t SW_PAD_CTL_PAD_UART3_RX_DATA;           /**< SW_PAD_CTL_PAD_UART3_RX_DATA SW PAD Control Register, offset: 0x3A8 */
21876   __IO  uint32_t SW_PAD_CTL_PAD_UART3_TX_DATA;           /**< SW_PAD_CTL_PAD_UART3_TX_DATA SW PAD Control Register, offset: 0x3AC */
21877   __IO  uint32_t SW_PAD_CTL_PAD_UART3_RTS_B;             /**< SW_PAD_CTL_PAD_UART3_RTS_B SW PAD Control Register, offset: 0x3B0 */
21878   __IO  uint32_t SW_PAD_CTL_PAD_UART3_CTS_B;             /**< SW_PAD_CTL_PAD_UART3_CTS_B SW PAD Control Register, offset: 0x3B4 */
21879   __IO  uint32_t SW_PAD_CTL_PAD_I2C1_SCL;                /**< SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register, offset: 0x3B8 */
21880   __IO  uint32_t SW_PAD_CTL_PAD_I2C1_SDA;                /**< SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register, offset: 0x3BC */
21881   __IO  uint32_t SW_PAD_CTL_PAD_I2C2_SCL;                /**< SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register, offset: 0x3C0 */
21882   __IO  uint32_t SW_PAD_CTL_PAD_I2C2_SDA;                /**< SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register, offset: 0x3C4 */
21883   __IO  uint32_t SW_PAD_CTL_PAD_I2C3_SCL;                /**< SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register, offset: 0x3C8 */
21884   __IO  uint32_t SW_PAD_CTL_PAD_I2C3_SDA;                /**< SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register, offset: 0x3CC */
21885   __IO  uint32_t SW_PAD_CTL_PAD_I2C4_SCL;                /**< SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register, offset: 0x3D0 */
21886   __IO  uint32_t SW_PAD_CTL_PAD_I2C4_SDA;                /**< SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register, offset: 0x3D4 */
21887   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI1_SCLK;             /**< SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control Register, offset: 0x3D8 */
21888   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI1_MOSI;             /**< SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control Register, offset: 0x3DC */
21889   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI1_MISO;             /**< SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register, offset: 0x3E0 */
21890   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI1_SS0;              /**< SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control Register, offset: 0x3E4 */
21891   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI2_SCLK;             /**< SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control Register, offset: 0x3E8 */
21892   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI2_MOSI;             /**< SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control Register, offset: 0x3EC */
21893   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI2_MISO;             /**< SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control Register, offset: 0x3F0 */
21894   __IO  uint32_t SW_PAD_CTL_PAD_ECSPI2_SS0;              /**< SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control Register, offset: 0x3F4 */
21895   __IO  uint32_t SW_PAD_CTL_PAD_SD1_CD_B;                /**< SW_PAD_CTL_PAD_SD1_CD_B SW PAD Control Register, offset: 0x3F8 */
21896   __IO  uint32_t SW_PAD_CTL_PAD_SD1_WP;                  /**< SW_PAD_CTL_PAD_SD1_WP SW PAD Control Register, offset: 0x3FC */
21897   __IO  uint32_t SW_PAD_CTL_PAD_SD1_RESET_B;             /**< SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control Register, offset: 0x400 */
21898   __IO  uint32_t SW_PAD_CTL_PAD_SD1_CLK;                 /**< SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register, offset: 0x404 */
21899   __IO  uint32_t SW_PAD_CTL_PAD_SD1_CMD;                 /**< SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register, offset: 0x408 */
21900   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA0;               /**< SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register, offset: 0x40C */
21901   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA1;               /**< SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register, offset: 0x410 */
21902   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA2;               /**< SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register, offset: 0x414 */
21903   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA3;               /**< SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register, offset: 0x418 */
21904   __IO  uint32_t SW_PAD_CTL_PAD_SD2_CD_B;                /**< SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register, offset: 0x41C */
21905   __IO  uint32_t SW_PAD_CTL_PAD_SD2_WP;                  /**< SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register, offset: 0x420 */
21906   __IO  uint32_t SW_PAD_CTL_PAD_SD2_RESET_B;             /**< SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control Register, offset: 0x424 */
21907   __IO  uint32_t SW_PAD_CTL_PAD_SD2_CLK;                 /**< SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register, offset: 0x428 */
21908   __IO  uint32_t SW_PAD_CTL_PAD_SD2_CMD;                 /**< SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register, offset: 0x42C */
21909   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA0;               /**< SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control Register, offset: 0x430 */
21910   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA1;               /**< SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control Register, offset: 0x434 */
21911   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA2;               /**< SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control Register, offset: 0x438 */
21912   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA3;               /**< SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control Register, offset: 0x43C */
21913   __IO  uint32_t SW_PAD_CTL_PAD_SD3_CLK;                 /**< SW_PAD_CTL_PAD_SD3_CLK SW PAD Control Register, offset: 0x440 */
21914   __IO  uint32_t SW_PAD_CTL_PAD_SD3_CMD;                 /**< SW_PAD_CTL_PAD_SD3_CMD SW PAD Control Register, offset: 0x444 */
21915   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA0;               /**< SW_PAD_CTL_PAD_SD3_DATA0 SW PAD Control Register, offset: 0x448 */
21916   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA1;               /**< SW_PAD_CTL_PAD_SD3_DATA1 SW PAD Control Register, offset: 0x44C */
21917   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA2;               /**< SW_PAD_CTL_PAD_SD3_DATA2 SW PAD Control Register, offset: 0x450 */
21918   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA3;               /**< SW_PAD_CTL_PAD_SD3_DATA3 SW PAD Control Register, offset: 0x454 */
21919   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA4;               /**< SW_PAD_CTL_PAD_SD3_DATA4 SW PAD Control Register, offset: 0x458 */
21920   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA5;               /**< SW_PAD_CTL_PAD_SD3_DATA5 SW PAD Control Register, offset: 0x45C */
21921   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA6;               /**< SW_PAD_CTL_PAD_SD3_DATA6 SW PAD Control Register, offset: 0x460 */
21922   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA7;               /**< SW_PAD_CTL_PAD_SD3_DATA7 SW PAD Control Register, offset: 0x464 */
21923   __IO  uint32_t SW_PAD_CTL_PAD_SD3_STROBE;              /**< SW_PAD_CTL_PAD_SD3_STROBE SW PAD Control Register, offset: 0x468 */
21924   __IO  uint32_t SW_PAD_CTL_PAD_SD3_RESET_B;             /**< SW_PAD_CTL_PAD_SD3_RESET_B SW PAD Control Register, offset: 0x46C */
21925   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_RX_DATA;            /**< SW_PAD_CTL_PAD_SAI1_RX_DATA SW PAD Control Register, offset: 0x470 */
21926   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_TX_BCLK;            /**< SW_PAD_CTL_PAD_SAI1_TX_BCLK SW PAD Control Register, offset: 0x474 */
21927   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_TX_SYNC;            /**< SW_PAD_CTL_PAD_SAI1_TX_SYNC SW PAD Control Register, offset: 0x478 */
21928   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_TX_DATA;            /**< SW_PAD_CTL_PAD_SAI1_TX_DATA SW PAD Control Register, offset: 0x47C */
21929   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_RX_SYNC;            /**< SW_PAD_CTL_PAD_SAI1_RX_SYNC SW PAD Control Register, offset: 0x480 */
21930   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_RX_BCLK;            /**< SW_PAD_CTL_PAD_SAI1_RX_BCLK SW PAD Control Register, offset: 0x484 */
21931   __IO  uint32_t SW_PAD_CTL_PAD_SAI1_MCLK;               /**< SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control Register, offset: 0x488 */
21932   __IO  uint32_t SW_PAD_CTL_PAD_SAI2_TX_SYNC;            /**< SW_PAD_CTL_PAD_SAI2_TX_SYNC SW PAD Control Register, offset: 0x48C */
21933   __IO  uint32_t SW_PAD_CTL_PAD_SAI2_TX_BCLK;            /**< SW_PAD_CTL_PAD_SAI2_TX_BCLK SW PAD Control Register, offset: 0x490 */
21934   __IO  uint32_t SW_PAD_CTL_PAD_SAI2_RX_DATA;            /**< SW_PAD_CTL_PAD_SAI2_RX_DATA SW PAD Control Register, offset: 0x494 */
21935   __IO  uint32_t SW_PAD_CTL_PAD_SAI2_TX_DATA;            /**< SW_PAD_CTL_PAD_SAI2_TX_DATA SW PAD Control Register, offset: 0x498 */
21936   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD0;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD0 SW PAD Control Register, offset: 0x49C */
21937   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD1;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD1 SW PAD Control Register, offset: 0x4A0 */
21938   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD2;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD2 SW PAD Control Register, offset: 0x4A4 */
21939   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD3;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD3 SW PAD Control Register, offset: 0x4A8 */
21940   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL;      /**< SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL SW PAD Control Register, offset: 0x4AC */
21941   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RXC;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_RXC SW PAD Control Register, offset: 0x4B0 */
21942   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD0;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD0 SW PAD Control Register, offset: 0x4B4 */
21943   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD1;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD1 SW PAD Control Register, offset: 0x4B8 */
21944   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD2;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD2 SW PAD Control Register, offset: 0x4BC */
21945   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD3;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD3 SW PAD Control Register, offset: 0x4C0 */
21946   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL;      /**< SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL SW PAD Control Register, offset: 0x4C4 */
21947   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TXC;         /**< SW_PAD_CTL_PAD_ENET1_RGMII_TXC SW PAD Control Register, offset: 0x4C8 */
21948   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_TX_CLK;            /**< SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Control Register, offset: 0x4CC */
21949   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RX_CLK;            /**< SW_PAD_CTL_PAD_ENET1_RX_CLK SW PAD Control Register, offset: 0x4D0 */
21950   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_CRS;               /**< SW_PAD_CTL_PAD_ENET1_CRS SW PAD Control Register, offset: 0x4D4 */
21951   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_COL;               /**< SW_PAD_CTL_PAD_ENET1_COL SW PAD Control Register, offset: 0x4D8 */
21952   __IO  uint32_t FLEXCAN1_RX_SELECT_INPUT;               /**< FLEXCAN1_RX_SELECT_INPUT DAISY Register, offset: 0x4DC */
21953   __IO  uint32_t FLEXCAN2_RX_SELECT_INPUT;               /**< FLEXCAN2_RX_SELECT_INPUT DAISY Register, offset: 0x4E0 */
21954   __IO  uint32_t CCM_EXT_CLK_1_SELECT_INPUT;             /**< CCM_EXT_CLK_1_SELECT_INPUT DAISY Register, offset: 0x4E4 */
21955   __IO  uint32_t CCM_EXT_CLK_2_SELECT_INPUT;             /**< CCM_EXT_CLK_2_SELECT_INPUT DAISY Register, offset: 0x4E8 */
21956   __IO  uint32_t CCM_EXT_CLK_3_SELECT_INPUT;             /**< CCM_EXT_CLK_3_SELECT_INPUT DAISY Register, offset: 0x4EC */
21957   __IO  uint32_t CCM_EXT_CLK_4_SELECT_INPUT;             /**< CCM_EXT_CLK_4_SELECT_INPUT DAISY Register, offset: 0x4F0 */
21958   __IO  uint32_t CCM_PMIC_READY_SELECT_INPUT;            /**< CCM_PMIC_READY_SELECT_INPUT DAISY Register, offset: 0x4F4 */
21959   __IO  uint32_t CSI_DATA2_SELECT_INPUT;                 /**< CSI_DATA2_SELECT_INPUT DAISY Register, offset: 0x4F8 */
21960   __IO  uint32_t CSI_DATA3_SELECT_INPUT;                 /**< CSI_DATA3_SELECT_INPUT DAISY Register, offset: 0x4FC */
21961   __IO  uint32_t CSI_DATA4_SELECT_INPUT;                 /**< CSI_DATA4_SELECT_INPUT DAISY Register, offset: 0x500 */
21962   __IO  uint32_t CSI_DATA5_SELECT_INPUT;                 /**< CSI_DATA5_SELECT_INPUT DAISY Register, offset: 0x504 */
21963   __IO  uint32_t CSI_DATA6_SELECT_INPUT;                 /**< CSI_DATA6_SELECT_INPUT DAISY Register, offset: 0x508 */
21964   __IO  uint32_t CSI_DATA7_SELECT_INPUT;                 /**< CSI_DATA7_SELECT_INPUT DAISY Register, offset: 0x50C */
21965   __IO  uint32_t CSI_DATA8_SELECT_INPUT;                 /**< CSI_DATA8_SELECT_INPUT DAISY Register, offset: 0x510 */
21966   __IO  uint32_t CSI_DATA9_SELECT_INPUT;                 /**< CSI_DATA9_SELECT_INPUT DAISY Register, offset: 0x514 */
21967   __IO  uint32_t CSI_HSYNC_SELECT_INPUT;                 /**< CSI_HSYNC_SELECT_INPUT DAISY Register, offset: 0x518 */
21968   __IO  uint32_t CSI_PIXCLK_SELECT_INPUT;                /**< CSI_PIXCLK_SELECT_INPUT DAISY Register, offset: 0x51C */
21969   __IO  uint32_t CSI_VSYNC_SELECT_INPUT;                 /**< CSI_VSYNC_SELECT_INPUT DAISY Register, offset: 0x520 */
21970   __IO  uint32_t ECSPI1_SCLK_SELECT_INPUT;               /**< ECSPI1_SCLK_SELECT_INPUT DAISY Register, offset: 0x524 */
21971   __IO  uint32_t ECSPI1_MISO_SELECT_INPUT;               /**< ECSPI1_MISO_SELECT_INPUT DAISY Register, offset: 0x528 */
21972   __IO  uint32_t ECSPI1_MOSI_SELECT_INPUT;               /**< ECSPI1_MOSI_SELECT_INPUT DAISY Register, offset: 0x52C */
21973   __IO  uint32_t ECSPI1_SS0_B_SELECT_INPUT;              /**< ECSPI1_SS0_B_SELECT_INPUT DAISY Register, offset: 0x530 */
21974   __IO  uint32_t ECSPI2_SCLK_SELECT_INPUT;               /**< ECSPI2_SCLK_SELECT_INPUT DAISY Register, offset: 0x534 */
21975   __IO  uint32_t ECSPI2_MISO_SELECT_INPUT;               /**< ECSPI2_MISO_SELECT_INPUT DAISY Register, offset: 0x538 */
21976   __IO  uint32_t ECSPI2_MOSI_SELECT_INPUT;               /**< ECSPI2_MOSI_SELECT_INPUT DAISY Register, offset: 0x53C */
21977   __IO  uint32_t ECSPI2_SS0_B_SELECT_INPUT;              /**< ECSPI2_SS0_B_SELECT_INPUT DAISY Register, offset: 0x540 */
21978   __IO  uint32_t ECSPI3_SCLK_SELECT_INPUT;               /**< ECSPI3_SCLK_SELECT_INPUT DAISY Register, offset: 0x544 */
21979   __IO  uint32_t ECSPI3_MISO_SELECT_INPUT;               /**< ECSPI3_MISO_SELECT_INPUT DAISY Register, offset: 0x548 */
21980   __IO  uint32_t ECSPI3_MOSI_SELECT_INPUT;               /**< ECSPI3_MOSI_SELECT_INPUT DAISY Register, offset: 0x54C */
21981   __IO  uint32_t ECSPI3_SS0_B_SELECT_INPUT;              /**< ECSPI3_SS0_B_SELECT_INPUT DAISY Register, offset: 0x550 */
21982   __IO  uint32_t ECSPI4_SCLK_SELECT_INPUT;               /**< ECSPI4_SCLK_SELECT_INPUT DAISY Register, offset: 0x554 */
21983   __IO  uint32_t ECSPI4_MISO_SELECT_INPUT;               /**< ECSPI4_MISO_SELECT_INPUT DAISY Register, offset: 0x558 */
21984   __IO  uint32_t ECSPI4_MOSI_SELECT_INPUT;               /**< ECSPI4_MOSI_SELECT_INPUT DAISY Register, offset: 0x55C */
21985   __IO  uint32_t ECSPI4_SS0_B_SELECT_INPUT;              /**< ECSPI4_SS0_B_SELECT_INPUT DAISY Register, offset: 0x560 */
21986   __IO  uint32_t CCM_ENET1_REF_CLK_SELECT_INPUT;         /**< CCM_ENET1_REF_CLK_SELECT_INPUT DAISY Register, offset: 0x564 */
21987   __IO  uint32_t ENET1_MDIO_SELECT_INPUT;                /**< ENET1_MDIO_SELECT_INPUT DAISY Register, offset: 0x568 */
21988   __IO  uint32_t ENET1_RX_CLK_SELECT_INPUT;              /**< ENET1_RX_CLK_SELECT_INPUT DAISY Register, offset: 0x56C */
21989   __IO  uint32_t CCM_ENET2_REF_CLK_SELECT_INPUT;         /**< CCM_ENET2_REF_CLK_SELECT_INPUT DAISY Register, offset: 0x570 */
21990   __IO  uint32_t ENET2_MDIO_SELECT_INPUT;                /**< ENET2_MDIO_SELECT_INPUT DAISY Register, offset: 0x574 */
21991   __IO  uint32_t ENET2_RX_CLK_SELECT_INPUT;              /**< ENET2_RX_CLK_SELECT_INPUT DAISY Register, offset: 0x578 */
21992   __IO  uint32_t EPDC_PWR_IRQ_SELECT_INPUT;              /**< EPDC_PWR_IRQ_SELECT_INPUT DAISY Register, offset: 0x57C */
21993   __IO  uint32_t EPDC_PWR_STAT_SELECT_INPUT;             /**< EPDC_PWR_STAT_SELECT_INPUT DAISY Register, offset: 0x580 */
21994   __IO  uint32_t FLEXTIMER1_CH0_SELECT_INPUT;            /**< FLEXTIMER1_CH0_SELECT_INPUT DAISY Register, offset: 0x584 */
21995   __IO  uint32_t FLEXTIMER1_CH1_SELECT_INPUT;            /**< FLEXTIMER1_CH1_SELECT_INPUT DAISY Register, offset: 0x588 */
21996   __IO  uint32_t FLEXTIMER1_CH2_SELECT_INPUT;            /**< FLEXTIMER1_CH2_SELECT_INPUT DAISY Register, offset: 0x58C */
21997   __IO  uint32_t FLEXTIMER1_CH3_SELECT_INPUT;            /**< FLEXTIMER1_CH3_SELECT_INPUT DAISY Register, offset: 0x590 */
21998   __IO  uint32_t FLEXTIMER1_CH4_SELECT_INPUT;            /**< FLEXTIMER1_CH4_SELECT_INPUT DAISY Register, offset: 0x594 */
21999   __IO  uint32_t FLEXTIMER1_CH5_SELECT_INPUT;            /**< FLEXTIMER1_CH5_SELECT_INPUT DAISY Register, offset: 0x598 */
22000   __IO  uint32_t FLEXTIMER1_CH6_SELECT_INPUT;            /**< FLEXTIMER1_CH6_SELECT_INPUT DAISY Register, offset: 0x59C */
22001   __IO  uint32_t FLEXTIMER1_CH7_SELECT_INPUT;            /**< FLEXTIMER1_CH7_SELECT_INPUT DAISY Register, offset: 0x5A0 */
22002   __IO  uint32_t FLEXTIMER1_PHA_SELECT_INPUT;            /**< FLEXTIMER1_PHA_SELECT_INPUT DAISY Register, offset: 0x5A4 */
22003   __IO  uint32_t FLEXTIMER1_PHB_SELECT_INPUT;            /**< FLEXTIMER1_PHB_SELECT_INPUT DAISY Register, offset: 0x5A8 */
22004   __IO  uint32_t FLEXTIMER2_CH0_SELECT_INPUT;            /**< FLEXTIMER2_CH0_SELECT_INPUT DAISY Register, offset: 0x5AC */
22005   __IO  uint32_t FLEXTIMER2_CH1_SELECT_INPUT;            /**< FLEXTIMER2_CH1_SELECT_INPUT DAISY Register, offset: 0x5B0 */
22006   __IO  uint32_t FLEXTIMER2_CH2_SELECT_INPUT;            /**< FLEXTIMER2_CH2_SELECT_INPUT DAISY Register, offset: 0x5B4 */
22007   __IO  uint32_t FLEXTIMER2_CH3_SELECT_INPUT;            /**< FLEXTIMER2_CH3_SELECT_INPUT DAISY Register, offset: 0x5B8 */
22008   __IO  uint32_t FLEXTIMER2_CH4_SELECT_INPUT;            /**< FLEXTIMER2_CH4_SELECT_INPUT DAISY Register, offset: 0x5BC */
22009   __IO  uint32_t FLEXTIMER2_CH5_SELECT_INPUT;            /**< FLEXTIMER2_CH5_SELECT_INPUT DAISY Register, offset: 0x5C0 */
22010   __IO  uint32_t FLEXTIMER2_CH6_SELECT_INPUT;            /**< FLEXTIMER2_CH6_SELECT_INPUT DAISY Register, offset: 0x5C4 */
22011   __IO  uint32_t FLEXTIMER2_CH7_SELECT_INPUT;            /**< FLEXTIMER2_CH7_SELECT_INPUT DAISY Register, offset: 0x5C8 */
22012   __IO  uint32_t FLEXTIMER2_PHA_SELECT_INPUT;            /**< FLEXTIMER2_PHA_SELECT_INPUT DAISY Register, offset: 0x5CC */
22013   __IO  uint32_t FLEXTIMER2_PHB_SELECT_INPUT;            /**< FLEXTIMER2_PHB_SELECT_INPUT DAISY Register, offset: 0x5D0 */
22014   __IO  uint32_t I2C1_SCL_SELECT_INPUT;                  /**< I2C1_SCL_SELECT_INPUT DAISY Register, offset: 0x5D4 */
22015   __IO  uint32_t I2C1_SDA_SELECT_INPUT;                  /**< I2C1_SDA_SELECT_INPUT DAISY Register, offset: 0x5D8 */
22016   __IO  uint32_t I2C2_SCL_SELECT_INPUT;                  /**< I2C2_SCL_SELECT_INPUT DAISY Register, offset: 0x5DC */
22017   __IO  uint32_t I2C2_SDA_SELECT_INPUT;                  /**< I2C2_SDA_SELECT_INPUT DAISY Register, offset: 0x5E0 */
22018   __IO  uint32_t I2C3_SCL_SELECT_INPUT;                  /**< I2C3_SCL_SELECT_INPUT DAISY Register, offset: 0x5E4 */
22019   __IO  uint32_t I2C3_SDA_SELECT_INPUT;                  /**< I2C3_SDA_SELECT_INPUT DAISY Register, offset: 0x5E8 */
22020   __IO  uint32_t I2C4_SCL_SELECT_INPUT;                  /**< I2C4_SCL_SELECT_INPUT DAISY Register, offset: 0x5EC */
22021   __IO  uint32_t I2C4_SDA_SELECT_INPUT;                  /**< I2C4_SDA_SELECT_INPUT DAISY Register, offset: 0x5F0 */
22022   __IO  uint32_t KPP_COL0_SELECT_INPUT;                  /**< KPP_COL0_SELECT_INPUT DAISY Register, offset: 0x5F4 */
22023   __IO  uint32_t KPP_COL1_SELECT_INPUT;                  /**< KPP_COL1_SELECT_INPUT DAISY Register, offset: 0x5F8 */
22024   __IO  uint32_t KPP_COL2_SELECT_INPUT;                  /**< KPP_COL2_SELECT_INPUT DAISY Register, offset: 0x5FC */
22025   __IO  uint32_t KPP_COL3_SELECT_INPUT;                  /**< KPP_COL3_SELECT_INPUT DAISY Register, offset: 0x600 */
22026   __IO  uint32_t KPP_COL4_SELECT_INPUT;                  /**< KPP_COL4_SELECT_INPUT DAISY Register, offset: 0x604 */
22027   __IO  uint32_t KPP_COL5_SELECT_INPUT;                  /**< KPP_COL5_SELECT_INPUT DAISY Register, offset: 0x608 */
22028   __IO  uint32_t KPP_COL6_SELECT_INPUT;                  /**< KPP_COL6_SELECT_INPUT DAISY Register, offset: 0x60C */
22029   __IO  uint32_t KPP_COL7_SELECT_INPUT;                  /**< KPP_COL7_SELECT_INPUT DAISY Register, offset: 0x610 */
22030   __IO  uint32_t KPP_ROW0_SELECT_INPUT;                  /**< KPP_ROW0_SELECT_INPUT DAISY Register, offset: 0x614 */
22031   __IO  uint32_t KPP_ROW1_SELECT_INPUT;                  /**< KPP_ROW1_SELECT_INPUT DAISY Register, offset: 0x618 */
22032   __IO  uint32_t KPP_ROW2_SELECT_INPUT;                  /**< KPP_ROW2_SELECT_INPUT DAISY Register, offset: 0x61C */
22033   __IO  uint32_t KPP_ROW3_SELECT_INPUT;                  /**< KPP_ROW3_SELECT_INPUT DAISY Register, offset: 0x620 */
22034   __IO  uint32_t KPP_ROW4_SELECT_INPUT;                  /**< KPP_ROW4_SELECT_INPUT DAISY Register, offset: 0x624 */
22035   __IO  uint32_t KPP_ROW5_SELECT_INPUT;                  /**< KPP_ROW5_SELECT_INPUT DAISY Register, offset: 0x628 */
22036   __IO  uint32_t KPP_ROW6_SELECT_INPUT;                  /**< KPP_ROW6_SELECT_INPUT DAISY Register, offset: 0x62C */
22037   __IO  uint32_t KPP_ROW7_SELECT_INPUT;                  /**< KPP_ROW7_SELECT_INPUT DAISY Register, offset: 0x630 */
22038   __IO  uint32_t LCD_BUSY_SELECT_INPUT;                  /**< LCD_BUSY_SELECT_INPUT DAISY Register, offset: 0x634 */
22039   __IO  uint32_t LCD_DATA00_SELECT_INPUT;                /**< LCD_DATA00_SELECT_INPUT DAISY Register, offset: 0x638 */
22040   __IO  uint32_t LCD_DATA01_SELECT_INPUT;                /**< LCD_DATA01_SELECT_INPUT DAISY Register, offset: 0x63C */
22041   __IO  uint32_t LCD_DATA02_SELECT_INPUT;                /**< LCD_DATA02_SELECT_INPUT DAISY Register, offset: 0x640 */
22042   __IO  uint32_t LCD_DATA03_SELECT_INPUT;                /**< LCD_DATA03_SELECT_INPUT DAISY Register, offset: 0x644 */
22043   __IO  uint32_t LCD_DATA04_SELECT_INPUT;                /**< LCD_DATA04_SELECT_INPUT DAISY Register, offset: 0x648 */
22044   __IO  uint32_t LCD_DATA05_SELECT_INPUT;                /**< LCD_DATA05_SELECT_INPUT DAISY Register, offset: 0x64C */
22045   __IO  uint32_t LCD_DATA06_SELECT_INPUT;                /**< LCD_DATA06_SELECT_INPUT DAISY Register, offset: 0x650 */
22046   __IO  uint32_t LCD_DATA07_SELECT_INPUT;                /**< LCD_DATA07_SELECT_INPUT DAISY Register, offset: 0x654 */
22047   __IO  uint32_t LCD_DATA08_SELECT_INPUT;                /**< LCD_DATA08_SELECT_INPUT DAISY Register, offset: 0x658 */
22048   __IO  uint32_t LCD_DATA09_SELECT_INPUT;                /**< LCD_DATA09_SELECT_INPUT DAISY Register, offset: 0x65C */
22049   __IO  uint32_t LCD_DATA10_SELECT_INPUT;                /**< LCD_DATA10_SELECT_INPUT DAISY Register, offset: 0x660 */
22050   __IO  uint32_t LCD_DATA11_SELECT_INPUT;                /**< LCD_DATA11_SELECT_INPUT DAISY Register, offset: 0x664 */
22051   __IO  uint32_t LCD_DATA12_SELECT_INPUT;                /**< LCD_DATA12_SELECT_INPUT DAISY Register, offset: 0x668 */
22052   __IO  uint32_t LCD_DATA13_SELECT_INPUT;                /**< LCD_DATA13_SELECT_INPUT DAISY Register, offset: 0x66C */
22053   __IO  uint32_t LCD_DATA14_SELECT_INPUT;                /**< LCD_DATA14_SELECT_INPUT DAISY Register, offset: 0x670 */
22054   __IO  uint32_t LCD_DATA15_SELECT_INPUT;                /**< LCD_DATA15_SELECT_INPUT DAISY Register, offset: 0x674 */
22055   __IO  uint32_t LCD_DATA16_SELECT_INPUT;                /**< LCD_DATA16_SELECT_INPUT DAISY Register, offset: 0x678 */
22056   __IO  uint32_t LCD_DATA17_SELECT_INPUT;                /**< LCD_DATA17_SELECT_INPUT DAISY Register, offset: 0x67C */
22057   __IO  uint32_t LCD_DATA18_SELECT_INPUT;                /**< LCD_DATA18_SELECT_INPUT DAISY Register, offset: 0x680 */
22058   __IO  uint32_t LCD_DATA19_SELECT_INPUT;                /**< LCD_DATA19_SELECT_INPUT DAISY Register, offset: 0x684 */
22059   __IO  uint32_t LCD_DATA20_SELECT_INPUT;                /**< LCD_DATA20_SELECT_INPUT DAISY Register, offset: 0x688 */
22060   __IO  uint32_t LCD_DATA21_SELECT_INPUT;                /**< LCD_DATA21_SELECT_INPUT DAISY Register, offset: 0x68C */
22061   __IO  uint32_t LCD_DATA22_SELECT_INPUT;                /**< LCD_DATA22_SELECT_INPUT DAISY Register, offset: 0x690 */
22062   __IO  uint32_t LCD_DATA23_SELECT_INPUT;                /**< LCD_DATA23_SELECT_INPUT DAISY Register, offset: 0x694 */
22063   __IO  uint32_t LCD_VSYNC_SELECT_INPUT;                 /**< LCD_VSYNC_SELECT_INPUT DAISY Register, offset: 0x698 */
22064   __IO  uint32_t SAI1_RX_BCLK_SELECT_INPUT;              /**< SAI1_RX_BCLK_SELECT_INPUT DAISY Register, offset: 0x69C */
22065   __IO  uint32_t SAI1_RX_DATA_SELECT_INPUT;              /**< SAI1_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6A0 */
22066   __IO  uint32_t SAI1_RX_SYNC_SELECT_INPUT;              /**< SAI1_RX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6A4 */
22067   __IO  uint32_t SAI1_TX_BCLK_SELECT_INPUT;              /**< SAI1_TX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6A8 */
22068   __IO  uint32_t SAI1_TX_SYNC_SELECT_INPUT;              /**< SAI1_TX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6AC */
22069   __IO  uint32_t SAI2_RX_BCLK_SELECT_INPUT;              /**< SAI2_RX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6B0 */
22070   __IO  uint32_t SAI2_RX_DATA_SELECT_INPUT;              /**< SAI2_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6B4 */
22071   __IO  uint32_t SAI2_RX_SYNC_SELECT_INPUT;              /**< SAI2_RX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6B8 */
22072   __IO  uint32_t SAI2_TX_BCLK_SELECT_INPUT;              /**< SAI2_TX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6BC */
22073   __IO  uint32_t SAI2_TX_SYNC_SELECT_INPUT;              /**< SAI2_TX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6C0 */
22074   __IO  uint32_t SAI3_RX_BCLK_SELECT_INPUT;              /**< SAI3_RX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6C4 */
22075   __IO  uint32_t SAI3_RX_DATA_SELECT_INPUT;              /**< SAI3_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6C8 */
22076   __IO  uint32_t SAI3_RX_SYNC_SELECT_INPUT;              /**< SAI3_RX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6CC */
22077   __IO  uint32_t SAI3_TX_BCLK_SELECT_INPUT;              /**< SAI3_TX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6D0 */
22078   __IO  uint32_t SAI3_TX_SYNC_SELECT_INPUT;              /**< SAI3_TX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6D4 */
22079   __IO  uint32_t SDMA_EVENTS0_SELECT_INPUT;              /**< SDMA_EVENTS0_SELECT_INPUT DAISY Register, offset: 0x6D8 */
22080   __IO  uint32_t SDMA_EVENTS1_SELECT_INPUT;              /**< SDMA_EVENTS1_SELECT_INPUT DAISY Register, offset: 0x6DC */
22081   __IO  uint32_t SIM1_PORT1_PD_SELECT_INPUT;             /**< SIM1_PORT1_PD_SELECT_INPUT DAISY Register, offset: 0x6E0 */
22082   __IO  uint32_t SIM1_PORT1_TRXD_SELECT_INPUT;           /**< SIM1_PORT1_TRXD_SELECT_INPUT DAISY Register, offset: 0x6E4 */
22083   __IO  uint32_t SIM2_PORT1_PD_SELECT_INPUT;             /**< SIM2_PORT1_PD_SELECT_INPUT DAISY Register, offset: 0x6E8 */
22084   __IO  uint32_t SIM2_PORT1_TRXD_SELECT_INPUT;           /**< SIM2_PORT1_TRXD_SELECT_INPUT DAISY Register, offset: 0x6EC */
22085   __IO  uint32_t UART1_RTS_B_SELECT_INPUT;               /**< UART1_RTS_B_SELECT_INPUT DAISY Register, offset: 0x6F0 */
22086   __IO  uint32_t UART1_RX_DATA_SELECT_INPUT;             /**< UART1_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6F4 */
22087   __IO  uint32_t UART2_RTS_B_SELECT_INPUT;               /**< UART2_RTS_B_SELECT_INPUT DAISY Register, offset: 0x6F8 */
22088   __IO  uint32_t UART2_RX_DATA_SELECT_INPUT;             /**< UART2_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6FC */
22089   __IO  uint32_t UART3_RTS_B_SELECT_INPUT;               /**< UART3_RTS_B_SELECT_INPUT DAISY Register, offset: 0x700 */
22090   __IO  uint32_t UART3_RX_DATA_SELECT_INPUT;             /**< UART3_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x704 */
22091   __IO  uint32_t UART4_RTS_B_SELECT_INPUT;               /**< UART4_RTS_B_SELECT_INPUT DAISY Register, offset: 0x708 */
22092   __IO  uint32_t UART4_RX_DATA_SELECT_INPUT;             /**< UART4_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x70C */
22093   __IO  uint32_t UART5_RTS_B_SELECT_INPUT;               /**< UART5_RTS_B_SELECT_INPUT DAISY Register, offset: 0x710 */
22094   __IO  uint32_t UART5_RX_DATA_SELECT_INPUT;             /**< UART5_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x714 */
22095   __IO  uint32_t UART6_RTS_B_SELECT_INPUT;               /**< UART6_RTS_B_SELECT_INPUT DAISY Register, offset: 0x718 */
22096   __IO  uint32_t UART6_RX_DATA_SELECT_INPUT;             /**< UART6_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x71C */
22097   __IO  uint32_t UART7_RTS_B_SELECT_INPUT;               /**< UART7_RTS_B_SELECT_INPUT DAISY Register, offset: 0x720 */
22098   __IO  uint32_t UART7_RX_DATA_SELECT_INPUT;             /**< UART7_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x724 */
22099   __IO  uint32_t USB_OTG2_OC_SELECT_INPUT;               /**< USB_OTG2_OC_SELECT_INPUT DAISY Register, offset: 0x728 */
22100   __IO  uint32_t USB_OTG1_OC_SELECT_INPUT;               /**< USB_OTG1_OC_SELECT_INPUT DAISY Register, offset: 0x72C */
22101   __IO  uint32_t USB_OTG2_ID_SELECT_INPUT;               /**< USB_OTG2_ID_SELECT_INPUT DAISY Register, offset: 0x730 */
22102   __IO  uint32_t USB_OTG1_ID_SELECT_INPUT;               /**< USB_OTG1_ID_SELECT_INPUT DAISY Register, offset: 0x734 */
22103   __IO  uint32_t SD3_CD_B_SELECT_INPUT;                  /**< SD3_CD_B_SELECT_INPUT DAISY Register, offset: 0x738 */
22104   __IO  uint32_t SD3_WP_SELECT_INPUT;                    /**< SD3_WP_SELECT_INPUT DAISY Register, offset: 0x73C */
22105 } IOMUXC_Type, *IOMUXC_MemMapPtr;
22106 /* ----------------------------------------------------------------------------
22107    -- IOMUXC - Register accessor macros
22108    ---------------------------------------------------------------------------- */
22109 
22110 /*!
22111  * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros
22112  * @{
22113  */
22114 
22115 
22116 /* IOMUXC - Register accessors */
22117 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08)
22118 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09)
22119 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10)
22120 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11)
22121 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12)
22122 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13)
22123 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO14)
22124 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO15)
22125 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA00)
22126 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA01)
22127 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA02)
22128 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA03)
22129 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA04)
22130 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA05)
22131 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA06)
22132 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA07)
22133 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA08)
22134 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA09)
22135 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA10)
22136 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA11)
22137 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA12)
22138 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA13)
22139 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA14)
22140 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA15)
22141 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCLK)
22142 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDLE)
22143 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDOE)
22144 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDSHR)
22145 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE0)
22146 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE1)
22147 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE2)
22148 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE3)
22149 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDCLK)
22150 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDOE)
22151 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDRL)
22152 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDSP)
22153 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR0)
22154 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR1)
22155 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_COM)
22156 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_STAT)
22157 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_LCD_CLK)
22158 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_ENABLE)
22159 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_HSYNC)
22160 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_VSYNC)
22161 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_RESET)
22162 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA00)
22163 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA01)
22164 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA02)
22165 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA03)
22166 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA04)
22167 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA05)
22168 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA06)
22169 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA07)
22170 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA08)
22171 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA09)
22172 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA10)
22173 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA11)
22174 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA12)
22175 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA13)
22176 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA14)
22177 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA15)
22178 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA16)
22179 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA17)
22180 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA18)
22181 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA19)
22182 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA20)
22183 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA21)
22184 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA22)
22185 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA23)
22186 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_RX_DATA)
22187 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_TX_DATA)
22188 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_RX_DATA)
22189 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_TX_DATA)
22190 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RX_DATA)
22191 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_TX_DATA)
22192 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RTS_B)
22193 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_CTS_B)
22194 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SCL)
22195 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SDA)
22196 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SCL)
22197 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SDA)
22198 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SCL)
22199 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SDA)
22200 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SCL)
22201 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SDA)
22202 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SCLK)
22203 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MOSI)
22204 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MISO)
22205 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SS0)
22206 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SCLK)
22207 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MOSI)
22208 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MISO)
22209 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SS0)
22210 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CD_B)
22211 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(base)   ((base)->SW_MUX_CTL_PAD_SD1_WP)
22212 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_RESET_B)
22213 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD1_CLK)
22214 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD1_CMD)
22215 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0)
22216 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1)
22217 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2)
22218 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3)
22219 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CD_B)
22220 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(base)   ((base)->SW_MUX_CTL_PAD_SD2_WP)
22221 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_RESET_B)
22222 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD2_CLK)
22223 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD2_CMD)
22224 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0)
22225 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1)
22226 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2)
22227 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3)
22228 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD3_CLK)
22229 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD3_CMD)
22230 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0)
22231 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1)
22232 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2)
22233 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3)
22234 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4)
22235 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5)
22236 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6)
22237 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7)
22238 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_STROBE)
22239 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_RESET_B)
22240 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_DATA)
22241 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_BCLK)
22242 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_SYNC)
22243 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_DATA)
22244 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_SYNC)
22245 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_BCLK)
22246 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_MCLK)
22247 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_SYNC)
22248 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_BCLK)
22249 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_RX_DATA)
22250 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_DATA)
22251 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD0)
22252 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD1)
22253 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD2)
22254 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD3)
22255 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL)
22256 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RXC)
22257 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD0)
22258 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD1)
22259 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD2)
22260 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD3)
22261 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL)
22262 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TXC)
22263 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK)
22264 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK)
22265 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS)
22266 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL)
22267 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08)
22268 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09)
22269 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10)
22270 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11)
22271 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12)
22272 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13)
22273 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO14)
22274 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO15)
22275 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD)
22276 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK)
22277 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI)
22278 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO)
22279 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS)
22280 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B)
22281 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA00)
22282 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA01)
22283 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA02)
22284 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA03)
22285 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA04)
22286 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA05)
22287 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA06)
22288 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA07)
22289 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA08)
22290 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA09)
22291 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA10)
22292 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA11)
22293 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA12)
22294 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA13)
22295 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA14)
22296 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA15)
22297 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCLK)
22298 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDLE)
22299 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDOE)
22300 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDSHR)
22301 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE0)
22302 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE1)
22303 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE2)
22304 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE3)
22305 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDCLK)
22306 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDOE)
22307 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDRL)
22308 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDSP)
22309 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR0)
22310 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR1)
22311 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_COM)
22312 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_STAT)
22313 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_LCD_CLK)
22314 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_ENABLE)
22315 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_HSYNC)
22316 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_VSYNC)
22317 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_RESET)
22318 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA00)
22319 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA01)
22320 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA02)
22321 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA03)
22322 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA04)
22323 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA05)
22324 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA06)
22325 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA07)
22326 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA08)
22327 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA09)
22328 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA10)
22329 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA11)
22330 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA12)
22331 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA13)
22332 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA14)
22333 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA15)
22334 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA16)
22335 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA17)
22336 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA18)
22337 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA19)
22338 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA20)
22339 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA21)
22340 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA22)
22341 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA23)
22342 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_RX_DATA)
22343 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_TX_DATA)
22344 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_RX_DATA)
22345 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_TX_DATA)
22346 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RX_DATA)
22347 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_TX_DATA)
22348 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS_B)
22349 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS_B)
22350 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SCL)
22351 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SDA)
22352 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SCL)
22353 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SDA)
22354 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SCL)
22355 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SDA)
22356 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SCL)
22357 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SDA)
22358 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SCLK)
22359 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MOSI)
22360 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MISO)
22361 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SS0)
22362 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SCLK)
22363 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MOSI)
22364 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MISO)
22365 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SS0)
22366 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CD_B)
22367 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(base)   ((base)->SW_PAD_CTL_PAD_SD1_WP)
22368 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_RESET_B)
22369 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD1_CLK)
22370 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD1_CMD)
22371 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0)
22372 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1)
22373 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2)
22374 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3)
22375 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CD_B)
22376 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(base)   ((base)->SW_PAD_CTL_PAD_SD2_WP)
22377 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_RESET_B)
22378 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD2_CLK)
22379 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD2_CMD)
22380 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0)
22381 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1)
22382 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2)
22383 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3)
22384 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD3_CLK)
22385 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD3_CMD)
22386 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0)
22387 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1)
22388 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2)
22389 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3)
22390 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4)
22391 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5)
22392 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6)
22393 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7)
22394 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_STROBE)
22395 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_RESET_B)
22396 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_DATA)
22397 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_BCLK)
22398 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_SYNC)
22399 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_DATA)
22400 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_SYNC)
22401 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_BCLK)
22402 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_MCLK)
22403 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_SYNC)
22404 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_BCLK)
22405 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_RX_DATA)
22406 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_DATA)
22407 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD0)
22408 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD1)
22409 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD2)
22410 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD3)
22411 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL)
22412 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RXC)
22413 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD0)
22414 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD1)
22415 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD2)
22416 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD3)
22417 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL)
22418 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TXC)
22419 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK)
22420 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK)
22421 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS)
22422 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL)
22423 #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN1_RX_SELECT_INPUT)
22424 #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN2_RX_SELECT_INPUT)
22425 #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_1_SELECT_INPUT)
22426 #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_2_SELECT_INPUT)
22427 #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_3_SELECT_INPUT)
22428 #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_4_SELECT_INPUT)
22429 #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_READY_SELECT_INPUT)
22430 #define IOMUXC_CSI_DATA2_SELECT_INPUT_REG(base)  ((base)->CSI_DATA2_SELECT_INPUT)
22431 #define IOMUXC_CSI_DATA3_SELECT_INPUT_REG(base)  ((base)->CSI_DATA3_SELECT_INPUT)
22432 #define IOMUXC_CSI_DATA4_SELECT_INPUT_REG(base)  ((base)->CSI_DATA4_SELECT_INPUT)
22433 #define IOMUXC_CSI_DATA5_SELECT_INPUT_REG(base)  ((base)->CSI_DATA5_SELECT_INPUT)
22434 #define IOMUXC_CSI_DATA6_SELECT_INPUT_REG(base)  ((base)->CSI_DATA6_SELECT_INPUT)
22435 #define IOMUXC_CSI_DATA7_SELECT_INPUT_REG(base)  ((base)->CSI_DATA7_SELECT_INPUT)
22436 #define IOMUXC_CSI_DATA8_SELECT_INPUT_REG(base)  ((base)->CSI_DATA8_SELECT_INPUT)
22437 #define IOMUXC_CSI_DATA9_SELECT_INPUT_REG(base)  ((base)->CSI_DATA9_SELECT_INPUT)
22438 #define IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(base)  ((base)->CSI_HSYNC_SELECT_INPUT)
22439 #define IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI_PIXCLK_SELECT_INPUT)
22440 #define IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(base)  ((base)->CSI_VSYNC_SELECT_INPUT)
22441 #define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI1_SCLK_SELECT_INPUT)
22442 #define IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_MISO_SELECT_INPUT)
22443 #define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_MOSI_SELECT_INPUT)
22444 #define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI1_SS0_B_SELECT_INPUT)
22445 #define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI2_SCLK_SELECT_INPUT)
22446 #define IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_MISO_SELECT_INPUT)
22447 #define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_MOSI_SELECT_INPUT)
22448 #define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI2_SS0_B_SELECT_INPUT)
22449 #define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI3_SCLK_SELECT_INPUT)
22450 #define IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_MISO_SELECT_INPUT)
22451 #define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_MOSI_SELECT_INPUT)
22452 #define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI3_SS0_B_SELECT_INPUT)
22453 #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI4_SCLK_SELECT_INPUT)
22454 #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_MISO_SELECT_INPUT)
22455 #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_MOSI_SELECT_INPUT)
22456 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI4_SS0_B_SELECT_INPUT)
22457 #define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET1_REF_CLK_SELECT_INPUT)
22458 #define IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_MDIO_SELECT_INPUT)
22459 #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET1_RX_CLK_SELECT_INPUT)
22460 #define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET2_REF_CLK_SELECT_INPUT)
22461 #define IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_MDIO_SELECT_INPUT)
22462 #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET2_RX_CLK_SELECT_INPUT)
22463 #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_IRQ_SELECT_INPUT)
22464 #define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_STAT_SELECT_INPUT)
22465 #define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH0_SELECT_INPUT)
22466 #define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH1_SELECT_INPUT)
22467 #define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH2_SELECT_INPUT)
22468 #define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH3_SELECT_INPUT)
22469 #define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH4_SELECT_INPUT)
22470 #define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH5_SELECT_INPUT)
22471 #define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH6_SELECT_INPUT)
22472 #define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH7_SELECT_INPUT)
22473 #define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHA_SELECT_INPUT)
22474 #define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHB_SELECT_INPUT)
22475 #define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH0_SELECT_INPUT)
22476 #define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH1_SELECT_INPUT)
22477 #define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH2_SELECT_INPUT)
22478 #define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH3_SELECT_INPUT)
22479 #define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH4_SELECT_INPUT)
22480 #define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH5_SELECT_INPUT)
22481 #define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH6_SELECT_INPUT)
22482 #define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH7_SELECT_INPUT)
22483 #define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHA_SELECT_INPUT)
22484 #define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHB_SELECT_INPUT)
22485 #define IOMUXC_I2C1_SCL_SELECT_INPUT_REG(base)   ((base)->I2C1_SCL_SELECT_INPUT)
22486 #define IOMUXC_I2C1_SDA_SELECT_INPUT_REG(base)   ((base)->I2C1_SDA_SELECT_INPUT)
22487 #define IOMUXC_I2C2_SCL_SELECT_INPUT_REG(base)   ((base)->I2C2_SCL_SELECT_INPUT)
22488 #define IOMUXC_I2C2_SDA_SELECT_INPUT_REG(base)   ((base)->I2C2_SDA_SELECT_INPUT)
22489 #define IOMUXC_I2C3_SCL_SELECT_INPUT_REG(base)   ((base)->I2C3_SCL_SELECT_INPUT)
22490 #define IOMUXC_I2C3_SDA_SELECT_INPUT_REG(base)   ((base)->I2C3_SDA_SELECT_INPUT)
22491 #define IOMUXC_I2C4_SCL_SELECT_INPUT_REG(base)   ((base)->I2C4_SCL_SELECT_INPUT)
22492 #define IOMUXC_I2C4_SDA_SELECT_INPUT_REG(base)   ((base)->I2C4_SDA_SELECT_INPUT)
22493 #define IOMUXC_KPP_COL0_SELECT_INPUT_REG(base)   ((base)->KPP_COL0_SELECT_INPUT)
22494 #define IOMUXC_KPP_COL1_SELECT_INPUT_REG(base)   ((base)->KPP_COL1_SELECT_INPUT)
22495 #define IOMUXC_KPP_COL2_SELECT_INPUT_REG(base)   ((base)->KPP_COL2_SELECT_INPUT)
22496 #define IOMUXC_KPP_COL3_SELECT_INPUT_REG(base)   ((base)->KPP_COL3_SELECT_INPUT)
22497 #define IOMUXC_KPP_COL4_SELECT_INPUT_REG(base)   ((base)->KPP_COL4_SELECT_INPUT)
22498 #define IOMUXC_KPP_COL5_SELECT_INPUT_REG(base)   ((base)->KPP_COL5_SELECT_INPUT)
22499 #define IOMUXC_KPP_COL6_SELECT_INPUT_REG(base)   ((base)->KPP_COL6_SELECT_INPUT)
22500 #define IOMUXC_KPP_COL7_SELECT_INPUT_REG(base)   ((base)->KPP_COL7_SELECT_INPUT)
22501 #define IOMUXC_KPP_ROW0_SELECT_INPUT_REG(base)   ((base)->KPP_ROW0_SELECT_INPUT)
22502 #define IOMUXC_KPP_ROW1_SELECT_INPUT_REG(base)   ((base)->KPP_ROW1_SELECT_INPUT)
22503 #define IOMUXC_KPP_ROW2_SELECT_INPUT_REG(base)   ((base)->KPP_ROW2_SELECT_INPUT)
22504 #define IOMUXC_KPP_ROW3_SELECT_INPUT_REG(base)   ((base)->KPP_ROW3_SELECT_INPUT)
22505 #define IOMUXC_KPP_ROW4_SELECT_INPUT_REG(base)   ((base)->KPP_ROW4_SELECT_INPUT)
22506 #define IOMUXC_KPP_ROW5_SELECT_INPUT_REG(base)   ((base)->KPP_ROW5_SELECT_INPUT)
22507 #define IOMUXC_KPP_ROW6_SELECT_INPUT_REG(base)   ((base)->KPP_ROW6_SELECT_INPUT)
22508 #define IOMUXC_KPP_ROW7_SELECT_INPUT_REG(base)   ((base)->KPP_ROW7_SELECT_INPUT)
22509 #define IOMUXC_LCD_BUSY_SELECT_INPUT_REG(base)   ((base)->LCD_BUSY_SELECT_INPUT)
22510 #define IOMUXC_LCD_DATA00_SELECT_INPUT_REG(base) ((base)->LCD_DATA00_SELECT_INPUT)
22511 #define IOMUXC_LCD_DATA01_SELECT_INPUT_REG(base) ((base)->LCD_DATA01_SELECT_INPUT)
22512 #define IOMUXC_LCD_DATA02_SELECT_INPUT_REG(base) ((base)->LCD_DATA02_SELECT_INPUT)
22513 #define IOMUXC_LCD_DATA03_SELECT_INPUT_REG(base) ((base)->LCD_DATA03_SELECT_INPUT)
22514 #define IOMUXC_LCD_DATA04_SELECT_INPUT_REG(base) ((base)->LCD_DATA04_SELECT_INPUT)
22515 #define IOMUXC_LCD_DATA05_SELECT_INPUT_REG(base) ((base)->LCD_DATA05_SELECT_INPUT)
22516 #define IOMUXC_LCD_DATA06_SELECT_INPUT_REG(base) ((base)->LCD_DATA06_SELECT_INPUT)
22517 #define IOMUXC_LCD_DATA07_SELECT_INPUT_REG(base) ((base)->LCD_DATA07_SELECT_INPUT)
22518 #define IOMUXC_LCD_DATA08_SELECT_INPUT_REG(base) ((base)->LCD_DATA08_SELECT_INPUT)
22519 #define IOMUXC_LCD_DATA09_SELECT_INPUT_REG(base) ((base)->LCD_DATA09_SELECT_INPUT)
22520 #define IOMUXC_LCD_DATA10_SELECT_INPUT_REG(base) ((base)->LCD_DATA10_SELECT_INPUT)
22521 #define IOMUXC_LCD_DATA11_SELECT_INPUT_REG(base) ((base)->LCD_DATA11_SELECT_INPUT)
22522 #define IOMUXC_LCD_DATA12_SELECT_INPUT_REG(base) ((base)->LCD_DATA12_SELECT_INPUT)
22523 #define IOMUXC_LCD_DATA13_SELECT_INPUT_REG(base) ((base)->LCD_DATA13_SELECT_INPUT)
22524 #define IOMUXC_LCD_DATA14_SELECT_INPUT_REG(base) ((base)->LCD_DATA14_SELECT_INPUT)
22525 #define IOMUXC_LCD_DATA15_SELECT_INPUT_REG(base) ((base)->LCD_DATA15_SELECT_INPUT)
22526 #define IOMUXC_LCD_DATA16_SELECT_INPUT_REG(base) ((base)->LCD_DATA16_SELECT_INPUT)
22527 #define IOMUXC_LCD_DATA17_SELECT_INPUT_REG(base) ((base)->LCD_DATA17_SELECT_INPUT)
22528 #define IOMUXC_LCD_DATA18_SELECT_INPUT_REG(base) ((base)->LCD_DATA18_SELECT_INPUT)
22529 #define IOMUXC_LCD_DATA19_SELECT_INPUT_REG(base) ((base)->LCD_DATA19_SELECT_INPUT)
22530 #define IOMUXC_LCD_DATA20_SELECT_INPUT_REG(base) ((base)->LCD_DATA20_SELECT_INPUT)
22531 #define IOMUXC_LCD_DATA21_SELECT_INPUT_REG(base) ((base)->LCD_DATA21_SELECT_INPUT)
22532 #define IOMUXC_LCD_DATA22_SELECT_INPUT_REG(base) ((base)->LCD_DATA22_SELECT_INPUT)
22533 #define IOMUXC_LCD_DATA23_SELECT_INPUT_REG(base) ((base)->LCD_DATA23_SELECT_INPUT)
22534 #define IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(base)  ((base)->LCD_VSYNC_SELECT_INPUT)
22535 #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_RX_BCLK_SELECT_INPUT)
22536 #define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI1_RX_DATA_SELECT_INPUT)
22537 #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_RX_SYNC_SELECT_INPUT)
22538 #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_TX_BCLK_SELECT_INPUT)
22539 #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_TX_SYNC_SELECT_INPUT)
22540 #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_RX_BCLK_SELECT_INPUT)
22541 #define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI2_RX_DATA_SELECT_INPUT)
22542 #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_RX_SYNC_SELECT_INPUT)
22543 #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_TX_BCLK_SELECT_INPUT)
22544 #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_TX_SYNC_SELECT_INPUT)
22545 #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_RX_BCLK_SELECT_INPUT)
22546 #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI3_RX_DATA_SELECT_INPUT)
22547 #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_RX_SYNC_SELECT_INPUT)
22548 #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_TX_BCLK_SELECT_INPUT)
22549 #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_TX_SYNC_SELECT_INPUT)
22550 #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS0_SELECT_INPUT)
22551 #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS1_SELECT_INPUT)
22552 #define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_PD_SELECT_INPUT)
22553 #define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_TRXD_SELECT_INPUT)
22554 #define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_PD_SELECT_INPUT)
22555 #define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_TRXD_SELECT_INPUT)
22556 #define IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_RTS_B_SELECT_INPUT)
22557 #define IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART1_RX_DATA_SELECT_INPUT)
22558 #define IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_RTS_B_SELECT_INPUT)
22559 #define IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART2_RX_DATA_SELECT_INPUT)
22560 #define IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_RTS_B_SELECT_INPUT)
22561 #define IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART3_RX_DATA_SELECT_INPUT)
22562 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_RTS_B_SELECT_INPUT)
22563 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART4_RX_DATA_SELECT_INPUT)
22564 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_RTS_B_SELECT_INPUT)
22565 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART5_RX_DATA_SELECT_INPUT)
22566 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_RTS_B_SELECT_INPUT)
22567 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART6_RX_DATA_SELECT_INPUT)
22568 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(base) ((base)->UART7_RTS_B_SELECT_INPUT)
22569 #define IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART7_RX_DATA_SELECT_INPUT)
22570 #define IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG2_OC_SELECT_INPUT)
22571 #define IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG1_OC_SELECT_INPUT)
22572 #define IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG2_ID_SELECT_INPUT)
22573 #define IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG1_ID_SELECT_INPUT)
22574 #define IOMUXC_SD3_CD_B_SELECT_INPUT_REG(base)   ((base)->SD3_CD_B_SELECT_INPUT)
22575 #define IOMUXC_SD3_WP_SELECT_INPUT_REG(base)     ((base)->SD3_WP_SELECT_INPUT)
22576 
22577 /*!
22578  * @}
22579  */ /* end of group IOMUXC_Register_Accessor_Macros */
22580 /* ----------------------------------------------------------------------------
22581    -- IOMUXC Register Masks
22582    ---------------------------------------------------------------------------- */
22583 
22584 /*!
22585  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
22586  * @{
22587  */
22588 
22589 /* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */
22590 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u
22591 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0
22592 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK)
22593 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_MASK 0x10u
22594 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_SHIFT 4
22595 /* SW_MUX_CTL_PAD_GPIO1_IO09 Bit Fields */
22596 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK 0x7u
22597 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT 0
22598 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK)
22599 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_MASK 0x10u
22600 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_SHIFT 4
22601 /* SW_MUX_CTL_PAD_GPIO1_IO10 Bit Fields */
22602 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK 0x7u
22603 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT 0
22604 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK)
22605 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_MASK 0x10u
22606 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_SHIFT 4
22607 /* SW_MUX_CTL_PAD_GPIO1_IO11 Bit Fields */
22608 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK 0x7u
22609 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT 0
22610 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK)
22611 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_MASK 0x10u
22612 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_SHIFT 4
22613 /* SW_MUX_CTL_PAD_GPIO1_IO12 Bit Fields */
22614 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK 0x7u
22615 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT 0
22616 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK)
22617 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_MASK 0x10u
22618 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_SHIFT 4
22619 /* SW_MUX_CTL_PAD_GPIO1_IO13 Bit Fields */
22620 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK 0x7u
22621 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT 0
22622 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK)
22623 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_MASK 0x10u
22624 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_SHIFT 4
22625 /* SW_MUX_CTL_PAD_GPIO1_IO14 Bit Fields */
22626 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_MASK 0x7u
22627 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_SHIFT 0
22628 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_MASK)
22629 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_SION_MASK 0x10u
22630 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_SION_SHIFT 4
22631 /* SW_MUX_CTL_PAD_GPIO1_IO15 Bit Fields */
22632 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_MASK 0x7u
22633 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_SHIFT 0
22634 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_MASK)
22635 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_SION_MASK 0x10u
22636 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_SION_SHIFT 4
22637 /* SW_MUX_CTL_PAD_EPDC_DATA00 Bit Fields */
22638 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_MASK 0x7u
22639 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_SHIFT 0
22640 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_MASK)
22641 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_SION_MASK 0x10u
22642 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_SION_SHIFT 4
22643 /* SW_MUX_CTL_PAD_EPDC_DATA01 Bit Fields */
22644 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_MASK 0x7u
22645 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_SHIFT 0
22646 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_MASK)
22647 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_SION_MASK 0x10u
22648 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_SION_SHIFT 4
22649 /* SW_MUX_CTL_PAD_EPDC_DATA02 Bit Fields */
22650 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_MASK 0x7u
22651 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_SHIFT 0
22652 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_MASK)
22653 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_SION_MASK 0x10u
22654 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_SION_SHIFT 4
22655 /* SW_MUX_CTL_PAD_EPDC_DATA03 Bit Fields */
22656 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_MASK 0x7u
22657 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_SHIFT 0
22658 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_MASK)
22659 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_SION_MASK 0x10u
22660 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_SION_SHIFT 4
22661 /* SW_MUX_CTL_PAD_EPDC_DATA04 Bit Fields */
22662 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_MASK 0x7u
22663 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_SHIFT 0
22664 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_MASK)
22665 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_SION_MASK 0x10u
22666 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_SION_SHIFT 4
22667 /* SW_MUX_CTL_PAD_EPDC_DATA05 Bit Fields */
22668 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_MASK 0x7u
22669 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_SHIFT 0
22670 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_MASK)
22671 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_SION_MASK 0x10u
22672 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_SION_SHIFT 4
22673 /* SW_MUX_CTL_PAD_EPDC_DATA06 Bit Fields */
22674 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_MASK 0x7u
22675 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_SHIFT 0
22676 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_MASK)
22677 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_SION_MASK 0x10u
22678 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_SION_SHIFT 4
22679 /* SW_MUX_CTL_PAD_EPDC_DATA07 Bit Fields */
22680 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_MASK 0x7u
22681 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_SHIFT 0
22682 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_MASK)
22683 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_SION_MASK 0x10u
22684 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_SION_SHIFT 4
22685 /* SW_MUX_CTL_PAD_EPDC_DATA08 Bit Fields */
22686 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_MASK 0xFu
22687 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_SHIFT 0
22688 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_MASK)
22689 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_SION_MASK 0x10u
22690 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_SION_SHIFT 4
22691 /* SW_MUX_CTL_PAD_EPDC_DATA09 Bit Fields */
22692 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_MASK 0xFu
22693 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_SHIFT 0
22694 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_MASK)
22695 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_SION_MASK 0x10u
22696 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_SION_SHIFT 4
22697 /* SW_MUX_CTL_PAD_EPDC_DATA10 Bit Fields */
22698 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_MASK 0xFu
22699 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_SHIFT 0
22700 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_MASK)
22701 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_SION_MASK 0x10u
22702 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_SION_SHIFT 4
22703 /* SW_MUX_CTL_PAD_EPDC_DATA11 Bit Fields */
22704 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_MASK 0xFu
22705 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_SHIFT 0
22706 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_MASK)
22707 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_SION_MASK 0x10u
22708 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_SION_SHIFT 4
22709 /* SW_MUX_CTL_PAD_EPDC_DATA12 Bit Fields */
22710 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_MASK 0xFu
22711 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_SHIFT 0
22712 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_MASK)
22713 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_SION_MASK 0x10u
22714 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_SION_SHIFT 4
22715 /* SW_MUX_CTL_PAD_EPDC_DATA13 Bit Fields */
22716 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_MASK 0xFu
22717 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_SHIFT 0
22718 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_MASK)
22719 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_SION_MASK 0x10u
22720 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_SION_SHIFT 4
22721 /* SW_MUX_CTL_PAD_EPDC_DATA14 Bit Fields */
22722 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_MASK 0xFu
22723 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_SHIFT 0
22724 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_MASK)
22725 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_SION_MASK 0x10u
22726 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_SION_SHIFT 4
22727 /* SW_MUX_CTL_PAD_EPDC_DATA15 Bit Fields */
22728 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_MASK 0xFu
22729 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_SHIFT 0
22730 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_MASK)
22731 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_SION_MASK 0x10u
22732 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_SION_SHIFT 4
22733 /* SW_MUX_CTL_PAD_EPDC_SDCLK Bit Fields */
22734 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_MASK 0x7u
22735 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_SHIFT 0
22736 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_MASK)
22737 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_SION_MASK 0x10u
22738 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_SION_SHIFT 4
22739 /* SW_MUX_CTL_PAD_EPDC_SDLE Bit Fields */
22740 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_MASK 0x7u
22741 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_SHIFT 0
22742 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_MASK)
22743 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_SION_MASK 0x10u
22744 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_SION_SHIFT 4
22745 /* SW_MUX_CTL_PAD_EPDC_SDOE Bit Fields */
22746 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_MASK 0x7u
22747 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_SHIFT 0
22748 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_MASK)
22749 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_SION_MASK 0x10u
22750 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_SION_SHIFT 4
22751 /* SW_MUX_CTL_PAD_EPDC_SDSHR Bit Fields */
22752 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_MASK 0x7u
22753 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_SHIFT 0
22754 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_MASK)
22755 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_SION_MASK 0x10u
22756 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_SION_SHIFT 4
22757 /* SW_MUX_CTL_PAD_EPDC_SDCE0 Bit Fields */
22758 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_MASK 0x7u
22759 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_SHIFT 0
22760 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_MASK)
22761 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_SION_MASK 0x10u
22762 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_SION_SHIFT 4
22763 /* SW_MUX_CTL_PAD_EPDC_SDCE1 Bit Fields */
22764 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_MASK 0x7u
22765 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_SHIFT 0
22766 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_MASK)
22767 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_SION_MASK 0x10u
22768 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_SION_SHIFT 4
22769 /* SW_MUX_CTL_PAD_EPDC_SDCE2 Bit Fields */
22770 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_MASK 0x7u
22771 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_SHIFT 0
22772 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_MASK)
22773 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_SION_MASK 0x10u
22774 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_SION_SHIFT 4
22775 /* SW_MUX_CTL_PAD_EPDC_SDCE3 Bit Fields */
22776 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_MASK 0x7u
22777 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_SHIFT 0
22778 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_MASK)
22779 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_SION_MASK 0x10u
22780 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_SION_SHIFT 4
22781 /* SW_MUX_CTL_PAD_EPDC_GDCLK Bit Fields */
22782 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_MASK 0x7u
22783 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_SHIFT 0
22784 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_MASK)
22785 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_SION_MASK 0x10u
22786 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_SION_SHIFT 4
22787 /* SW_MUX_CTL_PAD_EPDC_GDOE Bit Fields */
22788 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_MASK 0x7u
22789 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_SHIFT 0
22790 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_MASK)
22791 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_SION_MASK 0x10u
22792 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_SION_SHIFT 4
22793 /* SW_MUX_CTL_PAD_EPDC_GDRL Bit Fields */
22794 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_MASK 0x7u
22795 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_SHIFT 0
22796 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_MASK)
22797 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_SION_MASK 0x10u
22798 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_SION_SHIFT 4
22799 /* SW_MUX_CTL_PAD_EPDC_GDSP Bit Fields */
22800 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_MASK 0x7u
22801 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_SHIFT 0
22802 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_MASK)
22803 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_SION_MASK 0x10u
22804 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_SION_SHIFT 4
22805 /* SW_MUX_CTL_PAD_EPDC_BDR0 Bit Fields */
22806 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_MASK 0x7u
22807 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_SHIFT 0
22808 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_MASK)
22809 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_SION_MASK 0x10u
22810 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_SION_SHIFT 4
22811 /* SW_MUX_CTL_PAD_EPDC_BDR1 Bit Fields */
22812 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_MASK 0x7u
22813 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_SHIFT 0
22814 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_MASK)
22815 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_SION_MASK 0x10u
22816 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_SION_SHIFT 4
22817 /* SW_MUX_CTL_PAD_EPDC_PWR_COM Bit Fields */
22818 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_MASK 0x7u
22819 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_SHIFT 0
22820 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_MASK)
22821 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_SION_MASK 0x10u
22822 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_SION_SHIFT 4
22823 /* SW_MUX_CTL_PAD_EPDC_PWR_STAT Bit Fields */
22824 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_MASK 0x7u
22825 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_SHIFT 0
22826 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_MASK)
22827 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_SION_MASK 0x10u
22828 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_SION_SHIFT 4
22829 /* SW_MUX_CTL_PAD_LCD_CLK Bit Fields */
22830 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_MASK 0x7u
22831 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_SHIFT 0
22832 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_MASK)
22833 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_SION_MASK  0x10u
22834 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_SION_SHIFT 4
22835 /* SW_MUX_CTL_PAD_LCD_ENABLE Bit Fields */
22836 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_MASK 0x7u
22837 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_SHIFT 0
22838 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_MASK)
22839 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_SION_MASK 0x10u
22840 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_SION_SHIFT 4
22841 /* SW_MUX_CTL_PAD_LCD_HSYNC Bit Fields */
22842 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_MASK 0x7u
22843 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_SHIFT 0
22844 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_MASK)
22845 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_SION_MASK 0x10u
22846 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_SION_SHIFT 4
22847 /* SW_MUX_CTL_PAD_LCD_VSYNC Bit Fields */
22848 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_MASK 0x7u
22849 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_SHIFT 0
22850 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_MASK)
22851 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_SION_MASK 0x10u
22852 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_SION_SHIFT 4
22853 /* SW_MUX_CTL_PAD_LCD_RESET Bit Fields */
22854 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_MASK 0x7u
22855 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_SHIFT 0
22856 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_MASK)
22857 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_SION_MASK 0x10u
22858 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_SION_SHIFT 4
22859 /* SW_MUX_CTL_PAD_LCD_DATA00 Bit Fields */
22860 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_MASK 0x7u
22861 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_SHIFT 0
22862 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_MASK)
22863 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_SION_MASK 0x10u
22864 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_SION_SHIFT 4
22865 /* SW_MUX_CTL_PAD_LCD_DATA01 Bit Fields */
22866 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_MASK 0x7u
22867 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_SHIFT 0
22868 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_MASK)
22869 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_SION_MASK 0x10u
22870 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_SION_SHIFT 4
22871 /* SW_MUX_CTL_PAD_LCD_DATA02 Bit Fields */
22872 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_MASK 0x7u
22873 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_SHIFT 0
22874 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_MASK)
22875 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_SION_MASK 0x10u
22876 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_SION_SHIFT 4
22877 /* SW_MUX_CTL_PAD_LCD_DATA03 Bit Fields */
22878 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_MASK 0x7u
22879 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_SHIFT 0
22880 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_MASK)
22881 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_SION_MASK 0x10u
22882 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_SION_SHIFT 4
22883 /* SW_MUX_CTL_PAD_LCD_DATA04 Bit Fields */
22884 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_MASK 0x7u
22885 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_SHIFT 0
22886 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_MASK)
22887 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_SION_MASK 0x10u
22888 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_SION_SHIFT 4
22889 /* SW_MUX_CTL_PAD_LCD_DATA05 Bit Fields */
22890 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_MASK 0x7u
22891 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_SHIFT 0
22892 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_MASK)
22893 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_SION_MASK 0x10u
22894 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_SION_SHIFT 4
22895 /* SW_MUX_CTL_PAD_LCD_DATA06 Bit Fields */
22896 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_MASK 0x7u
22897 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_SHIFT 0
22898 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_MASK)
22899 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_SION_MASK 0x10u
22900 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_SION_SHIFT 4
22901 /* SW_MUX_CTL_PAD_LCD_DATA07 Bit Fields */
22902 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_MASK 0x7u
22903 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_SHIFT 0
22904 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_MASK)
22905 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_SION_MASK 0x10u
22906 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_SION_SHIFT 4
22907 /* SW_MUX_CTL_PAD_LCD_DATA08 Bit Fields */
22908 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_MASK 0x7u
22909 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_SHIFT 0
22910 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_MASK)
22911 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_SION_MASK 0x10u
22912 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_SION_SHIFT 4
22913 /* SW_MUX_CTL_PAD_LCD_DATA09 Bit Fields */
22914 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_MASK 0x7u
22915 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_SHIFT 0
22916 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_MASK)
22917 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_SION_MASK 0x10u
22918 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_SION_SHIFT 4
22919 /* SW_MUX_CTL_PAD_LCD_DATA10 Bit Fields */
22920 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_MASK 0x7u
22921 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_SHIFT 0
22922 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_MASK)
22923 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_SION_MASK 0x10u
22924 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_SION_SHIFT 4
22925 /* SW_MUX_CTL_PAD_LCD_DATA11 Bit Fields */
22926 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_MASK 0x7u
22927 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_SHIFT 0
22928 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_MASK)
22929 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_SION_MASK 0x10u
22930 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_SION_SHIFT 4
22931 /* SW_MUX_CTL_PAD_LCD_DATA12 Bit Fields */
22932 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_MASK 0x7u
22933 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_SHIFT 0
22934 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_MASK)
22935 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_SION_MASK 0x10u
22936 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_SION_SHIFT 4
22937 /* SW_MUX_CTL_PAD_LCD_DATA13 Bit Fields */
22938 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_MASK 0x7u
22939 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_SHIFT 0
22940 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_MASK)
22941 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_SION_MASK 0x10u
22942 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_SION_SHIFT 4
22943 /* SW_MUX_CTL_PAD_LCD_DATA14 Bit Fields */
22944 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_MASK 0x7u
22945 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_SHIFT 0
22946 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_MASK)
22947 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_SION_MASK 0x10u
22948 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_SION_SHIFT 4
22949 /* SW_MUX_CTL_PAD_LCD_DATA15 Bit Fields */
22950 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_MASK 0x7u
22951 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_SHIFT 0
22952 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_MASK)
22953 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_SION_MASK 0x10u
22954 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_SION_SHIFT 4
22955 /* SW_MUX_CTL_PAD_LCD_DATA16 Bit Fields */
22956 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_MASK 0x7u
22957 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_SHIFT 0
22958 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_MASK)
22959 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_SION_MASK 0x10u
22960 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_SION_SHIFT 4
22961 /* SW_MUX_CTL_PAD_LCD_DATA17 Bit Fields */
22962 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_MASK 0x7u
22963 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_SHIFT 0
22964 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_MASK)
22965 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_SION_MASK 0x10u
22966 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_SION_SHIFT 4
22967 /* SW_MUX_CTL_PAD_LCD_DATA18 Bit Fields */
22968 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_MASK 0x7u
22969 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_SHIFT 0
22970 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_MASK)
22971 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_SION_MASK 0x10u
22972 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_SION_SHIFT 4
22973 /* SW_MUX_CTL_PAD_LCD_DATA19 Bit Fields */
22974 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_MASK 0x7u
22975 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_SHIFT 0
22976 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_MASK)
22977 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_SION_MASK 0x10u
22978 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_SION_SHIFT 4
22979 /* SW_MUX_CTL_PAD_LCD_DATA20 Bit Fields */
22980 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_MASK 0x7u
22981 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_SHIFT 0
22982 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_MASK)
22983 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_SION_MASK 0x10u
22984 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_SION_SHIFT 4
22985 /* SW_MUX_CTL_PAD_LCD_DATA21 Bit Fields */
22986 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_MASK 0x7u
22987 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_SHIFT 0
22988 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_MASK)
22989 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_SION_MASK 0x10u
22990 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_SION_SHIFT 4
22991 /* SW_MUX_CTL_PAD_LCD_DATA22 Bit Fields */
22992 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_MASK 0x7u
22993 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_SHIFT 0
22994 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_MASK)
22995 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_SION_MASK 0x10u
22996 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_SION_SHIFT 4
22997 /* SW_MUX_CTL_PAD_LCD_DATA23 Bit Fields */
22998 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_MASK 0x7u
22999 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_SHIFT 0
23000 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_MASK)
23001 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_SION_MASK 0x10u
23002 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_SION_SHIFT 4
23003 /* SW_MUX_CTL_PAD_UART1_RX_DATA Bit Fields */
23004 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_MASK 0x7u
23005 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_SHIFT 0
23006 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_MASK)
23007 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION_MASK 0x10u
23008 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION_SHIFT 4
23009 /* SW_MUX_CTL_PAD_UART1_TX_DATA Bit Fields */
23010 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_MASK 0x7u
23011 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_SHIFT 0
23012 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_MASK)
23013 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION_MASK 0x10u
23014 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION_SHIFT 4
23015 /* SW_MUX_CTL_PAD_UART2_RX_DATA Bit Fields */
23016 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_MASK 0x7u
23017 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_SHIFT 0
23018 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_MASK)
23019 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_SION_MASK 0x10u
23020 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_SION_SHIFT 4
23021 /* SW_MUX_CTL_PAD_UART2_TX_DATA Bit Fields */
23022 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_MASK 0x7u
23023 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_SHIFT 0
23024 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_MASK)
23025 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_SION_MASK 0x10u
23026 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_SION_SHIFT 4
23027 /* SW_MUX_CTL_PAD_UART3_RX_DATA Bit Fields */
23028 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_MASK 0x7u
23029 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_SHIFT 0
23030 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_MASK)
23031 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_SION_MASK 0x10u
23032 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_SION_SHIFT 4
23033 /* SW_MUX_CTL_PAD_UART3_TX_DATA Bit Fields */
23034 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_MASK 0x7u
23035 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_SHIFT 0
23036 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_MASK)
23037 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_SION_MASK 0x10u
23038 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_SION_SHIFT 4
23039 /* SW_MUX_CTL_PAD_UART3_RTS_B Bit Fields */
23040 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_MASK 0x7u
23041 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_SHIFT 0
23042 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_MASK)
23043 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_SION_MASK 0x10u
23044 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_SION_SHIFT 4
23045 /* SW_MUX_CTL_PAD_UART3_CTS_B Bit Fields */
23046 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_MASK 0x7u
23047 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_SHIFT 0
23048 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_MASK)
23049 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_SION_MASK 0x10u
23050 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_SION_SHIFT 4
23051 /* SW_MUX_CTL_PAD_I2C1_SCL Bit Fields */
23052 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_MASK 0x7u
23053 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_SHIFT 0
23054 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_MASK)
23055 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_SION_MASK 0x10u
23056 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_SION_SHIFT 4
23057 /* SW_MUX_CTL_PAD_I2C1_SDA Bit Fields */
23058 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_MASK 0x7u
23059 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_SHIFT 0
23060 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_MASK)
23061 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_SION_MASK 0x10u
23062 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_SION_SHIFT 4
23063 /* SW_MUX_CTL_PAD_I2C2_SCL Bit Fields */
23064 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_MASK 0x7u
23065 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_SHIFT 0
23066 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_MASK)
23067 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_SION_MASK 0x10u
23068 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_SION_SHIFT 4
23069 /* SW_MUX_CTL_PAD_I2C2_SDA Bit Fields */
23070 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_MASK 0x7u
23071 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_SHIFT 0
23072 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_MASK)
23073 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_SION_MASK 0x10u
23074 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_SION_SHIFT 4
23075 /* SW_MUX_CTL_PAD_I2C3_SCL Bit Fields */
23076 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_MASK 0x7u
23077 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_SHIFT 0
23078 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_MASK)
23079 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_SION_MASK 0x10u
23080 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_SION_SHIFT 4
23081 /* SW_MUX_CTL_PAD_I2C3_SDA Bit Fields */
23082 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_MASK 0x7u
23083 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_SHIFT 0
23084 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_MASK)
23085 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_SION_MASK 0x10u
23086 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_SION_SHIFT 4
23087 /* SW_MUX_CTL_PAD_I2C4_SCL Bit Fields */
23088 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_MASK 0x7u
23089 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_SHIFT 0
23090 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_MASK)
23091 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_SION_MASK 0x10u
23092 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_SION_SHIFT 4
23093 /* SW_MUX_CTL_PAD_I2C4_SDA Bit Fields */
23094 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_MASK 0x7u
23095 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_SHIFT 0
23096 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_MASK)
23097 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_SION_MASK 0x10u
23098 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_SION_SHIFT 4
23099 /* SW_MUX_CTL_PAD_ECSPI1_SCLK Bit Fields */
23100 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_MASK 0x7u
23101 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_SHIFT 0
23102 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_MASK)
23103 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_SION_MASK 0x10u
23104 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_SION_SHIFT 4
23105 /* SW_MUX_CTL_PAD_ECSPI1_MOSI Bit Fields */
23106 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_MASK 0x7u
23107 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_SHIFT 0
23108 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_MASK)
23109 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_SION_MASK 0x10u
23110 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_SION_SHIFT 4
23111 /* SW_MUX_CTL_PAD_ECSPI1_MISO Bit Fields */
23112 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_MASK 0x7u
23113 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_SHIFT 0
23114 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_MASK)
23115 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_SION_MASK 0x10u
23116 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_SION_SHIFT 4
23117 /* SW_MUX_CTL_PAD_ECSPI1_SS0 Bit Fields */
23118 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_MASK 0x7u
23119 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_SHIFT 0
23120 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_MASK)
23121 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_SION_MASK 0x10u
23122 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_SION_SHIFT 4
23123 /* SW_MUX_CTL_PAD_ECSPI2_SCLK Bit Fields */
23124 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_MASK 0x7u
23125 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_SHIFT 0
23126 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_MASK)
23127 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_SION_MASK 0x10u
23128 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_SION_SHIFT 4
23129 /* SW_MUX_CTL_PAD_ECSPI2_MOSI Bit Fields */
23130 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_MASK 0x7u
23131 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_SHIFT 0
23132 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_MASK)
23133 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_SION_MASK 0x10u
23134 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_SION_SHIFT 4
23135 /* SW_MUX_CTL_PAD_ECSPI2_MISO Bit Fields */
23136 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_MASK 0x7u
23137 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_SHIFT 0
23138 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_MASK)
23139 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_SION_MASK 0x10u
23140 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_SION_SHIFT 4
23141 /* SW_MUX_CTL_PAD_ECSPI2_SS0 Bit Fields */
23142 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_MASK 0x7u
23143 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_SHIFT 0
23144 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_MASK)
23145 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_SION_MASK 0x10u
23146 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_SION_SHIFT 4
23147 /* SW_MUX_CTL_PAD_SD1_CD_B Bit Fields */
23148 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_MASK 0x7u
23149 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_SHIFT 0
23150 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_MASK)
23151 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_SION_MASK 0x10u
23152 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_SION_SHIFT 4
23153 /* SW_MUX_CTL_PAD_SD1_WP Bit Fields */
23154 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_MASK 0x7u
23155 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_SHIFT 0
23156 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_MASK)
23157 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_SION_MASK   0x10u
23158 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_SION_SHIFT  4
23159 /* SW_MUX_CTL_PAD_SD1_RESET_B Bit Fields */
23160 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_MASK 0x7u
23161 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_SHIFT 0
23162 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_MASK)
23163 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_SION_MASK 0x10u
23164 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_SION_SHIFT 4
23165 /* SW_MUX_CTL_PAD_SD1_CLK Bit Fields */
23166 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK 0x7u
23167 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT 0
23168 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK)
23169 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_MASK  0x10u
23170 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_SHIFT 4
23171 /* SW_MUX_CTL_PAD_SD1_CMD Bit Fields */
23172 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK 0x7u
23173 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT 0
23174 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK)
23175 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_MASK  0x10u
23176 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_SHIFT 4
23177 /* SW_MUX_CTL_PAD_SD1_DATA0 Bit Fields */
23178 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK 0x7u
23179 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT 0
23180 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK)
23181 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_MASK 0x10u
23182 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_SHIFT 4
23183 /* SW_MUX_CTL_PAD_SD1_DATA1 Bit Fields */
23184 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK 0x7u
23185 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT 0
23186 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK)
23187 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_MASK 0x10u
23188 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_SHIFT 4
23189 /* SW_MUX_CTL_PAD_SD1_DATA2 Bit Fields */
23190 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK 0x7u
23191 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT 0
23192 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK)
23193 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_MASK 0x10u
23194 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_SHIFT 4
23195 /* SW_MUX_CTL_PAD_SD1_DATA3 Bit Fields */
23196 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK 0x7u
23197 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT 0
23198 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK)
23199 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_MASK 0x10u
23200 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_SHIFT 4
23201 /* SW_MUX_CTL_PAD_SD2_CD_B Bit Fields */
23202 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_MASK 0x7u
23203 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_SHIFT 0
23204 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_MASK)
23205 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_SION_MASK 0x10u
23206 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_SION_SHIFT 4
23207 /* SW_MUX_CTL_PAD_SD2_WP Bit Fields */
23208 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_MASK 0x7u
23209 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_SHIFT 0
23210 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_MASK)
23211 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_SION_MASK   0x10u
23212 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_SION_SHIFT  4
23213 /* SW_MUX_CTL_PAD_SD2_RESET_B Bit Fields */
23214 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_MASK 0x7u
23215 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_SHIFT 0
23216 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_MASK)
23217 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_SION_MASK 0x10u
23218 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_SION_SHIFT 4
23219 /* SW_MUX_CTL_PAD_SD2_CLK Bit Fields */
23220 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK 0x7u
23221 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT 0
23222 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK)
23223 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_MASK  0x10u
23224 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_SHIFT 4
23225 /* SW_MUX_CTL_PAD_SD2_CMD Bit Fields */
23226 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK 0x7u
23227 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT 0
23228 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK)
23229 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_MASK  0x10u
23230 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_SHIFT 4
23231 /* SW_MUX_CTL_PAD_SD2_DATA0 Bit Fields */
23232 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK 0x7u
23233 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT 0
23234 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK)
23235 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_MASK 0x10u
23236 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_SHIFT 4
23237 /* SW_MUX_CTL_PAD_SD2_DATA1 Bit Fields */
23238 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK 0x7u
23239 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT 0
23240 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK)
23241 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_MASK 0x10u
23242 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_SHIFT 4
23243 /* SW_MUX_CTL_PAD_SD2_DATA2 Bit Fields */
23244 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK 0x7u
23245 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT 0
23246 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK)
23247 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_MASK 0x10u
23248 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_SHIFT 4
23249 /* SW_MUX_CTL_PAD_SD2_DATA3 Bit Fields */
23250 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK 0x7u
23251 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT 0
23252 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK)
23253 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_MASK 0x10u
23254 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_SHIFT 4
23255 /* SW_MUX_CTL_PAD_SD3_CLK Bit Fields */
23256 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK 0x7u
23257 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT 0
23258 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK)
23259 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_MASK  0x10u
23260 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_SHIFT 4
23261 /* SW_MUX_CTL_PAD_SD3_CMD Bit Fields */
23262 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK 0x7u
23263 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT 0
23264 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK)
23265 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_MASK  0x10u
23266 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_SHIFT 4
23267 /* SW_MUX_CTL_PAD_SD3_DATA0 Bit Fields */
23268 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK 0x7u
23269 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT 0
23270 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK)
23271 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_MASK 0x10u
23272 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_SHIFT 4
23273 /* SW_MUX_CTL_PAD_SD3_DATA1 Bit Fields */
23274 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK 0x7u
23275 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT 0
23276 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK)
23277 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_MASK 0x10u
23278 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_SHIFT 4
23279 /* SW_MUX_CTL_PAD_SD3_DATA2 Bit Fields */
23280 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK 0x7u
23281 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT 0
23282 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK)
23283 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_MASK 0x10u
23284 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_SHIFT 4
23285 /* SW_MUX_CTL_PAD_SD3_DATA3 Bit Fields */
23286 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK 0x7u
23287 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT 0
23288 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK)
23289 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_MASK 0x10u
23290 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_SHIFT 4
23291 /* SW_MUX_CTL_PAD_SD3_DATA4 Bit Fields */
23292 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK 0x7u
23293 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT 0
23294 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK)
23295 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_MASK 0x10u
23296 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_SHIFT 4
23297 /* SW_MUX_CTL_PAD_SD3_DATA5 Bit Fields */
23298 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK 0x7u
23299 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT 0
23300 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK)
23301 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_MASK 0x10u
23302 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_SHIFT 4
23303 /* SW_MUX_CTL_PAD_SD3_DATA6 Bit Fields */
23304 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK 0x7u
23305 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT 0
23306 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK)
23307 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_MASK 0x10u
23308 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_SHIFT 4
23309 /* SW_MUX_CTL_PAD_SD3_DATA7 Bit Fields */
23310 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK 0x7u
23311 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT 0
23312 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK)
23313 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_MASK 0x10u
23314 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_SHIFT 4
23315 /* SW_MUX_CTL_PAD_SD3_STROBE Bit Fields */
23316 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_MASK 0x7u
23317 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_SHIFT 0
23318 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_MASK)
23319 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_SION_MASK 0x10u
23320 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_SION_SHIFT 4
23321 /* SW_MUX_CTL_PAD_SD3_RESET_B Bit Fields */
23322 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_MASK 0x7u
23323 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_SHIFT 0
23324 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_MASK)
23325 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_SION_MASK 0x10u
23326 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_SION_SHIFT 4
23327 /* SW_MUX_CTL_PAD_SAI1_RX_DATA Bit Fields */
23328 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_MASK 0x7u
23329 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_SHIFT 0
23330 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_MASK)
23331 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_SION_MASK 0x10u
23332 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_SION_SHIFT 4
23333 /* SW_MUX_CTL_PAD_SAI1_TX_BCLK Bit Fields */
23334 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_MASK 0x7u
23335 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_SHIFT 0
23336 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_MASK)
23337 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_SION_MASK 0x10u
23338 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_SION_SHIFT 4
23339 /* SW_MUX_CTL_PAD_SAI1_TX_SYNC Bit Fields */
23340 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_MASK 0x7u
23341 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_SHIFT 0
23342 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_MASK)
23343 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_SION_MASK 0x10u
23344 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_SION_SHIFT 4
23345 /* SW_MUX_CTL_PAD_SAI1_TX_DATA Bit Fields */
23346 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_MASK 0x7u
23347 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_SHIFT 0
23348 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_MASK)
23349 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_SION_MASK 0x10u
23350 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_SION_SHIFT 4
23351 /* SW_MUX_CTL_PAD_SAI1_RX_SYNC Bit Fields */
23352 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_MASK 0x7u
23353 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_SHIFT 0
23354 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_MASK)
23355 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_SION_MASK 0x10u
23356 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_SION_SHIFT 4
23357 /* SW_MUX_CTL_PAD_SAI1_RX_BCLK Bit Fields */
23358 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_MASK 0x7u
23359 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_SHIFT 0
23360 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_MASK)
23361 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_SION_MASK 0x10u
23362 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_SION_SHIFT 4
23363 /* SW_MUX_CTL_PAD_SAI1_MCLK Bit Fields */
23364 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_MASK 0x7u
23365 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_SHIFT 0
23366 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_MASK)
23367 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_SION_MASK 0x10u
23368 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_SION_SHIFT 4
23369 /* SW_MUX_CTL_PAD_SAI2_TX_SYNC Bit Fields */
23370 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_MASK 0x7u
23371 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_SHIFT 0
23372 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_MASK)
23373 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_SION_MASK 0x10u
23374 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_SION_SHIFT 4
23375 /* SW_MUX_CTL_PAD_SAI2_TX_BCLK Bit Fields */
23376 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_MASK 0x7u
23377 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_SHIFT 0
23378 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_MASK)
23379 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_SION_MASK 0x10u
23380 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_SION_SHIFT 4
23381 /* SW_MUX_CTL_PAD_SAI2_RX_DATA Bit Fields */
23382 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_MASK 0x7u
23383 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_SHIFT 0
23384 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_MASK)
23385 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_SION_MASK 0x10u
23386 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_SION_SHIFT 4
23387 /* SW_MUX_CTL_PAD_SAI2_TX_DATA Bit Fields */
23388 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_MASK 0x7u
23389 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_SHIFT 0
23390 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_MASK)
23391 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_SION_MASK 0x10u
23392 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_SION_SHIFT 4
23393 /* SW_MUX_CTL_PAD_ENET1_RGMII_RD0 Bit Fields */
23394 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_MASK 0x7u
23395 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_SHIFT 0
23396 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_MASK)
23397 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_SION_MASK 0x10u
23398 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_SION_SHIFT 4
23399 /* SW_MUX_CTL_PAD_ENET1_RGMII_RD1 Bit Fields */
23400 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_MASK 0x7u
23401 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_SHIFT 0
23402 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_MASK)
23403 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_SION_MASK 0x10u
23404 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_SION_SHIFT 4
23405 /* SW_MUX_CTL_PAD_ENET1_RGMII_RD2 Bit Fields */
23406 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_MASK 0x7u
23407 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_SHIFT 0
23408 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_MASK)
23409 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_SION_MASK 0x10u
23410 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_SION_SHIFT 4
23411 /* SW_MUX_CTL_PAD_ENET1_RGMII_RD3 Bit Fields */
23412 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_MASK 0x7u
23413 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_SHIFT 0
23414 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_MASK)
23415 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_SION_MASK 0x10u
23416 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_SION_SHIFT 4
23417 /* SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL Bit Fields */
23418 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_MASK 0x7u
23419 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_SHIFT 0
23420 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_MASK)
23421 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_SION_MASK 0x10u
23422 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_SION_SHIFT 4
23423 /* SW_MUX_CTL_PAD_ENET1_RGMII_RXC Bit Fields */
23424 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_MASK 0x7u
23425 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_SHIFT 0
23426 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_MASK)
23427 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_SION_MASK 0x10u
23428 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_SION_SHIFT 4
23429 /* SW_MUX_CTL_PAD_ENET1_RGMII_TD0 Bit Fields */
23430 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_MASK 0x7u
23431 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_SHIFT 0
23432 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_MASK)
23433 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_SION_MASK 0x10u
23434 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_SION_SHIFT 4
23435 /* SW_MUX_CTL_PAD_ENET1_RGMII_TD1 Bit Fields */
23436 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_MASK 0x7u
23437 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_SHIFT 0
23438 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_MASK)
23439 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_SION_MASK 0x10u
23440 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_SION_SHIFT 4
23441 /* SW_MUX_CTL_PAD_ENET1_RGMII_TD2 Bit Fields */
23442 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_MASK 0x7u
23443 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_SHIFT 0
23444 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_MASK)
23445 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_SION_MASK 0x10u
23446 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_SION_SHIFT 4
23447 /* SW_MUX_CTL_PAD_ENET1_RGMII_TD3 Bit Fields */
23448 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_MASK 0x7u
23449 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_SHIFT 0
23450 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_MASK)
23451 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_SION_MASK 0x10u
23452 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_SION_SHIFT 4
23453 /* SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL Bit Fields */
23454 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_MASK 0x7u
23455 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_SHIFT 0
23456 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_MASK)
23457 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_SION_MASK 0x10u
23458 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_SION_SHIFT 4
23459 /* SW_MUX_CTL_PAD_ENET1_RGMII_TXC Bit Fields */
23460 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_MASK 0x7u
23461 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_SHIFT 0
23462 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_MASK)
23463 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_SION_MASK 0x10u
23464 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_SION_SHIFT 4
23465 /* SW_MUX_CTL_PAD_ENET1_TX_CLK Bit Fields */
23466 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK 0x7u
23467 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT 0
23468 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK)
23469 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_MASK 0x10u
23470 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_SHIFT 4
23471 /* SW_MUX_CTL_PAD_ENET1_RX_CLK Bit Fields */
23472 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK 0x7u
23473 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT 0
23474 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK)
23475 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_MASK 0x10u
23476 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_SHIFT 4
23477 /* SW_MUX_CTL_PAD_ENET1_CRS Bit Fields */
23478 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK 0x7u
23479 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT 0
23480 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK)
23481 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_MASK 0x10u
23482 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_SHIFT 4
23483 /* SW_MUX_CTL_PAD_ENET1_COL Bit Fields */
23484 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK 0x7u
23485 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT 0
23486 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK)
23487 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_MASK 0x10u
23488 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_SHIFT 4
23489 /* SW_PAD_CTL_PAD_GPIO1_IO08 Bit Fields */
23490 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK 0x3u
23491 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT 0
23492 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK)
23493 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_MASK 0x4u
23494 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_SHIFT 2
23495 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_MASK 0x8u
23496 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_SHIFT 3
23497 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PE_MASK 0x10u
23498 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PE_SHIFT 4
23499 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_MASK 0x60u
23500 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_SHIFT 5
23501 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_MASK)
23502 /* SW_PAD_CTL_PAD_GPIO1_IO09 Bit Fields */
23503 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK 0x3u
23504 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT 0
23505 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK)
23506 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_MASK 0x4u
23507 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_SHIFT 2
23508 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_MASK 0x8u
23509 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_SHIFT 3
23510 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PE_MASK 0x10u
23511 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PE_SHIFT 4
23512 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_MASK 0x60u
23513 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_SHIFT 5
23514 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_MASK)
23515 /* SW_PAD_CTL_PAD_GPIO1_IO10 Bit Fields */
23516 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK 0x3u
23517 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT 0
23518 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK)
23519 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_MASK 0x4u
23520 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_SHIFT 2
23521 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_MASK 0x8u
23522 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_SHIFT 3
23523 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PE_MASK 0x10u
23524 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PE_SHIFT 4
23525 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_MASK 0x60u
23526 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_SHIFT 5
23527 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_MASK)
23528 /* SW_PAD_CTL_PAD_GPIO1_IO11 Bit Fields */
23529 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK 0x3u
23530 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT 0
23531 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK)
23532 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_MASK 0x4u
23533 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_SHIFT 2
23534 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_MASK 0x8u
23535 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_SHIFT 3
23536 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PE_MASK 0x10u
23537 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PE_SHIFT 4
23538 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_MASK 0x60u
23539 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_SHIFT 5
23540 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_MASK)
23541 /* SW_PAD_CTL_PAD_GPIO1_IO12 Bit Fields */
23542 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK 0x3u
23543 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT 0
23544 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK)
23545 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_MASK 0x4u
23546 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_SHIFT 2
23547 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_MASK 0x8u
23548 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_SHIFT 3
23549 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PE_MASK 0x10u
23550 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PE_SHIFT 4
23551 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_MASK 0x60u
23552 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_SHIFT 5
23553 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_MASK)
23554 /* SW_PAD_CTL_PAD_GPIO1_IO13 Bit Fields */
23555 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK 0x3u
23556 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT 0
23557 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK)
23558 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_MASK 0x4u
23559 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_SHIFT 2
23560 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_MASK 0x8u
23561 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_SHIFT 3
23562 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PE_MASK 0x10u
23563 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PE_SHIFT 4
23564 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_MASK 0x60u
23565 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_SHIFT 5
23566 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_MASK)
23567 /* SW_PAD_CTL_PAD_GPIO1_IO14 Bit Fields */
23568 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_MASK 0x3u
23569 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_SHIFT 0
23570 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_MASK)
23571 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_SRE_MASK 0x4u
23572 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_SRE_SHIFT 2
23573 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_HYS_MASK 0x8u
23574 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_HYS_SHIFT 3
23575 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_MASK 0x10u
23576 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_SHIFT 4
23577 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_MASK 0x60u
23578 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_SHIFT 5
23579 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_MASK)
23580 /* SW_PAD_CTL_PAD_GPIO1_IO15 Bit Fields */
23581 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_MASK 0x3u
23582 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_SHIFT 0
23583 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_MASK)
23584 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_SRE_MASK 0x4u
23585 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_SRE_SHIFT 2
23586 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_MASK 0x8u
23587 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_SHIFT 3
23588 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PE_MASK 0x10u
23589 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PE_SHIFT 4
23590 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_MASK 0x60u
23591 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_SHIFT 5
23592 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_MASK)
23593 /* SW_PAD_CTL_PAD_JTAG_MOD Bit Fields */
23594 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK  0x3u
23595 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT 0
23596 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK)
23597 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_MASK  0x4u
23598 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_SHIFT 2
23599 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_MASK  0x8u
23600 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_SHIFT 3
23601 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PE_MASK   0x10u
23602 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PE_SHIFT  4
23603 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_MASK   0x60u
23604 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_SHIFT  5
23605 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_MASK)
23606 /* SW_PAD_CTL_PAD_JTAG_TCK Bit Fields */
23607 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK  0x3u
23608 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT 0
23609 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK)
23610 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_MASK  0x4u
23611 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_SHIFT 2
23612 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_MASK  0x8u
23613 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_SHIFT 3
23614 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PE_MASK   0x10u
23615 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PE_SHIFT  4
23616 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_MASK   0x60u
23617 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_SHIFT  5
23618 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_MASK)
23619 /* SW_PAD_CTL_PAD_JTAG_TDI Bit Fields */
23620 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK  0x3u
23621 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT 0
23622 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK)
23623 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_MASK  0x4u
23624 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_SHIFT 2
23625 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_MASK  0x8u
23626 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_SHIFT 3
23627 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PE_MASK   0x10u
23628 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PE_SHIFT  4
23629 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_MASK   0x60u
23630 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_SHIFT  5
23631 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_MASK)
23632 /* SW_PAD_CTL_PAD_JTAG_TDO Bit Fields */
23633 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK  0x3u
23634 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT 0
23635 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK)
23636 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_MASK  0x4u
23637 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_SHIFT 2
23638 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_MASK  0x8u
23639 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_SHIFT 3
23640 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PE_MASK   0x10u
23641 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PE_SHIFT  4
23642 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_MASK   0x60u
23643 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_SHIFT  5
23644 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_MASK)
23645 /* SW_PAD_CTL_PAD_JTAG_TMS Bit Fields */
23646 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK  0x3u
23647 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT 0
23648 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK)
23649 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_MASK  0x4u
23650 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_SHIFT 2
23651 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_MASK  0x8u
23652 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_SHIFT 3
23653 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PE_MASK   0x10u
23654 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PE_SHIFT  4
23655 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_MASK   0x60u
23656 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_SHIFT  5
23657 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_MASK)
23658 /* SW_PAD_CTL_PAD_JTAG_TRST_B Bit Fields */
23659 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK 0x3u
23660 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT 0
23661 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK)
23662 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_MASK 0x4u
23663 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_SHIFT 2
23664 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_MASK 0x8u
23665 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_SHIFT 3
23666 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PE_MASK 0x10u
23667 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PE_SHIFT 4
23668 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_MASK 0x60u
23669 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_SHIFT 5
23670 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_MASK)
23671 /* SW_PAD_CTL_PAD_EPDC_DATA00 Bit Fields */
23672 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_MASK 0x3u
23673 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_SHIFT 0
23674 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_MASK)
23675 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_SRE_MASK 0x4u
23676 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_SRE_SHIFT 2
23677 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_HYS_MASK 0x8u
23678 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_HYS_SHIFT 3
23679 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PE_MASK 0x10u
23680 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PE_SHIFT 4
23681 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_MASK 0x60u
23682 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_SHIFT 5
23683 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_MASK)
23684 /* SW_PAD_CTL_PAD_EPDC_DATA01 Bit Fields */
23685 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_MASK 0x3u
23686 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_SHIFT 0
23687 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_MASK)
23688 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_SRE_MASK 0x4u
23689 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_SRE_SHIFT 2
23690 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_HYS_MASK 0x8u
23691 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_HYS_SHIFT 3
23692 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PE_MASK 0x10u
23693 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PE_SHIFT 4
23694 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_MASK 0x60u
23695 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_SHIFT 5
23696 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_MASK)
23697 /* SW_PAD_CTL_PAD_EPDC_DATA02 Bit Fields */
23698 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_MASK 0x3u
23699 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_SHIFT 0
23700 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_MASK)
23701 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_SRE_MASK 0x4u
23702 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_SRE_SHIFT 2
23703 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_HYS_MASK 0x8u
23704 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_HYS_SHIFT 3
23705 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PE_MASK 0x10u
23706 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PE_SHIFT 4
23707 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_MASK 0x60u
23708 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_SHIFT 5
23709 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_MASK)
23710 /* SW_PAD_CTL_PAD_EPDC_DATA03 Bit Fields */
23711 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_MASK 0x3u
23712 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_SHIFT 0
23713 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_MASK)
23714 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_SRE_MASK 0x4u
23715 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_SRE_SHIFT 2
23716 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_HYS_MASK 0x8u
23717 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_HYS_SHIFT 3
23718 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PE_MASK 0x10u
23719 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PE_SHIFT 4
23720 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_MASK 0x60u
23721 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_SHIFT 5
23722 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_MASK)
23723 /* SW_PAD_CTL_PAD_EPDC_DATA04 Bit Fields */
23724 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_MASK 0x3u
23725 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_SHIFT 0
23726 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_MASK)
23727 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_SRE_MASK 0x4u
23728 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_SRE_SHIFT 2
23729 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_HYS_MASK 0x8u
23730 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_HYS_SHIFT 3
23731 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PE_MASK 0x10u
23732 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PE_SHIFT 4
23733 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_MASK 0x60u
23734 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_SHIFT 5
23735 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_MASK)
23736 /* SW_PAD_CTL_PAD_EPDC_DATA05 Bit Fields */
23737 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_MASK 0x3u
23738 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_SHIFT 0
23739 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_MASK)
23740 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_SRE_MASK 0x4u
23741 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_SRE_SHIFT 2
23742 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_HYS_MASK 0x8u
23743 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_HYS_SHIFT 3
23744 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PE_MASK 0x10u
23745 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PE_SHIFT 4
23746 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_MASK 0x60u
23747 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_SHIFT 5
23748 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_MASK)
23749 /* SW_PAD_CTL_PAD_EPDC_DATA06 Bit Fields */
23750 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_MASK 0x3u
23751 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_SHIFT 0
23752 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_MASK)
23753 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_SRE_MASK 0x4u
23754 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_SRE_SHIFT 2
23755 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_HYS_MASK 0x8u
23756 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_HYS_SHIFT 3
23757 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PE_MASK 0x10u
23758 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PE_SHIFT 4
23759 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_MASK 0x60u
23760 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_SHIFT 5
23761 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_MASK)
23762 /* SW_PAD_CTL_PAD_EPDC_DATA07 Bit Fields */
23763 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_MASK 0x3u
23764 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_SHIFT 0
23765 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_MASK)
23766 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_SRE_MASK 0x4u
23767 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_SRE_SHIFT 2
23768 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_HYS_MASK 0x8u
23769 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_HYS_SHIFT 3
23770 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PE_MASK 0x10u
23771 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PE_SHIFT 4
23772 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_MASK 0x60u
23773 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_SHIFT 5
23774 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_MASK)
23775 /* SW_PAD_CTL_PAD_EPDC_DATA08 Bit Fields */
23776 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_MASK 0x3u
23777 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_SHIFT 0
23778 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_MASK)
23779 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_SRE_MASK 0x4u
23780 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_SRE_SHIFT 2
23781 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_HYS_MASK 0x8u
23782 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_HYS_SHIFT 3
23783 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PE_MASK 0x10u
23784 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PE_SHIFT 4
23785 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_MASK 0x60u
23786 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_SHIFT 5
23787 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_MASK)
23788 /* SW_PAD_CTL_PAD_EPDC_DATA09 Bit Fields */
23789 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_MASK 0x3u
23790 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_SHIFT 0
23791 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_MASK)
23792 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_SRE_MASK 0x4u
23793 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_SRE_SHIFT 2
23794 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_HYS_MASK 0x8u
23795 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_HYS_SHIFT 3
23796 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PE_MASK 0x10u
23797 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PE_SHIFT 4
23798 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_MASK 0x60u
23799 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_SHIFT 5
23800 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_MASK)
23801 /* SW_PAD_CTL_PAD_EPDC_DATA10 Bit Fields */
23802 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_MASK 0x3u
23803 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_SHIFT 0
23804 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_MASK)
23805 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_SRE_MASK 0x4u
23806 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_SRE_SHIFT 2
23807 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_HYS_MASK 0x8u
23808 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_HYS_SHIFT 3
23809 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PE_MASK 0x10u
23810 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PE_SHIFT 4
23811 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_MASK 0x60u
23812 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_SHIFT 5
23813 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_MASK)
23814 /* SW_PAD_CTL_PAD_EPDC_DATA11 Bit Fields */
23815 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_MASK 0x3u
23816 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_SHIFT 0
23817 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_MASK)
23818 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_SRE_MASK 0x4u
23819 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_SRE_SHIFT 2
23820 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_HYS_MASK 0x8u
23821 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_HYS_SHIFT 3
23822 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PE_MASK 0x10u
23823 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PE_SHIFT 4
23824 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_MASK 0x60u
23825 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_SHIFT 5
23826 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_MASK)
23827 /* SW_PAD_CTL_PAD_EPDC_DATA12 Bit Fields */
23828 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_MASK 0x3u
23829 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_SHIFT 0
23830 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_MASK)
23831 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_SRE_MASK 0x4u
23832 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_SRE_SHIFT 2
23833 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_HYS_MASK 0x8u
23834 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_HYS_SHIFT 3
23835 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PE_MASK 0x10u
23836 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PE_SHIFT 4
23837 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_MASK 0x60u
23838 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_SHIFT 5
23839 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_MASK)
23840 /* SW_PAD_CTL_PAD_EPDC_DATA13 Bit Fields */
23841 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_MASK 0x3u
23842 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_SHIFT 0
23843 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_MASK)
23844 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_SRE_MASK 0x4u
23845 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_SRE_SHIFT 2
23846 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_HYS_MASK 0x8u
23847 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_HYS_SHIFT 3
23848 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PE_MASK 0x10u
23849 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PE_SHIFT 4
23850 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_MASK 0x60u
23851 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_SHIFT 5
23852 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_MASK)
23853 /* SW_PAD_CTL_PAD_EPDC_DATA14 Bit Fields */
23854 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_MASK 0x3u
23855 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_SHIFT 0
23856 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_MASK)
23857 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_SRE_MASK 0x4u
23858 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_SRE_SHIFT 2
23859 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_HYS_MASK 0x8u
23860 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_HYS_SHIFT 3
23861 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PE_MASK 0x10u
23862 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PE_SHIFT 4
23863 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_MASK 0x60u
23864 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_SHIFT 5
23865 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_MASK)
23866 /* SW_PAD_CTL_PAD_EPDC_DATA15 Bit Fields */
23867 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_MASK 0x3u
23868 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_SHIFT 0
23869 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_MASK)
23870 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_SRE_MASK 0x4u
23871 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_SRE_SHIFT 2
23872 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_HYS_MASK 0x8u
23873 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_HYS_SHIFT 3
23874 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PE_MASK 0x10u
23875 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PE_SHIFT 4
23876 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_MASK 0x60u
23877 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_SHIFT 5
23878 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_MASK)
23879 /* SW_PAD_CTL_PAD_EPDC_SDCLK Bit Fields */
23880 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_MASK 0x3u
23881 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_SHIFT 0
23882 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_MASK)
23883 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_SRE_MASK 0x4u
23884 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_SRE_SHIFT 2
23885 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_HYS_MASK 0x8u
23886 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_HYS_SHIFT 3
23887 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PE_MASK 0x10u
23888 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PE_SHIFT 4
23889 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_MASK 0x60u
23890 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_SHIFT 5
23891 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_MASK)
23892 /* SW_PAD_CTL_PAD_EPDC_SDLE Bit Fields */
23893 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_MASK 0x3u
23894 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_SHIFT 0
23895 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_MASK)
23896 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_SRE_MASK 0x4u
23897 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_SRE_SHIFT 2
23898 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_HYS_MASK 0x8u
23899 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_HYS_SHIFT 3
23900 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PE_MASK  0x10u
23901 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PE_SHIFT 4
23902 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_MASK  0x60u
23903 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_SHIFT 5
23904 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_MASK)
23905 /* SW_PAD_CTL_PAD_EPDC_SDOE Bit Fields */
23906 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_MASK 0x3u
23907 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_SHIFT 0
23908 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_MASK)
23909 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_SRE_MASK 0x4u
23910 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_SRE_SHIFT 2
23911 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_HYS_MASK 0x8u
23912 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_HYS_SHIFT 3
23913 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PE_MASK  0x10u
23914 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PE_SHIFT 4
23915 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_MASK  0x60u
23916 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_SHIFT 5
23917 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_MASK)
23918 /* SW_PAD_CTL_PAD_EPDC_SDSHR Bit Fields */
23919 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_MASK 0x3u
23920 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_SHIFT 0
23921 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_MASK)
23922 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_SRE_MASK 0x4u
23923 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_SRE_SHIFT 2
23924 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_HYS_MASK 0x8u
23925 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_HYS_SHIFT 3
23926 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PE_MASK 0x10u
23927 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PE_SHIFT 4
23928 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_MASK 0x60u
23929 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_SHIFT 5
23930 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_MASK)
23931 /* SW_PAD_CTL_PAD_EPDC_SDCE0 Bit Fields */
23932 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_MASK 0x3u
23933 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_SHIFT 0
23934 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_MASK)
23935 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_SRE_MASK 0x4u
23936 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_SRE_SHIFT 2
23937 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_HYS_MASK 0x8u
23938 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_HYS_SHIFT 3
23939 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PE_MASK 0x10u
23940 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PE_SHIFT 4
23941 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_MASK 0x60u
23942 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_SHIFT 5
23943 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_MASK)
23944 /* SW_PAD_CTL_PAD_EPDC_SDCE1 Bit Fields */
23945 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_MASK 0x3u
23946 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_SHIFT 0
23947 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_MASK)
23948 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_SRE_MASK 0x4u
23949 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_SRE_SHIFT 2
23950 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_HYS_MASK 0x8u
23951 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_HYS_SHIFT 3
23952 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PE_MASK 0x10u
23953 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PE_SHIFT 4
23954 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_MASK 0x60u
23955 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_SHIFT 5
23956 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_MASK)
23957 /* SW_PAD_CTL_PAD_EPDC_SDCE2 Bit Fields */
23958 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_MASK 0x3u
23959 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_SHIFT 0
23960 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_MASK)
23961 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_SRE_MASK 0x4u
23962 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_SRE_SHIFT 2
23963 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_HYS_MASK 0x8u
23964 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_HYS_SHIFT 3
23965 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PE_MASK 0x10u
23966 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PE_SHIFT 4
23967 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_MASK 0x60u
23968 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_SHIFT 5
23969 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_MASK)
23970 /* SW_PAD_CTL_PAD_EPDC_SDCE3 Bit Fields */
23971 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_MASK 0x3u
23972 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_SHIFT 0
23973 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_MASK)
23974 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_SRE_MASK 0x4u
23975 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_SRE_SHIFT 2
23976 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_HYS_MASK 0x8u
23977 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_HYS_SHIFT 3
23978 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PE_MASK 0x10u
23979 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PE_SHIFT 4
23980 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_MASK 0x60u
23981 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_SHIFT 5
23982 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_MASK)
23983 /* SW_PAD_CTL_PAD_EPDC_GDCLK Bit Fields */
23984 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_MASK 0x3u
23985 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_SHIFT 0
23986 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_MASK)
23987 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_SRE_MASK 0x4u
23988 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_SRE_SHIFT 2
23989 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_HYS_MASK 0x8u
23990 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_HYS_SHIFT 3
23991 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PE_MASK 0x10u
23992 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PE_SHIFT 4
23993 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_MASK 0x60u
23994 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_SHIFT 5
23995 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_MASK)
23996 /* SW_PAD_CTL_PAD_EPDC_GDOE Bit Fields */
23997 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_MASK 0x3u
23998 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_SHIFT 0
23999 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_MASK)
24000 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_SRE_MASK 0x4u
24001 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_SRE_SHIFT 2
24002 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_HYS_MASK 0x8u
24003 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_HYS_SHIFT 3
24004 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PE_MASK  0x10u
24005 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PE_SHIFT 4
24006 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_MASK  0x60u
24007 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_SHIFT 5
24008 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_MASK)
24009 /* SW_PAD_CTL_PAD_EPDC_GDRL Bit Fields */
24010 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_MASK 0x3u
24011 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_SHIFT 0
24012 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_MASK)
24013 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_SRE_MASK 0x4u
24014 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_SRE_SHIFT 2
24015 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_HYS_MASK 0x8u
24016 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_HYS_SHIFT 3
24017 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PE_MASK  0x10u
24018 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PE_SHIFT 4
24019 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_MASK  0x60u
24020 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_SHIFT 5
24021 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_MASK)
24022 /* SW_PAD_CTL_PAD_EPDC_GDSP Bit Fields */
24023 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_MASK 0x3u
24024 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_SHIFT 0
24025 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_MASK)
24026 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_SRE_MASK 0x4u
24027 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_SRE_SHIFT 2
24028 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_HYS_MASK 0x8u
24029 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_HYS_SHIFT 3
24030 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PE_MASK  0x10u
24031 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PE_SHIFT 4
24032 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_MASK  0x60u
24033 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_SHIFT 5
24034 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_MASK)
24035 /* SW_PAD_CTL_PAD_EPDC_BDR0 Bit Fields */
24036 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_MASK 0x3u
24037 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_SHIFT 0
24038 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_MASK)
24039 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_SRE_MASK 0x4u
24040 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_SRE_SHIFT 2
24041 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_HYS_MASK 0x8u
24042 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_HYS_SHIFT 3
24043 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PE_MASK  0x10u
24044 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PE_SHIFT 4
24045 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_MASK  0x60u
24046 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_SHIFT 5
24047 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_MASK)
24048 /* SW_PAD_CTL_PAD_EPDC_BDR1 Bit Fields */
24049 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_MASK 0x3u
24050 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_SHIFT 0
24051 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_MASK)
24052 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_SRE_MASK 0x4u
24053 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_SRE_SHIFT 2
24054 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_HYS_MASK 0x8u
24055 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_HYS_SHIFT 3
24056 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PE_MASK  0x10u
24057 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PE_SHIFT 4
24058 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_MASK  0x60u
24059 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_SHIFT 5
24060 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_MASK)
24061 /* SW_PAD_CTL_PAD_EPDC_PWR_COM Bit Fields */
24062 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_MASK 0x3u
24063 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_SHIFT 0
24064 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_MASK)
24065 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_SRE_MASK 0x4u
24066 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_SRE_SHIFT 2
24067 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_HYS_MASK 0x8u
24068 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_HYS_SHIFT 3
24069 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PE_MASK 0x10u
24070 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PE_SHIFT 4
24071 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_MASK 0x60u
24072 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_SHIFT 5
24073 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_MASK)
24074 /* SW_PAD_CTL_PAD_EPDC_PWR_STAT Bit Fields */
24075 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_MASK 0x3u
24076 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_SHIFT 0
24077 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_MASK)
24078 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_SRE_MASK 0x4u
24079 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_SRE_SHIFT 2
24080 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_HYS_MASK 0x8u
24081 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_HYS_SHIFT 3
24082 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PE_MASK 0x10u
24083 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PE_SHIFT 4
24084 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_MASK 0x60u
24085 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_SHIFT 5
24086 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_MASK)
24087 /* SW_PAD_CTL_PAD_LCD_CLK Bit Fields */
24088 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_MASK   0x3u
24089 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_SHIFT  0
24090 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_MASK)
24091 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_SRE_MASK   0x4u
24092 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_SRE_SHIFT  2
24093 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_HYS_MASK   0x8u
24094 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_HYS_SHIFT  3
24095 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PE_MASK    0x10u
24096 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PE_SHIFT   4
24097 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_MASK    0x60u
24098 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_SHIFT   5
24099 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_MASK)
24100 /* SW_PAD_CTL_PAD_LCD_ENABLE Bit Fields */
24101 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_MASK 0x3u
24102 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_SHIFT 0
24103 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_MASK)
24104 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_SRE_MASK 0x4u
24105 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_SRE_SHIFT 2
24106 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_HYS_MASK 0x8u
24107 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_HYS_SHIFT 3
24108 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PE_MASK 0x10u
24109 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PE_SHIFT 4
24110 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_MASK 0x60u
24111 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_SHIFT 5
24112 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_MASK)
24113 /* SW_PAD_CTL_PAD_LCD_HSYNC Bit Fields */
24114 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_MASK 0x3u
24115 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_SHIFT 0
24116 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_MASK)
24117 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_SRE_MASK 0x4u
24118 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_SRE_SHIFT 2
24119 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_HYS_MASK 0x8u
24120 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_HYS_SHIFT 3
24121 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PE_MASK  0x10u
24122 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PE_SHIFT 4
24123 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_MASK  0x60u
24124 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_SHIFT 5
24125 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_MASK)
24126 /* SW_PAD_CTL_PAD_LCD_VSYNC Bit Fields */
24127 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_MASK 0x3u
24128 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_SHIFT 0
24129 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_MASK)
24130 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_SRE_MASK 0x4u
24131 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_SRE_SHIFT 2
24132 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_HYS_MASK 0x8u
24133 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_HYS_SHIFT 3
24134 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PE_MASK  0x10u
24135 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PE_SHIFT 4
24136 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_MASK  0x60u
24137 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_SHIFT 5
24138 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_MASK)
24139 /* SW_PAD_CTL_PAD_LCD_RESET Bit Fields */
24140 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_MASK 0x3u
24141 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_SHIFT 0
24142 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_MASK)
24143 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_SRE_MASK 0x4u
24144 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_SRE_SHIFT 2
24145 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_HYS_MASK 0x8u
24146 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_HYS_SHIFT 3
24147 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PE_MASK  0x10u
24148 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PE_SHIFT 4
24149 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_MASK  0x60u
24150 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_SHIFT 5
24151 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_MASK)
24152 /* SW_PAD_CTL_PAD_LCD_DATA00 Bit Fields */
24153 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_MASK 0x3u
24154 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_SHIFT 0
24155 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_MASK)
24156 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_SRE_MASK 0x4u
24157 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_SRE_SHIFT 2
24158 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_HYS_MASK 0x8u
24159 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_HYS_SHIFT 3
24160 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PE_MASK 0x10u
24161 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PE_SHIFT 4
24162 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_MASK 0x60u
24163 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_SHIFT 5
24164 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_MASK)
24165 /* SW_PAD_CTL_PAD_LCD_DATA01 Bit Fields */
24166 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_MASK 0x3u
24167 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_SHIFT 0
24168 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_MASK)
24169 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_SRE_MASK 0x4u
24170 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_SRE_SHIFT 2
24171 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_HYS_MASK 0x8u
24172 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_HYS_SHIFT 3
24173 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PE_MASK 0x10u
24174 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PE_SHIFT 4
24175 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_MASK 0x60u
24176 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_SHIFT 5
24177 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_MASK)
24178 /* SW_PAD_CTL_PAD_LCD_DATA02 Bit Fields */
24179 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_MASK 0x3u
24180 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_SHIFT 0
24181 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_MASK)
24182 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_SRE_MASK 0x4u
24183 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_SRE_SHIFT 2
24184 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_HYS_MASK 0x8u
24185 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_HYS_SHIFT 3
24186 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PE_MASK 0x10u
24187 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PE_SHIFT 4
24188 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_MASK 0x60u
24189 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_SHIFT 5
24190 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_MASK)
24191 /* SW_PAD_CTL_PAD_LCD_DATA03 Bit Fields */
24192 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_MASK 0x3u
24193 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_SHIFT 0
24194 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_MASK)
24195 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_SRE_MASK 0x4u
24196 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_SRE_SHIFT 2
24197 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_HYS_MASK 0x8u
24198 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_HYS_SHIFT 3
24199 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PE_MASK 0x10u
24200 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PE_SHIFT 4
24201 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_MASK 0x60u
24202 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_SHIFT 5
24203 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_MASK)
24204 /* SW_PAD_CTL_PAD_LCD_DATA04 Bit Fields */
24205 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_MASK 0x3u
24206 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_SHIFT 0
24207 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_MASK)
24208 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_SRE_MASK 0x4u
24209 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_SRE_SHIFT 2
24210 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_HYS_MASK 0x8u
24211 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_HYS_SHIFT 3
24212 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PE_MASK 0x10u
24213 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PE_SHIFT 4
24214 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_MASK 0x60u
24215 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_SHIFT 5
24216 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_MASK)
24217 /* SW_PAD_CTL_PAD_LCD_DATA05 Bit Fields */
24218 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_MASK 0x3u
24219 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_SHIFT 0
24220 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_MASK)
24221 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_SRE_MASK 0x4u
24222 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_SRE_SHIFT 2
24223 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_HYS_MASK 0x8u
24224 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_HYS_SHIFT 3
24225 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PE_MASK 0x10u
24226 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PE_SHIFT 4
24227 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_MASK 0x60u
24228 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_SHIFT 5
24229 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_MASK)
24230 /* SW_PAD_CTL_PAD_LCD_DATA06 Bit Fields */
24231 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_MASK 0x3u
24232 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_SHIFT 0
24233 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_MASK)
24234 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_SRE_MASK 0x4u
24235 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_SRE_SHIFT 2
24236 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_HYS_MASK 0x8u
24237 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_HYS_SHIFT 3
24238 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PE_MASK 0x10u
24239 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PE_SHIFT 4
24240 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_MASK 0x60u
24241 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_SHIFT 5
24242 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_MASK)
24243 /* SW_PAD_CTL_PAD_LCD_DATA07 Bit Fields */
24244 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_MASK 0x3u
24245 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_SHIFT 0
24246 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_MASK)
24247 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_SRE_MASK 0x4u
24248 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_SRE_SHIFT 2
24249 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_HYS_MASK 0x8u
24250 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_HYS_SHIFT 3
24251 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PE_MASK 0x10u
24252 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PE_SHIFT 4
24253 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_MASK 0x60u
24254 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_SHIFT 5
24255 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_MASK)
24256 /* SW_PAD_CTL_PAD_LCD_DATA08 Bit Fields */
24257 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_MASK 0x3u
24258 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_SHIFT 0
24259 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_MASK)
24260 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_SRE_MASK 0x4u
24261 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_SRE_SHIFT 2
24262 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_HYS_MASK 0x8u
24263 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_HYS_SHIFT 3
24264 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PE_MASK 0x10u
24265 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PE_SHIFT 4
24266 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_MASK 0x60u
24267 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_SHIFT 5
24268 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_MASK)
24269 /* SW_PAD_CTL_PAD_LCD_DATA09 Bit Fields */
24270 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_MASK 0x3u
24271 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_SHIFT 0
24272 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_MASK)
24273 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_SRE_MASK 0x4u
24274 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_SRE_SHIFT 2
24275 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_HYS_MASK 0x8u
24276 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_HYS_SHIFT 3
24277 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PE_MASK 0x10u
24278 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PE_SHIFT 4
24279 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_MASK 0x60u
24280 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_SHIFT 5
24281 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_MASK)
24282 /* SW_PAD_CTL_PAD_LCD_DATA10 Bit Fields */
24283 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_MASK 0x3u
24284 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_SHIFT 0
24285 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_MASK)
24286 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_SRE_MASK 0x4u
24287 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_SRE_SHIFT 2
24288 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_HYS_MASK 0x8u
24289 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_HYS_SHIFT 3
24290 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PE_MASK 0x10u
24291 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PE_SHIFT 4
24292 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_MASK 0x60u
24293 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_SHIFT 5
24294 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_MASK)
24295 /* SW_PAD_CTL_PAD_LCD_DATA11 Bit Fields */
24296 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_MASK 0x3u
24297 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_SHIFT 0
24298 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_MASK)
24299 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_SRE_MASK 0x4u
24300 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_SRE_SHIFT 2
24301 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_HYS_MASK 0x8u
24302 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_HYS_SHIFT 3
24303 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PE_MASK 0x10u
24304 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PE_SHIFT 4
24305 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_MASK 0x60u
24306 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_SHIFT 5
24307 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_MASK)
24308 /* SW_PAD_CTL_PAD_LCD_DATA12 Bit Fields */
24309 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_MASK 0x3u
24310 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_SHIFT 0
24311 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_MASK)
24312 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_SRE_MASK 0x4u
24313 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_SRE_SHIFT 2
24314 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_HYS_MASK 0x8u
24315 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_HYS_SHIFT 3
24316 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PE_MASK 0x10u
24317 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PE_SHIFT 4
24318 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_MASK 0x60u
24319 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_SHIFT 5
24320 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_MASK)
24321 /* SW_PAD_CTL_PAD_LCD_DATA13 Bit Fields */
24322 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_MASK 0x3u
24323 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_SHIFT 0
24324 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_MASK)
24325 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_SRE_MASK 0x4u
24326 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_SRE_SHIFT 2
24327 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_HYS_MASK 0x8u
24328 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_HYS_SHIFT 3
24329 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PE_MASK 0x10u
24330 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PE_SHIFT 4
24331 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_MASK 0x60u
24332 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_SHIFT 5
24333 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_MASK)
24334 /* SW_PAD_CTL_PAD_LCD_DATA14 Bit Fields */
24335 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_MASK 0x3u
24336 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_SHIFT 0
24337 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_MASK)
24338 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_SRE_MASK 0x4u
24339 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_SRE_SHIFT 2
24340 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_HYS_MASK 0x8u
24341 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_HYS_SHIFT 3
24342 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PE_MASK 0x10u
24343 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PE_SHIFT 4
24344 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_MASK 0x60u
24345 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_SHIFT 5
24346 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_MASK)
24347 /* SW_PAD_CTL_PAD_LCD_DATA15 Bit Fields */
24348 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_MASK 0x3u
24349 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_SHIFT 0
24350 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_MASK)
24351 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_SRE_MASK 0x4u
24352 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_SRE_SHIFT 2
24353 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_HYS_MASK 0x8u
24354 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_HYS_SHIFT 3
24355 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PE_MASK 0x10u
24356 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PE_SHIFT 4
24357 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_MASK 0x60u
24358 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_SHIFT 5
24359 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_MASK)
24360 /* SW_PAD_CTL_PAD_LCD_DATA16 Bit Fields */
24361 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_MASK 0x3u
24362 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_SHIFT 0
24363 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_MASK)
24364 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_SRE_MASK 0x4u
24365 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_SRE_SHIFT 2
24366 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_HYS_MASK 0x8u
24367 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_HYS_SHIFT 3
24368 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PE_MASK 0x10u
24369 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PE_SHIFT 4
24370 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_MASK 0x60u
24371 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_SHIFT 5
24372 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_MASK)
24373 /* SW_PAD_CTL_PAD_LCD_DATA17 Bit Fields */
24374 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_MASK 0x3u
24375 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_SHIFT 0
24376 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_MASK)
24377 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_SRE_MASK 0x4u
24378 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_SRE_SHIFT 2
24379 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_HYS_MASK 0x8u
24380 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_HYS_SHIFT 3
24381 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PE_MASK 0x10u
24382 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PE_SHIFT 4
24383 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_MASK 0x60u
24384 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_SHIFT 5
24385 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_MASK)
24386 /* SW_PAD_CTL_PAD_LCD_DATA18 Bit Fields */
24387 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_MASK 0x3u
24388 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_SHIFT 0
24389 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_MASK)
24390 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_SRE_MASK 0x4u
24391 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_SRE_SHIFT 2
24392 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_HYS_MASK 0x8u
24393 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_HYS_SHIFT 3
24394 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PE_MASK 0x10u
24395 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PE_SHIFT 4
24396 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_MASK 0x60u
24397 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_SHIFT 5
24398 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_MASK)
24399 /* SW_PAD_CTL_PAD_LCD_DATA19 Bit Fields */
24400 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_MASK 0x3u
24401 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_SHIFT 0
24402 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_MASK)
24403 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_SRE_MASK 0x4u
24404 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_SRE_SHIFT 2
24405 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_HYS_MASK 0x8u
24406 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_HYS_SHIFT 3
24407 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PE_MASK 0x10u
24408 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PE_SHIFT 4
24409 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_MASK 0x60u
24410 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_SHIFT 5
24411 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_MASK)
24412 /* SW_PAD_CTL_PAD_LCD_DATA20 Bit Fields */
24413 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_MASK 0x3u
24414 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_SHIFT 0
24415 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_MASK)
24416 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_SRE_MASK 0x4u
24417 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_SRE_SHIFT 2
24418 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_HYS_MASK 0x8u
24419 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_HYS_SHIFT 3
24420 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PE_MASK 0x10u
24421 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PE_SHIFT 4
24422 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_MASK 0x60u
24423 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_SHIFT 5
24424 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_MASK)
24425 /* SW_PAD_CTL_PAD_LCD_DATA21 Bit Fields */
24426 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_MASK 0x3u
24427 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_SHIFT 0
24428 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_MASK)
24429 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_SRE_MASK 0x4u
24430 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_SRE_SHIFT 2
24431 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_HYS_MASK 0x8u
24432 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_HYS_SHIFT 3
24433 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PE_MASK 0x10u
24434 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PE_SHIFT 4
24435 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_MASK 0x60u
24436 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_SHIFT 5
24437 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_MASK)
24438 /* SW_PAD_CTL_PAD_LCD_DATA22 Bit Fields */
24439 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_MASK 0x3u
24440 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_SHIFT 0
24441 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_MASK)
24442 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_SRE_MASK 0x4u
24443 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_SRE_SHIFT 2
24444 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_HYS_MASK 0x8u
24445 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_HYS_SHIFT 3
24446 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PE_MASK 0x10u
24447 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PE_SHIFT 4
24448 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_MASK 0x60u
24449 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_SHIFT 5
24450 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_MASK)
24451 /* SW_PAD_CTL_PAD_LCD_DATA23 Bit Fields */
24452 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_MASK 0x3u
24453 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_SHIFT 0
24454 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_MASK)
24455 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_SRE_MASK 0x4u
24456 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_SRE_SHIFT 2
24457 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_HYS_MASK 0x8u
24458 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_HYS_SHIFT 3
24459 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PE_MASK 0x10u
24460 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PE_SHIFT 4
24461 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_MASK 0x60u
24462 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_SHIFT 5
24463 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_MASK)
24464 /* SW_PAD_CTL_PAD_UART1_RX_DATA Bit Fields */
24465 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_MASK 0x3u
24466 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_SHIFT 0
24467 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_MASK)
24468 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_MASK 0x4u
24469 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SHIFT 2
24470 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_MASK 0x8u
24471 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_SHIFT 3
24472 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_MASK 0x10u
24473 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_SHIFT 4
24474 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_MASK 0x60u
24475 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_SHIFT 5
24476 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_MASK)
24477 /* SW_PAD_CTL_PAD_UART1_TX_DATA Bit Fields */
24478 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_MASK 0x3u
24479 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_SHIFT 0
24480 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_MASK)
24481 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_MASK 0x4u
24482 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SHIFT 2
24483 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_MASK 0x8u
24484 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_SHIFT 3
24485 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_MASK 0x10u
24486 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_SHIFT 4
24487 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_MASK 0x60u
24488 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_SHIFT 5
24489 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_MASK)
24490 /* SW_PAD_CTL_PAD_UART2_RX_DATA Bit Fields */
24491 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_MASK 0x3u
24492 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_SHIFT 0
24493 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_MASK)
24494 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_SRE_MASK 0x4u
24495 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_SRE_SHIFT 2
24496 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_MASK 0x8u
24497 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_SHIFT 3
24498 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PE_MASK 0x10u
24499 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PE_SHIFT 4
24500 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_MASK 0x60u
24501 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_SHIFT 5
24502 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_MASK)
24503 /* SW_PAD_CTL_PAD_UART2_TX_DATA Bit Fields */
24504 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_MASK 0x3u
24505 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_SHIFT 0
24506 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_MASK)
24507 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_SRE_MASK 0x4u
24508 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_SRE_SHIFT 2
24509 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_HYS_MASK 0x8u
24510 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_HYS_SHIFT 3
24511 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PE_MASK 0x10u
24512 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PE_SHIFT 4
24513 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_MASK 0x60u
24514 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_SHIFT 5
24515 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_MASK)
24516 /* SW_PAD_CTL_PAD_UART3_RX_DATA Bit Fields */
24517 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_MASK 0x3u
24518 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_SHIFT 0
24519 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_MASK)
24520 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_SRE_MASK 0x4u
24521 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_SRE_SHIFT 2
24522 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_HYS_MASK 0x8u
24523 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_HYS_SHIFT 3
24524 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PE_MASK 0x10u
24525 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PE_SHIFT 4
24526 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_MASK 0x60u
24527 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_SHIFT 5
24528 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_MASK)
24529 /* SW_PAD_CTL_PAD_UART3_TX_DATA Bit Fields */
24530 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_MASK 0x3u
24531 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_SHIFT 0
24532 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_MASK)
24533 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_SRE_MASK 0x4u
24534 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_SRE_SHIFT 2
24535 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_HYS_MASK 0x8u
24536 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_HYS_SHIFT 3
24537 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PE_MASK 0x10u
24538 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PE_SHIFT 4
24539 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_MASK 0x60u
24540 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_SHIFT 5
24541 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_MASK)
24542 /* SW_PAD_CTL_PAD_UART3_RTS_B Bit Fields */
24543 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_MASK 0x3u
24544 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_SHIFT 0
24545 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_MASK)
24546 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_SRE_MASK 0x4u
24547 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_SRE_SHIFT 2
24548 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_HYS_MASK 0x8u
24549 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_HYS_SHIFT 3
24550 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PE_MASK 0x10u
24551 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PE_SHIFT 4
24552 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_MASK 0x60u
24553 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_SHIFT 5
24554 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_MASK)
24555 /* SW_PAD_CTL_PAD_UART3_CTS_B Bit Fields */
24556 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_MASK 0x3u
24557 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_SHIFT 0
24558 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_MASK)
24559 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_SRE_MASK 0x4u
24560 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_SRE_SHIFT 2
24561 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_HYS_MASK 0x8u
24562 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_HYS_SHIFT 3
24563 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PE_MASK 0x10u
24564 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PE_SHIFT 4
24565 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_MASK 0x60u
24566 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_SHIFT 5
24567 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_MASK)
24568 /* SW_PAD_CTL_PAD_I2C1_SCL Bit Fields */
24569 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_MASK  0x3u
24570 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_SHIFT 0
24571 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_MASK)
24572 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_SRE_MASK  0x4u
24573 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_SRE_SHIFT 2
24574 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_HYS_MASK  0x8u
24575 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_HYS_SHIFT 3
24576 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PE_MASK   0x10u
24577 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PE_SHIFT  4
24578 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_MASK   0x60u
24579 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_SHIFT  5
24580 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_MASK)
24581 /* SW_PAD_CTL_PAD_I2C1_SDA Bit Fields */
24582 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_MASK  0x3u
24583 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_SHIFT 0
24584 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_MASK)
24585 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_SRE_MASK  0x4u
24586 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_SRE_SHIFT 2
24587 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_HYS_MASK  0x8u
24588 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_HYS_SHIFT 3
24589 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PE_MASK   0x10u
24590 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PE_SHIFT  4
24591 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_MASK   0x60u
24592 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_SHIFT  5
24593 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_MASK)
24594 /* SW_PAD_CTL_PAD_I2C2_SCL Bit Fields */
24595 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_MASK  0x3u
24596 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_SHIFT 0
24597 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_MASK)
24598 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_SRE_MASK  0x4u
24599 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_SRE_SHIFT 2
24600 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_HYS_MASK  0x8u
24601 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_HYS_SHIFT 3
24602 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PE_MASK   0x10u
24603 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PE_SHIFT  4
24604 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_MASK   0x60u
24605 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_SHIFT  5
24606 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_MASK)
24607 /* SW_PAD_CTL_PAD_I2C2_SDA Bit Fields */
24608 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_MASK  0x3u
24609 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_SHIFT 0
24610 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_MASK)
24611 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_SRE_MASK  0x4u
24612 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_SRE_SHIFT 2
24613 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_HYS_MASK  0x8u
24614 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_HYS_SHIFT 3
24615 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PE_MASK   0x10u
24616 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PE_SHIFT  4
24617 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_MASK   0x60u
24618 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_SHIFT  5
24619 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_MASK)
24620 /* SW_PAD_CTL_PAD_I2C3_SCL Bit Fields */
24621 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_MASK  0x3u
24622 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_SHIFT 0
24623 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_MASK)
24624 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_SRE_MASK  0x4u
24625 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_SRE_SHIFT 2
24626 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_MASK  0x8u
24627 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_SHIFT 3
24628 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_MASK   0x10u
24629 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_SHIFT  4
24630 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_MASK   0x60u
24631 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_SHIFT  5
24632 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_MASK)
24633 /* SW_PAD_CTL_PAD_I2C3_SDA Bit Fields */
24634 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_MASK  0x3u
24635 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_SHIFT 0
24636 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_MASK)
24637 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_SRE_MASK  0x4u
24638 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_SRE_SHIFT 2
24639 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_MASK  0x8u
24640 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_SHIFT 3
24641 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_MASK   0x10u
24642 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_SHIFT  4
24643 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_MASK   0x60u
24644 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_SHIFT  5
24645 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_MASK)
24646 /* SW_PAD_CTL_PAD_I2C4_SCL Bit Fields */
24647 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_MASK  0x3u
24648 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_SHIFT 0
24649 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_MASK)
24650 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_SRE_MASK  0x4u
24651 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_SRE_SHIFT 2
24652 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_HYS_MASK  0x8u
24653 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_HYS_SHIFT 3
24654 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PE_MASK   0x10u
24655 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PE_SHIFT  4
24656 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_MASK   0x60u
24657 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_SHIFT  5
24658 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_MASK)
24659 /* SW_PAD_CTL_PAD_I2C4_SDA Bit Fields */
24660 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_MASK  0x3u
24661 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_SHIFT 0
24662 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_MASK)
24663 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_SRE_MASK  0x4u
24664 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_SRE_SHIFT 2
24665 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_HYS_MASK  0x8u
24666 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_HYS_SHIFT 3
24667 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PE_MASK   0x10u
24668 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PE_SHIFT  4
24669 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_MASK   0x60u
24670 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_SHIFT  5
24671 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_MASK)
24672 /* SW_PAD_CTL_PAD_ECSPI1_SCLK Bit Fields */
24673 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_MASK 0x3u
24674 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_SHIFT 0
24675 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_MASK)
24676 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_MASK 0x4u
24677 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SHIFT 2
24678 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_MASK 0x8u
24679 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_SHIFT 3
24680 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_MASK 0x10u
24681 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_SHIFT 4
24682 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_MASK 0x60u
24683 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_SHIFT 5
24684 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_MASK)
24685 /* SW_PAD_CTL_PAD_ECSPI1_MOSI Bit Fields */
24686 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_MASK 0x3u
24687 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_SHIFT 0
24688 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_MASK)
24689 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_MASK 0x4u
24690 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SHIFT 2
24691 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_MASK 0x8u
24692 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_SHIFT 3
24693 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_MASK 0x10u
24694 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_SHIFT 4
24695 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_MASK 0x60u
24696 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_SHIFT 5
24697 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_MASK)
24698 /* SW_PAD_CTL_PAD_ECSPI1_MISO Bit Fields */
24699 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_MASK 0x3u
24700 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_SHIFT 0
24701 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_MASK)
24702 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_SRE_MASK 0x4u
24703 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_SRE_SHIFT 2
24704 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_MASK 0x8u
24705 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_SHIFT 3
24706 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PE_MASK 0x10u
24707 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PE_SHIFT 4
24708 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_MASK 0x60u
24709 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_SHIFT 5
24710 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_MASK)
24711 /* SW_PAD_CTL_PAD_ECSPI1_SS0 Bit Fields */
24712 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_MASK 0x3u
24713 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_SHIFT 0
24714 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_MASK)
24715 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_SRE_MASK 0x4u
24716 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_SRE_SHIFT 2
24717 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_MASK 0x8u
24718 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_SHIFT 3
24719 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_MASK 0x10u
24720 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_SHIFT 4
24721 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_MASK 0x60u
24722 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_SHIFT 5
24723 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_MASK)
24724 /* SW_PAD_CTL_PAD_ECSPI2_SCLK Bit Fields */
24725 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_MASK 0x3u
24726 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_SHIFT 0
24727 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_MASK)
24728 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_SRE_MASK 0x4u
24729 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_SRE_SHIFT 2
24730 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_HYS_MASK 0x8u
24731 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_HYS_SHIFT 3
24732 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PE_MASK 0x10u
24733 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PE_SHIFT 4
24734 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_MASK 0x60u
24735 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_SHIFT 5
24736 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_MASK)
24737 /* SW_PAD_CTL_PAD_ECSPI2_MOSI Bit Fields */
24738 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_MASK 0x3u
24739 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_SHIFT 0
24740 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_MASK)
24741 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_SRE_MASK 0x4u
24742 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_SRE_SHIFT 2
24743 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_HYS_MASK 0x8u
24744 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_HYS_SHIFT 3
24745 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PE_MASK 0x10u
24746 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PE_SHIFT 4
24747 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_MASK 0x60u
24748 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_SHIFT 5
24749 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_MASK)
24750 /* SW_PAD_CTL_PAD_ECSPI2_MISO Bit Fields */
24751 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_MASK 0x3u
24752 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_SHIFT 0
24753 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_MASK)
24754 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_SRE_MASK 0x4u
24755 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_SRE_SHIFT 2
24756 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_HYS_MASK 0x8u
24757 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_HYS_SHIFT 3
24758 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PE_MASK 0x10u
24759 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PE_SHIFT 4
24760 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_MASK 0x60u
24761 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_SHIFT 5
24762 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_MASK)
24763 /* SW_PAD_CTL_PAD_ECSPI2_SS0 Bit Fields */
24764 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_MASK 0x3u
24765 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_SHIFT 0
24766 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_MASK)
24767 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_SRE_MASK 0x4u
24768 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_SRE_SHIFT 2
24769 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_HYS_MASK 0x8u
24770 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_HYS_SHIFT 3
24771 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PE_MASK 0x10u
24772 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PE_SHIFT 4
24773 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_MASK 0x60u
24774 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_SHIFT 5
24775 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_MASK)
24776 /* SW_PAD_CTL_PAD_SD1_CD_B Bit Fields */
24777 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_MASK  0x3u
24778 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_SHIFT 0
24779 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_MASK)
24780 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_SRE_MASK  0x4u
24781 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_SRE_SHIFT 2
24782 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_HYS_MASK  0x8u
24783 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_HYS_SHIFT 3
24784 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PE_MASK   0x10u
24785 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PE_SHIFT  4
24786 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_MASK   0x60u
24787 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_SHIFT  5
24788 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_MASK)
24789 /* SW_PAD_CTL_PAD_SD1_WP Bit Fields */
24790 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_MASK    0x3u
24791 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_SHIFT   0
24792 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_MASK)
24793 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_SRE_MASK    0x4u
24794 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_SRE_SHIFT   2
24795 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_HYS_MASK    0x8u
24796 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_HYS_SHIFT   3
24797 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PE_MASK     0x10u
24798 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PE_SHIFT    4
24799 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_MASK     0x60u
24800 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_SHIFT    5
24801 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_MASK)
24802 /* SW_PAD_CTL_PAD_SD1_RESET_B Bit Fields */
24803 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_MASK 0x3u
24804 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_SHIFT 0
24805 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_MASK)
24806 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_SRE_MASK 0x4u
24807 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_SRE_SHIFT 2
24808 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_HYS_MASK 0x8u
24809 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_HYS_SHIFT 3
24810 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PE_MASK 0x10u
24811 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PE_SHIFT 4
24812 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_MASK 0x60u
24813 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_SHIFT 5
24814 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_MASK)
24815 /* SW_PAD_CTL_PAD_SD1_CLK Bit Fields */
24816 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK   0x3u
24817 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT  0
24818 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK)
24819 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_MASK   0x4u
24820 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_SHIFT  2
24821 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_MASK   0x8u
24822 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_SHIFT  3
24823 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PE_MASK    0x10u
24824 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PE_SHIFT   4
24825 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_MASK    0x60u
24826 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_SHIFT   5
24827 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_MASK)
24828 /* SW_PAD_CTL_PAD_SD1_CMD Bit Fields */
24829 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK   0x3u
24830 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT  0
24831 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK)
24832 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_MASK   0x4u
24833 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_SHIFT  2
24834 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_MASK   0x8u
24835 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_SHIFT  3
24836 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PE_MASK    0x10u
24837 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PE_SHIFT   4
24838 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_MASK    0x60u
24839 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_SHIFT   5
24840 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_MASK)
24841 /* SW_PAD_CTL_PAD_SD1_DATA0 Bit Fields */
24842 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK 0x3u
24843 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT 0
24844 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK)
24845 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_MASK 0x4u
24846 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_SHIFT 2
24847 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_MASK 0x8u
24848 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_SHIFT 3
24849 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PE_MASK  0x10u
24850 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PE_SHIFT 4
24851 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_MASK  0x60u
24852 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_SHIFT 5
24853 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_MASK)
24854 /* SW_PAD_CTL_PAD_SD1_DATA1 Bit Fields */
24855 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK 0x3u
24856 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT 0
24857 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK)
24858 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_MASK 0x4u
24859 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_SHIFT 2
24860 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_MASK 0x8u
24861 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_SHIFT 3
24862 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PE_MASK  0x10u
24863 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PE_SHIFT 4
24864 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_MASK  0x60u
24865 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_SHIFT 5
24866 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_MASK)
24867 /* SW_PAD_CTL_PAD_SD1_DATA2 Bit Fields */
24868 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK 0x3u
24869 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT 0
24870 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK)
24871 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_MASK 0x4u
24872 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_SHIFT 2
24873 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_MASK 0x8u
24874 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_SHIFT 3
24875 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PE_MASK  0x10u
24876 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PE_SHIFT 4
24877 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_MASK  0x60u
24878 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_SHIFT 5
24879 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_MASK)
24880 /* SW_PAD_CTL_PAD_SD1_DATA3 Bit Fields */
24881 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK 0x3u
24882 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT 0
24883 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK)
24884 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_MASK 0x4u
24885 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_SHIFT 2
24886 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_MASK 0x8u
24887 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_SHIFT 3
24888 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PE_MASK  0x10u
24889 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PE_SHIFT 4
24890 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_MASK  0x60u
24891 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_SHIFT 5
24892 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_MASK)
24893 /* SW_PAD_CTL_PAD_SD2_CD_B Bit Fields */
24894 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_MASK  0x3u
24895 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_SHIFT 0
24896 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_MASK)
24897 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_SRE_MASK  0x4u
24898 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_SRE_SHIFT 2
24899 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_HYS_MASK  0x8u
24900 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_HYS_SHIFT 3
24901 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PE_MASK   0x10u
24902 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PE_SHIFT  4
24903 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_MASK   0x60u
24904 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_SHIFT  5
24905 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_MASK)
24906 /* SW_PAD_CTL_PAD_SD2_WP Bit Fields */
24907 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_MASK    0x3u
24908 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_SHIFT   0
24909 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_MASK)
24910 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_SRE_MASK    0x4u
24911 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_SRE_SHIFT   2
24912 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_HYS_MASK    0x8u
24913 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_HYS_SHIFT   3
24914 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PE_MASK     0x10u
24915 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PE_SHIFT    4
24916 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_MASK     0x60u
24917 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_SHIFT    5
24918 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_MASK)
24919 /* SW_PAD_CTL_PAD_SD2_RESET_B Bit Fields */
24920 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_MASK 0x3u
24921 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_SHIFT 0
24922 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_MASK)
24923 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_SRE_MASK 0x4u
24924 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_SRE_SHIFT 2
24925 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_HYS_MASK 0x8u
24926 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_HYS_SHIFT 3
24927 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PE_MASK 0x10u
24928 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PE_SHIFT 4
24929 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_MASK 0x60u
24930 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_SHIFT 5
24931 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_MASK)
24932 /* SW_PAD_CTL_PAD_SD2_CLK Bit Fields */
24933 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK   0x3u
24934 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT  0
24935 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK)
24936 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_MASK   0x4u
24937 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_SHIFT  2
24938 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_MASK   0x8u
24939 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_SHIFT  3
24940 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PE_MASK    0x10u
24941 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PE_SHIFT   4
24942 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_MASK    0x60u
24943 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_SHIFT   5
24944 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_MASK)
24945 /* SW_PAD_CTL_PAD_SD2_CMD Bit Fields */
24946 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK   0x3u
24947 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT  0
24948 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK)
24949 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_MASK   0x4u
24950 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_SHIFT  2
24951 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_MASK   0x8u
24952 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_SHIFT  3
24953 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PE_MASK    0x10u
24954 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PE_SHIFT   4
24955 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_MASK    0x60u
24956 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_SHIFT   5
24957 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_MASK)
24958 /* SW_PAD_CTL_PAD_SD2_DATA0 Bit Fields */
24959 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK 0x3u
24960 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT 0
24961 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK)
24962 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_MASK 0x4u
24963 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_SHIFT 2
24964 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_MASK 0x8u
24965 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_SHIFT 3
24966 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PE_MASK  0x10u
24967 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PE_SHIFT 4
24968 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_MASK  0x60u
24969 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_SHIFT 5
24970 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_MASK)
24971 /* SW_PAD_CTL_PAD_SD2_DATA1 Bit Fields */
24972 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK 0x3u
24973 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT 0
24974 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK)
24975 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_MASK 0x4u
24976 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_SHIFT 2
24977 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_MASK 0x8u
24978 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_SHIFT 3
24979 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PE_MASK  0x10u
24980 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PE_SHIFT 4
24981 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_MASK  0x60u
24982 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_SHIFT 5
24983 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_MASK)
24984 /* SW_PAD_CTL_PAD_SD2_DATA2 Bit Fields */
24985 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK 0x3u
24986 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT 0
24987 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK)
24988 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_MASK 0x4u
24989 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_SHIFT 2
24990 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_MASK 0x8u
24991 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_SHIFT 3
24992 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PE_MASK  0x10u
24993 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PE_SHIFT 4
24994 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_MASK  0x60u
24995 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_SHIFT 5
24996 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_MASK)
24997 /* SW_PAD_CTL_PAD_SD2_DATA3 Bit Fields */
24998 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK 0x3u
24999 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT 0
25000 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK)
25001 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_MASK 0x4u
25002 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_SHIFT 2
25003 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_MASK 0x8u
25004 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_SHIFT 3
25005 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PE_MASK  0x10u
25006 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PE_SHIFT 4
25007 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_MASK  0x60u
25008 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_SHIFT 5
25009 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_MASK)
25010 /* SW_PAD_CTL_PAD_SD3_CLK Bit Fields */
25011 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK   0x3u
25012 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT  0
25013 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK)
25014 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_MASK   0x4u
25015 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_SHIFT  2
25016 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_MASK   0x8u
25017 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_SHIFT  3
25018 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PE_MASK    0x10u
25019 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PE_SHIFT   4
25020 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_MASK    0x60u
25021 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_SHIFT   5
25022 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_MASK)
25023 /* SW_PAD_CTL_PAD_SD3_CMD Bit Fields */
25024 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK   0x3u
25025 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT  0
25026 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK)
25027 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_MASK   0x4u
25028 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_SHIFT  2
25029 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_MASK   0x8u
25030 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_SHIFT  3
25031 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PE_MASK    0x10u
25032 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PE_SHIFT   4
25033 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_MASK    0x60u
25034 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_SHIFT   5
25035 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_MASK)
25036 /* SW_PAD_CTL_PAD_SD3_DATA0 Bit Fields */
25037 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK 0x3u
25038 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT 0
25039 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK)
25040 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_MASK 0x4u
25041 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_SHIFT 2
25042 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_MASK 0x8u
25043 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_SHIFT 3
25044 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PE_MASK  0x10u
25045 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PE_SHIFT 4
25046 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_MASK  0x60u
25047 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_SHIFT 5
25048 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_MASK)
25049 /* SW_PAD_CTL_PAD_SD3_DATA1 Bit Fields */
25050 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK 0x3u
25051 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT 0
25052 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK)
25053 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_MASK 0x4u
25054 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_SHIFT 2
25055 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_MASK 0x8u
25056 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_SHIFT 3
25057 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PE_MASK  0x10u
25058 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PE_SHIFT 4
25059 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_MASK  0x60u
25060 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_SHIFT 5
25061 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_MASK)
25062 /* SW_PAD_CTL_PAD_SD3_DATA2 Bit Fields */
25063 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK 0x3u
25064 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT 0
25065 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK)
25066 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_MASK 0x4u
25067 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_SHIFT 2
25068 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_MASK 0x8u
25069 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_SHIFT 3
25070 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PE_MASK  0x10u
25071 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PE_SHIFT 4
25072 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_MASK  0x60u
25073 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_SHIFT 5
25074 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_MASK)
25075 /* SW_PAD_CTL_PAD_SD3_DATA3 Bit Fields */
25076 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK 0x3u
25077 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT 0
25078 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK)
25079 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_MASK 0x4u
25080 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_SHIFT 2
25081 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_MASK 0x8u
25082 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_SHIFT 3
25083 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PE_MASK  0x10u
25084 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PE_SHIFT 4
25085 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_MASK  0x60u
25086 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_SHIFT 5
25087 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_MASK)
25088 /* SW_PAD_CTL_PAD_SD3_DATA4 Bit Fields */
25089 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK 0x3u
25090 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT 0
25091 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK)
25092 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_MASK 0x4u
25093 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_SHIFT 2
25094 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_MASK 0x8u
25095 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_SHIFT 3
25096 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PE_MASK  0x10u
25097 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PE_SHIFT 4
25098 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_MASK  0x60u
25099 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_SHIFT 5
25100 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_MASK)
25101 /* SW_PAD_CTL_PAD_SD3_DATA5 Bit Fields */
25102 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK 0x3u
25103 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT 0
25104 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK)
25105 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_MASK 0x4u
25106 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_SHIFT 2
25107 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_MASK 0x8u
25108 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_SHIFT 3
25109 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PE_MASK  0x10u
25110 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PE_SHIFT 4
25111 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_MASK  0x60u
25112 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_SHIFT 5
25113 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_MASK)
25114 /* SW_PAD_CTL_PAD_SD3_DATA6 Bit Fields */
25115 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK 0x3u
25116 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT 0
25117 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK)
25118 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_MASK 0x4u
25119 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_SHIFT 2
25120 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_MASK 0x8u
25121 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_SHIFT 3
25122 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PE_MASK  0x10u
25123 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PE_SHIFT 4
25124 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_MASK  0x60u
25125 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_SHIFT 5
25126 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_MASK)
25127 /* SW_PAD_CTL_PAD_SD3_DATA7 Bit Fields */
25128 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK 0x3u
25129 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT 0
25130 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK)
25131 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_MASK 0x4u
25132 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_SHIFT 2
25133 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_MASK 0x8u
25134 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_SHIFT 3
25135 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PE_MASK  0x10u
25136 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PE_SHIFT 4
25137 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_MASK  0x60u
25138 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_SHIFT 5
25139 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_MASK)
25140 /* SW_PAD_CTL_PAD_SD3_STROBE Bit Fields */
25141 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_MASK 0x3u
25142 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_SHIFT 0
25143 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_MASK)
25144 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_SRE_MASK 0x4u
25145 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_SRE_SHIFT 2
25146 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_HYS_MASK 0x8u
25147 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_HYS_SHIFT 3
25148 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PE_MASK 0x10u
25149 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PE_SHIFT 4
25150 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_MASK 0x60u
25151 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_SHIFT 5
25152 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_MASK)
25153 /* SW_PAD_CTL_PAD_SD3_RESET_B Bit Fields */
25154 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_MASK 0x3u
25155 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_SHIFT 0
25156 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_MASK)
25157 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_SRE_MASK 0x4u
25158 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_SRE_SHIFT 2
25159 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_HYS_MASK 0x8u
25160 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_HYS_SHIFT 3
25161 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PE_MASK 0x10u
25162 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PE_SHIFT 4
25163 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_MASK 0x60u
25164 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_SHIFT 5
25165 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_MASK)
25166 /* SW_PAD_CTL_PAD_SAI1_RX_DATA Bit Fields */
25167 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_MASK 0x3u
25168 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_SHIFT 0
25169 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_MASK)
25170 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_SRE_MASK 0x4u
25171 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_SRE_SHIFT 2
25172 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_HYS_MASK 0x8u
25173 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_HYS_SHIFT 3
25174 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PE_MASK 0x10u
25175 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PE_SHIFT 4
25176 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_MASK 0x60u
25177 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_SHIFT 5
25178 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_MASK)
25179 /* SW_PAD_CTL_PAD_SAI1_TX_BCLK Bit Fields */
25180 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_MASK 0x3u
25181 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_SHIFT 0
25182 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_MASK)
25183 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_SRE_MASK 0x4u
25184 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_SRE_SHIFT 2
25185 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_HYS_MASK 0x8u
25186 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_HYS_SHIFT 3
25187 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PE_MASK 0x10u
25188 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PE_SHIFT 4
25189 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_MASK 0x60u
25190 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_SHIFT 5
25191 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_MASK)
25192 /* SW_PAD_CTL_PAD_SAI1_TX_SYNC Bit Fields */
25193 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_MASK 0x3u
25194 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_SHIFT 0
25195 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_MASK)
25196 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_SRE_MASK 0x4u
25197 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_SRE_SHIFT 2
25198 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_HYS_MASK 0x8u
25199 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_HYS_SHIFT 3
25200 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PE_MASK 0x10u
25201 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PE_SHIFT 4
25202 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_MASK 0x60u
25203 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_SHIFT 5
25204 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_MASK)
25205 /* SW_PAD_CTL_PAD_SAI1_TX_DATA Bit Fields */
25206 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_MASK 0x3u
25207 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_SHIFT 0
25208 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_MASK)
25209 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_SRE_MASK 0x4u
25210 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_SRE_SHIFT 2
25211 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_HYS_MASK 0x8u
25212 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_HYS_SHIFT 3
25213 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PE_MASK 0x10u
25214 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PE_SHIFT 4
25215 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_MASK 0x60u
25216 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_SHIFT 5
25217 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_MASK)
25218 /* SW_PAD_CTL_PAD_SAI1_RX_SYNC Bit Fields */
25219 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_MASK 0x3u
25220 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_SHIFT 0
25221 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_MASK)
25222 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_SRE_MASK 0x4u
25223 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_SRE_SHIFT 2
25224 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_HYS_MASK 0x8u
25225 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_HYS_SHIFT 3
25226 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PE_MASK 0x10u
25227 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PE_SHIFT 4
25228 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_MASK 0x60u
25229 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_SHIFT 5
25230 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_MASK)
25231 /* SW_PAD_CTL_PAD_SAI1_RX_BCLK Bit Fields */
25232 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_MASK 0x3u
25233 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_SHIFT 0
25234 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_MASK)
25235 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_SRE_MASK 0x4u
25236 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_SRE_SHIFT 2
25237 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_HYS_MASK 0x8u
25238 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_HYS_SHIFT 3
25239 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PE_MASK 0x10u
25240 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PE_SHIFT 4
25241 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_MASK 0x60u
25242 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_SHIFT 5
25243 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_MASK)
25244 /* SW_PAD_CTL_PAD_SAI1_MCLK Bit Fields */
25245 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_MASK 0x3u
25246 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_SHIFT 0
25247 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_MASK)
25248 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_SRE_MASK 0x4u
25249 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_SRE_SHIFT 2
25250 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_HYS_MASK 0x8u
25251 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_HYS_SHIFT 3
25252 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PE_MASK  0x10u
25253 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PE_SHIFT 4
25254 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_MASK  0x60u
25255 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_SHIFT 5
25256 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_MASK)
25257 /* SW_PAD_CTL_PAD_SAI2_TX_SYNC Bit Fields */
25258 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_MASK 0x3u
25259 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_SHIFT 0
25260 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_MASK)
25261 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_SRE_MASK 0x4u
25262 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_SRE_SHIFT 2
25263 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_HYS_MASK 0x8u
25264 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_HYS_SHIFT 3
25265 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PE_MASK 0x10u
25266 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PE_SHIFT 4
25267 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_MASK 0x60u
25268 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_SHIFT 5
25269 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_MASK)
25270 /* SW_PAD_CTL_PAD_SAI2_TX_BCLK Bit Fields */
25271 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_MASK 0x3u
25272 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_SHIFT 0
25273 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_MASK)
25274 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_SRE_MASK 0x4u
25275 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_SRE_SHIFT 2
25276 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_HYS_MASK 0x8u
25277 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_HYS_SHIFT 3
25278 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PE_MASK 0x10u
25279 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PE_SHIFT 4
25280 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_MASK 0x60u
25281 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_SHIFT 5
25282 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_MASK)
25283 /* SW_PAD_CTL_PAD_SAI2_RX_DATA Bit Fields */
25284 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_MASK 0x3u
25285 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_SHIFT 0
25286 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_MASK)
25287 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_SRE_MASK 0x4u
25288 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_SRE_SHIFT 2
25289 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_HYS_MASK 0x8u
25290 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_HYS_SHIFT 3
25291 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PE_MASK 0x10u
25292 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PE_SHIFT 4
25293 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_MASK 0x60u
25294 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_SHIFT 5
25295 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_MASK)
25296 /* SW_PAD_CTL_PAD_SAI2_TX_DATA Bit Fields */
25297 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_MASK 0x3u
25298 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_SHIFT 0
25299 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_MASK)
25300 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_SRE_MASK 0x4u
25301 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_SRE_SHIFT 2
25302 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_HYS_MASK 0x8u
25303 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_HYS_SHIFT 3
25304 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PE_MASK 0x10u
25305 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PE_SHIFT 4
25306 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_MASK 0x60u
25307 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_SHIFT 5
25308 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_MASK)
25309 /* SW_PAD_CTL_PAD_ENET1_RGMII_RD0 Bit Fields */
25310 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_MASK 0x3u
25311 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_SHIFT 0
25312 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_MASK)
25313 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_SRE_MASK 0x4u
25314 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_SRE_SHIFT 2
25315 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_HYS_MASK 0x8u
25316 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_HYS_SHIFT 3
25317 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PE_MASK 0x10u
25318 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PE_SHIFT 4
25319 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_MASK 0x60u
25320 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_SHIFT 5
25321 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_MASK)
25322 /* SW_PAD_CTL_PAD_ENET1_RGMII_RD1 Bit Fields */
25323 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_MASK 0x3u
25324 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_SHIFT 0
25325 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_MASK)
25326 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_SRE_MASK 0x4u
25327 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_SRE_SHIFT 2
25328 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_HYS_MASK 0x8u
25329 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_HYS_SHIFT 3
25330 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PE_MASK 0x10u
25331 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PE_SHIFT 4
25332 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_MASK 0x60u
25333 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_SHIFT 5
25334 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_MASK)
25335 /* SW_PAD_CTL_PAD_ENET1_RGMII_RD2 Bit Fields */
25336 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_MASK 0x3u
25337 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_SHIFT 0
25338 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_MASK)
25339 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_SRE_MASK 0x4u
25340 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_SRE_SHIFT 2
25341 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_HYS_MASK 0x8u
25342 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_HYS_SHIFT 3
25343 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PE_MASK 0x10u
25344 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PE_SHIFT 4
25345 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_MASK 0x60u
25346 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_SHIFT 5
25347 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_MASK)
25348 /* SW_PAD_CTL_PAD_ENET1_RGMII_RD3 Bit Fields */
25349 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_MASK 0x3u
25350 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_SHIFT 0
25351 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_MASK)
25352 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_SRE_MASK 0x4u
25353 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_SRE_SHIFT 2
25354 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_MASK 0x8u
25355 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_SHIFT 3
25356 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_MASK 0x10u
25357 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_SHIFT 4
25358 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_MASK 0x60u
25359 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_SHIFT 5
25360 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_MASK)
25361 /* SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL Bit Fields */
25362 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_MASK 0x3u
25363 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_SHIFT 0
25364 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_MASK)
25365 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_SRE_MASK 0x4u
25366 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_SRE_SHIFT 2
25367 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_HYS_MASK 0x8u
25368 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_HYS_SHIFT 3
25369 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PE_MASK 0x10u
25370 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PE_SHIFT 4
25371 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_MASK 0x60u
25372 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_SHIFT 5
25373 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_MASK)
25374 /* SW_PAD_CTL_PAD_ENET1_RGMII_RXC Bit Fields */
25375 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_MASK 0x3u
25376 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_SHIFT 0
25377 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_MASK)
25378 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_SRE_MASK 0x4u
25379 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_SRE_SHIFT 2
25380 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_HYS_MASK 0x8u
25381 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_HYS_SHIFT 3
25382 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PE_MASK 0x10u
25383 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PE_SHIFT 4
25384 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_MASK 0x60u
25385 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_SHIFT 5
25386 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_MASK)
25387 /* SW_PAD_CTL_PAD_ENET1_RGMII_TD0 Bit Fields */
25388 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_MASK 0x3u
25389 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_SHIFT 0
25390 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_MASK)
25391 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_SRE_MASK 0x4u
25392 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_SRE_SHIFT 2
25393 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_HYS_MASK 0x8u
25394 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_HYS_SHIFT 3
25395 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PE_MASK 0x10u
25396 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PE_SHIFT 4
25397 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_MASK 0x60u
25398 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_SHIFT 5
25399 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_MASK)
25400 /* SW_PAD_CTL_PAD_ENET1_RGMII_TD1 Bit Fields */
25401 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_MASK 0x3u
25402 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_SHIFT 0
25403 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_MASK)
25404 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_SRE_MASK 0x4u
25405 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_SRE_SHIFT 2
25406 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_HYS_MASK 0x8u
25407 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_HYS_SHIFT 3
25408 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PE_MASK 0x10u
25409 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PE_SHIFT 4
25410 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_MASK 0x60u
25411 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_SHIFT 5
25412 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_MASK)
25413 /* SW_PAD_CTL_PAD_ENET1_RGMII_TD2 Bit Fields */
25414 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_MASK 0x3u
25415 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_SHIFT 0
25416 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_MASK)
25417 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_SRE_MASK 0x4u
25418 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_SRE_SHIFT 2
25419 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_HYS_MASK 0x8u
25420 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_HYS_SHIFT 3
25421 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PE_MASK 0x10u
25422 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PE_SHIFT 4
25423 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_MASK 0x60u
25424 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_SHIFT 5
25425 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_MASK)
25426 /* SW_PAD_CTL_PAD_ENET1_RGMII_TD3 Bit Fields */
25427 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_MASK 0x3u
25428 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_SHIFT 0
25429 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_MASK)
25430 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_SRE_MASK 0x4u
25431 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_SRE_SHIFT 2
25432 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_MASK 0x8u
25433 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_SHIFT 3
25434 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PE_MASK 0x10u
25435 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PE_SHIFT 4
25436 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_MASK 0x60u
25437 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_SHIFT 5
25438 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_MASK)
25439 /* SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL Bit Fields */
25440 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_MASK 0x3u
25441 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_SHIFT 0
25442 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_MASK)
25443 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_SRE_MASK 0x4u
25444 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_SRE_SHIFT 2
25445 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_HYS_MASK 0x8u
25446 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_HYS_SHIFT 3
25447 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PE_MASK 0x10u
25448 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PE_SHIFT 4
25449 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_MASK 0x60u
25450 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_SHIFT 5
25451 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_MASK)
25452 /* SW_PAD_CTL_PAD_ENET1_RGMII_TXC Bit Fields */
25453 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_MASK 0x3u
25454 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_SHIFT 0
25455 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_MASK)
25456 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_SRE_MASK 0x4u
25457 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_SRE_SHIFT 2
25458 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_HYS_MASK 0x8u
25459 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_HYS_SHIFT 3
25460 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PE_MASK 0x10u
25461 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PE_SHIFT 4
25462 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_MASK 0x60u
25463 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_SHIFT 5
25464 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_MASK)
25465 /* SW_PAD_CTL_PAD_ENET1_TX_CLK Bit Fields */
25466 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK 0x3u
25467 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT 0
25468 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK)
25469 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_MASK 0x4u
25470 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_SHIFT 2
25471 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_MASK 0x8u
25472 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_SHIFT 3
25473 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PE_MASK 0x10u
25474 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PE_SHIFT 4
25475 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_MASK 0x60u
25476 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_SHIFT 5
25477 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_MASK)
25478 /* SW_PAD_CTL_PAD_ENET1_RX_CLK Bit Fields */
25479 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK 0x3u
25480 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT 0
25481 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK)
25482 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_MASK 0x4u
25483 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_SHIFT 2
25484 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_MASK 0x8u
25485 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_SHIFT 3
25486 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PE_MASK 0x10u
25487 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PE_SHIFT 4
25488 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_MASK 0x60u
25489 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_SHIFT 5
25490 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_MASK)
25491 /* SW_PAD_CTL_PAD_ENET1_CRS Bit Fields */
25492 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK 0x3u
25493 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT 0
25494 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK)
25495 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_MASK 0x4u
25496 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_SHIFT 2
25497 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_MASK 0x8u
25498 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_SHIFT 3
25499 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PE_MASK  0x10u
25500 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PE_SHIFT 4
25501 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_MASK  0x60u
25502 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_SHIFT 5
25503 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_MASK)
25504 /* SW_PAD_CTL_PAD_ENET1_COL Bit Fields */
25505 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK 0x3u
25506 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT 0
25507 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK)
25508 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_MASK 0x4u
25509 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_SHIFT 2
25510 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_MASK 0x8u
25511 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_SHIFT 3
25512 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PE_MASK  0x10u
25513 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PE_SHIFT 4
25514 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_MASK  0x60u
25515 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_SHIFT 5
25516 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_MASK)
25517 /* FLEXCAN1_RX_SELECT_INPUT Bit Fields */
25518 #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_MASK 0x7u
25519 #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_SHIFT 0
25520 #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_MASK)
25521 /* FLEXCAN2_RX_SELECT_INPUT Bit Fields */
25522 #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_MASK 0x7u
25523 #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_SHIFT 0
25524 #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_MASK)
25525 /* CCM_EXT_CLK_1_SELECT_INPUT Bit Fields */
25526 #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_MASK 0x3u
25527 #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_SHIFT 0
25528 #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_MASK)
25529 /* CCM_EXT_CLK_2_SELECT_INPUT Bit Fields */
25530 #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_MASK 0x3u
25531 #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_SHIFT 0
25532 #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_MASK)
25533 /* CCM_EXT_CLK_3_SELECT_INPUT Bit Fields */
25534 #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_MASK 0x3u
25535 #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_SHIFT 0
25536 #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_MASK)
25537 /* CCM_EXT_CLK_4_SELECT_INPUT Bit Fields */
25538 #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_MASK 0x3u
25539 #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_SHIFT 0
25540 #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_MASK)
25541 /* CCM_PMIC_READY_SELECT_INPUT Bit Fields */
25542 #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_MASK 0x3u
25543 #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_SHIFT 0
25544 #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_MASK)
25545 /* CSI_DATA2_SELECT_INPUT Bit Fields */
25546 #define IOMUXC_CSI_DATA2_SELECT_INPUT_DAISY_MASK 0x1u
25547 #define IOMUXC_CSI_DATA2_SELECT_INPUT_DAISY_SHIFT 0
25548 /* CSI_DATA3_SELECT_INPUT Bit Fields */
25549 #define IOMUXC_CSI_DATA3_SELECT_INPUT_DAISY_MASK 0x1u
25550 #define IOMUXC_CSI_DATA3_SELECT_INPUT_DAISY_SHIFT 0
25551 /* CSI_DATA4_SELECT_INPUT Bit Fields */
25552 #define IOMUXC_CSI_DATA4_SELECT_INPUT_DAISY_MASK 0x1u
25553 #define IOMUXC_CSI_DATA4_SELECT_INPUT_DAISY_SHIFT 0
25554 /* CSI_DATA5_SELECT_INPUT Bit Fields */
25555 #define IOMUXC_CSI_DATA5_SELECT_INPUT_DAISY_MASK 0x1u
25556 #define IOMUXC_CSI_DATA5_SELECT_INPUT_DAISY_SHIFT 0
25557 /* CSI_DATA6_SELECT_INPUT Bit Fields */
25558 #define IOMUXC_CSI_DATA6_SELECT_INPUT_DAISY_MASK 0x1u
25559 #define IOMUXC_CSI_DATA6_SELECT_INPUT_DAISY_SHIFT 0
25560 /* CSI_DATA7_SELECT_INPUT Bit Fields */
25561 #define IOMUXC_CSI_DATA7_SELECT_INPUT_DAISY_MASK 0x1u
25562 #define IOMUXC_CSI_DATA7_SELECT_INPUT_DAISY_SHIFT 0
25563 /* CSI_DATA8_SELECT_INPUT Bit Fields */
25564 #define IOMUXC_CSI_DATA8_SELECT_INPUT_DAISY_MASK 0x1u
25565 #define IOMUXC_CSI_DATA8_SELECT_INPUT_DAISY_SHIFT 0
25566 /* CSI_DATA9_SELECT_INPUT Bit Fields */
25567 #define IOMUXC_CSI_DATA9_SELECT_INPUT_DAISY_MASK 0x1u
25568 #define IOMUXC_CSI_DATA9_SELECT_INPUT_DAISY_SHIFT 0
25569 /* CSI_HSYNC_SELECT_INPUT Bit Fields */
25570 #define IOMUXC_CSI_HSYNC_SELECT_INPUT_DAISY_MASK 0x1u
25571 #define IOMUXC_CSI_HSYNC_SELECT_INPUT_DAISY_SHIFT 0
25572 /* CSI_PIXCLK_SELECT_INPUT Bit Fields */
25573 #define IOMUXC_CSI_PIXCLK_SELECT_INPUT_DAISY_MASK 0x1u
25574 #define IOMUXC_CSI_PIXCLK_SELECT_INPUT_DAISY_SHIFT 0
25575 /* CSI_VSYNC_SELECT_INPUT Bit Fields */
25576 #define IOMUXC_CSI_VSYNC_SELECT_INPUT_DAISY_MASK 0x1u
25577 #define IOMUXC_CSI_VSYNC_SELECT_INPUT_DAISY_SHIFT 0
25578 /* ECSPI1_SCLK_SELECT_INPUT Bit Fields */
25579 #define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_DAISY_MASK 0x1u
25580 #define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_DAISY_SHIFT 0
25581 /* ECSPI1_MISO_SELECT_INPUT Bit Fields */
25582 #define IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_MASK 0x1u
25583 #define IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_SHIFT 0
25584 /* ECSPI1_MOSI_SELECT_INPUT Bit Fields */
25585 #define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
25586 #define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_SHIFT 0
25587 /* ECSPI1_SS0_B_SELECT_INPUT Bit Fields */
25588 #define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_DAISY_MASK 0x1u
25589 #define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_DAISY_SHIFT 0
25590 /* ECSPI2_SCLK_SELECT_INPUT Bit Fields */
25591 #define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_DAISY_MASK 0x1u
25592 #define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_DAISY_SHIFT 0
25593 /* ECSPI2_MISO_SELECT_INPUT Bit Fields */
25594 #define IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY_MASK 0x1u
25595 #define IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY_SHIFT 0
25596 /* ECSPI2_MOSI_SELECT_INPUT Bit Fields */
25597 #define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
25598 #define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY_SHIFT 0
25599 /* ECSPI2_SS0_B_SELECT_INPUT Bit Fields */
25600 #define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_DAISY_MASK 0x1u
25601 #define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_DAISY_SHIFT 0
25602 /* ECSPI3_SCLK_SELECT_INPUT Bit Fields */
25603 #define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_DAISY_MASK 0x1u
25604 #define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_DAISY_SHIFT 0
25605 /* ECSPI3_MISO_SELECT_INPUT Bit Fields */
25606 #define IOMUXC_ECSPI3_MISO_SELECT_INPUT_DAISY_MASK 0x1u
25607 #define IOMUXC_ECSPI3_MISO_SELECT_INPUT_DAISY_SHIFT 0
25608 /* ECSPI3_MOSI_SELECT_INPUT Bit Fields */
25609 #define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
25610 #define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_DAISY_SHIFT 0
25611 /* ECSPI3_SS0_B_SELECT_INPUT Bit Fields */
25612 #define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_DAISY_MASK 0x1u
25613 #define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_DAISY_SHIFT 0
25614 /* ECSPI4_SCLK_SELECT_INPUT Bit Fields */
25615 #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_MASK 0x3u
25616 #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_SHIFT 0
25617 #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_MASK)
25618 /* ECSPI4_MISO_SELECT_INPUT Bit Fields */
25619 #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_MASK 0x3u
25620 #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_SHIFT 0
25621 #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_MASK)
25622 /* ECSPI4_MOSI_SELECT_INPUT Bit Fields */
25623 #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_MASK 0x3u
25624 #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_SHIFT 0
25625 #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_MASK)
25626 /* ECSPI4_SS0_B_SELECT_INPUT Bit Fields */
25627 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_MASK 0x3u
25628 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_SHIFT 0
25629 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_MASK)
25630 /* CCM_ENET1_REF_CLK_SELECT_INPUT Bit Fields */
25631 #define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_MASK 0x3u
25632 #define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_SHIFT 0
25633 #define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_MASK)
25634 /* ENET1_MDIO_SELECT_INPUT Bit Fields */
25635 #define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_MASK 0x3u
25636 #define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_SHIFT 0
25637 #define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_MASK)
25638 /* ENET1_RX_CLK_SELECT_INPUT Bit Fields */
25639 #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_DAISY_MASK 0x1u
25640 #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_DAISY_SHIFT 0
25641 /* CCM_ENET2_REF_CLK_SELECT_INPUT Bit Fields */
25642 #define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_MASK 0x3u
25643 #define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_SHIFT 0
25644 #define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_MASK)
25645 /* ENET2_MDIO_SELECT_INPUT Bit Fields */
25646 #define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_MASK 0x3u
25647 #define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_SHIFT 0
25648 #define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_MASK)
25649 /* ENET2_RX_CLK_SELECT_INPUT Bit Fields */
25650 #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_DAISY_MASK 0x1u
25651 #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_DAISY_SHIFT 0
25652 /* EPDC_PWR_IRQ_SELECT_INPUT Bit Fields */
25653 #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_DAISY_MASK 0x1u
25654 #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_DAISY_SHIFT 0
25655 /* EPDC_PWR_STAT_SELECT_INPUT Bit Fields */
25656 #define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_DAISY_MASK 0x1u
25657 #define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_DAISY_SHIFT 0
25658 /* FLEXTIMER1_CH0_SELECT_INPUT Bit Fields */
25659 #define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_DAISY_MASK 0x1u
25660 #define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_DAISY_SHIFT 0
25661 /* FLEXTIMER1_CH1_SELECT_INPUT Bit Fields */
25662 #define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_DAISY_MASK 0x1u
25663 #define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_DAISY_SHIFT 0
25664 /* FLEXTIMER1_CH2_SELECT_INPUT Bit Fields */
25665 #define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_DAISY_MASK 0x1u
25666 #define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_DAISY_SHIFT 0
25667 /* FLEXTIMER1_CH3_SELECT_INPUT Bit Fields */
25668 #define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_DAISY_MASK 0x1u
25669 #define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_DAISY_SHIFT 0
25670 /* FLEXTIMER1_CH4_SELECT_INPUT Bit Fields */
25671 #define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_DAISY_MASK 0x1u
25672 #define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_DAISY_SHIFT 0
25673 /* FLEXTIMER1_CH5_SELECT_INPUT Bit Fields */
25674 #define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_DAISY_MASK 0x1u
25675 #define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_DAISY_SHIFT 0
25676 /* FLEXTIMER1_CH6_SELECT_INPUT Bit Fields */
25677 #define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_DAISY_MASK 0x1u
25678 #define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_DAISY_SHIFT 0
25679 /* FLEXTIMER1_CH7_SELECT_INPUT Bit Fields */
25680 #define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_DAISY_MASK 0x1u
25681 #define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_DAISY_SHIFT 0
25682 /* FLEXTIMER1_PHA_SELECT_INPUT Bit Fields */
25683 #define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_DAISY_MASK 0x1u
25684 #define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_DAISY_SHIFT 0
25685 /* FLEXTIMER1_PHB_SELECT_INPUT Bit Fields */
25686 #define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_DAISY_MASK 0x1u
25687 #define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_DAISY_SHIFT 0
25688 /* FLEXTIMER2_CH0_SELECT_INPUT Bit Fields */
25689 #define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_DAISY_MASK 0x1u
25690 #define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_DAISY_SHIFT 0
25691 /* FLEXTIMER2_CH1_SELECT_INPUT Bit Fields */
25692 #define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_DAISY_MASK 0x1u
25693 #define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_DAISY_SHIFT 0
25694 /* FLEXTIMER2_CH2_SELECT_INPUT Bit Fields */
25695 #define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_DAISY_MASK 0x1u
25696 #define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_DAISY_SHIFT 0
25697 /* FLEXTIMER2_CH3_SELECT_INPUT Bit Fields */
25698 #define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_DAISY_MASK 0x1u
25699 #define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_DAISY_SHIFT 0
25700 /* FLEXTIMER2_CH4_SELECT_INPUT Bit Fields */
25701 #define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_DAISY_MASK 0x1u
25702 #define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_DAISY_SHIFT 0
25703 /* FLEXTIMER2_CH5_SELECT_INPUT Bit Fields */
25704 #define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_DAISY_MASK 0x1u
25705 #define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_DAISY_SHIFT 0
25706 /* FLEXTIMER2_CH6_SELECT_INPUT Bit Fields */
25707 #define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_DAISY_MASK 0x1u
25708 #define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_DAISY_SHIFT 0
25709 /* FLEXTIMER2_CH7_SELECT_INPUT Bit Fields */
25710 #define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_DAISY_MASK 0x1u
25711 #define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_DAISY_SHIFT 0
25712 /* FLEXTIMER2_PHA_SELECT_INPUT Bit Fields */
25713 #define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_DAISY_MASK 0x1u
25714 #define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_DAISY_SHIFT 0
25715 /* FLEXTIMER2_PHB_SELECT_INPUT Bit Fields */
25716 #define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_DAISY_MASK 0x1u
25717 #define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_DAISY_SHIFT 0
25718 /* I2C1_SCL_SELECT_INPUT Bit Fields */
25719 #define IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_MASK  0x3u
25720 #define IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_SHIFT 0
25721 #define IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_MASK)
25722 /* I2C1_SDA_SELECT_INPUT Bit Fields */
25723 #define IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_MASK  0x3u
25724 #define IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_SHIFT 0
25725 #define IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_MASK)
25726 /* I2C2_SCL_SELECT_INPUT Bit Fields */
25727 #define IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_MASK  0x3u
25728 #define IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_SHIFT 0
25729 #define IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_MASK)
25730 /* I2C2_SDA_SELECT_INPUT Bit Fields */
25731 #define IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_MASK  0x3u
25732 #define IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_SHIFT 0
25733 #define IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_MASK)
25734 /* I2C3_SCL_SELECT_INPUT Bit Fields */
25735 #define IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_MASK  0x7u
25736 #define IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_SHIFT 0
25737 #define IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_MASK)
25738 /* I2C3_SDA_SELECT_INPUT Bit Fields */
25739 #define IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_MASK  0x7u
25740 #define IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_SHIFT 0
25741 #define IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_MASK)
25742 /* I2C4_SCL_SELECT_INPUT Bit Fields */
25743 #define IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_MASK  0x7u
25744 #define IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_SHIFT 0
25745 #define IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_MASK)
25746 /* I2C4_SDA_SELECT_INPUT Bit Fields */
25747 #define IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_MASK  0x7u
25748 #define IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_SHIFT 0
25749 #define IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_MASK)
25750 /* KPP_COL0_SELECT_INPUT Bit Fields */
25751 #define IOMUXC_KPP_COL0_SELECT_INPUT_DAISY_MASK  0x1u
25752 #define IOMUXC_KPP_COL0_SELECT_INPUT_DAISY_SHIFT 0
25753 /* KPP_COL1_SELECT_INPUT Bit Fields */
25754 #define IOMUXC_KPP_COL1_SELECT_INPUT_DAISY_MASK  0x1u
25755 #define IOMUXC_KPP_COL1_SELECT_INPUT_DAISY_SHIFT 0
25756 /* KPP_COL2_SELECT_INPUT Bit Fields */
25757 #define IOMUXC_KPP_COL2_SELECT_INPUT_DAISY_MASK  0x1u
25758 #define IOMUXC_KPP_COL2_SELECT_INPUT_DAISY_SHIFT 0
25759 /* KPP_COL3_SELECT_INPUT Bit Fields */
25760 #define IOMUXC_KPP_COL3_SELECT_INPUT_DAISY_MASK  0x1u
25761 #define IOMUXC_KPP_COL3_SELECT_INPUT_DAISY_SHIFT 0
25762 /* KPP_COL4_SELECT_INPUT Bit Fields */
25763 #define IOMUXC_KPP_COL4_SELECT_INPUT_DAISY_MASK  0x1u
25764 #define IOMUXC_KPP_COL4_SELECT_INPUT_DAISY_SHIFT 0
25765 /* KPP_COL5_SELECT_INPUT Bit Fields */
25766 #define IOMUXC_KPP_COL5_SELECT_INPUT_DAISY_MASK  0x1u
25767 #define IOMUXC_KPP_COL5_SELECT_INPUT_DAISY_SHIFT 0
25768 /* KPP_COL6_SELECT_INPUT Bit Fields */
25769 #define IOMUXC_KPP_COL6_SELECT_INPUT_DAISY_MASK  0x1u
25770 #define IOMUXC_KPP_COL6_SELECT_INPUT_DAISY_SHIFT 0
25771 /* KPP_COL7_SELECT_INPUT Bit Fields */
25772 #define IOMUXC_KPP_COL7_SELECT_INPUT_DAISY_MASK  0x1u
25773 #define IOMUXC_KPP_COL7_SELECT_INPUT_DAISY_SHIFT 0
25774 /* KPP_ROW0_SELECT_INPUT Bit Fields */
25775 #define IOMUXC_KPP_ROW0_SELECT_INPUT_DAISY_MASK  0x1u
25776 #define IOMUXC_KPP_ROW0_SELECT_INPUT_DAISY_SHIFT 0
25777 /* KPP_ROW1_SELECT_INPUT Bit Fields */
25778 #define IOMUXC_KPP_ROW1_SELECT_INPUT_DAISY_MASK  0x1u
25779 #define IOMUXC_KPP_ROW1_SELECT_INPUT_DAISY_SHIFT 0
25780 /* KPP_ROW2_SELECT_INPUT Bit Fields */
25781 #define IOMUXC_KPP_ROW2_SELECT_INPUT_DAISY_MASK  0x1u
25782 #define IOMUXC_KPP_ROW2_SELECT_INPUT_DAISY_SHIFT 0
25783 /* KPP_ROW3_SELECT_INPUT Bit Fields */
25784 #define IOMUXC_KPP_ROW3_SELECT_INPUT_DAISY_MASK  0x1u
25785 #define IOMUXC_KPP_ROW3_SELECT_INPUT_DAISY_SHIFT 0
25786 /* KPP_ROW4_SELECT_INPUT Bit Fields */
25787 #define IOMUXC_KPP_ROW4_SELECT_INPUT_DAISY_MASK  0x1u
25788 #define IOMUXC_KPP_ROW4_SELECT_INPUT_DAISY_SHIFT 0
25789 /* KPP_ROW5_SELECT_INPUT Bit Fields */
25790 #define IOMUXC_KPP_ROW5_SELECT_INPUT_DAISY_MASK  0x1u
25791 #define IOMUXC_KPP_ROW5_SELECT_INPUT_DAISY_SHIFT 0
25792 /* KPP_ROW6_SELECT_INPUT Bit Fields */
25793 #define IOMUXC_KPP_ROW6_SELECT_INPUT_DAISY_MASK  0x1u
25794 #define IOMUXC_KPP_ROW6_SELECT_INPUT_DAISY_SHIFT 0
25795 /* KPP_ROW7_SELECT_INPUT Bit Fields */
25796 #define IOMUXC_KPP_ROW7_SELECT_INPUT_DAISY_MASK  0x1u
25797 #define IOMUXC_KPP_ROW7_SELECT_INPUT_DAISY_SHIFT 0
25798 /* LCD_BUSY_SELECT_INPUT Bit Fields */
25799 #define IOMUXC_LCD_BUSY_SELECT_INPUT_DAISY_MASK  0x1u
25800 #define IOMUXC_LCD_BUSY_SELECT_INPUT_DAISY_SHIFT 0
25801 /* LCD_DATA00_SELECT_INPUT Bit Fields */
25802 #define IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_MASK 0x3u
25803 #define IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_SHIFT 0
25804 #define IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_MASK)
25805 /* LCD_DATA01_SELECT_INPUT Bit Fields */
25806 #define IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_MASK 0x3u
25807 #define IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_SHIFT 0
25808 #define IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_MASK)
25809 /* LCD_DATA02_SELECT_INPUT Bit Fields */
25810 #define IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_MASK 0x3u
25811 #define IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_SHIFT 0
25812 #define IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_MASK)
25813 /* LCD_DATA03_SELECT_INPUT Bit Fields */
25814 #define IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_MASK 0x3u
25815 #define IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_SHIFT 0
25816 #define IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_MASK)
25817 /* LCD_DATA04_SELECT_INPUT Bit Fields */
25818 #define IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_MASK 0x3u
25819 #define IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_SHIFT 0
25820 #define IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_MASK)
25821 /* LCD_DATA05_SELECT_INPUT Bit Fields */
25822 #define IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_MASK 0x3u
25823 #define IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_SHIFT 0
25824 #define IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_MASK)
25825 /* LCD_DATA06_SELECT_INPUT Bit Fields */
25826 #define IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_MASK 0x3u
25827 #define IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_SHIFT 0
25828 #define IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_MASK)
25829 /* LCD_DATA07_SELECT_INPUT Bit Fields */
25830 #define IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_MASK 0x3u
25831 #define IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_SHIFT 0
25832 #define IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_MASK)
25833 /* LCD_DATA08_SELECT_INPUT Bit Fields */
25834 #define IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_MASK 0x3u
25835 #define IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_SHIFT 0
25836 #define IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_MASK)
25837 /* LCD_DATA09_SELECT_INPUT Bit Fields */
25838 #define IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_MASK 0x3u
25839 #define IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_SHIFT 0
25840 #define IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_MASK)
25841 /* LCD_DATA10_SELECT_INPUT Bit Fields */
25842 #define IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_MASK 0x3u
25843 #define IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_SHIFT 0
25844 #define IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_MASK)
25845 /* LCD_DATA11_SELECT_INPUT Bit Fields */
25846 #define IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_MASK 0x3u
25847 #define IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_SHIFT 0
25848 #define IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_MASK)
25849 /* LCD_DATA12_SELECT_INPUT Bit Fields */
25850 #define IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_MASK 0x3u
25851 #define IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_SHIFT 0
25852 #define IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_MASK)
25853 /* LCD_DATA13_SELECT_INPUT Bit Fields */
25854 #define IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_MASK 0x3u
25855 #define IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_SHIFT 0
25856 #define IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_MASK)
25857 /* LCD_DATA14_SELECT_INPUT Bit Fields */
25858 #define IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_MASK 0x3u
25859 #define IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_SHIFT 0
25860 #define IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_MASK)
25861 /* LCD_DATA15_SELECT_INPUT Bit Fields */
25862 #define IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_MASK 0x3u
25863 #define IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_SHIFT 0
25864 #define IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_MASK)
25865 /* LCD_DATA16_SELECT_INPUT Bit Fields */
25866 #define IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_MASK 0x3u
25867 #define IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_SHIFT 0
25868 #define IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_MASK)
25869 /* LCD_DATA17_SELECT_INPUT Bit Fields */
25870 #define IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_MASK 0x3u
25871 #define IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_SHIFT 0
25872 #define IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_MASK)
25873 /* LCD_DATA18_SELECT_INPUT Bit Fields */
25874 #define IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_MASK 0x3u
25875 #define IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_SHIFT 0
25876 #define IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_MASK)
25877 /* LCD_DATA19_SELECT_INPUT Bit Fields */
25878 #define IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_MASK 0x3u
25879 #define IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_SHIFT 0
25880 #define IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_MASK)
25881 /* LCD_DATA20_SELECT_INPUT Bit Fields */
25882 #define IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_MASK 0x3u
25883 #define IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_SHIFT 0
25884 #define IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_MASK)
25885 /* LCD_DATA21_SELECT_INPUT Bit Fields */
25886 #define IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_MASK 0x3u
25887 #define IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_SHIFT 0
25888 #define IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_MASK)
25889 /* LCD_DATA22_SELECT_INPUT Bit Fields */
25890 #define IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_MASK 0x3u
25891 #define IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_SHIFT 0
25892 #define IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_MASK)
25893 /* LCD_DATA23_SELECT_INPUT Bit Fields */
25894 #define IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_MASK 0x3u
25895 #define IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_SHIFT 0
25896 #define IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_MASK)
25897 /* LCD_VSYNC_SELECT_INPUT Bit Fields */
25898 #define IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_MASK 0x3u
25899 #define IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_SHIFT 0
25900 #define IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_MASK)
25901 /* SAI1_RX_BCLK_SELECT_INPUT Bit Fields */
25902 #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u
25903 #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_DAISY_SHIFT 0
25904 /* SAI1_RX_DATA_SELECT_INPUT Bit Fields */
25905 #define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_DAISY_MASK 0x1u
25906 #define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
25907 /* SAI1_RX_SYNC_SELECT_INPUT Bit Fields */
25908 #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u
25909 #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_DAISY_SHIFT 0
25910 /* SAI1_TX_BCLK_SELECT_INPUT Bit Fields */
25911 #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u
25912 #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_DAISY_SHIFT 0
25913 /* SAI1_TX_SYNC_SELECT_INPUT Bit Fields */
25914 #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u
25915 #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_DAISY_SHIFT 0
25916 /* SAI2_RX_BCLK_SELECT_INPUT Bit Fields */
25917 #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u
25918 #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_DAISY_SHIFT 0
25919 /* SAI2_RX_DATA_SELECT_INPUT Bit Fields */
25920 #define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_DAISY_MASK 0x1u
25921 #define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
25922 /* SAI2_RX_SYNC_SELECT_INPUT Bit Fields */
25923 #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u
25924 #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_DAISY_SHIFT 0
25925 /* SAI2_TX_BCLK_SELECT_INPUT Bit Fields */
25926 #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u
25927 #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_DAISY_SHIFT 0
25928 /* SAI2_TX_SYNC_SELECT_INPUT Bit Fields */
25929 #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u
25930 #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_DAISY_SHIFT 0
25931 /* SAI3_RX_BCLK_SELECT_INPUT Bit Fields */
25932 #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_MASK 0x3u
25933 #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_SHIFT 0
25934 #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_MASK)
25935 /* SAI3_RX_DATA_SELECT_INPUT Bit Fields */
25936 #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_MASK 0x3u
25937 #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
25938 #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_MASK)
25939 /* SAI3_RX_SYNC_SELECT_INPUT Bit Fields */
25940 #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_MASK 0x3u
25941 #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_SHIFT 0
25942 #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_MASK)
25943 /* SAI3_TX_BCLK_SELECT_INPUT Bit Fields */
25944 #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_MASK 0x3u
25945 #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_SHIFT 0
25946 #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_MASK)
25947 /* SAI3_TX_SYNC_SELECT_INPUT Bit Fields */
25948 #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_MASK 0x3u
25949 #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_SHIFT 0
25950 #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_MASK)
25951 /* SDMA_EVENTS0_SELECT_INPUT Bit Fields */
25952 #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_MASK 0x3u
25953 #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_SHIFT 0
25954 #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_MASK)
25955 /* SDMA_EVENTS1_SELECT_INPUT Bit Fields */
25956 #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_MASK 0x3u
25957 #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_SHIFT 0
25958 #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_MASK)
25959 /* SIM1_PORT1_PD_SELECT_INPUT Bit Fields */
25960 #define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_DAISY_MASK 0x1u
25961 #define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_DAISY_SHIFT 0
25962 /* SIM1_PORT1_TRXD_SELECT_INPUT Bit Fields */
25963 #define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_DAISY_MASK 0x1u
25964 #define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_DAISY_SHIFT 0
25965 /* SIM2_PORT1_PD_SELECT_INPUT Bit Fields */
25966 #define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_DAISY_MASK 0x1u
25967 #define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_DAISY_SHIFT 0
25968 /* SIM2_PORT1_TRXD_SELECT_INPUT Bit Fields */
25969 #define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_DAISY_MASK 0x1u
25970 #define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_DAISY_SHIFT 0
25971 /* UART1_RTS_B_SELECT_INPUT Bit Fields */
25972 #define IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
25973 #define IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
25974 #define IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_MASK)
25975 /* UART1_RX_DATA_SELECT_INPUT Bit Fields */
25976 #define IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_MASK 0x3u
25977 #define IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
25978 #define IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_MASK)
25979 /* UART2_RTS_B_SELECT_INPUT Bit Fields */
25980 #define IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
25981 #define IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
25982 #define IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_MASK)
25983 /* UART2_RX_DATA_SELECT_INPUT Bit Fields */
25984 #define IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_MASK 0x3u
25985 #define IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
25986 #define IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_MASK)
25987 /* UART3_RTS_B_SELECT_INPUT Bit Fields */
25988 #define IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u
25989 #define IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
25990 #define IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_MASK)
25991 /* UART3_RX_DATA_SELECT_INPUT Bit Fields */
25992 #define IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u
25993 #define IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
25994 #define IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_MASK)
25995 /* UART4_RTS_B_SELECT_INPUT Bit Fields */
25996 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u
25997 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
25998 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_MASK)
25999 /* UART4_RX_DATA_SELECT_INPUT Bit Fields */
26000 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u
26001 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
26002 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_MASK)
26003 /* UART5_RTS_B_SELECT_INPUT Bit Fields */
26004 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u
26005 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
26006 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_MASK)
26007 /* UART5_RX_DATA_SELECT_INPUT Bit Fields */
26008 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u
26009 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
26010 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_MASK)
26011 /* UART6_RTS_B_SELECT_INPUT Bit Fields */
26012 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u
26013 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
26014 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_MASK)
26015 /* UART6_RX_DATA_SELECT_INPUT Bit Fields */
26016 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u
26017 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
26018 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_MASK)
26019 /* UART7_RTS_B_SELECT_INPUT Bit Fields */
26020 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u
26021 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
26022 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_MASK)
26023 /* UART7_RX_DATA_SELECT_INPUT Bit Fields */
26024 #define IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u
26025 #define IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0
26026 #define IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_MASK)
26027 /* USB_OTG2_OC_SELECT_INPUT Bit Fields */
26028 #define IOMUXC_USB_OTG2_OC_SELECT_INPUT_DAISY_MASK 0x1u
26029 #define IOMUXC_USB_OTG2_OC_SELECT_INPUT_DAISY_SHIFT 0
26030 /* USB_OTG1_OC_SELECT_INPUT Bit Fields */
26031 #define IOMUXC_USB_OTG1_OC_SELECT_INPUT_DAISY_MASK 0x1u
26032 #define IOMUXC_USB_OTG1_OC_SELECT_INPUT_DAISY_SHIFT 0
26033 /* USB_OTG2_ID_SELECT_INPUT Bit Fields */
26034 #define IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_MASK 0x3u
26035 #define IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_SHIFT 0
26036 #define IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_MASK)
26037 /* USB_OTG1_ID_SELECT_INPUT Bit Fields */
26038 #define IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_MASK 0x3u
26039 #define IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_SHIFT 0
26040 #define IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_MASK)
26041 /* SD3_CD_B_SELECT_INPUT Bit Fields */
26042 #define IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_MASK  0x3u
26043 #define IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_SHIFT 0
26044 #define IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_MASK)
26045 /* SD3_WP_SELECT_INPUT Bit Fields */
26046 #define IOMUXC_SD3_WP_SELECT_INPUT_DAISY_MASK    0x3u
26047 #define IOMUXC_SD3_WP_SELECT_INPUT_DAISY_SHIFT   0
26048 #define IOMUXC_SD3_WP_SELECT_INPUT_DAISY(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_SD3_WP_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SD3_WP_SELECT_INPUT_DAISY_MASK)
26049 
26050 /*!
26051  * @}
26052  */ /* end of group IOMUXC_Register_Masks */
26053 
26054 /* IOMUXC - Peripheral instance base addresses */
26055 /** Peripheral IOMUXC base address */
26056 #define IOMUXC_BASE                              (0x30330000u)
26057 /** Peripheral IOMUXC base pointer */
26058 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
26059 #define IOMUXC_BASE_PTR                          (IOMUXC)
26060 /** Array initializer of IOMUXC peripheral base addresses */
26061 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
26062 /** Array initializer of IOMUXC peripheral base pointers */
26063 #define IOMUXC_BASE_PTRS                         { IOMUXC }
26064 /* ----------------------------------------------------------------------------
26065    -- IOMUXC - Register accessor macros
26066    ---------------------------------------------------------------------------- */
26067 
26068 /*!
26069  * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros
26070  * @{
26071  */
26072 
26073 
26074 /* IOMUXC - Register instance definitions */
26075 /* IOMUXC */
26076 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
26077 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
26078 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
26079 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
26080 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
26081 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
26082 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(IOMUXC_BASE_PTR)
26083 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(IOMUXC_BASE_PTR)
26084 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(IOMUXC_BASE_PTR)
26085 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(IOMUXC_BASE_PTR)
26086 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(IOMUXC_BASE_PTR)
26087 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(IOMUXC_BASE_PTR)
26088 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(IOMUXC_BASE_PTR)
26089 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(IOMUXC_BASE_PTR)
26090 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(IOMUXC_BASE_PTR)
26091 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(IOMUXC_BASE_PTR)
26092 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(IOMUXC_BASE_PTR)
26093 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(IOMUXC_BASE_PTR)
26094 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(IOMUXC_BASE_PTR)
26095 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(IOMUXC_BASE_PTR)
26096 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(IOMUXC_BASE_PTR)
26097 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(IOMUXC_BASE_PTR)
26098 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(IOMUXC_BASE_PTR)
26099 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15        IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(IOMUXC_BASE_PTR)
26100 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK         IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(IOMUXC_BASE_PTR)
26101 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE          IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(IOMUXC_BASE_PTR)
26102 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE          IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(IOMUXC_BASE_PTR)
26103 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR         IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(IOMUXC_BASE_PTR)
26104 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0         IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(IOMUXC_BASE_PTR)
26105 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1         IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(IOMUXC_BASE_PTR)
26106 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2         IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(IOMUXC_BASE_PTR)
26107 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3         IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(IOMUXC_BASE_PTR)
26108 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK         IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(IOMUXC_BASE_PTR)
26109 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE          IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(IOMUXC_BASE_PTR)
26110 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL          IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(IOMUXC_BASE_PTR)
26111 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP          IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(IOMUXC_BASE_PTR)
26112 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0          IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(IOMUXC_BASE_PTR)
26113 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1          IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(IOMUXC_BASE_PTR)
26114 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM       IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(IOMUXC_BASE_PTR)
26115 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT      IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(IOMUXC_BASE_PTR)
26116 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK            IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(IOMUXC_BASE_PTR)
26117 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE         IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(IOMUXC_BASE_PTR)
26118 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC          IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(IOMUXC_BASE_PTR)
26119 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC          IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(IOMUXC_BASE_PTR)
26120 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET          IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(IOMUXC_BASE_PTR)
26121 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(IOMUXC_BASE_PTR)
26122 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(IOMUXC_BASE_PTR)
26123 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(IOMUXC_BASE_PTR)
26124 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(IOMUXC_BASE_PTR)
26125 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(IOMUXC_BASE_PTR)
26126 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(IOMUXC_BASE_PTR)
26127 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(IOMUXC_BASE_PTR)
26128 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(IOMUXC_BASE_PTR)
26129 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(IOMUXC_BASE_PTR)
26130 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(IOMUXC_BASE_PTR)
26131 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(IOMUXC_BASE_PTR)
26132 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(IOMUXC_BASE_PTR)
26133 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(IOMUXC_BASE_PTR)
26134 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(IOMUXC_BASE_PTR)
26135 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(IOMUXC_BASE_PTR)
26136 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(IOMUXC_BASE_PTR)
26137 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(IOMUXC_BASE_PTR)
26138 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(IOMUXC_BASE_PTR)
26139 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(IOMUXC_BASE_PTR)
26140 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(IOMUXC_BASE_PTR)
26141 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(IOMUXC_BASE_PTR)
26142 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(IOMUXC_BASE_PTR)
26143 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(IOMUXC_BASE_PTR)
26144 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23         IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(IOMUXC_BASE_PTR)
26145 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA      IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(IOMUXC_BASE_PTR)
26146 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA      IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(IOMUXC_BASE_PTR)
26147 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA      IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(IOMUXC_BASE_PTR)
26148 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA      IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR)
26149 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA      IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR)
26150 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA      IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR)
26151 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B        IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(IOMUXC_BASE_PTR)
26152 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B        IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(IOMUXC_BASE_PTR)
26153 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL           IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR)
26154 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA           IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR)
26155 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL           IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR)
26156 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA           IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(IOMUXC_BASE_PTR)
26157 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL           IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(IOMUXC_BASE_PTR)
26158 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA           IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(IOMUXC_BASE_PTR)
26159 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL           IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(IOMUXC_BASE_PTR)
26160 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA           IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(IOMUXC_BASE_PTR)
26161 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK        IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(IOMUXC_BASE_PTR)
26162 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI        IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(IOMUXC_BASE_PTR)
26163 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO        IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(IOMUXC_BASE_PTR)
26164 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0         IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(IOMUXC_BASE_PTR)
26165 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK        IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(IOMUXC_BASE_PTR)
26166 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI        IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(IOMUXC_BASE_PTR)
26167 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO        IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(IOMUXC_BASE_PTR)
26168 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0         IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(IOMUXC_BASE_PTR)
26169 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B           IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(IOMUXC_BASE_PTR)
26170 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP             IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(IOMUXC_BASE_PTR)
26171 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B        IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(IOMUXC_BASE_PTR)
26172 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK            IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
26173 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD            IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
26174 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
26175 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
26176 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
26177 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
26178 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B           IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(IOMUXC_BASE_PTR)
26179 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP             IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(IOMUXC_BASE_PTR)
26180 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B        IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(IOMUXC_BASE_PTR)
26181 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK            IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
26182 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD            IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
26183 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
26184 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
26185 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
26186 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
26187 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK            IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
26188 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD            IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
26189 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
26190 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
26191 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
26192 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
26193 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
26194 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
26195 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
26196 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
26197 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE         IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(IOMUXC_BASE_PTR)
26198 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B        IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(IOMUXC_BASE_PTR)
26199 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA       IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(IOMUXC_BASE_PTR)
26200 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK       IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(IOMUXC_BASE_PTR)
26201 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC       IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(IOMUXC_BASE_PTR)
26202 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA       IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(IOMUXC_BASE_PTR)
26203 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC       IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(IOMUXC_BASE_PTR)
26204 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK       IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(IOMUXC_BASE_PTR)
26205 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK          IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(IOMUXC_BASE_PTR)
26206 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC       IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(IOMUXC_BASE_PTR)
26207 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK       IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(IOMUXC_BASE_PTR)
26208 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA       IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(IOMUXC_BASE_PTR)
26209 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA       IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(IOMUXC_BASE_PTR)
26210 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(IOMUXC_BASE_PTR)
26211 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(IOMUXC_BASE_PTR)
26212 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(IOMUXC_BASE_PTR)
26213 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(IOMUXC_BASE_PTR)
26214 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(IOMUXC_BASE_PTR)
26215 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(IOMUXC_BASE_PTR)
26216 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(IOMUXC_BASE_PTR)
26217 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(IOMUXC_BASE_PTR)
26218 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(IOMUXC_BASE_PTR)
26219 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(IOMUXC_BASE_PTR)
26220 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(IOMUXC_BASE_PTR)
26221 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC    IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(IOMUXC_BASE_PTR)
26222 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK       IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
26223 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK       IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
26224 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS          IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
26225 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL          IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
26226 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
26227 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
26228 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
26229 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
26230 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
26231 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
26232 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(IOMUXC_BASE_PTR)
26233 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(IOMUXC_BASE_PTR)
26234 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD           IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(IOMUXC_BASE_PTR)
26235 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK           IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(IOMUXC_BASE_PTR)
26236 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI           IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(IOMUXC_BASE_PTR)
26237 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO           IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(IOMUXC_BASE_PTR)
26238 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS           IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(IOMUXC_BASE_PTR)
26239 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B        IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(IOMUXC_BASE_PTR)
26240 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(IOMUXC_BASE_PTR)
26241 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(IOMUXC_BASE_PTR)
26242 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(IOMUXC_BASE_PTR)
26243 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(IOMUXC_BASE_PTR)
26244 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(IOMUXC_BASE_PTR)
26245 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(IOMUXC_BASE_PTR)
26246 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(IOMUXC_BASE_PTR)
26247 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(IOMUXC_BASE_PTR)
26248 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(IOMUXC_BASE_PTR)
26249 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(IOMUXC_BASE_PTR)
26250 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(IOMUXC_BASE_PTR)
26251 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(IOMUXC_BASE_PTR)
26252 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(IOMUXC_BASE_PTR)
26253 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(IOMUXC_BASE_PTR)
26254 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(IOMUXC_BASE_PTR)
26255 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15        IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(IOMUXC_BASE_PTR)
26256 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK         IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(IOMUXC_BASE_PTR)
26257 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE          IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(IOMUXC_BASE_PTR)
26258 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE          IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(IOMUXC_BASE_PTR)
26259 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR         IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(IOMUXC_BASE_PTR)
26260 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0         IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(IOMUXC_BASE_PTR)
26261 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1         IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(IOMUXC_BASE_PTR)
26262 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2         IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(IOMUXC_BASE_PTR)
26263 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3         IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(IOMUXC_BASE_PTR)
26264 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK         IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(IOMUXC_BASE_PTR)
26265 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE          IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(IOMUXC_BASE_PTR)
26266 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL          IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(IOMUXC_BASE_PTR)
26267 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP          IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(IOMUXC_BASE_PTR)
26268 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0          IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(IOMUXC_BASE_PTR)
26269 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1          IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(IOMUXC_BASE_PTR)
26270 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM       IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(IOMUXC_BASE_PTR)
26271 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT      IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(IOMUXC_BASE_PTR)
26272 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK            IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(IOMUXC_BASE_PTR)
26273 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE         IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(IOMUXC_BASE_PTR)
26274 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC          IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(IOMUXC_BASE_PTR)
26275 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC          IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(IOMUXC_BASE_PTR)
26276 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET          IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(IOMUXC_BASE_PTR)
26277 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(IOMUXC_BASE_PTR)
26278 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(IOMUXC_BASE_PTR)
26279 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(IOMUXC_BASE_PTR)
26280 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(IOMUXC_BASE_PTR)
26281 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(IOMUXC_BASE_PTR)
26282 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(IOMUXC_BASE_PTR)
26283 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(IOMUXC_BASE_PTR)
26284 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(IOMUXC_BASE_PTR)
26285 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(IOMUXC_BASE_PTR)
26286 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(IOMUXC_BASE_PTR)
26287 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(IOMUXC_BASE_PTR)
26288 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(IOMUXC_BASE_PTR)
26289 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(IOMUXC_BASE_PTR)
26290 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(IOMUXC_BASE_PTR)
26291 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(IOMUXC_BASE_PTR)
26292 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(IOMUXC_BASE_PTR)
26293 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(IOMUXC_BASE_PTR)
26294 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(IOMUXC_BASE_PTR)
26295 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(IOMUXC_BASE_PTR)
26296 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(IOMUXC_BASE_PTR)
26297 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(IOMUXC_BASE_PTR)
26298 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(IOMUXC_BASE_PTR)
26299 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(IOMUXC_BASE_PTR)
26300 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23         IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(IOMUXC_BASE_PTR)
26301 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA      IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(IOMUXC_BASE_PTR)
26302 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA      IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(IOMUXC_BASE_PTR)
26303 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA      IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(IOMUXC_BASE_PTR)
26304 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA      IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR)
26305 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA      IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR)
26306 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA      IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR)
26307 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B        IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(IOMUXC_BASE_PTR)
26308 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B        IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(IOMUXC_BASE_PTR)
26309 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL           IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR)
26310 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA           IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR)
26311 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL           IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR)
26312 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA           IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(IOMUXC_BASE_PTR)
26313 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL           IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(IOMUXC_BASE_PTR)
26314 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA           IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(IOMUXC_BASE_PTR)
26315 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL           IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(IOMUXC_BASE_PTR)
26316 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA           IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(IOMUXC_BASE_PTR)
26317 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK        IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(IOMUXC_BASE_PTR)
26318 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI        IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(IOMUXC_BASE_PTR)
26319 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO        IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(IOMUXC_BASE_PTR)
26320 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0         IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(IOMUXC_BASE_PTR)
26321 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK        IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(IOMUXC_BASE_PTR)
26322 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI        IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(IOMUXC_BASE_PTR)
26323 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO        IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(IOMUXC_BASE_PTR)
26324 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0         IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(IOMUXC_BASE_PTR)
26325 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B           IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(IOMUXC_BASE_PTR)
26326 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP             IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(IOMUXC_BASE_PTR)
26327 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B        IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(IOMUXC_BASE_PTR)
26328 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK            IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
26329 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD            IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
26330 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
26331 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
26332 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
26333 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
26334 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B           IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(IOMUXC_BASE_PTR)
26335 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP             IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(IOMUXC_BASE_PTR)
26336 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B        IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(IOMUXC_BASE_PTR)
26337 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK            IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
26338 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD            IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
26339 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
26340 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
26341 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
26342 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
26343 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK            IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
26344 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD            IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
26345 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
26346 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
26347 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
26348 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
26349 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
26350 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
26351 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
26352 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
26353 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE         IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(IOMUXC_BASE_PTR)
26354 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B        IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(IOMUXC_BASE_PTR)
26355 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA       IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(IOMUXC_BASE_PTR)
26356 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK       IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(IOMUXC_BASE_PTR)
26357 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC       IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(IOMUXC_BASE_PTR)
26358 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA       IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(IOMUXC_BASE_PTR)
26359 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC       IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(IOMUXC_BASE_PTR)
26360 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK       IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(IOMUXC_BASE_PTR)
26361 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK          IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(IOMUXC_BASE_PTR)
26362 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC       IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(IOMUXC_BASE_PTR)
26363 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK       IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(IOMUXC_BASE_PTR)
26364 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA       IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(IOMUXC_BASE_PTR)
26365 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA       IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(IOMUXC_BASE_PTR)
26366 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(IOMUXC_BASE_PTR)
26367 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(IOMUXC_BASE_PTR)
26368 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(IOMUXC_BASE_PTR)
26369 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(IOMUXC_BASE_PTR)
26370 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(IOMUXC_BASE_PTR)
26371 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(IOMUXC_BASE_PTR)
26372 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(IOMUXC_BASE_PTR)
26373 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(IOMUXC_BASE_PTR)
26374 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(IOMUXC_BASE_PTR)
26375 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(IOMUXC_BASE_PTR)
26376 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(IOMUXC_BASE_PTR)
26377 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC    IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(IOMUXC_BASE_PTR)
26378 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK       IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
26379 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK       IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
26380 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS          IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
26381 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL          IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
26382 #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT          IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26383 #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT          IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26384 #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT        IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26385 #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT        IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26386 #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT        IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26387 #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT        IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26388 #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT       IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26389 #define IOMUXC_CSI_DATA2_SELECT_INPUT            IOMUXC_CSI_DATA2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26390 #define IOMUXC_CSI_DATA3_SELECT_INPUT            IOMUXC_CSI_DATA3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26391 #define IOMUXC_CSI_DATA4_SELECT_INPUT            IOMUXC_CSI_DATA4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26392 #define IOMUXC_CSI_DATA5_SELECT_INPUT            IOMUXC_CSI_DATA5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26393 #define IOMUXC_CSI_DATA6_SELECT_INPUT            IOMUXC_CSI_DATA6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26394 #define IOMUXC_CSI_DATA7_SELECT_INPUT            IOMUXC_CSI_DATA7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26395 #define IOMUXC_CSI_DATA8_SELECT_INPUT            IOMUXC_CSI_DATA8_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26396 #define IOMUXC_CSI_DATA9_SELECT_INPUT            IOMUXC_CSI_DATA9_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26397 #define IOMUXC_CSI_HSYNC_SELECT_INPUT            IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26398 #define IOMUXC_CSI_PIXCLK_SELECT_INPUT           IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26399 #define IOMUXC_CSI_VSYNC_SELECT_INPUT            IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26400 #define IOMUXC_ECSPI1_SCLK_SELECT_INPUT          IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26401 #define IOMUXC_ECSPI1_MISO_SELECT_INPUT          IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26402 #define IOMUXC_ECSPI1_MOSI_SELECT_INPUT          IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26403 #define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT         IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26404 #define IOMUXC_ECSPI2_SCLK_SELECT_INPUT          IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26405 #define IOMUXC_ECSPI2_MISO_SELECT_INPUT          IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26406 #define IOMUXC_ECSPI2_MOSI_SELECT_INPUT          IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26407 #define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT         IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26408 #define IOMUXC_ECSPI3_SCLK_SELECT_INPUT          IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26409 #define IOMUXC_ECSPI3_MISO_SELECT_INPUT          IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26410 #define IOMUXC_ECSPI3_MOSI_SELECT_INPUT          IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26411 #define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT         IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26412 #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT          IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26413 #define IOMUXC_ECSPI4_MISO_SELECT_INPUT          IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26414 #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT          IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26415 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT         IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26416 #define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT    IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26417 #define IOMUXC_ENET1_MDIO_SELECT_INPUT           IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26418 #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT         IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26419 #define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT    IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26420 #define IOMUXC_ENET2_MDIO_SELECT_INPUT           IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26421 #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT         IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26422 #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT         IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26423 #define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT        IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26424 #define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26425 #define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26426 #define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26427 #define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26428 #define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26429 #define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26430 #define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26431 #define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT       IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26432 #define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT       IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26433 #define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT       IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26434 #define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26435 #define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26436 #define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26437 #define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26438 #define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26439 #define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26440 #define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26441 #define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT       IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26442 #define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT       IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26443 #define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT       IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26444 #define IOMUXC_I2C1_SCL_SELECT_INPUT             IOMUXC_I2C1_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26445 #define IOMUXC_I2C1_SDA_SELECT_INPUT             IOMUXC_I2C1_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26446 #define IOMUXC_I2C2_SCL_SELECT_INPUT             IOMUXC_I2C2_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26447 #define IOMUXC_I2C2_SDA_SELECT_INPUT             IOMUXC_I2C2_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26448 #define IOMUXC_I2C3_SCL_SELECT_INPUT             IOMUXC_I2C3_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26449 #define IOMUXC_I2C3_SDA_SELECT_INPUT             IOMUXC_I2C3_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26450 #define IOMUXC_I2C4_SCL_SELECT_INPUT             IOMUXC_I2C4_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26451 #define IOMUXC_I2C4_SDA_SELECT_INPUT             IOMUXC_I2C4_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26452 #define IOMUXC_KPP_COL0_SELECT_INPUT             IOMUXC_KPP_COL0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26453 #define IOMUXC_KPP_COL1_SELECT_INPUT             IOMUXC_KPP_COL1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26454 #define IOMUXC_KPP_COL2_SELECT_INPUT             IOMUXC_KPP_COL2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26455 #define IOMUXC_KPP_COL3_SELECT_INPUT             IOMUXC_KPP_COL3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26456 #define IOMUXC_KPP_COL4_SELECT_INPUT             IOMUXC_KPP_COL4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26457 #define IOMUXC_KPP_COL5_SELECT_INPUT             IOMUXC_KPP_COL5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26458 #define IOMUXC_KPP_COL6_SELECT_INPUT             IOMUXC_KPP_COL6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26459 #define IOMUXC_KPP_COL7_SELECT_INPUT             IOMUXC_KPP_COL7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26460 #define IOMUXC_KPP_ROW0_SELECT_INPUT             IOMUXC_KPP_ROW0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26461 #define IOMUXC_KPP_ROW1_SELECT_INPUT             IOMUXC_KPP_ROW1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26462 #define IOMUXC_KPP_ROW2_SELECT_INPUT             IOMUXC_KPP_ROW2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26463 #define IOMUXC_KPP_ROW3_SELECT_INPUT             IOMUXC_KPP_ROW3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26464 #define IOMUXC_KPP_ROW4_SELECT_INPUT             IOMUXC_KPP_ROW4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26465 #define IOMUXC_KPP_ROW5_SELECT_INPUT             IOMUXC_KPP_ROW5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26466 #define IOMUXC_KPP_ROW6_SELECT_INPUT             IOMUXC_KPP_ROW6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26467 #define IOMUXC_KPP_ROW7_SELECT_INPUT             IOMUXC_KPP_ROW7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26468 #define IOMUXC_LCD_BUSY_SELECT_INPUT             IOMUXC_LCD_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26469 #define IOMUXC_LCD_DATA00_SELECT_INPUT           IOMUXC_LCD_DATA00_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26470 #define IOMUXC_LCD_DATA01_SELECT_INPUT           IOMUXC_LCD_DATA01_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26471 #define IOMUXC_LCD_DATA02_SELECT_INPUT           IOMUXC_LCD_DATA02_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26472 #define IOMUXC_LCD_DATA03_SELECT_INPUT           IOMUXC_LCD_DATA03_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26473 #define IOMUXC_LCD_DATA04_SELECT_INPUT           IOMUXC_LCD_DATA04_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26474 #define IOMUXC_LCD_DATA05_SELECT_INPUT           IOMUXC_LCD_DATA05_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26475 #define IOMUXC_LCD_DATA06_SELECT_INPUT           IOMUXC_LCD_DATA06_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26476 #define IOMUXC_LCD_DATA07_SELECT_INPUT           IOMUXC_LCD_DATA07_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26477 #define IOMUXC_LCD_DATA08_SELECT_INPUT           IOMUXC_LCD_DATA08_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26478 #define IOMUXC_LCD_DATA09_SELECT_INPUT           IOMUXC_LCD_DATA09_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26479 #define IOMUXC_LCD_DATA10_SELECT_INPUT           IOMUXC_LCD_DATA10_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26480 #define IOMUXC_LCD_DATA11_SELECT_INPUT           IOMUXC_LCD_DATA11_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26481 #define IOMUXC_LCD_DATA12_SELECT_INPUT           IOMUXC_LCD_DATA12_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26482 #define IOMUXC_LCD_DATA13_SELECT_INPUT           IOMUXC_LCD_DATA13_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26483 #define IOMUXC_LCD_DATA14_SELECT_INPUT           IOMUXC_LCD_DATA14_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26484 #define IOMUXC_LCD_DATA15_SELECT_INPUT           IOMUXC_LCD_DATA15_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26485 #define IOMUXC_LCD_DATA16_SELECT_INPUT           IOMUXC_LCD_DATA16_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26486 #define IOMUXC_LCD_DATA17_SELECT_INPUT           IOMUXC_LCD_DATA17_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26487 #define IOMUXC_LCD_DATA18_SELECT_INPUT           IOMUXC_LCD_DATA18_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26488 #define IOMUXC_LCD_DATA19_SELECT_INPUT           IOMUXC_LCD_DATA19_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26489 #define IOMUXC_LCD_DATA20_SELECT_INPUT           IOMUXC_LCD_DATA20_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26490 #define IOMUXC_LCD_DATA21_SELECT_INPUT           IOMUXC_LCD_DATA21_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26491 #define IOMUXC_LCD_DATA22_SELECT_INPUT           IOMUXC_LCD_DATA22_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26492 #define IOMUXC_LCD_DATA23_SELECT_INPUT           IOMUXC_LCD_DATA23_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26493 #define IOMUXC_LCD_VSYNC_SELECT_INPUT            IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26494 #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT         IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26495 #define IOMUXC_SAI1_RX_DATA_SELECT_INPUT         IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26496 #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT         IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26497 #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT         IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26498 #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT         IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26499 #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT         IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26500 #define IOMUXC_SAI2_RX_DATA_SELECT_INPUT         IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26501 #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT         IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26502 #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT         IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26503 #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT         IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26504 #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT         IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26505 #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT         IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26506 #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT         IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26507 #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT         IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26508 #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT         IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26509 #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT         IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26510 #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT         IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26511 #define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT        IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26512 #define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT      IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26513 #define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT        IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26514 #define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT      IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26515 #define IOMUXC_UART1_RTS_B_SELECT_INPUT          IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26516 #define IOMUXC_UART1_RX_DATA_SELECT_INPUT        IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26517 #define IOMUXC_UART2_RTS_B_SELECT_INPUT          IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26518 #define IOMUXC_UART2_RX_DATA_SELECT_INPUT        IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26519 #define IOMUXC_UART3_RTS_B_SELECT_INPUT          IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26520 #define IOMUXC_UART3_RX_DATA_SELECT_INPUT        IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26521 #define IOMUXC_UART4_RTS_B_SELECT_INPUT          IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26522 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT        IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26523 #define IOMUXC_UART5_RTS_B_SELECT_INPUT          IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26524 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT        IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26525 #define IOMUXC_UART6_RTS_B_SELECT_INPUT          IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26526 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT        IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26527 #define IOMUXC_UART7_RTS_B_SELECT_INPUT          IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26528 #define IOMUXC_UART7_RX_DATA_SELECT_INPUT        IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26529 #define IOMUXC_USB_OTG2_OC_SELECT_INPUT          IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26530 #define IOMUXC_USB_OTG1_OC_SELECT_INPUT          IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26531 #define IOMUXC_USB_OTG2_ID_SELECT_INPUT          IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26532 #define IOMUXC_USB_OTG1_ID_SELECT_INPUT          IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26533 #define IOMUXC_SD3_CD_B_SELECT_INPUT             IOMUXC_SD3_CD_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26534 #define IOMUXC_SD3_WP_SELECT_INPUT               IOMUXC_SD3_WP_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26535 /*!
26536  * @}
26537  */ /* end of group IOMUXC_Register_Accessor_Macros */
26538 
26539 
26540 /*!
26541  * @}
26542  */ /* end of group IOMUXC_Peripheral */
26543 
26544 /* ----------------------------------------------------------------------------
26545    -- IOMUXC_GPR Peripheral Access Layer
26546    ---------------------------------------------------------------------------- */
26547 
26548 /*!
26549  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
26550  * @{
26551  */
26552 
26553 /** IOMUXC_GPR - Register Layout Typedef */
26554 typedef struct {
26555   __IO  uint32_t GPR0;                                   /**< GPR0 General Purpose Register, offset: 0x0 */
26556   __IO  uint32_t GPR1;                                   /**< GPR1 General Purpose Register, offset: 0x4 */
26557   __IO  uint32_t GPR2;                                   /**< GPR2 General Purpose Register, offset: 0x8 */
26558   __IO  uint32_t GPR3;                                   /**< GPR3 General Purpose Register, offset: 0xC */
26559   __IO  uint32_t GPR4;                                   /**< GPR4 General Purpose Register, offset: 0x10 */
26560   __IO  uint32_t GPR5;                                   /**< GPR5 General Purpose Register, offset: 0x14 */
26561   __IO  uint32_t GPR6;                                   /**< GPR6 General Purpose Register, offset: 0x18 */
26562   __IO  uint32_t GPR7;                                   /**< GPR7 General Purpose Register, offset: 0x1C */
26563   __IO  uint32_t GPR8;                                   /**< GPR8 General Purpose Register, offset: 0x20 */
26564   __IO  uint32_t GPR9;                                   /**< GPR9 General Purpose Register, offset: 0x24 */
26565   __IO  uint32_t GPR10;                                  /**< GPR10 General Purpose Register, offset: 0x28 */
26566   __IO  uint32_t GPR11;                                  /**< GPR11 General Purpose Register, offset: 0x2C */
26567   __IO  uint32_t GPR12;                                  /**< GPR12 General Purpose Register, offset: 0x30 */
26568   __IO  uint32_t GPR13;                                  /**< GPR13 General Purpose Register, offset: 0x34 */
26569   __IO  uint32_t GPR14;                                  /**< GPR14 General Purpose Register, offset: 0x38 */
26570   __IO  uint32_t GPR15;                                  /**< GPR15 General Purpose Register, offset: 0x3C */
26571   __IO  uint32_t GPR16;                                  /**< GPR16 General Purpose Register, offset: 0x40 */
26572   __IO  uint32_t GPR17;                                  /**< GPR17 General Purpose Register, offset: 0x44 */
26573   __IO  uint32_t GPR18;                                  /**< GPR18 General Purpose Register, offset: 0x48 */
26574   __I   uint32_t GPR19;                                  /**< GPR19 General Purpose Register, offset: 0x4C */
26575   __IO  uint32_t GPR20;                                  /**< GPR20 General Purpose Register, offset: 0x50 */
26576   __IO  uint32_t GPR21;                                  /**< GPR21 General Purpose Register, offset: 0x54 */
26577   __I   uint32_t GPR22;                                  /**< GPR22 General Purpose Register, offset: 0x58 */
26578 } IOMUXC_GPR_Type, *IOMUXC_GPR_MemMapPtr;
26579 /* ----------------------------------------------------------------------------
26580    -- IOMUXC_GPR - Register accessor macros
26581    ---------------------------------------------------------------------------- */
26582 
26583 /*!
26584  * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros
26585  * @{
26586  */
26587 
26588 
26589 /* IOMUXC_GPR - Register accessors */
26590 #define IOMUXC_GPR_GPR0_REG(base)                ((base)->GPR0)
26591 #define IOMUXC_GPR_GPR1_REG(base)                ((base)->GPR1)
26592 #define IOMUXC_GPR_GPR2_REG(base)                ((base)->GPR2)
26593 #define IOMUXC_GPR_GPR3_REG(base)                ((base)->GPR3)
26594 #define IOMUXC_GPR_GPR4_REG(base)                ((base)->GPR4)
26595 #define IOMUXC_GPR_GPR5_REG(base)                ((base)->GPR5)
26596 #define IOMUXC_GPR_GPR6_REG(base)                ((base)->GPR6)
26597 #define IOMUXC_GPR_GPR7_REG(base)                ((base)->GPR7)
26598 #define IOMUXC_GPR_GPR8_REG(base)                ((base)->GPR8)
26599 #define IOMUXC_GPR_GPR9_REG(base)                ((base)->GPR9)
26600 #define IOMUXC_GPR_GPR10_REG(base)               ((base)->GPR10)
26601 #define IOMUXC_GPR_GPR11_REG(base)               ((base)->GPR11)
26602 #define IOMUXC_GPR_GPR12_REG(base)               ((base)->GPR12)
26603 #define IOMUXC_GPR_GPR13_REG(base)               ((base)->GPR13)
26604 #define IOMUXC_GPR_GPR14_REG(base)               ((base)->GPR14)
26605 #define IOMUXC_GPR_GPR15_REG(base)               ((base)->GPR15)
26606 #define IOMUXC_GPR_GPR16_REG(base)               ((base)->GPR16)
26607 #define IOMUXC_GPR_GPR17_REG(base)               ((base)->GPR17)
26608 #define IOMUXC_GPR_GPR18_REG(base)               ((base)->GPR18)
26609 #define IOMUXC_GPR_GPR19_REG(base)               ((base)->GPR19)
26610 #define IOMUXC_GPR_GPR20_REG(base)               ((base)->GPR20)
26611 #define IOMUXC_GPR_GPR21_REG(base)               ((base)->GPR21)
26612 #define IOMUXC_GPR_GPR22_REG(base)               ((base)->GPR22)
26613 
26614 /*!
26615  * @}
26616  */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */
26617 /* ----------------------------------------------------------------------------
26618    -- IOMUXC_GPR Register Masks
26619    ---------------------------------------------------------------------------- */
26620 
26621 /*!
26622  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
26623  * @{
26624  */
26625 
26626 /* GPR0 Bit Fields */
26627 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u
26628 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT    0
26629 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK     0x2u
26630 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT    1
26631 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK     0x4u
26632 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT    2
26633 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK     0x8u
26634 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT    3
26635 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK     0x10u
26636 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT    4
26637 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK     0x20u
26638 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT    5
26639 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK     0x40u
26640 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT    6
26641 /* GPR1 Bit Fields */
26642 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_MASK        0x1u
26643 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_SHIFT       0
26644 #define IOMUXC_GPR_GPR1_WEIM_ADDRS0_MASK         0x6u
26645 #define IOMUXC_GPR_GPR1_WEIM_ADDRS0_SHIFT        1
26646 #define IOMUXC_GPR_GPR1_WEIM_ADDRS0(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS0_MASK)
26647 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS1_MASK        0x8u
26648 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS1_SHIFT       3
26649 #define IOMUXC_GPR_GPR1_WEIM_ADDRS1_MASK         0x30u
26650 #define IOMUXC_GPR_GPR1_WEIM_ADDRS1_SHIFT        4
26651 #define IOMUXC_GPR_GPR1_WEIM_ADDRS1(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS1_MASK)
26652 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS2_MASK        0x40u
26653 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS2_SHIFT       6
26654 #define IOMUXC_GPR_GPR1_WEIM_ADDRS2_MASK         0x180u
26655 #define IOMUXC_GPR_GPR1_WEIM_ADDRS2_SHIFT        7
26656 #define IOMUXC_GPR_GPR1_WEIM_ADDRS2(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS2_MASK)
26657 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS3_MASK        0x200u
26658 #define IOMUXC_GPR_GPR1_WEIM_ACT_CS3_SHIFT       9
26659 #define IOMUXC_GPR_GPR1_WEIM_ADDRS3_MASK         0xC00u
26660 #define IOMUXC_GPR_GPR1_WEIM_ADDRS3_SHIFT        10
26661 #define IOMUXC_GPR_GPR1_WEIM_ADDRS3(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS3_MASK)
26662 #define IOMUXC_GPR_GPR1_IRQ_MASK                 0x1000u
26663 #define IOMUXC_GPR_GPR1_IRQ_SHIFT                12
26664 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_SEL_MASK    0x2000u
26665 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_SEL_SHIFT   13
26666 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_SEL_MASK    0x4000u
26667 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_SEL_SHIFT   14
26668 #define IOMUXC_GPR_GPR1_PAD_ADD_DS_MASK          0x10000u
26669 #define IOMUXC_GPR_GPR1_PAD_ADD_DS_SHIFT         16
26670 #define IOMUXC_GPR_GPR1_ENET1_CLK_DIR_MASK       0x20000u
26671 #define IOMUXC_GPR_GPR1_ENET1_CLK_DIR_SHIFT      17
26672 #define IOMUXC_GPR_GPR1_ENET2_CLK_DIR_MASK       0x40000u
26673 #define IOMUXC_GPR_GPR1_ENET2_CLK_DIR_SHIFT      18
26674 #define IOMUXC_GPR_GPR1_EXC_ERR_RESP_EN_MASK     0x400000u
26675 #define IOMUXC_GPR_GPR1_EXC_ERR_RESP_EN_SHIFT    22
26676 #define IOMUXC_GPR_GPR1_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
26677 #define IOMUXC_GPR_GPR1_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
26678 #define IOMUXC_GPR_GPR1_DBG_ACK_MASK             0x30000000u
26679 #define IOMUXC_GPR_GPR1_DBG_ACK_SHIFT            28
26680 #define IOMUXC_GPR_GPR1_DBG_ACK(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_DBG_ACK_MASK)
26681 #define IOMUXC_GPR_GPR1_ENABLE_OCRAM_EPDC_MASK   0x40000000u
26682 #define IOMUXC_GPR_GPR1_ENABLE_OCRAM_EPDC_SHIFT  30
26683 /* GPR2 Bit Fields */
26684 #define IOMUXC_GPR_GPR2_MEM_PXP_LOWPOWER_MASK    0x1u
26685 #define IOMUXC_GPR_GPR2_MEM_PXP_LOWPOWER_SHIFT   0
26686 #define IOMUXC_GPR_GPR2_MEM_PXP_SD_MASK          0x2u
26687 #define IOMUXC_GPR_GPR2_MEM_PXP_SD_SHIFT         1
26688 #define IOMUXC_GPR_GPR2_MEM_PXP_DS_MASK          0x4u
26689 #define IOMUXC_GPR_GPR2_MEM_PXP_DS_SHIFT         2
26690 #define IOMUXC_GPR_GPR2_MEM_PXP_LS_MASK          0x8u
26691 #define IOMUXC_GPR_GPR2_MEM_PXP_LS_SHIFT         3
26692 #define IOMUXC_GPR_GPR2_MEM_LCDIF_LOWPOWER_MASK  0x10u
26693 #define IOMUXC_GPR_GPR2_MEM_LCDIF_LOWPOWER_SHIFT 4
26694 #define IOMUXC_GPR_GPR2_MEM_LCDIF_SD_MASK        0x20u
26695 #define IOMUXC_GPR_GPR2_MEM_LCDIF_SD_SHIFT       5
26696 #define IOMUXC_GPR_GPR2_MEM_LCDIF_DS_MASK        0x40u
26697 #define IOMUXC_GPR_GPR2_MEM_LCDIF_DS_SHIFT       6
26698 #define IOMUXC_GPR_GPR2_MEM_LCDIF_LS_MASK        0x80u
26699 #define IOMUXC_GPR_GPR2_MEM_LCDIF_LS_SHIFT       7
26700 #define IOMUXC_GPR_GPR2_MEM_EPDC_LOWPOWER_MASK   0x100u
26701 #define IOMUXC_GPR_GPR2_MEM_EPDC_LOWPOWER_SHIFT  8
26702 #define IOMUXC_GPR_GPR2_MEM_EPDC_SD_MASK         0x200u
26703 #define IOMUXC_GPR_GPR2_MEM_EPDC_SD_SHIFT        9
26704 #define IOMUXC_GPR_GPR2_MEM_EPDC_DS_MASK         0x400u
26705 #define IOMUXC_GPR_GPR2_MEM_EPDC_DS_SHIFT        10
26706 #define IOMUXC_GPR_GPR2_MEM_EPDC_LS_MASK         0x800u
26707 #define IOMUXC_GPR_GPR2_MEM_EPDC_LS_SHIFT        11
26708 #define IOMUXC_GPR_GPR2_MEM_CPU_LOWPOWER_MASK    0x1000u
26709 #define IOMUXC_GPR_GPR2_MEM_CPU_LOWPOWER_SHIFT   12
26710 #define IOMUXC_GPR_GPR2_MEM_CPU_SD_MASK          0x2000u
26711 #define IOMUXC_GPR_GPR2_MEM_CPU_SD_SHIFT         13
26712 #define IOMUXC_GPR_GPR2_MEM_CPU_DS_MASK          0x4000u
26713 #define IOMUXC_GPR_GPR2_MEM_CPU_DS_SHIFT         14
26714 #define IOMUXC_GPR_GPR2_MEM_CPU_LS_MASK          0x8000u
26715 #define IOMUXC_GPR_GPR2_MEM_CPU_LS_SHIFT         15
26716 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK         0xFF0000u
26717 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT        16
26718 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
26719 #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK          0x1000000u
26720 #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT         24
26721 #define IOMUXC_GPR_GPR2_MQS_EN_MASK              0x2000000u
26722 #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT             25
26723 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK      0x4000000u
26724 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT     26
26725 #define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK   0x8000000u
26726 #define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT  27
26727 #define IOMUXC_GPR_GPR2_DRAM_RESET_MASK          0x10000000u
26728 #define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT         28
26729 #define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK           0x20000000u
26730 #define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT          29
26731 #define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK           0x40000000u
26732 #define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT          30
26733 #define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK     0x80000000u
26734 #define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT    31
26735 /* GPR3 Bit Fields */
26736 #define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_MASK       0x1u
26737 #define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_SHIFT      0
26738 #define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_MASK       0x2u
26739 #define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_SHIFT      1
26740 #define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_MASK       0x4u
26741 #define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_SHIFT      2
26742 #define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_MASK       0x8u
26743 #define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_SHIFT      3
26744 #define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_MASK     0x10u
26745 #define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_SHIFT    4
26746 #define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_MASK     0x20u
26747 #define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_SHIFT    5
26748 #define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_MASK     0x40u
26749 #define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_SHIFT    6
26750 #define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_MASK     0x80u
26751 #define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_SHIFT    7
26752 #define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_MASK     0x100u
26753 #define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_SHIFT    8
26754 #define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_MASK     0x200u
26755 #define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_SHIFT    9
26756 #define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_MASK     0x400u
26757 #define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_SHIFT    10
26758 #define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_MASK     0x800u
26759 #define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_SHIFT    11
26760 #define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_MASK     0x1000u
26761 #define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_SHIFT    12
26762 #define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_MASK     0x2000u
26763 #define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_SHIFT    13
26764 #define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_MASK     0x4000u
26765 #define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_SHIFT    14
26766 #define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_MASK     0x8000u
26767 #define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_SHIFT    15
26768 #define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_PDG_MASK   0x10000u
26769 #define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_PDG_SHIFT  16
26770 #define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_PDG_MASK   0x20000u
26771 #define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_PDG_SHIFT  17
26772 #define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_PDG_MASK   0x40000u
26773 #define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_PDG_SHIFT  18
26774 #define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_PNDG_MASK  0x80000u
26775 #define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_PNDG_SHIFT 19
26776 #define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_PNDG_MASK 0x100000u
26777 #define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_PNDG_SHIFT 20
26778 #define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_PNDG_MASK 0x200000u
26779 #define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_PNDG_SHIFT 21
26780 #define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_PNDG_MASK 0x400000u
26781 #define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_PNDG_SHIFT 22
26782 #define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_PNDG_MASK 0x800000u
26783 #define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_PNDG_SHIFT 23
26784 #define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_PNDG_MASK 0x1000000u
26785 #define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_PNDG_SHIFT 24
26786 #define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_PNDG_MASK 0x2000000u
26787 #define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_PNDG_SHIFT 25
26788 #define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_PNDG_MASK 0x4000000u
26789 #define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_PNDG_SHIFT 26
26790 #define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_PNDG_MASK 0x8000000u
26791 #define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_PNDG_SHIFT 27
26792 #define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_PNDG_MASK 0x10000000u
26793 #define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_PNDG_SHIFT 28
26794 #define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_PNDG_MASK 0x20000000u
26795 #define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_PNDG_SHIFT 29
26796 #define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_PNDG_MASK 0x40000000u
26797 #define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_PNDG_SHIFT 30
26798 #define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_PNDG_MASK 0x80000000u
26799 #define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_PNDG_SHIFT 31
26800 /* GPR4 Bit Fields */
26801 #define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_MASK       0x1u
26802 #define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_SHIFT      0
26803 #define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_MASK       0x2u
26804 #define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_SHIFT      1
26805 #define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_MASK       0x4u
26806 #define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_SHIFT      2
26807 #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_MASK      0x8u
26808 #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_SHIFT     3
26809 #define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_MASK      0x10u
26810 #define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_SHIFT     4
26811 #define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_MASK       0x20u
26812 #define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_SHIFT      5
26813 #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_MASK       0x40u
26814 #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_SHIFT      6
26815 #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_MASK       0x80u
26816 #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_SHIFT      7
26817 #define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_ACK_MASK   0x10000u
26818 #define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_ACK_SHIFT  16
26819 #define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_ACK_MASK   0x20000u
26820 #define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_ACK_SHIFT  17
26821 #define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_ACK_MASK   0x40000u
26822 #define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_ACK_SHIFT  18
26823 #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_MASK  0x80000u
26824 #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_SHIFT 19
26825 #define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_ACK_MASK  0x100000u
26826 #define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_ACK_SHIFT 20
26827 #define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_ACK_MASK   0x200000u
26828 #define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_ACK_SHIFT  21
26829 #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_MASK   0x400000u
26830 #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_SHIFT  22
26831 #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_MASK   0x800000u
26832 #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_SHIFT  23
26833 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK      0x6000000u
26834 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT     25
26835 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFI(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK)
26836 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK      0x18000000u
26837 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT     27
26838 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK)
26839 /* GPR5 Bit Fields */
26840 #define IOMUXC_GPR_GPR5_CSI_MUX_CONTROL_MASK     0x10u
26841 #define IOMUXC_GPR_GPR5_CSI_MUX_CONTROL_SHIFT    4
26842 #define IOMUXC_GPR_GPR5_LVDS_MUX_CONTROL_MASK    0x20u
26843 #define IOMUXC_GPR_GPR5_LVDS_MUX_CONTROL_SHIFT   5
26844 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK          0x40u
26845 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT         6
26846 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK          0x80u
26847 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT         7
26848 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_MASK     0x1000u
26849 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_SHIFT    12
26850 #define IOMUXC_GPR_GPR5_PCIE_BTNRST_MASK         0x80000u
26851 #define IOMUXC_GPR_GPR5_PCIE_BTNRST_SHIFT        19
26852 #define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK          0x100000u
26853 #define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT         20
26854 #define IOMUXC_GPR_GPR5_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
26855 #define IOMUXC_GPR_GPR5_LCDIF_CSI_VSYNC_SEL_SHIFT 21
26856 #define IOMUXC_GPR_GPR5_WDOG4_MASK_MASK          0x400000u
26857 #define IOMUXC_GPR_GPR5_WDOG4_MASK_SHIFT         22
26858 #define IOMUXC_GPR_GPR5_GPT4_CAPIN1_SEL_MASK     0x1000000u
26859 #define IOMUXC_GPR_GPR5_GPT4_CAPIN1_SEL_SHIFT    24
26860 #define IOMUXC_GPR_GPR5_GPT4_CAPIN2_SEL_MASK     0x2000000u
26861 #define IOMUXC_GPR_GPR5_GPT4_CAPIN2_SEL_SHIFT    25
26862 #define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK  0x4000000u
26863 #define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT 26
26864 #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK  0x8000000u
26865 #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT 27
26866 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT1_MASK     0x10000000u
26867 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT1_SHIFT    28
26868 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT2_MASK     0x20000000u
26869 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT2_SHIFT    29
26870 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT3_MASK     0x40000000u
26871 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT3_SHIFT    30
26872 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT4_MASK     0x80000000u
26873 #define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT4_SHIFT    31
26874 /* GPR6 Bit Fields */
26875 #define IOMUXC_GPR_GPR6_ARCACHE_PXP6_MASK        0x1u
26876 #define IOMUXC_GPR_GPR6_ARCACHE_PXP6_SHIFT       0
26877 #define IOMUXC_GPR_GPR6_AWCACHE_PXP6_MASK        0x2u
26878 #define IOMUXC_GPR_GPR6_AWCACHE_PXP6_SHIFT       1
26879 #define IOMUXC_GPR_GPR6_ARCACHE_PXP6_EN_MASK     0x4u
26880 #define IOMUXC_GPR_GPR6_ARCACHE_PXP6_EN_SHIFT    2
26881 #define IOMUXC_GPR_GPR6_AWCACHE_PXP6_EN_MASK     0x8u
26882 #define IOMUXC_GPR_GPR6_AWCACHE_PXP6_EN_SHIFT    3
26883 /* GPR7 Bit Fields */
26884 #define IOMUXC_GPR_GPR7_CHD1_EN_PWRUPLOAD_MASK   0x8u
26885 #define IOMUXC_GPR_GPR7_CHD1_EN_PWRUPLOAD_SHIFT  3
26886 #define IOMUXC_GPR_GPR7_CHD1_TEST_MASK           0x30u
26887 #define IOMUXC_GPR_GPR7_CHD1_TEST_SHIFT          4
26888 #define IOMUXC_GPR_GPR7_CHD1_TEST(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_CHD1_TEST_SHIFT))&IOMUXC_GPR_GPR7_CHD1_TEST_MASK)
26889 #define IOMUXC_GPR_GPR7_CHD2_EN_PWRUPLOAD_LDO_USB_1p0_MASK 0x200u
26890 #define IOMUXC_GPR_GPR7_CHD2_EN_PWRUPLOAD_LDO_USB_1p0_SHIFT 9
26891 #define IOMUXC_GPR_GPR7_CHD2_TEST_MASK           0xC00u
26892 #define IOMUXC_GPR_GPR7_CHD2_TEST_SHIFT          10
26893 #define IOMUXC_GPR_GPR7_CHD2_TEST(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_CHD2_TEST_SHIFT))&IOMUXC_GPR_GPR7_CHD2_TEST_MASK)
26894 /* GPR8 Bit Fields */
26895 #define IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_MASK 0xF8u
26896 #define IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_SHIFT 3
26897 #define IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_SHIFT))&IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_MASK)
26898 #define IOMUXC_GPR_GPR8_DDR_PHY_DFI_INIT_START_MASK 0x100u
26899 #define IOMUXC_GPR_GPR8_DDR_PHY_DFI_INIT_START_SHIFT 8
26900 /* GPR9 Bit Fields */
26901 #define IOMUXC_GPR_GPR9_TZASC1_MUX_CONTROL_MASK  0x1u
26902 #define IOMUXC_GPR_GPR9_TZASC1_MUX_CONTROL_SHIFT 0
26903 #define IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_MASK     0x3Eu
26904 #define IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_SHIFT    1
26905 #define IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_SHIFT))&IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_MASK)
26906 /* GPR10 Bit Fields */
26907 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_EN_MASK    0x4u
26908 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_EN_SHIFT   2
26909 #define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_EN_MASK   0x8u
26910 #define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_EN_SHIFT  3
26911 #define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_MASK 0x3F0u
26912 #define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_SHIFT 4
26913 #define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_MASK)
26914 #define IOMUXC_GPR_GPR10_GPR10_LOCK_MASK         0xFFFFFC00u
26915 #define IOMUXC_GPR_GPR10_GPR10_LOCK_SHIFT        10
26916 #define IOMUXC_GPR_GPR10_GPR10_LOCK(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR10_LOCK_SHIFT))&IOMUXC_GPR_GPR10_GPR10_LOCK_MASK)
26917 /* GPR11 Bit Fields */
26918 #define IOMUXC_GPR_GPR11_OCRAM_TZ_EN_MASK        0x1u
26919 #define IOMUXC_GPR_GPR11_OCRAM_TZ_EN_SHIFT       0
26920 #define IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_MASK      0x3Eu
26921 #define IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_SHIFT     1
26922 #define IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_MASK)
26923 #define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_EN_MASK    0x40u
26924 #define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_EN_SHIFT   6
26925 #define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_MASK  0x380u
26926 #define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_SHIFT 7
26927 #define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_MASK)
26928 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_MASK      0x400u
26929 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_SHIFT     10
26930 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK    0x3800u
26931 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT   11
26932 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK)
26933 #define IOMUXC_GPR_GPR11_GPR11_LOCK_MASK         0xFFFFC000u
26934 #define IOMUXC_GPR_GPR11_GPR11_LOCK_SHIFT        14
26935 #define IOMUXC_GPR_GPR11_GPR11_LOCK(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR11_LOCK_SHIFT))&IOMUXC_GPR_GPR11_GPR11_LOCK_MASK)
26936 /* GPR12 Bit Fields */
26937 #define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
26938 #define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
26939 #define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
26940 #define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
26941 #define IOMUXC_GPR_GPR12_PCIE_PHY_SSC_EN_MASK    0x8u
26942 #define IOMUXC_GPR_GPR12_PCIE_PHY_SSC_EN_SHIFT   3
26943 #define IOMUXC_GPR_GPR12_PCIE_PHY_CMN_REG_RST_MASK 0x10u
26944 #define IOMUXC_GPR_GPR12_PCIE_PHY_CMN_REG_RST_SHIFT 4
26945 #define IOMUXC_GPR_GPR12_PCIE_PHY_REFCLK_SEL_MASK 0x20u
26946 #define IOMUXC_GPR_GPR12_PCIE_PHY_REFCLK_SEL_SHIFT 5
26947 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
26948 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
26949 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_MASK)
26950 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
26951 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
26952 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
26953 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
26954 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
26955 #define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
26956 /* GPR13 Bit Fields */
26957 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK      0x1u
26958 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT     0
26959 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK      0x2u
26960 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT     1
26961 #define IOMUXC_GPR_GPR13_ARCACHE_PXP_MASK        0x4u
26962 #define IOMUXC_GPR_GPR13_ARCACHE_PXP_SHIFT       2
26963 #define IOMUXC_GPR_GPR13_AWCACHE_PXP_MASK        0x8u
26964 #define IOMUXC_GPR_GPR13_AWCACHE_PXP_SHIFT       3
26965 #define IOMUXC_GPR_GPR13_ARCACHE_PCIE_MASK       0x10u
26966 #define IOMUXC_GPR_GPR13_ARCACHE_PCIE_SHIFT      4
26967 #define IOMUXC_GPR_GPR13_AWCACHE_PCIE_MASK       0x20u
26968 #define IOMUXC_GPR_GPR13_AWCACHE_PCIE_SHIFT      5
26969 #define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_MASK      0x40u
26970 #define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_SHIFT     6
26971 #define IOMUXC_GPR_GPR13_ARCACHE_EPDC_MASK       0x80u
26972 #define IOMUXC_GPR_GPR13_ARCACHE_EPDC_SHIFT      7
26973 #define IOMUXC_GPR_GPR13_ARCACHE_PXP_EN_MASK     0x100u
26974 #define IOMUXC_GPR_GPR13_ARCACHE_PXP_EN_SHIFT    8
26975 #define IOMUXC_GPR_GPR13_AWCACHE_PXP_EN_MASK     0x200u
26976 #define IOMUXC_GPR_GPR13_AWCACHE_PXP_EN_SHIFT    9
26977 #define IOMUXC_GPR_GPR13_ARCACHE_PCIE_EN_MASK    0x400u
26978 #define IOMUXC_GPR_GPR13_ARCACHE_PCIE_EN_SHIFT   10
26979 #define IOMUXC_GPR_GPR13_AWCACHE_PCIE_EN_MASK    0x800u
26980 #define IOMUXC_GPR_GPR13_AWCACHE_PCIE_EN_SHIFT   11
26981 #define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_EN_MASK   0x1000u
26982 #define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_EN_SHIFT  12
26983 #define IOMUXC_GPR_GPR13_ARCACHE_EPDC_EN_MASK    0x2000u
26984 #define IOMUXC_GPR_GPR13_ARCACHE_EPDC_EN_SHIFT   13
26985 #define IOMUXC_GPR_GPR13_AWCACHE_EPDC_MASK       0x4000u
26986 #define IOMUXC_GPR_GPR13_AWCACHE_EPDC_SHIFT      14
26987 #define IOMUXC_GPR_GPR13_AWCACHE_EPDC_EN_MASK    0x8000u
26988 #define IOMUXC_GPR_GPR13_AWCACHE_EPDC_EN_SHIFT   15
26989 #define IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
26990 #define IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
26991 #define IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
26992 #define IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_MASK  0xF000000u
26993 #define IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_SHIFT 24
26994 #define IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_MASK)
26995 #define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
26996 #define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
26997 #define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
26998 #define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
26999 #define IOMUXC_GPR_GPR13_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
27000 #define IOMUXC_GPR_GPR13_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
27001 #define IOMUXC_GPR_GPR13_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
27002 #define IOMUXC_GPR_GPR13_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
27003 /* GPR14 Bit Fields */
27004 #define IOMUXC_GPR_GPR14_SIM1_SIMV2_EMV_SEL_MASK 0x1u
27005 #define IOMUXC_GPR_GPR14_SIM1_SIMV2_EMV_SEL_SHIFT 0
27006 #define IOMUXC_GPR_GPR14_SIM2_SIMV2_EMV_SEL_MASK 0x2u
27007 #define IOMUXC_GPR_GPR14_SIM2_SIMV2_EMV_SEL_SHIFT 1
27008 /* GPR15 Bit Fields */
27009 #define IOMUXC_GPR_GPR15_LVDS_I_VBLK_FLAG_MASK   0x1u
27010 #define IOMUXC_GPR_GPR15_LVDS_I_VBLK_FLAG_SHIFT  0
27011 #define IOMUXC_GPR_GPR15_LVDS_I_AUTO_SEL_MASK    0x2u
27012 #define IOMUXC_GPR_GPR15_LVDS_I_AUTO_SEL_SHIFT   1
27013 #define IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
27014 #define IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_SHIFT 2
27015 #define IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_MASK)
27016 #define IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
27017 #define IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_SHIFT 16
27018 #define IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_MASK)
27019 /* GPR16 Bit Fields */
27020 #define IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_MASK  0x3u
27021 #define IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_SHIFT 0
27022 #define IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_MASK)
27023 #define IOMUXC_GPR_GPR16_LVDS_SEL_DATABF_MASK    0x4u
27024 #define IOMUXC_GPR_GPR16_LVDS_SEL_DATABF_SHIFT   2
27025 #define IOMUXC_GPR_GPR16_LVDS_CNTB_TDLY_MASK     0x8u
27026 #define IOMUXC_GPR_GPR16_LVDS_CNTB_TDLY_SHIFT    3
27027 #define IOMUXC_GPR_GPR16_LVDS_SKEW_EN_H_MASK     0x10u
27028 #define IOMUXC_GPR_GPR16_LVDS_SKEW_EN_H_SHIFT    4
27029 #define IOMUXC_GPR_GPR16_LVDS_SKEWINI_MASK       0x20u
27030 #define IOMUXC_GPR_GPR16_LVDS_SKEWINI_SHIFT      5
27031 #define IOMUXC_GPR_GPR16_LVDS_SK_BIAS_MASK       0x3C0u
27032 #define IOMUXC_GPR_GPR16_LVDS_SK_BIAS_SHIFT      6
27033 #define IOMUXC_GPR_GPR16_LVDS_SK_BIAS(x)         (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_LVDS_SK_BIAS_MASK)
27034 #define IOMUXC_GPR_GPR16_LVDS_AUTO_DSK_SEL_MASK  0x400u
27035 #define IOMUXC_GPR_GPR16_LVDS_AUTO_DSK_SEL_SHIFT 10
27036 #define IOMUXC_GPR_GPR16_LVDS_LOCK_CNT_MASK      0x800u
27037 #define IOMUXC_GPR_GPR16_LVDS_LOCK_CNT_SHIFT     11
27038 #define IOMUXC_GPR_GPR16_LVDS_OUTCON_MASK        0x1000u
27039 #define IOMUXC_GPR_GPR16_LVDS_OUTCON_SHIFT       12
27040 #define IOMUXC_GPR_GPR16_LVDS_FC_CODE_MASK       0xE000u
27041 #define IOMUXC_GPR_GPR16_LVDS_FC_CODE_SHIFT      13
27042 #define IOMUXC_GPR_GPR16_LVDS_FC_CODE(x)         (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_LVDS_FC_CODE_MASK)
27043 #define IOMUXC_GPR_GPR16_LVDS_SRC_TRH_MASK       0x10000u
27044 #define IOMUXC_GPR_GPR16_LVDS_SRC_TRH_SHIFT      16
27045 #define IOMUXC_GPR_GPR16_LVDS_VOD_HIGH_S_MASK    0x20000u
27046 #define IOMUXC_GPR_GPR16_LVDS_VOD_HIGH_S_SHIFT   17
27047 #define IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_MASK     0x180000u
27048 #define IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_SHIFT    19
27049 #define IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_MASK)
27050 #define IOMUXC_GPR_GPR16_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
27051 #define IOMUXC_GPR_GPR16_LVDS_CNNCT_MODE_SEL_SHIFT 21
27052 #define IOMUXC_GPR_GPR16_LVDS_FLT_CNT_MASK       0x400000u
27053 #define IOMUXC_GPR_GPR16_LVDS_FLT_CNT_SHIFT      22
27054 #define IOMUXC_GPR_GPR16_LVDS_VOD_ONLY_CNT_MASK  0x800000u
27055 #define IOMUXC_GPR_GPR16_LVDS_VOD_ONLY_CNT_SHIFT 23
27056 /* GPR17 Bit Fields */
27057 #define IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_MASK     0xFFu
27058 #define IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_SHIFT    0
27059 #define IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_MASK)
27060 #define IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_MASK     0xFF00u
27061 #define IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_SHIFT    8
27062 #define IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_MASK)
27063 /* GPR18 Bit Fields */
27064 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_MASK 0x7u
27065 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_SHIFT 0
27066 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_MASK)
27067 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_MASK 0x18u
27068 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_SHIFT 3
27069 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_MASK)
27070 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_MASK 0x60u
27071 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_SHIFT 5
27072 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_MASK)
27073 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
27074 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
27075 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_MASK)
27076 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
27077 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
27078 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
27079 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_SHIFT 16
27080 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_MASK)
27081 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
27082 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_SHIFT 24
27083 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_MASK)
27084 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_EN_MASK     0x4000000u
27085 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_EN_SHIFT    26
27086 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_RESETB_MASK 0x8000000u
27087 #define IOMUXC_GPR_GPR18_LVDS_I_BIST_RESETB_SHIFT 27
27088 #define IOMUXC_GPR_GPR18_LVDS_DLYS_BST_MASK      0x10000000u
27089 #define IOMUXC_GPR_GPR18_LVDS_DLYS_BST_SHIFT     28
27090 #define IOMUXC_GPR_GPR18_LVDS_SKINI_BST_MASK     0x20000000u
27091 #define IOMUXC_GPR_GPR18_LVDS_SKINI_BST_SHIFT    29
27092 /* GPR19 Bit Fields */
27093 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_STATUS_MASK 0x1u
27094 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_STATUS_SHIFT 0
27095 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
27096 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_SHIFT 8
27097 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_MASK)
27098 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_SYNC_MASK   0x10000u
27099 #define IOMUXC_GPR_GPR19_LVDS_O_BIST_SYNC_SHIFT  16
27100 #define IOMUXC_GPR_GPR19_LVDS_MON_FOR_CNNCT_MASK 0x20000u
27101 #define IOMUXC_GPR_GPR19_LVDS_MON_FOR_CNNCT_SHIFT 17
27102 /* GPR20 Bit Fields */
27103 #define IOMUXC_GPR_GPR20_LVDS_P_MASK             0x3Fu
27104 #define IOMUXC_GPR_GPR20_LVDS_P_SHIFT            0
27105 #define IOMUXC_GPR_GPR20_LVDS_P(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_LVDS_P_MASK)
27106 #define IOMUXC_GPR_GPR20_LVDS_M_MASK             0x3F00u
27107 #define IOMUXC_GPR_GPR20_LVDS_M_SHIFT            8
27108 #define IOMUXC_GPR_GPR20_LVDS_M(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_LVDS_M_MASK)
27109 #define IOMUXC_GPR_GPR20_LVDS_S_MASK             0x30000u
27110 #define IOMUXC_GPR_GPR20_LVDS_S_SHIFT            16
27111 #define IOMUXC_GPR_GPR20_LVDS_S(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_LVDS_S_MASK)
27112 #define IOMUXC_GPR_GPR20_LVDS_VSEL_MASK          0x1000000u
27113 #define IOMUXC_GPR_GPR20_LVDS_VSEL_SHIFT         24
27114 #define IOMUXC_GPR_GPR20_LVDS_CK_POL_SEL_MASK    0x2000000u
27115 #define IOMUXC_GPR_GPR20_LVDS_CK_POL_SEL_SHIFT   25
27116 #define IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
27117 #define IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_SHIFT 27
27118 #define IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_MASK)
27119 /* GPR21 Bit Fields */
27120 #define IOMUXC_GPR_GPR21_LVDS_SKC0_MASK          0x7u
27121 #define IOMUXC_GPR_GPR21_LVDS_SKC0_SHIFT         0
27122 #define IOMUXC_GPR_GPR21_LVDS_SKC0(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC0_MASK)
27123 #define IOMUXC_GPR_GPR21_LVDS_SKC1_MASK          0x38u
27124 #define IOMUXC_GPR_GPR21_LVDS_SKC1_SHIFT         3
27125 #define IOMUXC_GPR_GPR21_LVDS_SKC1(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC1_MASK)
27126 #define IOMUXC_GPR_GPR21_LVDS_SKC2_MASK          0x1C0u
27127 #define IOMUXC_GPR_GPR21_LVDS_SKC2_SHIFT         6
27128 #define IOMUXC_GPR_GPR21_LVDS_SKC2(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC2_MASK)
27129 #define IOMUXC_GPR_GPR21_LVDS_SKCCK_MASK         0xE00u
27130 #define IOMUXC_GPR_GPR21_LVDS_SKCCK_SHIFT        9
27131 #define IOMUXC_GPR_GPR21_LVDS_SKCCK(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKCCK_MASK)
27132 #define IOMUXC_GPR_GPR21_LVDS_SKC3_MASK          0x7000u
27133 #define IOMUXC_GPR_GPR21_LVDS_SKC3_SHIFT         12
27134 #define IOMUXC_GPR_GPR21_LVDS_SKC3(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC3_MASK)
27135 #define IOMUXC_GPR_GPR21_LVDS_SKC4_MASK          0x38000u
27136 #define IOMUXC_GPR_GPR21_LVDS_SKC4_SHIFT         15
27137 #define IOMUXC_GPR_GPR21_LVDS_SKC4(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC4_MASK)
27138 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK  0x40000u
27139 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
27140 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK  0x80000u
27141 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
27142 /* GPR22 Bit Fields */
27143 #define IOMUXC_GPR_GPR22_DDRC_MRR_DATA_MASK      0xFF0000u
27144 #define IOMUXC_GPR_GPR22_DDRC_MRR_DATA_SHIFT     16
27145 #define IOMUXC_GPR_GPR22_DDRC_MRR_DATA(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_DDRC_MRR_DATA_SHIFT))&IOMUXC_GPR_GPR22_DDRC_MRR_DATA_MASK)
27146 #define IOMUXC_GPR_GPR22_DDRC_MRR_VALID_MASK     0x1000000u
27147 #define IOMUXC_GPR_GPR22_DDRC_MRR_VALID_SHIFT    24
27148 #define IOMUXC_GPR_GPR22_DFI_INIT_COMPLETE_MASK  0x2000000u
27149 #define IOMUXC_GPR_GPR22_DFI_INIT_COMPLETE_SHIFT 25
27150 #define IOMUXC_GPR_GPR22_CHD2_DVDD_STABLE_MASK   0x4000000u
27151 #define IOMUXC_GPR_GPR22_CHD2_DVDD_STABLE_SHIFT  26
27152 #define IOMUXC_GPR_GPR22_CHD2_ISO_ENA_1_MASK     0x8000000u
27153 #define IOMUXC_GPR_GPR22_CHD2_ISO_ENA_1_SHIFT    27
27154 #define IOMUXC_GPR_GPR22_CHD1_DVDD_STABLE_MASK   0x10000000u
27155 #define IOMUXC_GPR_GPR22_CHD1_DVDD_STABLE_SHIFT  28
27156 #define IOMUXC_GPR_GPR22_CHD1_ISO_ENA_1_MASK     0x20000000u
27157 #define IOMUXC_GPR_GPR22_CHD1_ISO_ENA_1_SHIFT    29
27158 #define IOMUXC_GPR_GPR22_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
27159 #define IOMUXC_GPR_GPR22_PCIE_PHY_PLL_LOCKED_SHIFT 31
27160 
27161 /*!
27162  * @}
27163  */ /* end of group IOMUXC_GPR_Register_Masks */
27164 
27165 /* IOMUXC_GPR - Peripheral instance base addresses */
27166 /** Peripheral IOMUXC_GPR base address */
27167 #define IOMUXC_GPR_BASE                          (0x30340000u)
27168 /** Peripheral IOMUXC_GPR base pointer */
27169 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
27170 #define IOMUXC_GPR_BASE_PTR                      (IOMUXC_GPR)
27171 /** Array initializer of IOMUXC_GPR peripheral base addresses */
27172 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
27173 /** Array initializer of IOMUXC_GPR peripheral base pointers */
27174 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
27175 /** Interrupt vectors for the IOMUXC_GPR peripheral type */
27176 #define IOMUXC_GPR_IRQS                          { GPR_IRQn }
27177 /* ----------------------------------------------------------------------------
27178    -- IOMUXC_GPR - Register accessor macros
27179    ---------------------------------------------------------------------------- */
27180 
27181 /*!
27182  * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros
27183  * @{
27184  */
27185 
27186 
27187 /* IOMUXC_GPR - Register instance definitions */
27188 /* IOMUXC_GPR */
27189 #define IOMUXC_GPR_GPR0                          IOMUXC_GPR_GPR0_REG(IOMUXC_GPR_BASE_PTR)
27190 #define IOMUXC_GPR_GPR1                          IOMUXC_GPR_GPR1_REG(IOMUXC_GPR_BASE_PTR)
27191 #define IOMUXC_GPR_GPR2                          IOMUXC_GPR_GPR2_REG(IOMUXC_GPR_BASE_PTR)
27192 #define IOMUXC_GPR_GPR3                          IOMUXC_GPR_GPR3_REG(IOMUXC_GPR_BASE_PTR)
27193 #define IOMUXC_GPR_GPR4                          IOMUXC_GPR_GPR4_REG(IOMUXC_GPR_BASE_PTR)
27194 #define IOMUXC_GPR_GPR5                          IOMUXC_GPR_GPR5_REG(IOMUXC_GPR_BASE_PTR)
27195 #define IOMUXC_GPR_GPR6                          IOMUXC_GPR_GPR6_REG(IOMUXC_GPR_BASE_PTR)
27196 #define IOMUXC_GPR_GPR7                          IOMUXC_GPR_GPR7_REG(IOMUXC_GPR_BASE_PTR)
27197 #define IOMUXC_GPR_GPR8                          IOMUXC_GPR_GPR8_REG(IOMUXC_GPR_BASE_PTR)
27198 #define IOMUXC_GPR_GPR9                          IOMUXC_GPR_GPR9_REG(IOMUXC_GPR_BASE_PTR)
27199 #define IOMUXC_GPR_GPR10                         IOMUXC_GPR_GPR10_REG(IOMUXC_GPR_BASE_PTR)
27200 #define IOMUXC_GPR_GPR11                         IOMUXC_GPR_GPR11_REG(IOMUXC_GPR_BASE_PTR)
27201 #define IOMUXC_GPR_GPR12                         IOMUXC_GPR_GPR12_REG(IOMUXC_GPR_BASE_PTR)
27202 #define IOMUXC_GPR_GPR13                         IOMUXC_GPR_GPR13_REG(IOMUXC_GPR_BASE_PTR)
27203 #define IOMUXC_GPR_GPR14                         IOMUXC_GPR_GPR14_REG(IOMUXC_GPR_BASE_PTR)
27204 #define IOMUXC_GPR_GPR15                         IOMUXC_GPR_GPR15_REG(IOMUXC_GPR_BASE_PTR)
27205 #define IOMUXC_GPR_GPR16                         IOMUXC_GPR_GPR16_REG(IOMUXC_GPR_BASE_PTR)
27206 #define IOMUXC_GPR_GPR17                         IOMUXC_GPR_GPR17_REG(IOMUXC_GPR_BASE_PTR)
27207 #define IOMUXC_GPR_GPR18                         IOMUXC_GPR_GPR18_REG(IOMUXC_GPR_BASE_PTR)
27208 #define IOMUXC_GPR_GPR19                         IOMUXC_GPR_GPR19_REG(IOMUXC_GPR_BASE_PTR)
27209 #define IOMUXC_GPR_GPR20                         IOMUXC_GPR_GPR20_REG(IOMUXC_GPR_BASE_PTR)
27210 #define IOMUXC_GPR_GPR21                         IOMUXC_GPR_GPR21_REG(IOMUXC_GPR_BASE_PTR)
27211 #define IOMUXC_GPR_GPR22                         IOMUXC_GPR_GPR22_REG(IOMUXC_GPR_BASE_PTR)
27212 /*!
27213  * @}
27214  */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */
27215 
27216 
27217 /*!
27218  * @}
27219  */ /* end of group IOMUXC_GPR_Peripheral */
27220 
27221 /* ----------------------------------------------------------------------------
27222    -- IOMUXC_LPSR Peripheral Access Layer
27223    ---------------------------------------------------------------------------- */
27224 
27225 /*!
27226  * @addtogroup IOMUXC_LPSR_Peripheral_Access_Layer IOMUXC_LPSR Peripheral Access Layer
27227  * @{
27228  */
27229 
27230 /** IOMUXC_LPSR - Register Layout Typedef */
27231 typedef struct {
27232   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO00;              /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register, offset: 0x0 */
27233   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO01;              /**< SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register, offset: 0x4 */
27234   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO02;              /**< SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register, offset: 0x8 */
27235   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO03;              /**< SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register, offset: 0xC */
27236   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO04;              /**< SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register, offset: 0x10 */
27237   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO05;              /**< SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register, offset: 0x14 */
27238   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO06;              /**< SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register, offset: 0x18 */
27239   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO07;              /**< SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register, offset: 0x1C */
27240   __IO  uint32_t SW_PAD_CTL_PAD_TEST_MODE;               /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0x20 */
27241   __IO  uint32_t SW_PAD_CTL_PAD_SRC_POR_B;               /**< SW_PAD_CTL_PAD_SRC_POR_B SW PAD Control Register, offset: 0x24 */
27242   __IO  uint32_t SW_PAD_CTL_PAD_BOOT_MODE0;              /**< SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register, offset: 0x28 */
27243   __IO  uint32_t SW_PAD_CTL_PAD_BOOT_MODE1;              /**< SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register, offset: 0x2C */
27244   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO00;              /**< SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register, offset: 0x30 */
27245   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO01;              /**< SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register, offset: 0x34 */
27246   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO02;              /**< SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register, offset: 0x38 */
27247   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO03;              /**< SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register, offset: 0x3C */
27248   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO04;              /**< SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register, offset: 0x40 */
27249   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO05;              /**< SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register, offset: 0x44 */
27250   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO06;              /**< SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register, offset: 0x48 */
27251   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO07;              /**< SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register, offset: 0x4C */
27252 } IOMUXC_LPSR_Type, *IOMUXC_LPSR_MemMapPtr;
27253 /* ----------------------------------------------------------------------------
27254    -- IOMUXC_LPSR - Register accessor macros
27255    ---------------------------------------------------------------------------- */
27256 
27257 /*!
27258  * @addtogroup IOMUXC_LPSR_Register_Accessor_Macros IOMUXC_LPSR - Register accessor macros
27259  * @{
27260  */
27261 
27262 
27263 /* IOMUXC_LPSR - Register accessors */
27264 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO00)
27265 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01)
27266 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02)
27267 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03)
27268 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04)
27269 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05)
27270 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06)
27271 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07)
27272 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(base) ((base)->SW_PAD_CTL_PAD_TEST_MODE)
27273 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(base) ((base)->SW_PAD_CTL_PAD_SRC_POR_B)
27274 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE0)
27275 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE1)
27276 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00)
27277 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01)
27278 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02)
27279 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03)
27280 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04)
27281 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05)
27282 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06)
27283 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07)
27284 
27285 /*!
27286  * @}
27287  */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */
27288 /* ----------------------------------------------------------------------------
27289    -- IOMUXC_LPSR Register Masks
27290    ---------------------------------------------------------------------------- */
27291 
27292 /*!
27293  * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks
27294  * @{
27295  */
27296 
27297 /* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */
27298 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u
27299 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0
27300 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK)
27301 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_SION_MASK 0x10u
27302 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_SION_SHIFT 4
27303 /* SW_MUX_CTL_PAD_GPIO1_IO01 Bit Fields */
27304 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK 0x7u
27305 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT 0
27306 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK)
27307 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_SION_MASK 0x10u
27308 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_SION_SHIFT 4
27309 /* SW_MUX_CTL_PAD_GPIO1_IO02 Bit Fields */
27310 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK 0x7u
27311 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT 0
27312 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK)
27313 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK 0x10u
27314 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_SION_SHIFT 4
27315 /* SW_MUX_CTL_PAD_GPIO1_IO03 Bit Fields */
27316 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK 0x7u
27317 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT 0
27318 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK)
27319 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK 0x10u
27320 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_SION_SHIFT 4
27321 /* SW_MUX_CTL_PAD_GPIO1_IO04 Bit Fields */
27322 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK 0x7u
27323 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT 0
27324 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK)
27325 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_SION_MASK 0x10u
27326 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_SION_SHIFT 4
27327 /* SW_MUX_CTL_PAD_GPIO1_IO05 Bit Fields */
27328 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK 0x7u
27329 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT 0
27330 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK)
27331 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_SION_MASK 0x10u
27332 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_SION_SHIFT 4
27333 /* SW_MUX_CTL_PAD_GPIO1_IO06 Bit Fields */
27334 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK 0x7u
27335 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT 0
27336 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK)
27337 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_SION_MASK 0x10u
27338 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_SION_SHIFT 4
27339 /* SW_MUX_CTL_PAD_GPIO1_IO07 Bit Fields */
27340 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK 0x7u
27341 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT 0
27342 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK)
27343 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_SION_MASK 0x10u
27344 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_SION_SHIFT 4
27345 /* SW_PAD_CTL_PAD_TEST_MODE Bit Fields */
27346 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK 0x3u
27347 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT 0
27348 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
27349 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK 0x4u
27350 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT 2
27351 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK 0x8u
27352 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT 3
27353 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PE_MASK 0x10u
27354 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PE_SHIFT 4
27355 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_MASK 0x60u
27356 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_SHIFT 5
27357 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_MASK)
27358 /* SW_PAD_CTL_PAD_SRC_POR_B Bit Fields */
27359 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_MASK 0x3u
27360 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_SHIFT 0
27361 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_MASK)
27362 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_SRE_MASK 0x4u
27363 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_SRE_SHIFT 2
27364 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_HYS_MASK 0x8u
27365 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_HYS_SHIFT 3
27366 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PE_MASK 0x10u
27367 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PE_SHIFT 4
27368 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_MASK 0x60u
27369 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_SHIFT 5
27370 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_MASK)
27371 /* SW_PAD_CTL_PAD_BOOT_MODE0 Bit Fields */
27372 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_MASK 0x3u
27373 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_SHIFT 0
27374 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_MASK)
27375 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_SRE_MASK 0x4u
27376 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_SRE_SHIFT 2
27377 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_HYS_MASK 0x8u
27378 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_HYS_SHIFT 3
27379 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PE_MASK 0x10u
27380 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PE_SHIFT 4
27381 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_MASK 0x60u
27382 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_SHIFT 5
27383 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_MASK)
27384 /* SW_PAD_CTL_PAD_BOOT_MODE1 Bit Fields */
27385 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_MASK 0x3u
27386 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_SHIFT 0
27387 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_MASK)
27388 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_SRE_MASK 0x4u
27389 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_SRE_SHIFT 2
27390 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_HYS_MASK 0x8u
27391 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_HYS_SHIFT 3
27392 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PE_MASK 0x10u
27393 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PE_SHIFT 4
27394 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_MASK 0x60u
27395 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_SHIFT 5
27396 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_MASK)
27397 /* SW_PAD_CTL_PAD_GPIO1_IO00 Bit Fields */
27398 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK 0x3u
27399 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT 0
27400 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK)
27401 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_MASK 0x4u
27402 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_SHIFT 2
27403 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_MASK 0x8u
27404 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_SHIFT 3
27405 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PE_MASK 0x10u
27406 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PE_SHIFT 4
27407 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_MASK 0x60u
27408 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_SHIFT 5
27409 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_MASK)
27410 /* SW_PAD_CTL_PAD_GPIO1_IO01 Bit Fields */
27411 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK 0x3u
27412 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT 0
27413 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK)
27414 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_MASK 0x4u
27415 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_SHIFT 2
27416 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_MASK 0x8u
27417 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_SHIFT 3
27418 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PE_MASK 0x10u
27419 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PE_SHIFT 4
27420 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_MASK 0x60u
27421 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_SHIFT 5
27422 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_MASK)
27423 /* SW_PAD_CTL_PAD_GPIO1_IO02 Bit Fields */
27424 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK 0x3u
27425 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT 0
27426 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK)
27427 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK 0x4u
27428 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_SHIFT 2
27429 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK 0x8u
27430 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_SHIFT 3
27431 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PE_MASK 0x10u
27432 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PE_SHIFT 4
27433 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_MASK 0x60u
27434 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_SHIFT 5
27435 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_MASK)
27436 /* SW_PAD_CTL_PAD_GPIO1_IO03 Bit Fields */
27437 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK 0x3u
27438 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT 0
27439 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK)
27440 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK 0x4u
27441 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_SHIFT 2
27442 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK 0x8u
27443 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_SHIFT 3
27444 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PE_MASK 0x10u
27445 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PE_SHIFT 4
27446 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_MASK 0x60u
27447 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_SHIFT 5
27448 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_MASK)
27449 /* SW_PAD_CTL_PAD_GPIO1_IO04 Bit Fields */
27450 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK 0x3u
27451 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT 0
27452 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK)
27453 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_MASK 0x4u
27454 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_SHIFT 2
27455 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_MASK 0x8u
27456 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_SHIFT 3
27457 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PE_MASK 0x10u
27458 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PE_SHIFT 4
27459 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_MASK 0x60u
27460 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_SHIFT 5
27461 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_MASK)
27462 /* SW_PAD_CTL_PAD_GPIO1_IO05 Bit Fields */
27463 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK 0x3u
27464 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT 0
27465 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK)
27466 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_MASK 0x4u
27467 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_SHIFT 2
27468 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_MASK 0x8u
27469 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_SHIFT 3
27470 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PE_MASK 0x10u
27471 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PE_SHIFT 4
27472 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_MASK 0x60u
27473 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_SHIFT 5
27474 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_MASK)
27475 /* SW_PAD_CTL_PAD_GPIO1_IO06 Bit Fields */
27476 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK 0x3u
27477 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT 0
27478 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK)
27479 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_MASK 0x4u
27480 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_SHIFT 2
27481 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_MASK 0x8u
27482 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_SHIFT 3
27483 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PE_MASK 0x10u
27484 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PE_SHIFT 4
27485 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_MASK 0x60u
27486 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_SHIFT 5
27487 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_MASK)
27488 /* SW_PAD_CTL_PAD_GPIO1_IO07 Bit Fields */
27489 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK 0x3u
27490 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT 0
27491 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK)
27492 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_MASK 0x4u
27493 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_SHIFT 2
27494 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_MASK 0x8u
27495 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_SHIFT 3
27496 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PE_MASK 0x10u
27497 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PE_SHIFT 4
27498 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_MASK 0x60u
27499 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_SHIFT 5
27500 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_MASK)
27501 
27502 /*!
27503  * @}
27504  */ /* end of group IOMUXC_LPSR_Register_Masks */
27505 
27506 /* IOMUXC_LPSR - Peripheral instance base addresses */
27507 /** Peripheral IOMUXC_LPSR base address */
27508 #define IOMUXC_LPSR_BASE                         (0x302C0000u)
27509 /** Peripheral IOMUXC_LPSR base pointer */
27510 #define IOMUXC_LPSR                              ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
27511 #define IOMUXC_LPSR_BASE_PTR                     (IOMUXC_LPSR)
27512 /** Array initializer of IOMUXC_LPSR peripheral base addresses */
27513 #define IOMUXC_LPSR_BASE_ADDRS                   { IOMUXC_LPSR_BASE }
27514 /** Array initializer of IOMUXC_LPSR peripheral base pointers */
27515 #define IOMUXC_LPSR_BASE_PTRS                    { IOMUXC_LPSR }
27516 /* ----------------------------------------------------------------------------
27517    -- IOMUXC_LPSR - Register accessor macros
27518    ---------------------------------------------------------------------------- */
27519 
27520 /*!
27521  * @addtogroup IOMUXC_LPSR_Register_Accessor_Macros IOMUXC_LPSR - Register accessor macros
27522  * @{
27523  */
27524 
27525 
27526 /* IOMUXC_LPSR - Register instance definitions */
27527 /* IOMUXC_LPSR */
27528 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_REG(IOMUXC_LPSR_BASE_PTR)
27529 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(IOMUXC_LPSR_BASE_PTR)
27530 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(IOMUXC_LPSR_BASE_PTR)
27531 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(IOMUXC_LPSR_BASE_PTR)
27532 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(IOMUXC_LPSR_BASE_PTR)
27533 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(IOMUXC_LPSR_BASE_PTR)
27534 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(IOMUXC_LPSR_BASE_PTR)
27535 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07    IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(IOMUXC_LPSR_BASE_PTR)
27536 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE     IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(IOMUXC_LPSR_BASE_PTR)
27537 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B     IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(IOMUXC_LPSR_BASE_PTR)
27538 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0    IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(IOMUXC_LPSR_BASE_PTR)
27539 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1    IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(IOMUXC_LPSR_BASE_PTR)
27540 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(IOMUXC_LPSR_BASE_PTR)
27541 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(IOMUXC_LPSR_BASE_PTR)
27542 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(IOMUXC_LPSR_BASE_PTR)
27543 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(IOMUXC_LPSR_BASE_PTR)
27544 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(IOMUXC_LPSR_BASE_PTR)
27545 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(IOMUXC_LPSR_BASE_PTR)
27546 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(IOMUXC_LPSR_BASE_PTR)
27547 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07    IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(IOMUXC_LPSR_BASE_PTR)
27548 /*!
27549  * @}
27550  */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */
27551 
27552 
27553 /*!
27554  * @}
27555  */ /* end of group IOMUXC_LPSR_Peripheral */
27556 
27557 /* ----------------------------------------------------------------------------
27558    -- IOMUXC_LPSR_GPR Peripheral Access Layer
27559    ---------------------------------------------------------------------------- */
27560 
27561 /*!
27562  * @addtogroup IOMUXC_LPSR_GPR_Peripheral_Access_Layer IOMUXC_LPSR_GPR Peripheral Access Layer
27563  * @{
27564  */
27565 
27566 /** IOMUXC_LPSR_GPR - Register Layout Typedef */
27567 typedef struct {
27568   __IO  uint32_t IOMUXC_LPSR_GPR0;                       /**< IOMUXC_LPSR General Purpose Register 0, offset: 0x0 */
27569   __IO  uint32_t IOMUXC_LPSR_GPR1;                       /**< IOMUXC_LPSR General Purpose Register 1, offset: 0x4 */
27570   __IO  uint32_t IOMUXC_LPSR_GPR2;                       /**< IOMUXC_LPSR General Purpose Register 2, offset: 0x8 */
27571   __IO  uint32_t IOMUXC_LPSR_GPR3;                       /**< IOMUXC_LPSR General Purpose Register 3, offset: 0xC */
27572   __IO  uint32_t IOMUXC_LPSR_GPR4;                       /**< IOMUXC_LPSR General Purpose Register 4, offset: 0x10 */
27573   __IO  uint32_t IOMUXC_LPSR_GPR5;                       /**< IOMUXC_LPSR General Purpose Register 5, offset: 0x14 */
27574   __IO  uint32_t IOMUXC_LPSR_GPR6;                       /**< IOMUXC_LPSR General Purpose Register 6, offset: 0x18 */
27575   __IO  uint32_t IOMUXC_LPSR_GPR7;                       /**< IOMUXC_LPSR General Purpose Register 7, offset: 0x1C */
27576   __IO  uint32_t IOMUXC_LPSR_GPR8;                       /**< IOMUXC_LPSR General Purpose Register 8, offset: 0x20 */
27577   __IO  uint32_t IOMUXC_LPSR_GPR9;                       /**< IOMUXC_LPSR General Purpose Register 9, offset: 0x24 */
27578   __IO  uint32_t IOMUXC_LPSR_GPR10;                      /**< IOMUXC_LPSR General Purpose Register 10, offset: 0x28 */
27579   __IO  uint32_t IOMUXC_LPSR_GPR11;                      /**< IOMUXC_LPSR General Purpose Register 11, offset: 0x2C */
27580   __IO  uint32_t IOMUXC_LPSR_GPR12;                      /**< IOMUXC_LPSR General Purpose Register 12, offset: 0x30 */
27581   __IO  uint32_t IOMUXC_LPSR_GPR13;                      /**< IOMUXC_LPSR General Purpose Register 13, offset: 0x34 */
27582   __IO  uint32_t IOMUXC_LPSR_GPR14;                      /**< IOMUXC_LPSR General Purpose Register 14, offset: 0x38 */
27583   __IO  uint32_t IOMUXC_LPSR_GPR15;                      /**< IOMUXC_LPSR General Purpose Register 15, offset: 0x3C */
27584   __IO  uint32_t IOMUXC_LPSR_GPR16;                      /**< IOMUXC_LPSR General Purpose Register 16, offset: 0x40 */
27585   __IO  uint32_t IOMUXC_LPSR_GPR17;                      /**< IOMUXC_LPSR General Purpose Register 17, offset: 0x44 */
27586   __IO  uint32_t IOMUXC_LPSR_GPR18;                      /**< IOMUXC_LPSR General Purpose Register 18, offset: 0x48 */
27587   __IO  uint32_t IOMUXC_LPSR_GPR19;                      /**< IOMUXC_LPSR General Purpose Register 19, offset: 0x4C */
27588   __IO  uint32_t IOMUXC_LPSR_GPR20;                      /**< IOMUXC_LPSR General Purpose Register 20, offset: 0x50 */
27589   __IO  uint32_t IOMUXC_LPSR_GPR21;                      /**< IOMUXC_LPSR General Purpose Register 21, offset: 0x54 */
27590   __IO  uint32_t IOMUXC_LPSR_GPR22;                      /**< IOMUXC_LPSR General Purpose Register 22, offset: 0x58 */
27591 } IOMUXC_LPSR_GPR_Type, *IOMUXC_LPSR_GPR_MemMapPtr;
27592 /* ----------------------------------------------------------------------------
27593    -- IOMUXC_LPSR_GPR - Register accessor macros
27594    ---------------------------------------------------------------------------- */
27595 
27596 /*!
27597  * @addtogroup IOMUXC_LPSR_GPR_Register_Accessor_Macros IOMUXC_LPSR_GPR - Register accessor macros
27598  * @{
27599  */
27600 
27601 
27602 /* IOMUXC_LPSR_GPR - Register accessors */
27603 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_REG(base) ((base)->IOMUXC_LPSR_GPR0)
27604 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_REG(base) ((base)->IOMUXC_LPSR_GPR1)
27605 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_REG(base) ((base)->IOMUXC_LPSR_GPR2)
27606 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_REG(base) ((base)->IOMUXC_LPSR_GPR3)
27607 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_REG(base) ((base)->IOMUXC_LPSR_GPR4)
27608 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_REG(base) ((base)->IOMUXC_LPSR_GPR5)
27609 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_REG(base) ((base)->IOMUXC_LPSR_GPR6)
27610 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_REG(base) ((base)->IOMUXC_LPSR_GPR7)
27611 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_REG(base) ((base)->IOMUXC_LPSR_GPR8)
27612 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_REG(base) ((base)->IOMUXC_LPSR_GPR9)
27613 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_REG(base) ((base)->IOMUXC_LPSR_GPR10)
27614 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_REG(base) ((base)->IOMUXC_LPSR_GPR11)
27615 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_REG(base) ((base)->IOMUXC_LPSR_GPR12)
27616 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_REG(base) ((base)->IOMUXC_LPSR_GPR13)
27617 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_REG(base) ((base)->IOMUXC_LPSR_GPR14)
27618 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_REG(base) ((base)->IOMUXC_LPSR_GPR15)
27619 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_REG(base) ((base)->IOMUXC_LPSR_GPR16)
27620 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_REG(base) ((base)->IOMUXC_LPSR_GPR17)
27621 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_REG(base) ((base)->IOMUXC_LPSR_GPR18)
27622 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_REG(base) ((base)->IOMUXC_LPSR_GPR19)
27623 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_REG(base) ((base)->IOMUXC_LPSR_GPR20)
27624 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_REG(base) ((base)->IOMUXC_LPSR_GPR21)
27625 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_REG(base) ((base)->IOMUXC_LPSR_GPR22)
27626 
27627 /*!
27628  * @}
27629  */ /* end of group IOMUXC_LPSR_GPR_Register_Accessor_Macros */
27630 /* ----------------------------------------------------------------------------
27631    -- IOMUXC_LPSR_GPR Register Masks
27632    ---------------------------------------------------------------------------- */
27633 
27634 /*!
27635  * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks
27636  * @{
27637  */
27638 
27639 /* IOMUXC_LPSR_GPR0 Bit Fields */
27640 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_MASK 0xFFFFFFFFu
27641 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_SHIFT 0
27642 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_MASK)
27643 /* IOMUXC_LPSR_GPR1 Bit Fields */
27644 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_MASK 0xFFFFFFFFu
27645 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_SHIFT 0
27646 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_MASK)
27647 /* IOMUXC_LPSR_GPR2 Bit Fields */
27648 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_MASK 0xFFFFFFFFu
27649 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_SHIFT 0
27650 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_MASK)
27651 /* IOMUXC_LPSR_GPR3 Bit Fields */
27652 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_MASK 0xFFFFu
27653 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_SHIFT 0
27654 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_MASK)
27655 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_MASK 0xFFFF0000u
27656 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_SHIFT 16
27657 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_MASK)
27658 /* IOMUXC_LPSR_GPR4 Bit Fields */
27659 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_MASK 0xFFFFu
27660 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_SHIFT 0
27661 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_MASK)
27662 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_MASK 0xFFFF0000u
27663 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_SHIFT 16
27664 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_MASK)
27665 /* IOMUXC_LPSR_GPR5 Bit Fields */
27666 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_MASK 0xFFFFFFFFu
27667 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_SHIFT 0
27668 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_MASK)
27669 /* IOMUXC_LPSR_GPR6 Bit Fields */
27670 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_MASK 0xFFFFFFFFu
27671 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_SHIFT 0
27672 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_MASK)
27673 /* IOMUXC_LPSR_GPR7 Bit Fields */
27674 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_MASK 0xFFFFFFFFu
27675 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_SHIFT 0
27676 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_MASK)
27677 /* IOMUXC_LPSR_GPR8 Bit Fields */
27678 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_MASK 0xFFFFFFFFu
27679 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_SHIFT 0
27680 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_MASK)
27681 /* IOMUXC_LPSR_GPR9 Bit Fields */
27682 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_MASK 0xFFFFFFFFu
27683 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_SHIFT 0
27684 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_MASK)
27685 /* IOMUXC_LPSR_GPR10 Bit Fields */
27686 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_MASK 0xFFFFu
27687 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_SHIFT 0
27688 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_MASK)
27689 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_MASK 0xFFFF0000u
27690 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_SHIFT 16
27691 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_MASK)
27692 /* IOMUXC_LPSR_GPR11 Bit Fields */
27693 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_MASK 0xFFFFu
27694 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_SHIFT 0
27695 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_MASK)
27696 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_MASK 0xFFFF0000u
27697 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_SHIFT 16
27698 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_MASK)
27699 /* IOMUXC_LPSR_GPR12 Bit Fields */
27700 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_MASK 0xFFFFFFFFu
27701 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_SHIFT 0
27702 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_MASK)
27703 /* IOMUXC_LPSR_GPR13 Bit Fields */
27704 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_MASK 0xFFFFu
27705 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_SHIFT 0
27706 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_MASK)
27707 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_MASK 0xFFFF0000u
27708 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_SHIFT 16
27709 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_MASK)
27710 /* IOMUXC_LPSR_GPR14 Bit Fields */
27711 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_MASK 0xFFFFFFFFu
27712 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_SHIFT 0
27713 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_MASK)
27714 /* IOMUXC_LPSR_GPR15 Bit Fields */
27715 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_MASK 0xFFFFFFFFu
27716 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_SHIFT 0
27717 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_MASK)
27718 /* IOMUXC_LPSR_GPR16 Bit Fields */
27719 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_MASK 0xFFFFFFFFu
27720 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_SHIFT 0
27721 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_MASK)
27722 /* IOMUXC_LPSR_GPR17 Bit Fields */
27723 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_MASK 0xFFFFFFFFu
27724 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_SHIFT 0
27725 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_MASK)
27726 /* IOMUXC_LPSR_GPR18 Bit Fields */
27727 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_MASK 0xFFFFFFFFu
27728 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_SHIFT 0
27729 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_MASK)
27730 /* IOMUXC_LPSR_GPR19 Bit Fields */
27731 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_MASK 0xFFFFFFFFu
27732 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_SHIFT 0
27733 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_MASK)
27734 /* IOMUXC_LPSR_GPR20 Bit Fields */
27735 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_MASK 0x3u
27736 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_SHIFT 0
27737 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_MASK)
27738 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_SRE_MASK 0x4u
27739 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_SRE_SHIFT 2
27740 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_HYS_MASK 0x8u
27741 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_HYS_SHIFT 3
27742 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PE_MASK 0x10u
27743 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PE_SHIFT 4
27744 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_MASK 0x60u
27745 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_SHIFT 5
27746 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_MASK)
27747 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_MUX_CTL_MASK 0x80u
27748 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_MUX_CTL_SHIFT 7
27749 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_MASK 0x300u
27750 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_SHIFT 8
27751 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_MASK)
27752 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_SRE_MASK 0x400u
27753 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_SRE_SHIFT 10
27754 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_HYS_MASK 0x800u
27755 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_HYS_SHIFT 11
27756 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PE_MASK 0x1000u
27757 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PE_SHIFT 12
27758 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_MASK 0x6000u
27759 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_SHIFT 13
27760 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_MASK)
27761 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_MUX_CTL_MASK 0x8000u
27762 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_MUX_CTL_SHIFT 15
27763 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_MASK 0x30000u
27764 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_SHIFT 16
27765 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_MASK)
27766 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_SRE_MASK 0x40000u
27767 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_SRE_SHIFT 18
27768 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_HYS_MASK 0x80000u
27769 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_HYS_SHIFT 19
27770 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PE_MASK 0x100000u
27771 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PE_SHIFT 20
27772 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_MASK 0x600000u
27773 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_SHIFT 21
27774 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_MASK)
27775 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_MUX_CTL_MASK 0x800000u
27776 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_MUX_CTL_SHIFT 23
27777 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_MASK 0x3000000u
27778 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_SHIFT 24
27779 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_MASK)
27780 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_SRE_MASK 0x4000000u
27781 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_SRE_SHIFT 26
27782 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_HYS_MASK 0x8000000u
27783 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_HYS_SHIFT 27
27784 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PE_MASK 0x10000000u
27785 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PE_SHIFT 28
27786 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_MASK 0x60000000u
27787 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_SHIFT 29
27788 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_MASK)
27789 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_MUX_CTL_MASK 0x80000000u
27790 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_MUX_CTL_SHIFT 31
27791 /* IOMUXC_LPSR_GPR21 Bit Fields */
27792 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_MASK 0x3u
27793 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_SHIFT 0
27794 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_MASK)
27795 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_SRE_MASK 0x4u
27796 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_SRE_SHIFT 2
27797 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_HYS_MASK 0x8u
27798 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_HYS_SHIFT 3
27799 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PE_MASK 0x10u
27800 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PE_SHIFT 4
27801 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_MASK 0x60u
27802 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_SHIFT 5
27803 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_MASK)
27804 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_MUX_CTL_MASK 0x80u
27805 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_MUX_CTL_SHIFT 7
27806 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_MASK 0x300u
27807 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_SHIFT 8
27808 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_MASK)
27809 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_SRE_MASK 0x400u
27810 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_SRE_SHIFT 10
27811 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_HYS_MASK 0x800u
27812 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_HYS_SHIFT 11
27813 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PE_MASK 0x1000u
27814 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PE_SHIFT 12
27815 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_MASK 0x6000u
27816 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_SHIFT 13
27817 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_MASK)
27818 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_MUX_CTL_MASK 0x8000u
27819 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_MUX_CTL_SHIFT 15
27820 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_MASK 0x30000u
27821 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_SHIFT 16
27822 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_MASK)
27823 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_SRE_MASK 0x40000u
27824 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_SRE_SHIFT 18
27825 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_HYS_MASK 0x80000u
27826 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_HYS_SHIFT 19
27827 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PE_MASK 0x100000u
27828 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PE_SHIFT 20
27829 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_MASK 0x600000u
27830 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_SHIFT 21
27831 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_MASK)
27832 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_MUX_CTL_MASK 0x800000u
27833 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_MUX_CTL_SHIFT 23
27834 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_MASK 0x3000000u
27835 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_SHIFT 24
27836 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_MASK)
27837 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_SRE_MASK 0x4000000u
27838 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_SRE_SHIFT 26
27839 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_HYS_MASK 0x8000000u
27840 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_HYS_SHIFT 27
27841 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PE_MASK 0x10000000u
27842 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PE_SHIFT 28
27843 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_MASK 0x60000000u
27844 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_SHIFT 29
27845 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_MASK)
27846 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_MUX_CTL_MASK 0x80000000u
27847 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_MUX_CTL_SHIFT 31
27848 /* IOMUXC_LPSR_GPR22 Bit Fields */
27849 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_MASK 0xFFFFu
27850 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_SHIFT 0
27851 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_MASK)
27852 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_MASK 0xFFFF0000u
27853 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_SHIFT 16
27854 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_MASK)
27855 
27856 /*!
27857  * @}
27858  */ /* end of group IOMUXC_LPSR_GPR_Register_Masks */
27859 
27860 /* IOMUXC_LPSR_GPR - Peripheral instance base addresses */
27861 /** Peripheral IOMUXC_LPSR_GPR base address */
27862 #define IOMUXC_LPSR_GPR_BASE                     (0x30270000u)
27863 /** Peripheral IOMUXC_LPSR_GPR base pointer */
27864 #define IOMUXC_LPSR_GPR                          ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
27865 #define IOMUXC_LPSR_GPR_BASE_PTR                 (IOMUXC_LPSR_GPR)
27866 /** Array initializer of IOMUXC_LPSR_GPR peripheral base addresses */
27867 #define IOMUXC_LPSR_GPR_BASE_ADDRS               { IOMUXC_LPSR_GPR_BASE }
27868 /** Array initializer of IOMUXC_LPSR_GPR peripheral base pointers */
27869 #define IOMUXC_LPSR_GPR_BASE_PTRS                { IOMUXC_LPSR_GPR }
27870 /* ----------------------------------------------------------------------------
27871    -- IOMUXC_LPSR_GPR - Register accessor macros
27872    ---------------------------------------------------------------------------- */
27873 
27874 /*!
27875  * @addtogroup IOMUXC_LPSR_GPR_Register_Accessor_Macros IOMUXC_LPSR_GPR - Register accessor macros
27876  * @{
27877  */
27878 
27879 
27880 /* IOMUXC_LPSR_GPR - Register instance definitions */
27881 /* IOMUXC_LPSR_GPR */
27882 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27883 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27884 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27885 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27886 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27887 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27888 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27889 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27890 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27891 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9         IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27892 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27893 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27894 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27895 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27896 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27897 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27898 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27899 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27900 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27901 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27902 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27903 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27904 #define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22        IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_REG(IOMUXC_LPSR_GPR_BASE_PTR)
27905 /*!
27906  * @}
27907  */ /* end of group IOMUXC_LPSR_GPR_Register_Accessor_Macros */
27908 
27909 
27910 /*!
27911  * @}
27912  */ /* end of group IOMUXC_LPSR_GPR_Peripheral */
27913 
27914 /* ----------------------------------------------------------------------------
27915    -- KPP Peripheral Access Layer
27916    ---------------------------------------------------------------------------- */
27917 
27918 /*!
27919  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
27920  * @{
27921  */
27922 
27923 /** KPP - Register Layout Typedef */
27924 typedef struct {
27925   __IO  uint16_t KPCR;                                   /**< Keypad Control Register, offset: 0x0 */
27926   __IO  uint16_t KPSR;                                   /**< Keypad Status Register, offset: 0x2 */
27927   __IO  uint16_t KDDR;                                   /**< Keypad Data Direction Register, offset: 0x4 */
27928   __IO  uint16_t KPDR;                                   /**< Keypad Data Register, offset: 0x6 */
27929 } KPP_Type, *KPP_MemMapPtr;
27930 /* ----------------------------------------------------------------------------
27931    -- KPP - Register accessor macros
27932    ---------------------------------------------------------------------------- */
27933 
27934 /*!
27935  * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros
27936  * @{
27937  */
27938 
27939 
27940 /* KPP - Register accessors */
27941 #define KPP_KPCR_REG(base)                       ((base)->KPCR)
27942 #define KPP_KPSR_REG(base)                       ((base)->KPSR)
27943 #define KPP_KDDR_REG(base)                       ((base)->KDDR)
27944 #define KPP_KPDR_REG(base)                       ((base)->KPDR)
27945 
27946 /*!
27947  * @}
27948  */ /* end of group KPP_Register_Accessor_Macros */
27949 /* ----------------------------------------------------------------------------
27950    -- KPP Register Masks
27951    ---------------------------------------------------------------------------- */
27952 
27953 /*!
27954  * @addtogroup KPP_Register_Masks KPP Register Masks
27955  * @{
27956  */
27957 
27958 /* KPCR Bit Fields */
27959 #define KPP_KPCR_KRE_MASK                        0xFFu
27960 #define KPP_KPCR_KRE_SHIFT                       0
27961 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KRE_SHIFT))&KPP_KPCR_KRE_MASK)
27962 #define KPP_KPCR_KCO_MASK                        0xFF00u
27963 #define KPP_KPCR_KCO_SHIFT                       8
27964 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KCO_SHIFT))&KPP_KPCR_KCO_MASK)
27965 /* KPSR Bit Fields */
27966 #define KPP_KPSR_KPKD_MASK                       0x1u
27967 #define KPP_KPSR_KPKD_SHIFT                      0
27968 #define KPP_KPSR_KPKR_MASK                       0x2u
27969 #define KPP_KPSR_KPKR_SHIFT                      1
27970 #define KPP_KPSR_KDSC_MASK                       0x4u
27971 #define KPP_KPSR_KDSC_SHIFT                      2
27972 #define KPP_KPSR_KRSS_MASK                       0x8u
27973 #define KPP_KPSR_KRSS_SHIFT                      3
27974 #define KPP_KPSR_KDIE_MASK                       0x100u
27975 #define KPP_KPSR_KDIE_SHIFT                      8
27976 #define KPP_KPSR_KRIE_MASK                       0x200u
27977 #define KPP_KPSR_KRIE_SHIFT                      9
27978 /* KDDR Bit Fields */
27979 #define KPP_KDDR_KRDD_MASK                       0xFFu
27980 #define KPP_KDDR_KRDD_SHIFT                      0
27981 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KRDD_SHIFT))&KPP_KDDR_KRDD_MASK)
27982 #define KPP_KDDR_KCDD_MASK                       0xFF00u
27983 #define KPP_KDDR_KCDD_SHIFT                      8
27984 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KCDD_SHIFT))&KPP_KDDR_KCDD_MASK)
27985 /* KPDR Bit Fields */
27986 #define KPP_KPDR_KRD_MASK                        0xFFu
27987 #define KPP_KPDR_KRD_SHIFT                       0
27988 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KRD_SHIFT))&KPP_KPDR_KRD_MASK)
27989 #define KPP_KPDR_KCD_MASK                        0xFF00u
27990 #define KPP_KPDR_KCD_SHIFT                       8
27991 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KCD_SHIFT))&KPP_KPDR_KCD_MASK)
27992 
27993 /*!
27994  * @}
27995  */ /* end of group KPP_Register_Masks */
27996 
27997 /* KPP - Peripheral instance base addresses */
27998 /** Peripheral KPP base address */
27999 #define KPP_BASE                                 (0x30320000u)
28000 /** Peripheral KPP base pointer */
28001 #define KPP                                      ((KPP_Type *)KPP_BASE)
28002 #define KPP_BASE_PTR                             (KPP)
28003 /** Array initializer of KPP peripheral base addresses */
28004 #define KPP_BASE_ADDRS                           { KPP_BASE }
28005 /** Array initializer of KPP peripheral base pointers */
28006 #define KPP_BASE_PTRS                            { KPP }
28007 /** Interrupt vectors for the KPP peripheral type */
28008 #define KPP_IRQS                                 { KPP_IRQn }
28009 /* ----------------------------------------------------------------------------
28010    -- KPP - Register accessor macros
28011    ---------------------------------------------------------------------------- */
28012 
28013 /*!
28014  * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros
28015  * @{
28016  */
28017 
28018 
28019 /* KPP - Register instance definitions */
28020 /* KPP */
28021 #define KPP_KPCR                                 KPP_KPCR_REG(KPP_BASE_PTR)
28022 #define KPP_KPSR                                 KPP_KPSR_REG(KPP_BASE_PTR)
28023 #define KPP_KDDR                                 KPP_KDDR_REG(KPP_BASE_PTR)
28024 #define KPP_KPDR                                 KPP_KPDR_REG(KPP_BASE_PTR)
28025 /*!
28026  * @}
28027  */ /* end of group KPP_Register_Accessor_Macros */
28028 
28029 
28030 /*!
28031  * @}
28032  */ /* end of group KPP_Peripheral */
28033 
28034 /* ----------------------------------------------------------------------------
28035    -- LCDIF Peripheral Access Layer
28036    ---------------------------------------------------------------------------- */
28037 
28038 /*!
28039  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
28040  * @{
28041  */
28042 
28043 /** LCDIF - Register Layout Typedef */
28044 typedef struct {
28045   __IO  uint32_t RL;                                     /**< eLCDIF General Control Register, offset: 0x0 */
28046   __IO  uint32_t RL_SET;                                 /**< eLCDIF General Control Register, offset: 0x4 */
28047   __IO  uint32_t RL_CLR;                                 /**< eLCDIF General Control Register, offset: 0x8 */
28048   __IO  uint32_t RL_TOG;                                 /**< eLCDIF General Control Register, offset: 0xC */
28049   __IO  uint32_t CTRL1;                                  /**< eLCDIF General Control1 Register, offset: 0x10 */
28050   __IO  uint32_t CTRL1_SET;                              /**< eLCDIF General Control1 Register, offset: 0x14 */
28051   __IO  uint32_t CTRL1_CLR;                              /**< eLCDIF General Control1 Register, offset: 0x18 */
28052   __IO  uint32_t CTRL1_TOG;                              /**< eLCDIF General Control1 Register, offset: 0x1C */
28053   __IO  uint32_t CTRL2;                                  /**< eLCDIF General Control2 Register, offset: 0x20 */
28054   __IO  uint32_t CTRL2_SET;                              /**< eLCDIF General Control2 Register, offset: 0x24 */
28055   __IO  uint32_t CTRL2_CLR;                              /**< eLCDIF General Control2 Register, offset: 0x28 */
28056   __IO  uint32_t CTRL2_TOG;                              /**< eLCDIF General Control2 Register, offset: 0x2C */
28057   __IO  uint32_t TRANSFER_COUNT;                         /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
28058   uint8_t RESERVED_0[12];
28059   __IO  uint32_t CUR_BUF;                                /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
28060   uint8_t RESERVED_1[12];
28061   __IO  uint32_t NEXT_BUF;                               /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
28062   uint8_t RESERVED_2[12];
28063   __IO  uint32_t TIMING;                                 /**< LCD Interface Timing Register, offset: 0x60 */
28064   uint8_t RESERVED_3[12];
28065   __IO  uint32_t VDCTRL0;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
28066   __IO  uint32_t VDCTRL0_SET;                            /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
28067   __IO  uint32_t VDCTRL0_CLR;                            /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
28068   __IO  uint32_t VDCTRL0_TOG;                            /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
28069   __IO  uint32_t VDCTRL1;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
28070   uint8_t RESERVED_4[12];
28071   __IO  uint32_t VDCTRL2;                                /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
28072   uint8_t RESERVED_5[12];
28073   __IO  uint32_t VDCTRL3;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
28074   uint8_t RESERVED_6[12];
28075   __IO  uint32_t VDCTRL4;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
28076   uint8_t RESERVED_7[12];
28077   __IO  uint32_t DVICTRL0;                               /**< Digital Video Interface Control0 Register, offset: 0xC0 */
28078   uint8_t RESERVED_8[12];
28079   __IO  uint32_t DVICTRL1;                               /**< Digital Video Interface Control1 Register, offset: 0xD0 */
28080   uint8_t RESERVED_9[12];
28081   __IO  uint32_t DVICTRL2;                               /**< Digital Video Interface Control2 Register, offset: 0xE0 */
28082   uint8_t RESERVED_10[12];
28083   __IO  uint32_t DVICTRL3;                               /**< Digital Video Interface Control3 Register, offset: 0xF0 */
28084   uint8_t RESERVED_11[12];
28085   __IO  uint32_t DVICTRL4;                               /**< Digital Video Interface Control4 Register, offset: 0x100 */
28086   uint8_t RESERVED_12[12];
28087   __IO  uint32_t CSC_COEFF0;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */
28088   uint8_t RESERVED_13[12];
28089   __IO  uint32_t CSC_COEFF1;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */
28090   uint8_t RESERVED_14[12];
28091   __IO  uint32_t CSC_COEFF2;                             /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */
28092   uint8_t RESERVED_15[12];
28093   __IO  uint32_t CSC_COEFF3;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */
28094   uint8_t RESERVED_16[12];
28095   __IO  uint32_t CSC_COEFF4;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */
28096   uint8_t RESERVED_17[12];
28097   __IO  uint32_t CSC_OFFSET;                             /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */
28098   uint8_t RESERVED_18[12];
28099   __IO  uint32_t CSC_LIMIT;                              /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */
28100   uint8_t RESERVED_19[12];
28101   __IO  uint32_t DATA;                                   /**< LCD Interface Data Register, offset: 0x180 */
28102   uint8_t RESERVED_20[12];
28103   __IO  uint32_t BM_ERROR_STAT;                          /**< Bus Master Error Status Register, offset: 0x190 */
28104   uint8_t RESERVED_21[12];
28105   __IO  uint32_t CRC_STAT;                               /**< CRC Status Register, offset: 0x1A0 */
28106   uint8_t RESERVED_22[12];
28107   __I   uint32_t STAT;                                   /**< LCD Interface Status Register, offset: 0x1B0 */
28108   uint8_t RESERVED_23[12];
28109   __I   uint32_t VERSION;                                /**< LCD Interface Version Register, offset: 0x1C0 */
28110   uint8_t RESERVED_24[12];
28111   __I   uint32_t DEBUG0;                                 /**< LCD Interface Debug0 Register, offset: 0x1D0 */
28112   uint8_t RESERVED_25[12];
28113   __I   uint32_t DEBUG1;                                 /**< LCD Interface Debug1 Register, offset: 0x1E0 */
28114   uint8_t RESERVED_26[12];
28115   __I   uint32_t DEBUG2;                                 /**< LCD Interface Debug2 Register, offset: 0x1F0 */
28116   uint8_t RESERVED_27[12];
28117   __IO  uint32_t THRES;                                  /**< eLCDIF Threshold Register, offset: 0x200 */
28118   uint8_t RESERVED_28[12];
28119   __IO  uint32_t AS_CTRL;                                /**< eLCDIF AS Buffer Control Register, offset: 0x210 */
28120   uint8_t RESERVED_29[12];
28121   __IO  uint32_t AS_BUF;                                 /**< Alpha Surface Buffer Pointer, offset: 0x220 */
28122   uint8_t RESERVED_30[12];
28123   __IO  uint32_t AS_NEXT_BUF;                            /**< , offset: 0x230 */
28124   uint8_t RESERVED_31[12];
28125   __IO  uint32_t AS_CLRKEYLOW;                           /**< eLCDIF Overlay Color Key Low, offset: 0x240 */
28126   uint8_t RESERVED_32[12];
28127   __IO  uint32_t AS_CLRKEYHIGH;                          /**< eLCDIF Overlay Color Key High, offset: 0x250 */
28128   uint8_t RESERVED_33[12];
28129   __IO  uint32_t SYNC_DELAY;                             /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */
28130   uint8_t RESERVED_34[12];
28131   __IO  uint32_t DEBUG3;                                 /**< eLCDIF Interface Debug3 Register, offset: 0x270 */
28132   uint8_t RESERVED_35[12];
28133   __IO  uint32_t DEBUG4;                                 /**< LCD Interface Debug4 , offset: 0x280 */
28134   uint8_t RESERVED_36[12];
28135   __IO  uint32_t DEBUG5;                                 /**< LCD Interface Debug5 , offset: 0x290 */
28136 } LCDIF_Type, *LCDIF_MemMapPtr;
28137 /* ----------------------------------------------------------------------------
28138    -- LCDIF - Register accessor macros
28139    ---------------------------------------------------------------------------- */
28140 
28141 /*!
28142  * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros
28143  * @{
28144  */
28145 
28146 
28147 /* LCDIF - Register accessors */
28148 #define LCDIF_RL_REG(base)                       ((base)->RL)
28149 #define LCDIF_RL_SET_REG(base)                   ((base)->RL_SET)
28150 #define LCDIF_RL_CLR_REG(base)                   ((base)->RL_CLR)
28151 #define LCDIF_RL_TOG_REG(base)                   ((base)->RL_TOG)
28152 #define LCDIF_CTRL1_REG(base)                    ((base)->CTRL1)
28153 #define LCDIF_CTRL1_SET_REG(base)                ((base)->CTRL1_SET)
28154 #define LCDIF_CTRL1_CLR_REG(base)                ((base)->CTRL1_CLR)
28155 #define LCDIF_CTRL1_TOG_REG(base)                ((base)->CTRL1_TOG)
28156 #define LCDIF_CTRL2_REG(base)                    ((base)->CTRL2)
28157 #define LCDIF_CTRL2_SET_REG(base)                ((base)->CTRL2_SET)
28158 #define LCDIF_CTRL2_CLR_REG(base)                ((base)->CTRL2_CLR)
28159 #define LCDIF_CTRL2_TOG_REG(base)                ((base)->CTRL2_TOG)
28160 #define LCDIF_TRANSFER_COUNT_REG(base)           ((base)->TRANSFER_COUNT)
28161 #define LCDIF_CUR_BUF_REG(base)                  ((base)->CUR_BUF)
28162 #define LCDIF_NEXT_BUF_REG(base)                 ((base)->NEXT_BUF)
28163 #define LCDIF_TIMING_REG(base)                   ((base)->TIMING)
28164 #define LCDIF_VDCTRL0_REG(base)                  ((base)->VDCTRL0)
28165 #define LCDIF_VDCTRL0_SET_REG(base)              ((base)->VDCTRL0_SET)
28166 #define LCDIF_VDCTRL0_CLR_REG(base)              ((base)->VDCTRL0_CLR)
28167 #define LCDIF_VDCTRL0_TOG_REG(base)              ((base)->VDCTRL0_TOG)
28168 #define LCDIF_VDCTRL1_REG(base)                  ((base)->VDCTRL1)
28169 #define LCDIF_VDCTRL2_REG(base)                  ((base)->VDCTRL2)
28170 #define LCDIF_VDCTRL3_REG(base)                  ((base)->VDCTRL3)
28171 #define LCDIF_VDCTRL4_REG(base)                  ((base)->VDCTRL4)
28172 #define LCDIF_DVICTRL0_REG(base)                 ((base)->DVICTRL0)
28173 #define LCDIF_DVICTRL1_REG(base)                 ((base)->DVICTRL1)
28174 #define LCDIF_DVICTRL2_REG(base)                 ((base)->DVICTRL2)
28175 #define LCDIF_DVICTRL3_REG(base)                 ((base)->DVICTRL3)
28176 #define LCDIF_DVICTRL4_REG(base)                 ((base)->DVICTRL4)
28177 #define LCDIF_CSC_COEFF0_REG(base)               ((base)->CSC_COEFF0)
28178 #define LCDIF_CSC_COEFF1_REG(base)               ((base)->CSC_COEFF1)
28179 #define LCDIF_CSC_COEFF2_REG(base)               ((base)->CSC_COEFF2)
28180 #define LCDIF_CSC_COEFF3_REG(base)               ((base)->CSC_COEFF3)
28181 #define LCDIF_CSC_COEFF4_REG(base)               ((base)->CSC_COEFF4)
28182 #define LCDIF_CSC_OFFSET_REG(base)               ((base)->CSC_OFFSET)
28183 #define LCDIF_CSC_LIMIT_REG(base)                ((base)->CSC_LIMIT)
28184 #define LCDIF_DATA_REG(base)                     ((base)->DATA)
28185 #define LCDIF_BM_ERROR_STAT_REG(base)            ((base)->BM_ERROR_STAT)
28186 #define LCDIF_CRC_STAT_REG(base)                 ((base)->CRC_STAT)
28187 #define LCDIF_STAT_REG(base)                     ((base)->STAT)
28188 #define LCDIF_VERSION_REG(base)                  ((base)->VERSION)
28189 #define LCDIF_DEBUG0_REG(base)                   ((base)->DEBUG0)
28190 #define LCDIF_DEBUG1_REG(base)                   ((base)->DEBUG1)
28191 #define LCDIF_DEBUG2_REG(base)                   ((base)->DEBUG2)
28192 #define LCDIF_THRES_REG(base)                    ((base)->THRES)
28193 #define LCDIF_AS_CTRL_REG(base)                  ((base)->AS_CTRL)
28194 #define LCDIF_AS_BUF_REG(base)                   ((base)->AS_BUF)
28195 #define LCDIF_AS_NEXT_BUF_REG(base)              ((base)->AS_NEXT_BUF)
28196 #define LCDIF_AS_CLRKEYLOW_REG(base)             ((base)->AS_CLRKEYLOW)
28197 #define LCDIF_AS_CLRKEYHIGH_REG(base)            ((base)->AS_CLRKEYHIGH)
28198 #define LCDIF_SYNC_DELAY_REG(base)               ((base)->SYNC_DELAY)
28199 #define LCDIF_DEBUG3_REG(base)                   ((base)->DEBUG3)
28200 #define LCDIF_DEBUG4_REG(base)                   ((base)->DEBUG4)
28201 #define LCDIF_DEBUG5_REG(base)                   ((base)->DEBUG5)
28202 
28203 /*!
28204  * @}
28205  */ /* end of group LCDIF_Register_Accessor_Macros */
28206 /* ----------------------------------------------------------------------------
28207    -- LCDIF Register Masks
28208    ---------------------------------------------------------------------------- */
28209 
28210 /*!
28211  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
28212  * @{
28213  */
28214 
28215 /* RL Bit Fields */
28216 #define LCDIF_RL_RUN_MASK                        0x1u
28217 #define LCDIF_RL_RUN_SHIFT                       0
28218 #define LCDIF_RL_DATA_FORMAT_24_BIT_MASK         0x2u
28219 #define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT        1
28220 #define LCDIF_RL_DATA_FORMAT_18_BIT_MASK         0x4u
28221 #define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT        2
28222 #define LCDIF_RL_DATA_FORMAT_16_BIT_MASK         0x8u
28223 #define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT        3
28224 #define LCDIF_RL_RSRVD0_MASK                     0x10u
28225 #define LCDIF_RL_RSRVD0_SHIFT                    4
28226 #define LCDIF_RL_MASTER_MASK                     0x20u
28227 #define LCDIF_RL_MASTER_SHIFT                    5
28228 #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK       0x40u
28229 #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT      6
28230 #define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK        0x80u
28231 #define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT       7
28232 #define LCDIF_RL_WORD_LENGTH_MASK                0x300u
28233 #define LCDIF_RL_WORD_LENGTH_SHIFT               8
28234 #define LCDIF_RL_WORD_LENGTH(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_WORD_LENGTH_SHIFT))&LCDIF_RL_WORD_LENGTH_MASK)
28235 #define LCDIF_RL_LCD_DATABUS_WIDTH_MASK          0xC00u
28236 #define LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT         10
28237 #define LCDIF_RL_LCD_DATABUS_WIDTH(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_LCD_DATABUS_WIDTH_MASK)
28238 #define LCDIF_RL_CSC_DATA_SWIZZLE_MASK           0x3000u
28239 #define LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT          12
28240 #define LCDIF_RL_CSC_DATA_SWIZZLE(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CSC_DATA_SWIZZLE_MASK)
28241 #define LCDIF_RL_INPUT_DATA_SWIZZLE_MASK         0xC000u
28242 #define LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT        14
28243 #define LCDIF_RL_INPUT_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_INPUT_DATA_SWIZZLE_MASK)
28244 #define LCDIF_RL_DATA_SELECT_MASK                0x10000u
28245 #define LCDIF_RL_DATA_SELECT_SHIFT               16
28246 #define LCDIF_RL_DOTCLK_MODE_MASK                0x20000u
28247 #define LCDIF_RL_DOTCLK_MODE_SHIFT               17
28248 #define LCDIF_RL_VSYNC_MODE_MASK                 0x40000u
28249 #define LCDIF_RL_VSYNC_MODE_SHIFT                18
28250 #define LCDIF_RL_BYPASS_COUNT_MASK               0x80000u
28251 #define LCDIF_RL_BYPASS_COUNT_SHIFT              19
28252 #define LCDIF_RL_DVI_MODE_MASK                   0x100000u
28253 #define LCDIF_RL_DVI_MODE_SHIFT                  20
28254 #define LCDIF_RL_SHIFT_NUM_BITS_MASK             0x3E00000u
28255 #define LCDIF_RL_SHIFT_NUM_BITS_SHIFT            21
28256 #define LCDIF_RL_SHIFT_NUM_BITS(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SHIFT_NUM_BITS_MASK)
28257 #define LCDIF_RL_DATA_SHIFT_DIR_MASK             0x4000000u
28258 #define LCDIF_RL_DATA_SHIFT_DIR_SHIFT            26
28259 #define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_MASK        0x8000000u
28260 #define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_SHIFT       27
28261 #define LCDIF_RL_READ_WRITEB_MASK                0x10000000u
28262 #define LCDIF_RL_READ_WRITEB_SHIFT               28
28263 #define LCDIF_RL_YCBCR422_INPUT_MASK             0x20000000u
28264 #define LCDIF_RL_YCBCR422_INPUT_SHIFT            29
28265 #define LCDIF_RL_CLKGATE_MASK                    0x40000000u
28266 #define LCDIF_RL_CLKGATE_SHIFT                   30
28267 #define LCDIF_RL_SFTRST_MASK                     0x80000000u
28268 #define LCDIF_RL_SFTRST_SHIFT                    31
28269 /* RL_SET Bit Fields */
28270 #define LCDIF_RL_SET_RUN_MASK                    0x1u
28271 #define LCDIF_RL_SET_RUN_SHIFT                   0
28272 #define LCDIF_RL_SET_DATA_FORMAT_24_BIT_MASK     0x2u
28273 #define LCDIF_RL_SET_DATA_FORMAT_24_BIT_SHIFT    1
28274 #define LCDIF_RL_SET_DATA_FORMAT_18_BIT_MASK     0x4u
28275 #define LCDIF_RL_SET_DATA_FORMAT_18_BIT_SHIFT    2
28276 #define LCDIF_RL_SET_DATA_FORMAT_16_BIT_MASK     0x8u
28277 #define LCDIF_RL_SET_DATA_FORMAT_16_BIT_SHIFT    3
28278 #define LCDIF_RL_SET_RSRVD0_MASK                 0x10u
28279 #define LCDIF_RL_SET_RSRVD0_SHIFT                4
28280 #define LCDIF_RL_SET_MASTER_MASK                 0x20u
28281 #define LCDIF_RL_SET_MASTER_SHIFT                5
28282 #define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_MASK   0x40u
28283 #define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_SHIFT  6
28284 #define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_MASK    0x80u
28285 #define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_SHIFT   7
28286 #define LCDIF_RL_SET_WORD_LENGTH_MASK            0x300u
28287 #define LCDIF_RL_SET_WORD_LENGTH_SHIFT           8
28288 #define LCDIF_RL_SET_WORD_LENGTH(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_WORD_LENGTH_SHIFT))&LCDIF_RL_SET_WORD_LENGTH_MASK)
28289 #define LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK      0xC00u
28290 #define LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT     10
28291 #define LCDIF_RL_SET_LCD_DATABUS_WIDTH(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK)
28292 #define LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK       0x3000u
28293 #define LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT      12
28294 #define LCDIF_RL_SET_CSC_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK)
28295 #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK     0xC000u
28296 #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT    14
28297 #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK)
28298 #define LCDIF_RL_SET_DATA_SELECT_MASK            0x10000u
28299 #define LCDIF_RL_SET_DATA_SELECT_SHIFT           16
28300 #define LCDIF_RL_SET_DOTCLK_MODE_MASK            0x20000u
28301 #define LCDIF_RL_SET_DOTCLK_MODE_SHIFT           17
28302 #define LCDIF_RL_SET_VSYNC_MODE_MASK             0x40000u
28303 #define LCDIF_RL_SET_VSYNC_MODE_SHIFT            18
28304 #define LCDIF_RL_SET_BYPASS_COUNT_MASK           0x80000u
28305 #define LCDIF_RL_SET_BYPASS_COUNT_SHIFT          19
28306 #define LCDIF_RL_SET_DVI_MODE_MASK               0x100000u
28307 #define LCDIF_RL_SET_DVI_MODE_SHIFT              20
28308 #define LCDIF_RL_SET_SHIFT_NUM_BITS_MASK         0x3E00000u
28309 #define LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT        21
28310 #define LCDIF_RL_SET_SHIFT_NUM_BITS(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SET_SHIFT_NUM_BITS_MASK)
28311 #define LCDIF_RL_SET_DATA_SHIFT_DIR_MASK         0x4000000u
28312 #define LCDIF_RL_SET_DATA_SHIFT_DIR_SHIFT        26
28313 #define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_MASK    0x8000000u
28314 #define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT   27
28315 #define LCDIF_RL_SET_READ_WRITEB_MASK            0x10000000u
28316 #define LCDIF_RL_SET_READ_WRITEB_SHIFT           28
28317 #define LCDIF_RL_SET_YCBCR422_INPUT_MASK         0x20000000u
28318 #define LCDIF_RL_SET_YCBCR422_INPUT_SHIFT        29
28319 #define LCDIF_RL_SET_CLKGATE_MASK                0x40000000u
28320 #define LCDIF_RL_SET_CLKGATE_SHIFT               30
28321 #define LCDIF_RL_SET_SFTRST_MASK                 0x80000000u
28322 #define LCDIF_RL_SET_SFTRST_SHIFT                31
28323 /* RL_CLR Bit Fields */
28324 #define LCDIF_RL_CLR_RUN_MASK                    0x1u
28325 #define LCDIF_RL_CLR_RUN_SHIFT                   0
28326 #define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_MASK     0x2u
28327 #define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_SHIFT    1
28328 #define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_MASK     0x4u
28329 #define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_SHIFT    2
28330 #define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_MASK     0x8u
28331 #define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_SHIFT    3
28332 #define LCDIF_RL_CLR_RSRVD0_MASK                 0x10u
28333 #define LCDIF_RL_CLR_RSRVD0_SHIFT                4
28334 #define LCDIF_RL_CLR_MASTER_MASK                 0x20u
28335 #define LCDIF_RL_CLR_MASTER_SHIFT                5
28336 #define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_MASK   0x40u
28337 #define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT  6
28338 #define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_MASK    0x80u
28339 #define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_SHIFT   7
28340 #define LCDIF_RL_CLR_WORD_LENGTH_MASK            0x300u
28341 #define LCDIF_RL_CLR_WORD_LENGTH_SHIFT           8
28342 #define LCDIF_RL_CLR_WORD_LENGTH(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_WORD_LENGTH_SHIFT))&LCDIF_RL_CLR_WORD_LENGTH_MASK)
28343 #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK      0xC00u
28344 #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT     10
28345 #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK)
28346 #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK       0x3000u
28347 #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT      12
28348 #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK)
28349 #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK     0xC000u
28350 #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT    14
28351 #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK)
28352 #define LCDIF_RL_CLR_DATA_SELECT_MASK            0x10000u
28353 #define LCDIF_RL_CLR_DATA_SELECT_SHIFT           16
28354 #define LCDIF_RL_CLR_DOTCLK_MODE_MASK            0x20000u
28355 #define LCDIF_RL_CLR_DOTCLK_MODE_SHIFT           17
28356 #define LCDIF_RL_CLR_VSYNC_MODE_MASK             0x40000u
28357 #define LCDIF_RL_CLR_VSYNC_MODE_SHIFT            18
28358 #define LCDIF_RL_CLR_BYPASS_COUNT_MASK           0x80000u
28359 #define LCDIF_RL_CLR_BYPASS_COUNT_SHIFT          19
28360 #define LCDIF_RL_CLR_DVI_MODE_MASK               0x100000u
28361 #define LCDIF_RL_CLR_DVI_MODE_SHIFT              20
28362 #define LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK         0x3E00000u
28363 #define LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT        21
28364 #define LCDIF_RL_CLR_SHIFT_NUM_BITS(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK)
28365 #define LCDIF_RL_CLR_DATA_SHIFT_DIR_MASK         0x4000000u
28366 #define LCDIF_RL_CLR_DATA_SHIFT_DIR_SHIFT        26
28367 #define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_MASK    0x8000000u
28368 #define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT   27
28369 #define LCDIF_RL_CLR_READ_WRITEB_MASK            0x10000000u
28370 #define LCDIF_RL_CLR_READ_WRITEB_SHIFT           28
28371 #define LCDIF_RL_CLR_YCBCR422_INPUT_MASK         0x20000000u
28372 #define LCDIF_RL_CLR_YCBCR422_INPUT_SHIFT        29
28373 #define LCDIF_RL_CLR_CLKGATE_MASK                0x40000000u
28374 #define LCDIF_RL_CLR_CLKGATE_SHIFT               30
28375 #define LCDIF_RL_CLR_SFTRST_MASK                 0x80000000u
28376 #define LCDIF_RL_CLR_SFTRST_SHIFT                31
28377 /* RL_TOG Bit Fields */
28378 #define LCDIF_RL_TOG_RUN_MASK                    0x1u
28379 #define LCDIF_RL_TOG_RUN_SHIFT                   0
28380 #define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_MASK     0x2u
28381 #define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_SHIFT    1
28382 #define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_MASK     0x4u
28383 #define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_SHIFT    2
28384 #define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_MASK     0x8u
28385 #define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_SHIFT    3
28386 #define LCDIF_RL_TOG_RSRVD0_MASK                 0x10u
28387 #define LCDIF_RL_TOG_RSRVD0_SHIFT                4
28388 #define LCDIF_RL_TOG_MASTER_MASK                 0x20u
28389 #define LCDIF_RL_TOG_MASTER_SHIFT                5
28390 #define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_MASK   0x40u
28391 #define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT  6
28392 #define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_MASK    0x80u
28393 #define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_SHIFT   7
28394 #define LCDIF_RL_TOG_WORD_LENGTH_MASK            0x300u
28395 #define LCDIF_RL_TOG_WORD_LENGTH_SHIFT           8
28396 #define LCDIF_RL_TOG_WORD_LENGTH(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_WORD_LENGTH_SHIFT))&LCDIF_RL_TOG_WORD_LENGTH_MASK)
28397 #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK      0xC00u
28398 #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT     10
28399 #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK)
28400 #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK       0x3000u
28401 #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT      12
28402 #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK)
28403 #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK     0xC000u
28404 #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT    14
28405 #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK)
28406 #define LCDIF_RL_TOG_DATA_SELECT_MASK            0x10000u
28407 #define LCDIF_RL_TOG_DATA_SELECT_SHIFT           16
28408 #define LCDIF_RL_TOG_DOTCLK_MODE_MASK            0x20000u
28409 #define LCDIF_RL_TOG_DOTCLK_MODE_SHIFT           17
28410 #define LCDIF_RL_TOG_VSYNC_MODE_MASK             0x40000u
28411 #define LCDIF_RL_TOG_VSYNC_MODE_SHIFT            18
28412 #define LCDIF_RL_TOG_BYPASS_COUNT_MASK           0x80000u
28413 #define LCDIF_RL_TOG_BYPASS_COUNT_SHIFT          19
28414 #define LCDIF_RL_TOG_DVI_MODE_MASK               0x100000u
28415 #define LCDIF_RL_TOG_DVI_MODE_SHIFT              20
28416 #define LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK         0x3E00000u
28417 #define LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT        21
28418 #define LCDIF_RL_TOG_SHIFT_NUM_BITS(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK)
28419 #define LCDIF_RL_TOG_DATA_SHIFT_DIR_MASK         0x4000000u
28420 #define LCDIF_RL_TOG_DATA_SHIFT_DIR_SHIFT        26
28421 #define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_MASK    0x8000000u
28422 #define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT   27
28423 #define LCDIF_RL_TOG_READ_WRITEB_MASK            0x10000000u
28424 #define LCDIF_RL_TOG_READ_WRITEB_SHIFT           28
28425 #define LCDIF_RL_TOG_YCBCR422_INPUT_MASK         0x20000000u
28426 #define LCDIF_RL_TOG_YCBCR422_INPUT_SHIFT        29
28427 #define LCDIF_RL_TOG_CLKGATE_MASK                0x40000000u
28428 #define LCDIF_RL_TOG_CLKGATE_SHIFT               30
28429 #define LCDIF_RL_TOG_SFTRST_MASK                 0x80000000u
28430 #define LCDIF_RL_TOG_SFTRST_SHIFT                31
28431 /* CTRL1 Bit Fields */
28432 #define LCDIF_CTRL1_RESET_MASK                   0x1u
28433 #define LCDIF_CTRL1_RESET_SHIFT                  0
28434 #define LCDIF_CTRL1_MODE86_MASK                  0x2u
28435 #define LCDIF_CTRL1_MODE86_SHIFT                 1
28436 #define LCDIF_CTRL1_BUSY_ENABLE_MASK             0x4u
28437 #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT            2
28438 #define LCDIF_CTRL1_RSRVD0_MASK                  0xF8u
28439 #define LCDIF_CTRL1_RSRVD0_SHIFT                 3
28440 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD0_SHIFT))&LCDIF_CTRL1_RSRVD0_MASK)
28441 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          0x100u
28442 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         8
28443 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      0x200u
28444 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     9
28445 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           0x400u
28446 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          10
28447 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            0x800u
28448 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           11
28449 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       0x1000u
28450 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      12
28451 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   0x2000u
28452 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  13
28453 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        0x4000u
28454 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       14
28455 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         0x8000u
28456 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        15
28457 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     0xF0000u
28458 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    16
28459 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
28460 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
28461 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
28462 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              0x200000u
28463 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             21
28464 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
28465 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
28466 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        0x800000u
28467 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       23
28468 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    0x1000000u
28469 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   24
28470 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            0x2000000u
28471 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           25
28472 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         0x4000000u
28473 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        26
28474 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK     0x8000000u
28475 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT    27
28476 #define LCDIF_CTRL1_RSRVD1_MASK                  0xF0000000u
28477 #define LCDIF_CTRL1_RSRVD1_SHIFT                 28
28478 #define LCDIF_CTRL1_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD1_SHIFT))&LCDIF_CTRL1_RSRVD1_MASK)
28479 /* CTRL1_SET Bit Fields */
28480 #define LCDIF_CTRL1_SET_RESET_MASK               0x1u
28481 #define LCDIF_CTRL1_SET_RESET_SHIFT              0
28482 #define LCDIF_CTRL1_SET_MODE86_MASK              0x2u
28483 #define LCDIF_CTRL1_SET_MODE86_SHIFT             1
28484 #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK         0x4u
28485 #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT        2
28486 #define LCDIF_CTRL1_SET_RSRVD0_MASK              0xF8u
28487 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             3
28488 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD0_SHIFT))&LCDIF_CTRL1_SET_RSRVD0_MASK)
28489 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      0x100u
28490 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     8
28491 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  0x200u
28492 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT 9
28493 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       0x400u
28494 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      10
28495 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        0x800u
28496 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       11
28497 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   0x1000u
28498 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  12
28499 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u
28500 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT 13
28501 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    0x4000u
28502 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   14
28503 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     0x8000u
28504 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    15
28505 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK 0xF0000u
28506 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT 16
28507 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
28508 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
28509 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
28510 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          0x200000u
28511 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         21
28512 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
28513 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
28514 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    0x800000u
28515 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   23
28516 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK 0x1000000u
28517 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT 24
28518 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        0x2000000u
28519 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       25
28520 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     0x4000000u
28521 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    26
28522 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK 0x8000000u
28523 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT 27
28524 #define LCDIF_CTRL1_SET_RSRVD1_MASK              0xF0000000u
28525 #define LCDIF_CTRL1_SET_RSRVD1_SHIFT             28
28526 #define LCDIF_CTRL1_SET_RSRVD1(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD1_SHIFT))&LCDIF_CTRL1_SET_RSRVD1_MASK)
28527 /* CTRL1_CLR Bit Fields */
28528 #define LCDIF_CTRL1_CLR_RESET_MASK               0x1u
28529 #define LCDIF_CTRL1_CLR_RESET_SHIFT              0
28530 #define LCDIF_CTRL1_CLR_MODE86_MASK              0x2u
28531 #define LCDIF_CTRL1_CLR_MODE86_SHIFT             1
28532 #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK         0x4u
28533 #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT        2
28534 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              0xF8u
28535 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             3
28536 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD0_SHIFT))&LCDIF_CTRL1_CLR_RSRVD0_MASK)
28537 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      0x100u
28538 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     8
28539 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  0x200u
28540 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT 9
28541 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       0x400u
28542 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      10
28543 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        0x800u
28544 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       11
28545 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   0x1000u
28546 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  12
28547 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u
28548 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT 13
28549 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    0x4000u
28550 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   14
28551 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     0x8000u
28552 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    15
28553 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK 0xF0000u
28554 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT 16
28555 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
28556 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
28557 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
28558 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          0x200000u
28559 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         21
28560 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
28561 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
28562 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    0x800000u
28563 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   23
28564 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK 0x1000000u
28565 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT 24
28566 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        0x2000000u
28567 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       25
28568 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     0x4000000u
28569 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    26
28570 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK 0x8000000u
28571 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT 27
28572 #define LCDIF_CTRL1_CLR_RSRVD1_MASK              0xF0000000u
28573 #define LCDIF_CTRL1_CLR_RSRVD1_SHIFT             28
28574 #define LCDIF_CTRL1_CLR_RSRVD1(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD1_SHIFT))&LCDIF_CTRL1_CLR_RSRVD1_MASK)
28575 /* CTRL1_TOG Bit Fields */
28576 #define LCDIF_CTRL1_TOG_RESET_MASK               0x1u
28577 #define LCDIF_CTRL1_TOG_RESET_SHIFT              0
28578 #define LCDIF_CTRL1_TOG_MODE86_MASK              0x2u
28579 #define LCDIF_CTRL1_TOG_MODE86_SHIFT             1
28580 #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK         0x4u
28581 #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT        2
28582 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              0xF8u
28583 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             3
28584 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD0_SHIFT))&LCDIF_CTRL1_TOG_RSRVD0_MASK)
28585 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      0x100u
28586 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     8
28587 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  0x200u
28588 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT 9
28589 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       0x400u
28590 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      10
28591 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        0x800u
28592 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       11
28593 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   0x1000u
28594 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  12
28595 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u
28596 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT 13
28597 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    0x4000u
28598 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   14
28599 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     0x8000u
28600 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    15
28601 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK 0xF0000u
28602 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT 16
28603 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
28604 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
28605 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
28606 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          0x200000u
28607 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         21
28608 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
28609 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
28610 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    0x800000u
28611 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   23
28612 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK 0x1000000u
28613 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT 24
28614 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        0x2000000u
28615 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       25
28616 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     0x4000000u
28617 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    26
28618 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK 0x8000000u
28619 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT 27
28620 #define LCDIF_CTRL1_TOG_RSRVD1_MASK              0xF0000000u
28621 #define LCDIF_CTRL1_TOG_RSRVD1_SHIFT             28
28622 #define LCDIF_CTRL1_TOG_RSRVD1(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD1_SHIFT))&LCDIF_CTRL1_TOG_RSRVD1_MASK)
28623 /* CTRL2 Bit Fields */
28624 #define LCDIF_CTRL2_RSRVD0_MASK                  0x1u
28625 #define LCDIF_CTRL2_RSRVD0_SHIFT                 0
28626 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK      0xEu
28627 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT     1
28628 #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK)
28629 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
28630 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
28631 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28632 #define LCDIF_CTRL2_RSRVD1_MASK                  0x80u
28633 #define LCDIF_CTRL2_RSRVD1_SHIFT                 7
28634 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK   0x100u
28635 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT  8
28636 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
28637 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
28638 #define LCDIF_CTRL2_READ_PACK_DIR_MASK           0x400u
28639 #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT          10
28640 #define LCDIF_CTRL2_RSRVD2_MASK                  0x800u
28641 #define LCDIF_CTRL2_RSRVD2_SHIFT                 11
28642 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       0x7000u
28643 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      12
28644 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
28645 #define LCDIF_CTRL2_RSRVD3_MASK                  0x8000u
28646 #define LCDIF_CTRL2_RSRVD3_SHIFT                 15
28647 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        0x70000u
28648 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       16
28649 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
28650 #define LCDIF_CTRL2_RSRVD4_MASK                  0x80000u
28651 #define LCDIF_CTRL2_RSRVD4_SHIFT                 19
28652 #define LCDIF_CTRL2_BURST_LEN_8_MASK             0x100000u
28653 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            20
28654 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        0xE00000u
28655 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       21
28656 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
28657 #define LCDIF_CTRL2_RSRVD5_MASK                  0xFF000000u
28658 #define LCDIF_CTRL2_RSRVD5_SHIFT                 24
28659 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_RSRVD5_SHIFT))&LCDIF_CTRL2_RSRVD5_MASK)
28660 /* CTRL2_SET Bit Fields */
28661 #define LCDIF_CTRL2_SET_RSRVD0_MASK              0x1u
28662 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             0
28663 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK  0xEu
28664 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT 1
28665 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK)
28666 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
28667 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
28668 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28669 #define LCDIF_CTRL2_SET_RSRVD1_MASK              0x80u
28670 #define LCDIF_CTRL2_SET_RSRVD1_SHIFT             7
28671 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK 0x100u
28672 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT 8
28673 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
28674 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
28675 #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK       0x400u
28676 #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT      10
28677 #define LCDIF_CTRL2_SET_RSRVD2_MASK              0x800u
28678 #define LCDIF_CTRL2_SET_RSRVD2_SHIFT             11
28679 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   0x7000u
28680 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  12
28681 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
28682 #define LCDIF_CTRL2_SET_RSRVD3_MASK              0x8000u
28683 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             15
28684 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    0x70000u
28685 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   16
28686 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
28687 #define LCDIF_CTRL2_SET_RSRVD4_MASK              0x80000u
28688 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             19
28689 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         0x100000u
28690 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        20
28691 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    0xE00000u
28692 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   21
28693 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
28694 #define LCDIF_CTRL2_SET_RSRVD5_MASK              0xFF000000u
28695 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             24
28696 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_RSRVD5_SHIFT))&LCDIF_CTRL2_SET_RSRVD5_MASK)
28697 /* CTRL2_CLR Bit Fields */
28698 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              0x1u
28699 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             0
28700 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK  0xEu
28701 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT 1
28702 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK)
28703 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
28704 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
28705 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28706 #define LCDIF_CTRL2_CLR_RSRVD1_MASK              0x80u
28707 #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT             7
28708 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK 0x100u
28709 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT 8
28710 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
28711 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
28712 #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK       0x400u
28713 #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT      10
28714 #define LCDIF_CTRL2_CLR_RSRVD2_MASK              0x800u
28715 #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT             11
28716 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   0x7000u
28717 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  12
28718 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
28719 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              0x8000u
28720 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             15
28721 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    0x70000u
28722 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   16
28723 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
28724 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              0x80000u
28725 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             19
28726 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         0x100000u
28727 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        20
28728 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    0xE00000u
28729 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   21
28730 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
28731 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              0xFF000000u
28732 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             24
28733 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_RSRVD5_SHIFT))&LCDIF_CTRL2_CLR_RSRVD5_MASK)
28734 /* CTRL2_TOG Bit Fields */
28735 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              0x1u
28736 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             0
28737 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK  0xEu
28738 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT 1
28739 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK)
28740 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
28741 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
28742 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28743 #define LCDIF_CTRL2_TOG_RSRVD1_MASK              0x80u
28744 #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT             7
28745 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK 0x100u
28746 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT 8
28747 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
28748 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
28749 #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK       0x400u
28750 #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT      10
28751 #define LCDIF_CTRL2_TOG_RSRVD2_MASK              0x800u
28752 #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT             11
28753 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   0x7000u
28754 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  12
28755 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
28756 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              0x8000u
28757 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             15
28758 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    0x70000u
28759 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   16
28760 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
28761 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              0x80000u
28762 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             19
28763 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         0x100000u
28764 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        20
28765 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    0xE00000u
28766 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   21
28767 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
28768 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              0xFF000000u
28769 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             24
28770 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_RSRVD5_SHIFT))&LCDIF_CTRL2_TOG_RSRVD5_MASK)
28771 /* TRANSFER_COUNT Bit Fields */
28772 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        0xFFFFu
28773 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       0
28774 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
28775 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        0xFFFF0000u
28776 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       16
28777 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
28778 /* CUR_BUF Bit Fields */
28779 #define LCDIF_CUR_BUF_ADDR_MASK                  0xFFFFFFFFu
28780 #define LCDIF_CUR_BUF_ADDR_SHIFT                 0
28781 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CUR_BUF_ADDR_SHIFT))&LCDIF_CUR_BUF_ADDR_MASK)
28782 /* NEXT_BUF Bit Fields */
28783 #define LCDIF_NEXT_BUF_ADDR_MASK                 0xFFFFFFFFu
28784 #define LCDIF_NEXT_BUF_ADDR_SHIFT                0
28785 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_NEXT_BUF_ADDR_SHIFT))&LCDIF_NEXT_BUF_ADDR_MASK)
28786 /* TIMING Bit Fields */
28787 #define LCDIF_TIMING_DATA_SETUP_MASK             0xFFu
28788 #define LCDIF_TIMING_DATA_SETUP_SHIFT            0
28789 #define LCDIF_TIMING_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_SETUP_SHIFT))&LCDIF_TIMING_DATA_SETUP_MASK)
28790 #define LCDIF_TIMING_DATA_HOLD_MASK              0xFF00u
28791 #define LCDIF_TIMING_DATA_HOLD_SHIFT             8
28792 #define LCDIF_TIMING_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_HOLD_SHIFT))&LCDIF_TIMING_DATA_HOLD_MASK)
28793 #define LCDIF_TIMING_CMD_SETUP_MASK              0xFF0000u
28794 #define LCDIF_TIMING_CMD_SETUP_SHIFT             16
28795 #define LCDIF_TIMING_CMD_SETUP(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_SETUP_SHIFT))&LCDIF_TIMING_CMD_SETUP_MASK)
28796 #define LCDIF_TIMING_CMD_HOLD_MASK               0xFF000000u
28797 #define LCDIF_TIMING_CMD_HOLD_SHIFT              24
28798 #define LCDIF_TIMING_CMD_HOLD(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_HOLD_SHIFT))&LCDIF_TIMING_CMD_HOLD_MASK)
28799 /* VDCTRL0 Bit Fields */
28800 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     0x3FFFFu
28801 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    0
28802 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
28803 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        0x40000u
28804 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       18
28805 #define LCDIF_VDCTRL0_HALF_LINE_MASK             0x80000u
28806 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            19
28807 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
28808 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
28809 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     0x200000u
28810 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    21
28811 #define LCDIF_VDCTRL0_RSRVD1_MASK                0xC00000u
28812 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               22
28813 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD1_SHIFT))&LCDIF_VDCTRL0_RSRVD1_MASK)
28814 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            0x1000000u
28815 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           24
28816 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            0x2000000u
28817 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           25
28818 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             0x4000000u
28819 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            26
28820 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             0x8000000u
28821 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            27
28822 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        0x10000000u
28823 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       28
28824 #define LCDIF_VDCTRL0_VSYNC_OEB_MASK             0x20000000u
28825 #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT            29
28826 #define LCDIF_VDCTRL0_RSRVD2_MASK                0xC0000000u
28827 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               30
28828 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD2_SHIFT))&LCDIF_VDCTRL0_RSRVD2_MASK)
28829 /* VDCTRL0_SET Bit Fields */
28830 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu
28831 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT 0
28832 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
28833 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    0x40000u
28834 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   18
28835 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         0x80000u
28836 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        19
28837 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
28838 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
28839 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK 0x200000u
28840 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT 21
28841 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            0xC00000u
28842 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           22
28843 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD1_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD1_MASK)
28844 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        0x1000000u
28845 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       24
28846 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        0x2000000u
28847 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       25
28848 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         0x4000000u
28849 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        26
28850 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         0x8000000u
28851 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        27
28852 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    0x10000000u
28853 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   28
28854 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK         0x20000000u
28855 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT        29
28856 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            0xC0000000u
28857 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           30
28858 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD2_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD2_MASK)
28859 /* VDCTRL0_CLR Bit Fields */
28860 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu
28861 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT 0
28862 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
28863 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    0x40000u
28864 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   18
28865 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         0x80000u
28866 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        19
28867 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
28868 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
28869 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK 0x200000u
28870 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT 21
28871 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            0xC00000u
28872 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           22
28873 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
28874 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        0x1000000u
28875 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       24
28876 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        0x2000000u
28877 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       25
28878 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         0x4000000u
28879 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        26
28880 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         0x8000000u
28881 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        27
28882 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    0x10000000u
28883 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   28
28884 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK         0x20000000u
28885 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT        29
28886 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            0xC0000000u
28887 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           30
28888 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
28889 /* VDCTRL0_TOG Bit Fields */
28890 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu
28891 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT 0
28892 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
28893 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    0x40000u
28894 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   18
28895 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         0x80000u
28896 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        19
28897 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
28898 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
28899 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK 0x200000u
28900 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT 21
28901 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            0xC00000u
28902 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           22
28903 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
28904 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        0x1000000u
28905 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       24
28906 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        0x2000000u
28907 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       25
28908 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         0x4000000u
28909 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        26
28910 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         0x8000000u
28911 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        27
28912 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    0x10000000u
28913 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   28
28914 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK         0x20000000u
28915 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT        29
28916 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            0xC0000000u
28917 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           30
28918 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
28919 /* VDCTRL1 Bit Fields */
28920 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          0xFFFFFFFFu
28921 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         0
28922 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
28923 /* VDCTRL2 Bit Fields */
28924 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          0x3FFFFu
28925 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         0
28926 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
28927 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     0xFFFC0000u
28928 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    18
28929 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
28930 /* VDCTRL3 Bit Fields */
28931 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     0xFFFFu
28932 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    0
28933 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
28934 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   0xFFF0000u
28935 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  16
28936 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
28937 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            0x10000000u
28938 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           28
28939 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      0x20000000u
28940 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     29
28941 #define LCDIF_VDCTRL3_RSRVD0_MASK                0xC0000000u
28942 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               30
28943 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_RSRVD0_SHIFT))&LCDIF_VDCTRL3_RSRVD0_MASK)
28944 /* VDCTRL4 Bit Fields */
28945 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3FFFFu
28946 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT 0
28947 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT))&LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
28948 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       0x40000u
28949 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      18
28950 #define LCDIF_VDCTRL4_RSRVD0_MASK                0x1FF80000u
28951 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               19
28952 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_RSRVD0_SHIFT))&LCDIF_VDCTRL4_RSRVD0_MASK)
28953 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        0xE0000000u
28954 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       29
28955 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT))&LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
28956 /* DVICTRL0 Bit Fields */
28957 #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK       0xFFFu
28958 #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT      0
28959 #define LCDIF_DVICTRL0_H_BLANKING_CNT(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT))&LCDIF_DVICTRL0_H_BLANKING_CNT_MASK)
28960 #define LCDIF_DVICTRL0_RSRVD0_MASK               0xF000u
28961 #define LCDIF_DVICTRL0_RSRVD0_SHIFT              12
28962 #define LCDIF_DVICTRL0_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD0_SHIFT))&LCDIF_DVICTRL0_RSRVD0_MASK)
28963 #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK         0xFFF0000u
28964 #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT        16
28965 #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT))&LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK)
28966 #define LCDIF_DVICTRL0_RSRVD1_MASK               0xF0000000u
28967 #define LCDIF_DVICTRL0_RSRVD1_SHIFT              28
28968 #define LCDIF_DVICTRL0_RSRVD1(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD1_SHIFT))&LCDIF_DVICTRL0_RSRVD1_MASK)
28969 /* DVICTRL1 Bit Fields */
28970 #define LCDIF_DVICTRL1_F2_START_LINE_MASK        0x3FFu
28971 #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT       0
28972 #define LCDIF_DVICTRL1_F2_START_LINE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F2_START_LINE_SHIFT))&LCDIF_DVICTRL1_F2_START_LINE_MASK)
28973 #define LCDIF_DVICTRL1_F1_END_LINE_MASK          0xFFC00u
28974 #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT         10
28975 #define LCDIF_DVICTRL1_F1_END_LINE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_END_LINE_SHIFT))&LCDIF_DVICTRL1_F1_END_LINE_MASK)
28976 #define LCDIF_DVICTRL1_F1_START_LINE_MASK        0x3FF00000u
28977 #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT       20
28978 #define LCDIF_DVICTRL1_F1_START_LINE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_START_LINE_SHIFT))&LCDIF_DVICTRL1_F1_START_LINE_MASK)
28979 #define LCDIF_DVICTRL1_RSRVD0_MASK               0xC0000000u
28980 #define LCDIF_DVICTRL1_RSRVD0_SHIFT              30
28981 #define LCDIF_DVICTRL1_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_RSRVD0_SHIFT))&LCDIF_DVICTRL1_RSRVD0_MASK)
28982 /* DVICTRL2 Bit Fields */
28983 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK    0x3FFu
28984 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT   0
28985 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK)
28986 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK  0xFFC00u
28987 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT 10
28988 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK)
28989 #define LCDIF_DVICTRL2_F2_END_LINE_MASK          0x3FF00000u
28990 #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT         20
28991 #define LCDIF_DVICTRL2_F2_END_LINE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_F2_END_LINE_SHIFT))&LCDIF_DVICTRL2_F2_END_LINE_MASK)
28992 #define LCDIF_DVICTRL2_RSRVD0_MASK               0xC0000000u
28993 #define LCDIF_DVICTRL2_RSRVD0_SHIFT              30
28994 #define LCDIF_DVICTRL2_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_RSRVD0_SHIFT))&LCDIF_DVICTRL2_RSRVD0_MASK)
28995 /* DVICTRL3 Bit Fields */
28996 #define LCDIF_DVICTRL3_V_LINES_CNT_MASK          0x3FFu
28997 #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT         0
28998 #define LCDIF_DVICTRL3_V_LINES_CNT(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V_LINES_CNT_SHIFT))&LCDIF_DVICTRL3_V_LINES_CNT_MASK)
28999 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK    0xFFC00u
29000 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT   10
29001 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK)
29002 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK  0x3FF00000u
29003 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT 20
29004 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK)
29005 #define LCDIF_DVICTRL3_RSRVD0_MASK               0xC0000000u
29006 #define LCDIF_DVICTRL3_RSRVD0_SHIFT              30
29007 #define LCDIF_DVICTRL3_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_RSRVD0_SHIFT))&LCDIF_DVICTRL3_RSRVD0_MASK)
29008 /* DVICTRL4 Bit Fields */
29009 #define LCDIF_DVICTRL4_H_FILL_CNT_MASK           0xFFu
29010 #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT          0
29011 #define LCDIF_DVICTRL4_H_FILL_CNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_H_FILL_CNT_SHIFT))&LCDIF_DVICTRL4_H_FILL_CNT_MASK)
29012 #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK        0xFF00u
29013 #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT       8
29014 #define LCDIF_DVICTRL4_CR_FILL_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CR_FILL_VALUE_MASK)
29015 #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK        0xFF0000u
29016 #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT       16
29017 #define LCDIF_DVICTRL4_CB_FILL_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CB_FILL_VALUE_MASK)
29018 #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK         0xFF000000u
29019 #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT        24
29020 #define LCDIF_DVICTRL4_Y_FILL_VALUE(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_Y_FILL_VALUE_MASK)
29021 /* CSC_COEFF0 Bit Fields */
29022 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK 0x3u
29023 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT 0
29024 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT))&LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK)
29025 #define LCDIF_CSC_COEFF0_RSRVD0_MASK             0xFFFCu
29026 #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT            2
29027 #define LCDIF_CSC_COEFF0_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD0_SHIFT))&LCDIF_CSC_COEFF0_RSRVD0_MASK)
29028 #define LCDIF_CSC_COEFF0_C0_MASK                 0x3FF0000u
29029 #define LCDIF_CSC_COEFF0_C0_SHIFT                16
29030 #define LCDIF_CSC_COEFF0_C0(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_C0_SHIFT))&LCDIF_CSC_COEFF0_C0_MASK)
29031 #define LCDIF_CSC_COEFF0_RSRVD1_MASK             0xFC000000u
29032 #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT            26
29033 #define LCDIF_CSC_COEFF0_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD1_SHIFT))&LCDIF_CSC_COEFF0_RSRVD1_MASK)
29034 /* CSC_COEFF1 Bit Fields */
29035 #define LCDIF_CSC_COEFF1_C1_MASK                 0x3FFu
29036 #define LCDIF_CSC_COEFF1_C1_SHIFT                0
29037 #define LCDIF_CSC_COEFF1_C1(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C1_SHIFT))&LCDIF_CSC_COEFF1_C1_MASK)
29038 #define LCDIF_CSC_COEFF1_RSRVD0_MASK             0xFC00u
29039 #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT            10
29040 #define LCDIF_CSC_COEFF1_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD0_SHIFT))&LCDIF_CSC_COEFF1_RSRVD0_MASK)
29041 #define LCDIF_CSC_COEFF1_C2_MASK                 0x3FF0000u
29042 #define LCDIF_CSC_COEFF1_C2_SHIFT                16
29043 #define LCDIF_CSC_COEFF1_C2(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C2_SHIFT))&LCDIF_CSC_COEFF1_C2_MASK)
29044 #define LCDIF_CSC_COEFF1_RSRVD1_MASK             0xFC000000u
29045 #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT            26
29046 #define LCDIF_CSC_COEFF1_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD1_SHIFT))&LCDIF_CSC_COEFF1_RSRVD1_MASK)
29047 /* CSC_COEFF2 Bit Fields */
29048 #define LCDIF_CSC_COEFF2_C3_MASK                 0x3FFu
29049 #define LCDIF_CSC_COEFF2_C3_SHIFT                0
29050 #define LCDIF_CSC_COEFF2_C3(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C3_SHIFT))&LCDIF_CSC_COEFF2_C3_MASK)
29051 #define LCDIF_CSC_COEFF2_RSRVD0_MASK             0xFC00u
29052 #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT            10
29053 #define LCDIF_CSC_COEFF2_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD0_SHIFT))&LCDIF_CSC_COEFF2_RSRVD0_MASK)
29054 #define LCDIF_CSC_COEFF2_C4_MASK                 0x3FF0000u
29055 #define LCDIF_CSC_COEFF2_C4_SHIFT                16
29056 #define LCDIF_CSC_COEFF2_C4(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C4_SHIFT))&LCDIF_CSC_COEFF2_C4_MASK)
29057 #define LCDIF_CSC_COEFF2_RSRVD1_MASK             0xFC000000u
29058 #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT            26
29059 #define LCDIF_CSC_COEFF2_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD1_SHIFT))&LCDIF_CSC_COEFF2_RSRVD1_MASK)
29060 /* CSC_COEFF3 Bit Fields */
29061 #define LCDIF_CSC_COEFF3_C5_MASK                 0x3FFu
29062 #define LCDIF_CSC_COEFF3_C5_SHIFT                0
29063 #define LCDIF_CSC_COEFF3_C5(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C5_SHIFT))&LCDIF_CSC_COEFF3_C5_MASK)
29064 #define LCDIF_CSC_COEFF3_RSRVD0_MASK             0xFC00u
29065 #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT            10
29066 #define LCDIF_CSC_COEFF3_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD0_SHIFT))&LCDIF_CSC_COEFF3_RSRVD0_MASK)
29067 #define LCDIF_CSC_COEFF3_C6_MASK                 0x3FF0000u
29068 #define LCDIF_CSC_COEFF3_C6_SHIFT                16
29069 #define LCDIF_CSC_COEFF3_C6(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C6_SHIFT))&LCDIF_CSC_COEFF3_C6_MASK)
29070 #define LCDIF_CSC_COEFF3_RSRVD1_MASK             0xFC000000u
29071 #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT            26
29072 #define LCDIF_CSC_COEFF3_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD1_SHIFT))&LCDIF_CSC_COEFF3_RSRVD1_MASK)
29073 /* CSC_COEFF4 Bit Fields */
29074 #define LCDIF_CSC_COEFF4_C7_MASK                 0x3FFu
29075 #define LCDIF_CSC_COEFF4_C7_SHIFT                0
29076 #define LCDIF_CSC_COEFF4_C7(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C7_SHIFT))&LCDIF_CSC_COEFF4_C7_MASK)
29077 #define LCDIF_CSC_COEFF4_RSRVD0_MASK             0xFC00u
29078 #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT            10
29079 #define LCDIF_CSC_COEFF4_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD0_SHIFT))&LCDIF_CSC_COEFF4_RSRVD0_MASK)
29080 #define LCDIF_CSC_COEFF4_C8_MASK                 0x3FF0000u
29081 #define LCDIF_CSC_COEFF4_C8_SHIFT                16
29082 #define LCDIF_CSC_COEFF4_C8(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C8_SHIFT))&LCDIF_CSC_COEFF4_C8_MASK)
29083 #define LCDIF_CSC_COEFF4_RSRVD1_MASK             0xFC000000u
29084 #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT            26
29085 #define LCDIF_CSC_COEFF4_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD1_SHIFT))&LCDIF_CSC_COEFF4_RSRVD1_MASK)
29086 /* CSC_OFFSET Bit Fields */
29087 #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK           0x1FFu
29088 #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT          0
29089 #define LCDIF_CSC_OFFSET_Y_OFFSET(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_Y_OFFSET_MASK)
29090 #define LCDIF_CSC_OFFSET_RSRVD0_MASK             0xFE00u
29091 #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT            9
29092 #define LCDIF_CSC_OFFSET_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD0_SHIFT))&LCDIF_CSC_OFFSET_RSRVD0_MASK)
29093 #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK        0x1FF0000u
29094 #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT       16
29095 #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK)
29096 #define LCDIF_CSC_OFFSET_RSRVD1_MASK             0xFE000000u
29097 #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT            25
29098 #define LCDIF_CSC_OFFSET_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD1_SHIFT))&LCDIF_CSC_OFFSET_RSRVD1_MASK)
29099 /* CSC_LIMIT Bit Fields */
29100 #define LCDIF_CSC_LIMIT_Y_MAX_MASK               0xFFu
29101 #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT              0
29102 #define LCDIF_CSC_LIMIT_Y_MAX(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MAX_SHIFT))&LCDIF_CSC_LIMIT_Y_MAX_MASK)
29103 #define LCDIF_CSC_LIMIT_Y_MIN_MASK               0xFF00u
29104 #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT              8
29105 #define LCDIF_CSC_LIMIT_Y_MIN(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MIN_SHIFT))&LCDIF_CSC_LIMIT_Y_MIN_MASK)
29106 #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK            0xFF0000u
29107 #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT           16
29108 #define LCDIF_CSC_LIMIT_CBCR_MAX(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MAX_MASK)
29109 #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK            0xFF000000u
29110 #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT           24
29111 #define LCDIF_CSC_LIMIT_CBCR_MIN(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MIN_MASK)
29112 /* DATA Bit Fields */
29113 #define LCDIF_DATA_DATA_ZERO_MASK                0xFFu
29114 #define LCDIF_DATA_DATA_ZERO_SHIFT               0
29115 #define LCDIF_DATA_DATA_ZERO(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ZERO_SHIFT))&LCDIF_DATA_DATA_ZERO_MASK)
29116 #define LCDIF_DATA_DATA_ONE_MASK                 0xFF00u
29117 #define LCDIF_DATA_DATA_ONE_SHIFT                8
29118 #define LCDIF_DATA_DATA_ONE(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ONE_SHIFT))&LCDIF_DATA_DATA_ONE_MASK)
29119 #define LCDIF_DATA_DATA_TWO_MASK                 0xFF0000u
29120 #define LCDIF_DATA_DATA_TWO_SHIFT                16
29121 #define LCDIF_DATA_DATA_TWO(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_TWO_SHIFT))&LCDIF_DATA_DATA_TWO_MASK)
29122 #define LCDIF_DATA_DATA_THREE_MASK               0xFF000000u
29123 #define LCDIF_DATA_DATA_THREE_SHIFT              24
29124 #define LCDIF_DATA_DATA_THREE(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_THREE_SHIFT))&LCDIF_DATA_DATA_THREE_MASK)
29125 /* BM_ERROR_STAT Bit Fields */
29126 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            0xFFFFFFFFu
29127 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           0
29128 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_BM_ERROR_STAT_ADDR_SHIFT))&LCDIF_BM_ERROR_STAT_ADDR_MASK)
29129 /* CRC_STAT Bit Fields */
29130 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            0xFFFFFFFFu
29131 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           0
29132 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_CRC_STAT_CRC_VALUE_SHIFT))&LCDIF_CRC_STAT_CRC_VALUE_MASK)
29133 /* STAT Bit Fields */
29134 #define LCDIF_STAT_LFIFO_COUNT_MASK              0x1FFu
29135 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             0
29136 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_LFIFO_COUNT_SHIFT))&LCDIF_STAT_LFIFO_COUNT_MASK)
29137 #define LCDIF_STAT_RSRVD0_MASK                   0xFFFE00u
29138 #define LCDIF_STAT_RSRVD0_SHIFT                  9
29139 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_RSRVD0_SHIFT))&LCDIF_STAT_RSRVD0_MASK)
29140 #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK        0x1000000u
29141 #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT       24
29142 #define LCDIF_STAT_BUSY_MASK                     0x2000000u
29143 #define LCDIF_STAT_BUSY_SHIFT                    25
29144 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             0x4000000u
29145 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            26
29146 #define LCDIF_STAT_TXFIFO_FULL_MASK              0x8000000u
29147 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             27
29148 #define LCDIF_STAT_LFIFO_EMPTY_MASK              0x10000000u
29149 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             28
29150 #define LCDIF_STAT_LFIFO_FULL_MASK               0x20000000u
29151 #define LCDIF_STAT_LFIFO_FULL_SHIFT              29
29152 #define LCDIF_STAT_PRESENT_MASK                  0x80000000u
29153 #define LCDIF_STAT_PRESENT_SHIFT                 31
29154 /* VERSION Bit Fields */
29155 #define LCDIF_VERSION_STEP_MASK                  0xFFFFu
29156 #define LCDIF_VERSION_STEP_SHIFT                 0
29157 #define LCDIF_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_STEP_SHIFT))&LCDIF_VERSION_STEP_MASK)
29158 #define LCDIF_VERSION_MINOR_MASK                 0xFF0000u
29159 #define LCDIF_VERSION_MINOR_SHIFT                16
29160 #define LCDIF_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MINOR_SHIFT))&LCDIF_VERSION_MINOR_MASK)
29161 #define LCDIF_VERSION_MAJOR_MASK                 0xFF000000u
29162 #define LCDIF_VERSION_MAJOR_SHIFT                24
29163 #define LCDIF_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MAJOR_SHIFT))&LCDIF_VERSION_MAJOR_MASK)
29164 /* DEBUG0 Bit Fields */
29165 #define LCDIF_DEBUG0_MST_WORDS_MASK              0xFu
29166 #define LCDIF_DEBUG0_MST_WORDS_SHIFT             0
29167 #define LCDIF_DEBUG0_MST_WORDS(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_WORDS_SHIFT))&LCDIF_DEBUG0_MST_WORDS_MASK)
29168 #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK   0x1F0u
29169 #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT  4
29170 #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK)
29171 #define LCDIF_DEBUG0_MST_AVALID_MASK             0x200u
29172 #define LCDIF_DEBUG0_MST_AVALID_SHIFT            9
29173 #define LCDIF_DEBUG0_CUR_REQ_STATE_MASK          0xC00u
29174 #define LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT         10
29175 #define LCDIF_DEBUG0_CUR_REQ_STATE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG0_CUR_REQ_STATE_MASK)
29176 #define LCDIF_DEBUG0_PXP_B1_DONE_MASK            0x1000u
29177 #define LCDIF_DEBUG0_PXP_B1_DONE_SHIFT           12
29178 #define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_MASK     0x2000u
29179 #define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_SHIFT    13
29180 #define LCDIF_DEBUG0_PXP_B0_DONE_MASK            0x4000u
29181 #define LCDIF_DEBUG0_PXP_B0_DONE_SHIFT           14
29182 #define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_MASK     0x8000u
29183 #define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_SHIFT    15
29184 #define LCDIF_DEBUG0_CUR_STATE_MASK              0x7F0000u
29185 #define LCDIF_DEBUG0_CUR_STATE_SHIFT             16
29186 #define LCDIF_DEBUG0_CUR_STATE(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_STATE_SHIFT))&LCDIF_DEBUG0_CUR_STATE_MASK)
29187 #define LCDIF_DEBUG0_EMPTY_WORD_MASK             0x800000u
29188 #define LCDIF_DEBUG0_EMPTY_WORD_SHIFT            23
29189 #define LCDIF_DEBUG0_CUR_FRAME_TX_MASK           0x1000000u
29190 #define LCDIF_DEBUG0_CUR_FRAME_TX_SHIFT          24
29191 #define LCDIF_DEBUG0_VSYNC_MASK                  0x2000000u
29192 #define LCDIF_DEBUG0_VSYNC_SHIFT                 25
29193 #define LCDIF_DEBUG0_HSYNC_MASK                  0x4000000u
29194 #define LCDIF_DEBUG0_HSYNC_SHIFT                 26
29195 #define LCDIF_DEBUG0_ENABLE_MASK                 0x8000000u
29196 #define LCDIF_DEBUG0_ENABLE_SHIFT                27
29197 #define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_MASK    0x20000000u
29198 #define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_SHIFT   29
29199 #define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_MASK 0x40000000u
29200 #define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_SHIFT 30
29201 #define LCDIF_DEBUG0_STREAMING_END_DETECTED_MASK 0x80000000u
29202 #define LCDIF_DEBUG0_STREAMING_END_DETECTED_SHIFT 31
29203 /* DEBUG1 Bit Fields */
29204 #define LCDIF_DEBUG1_V_DATA_COUNT_MASK           0xFFFFu
29205 #define LCDIF_DEBUG1_V_DATA_COUNT_SHIFT          0
29206 #define LCDIF_DEBUG1_V_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_V_DATA_COUNT_MASK)
29207 #define LCDIF_DEBUG1_H_DATA_COUNT_MASK           0xFFFF0000u
29208 #define LCDIF_DEBUG1_H_DATA_COUNT_SHIFT          16
29209 #define LCDIF_DEBUG1_H_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_H_DATA_COUNT_MASK)
29210 /* DEBUG2 Bit Fields */
29211 #define LCDIF_DEBUG2_MST_ADDRESS_MASK            0xFFFFFFFFu
29212 #define LCDIF_DEBUG2_MST_ADDRESS_SHIFT           0
29213 #define LCDIF_DEBUG2_MST_ADDRESS(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG2_MST_ADDRESS_SHIFT))&LCDIF_DEBUG2_MST_ADDRESS_MASK)
29214 /* THRES Bit Fields */
29215 #define LCDIF_THRES_PANIC_MASK                   0x1FFu
29216 #define LCDIF_THRES_PANIC_SHIFT                  0
29217 #define LCDIF_THRES_PANIC(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_PANIC_SHIFT))&LCDIF_THRES_PANIC_MASK)
29218 #define LCDIF_THRES_RSRVD1_MASK                  0xFE00u
29219 #define LCDIF_THRES_RSRVD1_SHIFT                 9
29220 #define LCDIF_THRES_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD1_SHIFT))&LCDIF_THRES_RSRVD1_MASK)
29221 #define LCDIF_THRES_FASTCLOCK_MASK               0x1FF0000u
29222 #define LCDIF_THRES_FASTCLOCK_SHIFT              16
29223 #define LCDIF_THRES_FASTCLOCK(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_FASTCLOCK_SHIFT))&LCDIF_THRES_FASTCLOCK_MASK)
29224 #define LCDIF_THRES_RSRVD2_MASK                  0xFE000000u
29225 #define LCDIF_THRES_RSRVD2_SHIFT                 25
29226 #define LCDIF_THRES_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD2_SHIFT))&LCDIF_THRES_RSRVD2_MASK)
29227 /* AS_CTRL Bit Fields */
29228 #define LCDIF_AS_CTRL_AS_ENABLE_MASK             0x1u
29229 #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT            0
29230 #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK            0x6u
29231 #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT           1
29232 #define LCDIF_AS_CTRL_ALPHA_CTRL(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT))&LCDIF_AS_CTRL_ALPHA_CTRL_MASK)
29233 #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK       0x8u
29234 #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT      3
29235 #define LCDIF_AS_CTRL_FORMAT_MASK                0xF0u
29236 #define LCDIF_AS_CTRL_FORMAT_SHIFT               4
29237 #define LCDIF_AS_CTRL_FORMAT(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_FORMAT_SHIFT))&LCDIF_AS_CTRL_FORMAT_MASK)
29238 #define LCDIF_AS_CTRL_ALPHA_MASK                 0xFF00u
29239 #define LCDIF_AS_CTRL_ALPHA_SHIFT                8
29240 #define LCDIF_AS_CTRL_ALPHA(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_SHIFT))&LCDIF_AS_CTRL_ALPHA_MASK)
29241 #define LCDIF_AS_CTRL_ROP_MASK                   0xF0000u
29242 #define LCDIF_AS_CTRL_ROP_SHIFT                  16
29243 #define LCDIF_AS_CTRL_ROP(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ROP_SHIFT))&LCDIF_AS_CTRL_ROP_MASK)
29244 #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK          0x100000u
29245 #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT         20
29246 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK    0x600000u
29247 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT   21
29248 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK)
29249 #define LCDIF_AS_CTRL_PS_DISABLE_MASK            0x800000u
29250 #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT           23
29251 #define LCDIF_AS_CTRL_RVDS1_MASK                 0x7000000u
29252 #define LCDIF_AS_CTRL_RVDS1_SHIFT                24
29253 #define LCDIF_AS_CTRL_RVDS1(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_RVDS1_SHIFT))&LCDIF_AS_CTRL_RVDS1_MASK)
29254 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK       0x8000000u
29255 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT      27
29256 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK    0x10000000u
29257 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT   28
29258 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK        0x20000000u
29259 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT       29
29260 #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK         0x40000000u
29261 #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT        30
29262 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK      0x80000000u
29263 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT     31
29264 /* AS_BUF Bit Fields */
29265 #define LCDIF_AS_BUF_ADDR_MASK                   0xFFFFFFFFu
29266 #define LCDIF_AS_BUF_ADDR_SHIFT                  0
29267 #define LCDIF_AS_BUF_ADDR(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_BUF_ADDR_SHIFT))&LCDIF_AS_BUF_ADDR_MASK)
29268 /* AS_NEXT_BUF Bit Fields */
29269 #define LCDIF_AS_NEXT_BUF_ADDR_MASK              0xFFFFFFFFu
29270 #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT             0
29271 #define LCDIF_AS_NEXT_BUF_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_NEXT_BUF_ADDR_SHIFT))&LCDIF_AS_NEXT_BUF_ADDR_MASK)
29272 /* AS_CLRKEYLOW Bit Fields */
29273 #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK            0xFFFFFFu
29274 #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT           0
29275 #define LCDIF_AS_CLRKEYLOW_PIXEL(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT))&LCDIF_AS_CLRKEYLOW_PIXEL_MASK)
29276 #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK            0xFF000000u
29277 #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT           24
29278 #define LCDIF_AS_CLRKEYLOW_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT))&LCDIF_AS_CLRKEYLOW_RSVD1_MASK)
29279 /* AS_CLRKEYHIGH Bit Fields */
29280 #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK           0xFFFFFFu
29281 #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT          0
29282 #define LCDIF_AS_CLRKEYHIGH_PIXEL(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT))&LCDIF_AS_CLRKEYHIGH_PIXEL_MASK)
29283 #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK           0xFF000000u
29284 #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT          24
29285 #define LCDIF_AS_CLRKEYHIGH_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT))&LCDIF_AS_CLRKEYHIGH_RSVD1_MASK)
29286 /* SYNC_DELAY Bit Fields */
29287 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK      0xFFFFu
29288 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT     0
29289 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK)
29290 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK      0xFFFF0000u
29291 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT     16
29292 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK)
29293 /* DEBUG3 Bit Fields */
29294 #define LCDIF_DEBUG3_MST_WORDS_MASK              0xFu
29295 #define LCDIF_DEBUG3_MST_WORDS_SHIFT             0
29296 #define LCDIF_DEBUG3_MST_WORDS(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_WORDS_SHIFT))&LCDIF_DEBUG3_MST_WORDS_MASK)
29297 #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK   0x1F0u
29298 #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT  4
29299 #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK)
29300 #define LCDIF_DEBUG3_MST_AVALID_MASK             0x200u
29301 #define LCDIF_DEBUG3_MST_AVALID_SHIFT            9
29302 #define LCDIF_DEBUG3_CUR_REQ_STATE_MASK          0xC00u
29303 #define LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT         10
29304 #define LCDIF_DEBUG3_CUR_REQ_STATE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG3_CUR_REQ_STATE_MASK)
29305 #define LCDIF_DEBUG3_RSVD0_MASK                  0xFFFFF000u
29306 #define LCDIF_DEBUG3_RSVD0_SHIFT                 12
29307 #define LCDIF_DEBUG3_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_RSVD0_SHIFT))&LCDIF_DEBUG3_RSVD0_MASK)
29308 /* DEBUG4 Bit Fields */
29309 #define LCDIF_DEBUG4_V_DATA_COUNT_MASK           0xFFFFu
29310 #define LCDIF_DEBUG4_V_DATA_COUNT_SHIFT          0
29311 #define LCDIF_DEBUG4_V_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_V_DATA_COUNT_MASK)
29312 #define LCDIF_DEBUG4_H_DATA_COUNT_MASK           0xFFFF0000u
29313 #define LCDIF_DEBUG4_H_DATA_COUNT_SHIFT          16
29314 #define LCDIF_DEBUG4_H_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_H_DATA_COUNT_MASK)
29315 /* DEBUG5 Bit Fields */
29316 #define LCDIF_DEBUG5_MST_ADDRESS_MASK            0xFFFFFFFFu
29317 #define LCDIF_DEBUG5_MST_ADDRESS_SHIFT           0
29318 #define LCDIF_DEBUG5_MST_ADDRESS(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG5_MST_ADDRESS_SHIFT))&LCDIF_DEBUG5_MST_ADDRESS_MASK)
29319 
29320 /*!
29321  * @}
29322  */ /* end of group LCDIF_Register_Masks */
29323 
29324 /* LCDIF - Peripheral instance base addresses */
29325 /** Peripheral LCDIF1 base address */
29326 #define LCDIF1_BASE                              (0x30730000u)
29327 /** Peripheral LCDIF1 base pointer */
29328 #define LCDIF1                                   ((LCDIF_Type *)LCDIF1_BASE)
29329 #define LCDIF1_BASE_PTR                          (LCDIF1)
29330 /** Peripheral LCDIF2 base address */
29331 #define LCDIF2_BASE                              (0x30734000u)
29332 /** Peripheral LCDIF2 base pointer */
29333 #define LCDIF2                                   ((LCDIF_Type *)LCDIF2_BASE)
29334 #define LCDIF2_BASE_PTR                          (LCDIF2)
29335 /** Array initializer of LCDIF peripheral base addresses */
29336 #define LCDIF_BASE_ADDRS                         { LCDIF1_BASE, LCDIF2_BASE }
29337 /** Array initializer of LCDIF peripheral base pointers */
29338 #define LCDIF_BASE_PTRS                          { LCDIF1, LCDIF2 }
29339 /* ----------------------------------------------------------------------------
29340    -- LCDIF - Register accessor macros
29341    ---------------------------------------------------------------------------- */
29342 
29343 /*!
29344  * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros
29345  * @{
29346  */
29347 
29348 
29349 /* LCDIF - Register instance definitions */
29350 /* LCDIF1 */
29351 #define LCDIF1_RL                                LCDIF_RL_REG(LCDIF1_BASE_PTR)
29352 #define LCDIF1_RL_SET                            LCDIF_RL_SET_REG(LCDIF1_BASE_PTR)
29353 #define LCDIF1_RL_CLR                            LCDIF_RL_CLR_REG(LCDIF1_BASE_PTR)
29354 #define LCDIF1_RL_TOG                            LCDIF_RL_TOG_REG(LCDIF1_BASE_PTR)
29355 #define LCDIF1_CTRL1                             LCDIF_CTRL1_REG(LCDIF1_BASE_PTR)
29356 #define LCDIF1_CTRL1_SET                         LCDIF_CTRL1_SET_REG(LCDIF1_BASE_PTR)
29357 #define LCDIF1_CTRL1_CLR                         LCDIF_CTRL1_CLR_REG(LCDIF1_BASE_PTR)
29358 #define LCDIF1_CTRL1_TOG                         LCDIF_CTRL1_TOG_REG(LCDIF1_BASE_PTR)
29359 #define LCDIF1_CTRL2                             LCDIF_CTRL2_REG(LCDIF1_BASE_PTR)
29360 #define LCDIF1_CTRL2_SET                         LCDIF_CTRL2_SET_REG(LCDIF1_BASE_PTR)
29361 #define LCDIF1_CTRL2_CLR                         LCDIF_CTRL2_CLR_REG(LCDIF1_BASE_PTR)
29362 #define LCDIF1_CTRL2_TOG                         LCDIF_CTRL2_TOG_REG(LCDIF1_BASE_PTR)
29363 #define LCDIF1_TRANSFER_COUNT                    LCDIF_TRANSFER_COUNT_REG(LCDIF1_BASE_PTR)
29364 #define LCDIF1_CUR_BUF                           LCDIF_CUR_BUF_REG(LCDIF1_BASE_PTR)
29365 #define LCDIF1_NEXT_BUF                          LCDIF_NEXT_BUF_REG(LCDIF1_BASE_PTR)
29366 #define LCDIF1_TIMING                            LCDIF_TIMING_REG(LCDIF1_BASE_PTR)
29367 #define LCDIF1_VDCTRL0                           LCDIF_VDCTRL0_REG(LCDIF1_BASE_PTR)
29368 #define LCDIF1_VDCTRL0_SET                       LCDIF_VDCTRL0_SET_REG(LCDIF1_BASE_PTR)
29369 #define LCDIF1_VDCTRL0_CLR                       LCDIF_VDCTRL0_CLR_REG(LCDIF1_BASE_PTR)
29370 #define LCDIF1_VDCTRL0_TOG                       LCDIF_VDCTRL0_TOG_REG(LCDIF1_BASE_PTR)
29371 #define LCDIF1_VDCTRL1                           LCDIF_VDCTRL1_REG(LCDIF1_BASE_PTR)
29372 #define LCDIF1_VDCTRL2                           LCDIF_VDCTRL2_REG(LCDIF1_BASE_PTR)
29373 #define LCDIF1_VDCTRL3                           LCDIF_VDCTRL3_REG(LCDIF1_BASE_PTR)
29374 #define LCDIF1_VDCTRL4                           LCDIF_VDCTRL4_REG(LCDIF1_BASE_PTR)
29375 #define LCDIF1_DVICTRL0                          LCDIF_DVICTRL0_REG(LCDIF1_BASE_PTR)
29376 #define LCDIF1_DVICTRL1                          LCDIF_DVICTRL1_REG(LCDIF1_BASE_PTR)
29377 #define LCDIF1_DVICTRL2                          LCDIF_DVICTRL2_REG(LCDIF1_BASE_PTR)
29378 #define LCDIF1_DVICTRL3                          LCDIF_DVICTRL3_REG(LCDIF1_BASE_PTR)
29379 #define LCDIF1_DVICTRL4                          LCDIF_DVICTRL4_REG(LCDIF1_BASE_PTR)
29380 #define LCDIF1_CSC_COEFF0                        LCDIF_CSC_COEFF0_REG(LCDIF1_BASE_PTR)
29381 #define LCDIF1_CSC_COEFF1                        LCDIF_CSC_COEFF1_REG(LCDIF1_BASE_PTR)
29382 #define LCDIF1_CSC_COEFF2                        LCDIF_CSC_COEFF2_REG(LCDIF1_BASE_PTR)
29383 #define LCDIF1_CSC_COEFF3                        LCDIF_CSC_COEFF3_REG(LCDIF1_BASE_PTR)
29384 #define LCDIF1_CSC_COEFF4                        LCDIF_CSC_COEFF4_REG(LCDIF1_BASE_PTR)
29385 #define LCDIF1_CSC_OFFSET                        LCDIF_CSC_OFFSET_REG(LCDIF1_BASE_PTR)
29386 #define LCDIF1_CSC_LIMIT                         LCDIF_CSC_LIMIT_REG(LCDIF1_BASE_PTR)
29387 #define LCDIF1_DATA                              LCDIF_DATA_REG(LCDIF1_BASE_PTR)
29388 #define LCDIF1_BM_ERROR_STAT                     LCDIF_BM_ERROR_STAT_REG(LCDIF1_BASE_PTR)
29389 #define LCDIF1_CRC_STAT                          LCDIF_CRC_STAT_REG(LCDIF1_BASE_PTR)
29390 #define LCDIF1_STAT                              LCDIF_STAT_REG(LCDIF1_BASE_PTR)
29391 #define LCDIF1_VERSION                           LCDIF_VERSION_REG(LCDIF1_BASE_PTR)
29392 #define LCDIF1_DEBUG0                            LCDIF_DEBUG0_REG(LCDIF1_BASE_PTR)
29393 #define LCDIF1_DEBUG1                            LCDIF_DEBUG1_REG(LCDIF1_BASE_PTR)
29394 #define LCDIF1_DEBUG2                            LCDIF_DEBUG2_REG(LCDIF1_BASE_PTR)
29395 #define LCDIF1_THRES                             LCDIF_THRES_REG(LCDIF1_BASE_PTR)
29396 #define LCDIF1_AS_CTRL                           LCDIF_AS_CTRL_REG(LCDIF1_BASE_PTR)
29397 #define LCDIF1_AS_BUF                            LCDIF_AS_BUF_REG(LCDIF1_BASE_PTR)
29398 #define LCDIF1_AS_NEXT_BUF                       LCDIF_AS_NEXT_BUF_REG(LCDIF1_BASE_PTR)
29399 #define LCDIF1_AS_CLRKEYLOW                      LCDIF_AS_CLRKEYLOW_REG(LCDIF1_BASE_PTR)
29400 #define LCDIF1_AS_CLRKEYHIGH                     LCDIF_AS_CLRKEYHIGH_REG(LCDIF1_BASE_PTR)
29401 #define LCDIF1_SYNC_DELAY                        LCDIF_SYNC_DELAY_REG(LCDIF1_BASE_PTR)
29402 #define LCDIF1_DEBUG3                            LCDIF_DEBUG3_REG(LCDIF1_BASE_PTR)
29403 #define LCDIF1_DEBUG4                            LCDIF_DEBUG4_REG(LCDIF1_BASE_PTR)
29404 #define LCDIF1_DEBUG5                            LCDIF_DEBUG5_REG(LCDIF1_BASE_PTR)
29405 /* LCDIF2 */
29406 #define LCDIF2_RL                                LCDIF_RL_REG(LCDIF2_BASE_PTR)
29407 #define LCDIF2_RL_SET                            LCDIF_RL_SET_REG(LCDIF2_BASE_PTR)
29408 #define LCDIF2_RL_CLR                            LCDIF_RL_CLR_REG(LCDIF2_BASE_PTR)
29409 #define LCDIF2_RL_TOG                            LCDIF_RL_TOG_REG(LCDIF2_BASE_PTR)
29410 #define LCDIF2_CTRL1                             LCDIF_CTRL1_REG(LCDIF2_BASE_PTR)
29411 #define LCDIF2_CTRL1_SET                         LCDIF_CTRL1_SET_REG(LCDIF2_BASE_PTR)
29412 #define LCDIF2_CTRL1_CLR                         LCDIF_CTRL1_CLR_REG(LCDIF2_BASE_PTR)
29413 #define LCDIF2_CTRL1_TOG                         LCDIF_CTRL1_TOG_REG(LCDIF2_BASE_PTR)
29414 #define LCDIF2_CTRL2                             LCDIF_CTRL2_REG(LCDIF2_BASE_PTR)
29415 #define LCDIF2_CTRL2_SET                         LCDIF_CTRL2_SET_REG(LCDIF2_BASE_PTR)
29416 #define LCDIF2_CTRL2_CLR                         LCDIF_CTRL2_CLR_REG(LCDIF2_BASE_PTR)
29417 #define LCDIF2_CTRL2_TOG                         LCDIF_CTRL2_TOG_REG(LCDIF2_BASE_PTR)
29418 #define LCDIF2_TRANSFER_COUNT                    LCDIF_TRANSFER_COUNT_REG(LCDIF2_BASE_PTR)
29419 #define LCDIF2_CUR_BUF                           LCDIF_CUR_BUF_REG(LCDIF2_BASE_PTR)
29420 #define LCDIF2_NEXT_BUF                          LCDIF_NEXT_BUF_REG(LCDIF2_BASE_PTR)
29421 #define LCDIF2_TIMING                            LCDIF_TIMING_REG(LCDIF2_BASE_PTR)
29422 #define LCDIF2_VDCTRL0                           LCDIF_VDCTRL0_REG(LCDIF2_BASE_PTR)
29423 #define LCDIF2_VDCTRL0_SET                       LCDIF_VDCTRL0_SET_REG(LCDIF2_BASE_PTR)
29424 #define LCDIF2_VDCTRL0_CLR                       LCDIF_VDCTRL0_CLR_REG(LCDIF2_BASE_PTR)
29425 #define LCDIF2_VDCTRL0_TOG                       LCDIF_VDCTRL0_TOG_REG(LCDIF2_BASE_PTR)
29426 #define LCDIF2_VDCTRL1                           LCDIF_VDCTRL1_REG(LCDIF2_BASE_PTR)
29427 #define LCDIF2_VDCTRL2                           LCDIF_VDCTRL2_REG(LCDIF2_BASE_PTR)
29428 #define LCDIF2_VDCTRL3                           LCDIF_VDCTRL3_REG(LCDIF2_BASE_PTR)
29429 #define LCDIF2_VDCTRL4                           LCDIF_VDCTRL4_REG(LCDIF2_BASE_PTR)
29430 #define LCDIF2_DVICTRL0                          LCDIF_DVICTRL0_REG(LCDIF2_BASE_PTR)
29431 #define LCDIF2_DVICTRL1                          LCDIF_DVICTRL1_REG(LCDIF2_BASE_PTR)
29432 #define LCDIF2_DVICTRL2                          LCDIF_DVICTRL2_REG(LCDIF2_BASE_PTR)
29433 #define LCDIF2_DVICTRL3                          LCDIF_DVICTRL3_REG(LCDIF2_BASE_PTR)
29434 #define LCDIF2_DVICTRL4                          LCDIF_DVICTRL4_REG(LCDIF2_BASE_PTR)
29435 #define LCDIF2_CSC_COEFF0                        LCDIF_CSC_COEFF0_REG(LCDIF2_BASE_PTR)
29436 #define LCDIF2_CSC_COEFF1                        LCDIF_CSC_COEFF1_REG(LCDIF2_BASE_PTR)
29437 #define LCDIF2_CSC_COEFF2                        LCDIF_CSC_COEFF2_REG(LCDIF2_BASE_PTR)
29438 #define LCDIF2_CSC_COEFF3                        LCDIF_CSC_COEFF3_REG(LCDIF2_BASE_PTR)
29439 #define LCDIF2_CSC_COEFF4                        LCDIF_CSC_COEFF4_REG(LCDIF2_BASE_PTR)
29440 #define LCDIF2_CSC_OFFSET                        LCDIF_CSC_OFFSET_REG(LCDIF2_BASE_PTR)
29441 #define LCDIF2_CSC_LIMIT                         LCDIF_CSC_LIMIT_REG(LCDIF2_BASE_PTR)
29442 #define LCDIF2_DATA                              LCDIF_DATA_REG(LCDIF2_BASE_PTR)
29443 #define LCDIF2_BM_ERROR_STAT                     LCDIF_BM_ERROR_STAT_REG(LCDIF2_BASE_PTR)
29444 #define LCDIF2_CRC_STAT                          LCDIF_CRC_STAT_REG(LCDIF2_BASE_PTR)
29445 #define LCDIF2_STAT                              LCDIF_STAT_REG(LCDIF2_BASE_PTR)
29446 #define LCDIF2_VERSION                           LCDIF_VERSION_REG(LCDIF2_BASE_PTR)
29447 #define LCDIF2_DEBUG0                            LCDIF_DEBUG0_REG(LCDIF2_BASE_PTR)
29448 #define LCDIF2_DEBUG1                            LCDIF_DEBUG1_REG(LCDIF2_BASE_PTR)
29449 #define LCDIF2_DEBUG2                            LCDIF_DEBUG2_REG(LCDIF2_BASE_PTR)
29450 #define LCDIF2_THRES                             LCDIF_THRES_REG(LCDIF2_BASE_PTR)
29451 #define LCDIF2_AS_CTRL                           LCDIF_AS_CTRL_REG(LCDIF2_BASE_PTR)
29452 #define LCDIF2_AS_BUF                            LCDIF_AS_BUF_REG(LCDIF2_BASE_PTR)
29453 #define LCDIF2_AS_NEXT_BUF                       LCDIF_AS_NEXT_BUF_REG(LCDIF2_BASE_PTR)
29454 #define LCDIF2_AS_CLRKEYLOW                      LCDIF_AS_CLRKEYLOW_REG(LCDIF2_BASE_PTR)
29455 #define LCDIF2_AS_CLRKEYHIGH                     LCDIF_AS_CLRKEYHIGH_REG(LCDIF2_BASE_PTR)
29456 #define LCDIF2_SYNC_DELAY                        LCDIF_SYNC_DELAY_REG(LCDIF2_BASE_PTR)
29457 #define LCDIF2_DEBUG3                            LCDIF_DEBUG3_REG(LCDIF2_BASE_PTR)
29458 #define LCDIF2_DEBUG4                            LCDIF_DEBUG4_REG(LCDIF2_BASE_PTR)
29459 #define LCDIF2_DEBUG5                            LCDIF_DEBUG5_REG(LCDIF2_BASE_PTR)
29460 /*!
29461  * @}
29462  */ /* end of group LCDIF_Register_Accessor_Macros */
29463 
29464 
29465 /*!
29466  * @}
29467  */ /* end of group LCDIF_Peripheral */
29468 
29469 /* ----------------------------------------------------------------------------
29470    -- LMEM Peripheral Access Layer
29471    ---------------------------------------------------------------------------- */
29472 
29473 /*!
29474  * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
29475  * @{
29476  */
29477 
29478 /** LMEM - Register Layout Typedef */
29479 typedef struct {
29480   __IO  uint32_t PCCCR;                                  /**< Cache control register, offset: 0x0 */
29481   __IO  uint32_t PCCLCR;                                 /**< Cache line control register, offset: 0x4 */
29482   __IO  uint32_t PCCSAR;                                 /**< Cache search address register, offset: 0x8 */
29483   __IO  uint32_t PCCCVR;                                 /**< Cache read/write value register, offset: 0xC */
29484   uint8_t RESERVED_0[2032];
29485   __IO  uint32_t PSCCR;                                  /**< Cache control register, offset: 0x800 */
29486   __IO  uint32_t PSCLCR;                                 /**< Cache line control register, offset: 0x804 */
29487   __IO  uint32_t PSCSAR;                                 /**< Cache search address register, offset: 0x808 */
29488   __IO  uint32_t PSCCVR;                                 /**< Cache read/write value register, offset: 0x80C */
29489 } LMEM_Type, *LMEM_MemMapPtr;
29490 /* ----------------------------------------------------------------------------
29491    -- LMEM - Register accessor macros
29492    ---------------------------------------------------------------------------- */
29493 
29494 /*!
29495  * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros
29496  * @{
29497  */
29498 
29499 
29500 /* LMEM - Register accessors */
29501 #define LMEM_PCCCR_REG(base)                     ((base)->PCCCR)
29502 #define LMEM_PCCLCR_REG(base)                    ((base)->PCCLCR)
29503 #define LMEM_PCCSAR_REG(base)                    ((base)->PCCSAR)
29504 #define LMEM_PCCCVR_REG(base)                    ((base)->PCCCVR)
29505 #define LMEM_PSCCR_REG(base)                     ((base)->PSCCR)
29506 #define LMEM_PSCLCR_REG(base)                    ((base)->PSCLCR)
29507 #define LMEM_PSCSAR_REG(base)                    ((base)->PSCSAR)
29508 #define LMEM_PSCCVR_REG(base)                    ((base)->PSCCVR)
29509 
29510 /*!
29511  * @}
29512  */ /* end of group LMEM_Register_Accessor_Macros */
29513 /* ----------------------------------------------------------------------------
29514    -- LMEM Register Masks
29515    ---------------------------------------------------------------------------- */
29516 
29517 /*!
29518  * @addtogroup LMEM_Register_Masks LMEM Register Masks
29519  * @{
29520  */
29521 
29522 /* PCCCR Bit Fields */
29523 #define LMEM_PCCCR_ENCACHE_MASK                  0x1u
29524 #define LMEM_PCCCR_ENCACHE_SHIFT                 0
29525 #define LMEM_PCCCR_ENWRBUF_MASK                  0x2u
29526 #define LMEM_PCCCR_ENWRBUF_SHIFT                 1
29527 #define LMEM_PCCCR_PCCR2_MASK                    0x4u
29528 #define LMEM_PCCCR_PCCR2_SHIFT                   2
29529 #define LMEM_PCCCR_PCCR3_MASK                    0x8u
29530 #define LMEM_PCCCR_PCCR3_SHIFT                   3
29531 #define LMEM_PCCCR_INVW0_MASK                    0x1000000u
29532 #define LMEM_PCCCR_INVW0_SHIFT                   24
29533 #define LMEM_PCCCR_PUSHW0_MASK                   0x2000000u
29534 #define LMEM_PCCCR_PUSHW0_SHIFT                  25
29535 #define LMEM_PCCCR_INVW1_MASK                    0x4000000u
29536 #define LMEM_PCCCR_INVW1_SHIFT                   26
29537 #define LMEM_PCCCR_PUSHW1_MASK                   0x8000000u
29538 #define LMEM_PCCCR_PUSHW1_SHIFT                  27
29539 #define LMEM_PCCCR_GO_MASK                       0x80000000u
29540 #define LMEM_PCCCR_GO_SHIFT                      31
29541 /* PCCLCR Bit Fields */
29542 #define LMEM_PCCLCR_LGO_MASK                     0x1u
29543 #define LMEM_PCCLCR_LGO_SHIFT                    0
29544 #define LMEM_PCCLCR_CACHEADDR_MASK               0x1FFCu
29545 #define LMEM_PCCLCR_CACHEADDR_SHIFT              2
29546 #define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
29547 #define LMEM_PCCLCR_WSEL_MASK                    0x4000u
29548 #define LMEM_PCCLCR_WSEL_SHIFT                   14
29549 #define LMEM_PCCLCR_TDSEL_MASK                   0x10000u
29550 #define LMEM_PCCLCR_TDSEL_SHIFT                  16
29551 #define LMEM_PCCLCR_LCIVB_MASK                   0x100000u
29552 #define LMEM_PCCLCR_LCIVB_SHIFT                  20
29553 #define LMEM_PCCLCR_LCIMB_MASK                   0x200000u
29554 #define LMEM_PCCLCR_LCIMB_SHIFT                  21
29555 #define LMEM_PCCLCR_LCWAY_MASK                   0x400000u
29556 #define LMEM_PCCLCR_LCWAY_SHIFT                  22
29557 #define LMEM_PCCLCR_LCMD_MASK                    0x3000000u
29558 #define LMEM_PCCLCR_LCMD_SHIFT                   24
29559 #define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
29560 #define LMEM_PCCLCR_LADSEL_MASK                  0x4000000u
29561 #define LMEM_PCCLCR_LADSEL_SHIFT                 26
29562 #define LMEM_PCCLCR_LACC_MASK                    0x8000000u
29563 #define LMEM_PCCLCR_LACC_SHIFT                   27
29564 /* PCCSAR Bit Fields */
29565 #define LMEM_PCCSAR_LGO_MASK                     0x1u
29566 #define LMEM_PCCSAR_LGO_SHIFT                    0
29567 #define LMEM_PCCSAR_PHYADDR_MASK                 0xFFFFFFFCu
29568 #define LMEM_PCCSAR_PHYADDR_SHIFT                2
29569 #define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
29570 /* PCCCVR Bit Fields */
29571 #define LMEM_PCCCVR_DATA_MASK                    0xFFFFFFFFu
29572 #define LMEM_PCCCVR_DATA_SHIFT                   0
29573 #define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
29574 /* PSCCR Bit Fields */
29575 #define LMEM_PSCCR_ENCACHE_MASK                  0x1u
29576 #define LMEM_PSCCR_ENCACHE_SHIFT                 0
29577 #define LMEM_PSCCR_ENWRBUF_MASK                  0x2u
29578 #define LMEM_PSCCR_ENWRBUF_SHIFT                 1
29579 #define LMEM_PSCCR_INVW0_MASK                    0x1000000u
29580 #define LMEM_PSCCR_INVW0_SHIFT                   24
29581 #define LMEM_PSCCR_PUSHW0_MASK                   0x2000000u
29582 #define LMEM_PSCCR_PUSHW0_SHIFT                  25
29583 #define LMEM_PSCCR_INVW1_MASK                    0x4000000u
29584 #define LMEM_PSCCR_INVW1_SHIFT                   26
29585 #define LMEM_PSCCR_PUSHW1_MASK                   0x8000000u
29586 #define LMEM_PSCCR_PUSHW1_SHIFT                  27
29587 #define LMEM_PSCCR_GO_MASK                       0x80000000u
29588 #define LMEM_PSCCR_GO_SHIFT                      31
29589 /* PSCLCR Bit Fields */
29590 #define LMEM_PSCLCR_LGO_MASK                     0x1u
29591 #define LMEM_PSCLCR_LGO_SHIFT                    0
29592 #define LMEM_PSCLCR_CACHEADDR_MASK               0x1FFCu
29593 #define LMEM_PSCLCR_CACHEADDR_SHIFT              2
29594 #define LMEM_PSCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_CACHEADDR_SHIFT))&LMEM_PSCLCR_CACHEADDR_MASK)
29595 #define LMEM_PSCLCR_WSEL_MASK                    0x4000u
29596 #define LMEM_PSCLCR_WSEL_SHIFT                   14
29597 #define LMEM_PSCLCR_TDSEL_MASK                   0x10000u
29598 #define LMEM_PSCLCR_TDSEL_SHIFT                  16
29599 #define LMEM_PSCLCR_LCIVB_MASK                   0x100000u
29600 #define LMEM_PSCLCR_LCIVB_SHIFT                  20
29601 #define LMEM_PSCLCR_LCIMB_MASK                   0x200000u
29602 #define LMEM_PSCLCR_LCIMB_SHIFT                  21
29603 #define LMEM_PSCLCR_LCWAY_MASK                   0x400000u
29604 #define LMEM_PSCLCR_LCWAY_SHIFT                  22
29605 #define LMEM_PSCLCR_LCMD_MASK                    0x3000000u
29606 #define LMEM_PSCLCR_LCMD_SHIFT                   24
29607 #define LMEM_PSCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_LCMD_SHIFT))&LMEM_PSCLCR_LCMD_MASK)
29608 #define LMEM_PSCLCR_LADSEL_MASK                  0x4000000u
29609 #define LMEM_PSCLCR_LADSEL_SHIFT                 26
29610 #define LMEM_PSCLCR_LACC_MASK                    0x8000000u
29611 #define LMEM_PSCLCR_LACC_SHIFT                   27
29612 /* PSCSAR Bit Fields */
29613 #define LMEM_PSCSAR_LGO_MASK                     0x1u
29614 #define LMEM_PSCSAR_LGO_SHIFT                    0
29615 #define LMEM_PSCSAR_PHYADDR_MASK                 0xFFFFFFFCu
29616 #define LMEM_PSCSAR_PHYADDR_SHIFT                2
29617 #define LMEM_PSCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LMEM_PSCSAR_PHYADDR_SHIFT))&LMEM_PSCSAR_PHYADDR_MASK)
29618 /* PSCCVR Bit Fields */
29619 #define LMEM_PSCCVR_DATA_MASK                    0xFFFFFFFFu
29620 #define LMEM_PSCCVR_DATA_SHIFT                   0
29621 #define LMEM_PSCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PSCCVR_DATA_SHIFT))&LMEM_PSCCVR_DATA_MASK)
29622 
29623 /*!
29624  * @}
29625  */ /* end of group LMEM_Register_Masks */
29626 
29627 /* LMEM - Peripheral instance base addresses */
29628 /** Peripheral LMEM base address */
29629 #define LMEM_BASE                                (0xE0082000u)
29630 /** Peripheral LMEM base pointer */
29631 #define LMEM                                     ((LMEM_Type *)LMEM_BASE)
29632 #define LMEM_BASE_PTR                            (LMEM)
29633 /** Array initializer of LMEM peripheral base addresses */
29634 #define LMEM_BASE_ADDRS                          { LMEM_BASE }
29635 /** Array initializer of LMEM peripheral base pointers */
29636 #define LMEM_BASE_PTRS                           { LMEM }
29637 /* ----------------------------------------------------------------------------
29638    -- LMEM - Register accessor macros
29639    ---------------------------------------------------------------------------- */
29640 
29641 /*!
29642  * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros
29643  * @{
29644  */
29645 
29646 
29647 /* LMEM - Register instance definitions */
29648 /* LMEM */
29649 #define LMEM_PCCCR                               LMEM_PCCCR_REG(LMEM_BASE_PTR)
29650 #define LMEM_PCCLCR                              LMEM_PCCLCR_REG(LMEM_BASE_PTR)
29651 #define LMEM_PCCSAR                              LMEM_PCCSAR_REG(LMEM_BASE_PTR)
29652 #define LMEM_PCCCVR                              LMEM_PCCCVR_REG(LMEM_BASE_PTR)
29653 #define LMEM_PSCCR                               LMEM_PSCCR_REG(LMEM_BASE_PTR)
29654 #define LMEM_PSCLCR                              LMEM_PSCLCR_REG(LMEM_BASE_PTR)
29655 #define LMEM_PSCSAR                              LMEM_PSCSAR_REG(LMEM_BASE_PTR)
29656 #define LMEM_PSCCVR                              LMEM_PSCCVR_REG(LMEM_BASE_PTR)
29657 /*!
29658  * @}
29659  */ /* end of group LMEM_Register_Accessor_Macros */
29660 
29661 
29662 /*!
29663  * @}
29664  */ /* end of group LMEM_Peripheral */
29665 
29666 /* ----------------------------------------------------------------------------
29667    -- MCM Peripheral Access Layer
29668    ---------------------------------------------------------------------------- */
29669 
29670 /*!
29671  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
29672  * @{
29673  */
29674 
29675 /** MCM - Register Layout Typedef */
29676 typedef struct {
29677   uint8_t RESERVED_0[8];
29678   __I   uint16_t PLASC;                                  /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
29679   __I   uint16_t PLAMC;                                  /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
29680   uint8_t RESERVED_1[20];
29681   __I   uint32_t FADR;                                   /**< Fault address register, offset: 0x20 */
29682   __I   uint32_t FATR;                                   /**< Fault attributes register, offset: 0x24 */
29683   __I   uint32_t FDR;                                    /**< Fault data register, offset: 0x28 */
29684 } MCM_Type, *MCM_MemMapPtr;
29685 /* ----------------------------------------------------------------------------
29686    -- MCM - Register accessor macros
29687    ---------------------------------------------------------------------------- */
29688 
29689 /*!
29690  * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
29691  * @{
29692  */
29693 
29694 
29695 /* MCM - Register accessors */
29696 #define MCM_PLASC_REG(base)                      ((base)->PLASC)
29697 #define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
29698 #define MCM_FADR_REG(base)                       ((base)->FADR)
29699 #define MCM_FATR_REG(base)                       ((base)->FATR)
29700 #define MCM_FDR_REG(base)                        ((base)->FDR)
29701 
29702 /*!
29703  * @}
29704  */ /* end of group MCM_Register_Accessor_Macros */
29705 /* ----------------------------------------------------------------------------
29706    -- MCM Register Masks
29707    ---------------------------------------------------------------------------- */
29708 
29709 /*!
29710  * @addtogroup MCM_Register_Masks MCM Register Masks
29711  * @{
29712  */
29713 
29714 /* PLASC Bit Fields */
29715 #define MCM_PLASC_ASC_MASK                       0xFFu
29716 #define MCM_PLASC_ASC_SHIFT                      0
29717 #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
29718 /* PLAMC Bit Fields */
29719 #define MCM_PLAMC_AMC_MASK                       0xFFu
29720 #define MCM_PLAMC_AMC_SHIFT                      0
29721 #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
29722 /* FADR Bit Fields */
29723 #define MCM_FADR_ADDRESS_MASK                    0xFFFFFFFFu
29724 #define MCM_FADR_ADDRESS_SHIFT                   0
29725 #define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_FADR_ADDRESS_SHIFT))&MCM_FADR_ADDRESS_MASK)
29726 /* FATR Bit Fields */
29727 #define MCM_FATR_BEDA_MASK                       0x1u
29728 #define MCM_FATR_BEDA_SHIFT                      0
29729 #define MCM_FATR_BEMD_MASK                       0x2u
29730 #define MCM_FATR_BEMD_SHIFT                      1
29731 #define MCM_FATR_BESZ_MASK                       0x30u
29732 #define MCM_FATR_BESZ_SHIFT                      4
29733 #define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BESZ_SHIFT))&MCM_FATR_BESZ_MASK)
29734 #define MCM_FATR_BEWT_MASK                       0x80u
29735 #define MCM_FATR_BEWT_SHIFT                      7
29736 #define MCM_FATR_BEMN_MASK                       0xF00u
29737 #define MCM_FATR_BEMN_SHIFT                      8
29738 #define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BEMN_SHIFT))&MCM_FATR_BEMN_MASK)
29739 #define MCM_FATR_BEOVR_MASK                      0x80000000u
29740 #define MCM_FATR_BEOVR_SHIFT                     31
29741 /* FDR Bit Fields */
29742 #define MCM_FDR_DATA_MASK                        0xFFFFFFFFu
29743 #define MCM_FDR_DATA_SHIFT                       0
29744 #define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_FDR_DATA_SHIFT))&MCM_FDR_DATA_MASK)
29745 
29746 /*!
29747  * @}
29748  */ /* end of group MCM_Register_Masks */
29749 
29750 /* MCM - Peripheral instance base addresses */
29751 /** Peripheral MCM base address */
29752 #define MCM_BASE                                 (0xE0000000u)
29753 /** Peripheral MCM base pointer */
29754 #define MCM                                      ((MCM_Type *)MCM_BASE)
29755 #define MCM_BASE_PTR                             (MCM)
29756 /** Array initializer of MCM peripheral base addresses */
29757 #define MCM_BASE_ADDRS                           { MCM_BASE }
29758 /** Array initializer of MCM peripheral base pointers */
29759 #define MCM_BASE_PTRS                            { MCM }
29760 /* ----------------------------------------------------------------------------
29761    -- MCM - Register accessor macros
29762    ---------------------------------------------------------------------------- */
29763 
29764 /*!
29765  * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
29766  * @{
29767  */
29768 
29769 
29770 /* MCM - Register instance definitions */
29771 /* MCM */
29772 #define MCM_PLASC                                MCM_PLASC_REG(MCM_BASE_PTR)
29773 #define MCM_PLAMC                                MCM_PLAMC_REG(MCM_BASE_PTR)
29774 #define MCM_FADR                                 MCM_FADR_REG(MCM_BASE_PTR)
29775 #define MCM_FATR                                 MCM_FATR_REG(MCM_BASE_PTR)
29776 #define MCM_FDR                                  MCM_FDR_REG(MCM_BASE_PTR)
29777 /*!
29778  * @}
29779  */ /* end of group MCM_Register_Accessor_Macros */
29780 
29781 
29782 /*!
29783  * @}
29784  */ /* end of group MCM_Peripheral */
29785 
29786 /* ----------------------------------------------------------------------------
29787    -- MIPI_CSI2 Peripheral Access Layer
29788    ---------------------------------------------------------------------------- */
29789 
29790 /*!
29791  * @addtogroup MIPI_CSI2_Peripheral_Access_Layer MIPI_CSI2 Peripheral Access Layer
29792  * @{
29793  */
29794 
29795 /** MIPI_CSI2 - Register Layout Typedef */
29796 typedef struct {
29797   uint8_t RESERVED_0[4];
29798   __IO  uint32_t CSIS_CMN_CTRL;                          /**< CSIS Common Control, offset: 0x4 */
29799   __IO  uint32_t CSIS_CLK_CTRL;                          /**< CSIS Clock gate Control, offset: 0x8 */
29800   uint8_t RESERVED_1[4];
29801   __IO  uint32_t CSIS_INT_MSK;                           /**< CSIS Interrupt Mask, offset: 0x10 */
29802   __IO  uint32_t CSIS_INT_SRC;                           /**< CSIS Interrupt Source, offset: 0x14 */
29803   uint8_t RESERVED_2[8];
29804   __IO  uint32_t DPHY_STATUS;                            /**< D-PHY Status, offset: 0x20 */
29805   __IO  uint32_t DPHY_CMN_CTRL;                          /**< D-PHY Common Control, offset: 0x24 */
29806   uint8_t RESERVED_3[8];
29807   __IO  uint32_t DPHY_BCTRL_L;                           /**< D-PHY Master and Slave Control register low, offset: 0x30 */
29808   __IO  uint32_t DPHY_BCTRL_H;                           /**< D-PHY Master and Slave Control register high, offset: 0x34 */
29809   __IO  uint32_t DPHY_SCTRL_L;                           /**< D-PHY Slave Control register low, offset: 0x38 */
29810   __IO  uint32_t DPHY_SCTRL_H;                           /**< D-PHY Slave Control register high, offset: 0x3C */
29811   __IO  uint32_t ISP_CONFIG_CH0;                         /**< ISP Configuration register of CH0, offset: 0x40 */
29812   __IO  uint32_t ISP_RESOL_CH0;                          /**< ISP Image Resolution register of CH0, offset: 0x44 */
29813   __IO  uint32_t ISP_SYNC_CH0;                           /**< ISP SYNC register of CH0, offset: 0x48 */
29814   uint8_t RESERVED_4[52];
29815   __I   uint32_t SDW_CONFIG_CH0;                         /**< Shadow Configuration register of CH0, offset: 0x80 */
29816   __I   uint32_t SDW_RESOL_CH0;                          /**< Shadow Resolution register of CH0, offset: 0x84 */
29817   __IO  uint32_t SDW_SYNC_CH0;                           /**< Shadow SYNC register of CH0, offset: 0x88 */
29818   uint8_t RESERVED_5[52];
29819   __IO  uint32_t DBG_CTRL;                               /**< Debug Control register, offset: 0xC0 */
29820   __IO  uint32_t DBG_INTR_MSK;                           /**< Debug Interrupt Mask, offset: 0xC4 */
29821   __IO  uint32_t DBG_INTR_SRC;                           /**< Debug Interrupt Mask, offset: 0xC8 */
29822   uint8_t RESERVED_6[7988];
29823   __IO  uint32_t NON_IMG_DATA;                           /**< Non Image Data, offset: 0x2000 */
29824 } MIPI_CSI2_Type, *MIPI_CSI2_MemMapPtr;
29825 /* ----------------------------------------------------------------------------
29826    -- MIPI_CSI2 - Register accessor macros
29827    ---------------------------------------------------------------------------- */
29828 
29829 /*!
29830  * @addtogroup MIPI_CSI2_Register_Accessor_Macros MIPI_CSI2 - Register accessor macros
29831  * @{
29832  */
29833 
29834 
29835 /* MIPI_CSI2 - Register accessors */
29836 #define MIPI_CSI2_CSIS_CMN_CTRL_REG(base)        ((base)->CSIS_CMN_CTRL)
29837 #define MIPI_CSI2_CSIS_CLK_CTRL_REG(base)        ((base)->CSIS_CLK_CTRL)
29838 #define MIPI_CSI2_CSIS_INT_MSK_REG(base)         ((base)->CSIS_INT_MSK)
29839 #define MIPI_CSI2_CSIS_INT_SRC_REG(base)         ((base)->CSIS_INT_SRC)
29840 #define MIPI_CSI2_DPHY_STATUS_REG(base)          ((base)->DPHY_STATUS)
29841 #define MIPI_CSI2_DPHY_CMN_CTRL_REG(base)        ((base)->DPHY_CMN_CTRL)
29842 #define MIPI_CSI2_DPHY_BCTRL_L_REG(base)         ((base)->DPHY_BCTRL_L)
29843 #define MIPI_CSI2_DPHY_BCTRL_H_REG(base)         ((base)->DPHY_BCTRL_H)
29844 #define MIPI_CSI2_DPHY_SCTRL_L_REG(base)         ((base)->DPHY_SCTRL_L)
29845 #define MIPI_CSI2_DPHY_SCTRL_H_REG(base)         ((base)->DPHY_SCTRL_H)
29846 #define MIPI_CSI2_ISP_CONFIG_CH0_REG(base)       ((base)->ISP_CONFIG_CH0)
29847 #define MIPI_CSI2_ISP_RESOL_CH0_REG(base)        ((base)->ISP_RESOL_CH0)
29848 #define MIPI_CSI2_ISP_SYNC_CH0_REG(base)         ((base)->ISP_SYNC_CH0)
29849 #define MIPI_CSI2_SDW_CONFIG_CH0_REG(base)       ((base)->SDW_CONFIG_CH0)
29850 #define MIPI_CSI2_SDW_RESOL_CH0_REG(base)        ((base)->SDW_RESOL_CH0)
29851 #define MIPI_CSI2_SDW_SYNC_CH0_REG(base)         ((base)->SDW_SYNC_CH0)
29852 #define MIPI_CSI2_DBG_CTRL_REG(base)             ((base)->DBG_CTRL)
29853 #define MIPI_CSI2_DBG_INTR_MSK_REG(base)         ((base)->DBG_INTR_MSK)
29854 #define MIPI_CSI2_DBG_INTR_SRC_REG(base)         ((base)->DBG_INTR_SRC)
29855 #define MIPI_CSI2_NON_IMG_DATA_REG(base)         ((base)->NON_IMG_DATA)
29856 
29857 /*!
29858  * @}
29859  */ /* end of group MIPI_CSI2_Register_Accessor_Macros */
29860 /* ----------------------------------------------------------------------------
29861    -- MIPI_CSI2 Register Masks
29862    ---------------------------------------------------------------------------- */
29863 
29864 /*!
29865  * @addtogroup MIPI_CSI2_Register_Masks MIPI_CSI2 Register Masks
29866  * @{
29867  */
29868 
29869 /* CSIS_CMN_CTRL Bit Fields */
29870 #define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_MASK      0x1u
29871 #define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_SHIFT     0
29872 #define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_MASK     0x2u
29873 #define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_SHIFT    1
29874 #define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u
29875 #define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2
29876 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_MASK       0xF8u
29877 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_SHIFT      3
29878 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_MASK)
29879 #define MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_MASK 0x300u
29880 #define MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT 8
29881 #define MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_MASK)
29882 #define MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK 0xC00u
29883 #define MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT 10
29884 #define MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK)
29885 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_MASK       0xF000u
29886 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_SHIFT      12
29887 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD2(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_MASK)
29888 #define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK 0xF0000u
29889 #define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT 16
29890 #define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK)
29891 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_MASK       0xFFF00000u
29892 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_SHIFT      20
29893 #define MIPI_CSI2_CSIS_CMN_CTRL_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_MASK)
29894 /* CSIS_CLK_CTRL Bit Fields */
29895 #define MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_MASK    0xFu
29896 #define MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_SHIFT   0
29897 #define MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC(x)      (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_MASK)
29898 #define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_MASK  0xF0u
29899 #define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT 4
29900 #define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_MASK)
29901 #define MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_MASK       0xFF00u
29902 #define MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_SHIFT      8
29903 #define MIPI_CSI2_CSIS_CLK_CTRL_RSVD4(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_MASK)
29904 #define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK 0xFFFF0000u
29905 #define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT 16
29906 #define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK)
29907 /* CSIS_INT_MSK Bit Fields */
29908 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_id_MASK   0x1u
29909 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_id_SHIFT  0
29910 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_CRC_MASK  0x2u
29911 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_CRC_SHIFT 1
29912 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_ECC_MASK  0x4u
29913 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_ECC_SHIFT 2
29914 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_MASK 0x8u
29915 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_SHIFT 3
29916 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_MASK 0xF0u
29917 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT 4
29918 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_MASK)
29919 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK 0xF00u
29920 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT 8
29921 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK)
29922 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK 0xF000u
29923 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT 12
29924 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK)
29925 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK 0xF0000u
29926 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT 16
29927 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK)
29928 #define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_MASK 0xF00000u
29929 #define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT 20
29930 #define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_MASK)
29931 #define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_MASK 0xF000000u
29932 #define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT 24
29933 #define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_MASK)
29934 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDAFTER_MASK 0x10000000u
29935 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDAFTER_SHIFT 28
29936 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDBEFORE_MASK 0x20000000u
29937 #define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDBEFORE_SHIFT 29
29938 #define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENAFTER_MASK 0x40000000u
29939 #define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENAFTER_SHIFT 30
29940 #define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENBEFORE_MASK 0x80000000u
29941 #define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENBEFORE_SHIFT 31
29942 /* CSIS_INT_SRC Bit Fields */
29943 #define MIPI_CSI2_CSIS_INT_SRC_ERR_ID_MASK       0x1u
29944 #define MIPI_CSI2_CSIS_INT_SRC_ERR_ID_SHIFT      0
29945 #define MIPI_CSI2_CSIS_INT_SRC_ERR_CRC_MASK      0x2u
29946 #define MIPI_CSI2_CSIS_INT_SRC_ERR_CRC_SHIFT     1
29947 #define MIPI_CSI2_CSIS_INT_SRC_ERR_ECC_MASK      0x4u
29948 #define MIPI_CSI2_CSIS_INT_SRC_ERR_ECC_SHIFT     2
29949 #define MIPI_CSI2_CSIS_INT_SRC_ERR_WRONG_CFG_MASK 0x8u
29950 #define MIPI_CSI2_CSIS_INT_SRC_ERR_WRONG_CFG_SHIFT 3
29951 #define MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_MASK     0xF0u
29952 #define MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_SHIFT    4
29953 #define MIPI_CSI2_CSIS_INT_SRC_ERR_OVER(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_MASK)
29954 #define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_MASK  0xF00u
29955 #define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_SHIFT 8
29956 #define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_MASK)
29957 #define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_MASK  0xF000u
29958 #define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_SHIFT 12
29959 #define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_MASK)
29960 #define MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_MASK   0xF0000u
29961 #define MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_SHIFT  16
29962 #define MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_MASK)
29963 #define MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_MASK     0xF00000u
29964 #define MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_SHIFT    20
29965 #define MIPI_CSI2_CSIS_INT_SRC_FRAMEEND(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_MASK)
29966 #define MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_MASK   0xF000000u
29967 #define MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_SHIFT  24
29968 #define MIPI_CSI2_CSIS_INT_SRC_FRAMESTART(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_MASK)
29969 #define MIPI_CSI2_CSIS_INT_SRC_ODDAFTER_MASK     0x10000000u
29970 #define MIPI_CSI2_CSIS_INT_SRC_ODDAFTER_SHIFT    28
29971 #define MIPI_CSI2_CSIS_INT_SRC_ODDBEFORE_MASK    0x20000000u
29972 #define MIPI_CSI2_CSIS_INT_SRC_ODDBEFORE_SHIFT   29
29973 #define MIPI_CSI2_CSIS_INT_SRC_EVENAFTER_MASK    0x40000000u
29974 #define MIPI_CSI2_CSIS_INT_SRC_EVENAFTER_SHIFT   30
29975 #define MIPI_CSI2_CSIS_INT_SRC_EVENBEFORE_MASK   0x80000000u
29976 #define MIPI_CSI2_CSIS_INT_SRC_EVENBEFORE_SHIFT  31
29977 /* DPHY_STATUS Bit Fields */
29978 #define MIPI_CSI2_DPHY_STATUS_STOPSTATECLK_MASK  0x1u
29979 #define MIPI_CSI2_DPHY_STATUS_STOPSTATECLK_SHIFT 0
29980 #define MIPI_CSI2_DPHY_STATUS_ULPSCLK_MASK       0x2u
29981 #define MIPI_CSI2_DPHY_STATUS_ULPSCLK_SHIFT      1
29982 #define MIPI_CSI2_DPHY_STATUS_RSVD6_MASK         0xCu
29983 #define MIPI_CSI2_DPHY_STATUS_RSVD6_SHIFT        2
29984 #define MIPI_CSI2_DPHY_STATUS_RSVD6(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_RSVD6_SHIFT))&MIPI_CSI2_DPHY_STATUS_RSVD6_MASK)
29985 #define MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_MASK  0xF0u
29986 #define MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_SHIFT 4
29987 #define MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_SHIFT))&MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_MASK)
29988 #define MIPI_CSI2_DPHY_STATUS_ULPSDAT_MASK       0xF00u
29989 #define MIPI_CSI2_DPHY_STATUS_ULPSDAT_SHIFT      8
29990 #define MIPI_CSI2_DPHY_STATUS_ULPSDAT(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_ULPSDAT_SHIFT))&MIPI_CSI2_DPHY_STATUS_ULPSDAT_MASK)
29991 #define MIPI_CSI2_DPHY_STATUS_RSVD5_MASK         0xFFFFF000u
29992 #define MIPI_CSI2_DPHY_STATUS_RSVD5_SHIFT        12
29993 #define MIPI_CSI2_DPHY_STATUS_RSVD5(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_RSVD5_SHIFT))&MIPI_CSI2_DPHY_STATUS_RSVD5_MASK)
29994 /* DPHY_CMN_CTRL Bit Fields */
29995 #define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_CLK_MASK  0x1u
29996 #define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_CLK_SHIFT 0
29997 #define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_MASK  0x1Eu
29998 #define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT 1
29999 #define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_MASK)
30000 #define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_MASK 0x20u
30001 #define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_SHIFT 5
30002 #define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_MASK 0x40u
30003 #define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_SHIFT 6
30004 #define MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_MASK       0x3FFF80u
30005 #define MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_SHIFT      7
30006 #define MIPI_CSI2_DPHY_CMN_CTRL_RSVD7(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_MASK)
30007 #define MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK 0xC00000u
30008 #define MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT 22
30009 #define MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK)
30010 #define MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_MASK    0xFF000000u
30011 #define MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_SHIFT   24
30012 #define MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE(x)      (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_MASK)
30013 /* DPHY_BCTRL_L Bit Fields */
30014 #define MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_MASK   0xFFFFFFFFu
30015 #define MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT  0
30016 #define MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_MASK)
30017 /* DPHY_BCTRL_H Bit Fields */
30018 #define MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_MASK   0xFFFFFFFFu
30019 #define MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT  0
30020 #define MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_MASK)
30021 /* DPHY_SCTRL_L Bit Fields */
30022 #define MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_MASK   0xFFFFFFFFu
30023 #define MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT  0
30024 #define MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_MASK)
30025 /* DPHY_SCTRL_H Bit Fields */
30026 #define MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_MASK   0xFFFFFFFFu
30027 #define MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT  0
30028 #define MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_MASK)
30029 /* ISP_CONFIG_CH0 Bit Fields */
30030 #define MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u
30031 #define MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0
30032 #define MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK)
30033 #define MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_MASK 0xFCu
30034 #define MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_SHIFT 2
30035 #define MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_MASK)
30036 #define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_EN_MASK  0x100u
30037 #define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_EN_SHIFT 8
30038 #define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_PREDICT_MASK 0x200u
30039 #define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_PREDICT_SHIFT 9
30040 #define MIPI_CSI2_ISP_CONFIG_CH0_RGB_SWAP_MASK   0x400u
30041 #define MIPI_CSI2_ISP_CONFIG_CH0_RGB_SWAP_SHIFT  10
30042 #define MIPI_CSI2_ISP_CONFIG_CH0_PARALLEL_MASK   0x800u
30043 #define MIPI_CSI2_ISP_CONFIG_CH0_PARALLEL_SHIFT  11
30044 #define MIPI_CSI2_ISP_CONFIG_CH0_DOUBLE_CMPNT_MASK 0x1000u
30045 #define MIPI_CSI2_ISP_CONFIG_CH0_DOUBLE_CMPNT_SHIFT 12
30046 #define MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_MASK      0xFFE000u
30047 #define MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_SHIFT     13
30048 #define MIPI_CSI2_ISP_CONFIG_CH0_RSVD8(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_MASK)
30049 #define MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK 0xFF000000u
30050 #define MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT 24
30051 #define MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK)
30052 /* ISP_RESOL_CH0 Bit Fields */
30053 #define MIPI_CSI2_ISP_RESOL_CH0_HRESOL_MASK      0xFFFFu
30054 #define MIPI_CSI2_ISP_RESOL_CH0_HRESOL_SHIFT     0
30055 #define MIPI_CSI2_ISP_RESOL_CH0_HRESOL(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_RESOL_CH0_HRESOL_SHIFT))&MIPI_CSI2_ISP_RESOL_CH0_HRESOL_MASK)
30056 #define MIPI_CSI2_ISP_RESOL_CH0_VRESOL_MASK      0xFFFF0000u
30057 #define MIPI_CSI2_ISP_RESOL_CH0_VRESOL_SHIFT     16
30058 #define MIPI_CSI2_ISP_RESOL_CH0_VRESOL(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_RESOL_CH0_VRESOL_SHIFT))&MIPI_CSI2_ISP_RESOL_CH0_VRESOL_MASK)
30059 /* ISP_SYNC_CH0 Bit Fields */
30060 #define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_MASK  0xFFFu
30061 #define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT 0
30062 #define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_MASK)
30063 #define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_MASK  0x3F000u
30064 #define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT 12
30065 #define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_MASK)
30066 #define MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_MASK  0xFC0000u
30067 #define MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT 18
30068 #define MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_MASK)
30069 #define MIPI_CSI2_ISP_SYNC_CH0_RSVD9_MASK        0xFF000000u
30070 #define MIPI_CSI2_ISP_SYNC_CH0_RSVD9_SHIFT       24
30071 #define MIPI_CSI2_ISP_SYNC_CH0_RSVD9(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_RSVD9_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_RSVD9_MASK)
30072 /* SDW_CONFIG_CH0 Bit Fields */
30073 #define MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u
30074 #define MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0
30075 #define MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK)
30076 #define MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_MASK 0xFCu
30077 #define MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_SHIFT 2
30078 #define MIPI_CSI2_SDW_CONFIG_CH0_DataFormat(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_MASK)
30079 #define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_EN_SDW_MASK 0x100u
30080 #define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_EN_SDW_SHIFT 8
30081 #define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_MASK 0x200u
30082 #define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_SHIFT 9
30083 #define MIPI_CSI2_SDW_CONFIG_CH0_RGB_SWAP_SDW_MASK 0x400u
30084 #define MIPI_CSI2_SDW_CONFIG_CH0_RGB_SWAP_SDW_SHIFT 10
30085 #define MIPI_CSI2_SDW_CONFIG_CH0_PARALLEL_SDW_MASK 0x800u
30086 #define MIPI_CSI2_SDW_CONFIG_CH0_PARALLEL_SDW_SHIFT 11
30087 #define MIPI_CSI2_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_MASK 0x1000u
30088 #define MIPI_CSI2_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_SHIFT 12
30089 #define MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_MASK     0xFFE000u
30090 #define MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_SHIFT    13
30091 #define MIPI_CSI2_SDW_CONFIG_CH0_RSVD10(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_MASK)
30092 #define MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK 0xFF000000u
30093 #define MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT 24
30094 #define MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK)
30095 /* SDW_RESOL_CH0 Bit Fields */
30096 #define MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_MASK  0xFFFFu
30097 #define MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_SHIFT 0
30098 #define MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_SHIFT))&MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_MASK)
30099 #define MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_MASK  0xFFFF0000u
30100 #define MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_SHIFT 16
30101 #define MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_SHIFT))&MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_MASK)
30102 /* SDW_SYNC_CH0 Bit Fields */
30103 #define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK 0xFFFu
30104 #define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT 0
30105 #define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK)
30106 #define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK 0x3F000u
30107 #define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT 12
30108 #define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK)
30109 #define MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK 0xFC0000u
30110 #define MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT 18
30111 #define MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK)
30112 #define MIPI_CSI2_SDW_SYNC_CH0_RSVD11_MASK       0xFF000000u
30113 #define MIPI_CSI2_SDW_SYNC_CH0_RSVD11_SHIFT      24
30114 #define MIPI_CSI2_SDW_SYNC_CH0_RSVD11(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_RSVD11_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_RSVD11_MASK)
30115 /* DBG_CTRL Bit Fields */
30116 #define MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_MASK    0xFu
30117 #define MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_SHIFT   0
30118 #define MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT(x)      (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_MASK)
30119 #define MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK 0xF0u
30120 #define MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT 4
30121 #define MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME(x)  (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK)
30122 #define MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK 0xF00u
30123 #define MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT 8
30124 #define MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK)
30125 #define MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_MASK 0xF000u
30126 #define MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT 12
30127 #define MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_MASK)
30128 #define MIPI_CSI2_DBG_CTRL_RSVD12_MASK           0xFFFF0000u
30129 #define MIPI_CSI2_DBG_CTRL_RSVD12_SHIFT          16
30130 #define MIPI_CSI2_DBG_CTRL_RSVD12(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_RSVD12_SHIFT))&MIPI_CSI2_DBG_CTRL_RSVD12_MASK)
30131 /* DBG_INTR_MSK Bit Fields */
30132 #define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK 0xFu
30133 #define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT 0
30134 #define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK)
30135 #define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK 0xF0u
30136 #define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT 4
30137 #define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK)
30138 #define MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_MASK     0xF00u
30139 #define MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_SHIFT    8
30140 #define MIPI_CSI2_DBG_INTR_MSK_EARLY_FS(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_MASK)
30141 #define MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_MASK     0xF000u
30142 #define MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_SHIFT    12
30143 #define MIPI_CSI2_DBG_INTR_MSK_EARLY_FE(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_MASK)
30144 #define MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_MASK 0xF0000u
30145 #define MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT 16
30146 #define MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_MASK)
30147 #define MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK 0xF00000u
30148 #define MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT 20
30149 #define MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK)
30150 #define MIPI_CSI2_DBG_INTR_MSK_DT_IGNORE_MASK    0x1000000u
30151 #define MIPI_CSI2_DBG_INTR_MSK_DT_IGNORE_SHIFT   24
30152 #define MIPI_CSI2_DBG_INTR_MSK_DT_NOT_SUPPORT_MASK 0x2000000u
30153 #define MIPI_CSI2_DBG_INTR_MSK_DT_NOT_SUPPORT_SHIFT 25
30154 #define MIPI_CSI2_DBG_INTR_MSK_RSVD13_MASK       0xFC000000u
30155 #define MIPI_CSI2_DBG_INTR_MSK_RSVD13_SHIFT      26
30156 #define MIPI_CSI2_DBG_INTR_MSK_RSVD13(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_RSVD13_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_RSVD13_MASK)
30157 /* DBG_INTR_SRC Bit Fields */
30158 #define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK 0xFu
30159 #define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT 0
30160 #define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK)
30161 #define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK 0xF0u
30162 #define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT 4
30163 #define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK)
30164 #define MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_MASK     0xF00u
30165 #define MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_SHIFT    8
30166 #define MIPI_CSI2_DBG_INTR_SRC_EARLY_FS(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_MASK)
30167 #define MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_MASK     0xF000u
30168 #define MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_SHIFT    12
30169 #define MIPI_CSI2_DBG_INTR_SRC_EARLY_FE(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_MASK)
30170 #define MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_MASK 0xF0000u
30171 #define MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT 16
30172 #define MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_MASK)
30173 #define MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK 0xF00000u
30174 #define MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT 20
30175 #define MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK)
30176 #define MIPI_CSI2_DBG_INTR_SRC_DT_IGNORE_MASK    0x1000000u
30177 #define MIPI_CSI2_DBG_INTR_SRC_DT_IGNORE_SHIFT   24
30178 #define MIPI_CSI2_DBG_INTR_SRC_DT_NOT_SUPPURT_MASK 0x2000000u
30179 #define MIPI_CSI2_DBG_INTR_SRC_DT_NOT_SUPPURT_SHIFT 25
30180 #define MIPI_CSI2_DBG_INTR_SRC_RSVD14_MASK       0xFC000000u
30181 #define MIPI_CSI2_DBG_INTR_SRC_RSVD14_SHIFT      26
30182 #define MIPI_CSI2_DBG_INTR_SRC_RSVD14(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_RSVD14_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_RSVD14_MASK)
30183 /* NON_IMG_DATA Bit Fields */
30184 #define MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_MASK   0xFFFFFFFFu
30185 #define MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_SHIFT  0
30186 #define MIPI_CSI2_NON_IMG_DATA_NONIMGDATA(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_SHIFT))&MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_MASK)
30187 
30188 /*!
30189  * @}
30190  */ /* end of group MIPI_CSI2_Register_Masks */
30191 
30192 /* MIPI_CSI2 - Peripheral instance base addresses */
30193 /** Peripheral MIPI_CSI2 base address */
30194 #define MIPI_CSI2_BASE                           (0x30750000u)
30195 /** Peripheral MIPI_CSI2 base pointer */
30196 #define MIPI_CSI2                                ((MIPI_CSI2_Type *)MIPI_CSI2_BASE)
30197 #define MIPI_CSI2_BASE_PTR                       (MIPI_CSI2)
30198 /** Array initializer of MIPI_CSI2 peripheral base addresses */
30199 #define MIPI_CSI2_BASE_ADDRS                     { MIPI_CSI2_BASE }
30200 /** Array initializer of MIPI_CSI2 peripheral base pointers */
30201 #define MIPI_CSI2_BASE_PTRS                      { MIPI_CSI2 }
30202 /* ----------------------------------------------------------------------------
30203    -- MIPI_CSI2 - Register accessor macros
30204    ---------------------------------------------------------------------------- */
30205 
30206 /*!
30207  * @addtogroup MIPI_CSI2_Register_Accessor_Macros MIPI_CSI2 - Register accessor macros
30208  * @{
30209  */
30210 
30211 
30212 /* MIPI_CSI2 - Register instance definitions */
30213 /* MIPI_CSI2 */
30214 #define MIPI_CSI2_CSIS_CMN_CTRL                  MIPI_CSI2_CSIS_CMN_CTRL_REG(MIPI_CSI2_BASE_PTR)
30215 #define MIPI_CSI2_CSIS_CLK_CTRL                  MIPI_CSI2_CSIS_CLK_CTRL_REG(MIPI_CSI2_BASE_PTR)
30216 #define MIPI_CSI2_CSIS_INT_MSK                   MIPI_CSI2_CSIS_INT_MSK_REG(MIPI_CSI2_BASE_PTR)
30217 #define MIPI_CSI2_CSIS_INT_SRC                   MIPI_CSI2_CSIS_INT_SRC_REG(MIPI_CSI2_BASE_PTR)
30218 #define MIPI_CSI2_DPHY_STATUS                    MIPI_CSI2_DPHY_STATUS_REG(MIPI_CSI2_BASE_PTR)
30219 #define MIPI_CSI2_DPHY_CMN_CTRL                  MIPI_CSI2_DPHY_CMN_CTRL_REG(MIPI_CSI2_BASE_PTR)
30220 #define MIPI_CSI2_DPHY_BCTRL_L                   MIPI_CSI2_DPHY_BCTRL_L_REG(MIPI_CSI2_BASE_PTR)
30221 #define MIPI_CSI2_DPHY_BCTRL_H                   MIPI_CSI2_DPHY_BCTRL_H_REG(MIPI_CSI2_BASE_PTR)
30222 #define MIPI_CSI2_DPHY_SCTRL_L                   MIPI_CSI2_DPHY_SCTRL_L_REG(MIPI_CSI2_BASE_PTR)
30223 #define MIPI_CSI2_DPHY_SCTRL_H                   MIPI_CSI2_DPHY_SCTRL_H_REG(MIPI_CSI2_BASE_PTR)
30224 #define MIPI_CSI2_ISP_CONFIG_CH0                 MIPI_CSI2_ISP_CONFIG_CH0_REG(MIPI_CSI2_BASE_PTR)
30225 #define MIPI_CSI2_ISP_RESOL_CH0                  MIPI_CSI2_ISP_RESOL_CH0_REG(MIPI_CSI2_BASE_PTR)
30226 #define MIPI_CSI2_ISP_SYNC_CH0                   MIPI_CSI2_ISP_SYNC_CH0_REG(MIPI_CSI2_BASE_PTR)
30227 #define MIPI_CSI2_SDW_CONFIG_CH0                 MIPI_CSI2_SDW_CONFIG_CH0_REG(MIPI_CSI2_BASE_PTR)
30228 #define MIPI_CSI2_SDW_RESOL_CH0                  MIPI_CSI2_SDW_RESOL_CH0_REG(MIPI_CSI2_BASE_PTR)
30229 #define MIPI_CSI2_SDW_SYNC_CH0                   MIPI_CSI2_SDW_SYNC_CH0_REG(MIPI_CSI2_BASE_PTR)
30230 #define MIPI_CSI2_DBG_CTRL                       MIPI_CSI2_DBG_CTRL_REG(MIPI_CSI2_BASE_PTR)
30231 #define MIPI_CSI2_DBG_INTR_MSK                   MIPI_CSI2_DBG_INTR_MSK_REG(MIPI_CSI2_BASE_PTR)
30232 #define MIPI_CSI2_DBG_INTR_SRC                   MIPI_CSI2_DBG_INTR_SRC_REG(MIPI_CSI2_BASE_PTR)
30233 #define MIPI_CSI2_NON_IMG_DATA                   MIPI_CSI2_NON_IMG_DATA_REG(MIPI_CSI2_BASE_PTR)
30234 /*!
30235  * @}
30236  */ /* end of group MIPI_CSI2_Register_Accessor_Macros */
30237 
30238 
30239 /*!
30240  * @}
30241  */ /* end of group MIPI_CSI2_Peripheral */
30242 
30243 /* ----------------------------------------------------------------------------
30244    -- MIPI_DSI Peripheral Access Layer
30245    ---------------------------------------------------------------------------- */
30246 
30247 /*!
30248  * @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer
30249  * @{
30250  */
30251 
30252 /** MIPI_DSI - Register Layout Typedef */
30253 typedef struct {
30254   __IO  uint32_t VERSION;                                /**< Version Register, offset: 0x0 */
30255   __IO  uint32_t STATUS;                                 /**< , offset: 0x4 */
30256   __IO  uint32_t RGB_STATUS;                             /**< RGB Status Register, offset: 0x8 */
30257   __IO  uint32_t SWRST;                                  /**< , offset: 0xC */
30258   __IO  uint32_t CLKCTRL;                                /**< Clock Control Register, offset: 0x10 */
30259   __IO  uint32_t TIMEOUT;                                /**< , offset: 0x14 */
30260   __IO  uint32_t CONFIG;                                 /**< , offset: 0x18 */
30261   __IO  uint32_t ESCMODE;                                /**< Escape Mode Register, offset: 0x1C */
30262   __IO  uint32_t MDRESOL;                                /**< Main Display Image Resolution Register, offset: 0x20 */
30263   __IO  uint32_t MVPORCH;                                /**< Main Display VPORCH Register, offset: 0x24 */
30264   __IO  uint32_t MHPORCH;                                /**< , offset: 0x28 */
30265   __IO  uint32_t MSYNC;                                  /**< , offset: 0x2C */
30266   __IO  uint32_t SDRESOL;                                /**< Sub Display Image Resolution Register, offset: 0x30 */
30267   __IO  uint32_t INTSRC;                                 /**< Interrupt Source Register, offset: 0x34 */
30268   __IO  uint32_t INTMSK;                                 /**< Interrupt Mask Register, offset: 0x38 */
30269   __IO  uint32_t PKTHDR;                                 /**< Packet Header FIFO Register, offset: 0x3C */
30270   __IO  uint32_t PAYLOAD;                                /**< Payload FIFO Register, offset: 0x40 */
30271   __IO  uint32_t RXFIFO;                                 /**< Payload FIFO Register, offset: 0x44 */
30272   __IO  uint32_t FIFOTHLD;                               /**< FIFO Threshold Level Register, offset: 0x48 */
30273   __IO  uint32_t FIFOCTRL;                               /**< FIFO Status and Control Register, offset: 0x4C */
30274   __IO  uint32_t MEMACCHR;                               /**< FIFO Memory AC Characteristic Register, offset: 0x50 */
30275   uint8_t RESERVED_0[36];
30276   __IO  uint32_t MULTI_PKT;                              /**< , offset: 0x78 */
30277   uint8_t RESERVED_1[20];
30278   __IO  uint32_t PLLCTRL_1G;                             /**< 1 Gbps D-PHY PLL Control Register, offset: 0x90 */
30279   __IO  uint32_t PLLCTRL;                                /**< PLL Control register, offset: 0x94 */
30280   __IO  uint32_t PLLCTRL1;                               /**< PLL Control Register 1, offset: 0x98 */
30281   __IO  uint32_t PLLCTRL2;                               /**< PLL control register 2, offset: 0x9C */
30282   __IO  uint32_t PLLTMR;                                 /**< PLL Timer Register, offset: 0xA0 */
30283   __IO  uint32_t PHYCTRL_B1;                             /**< D-PHY Master and Slave Analog Block Control Register 1, offset: 0xA4 */
30284   __IO  uint32_t PHYCTRL_B2;                             /**< D-PHY Master and Slave Analog Block Control Register 2, offset: 0xA8 */
30285   __IO  uint32_t PHYCTRL_M1;                             /**< D-PHY Master Analog Block Control Register 1, offset: 0xAC */
30286   __IO  uint32_t PHYCTRL_M2;                             /**< D-PHY Master Analog Block Control Register 1, offset: 0xB0 */
30287   __IO  uint32_t PHYTIMING;                              /**< D-PHY Timing register, offset: 0xB4 */
30288   __IO  uint32_t PHYTIMING1;                             /**< , offset: 0xB8 */
30289   __IO  uint32_t PHYTIMING2;                             /**< D-PHY Timing Register 2, offset: 0xBC */
30290 } MIPI_DSI_Type, *MIPI_DSI_MemMapPtr;
30291 /* ----------------------------------------------------------------------------
30292    -- MIPI_DSI - Register accessor macros
30293    ---------------------------------------------------------------------------- */
30294 
30295 /*!
30296  * @addtogroup MIPI_DSI_Register_Accessor_Macros MIPI_DSI - Register accessor macros
30297  * @{
30298  */
30299 
30300 
30301 /* MIPI_DSI - Register accessors */
30302 #define MIPI_DSI_VERSION_REG(base)               ((base)->VERSION)
30303 #define MIPI_DSI_STATUS_REG(base)                ((base)->STATUS)
30304 #define MIPI_DSI_RGB_STATUS_REG(base)            ((base)->RGB_STATUS)
30305 #define MIPI_DSI_SWRST_REG(base)                 ((base)->SWRST)
30306 #define MIPI_DSI_CLKCTRL_REG(base)               ((base)->CLKCTRL)
30307 #define MIPI_DSI_TIMEOUT_REG(base)               ((base)->TIMEOUT)
30308 #define MIPI_DSI_CONFIG_REG(base)                ((base)->CONFIG)
30309 #define MIPI_DSI_ESCMODE_REG(base)               ((base)->ESCMODE)
30310 #define MIPI_DSI_MDRESOL_REG(base)               ((base)->MDRESOL)
30311 #define MIPI_DSI_MVPORCH_REG(base)               ((base)->MVPORCH)
30312 #define MIPI_DSI_MHPORCH_REG(base)               ((base)->MHPORCH)
30313 #define MIPI_DSI_MSYNC_REG(base)                 ((base)->MSYNC)
30314 #define MIPI_DSI_SDRESOL_REG(base)               ((base)->SDRESOL)
30315 #define MIPI_DSI_INTSRC_REG(base)                ((base)->INTSRC)
30316 #define MIPI_DSI_INTMSK_REG(base)                ((base)->INTMSK)
30317 #define MIPI_DSI_PKTHDR_REG(base)                ((base)->PKTHDR)
30318 #define MIPI_DSI_PAYLOAD_REG(base)               ((base)->PAYLOAD)
30319 #define MIPI_DSI_RXFIFO_REG(base)                ((base)->RXFIFO)
30320 #define MIPI_DSI_FIFOTHLD_REG(base)              ((base)->FIFOTHLD)
30321 #define MIPI_DSI_FIFOCTRL_REG(base)              ((base)->FIFOCTRL)
30322 #define MIPI_DSI_MEMACCHR_REG(base)              ((base)->MEMACCHR)
30323 #define MIPI_DSI_MULTI_PKT_REG(base)             ((base)->MULTI_PKT)
30324 #define MIPI_DSI_PLLCTRL_1G_REG(base)            ((base)->PLLCTRL_1G)
30325 #define MIPI_DSI_PLLCTRL_REG(base)               ((base)->PLLCTRL)
30326 #define MIPI_DSI_PLLCTRL1_REG(base)              ((base)->PLLCTRL1)
30327 #define MIPI_DSI_PLLCTRL2_REG(base)              ((base)->PLLCTRL2)
30328 #define MIPI_DSI_PLLTMR_REG(base)                ((base)->PLLTMR)
30329 #define MIPI_DSI_PHYCTRL_B1_REG(base)            ((base)->PHYCTRL_B1)
30330 #define MIPI_DSI_PHYCTRL_B2_REG(base)            ((base)->PHYCTRL_B2)
30331 #define MIPI_DSI_PHYCTRL_M1_REG(base)            ((base)->PHYCTRL_M1)
30332 #define MIPI_DSI_PHYCTRL_M2_REG(base)            ((base)->PHYCTRL_M2)
30333 #define MIPI_DSI_PHYTIMING_REG(base)             ((base)->PHYTIMING)
30334 #define MIPI_DSI_PHYTIMING1_REG(base)            ((base)->PHYTIMING1)
30335 #define MIPI_DSI_PHYTIMING2_REG(base)            ((base)->PHYTIMING2)
30336 
30337 /*!
30338  * @}
30339  */ /* end of group MIPI_DSI_Register_Accessor_Macros */
30340 /* ----------------------------------------------------------------------------
30341    -- MIPI_DSI Register Masks
30342    ---------------------------------------------------------------------------- */
30343 
30344 /*!
30345  * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks
30346  * @{
30347  */
30348 
30349 /* VERSION Bit Fields */
30350 #define MIPI_DSI_VERSION_VERSION_MASK            0xFFFFFFFFu
30351 #define MIPI_DSI_VERSION_VERSION_SHIFT           0
30352 #define MIPI_DSI_VERSION_VERSION(x)              (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_VERSION_VERSION_SHIFT))&MIPI_DSI_VERSION_VERSION_MASK)
30353 /* STATUS Bit Fields */
30354 #define MIPI_DSI_STATUS_STOPSTATEDAT_MASK        0xFu
30355 #define MIPI_DSI_STATUS_STOPSTATEDAT_SHIFT       0
30356 #define MIPI_DSI_STATUS_STOPSTATEDAT(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_STATUS_STOPSTATEDAT_SHIFT))&MIPI_DSI_STATUS_STOPSTATEDAT_MASK)
30357 #define MIPI_DSI_STATUS_ULPSDAT_MASK             0xF0u
30358 #define MIPI_DSI_STATUS_ULPSDAT_SHIFT            4
30359 #define MIPI_DSI_STATUS_ULPSDAT(x)               (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_STATUS_ULPSDAT_SHIFT))&MIPI_DSI_STATUS_ULPSDAT_MASK)
30360 #define MIPI_DSI_STATUS_STOPSTATECLK_MASK        0x100u
30361 #define MIPI_DSI_STATUS_STOPSTATECLK_SHIFT       8
30362 #define MIPI_DSI_STATUS_ULPSCLK_MASK             0x200u
30363 #define MIPI_DSI_STATUS_ULPSCLK_SHIFT            9
30364 #define MIPI_DSI_STATUS_TXREADYHSCLK_MASK        0x400u
30365 #define MIPI_DSI_STATUS_TXREADYHSCLK_SHIFT       10
30366 #define MIPI_DSI_STATUS_DIRECTION_MASK           0x10000u
30367 #define MIPI_DSI_STATUS_DIRECTION_SHIFT          16
30368 #define MIPI_DSI_STATUS_SWRSTRLS_MASK            0x100000u
30369 #define MIPI_DSI_STATUS_SWRSTRLS_SHIFT           20
30370 #define MIPI_DSI_STATUS_PLLSTABLE_MASK           0x80000000u
30371 #define MIPI_DSI_STATUS_PLLSTABLE_SHIFT          31
30372 /* RGB_STATUS Bit Fields */
30373 #define MIPI_DSI_RGB_STATUS_RGBSTATE_MASK        0x1FFFu
30374 #define MIPI_DSI_RGB_STATUS_RGBSTATE_SHIFT       0
30375 #define MIPI_DSI_RGB_STATUS_RGBSTATE(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_RGB_STATUS_RGBSTATE_SHIFT))&MIPI_DSI_RGB_STATUS_RGBSTATE_MASK)
30376 #define MIPI_DSI_RGB_STATUS_CMDMODE_INSEL_MASK   0x80000000u
30377 #define MIPI_DSI_RGB_STATUS_CMDMODE_INSEL_SHIFT  31
30378 /* SWRST Bit Fields */
30379 #define MIPI_DSI_SWRST_SWRST_MASK                0x1u
30380 #define MIPI_DSI_SWRST_SWRST_SHIFT               0
30381 #define MIPI_DSI_SWRST_FUNCRST_MASK              0x10000u
30382 #define MIPI_DSI_SWRST_FUNCRST_SHIFT             16
30383 /* CLKCTRL Bit Fields */
30384 #define MIPI_DSI_CLKCTRL_ESCPRESCALER_MASK       0xFFFFu
30385 #define MIPI_DSI_CLKCTRL_ESCPRESCALER_SHIFT      0
30386 #define MIPI_DSI_CLKCTRL_ESCPRESCALER(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CLKCTRL_ESCPRESCALER_SHIFT))&MIPI_DSI_CLKCTRL_ESCPRESCALER_MASK)
30387 #define MIPI_DSI_CLKCTRL_LANEESCCLKEN_MASK       0xF80000u
30388 #define MIPI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT      19
30389 #define MIPI_DSI_CLKCTRL_LANEESCCLKEN(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT))&MIPI_DSI_CLKCTRL_LANEESCCLKEN_MASK)
30390 #define MIPI_DSI_CLKCTRL_ByteClkEn_MASK          0x1000000u
30391 #define MIPI_DSI_CLKCTRL_ByteClkEn_SHIFT         24
30392 #define MIPI_DSI_CLKCTRL_BYTECLKSRC_MASK         0x6000000u
30393 #define MIPI_DSI_CLKCTRL_BYTECLKSRC_SHIFT        25
30394 #define MIPI_DSI_CLKCTRL_BYTECLKSRC(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CLKCTRL_BYTECLKSRC_SHIFT))&MIPI_DSI_CLKCTRL_BYTECLKSRC_MASK)
30395 #define MIPI_DSI_CLKCTRL_PLLBYPASS_MASK          0x8000000u
30396 #define MIPI_DSI_CLKCTRL_PLLBYPASS_SHIFT         27
30397 #define MIPI_DSI_CLKCTRL_ESCCLKEN_MASK           0x10000000u
30398 #define MIPI_DSI_CLKCTRL_ESCCLKEN_SHIFT          28
30399 #define MIPI_DSI_CLKCTRL_DPHY_SEL_MASK           0x20000000u
30400 #define MIPI_DSI_CLKCTRL_DPHY_SEL_SHIFT          29
30401 #define MIPI_DSI_CLKCTRL_TXREQUESTHSCLK_MASK     0x80000000u
30402 #define MIPI_DSI_CLKCTRL_TXREQUESTHSCLK_SHIFT    31
30403 /* TIMEOUT Bit Fields */
30404 #define MIPI_DSI_TIMEOUT_LPDRTOUT_MASK           0xFFFFu
30405 #define MIPI_DSI_TIMEOUT_LPDRTOUT_SHIFT          0
30406 #define MIPI_DSI_TIMEOUT_LPDRTOUT(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_TIMEOUT_LPDRTOUT_SHIFT))&MIPI_DSI_TIMEOUT_LPDRTOUT_MASK)
30407 #define MIPI_DSI_TIMEOUT_BTAOUT_MASK             0xFF0000u
30408 #define MIPI_DSI_TIMEOUT_BTAOUT_SHIFT            16
30409 #define MIPI_DSI_TIMEOUT_BTAOUT(x)               (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_TIMEOUT_BTAOUT_SHIFT))&MIPI_DSI_TIMEOUT_BTAOUT_MASK)
30410 /* CONFIG Bit Fields */
30411 #define MIPI_DSI_CONFIG_LANEEN_MASK              0x1Fu
30412 #define MIPI_DSI_CONFIG_LANEEN_SHIFT             0
30413 #define MIPI_DSI_CONFIG_LANEEN(x)                (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_LANEEN_SHIFT))&MIPI_DSI_CONFIG_LANEEN_MASK)
30414 #define MIPI_DSI_CONFIG_NUMOFDATLANE_MASK        0x60u
30415 #define MIPI_DSI_CONFIG_NUMOFDATLANE_SHIFT       5
30416 #define MIPI_DSI_CONFIG_NUMOFDATLANE(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_NUMOFDATLANE_SHIFT))&MIPI_DSI_CONFIG_NUMOFDATLANE_MASK)
30417 #define MIPI_DSI_CONFIG_SUBPIXFORMAT_MASK        0x700u
30418 #define MIPI_DSI_CONFIG_SUBPIXFORMAT_SHIFT       8
30419 #define MIPI_DSI_CONFIG_SUBPIXFORMAT(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_SUBPIXFORMAT_SHIFT))&MIPI_DSI_CONFIG_SUBPIXFORMAT_MASK)
30420 #define MIPI_DSI_CONFIG_MAINPIXFORMAT_MASK       0x7000u
30421 #define MIPI_DSI_CONFIG_MAINPIXFORMAT_SHIFT      12
30422 #define MIPI_DSI_CONFIG_MAINPIXFORMAT(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_MAINPIXFORMAT_SHIFT))&MIPI_DSI_CONFIG_MAINPIXFORMAT_MASK)
30423 #define MIPI_DSI_CONFIG_SUBVC_MASK               0x30000u
30424 #define MIPI_DSI_CONFIG_SUBVC_SHIFT              16
30425 #define MIPI_DSI_CONFIG_SUBVC(x)                 (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_SUBVC_SHIFT))&MIPI_DSI_CONFIG_SUBVC_MASK)
30426 #define MIPI_DSI_CONFIG_MAINVC_MASK              0xC0000u
30427 #define MIPI_DSI_CONFIG_MAINVC_SHIFT             18
30428 #define MIPI_DSI_CONFIG_MAINVC(x)                (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_MAINVC_SHIFT))&MIPI_DSI_CONFIG_MAINVC_MASK)
30429 #define MIPI_DSI_CONFIG_HSADISABLEMODE_MASK      0x100000u
30430 #define MIPI_DSI_CONFIG_HSADISABLEMODE_SHIFT     20
30431 #define MIPI_DSI_CONFIG_HBPDISABLEMODE_MASK      0x200000u
30432 #define MIPI_DSI_CONFIG_HBPDISABLEMODE_SHIFT     21
30433 #define MIPI_DSI_CONFIG_HFPDISABLEMODE_MASK      0x400000u
30434 #define MIPI_DSI_CONFIG_HFPDISABLEMODE_SHIFT     22
30435 #define MIPI_DSI_CONFIG_HSEDISABLEMODE_MASK      0x800000u
30436 #define MIPI_DSI_CONFIG_HSEDISABLEMODE_SHIFT     23
30437 #define MIPI_DSI_CONFIG_AUTOMODE_MASK            0x1000000u
30438 #define MIPI_DSI_CONFIG_AUTOMODE_SHIFT           24
30439 #define MIPI_DSI_CONFIG_VIDEOMODE_MASK           0x2000000u
30440 #define MIPI_DSI_CONFIG_VIDEOMODE_SHIFT          25
30441 #define MIPI_DSI_CONFIG_BURSTMODE_MASK           0x4000000u
30442 #define MIPI_DSI_CONFIG_BURSTMODE_SHIFT          26
30443 #define MIPI_DSI_CONFIG_SYNCINFORM_MASK          0x8000000u
30444 #define MIPI_DSI_CONFIG_SYNCINFORM_SHIFT         27
30445 #define MIPI_DSI_CONFIG_EOT_R03_MASK             0x10000000u
30446 #define MIPI_DSI_CONFIG_EOT_R03_SHIFT            28
30447 #define MIPI_DSI_CONFIG_MFLUSH_VS_MASK           0x20000000u
30448 #define MIPI_DSI_CONFIG_MFLUSH_VS_SHIFT          29
30449 #define MIPI_DSI_CONFIG_CLKLANE_STOP_START_MASK  0x40000000u
30450 #define MIPI_DSI_CONFIG_CLKLANE_STOP_START_SHIFT 30
30451 #define MIPI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_MASK 0x80000000u
30452 #define MIPI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_SHIFT 31
30453 /* ESCMODE Bit Fields */
30454 #define MIPI_DSI_ESCMODE_TXULPSCLKEXIT_MASK      0x1u
30455 #define MIPI_DSI_ESCMODE_TXULPSCLKEXIT_SHIFT     0
30456 #define MIPI_DSI_ESCMODE_TXULPSCLK_MASK          0x2u
30457 #define MIPI_DSI_ESCMODE_TXULPSCLK_SHIFT         1
30458 #define MIPI_DSI_ESCMODE_TXULPSEXIT_MASK         0x4u
30459 #define MIPI_DSI_ESCMODE_TXULPSEXIT_SHIFT        2
30460 #define MIPI_DSI_ESCMODE_TXULPSDAT_MASK          0x8u
30461 #define MIPI_DSI_ESCMODE_TXULPSDAT_SHIFT         3
30462 #define MIPI_DSI_ESCMODE_TXTRIGGERRST_MASK       0x10u
30463 #define MIPI_DSI_ESCMODE_TXTRIGGERRST_SHIFT      4
30464 #define MIPI_DSI_ESCMODE_TXLPDT_MASK             0x40u
30465 #define MIPI_DSI_ESCMODE_TXLPDT_SHIFT            6
30466 #define MIPI_DSI_ESCMODE_CMDLPDT_MASK            0x80u
30467 #define MIPI_DSI_ESCMODE_CMDLPDT_SHIFT           7
30468 #define MIPI_DSI_ESCMODE_FORCEBTA_MASK           0x10000u
30469 #define MIPI_DSI_ESCMODE_FORCEBTA_SHIFT          16
30470 #define MIPI_DSI_ESCMODE_FORCESTOPSTATE_MASK     0x100000u
30471 #define MIPI_DSI_ESCMODE_FORCESTOPSTATE_SHIFT    20
30472 #define MIPI_DSI_ESCMODE_STOPSTATE_CNT_MASK      0xFFE00000u
30473 #define MIPI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT     21
30474 #define MIPI_DSI_ESCMODE_STOPSTATE_CNT(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT))&MIPI_DSI_ESCMODE_STOPSTATE_CNT_MASK)
30475 /* MDRESOL Bit Fields */
30476 #define MIPI_DSI_MDRESOL_MAINHRESOL_MASK         0xFFFu
30477 #define MIPI_DSI_MDRESOL_MAINHRESOL_SHIFT        0
30478 #define MIPI_DSI_MDRESOL_MAINHRESOL(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MDRESOL_MAINHRESOL_SHIFT))&MIPI_DSI_MDRESOL_MAINHRESOL_MASK)
30479 #define MIPI_DSI_MDRESOL_MainVResol_MASK         0xFFF0000u
30480 #define MIPI_DSI_MDRESOL_MainVResol_SHIFT        16
30481 #define MIPI_DSI_MDRESOL_MainVResol(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MDRESOL_MainVResol_SHIFT))&MIPI_DSI_MDRESOL_MainVResol_MASK)
30482 #define MIPI_DSI_MDRESOL_MAINSTANDBY_MASK        0x80000000u
30483 #define MIPI_DSI_MDRESOL_MAINSTANDBY_SHIFT       31
30484 /* MVPORCH Bit Fields */
30485 #define MIPI_DSI_MVPORCH_MAINVBP_MASK            0x7FFu
30486 #define MIPI_DSI_MVPORCH_MAINVBP_SHIFT           0
30487 #define MIPI_DSI_MVPORCH_MAINVBP(x)              (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MVPORCH_MAINVBP_SHIFT))&MIPI_DSI_MVPORCH_MAINVBP_MASK)
30488 #define MIPI_DSI_MVPORCH_STABLEVFP_MASK          0x7FF0000u
30489 #define MIPI_DSI_MVPORCH_STABLEVFP_SHIFT         16
30490 #define MIPI_DSI_MVPORCH_STABLEVFP(x)            (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MVPORCH_STABLEVFP_SHIFT))&MIPI_DSI_MVPORCH_STABLEVFP_MASK)
30491 #define MIPI_DSI_MVPORCH_CMDALLOW_MASK           0xF0000000u
30492 #define MIPI_DSI_MVPORCH_CMDALLOW_SHIFT          28
30493 #define MIPI_DSI_MVPORCH_CMDALLOW(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MVPORCH_CMDALLOW_SHIFT))&MIPI_DSI_MVPORCH_CMDALLOW_MASK)
30494 /* MHPORCH Bit Fields */
30495 #define MIPI_DSI_MHPORCH_MAINHBP_MASK            0xFFFFu
30496 #define MIPI_DSI_MHPORCH_MAINHBP_SHIFT           0
30497 #define MIPI_DSI_MHPORCH_MAINHBP(x)              (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MHPORCH_MAINHBP_SHIFT))&MIPI_DSI_MHPORCH_MAINHBP_MASK)
30498 #define MIPI_DSI_MHPORCH_MAINHFP_MASK            0xFFFF0000u
30499 #define MIPI_DSI_MHPORCH_MAINHFP_SHIFT           16
30500 #define MIPI_DSI_MHPORCH_MAINHFP(x)              (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MHPORCH_MAINHFP_SHIFT))&MIPI_DSI_MHPORCH_MAINHFP_MASK)
30501 /* MSYNC Bit Fields */
30502 #define MIPI_DSI_MSYNC_MAINHSA_MASK              0xFFFFu
30503 #define MIPI_DSI_MSYNC_MAINHSA_SHIFT             0
30504 #define MIPI_DSI_MSYNC_MAINHSA(x)                (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MSYNC_MAINHSA_SHIFT))&MIPI_DSI_MSYNC_MAINHSA_MASK)
30505 #define MIPI_DSI_MSYNC_MAINVSA_MASK              0xFFC00000u
30506 #define MIPI_DSI_MSYNC_MAINVSA_SHIFT             22
30507 #define MIPI_DSI_MSYNC_MAINVSA(x)                (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MSYNC_MAINVSA_SHIFT))&MIPI_DSI_MSYNC_MAINVSA_MASK)
30508 /* SDRESOL Bit Fields */
30509 #define MIPI_DSI_SDRESOL_SUBHRESOL_MASK          0x7FFu
30510 #define MIPI_DSI_SDRESOL_SUBHRESOL_SHIFT         0
30511 #define MIPI_DSI_SDRESOL_SUBHRESOL(x)            (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_SDRESOL_SUBHRESOL_SHIFT))&MIPI_DSI_SDRESOL_SUBHRESOL_MASK)
30512 #define MIPI_DSI_SDRESOL_SUBVRESOL_MASK          0x7FF0000u
30513 #define MIPI_DSI_SDRESOL_SUBVRESOL_SHIFT         16
30514 #define MIPI_DSI_SDRESOL_SUBVRESOL(x)            (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_SDRESOL_SUBVRESOL_SHIFT))&MIPI_DSI_SDRESOL_SUBVRESOL_MASK)
30515 #define MIPI_DSI_SDRESOL_SUBSTANDBY_MASK         0x80000000u
30516 #define MIPI_DSI_SDRESOL_SUBSTANDBY_SHIFT        31
30517 /* INTSRC Bit Fields */
30518 #define MIPI_DSI_INTSRC_ERRCONTENTLP1_MASK       0x1u
30519 #define MIPI_DSI_INTSRC_ERRCONTENTLP1_SHIFT      0
30520 #define MIPI_DSI_INTSRC_ERRCONTENTLP0_MASK       0x2u
30521 #define MIPI_DSI_INTSRC_ERRCONTENTLP0_SHIFT      1
30522 #define MIPI_DSI_INTSRC_ERRCONTROL0_MASK         0x4u
30523 #define MIPI_DSI_INTSRC_ERRCONTROL0_SHIFT        2
30524 #define MIPI_DSI_INTSRC_ERRCONTROL1_MASK         0x8u
30525 #define MIPI_DSI_INTSRC_ERRCONTROL1_SHIFT        3
30526 #define MIPI_DSI_INTSRC_ERRSYNC0_MASK            0x40u
30527 #define MIPI_DSI_INTSRC_ERRSYNC0_SHIFT           6
30528 #define MIPI_DSI_INTSRC_ERRSYNC1_MASK            0x80u
30529 #define MIPI_DSI_INTSRC_ERRSYNC1_SHIFT           7
30530 #define MIPI_DSI_INTSRC_ERRESC0_MASK             0x400u
30531 #define MIPI_DSI_INTSRC_ERRESC0_SHIFT            10
30532 #define MIPI_DSI_INTSRC_ERRESC1_MASK             0x800u
30533 #define MIPI_DSI_INTSRC_ERRESC1_SHIFT            11
30534 #define MIPI_DSI_INTSRC_ERRRXCRC_MASK            0x4000u
30535 #define MIPI_DSI_INTSRC_ERRRXCRC_SHIFT           14
30536 #define MIPI_DSI_INTSRC_ERRRXECC_MASK            0x8000u
30537 #define MIPI_DSI_INTSRC_ERRRXECC_SHIFT           15
30538 #define MIPI_DSI_INTSRC_RXACK_MASK               0x10000u
30539 #define MIPI_DSI_INTSRC_RXACK_SHIFT              16
30540 #define MIPI_DSI_INTSRC_RXTE_MASK                0x20000u
30541 #define MIPI_DSI_INTSRC_RXTE_SHIFT               17
30542 #define MIPI_DSI_INTSRC_RXDATDONE_MASK           0x40000u
30543 #define MIPI_DSI_INTSRC_RXDATDONE_SHIFT          18
30544 #define MIPI_DSI_INTSRC_TATOUT_MASK              0x100000u
30545 #define MIPI_DSI_INTSRC_TATOUT_SHIFT             20
30546 #define MIPI_DSI_INTSRC_LPDRTOUT_MASK            0x200000u
30547 #define MIPI_DSI_INTSRC_LPDRTOUT_SHIFT           21
30548 #define MIPI_DSI_INTSRC_FRAMEDONE_MASK           0x1000000u
30549 #define MIPI_DSI_INTSRC_FRAMEDONE_SHIFT          24
30550 #define MIPI_DSI_INTSRC_BUSTURNOVER_MASK         0x2000000u
30551 #define MIPI_DSI_INTSRC_BUSTURNOVER_SHIFT        25
30552 #define MIPI_DSI_INTSRC_SYNCOVERRIDE_MASK        0x8000000u
30553 #define MIPI_DSI_INTSRC_SYNCOVERRIDE_SHIFT       27
30554 #define MIPI_DSI_INTSRC_SFRPHFIFOEMPTY_MASK      0x10000000u
30555 #define MIPI_DSI_INTSRC_SFRPHFIFOEMPTY_SHIFT     28
30556 #define MIPI_DSI_INTSRC_SFRPLFIFOEMPTY_MASK      0x20000000u
30557 #define MIPI_DSI_INTSRC_SFRPLFIFOEMPTY_SHIFT     29
30558 #define MIPI_DSI_INTSRC_SWRSTRELEASE_MASK        0x40000000u
30559 #define MIPI_DSI_INTSRC_SWRSTRELEASE_SHIFT       30
30560 #define MIPI_DSI_INTSRC_PLLSTABLE_MASK           0x80000000u
30561 #define MIPI_DSI_INTSRC_PLLSTABLE_SHIFT          31
30562 /* INTMSK Bit Fields */
30563 #define MIPI_DSI_INTMSK_MSKCONTENTLP1_MASK       0x1u
30564 #define MIPI_DSI_INTMSK_MSKCONTENTLP1_SHIFT      0
30565 #define MIPI_DSI_INTMSK_MSKCONTENTLP0_MASK       0x2u
30566 #define MIPI_DSI_INTMSK_MSKCONTENTLP0_SHIFT      1
30567 #define MIPI_DSI_INTMSK_MSKCONTROL0_MASK         0x4u
30568 #define MIPI_DSI_INTMSK_MSKCONTROL0_SHIFT        2
30569 #define MIPI_DSI_INTMSK_MSKCONTROL1_MASK         0x8u
30570 #define MIPI_DSI_INTMSK_MSKCONTROL1_SHIFT        3
30571 #define MIPI_DSI_INTMSK_MSKSYNC0_MASK            0x40u
30572 #define MIPI_DSI_INTMSK_MSKSYNC0_SHIFT           6
30573 #define MIPI_DSI_INTMSK_MSKSYNC1_MASK            0x80u
30574 #define MIPI_DSI_INTMSK_MSKSYNC1_SHIFT           7
30575 #define MIPI_DSI_INTMSK_MSKESC0_MASK             0x400u
30576 #define MIPI_DSI_INTMSK_MSKESC0_SHIFT            10
30577 #define MIPI_DSI_INTMSK_MSKESC1_MASK             0x800u
30578 #define MIPI_DSI_INTMSK_MSKESC1_SHIFT            11
30579 #define MIPI_DSI_INTMSK_MSKRXCRC_MASK            0x4000u
30580 #define MIPI_DSI_INTMSK_MSKRXCRC_SHIFT           14
30581 #define MIPI_DSI_INTMSK_MSKRXECC_MASK            0x8000u
30582 #define MIPI_DSI_INTMSK_MSKRXECC_SHIFT           15
30583 #define MIPI_DSI_INTMSK_MSKRXACK_MASK            0x10000u
30584 #define MIPI_DSI_INTMSK_MSKRXACK_SHIFT           16
30585 #define MIPI_DSI_INTMSK_MSKRXTE_MASK             0x20000u
30586 #define MIPI_DSI_INTMSK_MSKRXTE_SHIFT            17
30587 #define MIPI_DSI_INTMSK_MSKRXDATDONE_MASK        0x40000u
30588 #define MIPI_DSI_INTMSK_MSKRXDATDONE_SHIFT       18
30589 #define MIPI_DSI_INTMSK_MSKTATOUT_MASK           0x100000u
30590 #define MIPI_DSI_INTMSK_MSKTATOUT_SHIFT          20
30591 #define MIPI_DSI_INTMSK_MSKLPDRTOUT_MASK         0x200000u
30592 #define MIPI_DSI_INTMSK_MSKLPDRTOUT_SHIFT        21
30593 #define MIPI_DSI_INTMSK_MSKFRAMEDONE_MASK        0x1000000u
30594 #define MIPI_DSI_INTMSK_MSKFRAMEDONE_SHIFT       24
30595 #define MIPI_DSI_INTMSK_MSKBUSTURNOVER_MASK      0x2000000u
30596 #define MIPI_DSI_INTMSK_MSKBUSTURNOVER_SHIFT     25
30597 #define MIPI_DSI_INTMSK_MSKSYNCOVERRIDE_MASK     0x8000000u
30598 #define MIPI_DSI_INTMSK_MSKSYNCOVERRIDE_SHIFT    27
30599 #define MIPI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_MASK   0x10000000u
30600 #define MIPI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_SHIFT  28
30601 #define MIPI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_MASK   0x20000000u
30602 #define MIPI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_SHIFT  29
30603 #define MIPI_DSI_INTMSK_MSKSWRSTRELEASE_MASK     0x40000000u
30604 #define MIPI_DSI_INTMSK_MSKSWRSTRELEASE_SHIFT    30
30605 #define MIPI_DSI_INTMSK_MSKPLLSTABLE_MASK        0x80000000u
30606 #define MIPI_DSI_INTMSK_MSKPLLSTABLE_SHIFT       31
30607 /* PKTHDR Bit Fields */
30608 #define MIPI_DSI_PKTHDR_PACKETHEADER_MASK        0xFFFFFFu
30609 #define MIPI_DSI_PKTHDR_PACKETHEADER_SHIFT       0
30610 #define MIPI_DSI_PKTHDR_PACKETHEADER(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PKTHDR_PACKETHEADER_SHIFT))&MIPI_DSI_PKTHDR_PACKETHEADER_MASK)
30611 /* PAYLOAD Bit Fields */
30612 #define MIPI_DSI_PAYLOAD_PAYLOAD_MASK            0xFFFFFFFFu
30613 #define MIPI_DSI_PAYLOAD_PAYLOAD_SHIFT           0
30614 #define MIPI_DSI_PAYLOAD_PAYLOAD(x)              (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PAYLOAD_PAYLOAD_SHIFT))&MIPI_DSI_PAYLOAD_PAYLOAD_MASK)
30615 /* RXFIFO Bit Fields */
30616 #define MIPI_DSI_RXFIFO_RXFIFO_MASK              0xFFFFFFFFu
30617 #define MIPI_DSI_RXFIFO_RXFIFO_SHIFT             0
30618 #define MIPI_DSI_RXFIFO_RXFIFO(x)                (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_RXFIFO_RXFIFO_SHIFT))&MIPI_DSI_RXFIFO_RXFIFO_MASK)
30619 /* FIFOTHLD Bit Fields */
30620 #define MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK     0x1FFu
30621 #define MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT    0
30622 #define MIPI_DSI_FIFOTHLD_WFULLLEVELSFR(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT))&MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK)
30623 /* FIFOCTRL Bit Fields */
30624 #define MIPI_DSI_FIFOCTRL_NINITMAIN_MASK         0x1u
30625 #define MIPI_DSI_FIFOCTRL_NINITMAIN_SHIFT        0
30626 #define MIPI_DSI_FIFOCTRL_NINITSUB_MASK          0x2u
30627 #define MIPI_DSI_FIFOCTRL_NINITSUB_SHIFT         1
30628 #define MIPI_DSI_FIFOCTRL_NLNITL80_MASK          0x4u
30629 #define MIPI_DSI_FIFOCTRL_NLNITL80_SHIFT         2
30630 #define MIPI_DSI_FIFOCTRL_NINITSFR_MASK          0x8u
30631 #define MIPI_DSI_FIFOCTRL_NINITSFR_SHIFT         3
30632 #define MIPI_DSI_FIFOCTRL_NINITRX_MASK           0x10u
30633 #define MIPI_DSI_FIFOCTRL_NINITRX_SHIFT          4
30634 #define MIPI_DSI_FIFOCTRL_EMPTYLMAIN_MASK        0x100u
30635 #define MIPI_DSI_FIFOCTRL_EMPTYLMAIN_SHIFT       8
30636 #define MIPI_DSI_FIFOCTRL_FULLLMAIN_MASK         0x200u
30637 #define MIPI_DSI_FIFOCTRL_FULLLMAIN_SHIFT        9
30638 #define MIPI_DSI_FIFOCTRL_EMPTYHMAIN_MASK        0x400u
30639 #define MIPI_DSI_FIFOCTRL_EMPTYHMAIN_SHIFT       10
30640 #define MIPI_DSI_FIFOCTRL_FULLHMAIN_MASK         0x800u
30641 #define MIPI_DSI_FIFOCTRL_FULLHMAIN_SHIFT        11
30642 #define MIPI_DSI_FIFOCTRL_EMPTYLSUB_MASK         0x1000u
30643 #define MIPI_DSI_FIFOCTRL_EMPTYLSUB_SHIFT        12
30644 #define MIPI_DSI_FIFOCTRL_FULLLSUB_MASK          0x2000u
30645 #define MIPI_DSI_FIFOCTRL_FULLLSUB_SHIFT         13
30646 #define MIPI_DSI_FIFOCTRL_EMPTYHSUB_MASK         0x4000u
30647 #define MIPI_DSI_FIFOCTRL_EMPTYHSUB_SHIFT        14
30648 #define MIPI_DSI_FIFOCTRL_FULLHSUB_MASK          0x8000u
30649 #define MIPI_DSI_FIFOCTRL_FULLHSUB_SHIFT         15
30650 #define MIPI_DSI_FIFOCTRL_EMPTYLI80_MASK         0x10000u
30651 #define MIPI_DSI_FIFOCTRL_EMPTYLI80_SHIFT        16
30652 #define MIPI_DSI_FIFOCTRL_FULLLI80_MASK          0x20000u
30653 #define MIPI_DSI_FIFOCTRL_FULLLI80_SHIFT         17
30654 #define MIPI_DSI_FIFOCTRL_EMPTYHI80_MASK         0x40000u
30655 #define MIPI_DSI_FIFOCTRL_EMPTYHI80_SHIFT        18
30656 #define MIPI_DSI_FIFOCTRL_FULLHI80_MASK          0x80000u
30657 #define MIPI_DSI_FIFOCTRL_FULLHI80_SHIFT         19
30658 #define MIPI_DSI_FIFOCTRL_EMPTYLSFR_MASK         0x100000u
30659 #define MIPI_DSI_FIFOCTRL_EMPTYLSFR_SHIFT        20
30660 #define MIPI_DSI_FIFOCTRL_FULLLSFR_MASK          0x200000u
30661 #define MIPI_DSI_FIFOCTRL_FULLLSFR_SHIFT         21
30662 #define MIPI_DSI_FIFOCTRL_EMPTYHSFR_MASK         0x400000u
30663 #define MIPI_DSI_FIFOCTRL_EMPTYHSFR_SHIFT        22
30664 #define MIPI_DSI_FIFOCTRL_FullHSfr_MASK          0x800000u
30665 #define MIPI_DSI_FIFOCTRL_FullHSfr_SHIFT         23
30666 #define MIPI_DSI_FIFOCTRL_EMPTYRX_MASK           0x1000000u
30667 #define MIPI_DSI_FIFOCTRL_EMPTYRX_SHIFT          24
30668 #define MIPI_DSI_FIFOCTRL_FULLRX_MASK            0x2000000u
30669 #define MIPI_DSI_FIFOCTRL_FULLRX_SHIFT           25
30670 /* MEMACCHR Bit Fields */
30671 #define MIPI_DSI_MEMACCHR_EMAA_MD_MASK           0x7u
30672 #define MIPI_DSI_MEMACCHR_EMAA_MD_SHIFT          0
30673 #define MIPI_DSI_MEMACCHR_EMAA_MD(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAA_MD_SHIFT))&MIPI_DSI_MEMACCHR_EMAA_MD_MASK)
30674 #define MIPI_DSI_MEMACCHR_EMAB_MD_MASK           0x38u
30675 #define MIPI_DSI_MEMACCHR_EMAB_MD_SHIFT          3
30676 #define MIPI_DSI_MEMACCHR_EMAB_MD(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAB_MD_SHIFT))&MIPI_DSI_MEMACCHR_EMAB_MD_MASK)
30677 #define MIPI_DSI_MEMACCHR_RETN_MD_MASK           0x40u
30678 #define MIPI_DSI_MEMACCHR_RETN_MD_SHIFT          6
30679 #define MIPI_DSI_MEMACCHR_PGEN_MD_MASK           0x80u
30680 #define MIPI_DSI_MEMACCHR_PGEN_MD_SHIFT          7
30681 #define MIPI_DSI_MEMACCHR_EMAA_SD_MASK           0x700u
30682 #define MIPI_DSI_MEMACCHR_EMAA_SD_SHIFT          8
30683 #define MIPI_DSI_MEMACCHR_EMAA_SD(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAA_SD_SHIFT))&MIPI_DSI_MEMACCHR_EMAA_SD_MASK)
30684 #define MIPI_DSI_MEMACCHR_EMAB_SD_MASK           0x3800u
30685 #define MIPI_DSI_MEMACCHR_EMAB_SD_SHIFT          11
30686 #define MIPI_DSI_MEMACCHR_EMAB_SD(x)             (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAB_SD_SHIFT))&MIPI_DSI_MEMACCHR_EMAB_SD_MASK)
30687 #define MIPI_DSI_MEMACCHR_RETN_SD_MASK           0x4000u
30688 #define MIPI_DSI_MEMACCHR_RETN_SD_SHIFT          14
30689 #define MIPI_DSI_MEMACCHR_PGEN_SD_MASK           0x8000u
30690 #define MIPI_DSI_MEMACCHR_PGEN_SD_SHIFT          15
30691 /* MULTI_PKT Bit Fields */
30692 #define MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK 0xFFFFu
30693 #define MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT 0
30694 #define MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF(x)  (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT))&MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK)
30695 #define MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK 0xFFF0000u
30696 #define MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT 16
30697 #define MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF(x)   (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT))&MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK)
30698 #define MIPI_DSI_MULTI_PKT_PKT_GO_RDY_MASK       0x10000000u
30699 #define MIPI_DSI_MULTI_PKT_PKT_GO_RDY_SHIFT      28
30700 #define MIPI_DSI_MULTI_PKT_PKT_GO_EN_MASK        0x20000000u
30701 #define MIPI_DSI_MULTI_PKT_PKT_GO_EN_SHIFT       29
30702 #define MIPI_DSI_MULTI_PKT_MULTI_PKT_EN_MASK     0x40000000u
30703 #define MIPI_DSI_MULTI_PKT_MULTI_PKT_EN_SHIFT    30
30704 /* PLLCTRL_1G Bit Fields */
30705 #define MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK      0x7u
30706 #define MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT     0
30707 #define MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT))&MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK)
30708 #define MIPI_DSI_PLLCTRL_1G_PREPRCTL_MASK        0x70u
30709 #define MIPI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT       4
30710 #define MIPI_DSI_PLLCTRL_1G_PREPRCTL(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT))&MIPI_DSI_PLLCTRL_1G_PREPRCTL_MASK)
30711 #define MIPI_DSI_PLLCTRL_1G_FREQ_BAND_MASK       0xF00u
30712 #define MIPI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT      8
30713 #define MIPI_DSI_PLLCTRL_1G_FREQ_BAND(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT))&MIPI_DSI_PLLCTRL_1G_FREQ_BAND_MASK)
30714 #define MIPI_DSI_PLLCTRL_1G_HSZEROCTL_MASK       0xF000u
30715 #define MIPI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT      12
30716 #define MIPI_DSI_PLLCTRL_1G_HSZEROCTL(x)         (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT))&MIPI_DSI_PLLCTRL_1G_HSZEROCTL_MASK)
30717 /* PLLCTRL Bit Fields */
30718 #define MIPI_DSI_PLLCTRL_PMS_MASK                0xFFFFEu
30719 #define MIPI_DSI_PLLCTRL_PMS_SHIFT               1
30720 #define MIPI_DSI_PLLCTRL_PMS(x)                  (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_PMS_SHIFT))&MIPI_DSI_PLLCTRL_PMS_MASK)
30721 #define MIPI_DSI_PLLCTRL_PLLEN_MASK              0x800000u
30722 #define MIPI_DSI_PLLCTRL_PLLEN_SHIFT             23
30723 #define MIPI_DSI_PLLCTRL_DPDNSWAP_DAT_MASK       0x1000000u
30724 #define MIPI_DSI_PLLCTRL_DPDNSWAP_DAT_SHIFT      24
30725 #define MIPI_DSI_PLLCTRL_DPDNSWAP_CLK_MASK       0x2000000u
30726 #define MIPI_DSI_PLLCTRL_DPDNSWAP_CLK_SHIFT      25
30727 /* PLLCTRL1 Bit Fields */
30728 #define MIPI_DSI_PLLCTRL1_M_PLLCTL0_MASK         0xFFFFFFFFu
30729 #define MIPI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT        0
30730 #define MIPI_DSI_PLLCTRL1_M_PLLCTL0(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT))&MIPI_DSI_PLLCTRL1_M_PLLCTL0_MASK)
30731 /* PLLCTRL2 Bit Fields */
30732 #define MIPI_DSI_PLLCTRL2_M_PLLCTL1_MASK         0xFFu
30733 #define MIPI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT        0
30734 #define MIPI_DSI_PLLCTRL2_M_PLLCTL1(x)           (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT))&MIPI_DSI_PLLCTRL2_M_PLLCTL1_MASK)
30735 /* PLLTMR Bit Fields */
30736 #define MIPI_DSI_PLLTMR_PLLTIMER_MASK            0xFFFFFFFFu
30737 #define MIPI_DSI_PLLTMR_PLLTIMER_SHIFT           0
30738 #define MIPI_DSI_PLLTMR_PLLTIMER(x)              (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLTMR_PLLTIMER_SHIFT))&MIPI_DSI_PLLTMR_PLLTIMER_MASK)
30739 /* PHYCTRL_B1 Bit Fields */
30740 #define MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK      0xFFFFFFFFu
30741 #define MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT     0
30742 #define MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT))&MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK)
30743 /* PHYCTRL_B2 Bit Fields */
30744 #define MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK      0xFFFFFFFFu
30745 #define MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT     0
30746 #define MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT))&MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK)
30747 /* PHYCTRL_M1 Bit Fields */
30748 #define MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK      0xFFFFFFFFu
30749 #define MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT     0
30750 #define MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT))&MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK)
30751 /* PHYCTRL_M2 Bit Fields */
30752 #define MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK      0xFFFFFFFFu
30753 #define MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT     0
30754 #define MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1(x)        (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT))&MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK)
30755 /* PHYTIMING Bit Fields */
30756 #define MIPI_DSI_PHYTIMING_M_THSEXITCTL_MASK     0xFFu
30757 #define MIPI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT    0
30758 #define MIPI_DSI_PHYTIMING_M_THSEXITCTL(x)       (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT))&MIPI_DSI_PHYTIMING_M_THSEXITCTL_MASK)
30759 #define MIPI_DSI_PHYTIMING_M_TLPXCTL_MASK        0xFF00u
30760 #define MIPI_DSI_PHYTIMING_M_TLPXCTL_SHIFT       8
30761 #define MIPI_DSI_PHYTIMING_M_TLPXCTL(x)          (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING_M_TLPXCTL_SHIFT))&MIPI_DSI_PHYTIMING_M_TLPXCTL_MASK)
30762 /* PHYTIMING1 Bit Fields */
30763 #define MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK  0xFFu
30764 #define MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT 0
30765 #define MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL(x)    (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK)
30766 #define MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK   0xFF00u
30767 #define MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT  8
30768 #define MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK)
30769 #define MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK   0xFF0000u
30770 #define MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT  16
30771 #define MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK)
30772 #define MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK   0xFF000000u
30773 #define MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT  24
30774 #define MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK)
30775 /* PHYTIMING2 Bit Fields */
30776 #define MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK   0xFFu
30777 #define MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT  0
30778 #define MIPI_DSI_PHYTIMING2_M_THSTRAILCTL(x)     (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT))&MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK)
30779 #define MIPI_DSI_PHYTIMING2_M_THSZEROCTL_MASK    0xFF00u
30780 #define MIPI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT   8
30781 #define MIPI_DSI_PHYTIMING2_M_THSZEROCTL(x)      (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT))&MIPI_DSI_PHYTIMING2_M_THSZEROCTL_MASK)
30782 #define MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK    0xFF0000u
30783 #define MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT   16
30784 #define MIPI_DSI_PHYTIMING2_M_THSPRPRCTL(x)      (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT))&MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK)
30785 
30786 /*!
30787  * @}
30788  */ /* end of group MIPI_DSI_Register_Masks */
30789 
30790 /* MIPI_DSI - Peripheral instance base addresses */
30791 /** Peripheral MIPI_DSI base address */
30792 #define MIPI_DSI_BASE                            (0x30760000u)
30793 /** Peripheral MIPI_DSI base pointer */
30794 #define MIPI_DSI                                 ((MIPI_DSI_Type *)MIPI_DSI_BASE)
30795 #define MIPI_DSI_BASE_PTR                        (MIPI_DSI)
30796 /** Array initializer of MIPI_DSI peripheral base addresses */
30797 #define MIPI_DSI_BASE_ADDRS                      { MIPI_DSI_BASE }
30798 /** Array initializer of MIPI_DSI peripheral base pointers */
30799 #define MIPI_DSI_BASE_PTRS                       { MIPI_DSI }
30800 /** Interrupt vectors for the MIPI_DSI peripheral type */
30801 #define MIPI_DSI_IRQS                            { MIPI_DSI_IRQn }
30802 /* ----------------------------------------------------------------------------
30803    -- MIPI_DSI - Register accessor macros
30804    ---------------------------------------------------------------------------- */
30805 
30806 /*!
30807  * @addtogroup MIPI_DSI_Register_Accessor_Macros MIPI_DSI - Register accessor macros
30808  * @{
30809  */
30810 
30811 
30812 /* MIPI_DSI - Register instance definitions */
30813 /* MIPI_DSI */
30814 #define MIPI_DSI_VERSION                         MIPI_DSI_VERSION_REG(MIPI_DSI_BASE_PTR)
30815 #define MIPI_DSI_STATUS                          MIPI_DSI_STATUS_REG(MIPI_DSI_BASE_PTR)
30816 #define MIPI_DSI_RGB_STATUS                      MIPI_DSI_RGB_STATUS_REG(MIPI_DSI_BASE_PTR)
30817 #define MIPI_DSI_SWRST                           MIPI_DSI_SWRST_REG(MIPI_DSI_BASE_PTR)
30818 #define MIPI_DSI_CLKCTRL                         MIPI_DSI_CLKCTRL_REG(MIPI_DSI_BASE_PTR)
30819 #define MIPI_DSI_TIMEOUT                         MIPI_DSI_TIMEOUT_REG(MIPI_DSI_BASE_PTR)
30820 #define MIPI_DSI_CONFIG                          MIPI_DSI_CONFIG_REG(MIPI_DSI_BASE_PTR)
30821 #define MIPI_DSI_ESCMODE                         MIPI_DSI_ESCMODE_REG(MIPI_DSI_BASE_PTR)
30822 #define MIPI_DSI_MDRESOL                         MIPI_DSI_MDRESOL_REG(MIPI_DSI_BASE_PTR)
30823 #define MIPI_DSI_MVPORCH                         MIPI_DSI_MVPORCH_REG(MIPI_DSI_BASE_PTR)
30824 #define MIPI_DSI_MHPORCH                         MIPI_DSI_MHPORCH_REG(MIPI_DSI_BASE_PTR)
30825 #define MIPI_DSI_MSYNC                           MIPI_DSI_MSYNC_REG(MIPI_DSI_BASE_PTR)
30826 #define MIPI_DSI_SDRESOL                         MIPI_DSI_SDRESOL_REG(MIPI_DSI_BASE_PTR)
30827 #define MIPI_DSI_INTSRC                          MIPI_DSI_INTSRC_REG(MIPI_DSI_BASE_PTR)
30828 #define MIPI_DSI_INTMSK                          MIPI_DSI_INTMSK_REG(MIPI_DSI_BASE_PTR)
30829 #define MIPI_DSI_PKTHDR                          MIPI_DSI_PKTHDR_REG(MIPI_DSI_BASE_PTR)
30830 #define MIPI_DSI_PAYLOAD                         MIPI_DSI_PAYLOAD_REG(MIPI_DSI_BASE_PTR)
30831 #define MIPI_DSI_RXFIFO                          MIPI_DSI_RXFIFO_REG(MIPI_DSI_BASE_PTR)
30832 #define MIPI_DSI_FIFOTHLD                        MIPI_DSI_FIFOTHLD_REG(MIPI_DSI_BASE_PTR)
30833 #define MIPI_DSI_FIFOCTRL                        MIPI_DSI_FIFOCTRL_REG(MIPI_DSI_BASE_PTR)
30834 #define MIPI_DSI_MEMACCHR                        MIPI_DSI_MEMACCHR_REG(MIPI_DSI_BASE_PTR)
30835 #define MIPI_DSI_MULTI_PKT                       MIPI_DSI_MULTI_PKT_REG(MIPI_DSI_BASE_PTR)
30836 #define MIPI_DSI_PLLCTRL_1G                      MIPI_DSI_PLLCTRL_1G_REG(MIPI_DSI_BASE_PTR)
30837 #define MIPI_DSI_PLLCTRL                         MIPI_DSI_PLLCTRL_REG(MIPI_DSI_BASE_PTR)
30838 #define MIPI_DSI_PLLCTRL1                        MIPI_DSI_PLLCTRL1_REG(MIPI_DSI_BASE_PTR)
30839 #define MIPI_DSI_PLLCTRL2                        MIPI_DSI_PLLCTRL2_REG(MIPI_DSI_BASE_PTR)
30840 #define MIPI_DSI_PLLTMR                          MIPI_DSI_PLLTMR_REG(MIPI_DSI_BASE_PTR)
30841 #define MIPI_DSI_PHYCTRL_B1                      MIPI_DSI_PHYCTRL_B1_REG(MIPI_DSI_BASE_PTR)
30842 #define MIPI_DSI_PHYCTRL_B2                      MIPI_DSI_PHYCTRL_B2_REG(MIPI_DSI_BASE_PTR)
30843 #define MIPI_DSI_PHYCTRL_M1                      MIPI_DSI_PHYCTRL_M1_REG(MIPI_DSI_BASE_PTR)
30844 #define MIPI_DSI_PHYCTRL_M2                      MIPI_DSI_PHYCTRL_M2_REG(MIPI_DSI_BASE_PTR)
30845 #define MIPI_DSI_PHYTIMING                       MIPI_DSI_PHYTIMING_REG(MIPI_DSI_BASE_PTR)
30846 #define MIPI_DSI_PHYTIMING1                      MIPI_DSI_PHYTIMING1_REG(MIPI_DSI_BASE_PTR)
30847 #define MIPI_DSI_PHYTIMING2                      MIPI_DSI_PHYTIMING2_REG(MIPI_DSI_BASE_PTR)
30848 /*!
30849  * @}
30850  */ /* end of group MIPI_DSI_Register_Accessor_Macros */
30851 
30852 
30853 /*!
30854  * @}
30855  */ /* end of group MIPI_DSI_Peripheral */
30856 
30857 /* ----------------------------------------------------------------------------
30858    -- MU Peripheral Access Layer
30859    ---------------------------------------------------------------------------- */
30860 
30861 /*!
30862  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
30863  * @{
30864  */
30865 
30866 /** MU - Register Layout Typedef */
30867 typedef struct {
30868   __IO  uint32_t TR[4];                                  /**< Processor B Transmit Register 0, array offset: 0x0, array step: 0x4 */
30869   __I   uint32_t RR[4];                                  /**< Processor B Receive Register 0, array offset: 0x10, array step: 0x4 */
30870   __IO  uint32_t SR;                                     /**< Processor B Status Register, offset: 0x20 */
30871   __IO  uint32_t CR;                                     /**< Processor B Control Register, offset: 0x24 */
30872 } MU_Type, *MU_MemMapPtr;
30873 /* ----------------------------------------------------------------------------
30874    -- MU - Register accessor macros
30875    ---------------------------------------------------------------------------- */
30876 
30877 /*!
30878  * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros
30879  * @{
30880  */
30881 
30882 
30883 /* MU - Register accessors */
30884 #define MU_TR_REG(base,index)                    ((base)->TR[index])
30885 #define MU_TR_COUNT                              4
30886 #define MU_RR_REG(base,index)                    ((base)->RR[index])
30887 #define MU_RR_COUNT                              4
30888 #define MU_SR_REG(base)                          ((base)->SR)
30889 #define MU_CR_REG(base)                          ((base)->CR)
30890 
30891 /*!
30892  * @}
30893  */ /* end of group MU_Register_Accessor_Macros */
30894 /* ----------------------------------------------------------------------------
30895    -- MU Register Masks
30896    ---------------------------------------------------------------------------- */
30897 
30898 /*!
30899  * @addtogroup MU_Register_Masks MU Register Masks
30900  * @{
30901  */
30902 
30903 /* TR Bit Fields */
30904 #define MU_TR_TR0_MASK                           0xFFFFFFFFu
30905 #define MU_TR_TR0_SHIFT                          0
30906 #define MU_TR_TR0(x)                             (((uint32_t)(((uint32_t)(x))<<MU_TR_TR0_SHIFT))&MU_TR_TR0_MASK)
30907 /* RR Bit Fields */
30908 #define MU_RR_RR0_MASK                           0xFFFFFFFFu
30909 #define MU_RR_RR0_SHIFT                          0
30910 #define MU_RR_RR0(x)                             (((uint32_t)(((uint32_t)(x))<<MU_RR_RR0_SHIFT))&MU_RR_RR0_MASK)
30911 /* SR Bit Fields */
30912 #define MU_SR_Fn_MASK                            0x7u
30913 #define MU_SR_Fn_SHIFT                           0
30914 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x))<<MU_SR_Fn_SHIFT))&MU_SR_Fn_MASK)
30915 #define MU_SR_EP_MASK                            0x10u
30916 #define MU_SR_EP_SHIFT                           4
30917 #define MU_SR_PM_MASK                            0x60u
30918 #define MU_SR_PM_SHIFT                           5
30919 #define MU_SR_PM(x)                              (((uint32_t)(((uint32_t)(x))<<MU_SR_PM_SHIFT))&MU_SR_PM_MASK)
30920 #define MU_SR_RS_MASK                            0x80u
30921 #define MU_SR_RS_SHIFT                           7
30922 #define MU_SR_FUP_MASK                           0x100u
30923 #define MU_SR_FUP_SHIFT                          8
30924 #define MU_SR_TEn_MASK                           0xF00000u
30925 #define MU_SR_TEn_SHIFT                          20
30926 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x))<<MU_SR_TEn_SHIFT))&MU_SR_TEn_MASK)
30927 #define MU_SR_RFn_MASK                           0xF000000u
30928 #define MU_SR_RFn_SHIFT                          24
30929 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x))<<MU_SR_RFn_SHIFT))&MU_SR_RFn_MASK)
30930 #define MU_SR_GIPn_MASK                          0xF0000000u
30931 #define MU_SR_GIPn_SHIFT                         28
30932 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_SR_GIPn_SHIFT))&MU_SR_GIPn_MASK)
30933 /* CR Bit Fields */
30934 #define MU_CR_Fn_MASK                            0x7u
30935 #define MU_CR_Fn_SHIFT                           0
30936 #define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x))<<MU_CR_Fn_SHIFT))&MU_CR_Fn_MASK)
30937 #define MU_CR_HRM_MASK                           0x10u
30938 #define MU_CR_HRM_SHIFT                          4
30939 #define MU_CR_GIRn_MASK                          0xF0000u
30940 #define MU_CR_GIRn_SHIFT                         16
30941 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_GIRn_SHIFT))&MU_CR_GIRn_MASK)
30942 #define MU_CR_TIEn_MASK                          0xF00000u
30943 #define MU_CR_TIEn_SHIFT                         20
30944 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_TIEn_SHIFT))&MU_CR_TIEn_MASK)
30945 #define MU_CR_RIEn_MASK                          0xF000000u
30946 #define MU_CR_RIEn_SHIFT                         24
30947 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_RIEn_SHIFT))&MU_CR_RIEn_MASK)
30948 #define MU_CR_GIEn_MASK                          0xF0000000u
30949 #define MU_CR_GIEn_SHIFT                         28
30950 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_GIEn_SHIFT))&MU_CR_GIEn_MASK)
30951 
30952 /*!
30953  * @}
30954  */ /* end of group MU_Register_Masks */
30955 
30956 /* MU - Peripheral instance base addresses */
30957 /** Peripheral MUB base address */
30958 #define MUB_BASE                                 (0x30AB0000u)
30959 /** Peripheral MUB  base pointer */
30960 #define MUB                                      ((MU_Type *)MUB_BASE)
30961 #define MUB_BASE_PTR                             (MUB)
30962 /** Array initializer of MU peripheral base addresses */
30963 #define MU_BASE_ADDRS                            { MUB_BASE }
30964 /** Array initializer of MU peripheral base pointers */
30965 #define MU_BASE_PTRS                             { MUB }
30966 /** Interrupt vectors for the MU peripheral type */
30967 #define MU_IRQS                                  { MU_M4_IRQn }
30968 /* ----------------------------------------------------------------------------
30969    -- MU - Register accessor macros
30970    ---------------------------------------------------------------------------- */
30971 
30972 /*!
30973  * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros
30974  * @{
30975  */
30976 
30977 
30978 /* MU - Register instance definitions */
30979 /* MUB */
30980 #define MUB_TR0                                  MU_TR_REG(MUB_BASE_PTR,0)
30981 #define MUB_TR1                                  MU_TR_REG(MUB_BASE_PTR,1)
30982 #define MUB_TR2                                  MU_TR_REG(MUB_BASE_PTR,2)
30983 #define MUB_TR3                                  MU_TR_REG(MUB_BASE_PTR,3)
30984 #define MUB_RR0                                  MU_RR_REG(MUB_BASE_PTR,0)
30985 #define MUB_RR1                                  MU_RR_REG(MUB_BASE_PTR,1)
30986 #define MUB_RR2                                  MU_RR_REG(MUB_BASE_PTR,2)
30987 #define MUB_RR3                                  MU_RR_REG(MUB_BASE_PTR,3)
30988 #define MUB_SR                                   MU_SR_REG(MUB_BASE_PTR)
30989 #define MUB_CR                                   MU_CR_REG(MUB_BASE_PTR)
30990 /* MU - Register array accessors */
30991 #define MUB_TR(index)                            MU_TR_REG(MUB_BASE_PTR,index)
30992 #define MUB_RR(index)                            MU_RR_REG(MUB_BASE_PTR,index)
30993 /*!
30994  * @}
30995  */ /* end of group MU_Register_Accessor_Macros */
30996 
30997 
30998 /*!
30999  * @}
31000  */ /* end of group MU_Peripheral */
31001 
31002 /* ----------------------------------------------------------------------------
31003    -- OCOTP Peripheral Access Layer
31004    ---------------------------------------------------------------------------- */
31005 
31006 /*!
31007  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
31008  * @{
31009  */
31010 
31011 /** OCOTP - Register Layout Typedef */
31012 typedef struct {
31013   __IO  uint32_t CTRL;                                   /**< OTP Controller Control Register, offset: 0x0 */
31014   __IO  uint32_t CTRL_SET;                               /**< OTP Controller Control Register, offset: 0x4 */
31015   __IO  uint32_t CTRL_CLR;                               /**< OTP Controller Control Register, offset: 0x8 */
31016   __IO  uint32_t CTRL_TOG;                               /**< OTP Controller Control Register, offset: 0xC */
31017   __IO  uint32_t TIMING;                                 /**< OTP Controller Timing Register, offset: 0x10 */
31018   uint8_t RESERVED_0[12];
31019   __IO  uint32_t DATA0;                                  /**< OTP Controller Write Data Register, offset: 0x20 */
31020   uint8_t RESERVED_1[12];
31021   __IO  uint32_t DATA1;                                  /**< OTP Controller Write Data Register, offset: 0x30 */
31022   uint8_t RESERVED_2[12];
31023   __IO  uint32_t DATA2;                                  /**< OTP Controller Write Data Register, offset: 0x40 */
31024   uint8_t RESERVED_3[12];
31025   __IO  uint32_t DATA3;                                  /**< OTP Controller Write Data Register, offset: 0x50 */
31026   uint8_t RESERVED_4[12];
31027   __IO  uint32_t READ_CTRL;                              /**< OTP Controller Write Data Register, offset: 0x60 */
31028   uint8_t RESERVED_5[12];
31029   __IO  uint32_t READ_FUSE_DATA0;                        /**< OTP Controller Read Data Register, offset: 0x70 */
31030   uint8_t RESERVED_6[12];
31031   __IO  uint32_t READ_FUSE_DATA1;                        /**< OTP Controller Read Data Register, offset: 0x80 */
31032   uint8_t RESERVED_7[12];
31033   __IO  uint32_t READ_FUSE_DATA2;                        /**< OTP Controller Read Data Register, offset: 0x90 */
31034   uint8_t RESERVED_8[12];
31035   __IO  uint32_t READ_FUSE_DATA3;                        /**< OTP Controller Read Data Register, offset: 0xA0 */
31036   uint8_t RESERVED_9[12];
31037   __IO  uint32_t SW_STICKY;                              /**< Sticky bit Register, offset: 0xB0 */
31038   uint8_t RESERVED_10[12];
31039   __IO  uint32_t SCS;                                    /**< Software Controllable Signals Register, offset: 0xC0 */
31040   __IO  uint32_t SCS_SET;                                /**< Software Controllable Signals Register, offset: 0xC4 */
31041   __IO  uint32_t SCS_CLR;                                /**< Software Controllable Signals Register, offset: 0xC8 */
31042   __IO  uint32_t SCS_TOG;                                /**< Software Controllable Signals Register, offset: 0xCC */
31043   __IO  uint32_t CRC_ADDR;                               /**< OTP Controller CRC test address, offset: 0xD0 */
31044   uint8_t RESERVED_11[12];
31045   __IO  uint32_t CRC_VALUE;                              /**< OTP Controller CRC Value Register, offset: 0xE0 */
31046   uint8_t RESERVED_12[12];
31047   __IO  uint32_t VERSION;                                /**< OTP Controller Version Register, offset: 0xF0 */
31048   uint8_t RESERVED_13[780];
31049   __IO  uint32_t LOCK;                                   /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
31050   uint8_t RESERVED_14[12];
31051   __IO  uint32_t TESTER0;                                /**< Value of OTP Bank0 Word1 (Tester Information), offset: 0x410 */
31052   uint8_t RESERVED_15[12];
31053   __IO  uint32_t TESTER1;                                /**< Value of OTP Bank0 Word2 (Tester Information), offset: 0x420 */
31054   uint8_t RESERVED_16[12];
31055   __IO  uint32_t TESTER2;                                /**< Value of OTP Bank0 Word3 (Tester Information), offset: 0x430 */
31056   uint8_t RESERVED_17[12];
31057   __IO  uint32_t TESTER3;                                /**< Value of OTP Bank1 Word0 (Tester Information), offset: 0x440 */
31058   uint8_t RESERVED_18[12];
31059   __IO  uint32_t TESTER4;                                /**< Value of OTP Bank1 Word1 (Tester Information), offset: 0x450 */
31060   uint8_t RESERVED_19[12];
31061   __IO  uint32_t TESTER5;                                /**< Value of OTP Bank1 Word2 (Tester Information), offset: 0x460 */
31062   uint8_t RESERVED_20[12];
31063   __IO  uint32_t BOOT_CFG0;                              /**< Value of OTP Bank1 Word3 (Boot Configuration Information), offset: 0x470 */
31064   uint8_t RESERVED_21[12];
31065   __IO  uint32_t BOOT_CFG1;                              /**< Value of OTP Bank2 Word0 (Boot Configuration Information), offset: 0x480 */
31066   uint8_t RESERVED_22[12];
31067   __IO  uint32_t BOOT_CFG2;                              /**< Value of OTP Bank2 Word1 (Boot Configuration Information), offset: 0x490 */
31068   uint8_t RESERVED_23[12];
31069   __IO  uint32_t BOOT_CFG3;                              /**< Value of OTP Bank2 Word2 (Boot Configuration Information), offset: 0x4A0 */
31070   uint8_t RESERVED_24[12];
31071   __IO  uint32_t BOOT_CFG4;                              /**< Value of OTP Bank2 Word3 (BOOT Configuration Information), offset: 0x4B0 */
31072   uint8_t RESERVED_25[12];
31073   __IO  uint32_t MEM_TRIM0;                              /**< Value of OTP Bank3 Word0 (Memory Related Information), offset: 0x4C0 */
31074   uint8_t RESERVED_26[12];
31075   __IO  uint32_t MEM_TRIM1;                              /**< Value of OTP Bank3 Word1 (Memory Related Information), offset: 0x4D0 */
31076   uint8_t RESERVED_27[12];
31077   __IO  uint32_t ANA0;                                   /**< Value of OTP Bank3 Word2 (Analog Information), offset: 0x4E0 */
31078   uint8_t RESERVED_28[12];
31079   __IO  uint32_t ANA1;                                   /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */
31080   uint8_t RESERVED_29[12];
31081   __IO  uint32_t OTPMK0;                                 /**< Shadow Register for OTP Bank4 Word0 (OTPMK Key), offset: 0x500 */
31082   uint8_t RESERVED_30[12];
31083   __IO  uint32_t OTPMK1;                                 /**< Shadow Register for OTP Bank4 Word1 (OTPMK Key), offset: 0x510 */
31084   uint8_t RESERVED_31[12];
31085   __IO  uint32_t OTPMK2;                                 /**< Shadow Register for OTP Bank4 Word2 (OTPMK Key), offset: 0x520 */
31086   uint8_t RESERVED_32[12];
31087   __IO  uint32_t OTPMK3;                                 /**< Shadow Register for OTP Bank4 Word3 (OTPMK Key), offset: 0x530 */
31088   uint8_t RESERVED_33[12];
31089   __IO  uint32_t OTPMK4;                                 /**< Shadow Register for OTP Bank5 Word0 (OTPMK Key), offset: 0x540 */
31090   uint8_t RESERVED_34[12];
31091   __IO  uint32_t OTPMK5;                                 /**< Shadow Register for OTP Bank5 Word1 (OTPMK Key), offset: 0x550 */
31092   uint8_t RESERVED_35[12];
31093   __IO  uint32_t OTPMK6;                                 /**< Shadow Register for OTP Bank5 Word2 (OTPMK Key), offset: 0x560 */
31094   uint8_t RESERVED_36[12];
31095   __IO  uint32_t OTPMK7;                                 /**< Shadow Register for OTP Bank5 Word3 (OTPMK Key), offset: 0x570 */
31096   uint8_t RESERVED_37[12];
31097   __IO  uint32_t SRK0;                                   /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */
31098   uint8_t RESERVED_38[12];
31099   __IO  uint32_t SRK1;                                   /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */
31100   uint8_t RESERVED_39[12];
31101   __IO  uint32_t SRK2;                                   /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */
31102   uint8_t RESERVED_40[12];
31103   __IO  uint32_t SRK3;                                   /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */
31104   uint8_t RESERVED_41[12];
31105   __IO  uint32_t SRK4;                                   /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */
31106   uint8_t RESERVED_42[12];
31107   __IO  uint32_t SRK5;                                   /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */
31108   uint8_t RESERVED_43[12];
31109   __IO  uint32_t SRK6;                                   /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */
31110   uint8_t RESERVED_44[12];
31111   __IO  uint32_t SRK7;                                   /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */
31112   uint8_t RESERVED_45[12];
31113   __IO  uint32_t SJC_RESP0;                              /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */
31114   uint8_t RESERVED_46[12];
31115   __IO  uint32_t SJC_RESP1;                              /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */
31116   uint8_t RESERVED_47[12];
31117   __IO  uint32_t USB_ID;                                 /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */
31118   uint8_t RESERVED_48[12];
31119   __IO  uint32_t FIELD_RETURN;                           /**< Value of OTP Bank8 Word3 (Field Return), offset: 0x630 */
31120   uint8_t RESERVED_49[12];
31121   __IO  uint32_t MAC_ADDR0;                              /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */
31122   uint8_t RESERVED_50[12];
31123   __IO  uint32_t MAC_ADDR1;                              /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */
31124   uint8_t RESERVED_51[12];
31125   __IO  uint32_t MAC_ADDR2;                              /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */
31126   uint8_t RESERVED_52[12];
31127   __IO  uint32_t SRK_REVOKE;                             /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */
31128   uint8_t RESERVED_53[12];
31129   __IO  uint32_t MAU_KEY0;                               /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */
31130   uint8_t RESERVED_54[12];
31131   __IO  uint32_t MAU_KEY1;                               /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */
31132   uint8_t RESERVED_55[12];
31133   __IO  uint32_t MAU_KEY2;                               /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */
31134   uint8_t RESERVED_56[12];
31135   __IO  uint32_t MAU_KEY3;                               /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */
31136   uint8_t RESERVED_57[12];
31137   __IO  uint32_t MAU_KEY4;                               /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */
31138   uint8_t RESERVED_58[12];
31139   __IO  uint32_t MAU_KEY5;                               /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */
31140   uint8_t RESERVED_59[12];
31141   __IO  uint32_t MAU_KEY6;                               /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */
31142   uint8_t RESERVED_60[12];
31143   __IO  uint32_t MAU_KEY7;                               /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */
31144   uint8_t RESERVED_61[140];
31145   __IO  uint32_t GP10;                                   /**< Value of OTP Bank14 Word0, offset: 0x780 */
31146   uint8_t RESERVED_62[12];
31147   __IO  uint32_t GP11;                                   /**< Value of OTP Bank14 Word1, offset: 0x790 */
31148   uint8_t RESERVED_63[12];
31149   __IO  uint32_t GP20;                                   /**< Value of OTP Bank14 Word2, offset: 0x7A0 */
31150   uint8_t RESERVED_64[12];
31151   __IO  uint32_t GP21;                                   /**< Value of OTP Bank14 Word3, offset: 0x7B0 */
31152   uint8_t RESERVED_65[12];
31153   __IO  uint32_t CRC_GP10;                               /**< Value of OTP Bank15 Word0 (CRC Key), offset: 0x7C0 */
31154   uint8_t RESERVED_66[12];
31155   __IO  uint32_t CRC_GP11;                               /**< Value of OTP Bank15 Word1 (CRC Key), offset: 0x7D0 */
31156   uint8_t RESERVED_67[12];
31157   __IO  uint32_t CRC_GP20;                               /**< Value of OTP Bank15 Word2 (CRC Key), offset: 0x7E0 */
31158   uint8_t RESERVED_68[12];
31159   __IO  uint32_t CRC_GP21;                               /**< Value of OTP Bank15 Word3 (CRC Key), offset: 0x7F0 */
31160 } OCOTP_Type, *OCOTP_MemMapPtr;
31161 /* ----------------------------------------------------------------------------
31162    -- OCOTP - Register accessor macros
31163    ---------------------------------------------------------------------------- */
31164 
31165 /*!
31166  * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros
31167  * @{
31168  */
31169 
31170 
31171 /* OCOTP - Register accessors */
31172 #define OCOTP_CTRL_REG(base)                     ((base)->CTRL)
31173 #define OCOTP_CTRL_SET_REG(base)                 ((base)->CTRL_SET)
31174 #define OCOTP_CTRL_CLR_REG(base)                 ((base)->CTRL_CLR)
31175 #define OCOTP_CTRL_TOG_REG(base)                 ((base)->CTRL_TOG)
31176 #define OCOTP_TIMING_REG(base)                   ((base)->TIMING)
31177 #define OCOTP_DATA0_REG(base)                    ((base)->DATA0)
31178 #define OCOTP_DATA1_REG(base)                    ((base)->DATA1)
31179 #define OCOTP_DATA2_REG(base)                    ((base)->DATA2)
31180 #define OCOTP_DATA3_REG(base)                    ((base)->DATA3)
31181 #define OCOTP_READ_CTRL_REG(base)                ((base)->READ_CTRL)
31182 #define OCOTP_READ_FUSE_DATA0_REG(base)          ((base)->READ_FUSE_DATA0)
31183 #define OCOTP_READ_FUSE_DATA1_REG(base)          ((base)->READ_FUSE_DATA1)
31184 #define OCOTP_READ_FUSE_DATA2_REG(base)          ((base)->READ_FUSE_DATA2)
31185 #define OCOTP_READ_FUSE_DATA3_REG(base)          ((base)->READ_FUSE_DATA3)
31186 #define OCOTP_SW_STICKY_REG(base)                ((base)->SW_STICKY)
31187 #define OCOTP_SCS_REG(base)                      ((base)->SCS)
31188 #define OCOTP_SCS_SET_REG(base)                  ((base)->SCS_SET)
31189 #define OCOTP_SCS_CLR_REG(base)                  ((base)->SCS_CLR)
31190 #define OCOTP_SCS_TOG_REG(base)                  ((base)->SCS_TOG)
31191 #define OCOTP_CRC_ADDR_REG(base)                 ((base)->CRC_ADDR)
31192 #define OCOTP_CRC_VALUE_REG(base)                ((base)->CRC_VALUE)
31193 #define OCOTP_VERSION_REG(base)                  ((base)->VERSION)
31194 #define OCOTP_LOCK_REG(base)                     ((base)->LOCK)
31195 #define OCOTP_TESTER0_REG(base)                  ((base)->TESTER0)
31196 #define OCOTP_TESTER1_REG(base)                  ((base)->TESTER1)
31197 #define OCOTP_TESTER2_REG(base)                  ((base)->TESTER2)
31198 #define OCOTP_TESTER3_REG(base)                  ((base)->TESTER3)
31199 #define OCOTP_TESTER4_REG(base)                  ((base)->TESTER4)
31200 #define OCOTP_TESTER5_REG(base)                  ((base)->TESTER5)
31201 #define OCOTP_BOOT_CFG0_REG(base)                ((base)->BOOT_CFG0)
31202 #define OCOTP_BOOT_CFG1_REG(base)                ((base)->BOOT_CFG1)
31203 #define OCOTP_BOOT_CFG2_REG(base)                ((base)->BOOT_CFG2)
31204 #define OCOTP_BOOT_CFG3_REG(base)                ((base)->BOOT_CFG3)
31205 #define OCOTP_BOOT_CFG4_REG(base)                ((base)->BOOT_CFG4)
31206 #define OCOTP_MEM_TRIM0_REG(base)                ((base)->MEM_TRIM0)
31207 #define OCOTP_MEM_TRIM1_REG(base)                ((base)->MEM_TRIM1)
31208 #define OCOTP_ANA0_REG(base)                     ((base)->ANA0)
31209 #define OCOTP_ANA1_REG(base)                     ((base)->ANA1)
31210 #define OCOTP_OTPMK0_REG(base)                   ((base)->OTPMK0)
31211 #define OCOTP_OTPMK1_REG(base)                   ((base)->OTPMK1)
31212 #define OCOTP_OTPMK2_REG(base)                   ((base)->OTPMK2)
31213 #define OCOTP_OTPMK3_REG(base)                   ((base)->OTPMK3)
31214 #define OCOTP_OTPMK4_REG(base)                   ((base)->OTPMK4)
31215 #define OCOTP_OTPMK5_REG(base)                   ((base)->OTPMK5)
31216 #define OCOTP_OTPMK6_REG(base)                   ((base)->OTPMK6)
31217 #define OCOTP_OTPMK7_REG(base)                   ((base)->OTPMK7)
31218 #define OCOTP_SRK0_REG(base)                     ((base)->SRK0)
31219 #define OCOTP_SRK1_REG(base)                     ((base)->SRK1)
31220 #define OCOTP_SRK2_REG(base)                     ((base)->SRK2)
31221 #define OCOTP_SRK3_REG(base)                     ((base)->SRK3)
31222 #define OCOTP_SRK4_REG(base)                     ((base)->SRK4)
31223 #define OCOTP_SRK5_REG(base)                     ((base)->SRK5)
31224 #define OCOTP_SRK6_REG(base)                     ((base)->SRK6)
31225 #define OCOTP_SRK7_REG(base)                     ((base)->SRK7)
31226 #define OCOTP_SJC_RESP0_REG(base)                ((base)->SJC_RESP0)
31227 #define OCOTP_SJC_RESP1_REG(base)                ((base)->SJC_RESP1)
31228 #define OCOTP_USB_ID_REG(base)                   ((base)->USB_ID)
31229 #define OCOTP_FIELD_RETURN_REG(base)             ((base)->FIELD_RETURN)
31230 #define OCOTP_MAC_ADDR0_REG(base)                ((base)->MAC_ADDR0)
31231 #define OCOTP_MAC_ADDR1_REG(base)                ((base)->MAC_ADDR1)
31232 #define OCOTP_MAC_ADDR2_REG(base)                ((base)->MAC_ADDR2)
31233 #define OCOTP_SRK_REVOKE_REG(base)               ((base)->SRK_REVOKE)
31234 #define OCOTP_MAU_KEY0_REG(base)                 ((base)->MAU_KEY0)
31235 #define OCOTP_MAU_KEY1_REG(base)                 ((base)->MAU_KEY1)
31236 #define OCOTP_MAU_KEY2_REG(base)                 ((base)->MAU_KEY2)
31237 #define OCOTP_MAU_KEY3_REG(base)                 ((base)->MAU_KEY3)
31238 #define OCOTP_MAU_KEY4_REG(base)                 ((base)->MAU_KEY4)
31239 #define OCOTP_MAU_KEY5_REG(base)                 ((base)->MAU_KEY5)
31240 #define OCOTP_MAU_KEY6_REG(base)                 ((base)->MAU_KEY6)
31241 #define OCOTP_MAU_KEY7_REG(base)                 ((base)->MAU_KEY7)
31242 #define OCOTP_GP10_REG(base)                     ((base)->GP10)
31243 #define OCOTP_GP11_REG(base)                     ((base)->GP11)
31244 #define OCOTP_GP20_REG(base)                     ((base)->GP20)
31245 #define OCOTP_GP21_REG(base)                     ((base)->GP21)
31246 #define OCOTP_CRC_GP10_REG(base)                 ((base)->CRC_GP10)
31247 #define OCOTP_CRC_GP11_REG(base)                 ((base)->CRC_GP11)
31248 #define OCOTP_CRC_GP20_REG(base)                 ((base)->CRC_GP20)
31249 #define OCOTP_CRC_GP21_REG(base)                 ((base)->CRC_GP21)
31250 
31251 /*!
31252  * @}
31253  */ /* end of group OCOTP_Register_Accessor_Macros */
31254 /* ----------------------------------------------------------------------------
31255    -- OCOTP Register Masks
31256    ---------------------------------------------------------------------------- */
31257 
31258 /*!
31259  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
31260  * @{
31261  */
31262 
31263 /* CTRL Bit Fields */
31264 #define OCOTP_CTRL_ADDR_MASK                     0xFu
31265 #define OCOTP_CTRL_ADDR_SHIFT                    0
31266 #define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_ADDR_SHIFT))&OCOTP_CTRL_ADDR_MASK)
31267 #define OCOTP_CTRL_RSVD0_MASK                    0xF0u
31268 #define OCOTP_CTRL_RSVD0_SHIFT                   4
31269 #define OCOTP_CTRL_RSVD0(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_RSVD0_SHIFT))&OCOTP_CTRL_RSVD0_MASK)
31270 #define OCOTP_CTRL_BUSY_MASK                     0x100u
31271 #define OCOTP_CTRL_BUSY_SHIFT                    8
31272 #define OCOTP_CTRL_ERROR_MASK                    0x200u
31273 #define OCOTP_CTRL_ERROR_SHIFT                   9
31274 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK           0x400u
31275 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          10
31276 #define OCOTP_CTRL_CRC_TEST_MASK                 0x800u
31277 #define OCOTP_CTRL_CRC_TEST_SHIFT                11
31278 #define OCOTP_CTRL_CRC_FAIL_MASK                 0x1000u
31279 #define OCOTP_CTRL_CRC_FAIL_SHIFT                12
31280 #define OCOTP_CTRL_RSVD1_MASK                    0xE000u
31281 #define OCOTP_CTRL_RSVD1_SHIFT                   13
31282 #define OCOTP_CTRL_RSVD1(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_RSVD1_SHIFT))&OCOTP_CTRL_RSVD1_MASK)
31283 #define OCOTP_CTRL_WR_UNLOCK_MASK                0xFFFF0000u
31284 #define OCOTP_CTRL_WR_UNLOCK_SHIFT               16
31285 #define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_WR_UNLOCK_SHIFT))&OCOTP_CTRL_WR_UNLOCK_MASK)
31286 /* CTRL_SET Bit Fields */
31287 #define OCOTP_CTRL_SET_ADDR_MASK                 0xFu
31288 #define OCOTP_CTRL_SET_ADDR_SHIFT                0
31289 #define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_ADDR_SHIFT))&OCOTP_CTRL_SET_ADDR_MASK)
31290 #define OCOTP_CTRL_SET_RSVD0_MASK                0xF0u
31291 #define OCOTP_CTRL_SET_RSVD0_SHIFT               4
31292 #define OCOTP_CTRL_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_RSVD0_SHIFT))&OCOTP_CTRL_SET_RSVD0_MASK)
31293 #define OCOTP_CTRL_SET_BUSY_MASK                 0x100u
31294 #define OCOTP_CTRL_SET_BUSY_SHIFT                8
31295 #define OCOTP_CTRL_SET_ERROR_MASK                0x200u
31296 #define OCOTP_CTRL_SET_ERROR_SHIFT               9
31297 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       0x400u
31298 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      10
31299 #define OCOTP_CTRL_SET_CRC_TEST_MASK             0x800u
31300 #define OCOTP_CTRL_SET_CRC_TEST_SHIFT            11
31301 #define OCOTP_CTRL_SET_CRC_FAIL_MASK             0x1000u
31302 #define OCOTP_CTRL_SET_CRC_FAIL_SHIFT            12
31303 #define OCOTP_CTRL_SET_RSVD1_MASK                0xE000u
31304 #define OCOTP_CTRL_SET_RSVD1_SHIFT               13
31305 #define OCOTP_CTRL_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_RSVD1_SHIFT))&OCOTP_CTRL_SET_RSVD1_MASK)
31306 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK            0xFFFF0000u
31307 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           16
31308 #define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_WR_UNLOCK_SHIFT))&OCOTP_CTRL_SET_WR_UNLOCK_MASK)
31309 /* CTRL_CLR Bit Fields */
31310 #define OCOTP_CTRL_CLR_ADDR_MASK                 0xFu
31311 #define OCOTP_CTRL_CLR_ADDR_SHIFT                0
31312 #define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_ADDR_SHIFT))&OCOTP_CTRL_CLR_ADDR_MASK)
31313 #define OCOTP_CTRL_CLR_RSVD0_MASK                0xF0u
31314 #define OCOTP_CTRL_CLR_RSVD0_SHIFT               4
31315 #define OCOTP_CTRL_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_RSVD0_SHIFT))&OCOTP_CTRL_CLR_RSVD0_MASK)
31316 #define OCOTP_CTRL_CLR_BUSY_MASK                 0x100u
31317 #define OCOTP_CTRL_CLR_BUSY_SHIFT                8
31318 #define OCOTP_CTRL_CLR_ERROR_MASK                0x200u
31319 #define OCOTP_CTRL_CLR_ERROR_SHIFT               9
31320 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       0x400u
31321 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      10
31322 #define OCOTP_CTRL_CLR_CRC_TEST_MASK             0x800u
31323 #define OCOTP_CTRL_CLR_CRC_TEST_SHIFT            11
31324 #define OCOTP_CTRL_CLR_CRC_FAIL_MASK             0x1000u
31325 #define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT            12
31326 #define OCOTP_CTRL_CLR_RSVD1_MASK                0xE000u
31327 #define OCOTP_CTRL_CLR_RSVD1_SHIFT               13
31328 #define OCOTP_CTRL_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_RSVD1_SHIFT))&OCOTP_CTRL_CLR_RSVD1_MASK)
31329 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            0xFFFF0000u
31330 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           16
31331 #define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT))&OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
31332 /* CTRL_TOG Bit Fields */
31333 #define OCOTP_CTRL_TOG_ADDR_MASK                 0xFu
31334 #define OCOTP_CTRL_TOG_ADDR_SHIFT                0
31335 #define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_ADDR_SHIFT))&OCOTP_CTRL_TOG_ADDR_MASK)
31336 #define OCOTP_CTRL_TOG_RSVD0_MASK                0xF0u
31337 #define OCOTP_CTRL_TOG_RSVD0_SHIFT               4
31338 #define OCOTP_CTRL_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_RSVD0_SHIFT))&OCOTP_CTRL_TOG_RSVD0_MASK)
31339 #define OCOTP_CTRL_TOG_BUSY_MASK                 0x100u
31340 #define OCOTP_CTRL_TOG_BUSY_SHIFT                8
31341 #define OCOTP_CTRL_TOG_ERROR_MASK                0x200u
31342 #define OCOTP_CTRL_TOG_ERROR_SHIFT               9
31343 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       0x400u
31344 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      10
31345 #define OCOTP_CTRL_TOG_CRC_TEST_MASK             0x800u
31346 #define OCOTP_CTRL_TOG_CRC_TEST_SHIFT            11
31347 #define OCOTP_CTRL_TOG_CRC_FAIL_MASK             0x1000u
31348 #define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT            12
31349 #define OCOTP_CTRL_TOG_RSVD1_MASK                0xE000u
31350 #define OCOTP_CTRL_TOG_RSVD1_SHIFT               13
31351 #define OCOTP_CTRL_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_RSVD1_SHIFT))&OCOTP_CTRL_TOG_RSVD1_MASK)
31352 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            0xFFFF0000u
31353 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           16
31354 #define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT))&OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
31355 /* TIMING Bit Fields */
31356 #define OCOTP_TIMING_PROG_MASK                   0xFFFu
31357 #define OCOTP_TIMING_PROG_SHIFT                  0
31358 #define OCOTP_TIMING_PROG(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_PROG_SHIFT))&OCOTP_TIMING_PROG_MASK)
31359 #define OCOTP_TIMING_FSOURCE_MASK                0xFF000u
31360 #define OCOTP_TIMING_FSOURCE_SHIFT               12
31361 #define OCOTP_TIMING_FSOURCE(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_FSOURCE_SHIFT))&OCOTP_TIMING_FSOURCE_MASK)
31362 #define OCOTP_TIMING_RSRVD0_MASK                 0xFFF00000u
31363 #define OCOTP_TIMING_RSRVD0_SHIFT                20
31364 #define OCOTP_TIMING_RSRVD0(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_RSRVD0_SHIFT))&OCOTP_TIMING_RSRVD0_MASK)
31365 /* DATA0 Bit Fields */
31366 #define OCOTP_DATA0_DATA0_MASK                   0xFFFFFFFFu
31367 #define OCOTP_DATA0_DATA0_SHIFT                  0
31368 #define OCOTP_DATA0_DATA0(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA0_DATA0_SHIFT))&OCOTP_DATA0_DATA0_MASK)
31369 /* DATA1 Bit Fields */
31370 #define OCOTP_DATA1_DATA1_MASK                   0xFFFFFFFFu
31371 #define OCOTP_DATA1_DATA1_SHIFT                  0
31372 #define OCOTP_DATA1_DATA1(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA1_DATA1_SHIFT))&OCOTP_DATA1_DATA1_MASK)
31373 /* DATA2 Bit Fields */
31374 #define OCOTP_DATA2_DATA2_MASK                   0xFFFFFFFFu
31375 #define OCOTP_DATA2_DATA2_SHIFT                  0
31376 #define OCOTP_DATA2_DATA2(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA2_DATA2_SHIFT))&OCOTP_DATA2_DATA2_MASK)
31377 /* DATA3 Bit Fields */
31378 #define OCOTP_DATA3_DATA3_MASK                   0xFFFFFFFFu
31379 #define OCOTP_DATA3_DATA3_SHIFT                  0
31380 #define OCOTP_DATA3_DATA3(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA3_DATA3_SHIFT))&OCOTP_DATA3_DATA3_MASK)
31381 /* READ_CTRL Bit Fields */
31382 #define OCOTP_READ_CTRL_READ_FUSE_MASK           0x1u
31383 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT          0
31384 #define OCOTP_READ_CTRL_RSVD0_MASK               0xFFFFFFFEu
31385 #define OCOTP_READ_CTRL_RSVD0_SHIFT              1
31386 #define OCOTP_READ_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_CTRL_RSVD0_SHIFT))&OCOTP_READ_CTRL_RSVD0_MASK)
31387 /* READ_FUSE_DATA0 Bit Fields */
31388 #define OCOTP_READ_FUSE_DATA0_DATA0_MASK         0xFFFFFFFFu
31389 #define OCOTP_READ_FUSE_DATA0_DATA0_SHIFT        0
31390 #define OCOTP_READ_FUSE_DATA0_DATA0(x)           (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA0_DATA0_SHIFT))&OCOTP_READ_FUSE_DATA0_DATA0_MASK)
31391 /* READ_FUSE_DATA1 Bit Fields */
31392 #define OCOTP_READ_FUSE_DATA1_DATA1_MASK         0xFFFFFFFFu
31393 #define OCOTP_READ_FUSE_DATA1_DATA1_SHIFT        0
31394 #define OCOTP_READ_FUSE_DATA1_DATA1(x)           (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA1_DATA1_SHIFT))&OCOTP_READ_FUSE_DATA1_DATA1_MASK)
31395 /* READ_FUSE_DATA2 Bit Fields */
31396 #define OCOTP_READ_FUSE_DATA2_DATA2_MASK         0xFFFFFFFFu
31397 #define OCOTP_READ_FUSE_DATA2_DATA2_SHIFT        0
31398 #define OCOTP_READ_FUSE_DATA2_DATA2(x)           (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA2_DATA2_SHIFT))&OCOTP_READ_FUSE_DATA2_DATA2_MASK)
31399 /* READ_FUSE_DATA3 Bit Fields */
31400 #define OCOTP_READ_FUSE_DATA3_DATA3_MASK         0xFFFFFFFFu
31401 #define OCOTP_READ_FUSE_DATA3_DATA3_SHIFT        0
31402 #define OCOTP_READ_FUSE_DATA3_DATA3(x)           (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA3_DATA3_SHIFT))&OCOTP_READ_FUSE_DATA3_DATA3_MASK)
31403 /* SW_STICKY Bit Fields */
31404 #define OCOTP_SW_STICKY_RSVD0_MASK               0x1u
31405 #define OCOTP_SW_STICKY_RSVD0_SHIFT              0
31406 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK     0x2u
31407 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT    1
31408 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK   0x4u
31409 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT  2
31410 #define OCOTP_SW_STICKY_RSVD1_MASK               0xFFFFFFF8u
31411 #define OCOTP_SW_STICKY_RSVD1_SHIFT              3
31412 #define OCOTP_SW_STICKY_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_SW_STICKY_RSVD1_SHIFT))&OCOTP_SW_STICKY_RSVD1_MASK)
31413 /* SCS Bit Fields */
31414 #define OCOTP_SCS_HAB_JDE_MASK                   0x1u
31415 #define OCOTP_SCS_HAB_JDE_SHIFT                  0
31416 #define OCOTP_SCS_SPARE_MASK                     0x7FFFFFFEu
31417 #define OCOTP_SCS_SPARE_SHIFT                    1
31418 #define OCOTP_SCS_SPARE(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SPARE_SHIFT))&OCOTP_SCS_SPARE_MASK)
31419 #define OCOTP_SCS_LOCK_MASK                      0x80000000u
31420 #define OCOTP_SCS_LOCK_SHIFT                     31
31421 /* SCS_SET Bit Fields */
31422 #define OCOTP_SCS_SET_HAB_JDE_MASK               0x1u
31423 #define OCOTP_SCS_SET_HAB_JDE_SHIFT              0
31424 #define OCOTP_SCS_SET_SPARE_MASK                 0x7FFFFFFEu
31425 #define OCOTP_SCS_SET_SPARE_SHIFT                1
31426 #define OCOTP_SCS_SET_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SET_SPARE_SHIFT))&OCOTP_SCS_SET_SPARE_MASK)
31427 #define OCOTP_SCS_SET_LOCK_MASK                  0x80000000u
31428 #define OCOTP_SCS_SET_LOCK_SHIFT                 31
31429 /* SCS_CLR Bit Fields */
31430 #define OCOTP_SCS_CLR_HAB_JDE_MASK               0x1u
31431 #define OCOTP_SCS_CLR_HAB_JDE_SHIFT              0
31432 #define OCOTP_SCS_CLR_SPARE_MASK                 0x7FFFFFFEu
31433 #define OCOTP_SCS_CLR_SPARE_SHIFT                1
31434 #define OCOTP_SCS_CLR_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_CLR_SPARE_SHIFT))&OCOTP_SCS_CLR_SPARE_MASK)
31435 #define OCOTP_SCS_CLR_LOCK_MASK                  0x80000000u
31436 #define OCOTP_SCS_CLR_LOCK_SHIFT                 31
31437 /* SCS_TOG Bit Fields */
31438 #define OCOTP_SCS_TOG_HAB_JDE_MASK               0x1u
31439 #define OCOTP_SCS_TOG_HAB_JDE_SHIFT              0
31440 #define OCOTP_SCS_TOG_SPARE_MASK                 0x7FFFFFFEu
31441 #define OCOTP_SCS_TOG_SPARE_SHIFT                1
31442 #define OCOTP_SCS_TOG_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_TOG_SPARE_SHIFT))&OCOTP_SCS_TOG_SPARE_MASK)
31443 #define OCOTP_SCS_TOG_LOCK_MASK                  0x80000000u
31444 #define OCOTP_SCS_TOG_LOCK_SHIFT                 31
31445 /* CRC_ADDR Bit Fields */
31446 #define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK      0xFFu
31447 #define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT     0
31448 #define OCOTP_CRC_ADDR_DATA_START_ADDR(x)        (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT))&OCOTP_CRC_ADDR_DATA_START_ADDR_MASK)
31449 #define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK        0xFF00u
31450 #define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT       8
31451 #define OCOTP_CRC_ADDR_DATA_END_ADDR(x)          (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT))&OCOTP_CRC_ADDR_DATA_END_ADDR_MASK)
31452 #define OCOTP_CRC_ADDR_CRC_ADDR_MASK             0x30000u
31453 #define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT            16
31454 #define OCOTP_CRC_ADDR_CRC_ADDR(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_CRC_ADDR_SHIFT))&OCOTP_CRC_ADDR_CRC_ADDR_MASK)
31455 #define OCOTP_CRC_ADDR_RSVD0_MASK                0xFFFC0000u
31456 #define OCOTP_CRC_ADDR_RSVD0_SHIFT               18
31457 #define OCOTP_CRC_ADDR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_RSVD0_SHIFT))&OCOTP_CRC_ADDR_RSVD0_MASK)
31458 /* CRC_VALUE Bit Fields */
31459 #define OCOTP_CRC_VALUE_DATA_MASK                0xFFFFFFFFu
31460 #define OCOTP_CRC_VALUE_DATA_SHIFT               0
31461 #define OCOTP_CRC_VALUE_DATA(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_VALUE_DATA_SHIFT))&OCOTP_CRC_VALUE_DATA_MASK)
31462 /* VERSION Bit Fields */
31463 #define OCOTP_VERSION_STEP_MASK                  0xFFFFu
31464 #define OCOTP_VERSION_STEP_SHIFT                 0
31465 #define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_STEP_SHIFT))&OCOTP_VERSION_STEP_MASK)
31466 #define OCOTP_VERSION_MINOR_MASK                 0xFF0000u
31467 #define OCOTP_VERSION_MINOR_SHIFT                16
31468 #define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MINOR_SHIFT))&OCOTP_VERSION_MINOR_MASK)
31469 #define OCOTP_VERSION_MAJOR_MASK                 0xFF000000u
31470 #define OCOTP_VERSION_MAJOR_SHIFT                24
31471 #define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MAJOR_SHIFT))&OCOTP_VERSION_MAJOR_MASK)
31472 /* LOCK Bit Fields */
31473 #define OCOTP_LOCK_TESTER_MASK                   0x3u
31474 #define OCOTP_LOCK_TESTER_SHIFT                  0
31475 #define OCOTP_LOCK_TESTER(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_TESTER_SHIFT))&OCOTP_LOCK_TESTER_MASK)
31476 #define OCOTP_LOCK_BOOT_CFG_MASK                 0xCu
31477 #define OCOTP_LOCK_BOOT_CFG_SHIFT                2
31478 #define OCOTP_LOCK_BOOT_CFG(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_BOOT_CFG_SHIFT))&OCOTP_LOCK_BOOT_CFG_MASK)
31479 #define OCOTP_LOCK_MEM_TRIM_MASK                 0x30u
31480 #define OCOTP_LOCK_MEM_TRIM_SHIFT                4
31481 #define OCOTP_LOCK_MEM_TRIM(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MEM_TRIM_SHIFT))&OCOTP_LOCK_MEM_TRIM_MASK)
31482 #define OCOTP_LOCK_ANALOG_MASK                   0xC0u
31483 #define OCOTP_LOCK_ANALOG_SHIFT                  6
31484 #define OCOTP_LOCK_ANALOG(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_ANALOG_SHIFT))&OCOTP_LOCK_ANALOG_MASK)
31485 #define OCOTP_LOCK_OTPMK_MASK                    0x100u
31486 #define OCOTP_LOCK_OTPMK_SHIFT                   8
31487 #define OCOTP_LOCK_SRK_MASK                      0x200u
31488 #define OCOTP_LOCK_SRK_SHIFT                     9
31489 #define OCOTP_LOCK_SJC_RESP_MASK                 0x400u
31490 #define OCOTP_LOCK_SJC_RESP_SHIFT                10
31491 #define OCOTP_LOCK_RSVD0_MASK                    0x800u
31492 #define OCOTP_LOCK_RSVD0_SHIFT                   11
31493 #define OCOTP_LOCK_USB_ID_MASK                   0x3000u
31494 #define OCOTP_LOCK_USB_ID_SHIFT                  12
31495 #define OCOTP_LOCK_USB_ID(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_USB_ID_SHIFT))&OCOTP_LOCK_USB_ID_MASK)
31496 #define OCOTP_LOCK_MAC_ADDR_MASK                 0xC000u
31497 #define OCOTP_LOCK_MAC_ADDR_SHIFT                14
31498 #define OCOTP_LOCK_MAC_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MAC_ADDR_SHIFT))&OCOTP_LOCK_MAC_ADDR_MASK)
31499 #define OCOTP_LOCK_MAU_KEY_MASK                  0x10000u
31500 #define OCOTP_LOCK_MAU_KEY_SHIFT                 16
31501 #define OCOTP_LOCK_ROM_PATCH_MASK                0x20000u
31502 #define OCOTP_LOCK_ROM_PATCH_SHIFT               17
31503 #define OCOTP_LOCK_RSVD1_MASK                    0xC0000u
31504 #define OCOTP_LOCK_RSVD1_SHIFT                   18
31505 #define OCOTP_LOCK_RSVD1(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_RSVD1_SHIFT))&OCOTP_LOCK_RSVD1_MASK)
31506 #define OCOTP_LOCK_GP1_MASK                      0x300000u
31507 #define OCOTP_LOCK_GP1_SHIFT                     20
31508 #define OCOTP_LOCK_GP1(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP1_SHIFT))&OCOTP_LOCK_GP1_MASK)
31509 #define OCOTP_LOCK_GP2_MASK                      0xC00000u
31510 #define OCOTP_LOCK_GP2_SHIFT                     22
31511 #define OCOTP_LOCK_GP2(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP2_SHIFT))&OCOTP_LOCK_GP2_MASK)
31512 #define OCOTP_LOCK_RSVD2_MASK                    0xF000000u
31513 #define OCOTP_LOCK_RSVD2_SHIFT                   24
31514 #define OCOTP_LOCK_RSVD2(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_RSVD2_SHIFT))&OCOTP_LOCK_RSVD2_MASK)
31515 #define OCOTP_LOCK_CRC_GP1_MASK                  0x30000000u
31516 #define OCOTP_LOCK_CRC_GP1_SHIFT                 28
31517 #define OCOTP_LOCK_CRC_GP1(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_CRC_GP1_SHIFT))&OCOTP_LOCK_CRC_GP1_MASK)
31518 #define OCOTP_LOCK_CRC_GP2_MASK                  0xC0000000u
31519 #define OCOTP_LOCK_CRC_GP2_SHIFT                 30
31520 #define OCOTP_LOCK_CRC_GP2(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_CRC_GP2_SHIFT))&OCOTP_LOCK_CRC_GP2_MASK)
31521 /* TESTER0 Bit Fields */
31522 #define OCOTP_TESTER0_BITS_MASK                  0xFFFFFFFFu
31523 #define OCOTP_TESTER0_BITS_SHIFT                 0
31524 #define OCOTP_TESTER0_BITS(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER0_BITS_SHIFT))&OCOTP_TESTER0_BITS_MASK)
31525 /* TESTER1 Bit Fields */
31526 #define OCOTP_TESTER1_BITS_MASK                  0xFFFFFFFFu
31527 #define OCOTP_TESTER1_BITS_SHIFT                 0
31528 #define OCOTP_TESTER1_BITS(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER1_BITS_SHIFT))&OCOTP_TESTER1_BITS_MASK)
31529 /* TESTER2 Bit Fields */
31530 #define OCOTP_TESTER2_BITS_MASK                  0xFFFFFFFFu
31531 #define OCOTP_TESTER2_BITS_SHIFT                 0
31532 #define OCOTP_TESTER2_BITS(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER2_BITS_SHIFT))&OCOTP_TESTER2_BITS_MASK)
31533 /* TESTER3 Bit Fields */
31534 #define OCOTP_TESTER3_BITS_MASK                  0xFFFFFFFFu
31535 #define OCOTP_TESTER3_BITS_SHIFT                 0
31536 #define OCOTP_TESTER3_BITS(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER3_BITS_SHIFT))&OCOTP_TESTER3_BITS_MASK)
31537 /* TESTER4 Bit Fields */
31538 #define OCOTP_TESTER4_BITS_MASK                  0xFFFFFFFFu
31539 #define OCOTP_TESTER4_BITS_SHIFT                 0
31540 #define OCOTP_TESTER4_BITS(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER4_BITS_SHIFT))&OCOTP_TESTER4_BITS_MASK)
31541 /* TESTER5 Bit Fields */
31542 #define OCOTP_TESTER5_BITS_MASK                  0xFFFFFFFFu
31543 #define OCOTP_TESTER5_BITS_SHIFT                 0
31544 #define OCOTP_TESTER5_BITS(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER5_BITS_SHIFT))&OCOTP_TESTER5_BITS_MASK)
31545 /* BOOT_CFG0 Bit Fields */
31546 #define OCOTP_BOOT_CFG0_BITS_MASK                0xFFFFFFFFu
31547 #define OCOTP_BOOT_CFG0_BITS_SHIFT               0
31548 #define OCOTP_BOOT_CFG0_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG0_BITS_SHIFT))&OCOTP_BOOT_CFG0_BITS_MASK)
31549 /* BOOT_CFG1 Bit Fields */
31550 #define OCOTP_BOOT_CFG1_BITS_MASK                0xFFFFFFFFu
31551 #define OCOTP_BOOT_CFG1_BITS_SHIFT               0
31552 #define OCOTP_BOOT_CFG1_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG1_BITS_SHIFT))&OCOTP_BOOT_CFG1_BITS_MASK)
31553 /* BOOT_CFG2 Bit Fields */
31554 #define OCOTP_BOOT_CFG2_BITS_MASK                0xFFFFFFFFu
31555 #define OCOTP_BOOT_CFG2_BITS_SHIFT               0
31556 #define OCOTP_BOOT_CFG2_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG2_BITS_SHIFT))&OCOTP_BOOT_CFG2_BITS_MASK)
31557 /* BOOT_CFG3 Bit Fields */
31558 #define OCOTP_BOOT_CFG3_BITS_MASK                0xFFFFFFFFu
31559 #define OCOTP_BOOT_CFG3_BITS_SHIFT               0
31560 #define OCOTP_BOOT_CFG3_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG3_BITS_SHIFT))&OCOTP_BOOT_CFG3_BITS_MASK)
31561 /* BOOT_CFG4 Bit Fields */
31562 #define OCOTP_BOOT_CFG4_BITS_MASK                0xFFFFFFFFu
31563 #define OCOTP_BOOT_CFG4_BITS_SHIFT               0
31564 #define OCOTP_BOOT_CFG4_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG4_BITS_SHIFT))&OCOTP_BOOT_CFG4_BITS_MASK)
31565 /* MEM_TRIM0 Bit Fields */
31566 #define OCOTP_MEM_TRIM0_BITS_MASK                0xFFFFFFFFu
31567 #define OCOTP_MEM_TRIM0_BITS_SHIFT               0
31568 #define OCOTP_MEM_TRIM0_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM_TRIM0_BITS_SHIFT))&OCOTP_MEM_TRIM0_BITS_MASK)
31569 /* MEM_TRIM1 Bit Fields */
31570 #define OCOTP_MEM_TRIM1_BITS_MASK                0xFFFFFFFFu
31571 #define OCOTP_MEM_TRIM1_BITS_SHIFT               0
31572 #define OCOTP_MEM_TRIM1_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM_TRIM1_BITS_SHIFT))&OCOTP_MEM_TRIM1_BITS_MASK)
31573 /* ANA0 Bit Fields */
31574 #define OCOTP_ANA0_BITS_MASK                     0xFFFFFFFFu
31575 #define OCOTP_ANA0_BITS_SHIFT                    0
31576 #define OCOTP_ANA0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_BITS_SHIFT))&OCOTP_ANA0_BITS_MASK)
31577 /* ANA1 Bit Fields */
31578 #define OCOTP_ANA1_BITS_MASK                     0xFFFFFFFFu
31579 #define OCOTP_ANA1_BITS_SHIFT                    0
31580 #define OCOTP_ANA1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA1_BITS_SHIFT))&OCOTP_ANA1_BITS_MASK)
31581 /* OTPMK0 Bit Fields */
31582 #define OCOTP_OTPMK0_BITS_MASK                   0xFFFFFFFFu
31583 #define OCOTP_OTPMK0_BITS_SHIFT                  0
31584 #define OCOTP_OTPMK0_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK0_BITS_SHIFT))&OCOTP_OTPMK0_BITS_MASK)
31585 /* OTPMK1 Bit Fields */
31586 #define OCOTP_OTPMK1_BITS_MASK                   0xFFFFFFFFu
31587 #define OCOTP_OTPMK1_BITS_SHIFT                  0
31588 #define OCOTP_OTPMK1_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK1_BITS_SHIFT))&OCOTP_OTPMK1_BITS_MASK)
31589 /* OTPMK2 Bit Fields */
31590 #define OCOTP_OTPMK2_BITS_MASK                   0xFFFFFFFFu
31591 #define OCOTP_OTPMK2_BITS_SHIFT                  0
31592 #define OCOTP_OTPMK2_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK2_BITS_SHIFT))&OCOTP_OTPMK2_BITS_MASK)
31593 /* OTPMK3 Bit Fields */
31594 #define OCOTP_OTPMK3_BITS_MASK                   0xFFFFFFFFu
31595 #define OCOTP_OTPMK3_BITS_SHIFT                  0
31596 #define OCOTP_OTPMK3_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK3_BITS_SHIFT))&OCOTP_OTPMK3_BITS_MASK)
31597 /* OTPMK4 Bit Fields */
31598 #define OCOTP_OTPMK4_BITS_MASK                   0xFFFFFFFFu
31599 #define OCOTP_OTPMK4_BITS_SHIFT                  0
31600 #define OCOTP_OTPMK4_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK4_BITS_SHIFT))&OCOTP_OTPMK4_BITS_MASK)
31601 /* OTPMK5 Bit Fields */
31602 #define OCOTP_OTPMK5_BITS_MASK                   0xFFFFFFFFu
31603 #define OCOTP_OTPMK5_BITS_SHIFT                  0
31604 #define OCOTP_OTPMK5_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK5_BITS_SHIFT))&OCOTP_OTPMK5_BITS_MASK)
31605 /* OTPMK6 Bit Fields */
31606 #define OCOTP_OTPMK6_BITS_MASK                   0xFFFFFFFFu
31607 #define OCOTP_OTPMK6_BITS_SHIFT                  0
31608 #define OCOTP_OTPMK6_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK6_BITS_SHIFT))&OCOTP_OTPMK6_BITS_MASK)
31609 /* OTPMK7 Bit Fields */
31610 #define OCOTP_OTPMK7_BITS_MASK                   0xFFFFFFFFu
31611 #define OCOTP_OTPMK7_BITS_SHIFT                  0
31612 #define OCOTP_OTPMK7_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK7_BITS_SHIFT))&OCOTP_OTPMK7_BITS_MASK)
31613 /* SRK0 Bit Fields */
31614 #define OCOTP_SRK0_BITS_MASK                     0xFFFFFFFFu
31615 #define OCOTP_SRK0_BITS_SHIFT                    0
31616 #define OCOTP_SRK0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK0_BITS_SHIFT))&OCOTP_SRK0_BITS_MASK)
31617 /* SRK1 Bit Fields */
31618 #define OCOTP_SRK1_BITS_MASK                     0xFFFFFFFFu
31619 #define OCOTP_SRK1_BITS_SHIFT                    0
31620 #define OCOTP_SRK1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK1_BITS_SHIFT))&OCOTP_SRK1_BITS_MASK)
31621 /* SRK2 Bit Fields */
31622 #define OCOTP_SRK2_BITS_MASK                     0xFFFFFFFFu
31623 #define OCOTP_SRK2_BITS_SHIFT                    0
31624 #define OCOTP_SRK2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK2_BITS_SHIFT))&OCOTP_SRK2_BITS_MASK)
31625 /* SRK3 Bit Fields */
31626 #define OCOTP_SRK3_BITS_MASK                     0xFFFFFFFFu
31627 #define OCOTP_SRK3_BITS_SHIFT                    0
31628 #define OCOTP_SRK3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK3_BITS_SHIFT))&OCOTP_SRK3_BITS_MASK)
31629 /* SRK4 Bit Fields */
31630 #define OCOTP_SRK4_BITS_MASK                     0xFFFFFFFFu
31631 #define OCOTP_SRK4_BITS_SHIFT                    0
31632 #define OCOTP_SRK4_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK4_BITS_SHIFT))&OCOTP_SRK4_BITS_MASK)
31633 /* SRK5 Bit Fields */
31634 #define OCOTP_SRK5_BITS_MASK                     0xFFFFFFFFu
31635 #define OCOTP_SRK5_BITS_SHIFT                    0
31636 #define OCOTP_SRK5_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK5_BITS_SHIFT))&OCOTP_SRK5_BITS_MASK)
31637 /* SRK6 Bit Fields */
31638 #define OCOTP_SRK6_BITS_MASK                     0xFFFFFFFFu
31639 #define OCOTP_SRK6_BITS_SHIFT                    0
31640 #define OCOTP_SRK6_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK6_BITS_SHIFT))&OCOTP_SRK6_BITS_MASK)
31641 /* SRK7 Bit Fields */
31642 #define OCOTP_SRK7_BITS_MASK                     0xFFFFFFFFu
31643 #define OCOTP_SRK7_BITS_SHIFT                    0
31644 #define OCOTP_SRK7_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK7_BITS_SHIFT))&OCOTP_SRK7_BITS_MASK)
31645 /* SJC_RESP0 Bit Fields */
31646 #define OCOTP_SJC_RESP0_BITS_MASK                0xFFFFFFFFu
31647 #define OCOTP_SJC_RESP0_BITS_SHIFT               0
31648 #define OCOTP_SJC_RESP0_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_SJC_RESP0_BITS_SHIFT))&OCOTP_SJC_RESP0_BITS_MASK)
31649 /* SJC_RESP1 Bit Fields */
31650 #define OCOTP_SJC_RESP1_BITS_MASK                0xFFFFFFFFu
31651 #define OCOTP_SJC_RESP1_BITS_SHIFT               0
31652 #define OCOTP_SJC_RESP1_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_SJC_RESP1_BITS_SHIFT))&OCOTP_SJC_RESP1_BITS_MASK)
31653 /* USB_ID Bit Fields */
31654 #define OCOTP_USB_ID_BITS_MASK                   0xFFFFFFFFu
31655 #define OCOTP_USB_ID_BITS_SHIFT                  0
31656 #define OCOTP_USB_ID_BITS(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_USB_ID_BITS_SHIFT))&OCOTP_USB_ID_BITS_MASK)
31657 /* FIELD_RETURN Bit Fields */
31658 #define OCOTP_FIELD_RETURN_BITS_MASK             0xFFFFFFFFu
31659 #define OCOTP_FIELD_RETURN_BITS_SHIFT            0
31660 #define OCOTP_FIELD_RETURN_BITS(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_FIELD_RETURN_BITS_SHIFT))&OCOTP_FIELD_RETURN_BITS_MASK)
31661 /* MAC_ADDR0 Bit Fields */
31662 #define OCOTP_MAC_ADDR0_BITS_MASK                0xFFFFFFFFu
31663 #define OCOTP_MAC_ADDR0_BITS_SHIFT               0
31664 #define OCOTP_MAC_ADDR0_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC_ADDR0_BITS_SHIFT))&OCOTP_MAC_ADDR0_BITS_MASK)
31665 /* MAC_ADDR1 Bit Fields */
31666 #define OCOTP_MAC_ADDR1_BITS_MASK                0xFFFFFFFFu
31667 #define OCOTP_MAC_ADDR1_BITS_SHIFT               0
31668 #define OCOTP_MAC_ADDR1_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC_ADDR1_BITS_SHIFT))&OCOTP_MAC_ADDR1_BITS_MASK)
31669 /* MAC_ADDR2 Bit Fields */
31670 #define OCOTP_MAC_ADDR2_BITS_MASK                0xFFFFFFFFu
31671 #define OCOTP_MAC_ADDR2_BITS_SHIFT               0
31672 #define OCOTP_MAC_ADDR2_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC_ADDR2_BITS_SHIFT))&OCOTP_MAC_ADDR2_BITS_MASK)
31673 /* SRK_REVOKE Bit Fields */
31674 #define OCOTP_SRK_REVOKE_BITS_MASK               0xFFFFFFFFu
31675 #define OCOTP_SRK_REVOKE_BITS_SHIFT              0
31676 #define OCOTP_SRK_REVOKE_BITS(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK_REVOKE_BITS_SHIFT))&OCOTP_SRK_REVOKE_BITS_MASK)
31677 /* MAU_KEY0 Bit Fields */
31678 #define OCOTP_MAU_KEY0_BITS_MASK                 0xFFFFFFFFu
31679 #define OCOTP_MAU_KEY0_BITS_SHIFT                0
31680 #define OCOTP_MAU_KEY0_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY0_BITS_SHIFT))&OCOTP_MAU_KEY0_BITS_MASK)
31681 /* MAU_KEY1 Bit Fields */
31682 #define OCOTP_MAU_KEY1_BITS_MASK                 0xFFFFFFFFu
31683 #define OCOTP_MAU_KEY1_BITS_SHIFT                0
31684 #define OCOTP_MAU_KEY1_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY1_BITS_SHIFT))&OCOTP_MAU_KEY1_BITS_MASK)
31685 /* MAU_KEY2 Bit Fields */
31686 #define OCOTP_MAU_KEY2_BITS_MASK                 0xFFFFFFFFu
31687 #define OCOTP_MAU_KEY2_BITS_SHIFT                0
31688 #define OCOTP_MAU_KEY2_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY2_BITS_SHIFT))&OCOTP_MAU_KEY2_BITS_MASK)
31689 /* MAU_KEY3 Bit Fields */
31690 #define OCOTP_MAU_KEY3_BITS_MASK                 0xFFFFFFFFu
31691 #define OCOTP_MAU_KEY3_BITS_SHIFT                0
31692 #define OCOTP_MAU_KEY3_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY3_BITS_SHIFT))&OCOTP_MAU_KEY3_BITS_MASK)
31693 /* MAU_KEY4 Bit Fields */
31694 #define OCOTP_MAU_KEY4_BITS_MASK                 0xFFFFFFFFu
31695 #define OCOTP_MAU_KEY4_BITS_SHIFT                0
31696 #define OCOTP_MAU_KEY4_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY4_BITS_SHIFT))&OCOTP_MAU_KEY4_BITS_MASK)
31697 /* MAU_KEY5 Bit Fields */
31698 #define OCOTP_MAU_KEY5_BITS_MASK                 0xFFFFFFFFu
31699 #define OCOTP_MAU_KEY5_BITS_SHIFT                0
31700 #define OCOTP_MAU_KEY5_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY5_BITS_SHIFT))&OCOTP_MAU_KEY5_BITS_MASK)
31701 /* MAU_KEY6 Bit Fields */
31702 #define OCOTP_MAU_KEY6_BITS_MASK                 0xFFFFFFFFu
31703 #define OCOTP_MAU_KEY6_BITS_SHIFT                0
31704 #define OCOTP_MAU_KEY6_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY6_BITS_SHIFT))&OCOTP_MAU_KEY6_BITS_MASK)
31705 /* MAU_KEY7 Bit Fields */
31706 #define OCOTP_MAU_KEY7_BITS_MASK                 0xFFFFFFFFu
31707 #define OCOTP_MAU_KEY7_BITS_SHIFT                0
31708 #define OCOTP_MAU_KEY7_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY7_BITS_SHIFT))&OCOTP_MAU_KEY7_BITS_MASK)
31709 /* GP10 Bit Fields */
31710 #define OCOTP_GP10_BITS_MASK                     0xFFFFFFFFu
31711 #define OCOTP_GP10_BITS_SHIFT                    0
31712 #define OCOTP_GP10_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP10_BITS_SHIFT))&OCOTP_GP10_BITS_MASK)
31713 /* GP11 Bit Fields */
31714 #define OCOTP_GP11_BITS_MASK                     0xFFFFFFFFu
31715 #define OCOTP_GP11_BITS_SHIFT                    0
31716 #define OCOTP_GP11_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP11_BITS_SHIFT))&OCOTP_GP11_BITS_MASK)
31717 /* GP20 Bit Fields */
31718 #define OCOTP_GP20_BITS_MASK                     0xFFFFFFFFu
31719 #define OCOTP_GP20_BITS_SHIFT                    0
31720 #define OCOTP_GP20_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP20_BITS_SHIFT))&OCOTP_GP20_BITS_MASK)
31721 /* GP21 Bit Fields */
31722 #define OCOTP_GP21_BITS_MASK                     0xFFFFFFFFu
31723 #define OCOTP_GP21_BITS_SHIFT                    0
31724 #define OCOTP_GP21_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP21_BITS_SHIFT))&OCOTP_GP21_BITS_MASK)
31725 /* CRC_GP10 Bit Fields */
31726 #define OCOTP_CRC_GP10_BITS_MASK                 0xFFFFFFFFu
31727 #define OCOTP_CRC_GP10_BITS_SHIFT                0
31728 #define OCOTP_CRC_GP10_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP10_BITS_SHIFT))&OCOTP_CRC_GP10_BITS_MASK)
31729 /* CRC_GP11 Bit Fields */
31730 #define OCOTP_CRC_GP11_BITS_MASK                 0xFFFFFFFFu
31731 #define OCOTP_CRC_GP11_BITS_SHIFT                0
31732 #define OCOTP_CRC_GP11_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP11_BITS_SHIFT))&OCOTP_CRC_GP11_BITS_MASK)
31733 /* CRC_GP20 Bit Fields */
31734 #define OCOTP_CRC_GP20_BITS_MASK                 0xFFFFFFFFu
31735 #define OCOTP_CRC_GP20_BITS_SHIFT                0
31736 #define OCOTP_CRC_GP20_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP20_BITS_SHIFT))&OCOTP_CRC_GP20_BITS_MASK)
31737 /* CRC_GP21 Bit Fields */
31738 #define OCOTP_CRC_GP21_BITS_MASK                 0xFFFFFFFFu
31739 #define OCOTP_CRC_GP21_BITS_SHIFT                0
31740 #define OCOTP_CRC_GP21_BITS(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP21_BITS_SHIFT))&OCOTP_CRC_GP21_BITS_MASK)
31741 
31742 /*!
31743  * @}
31744  */ /* end of group OCOTP_Register_Masks */
31745 
31746 /* OCOTP - Peripheral instance base addresses */
31747 /** Peripheral OCOTP base address */
31748 #define OCOTP_BASE                               (0x30350000u)
31749 /** Peripheral OCOTP base pointer */
31750 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
31751 #define OCOTP_BASE_PTR                           (OCOTP)
31752 /** Array initializer of OCOTP peripheral base addresses */
31753 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
31754 /** Array initializer of OCOTP peripheral base pointers */
31755 #define OCOTP_BASE_PTRS                          { OCOTP }
31756 /* ----------------------------------------------------------------------------
31757    -- OCOTP - Register accessor macros
31758    ---------------------------------------------------------------------------- */
31759 
31760 /*!
31761  * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros
31762  * @{
31763  */
31764 
31765 
31766 /* OCOTP - Register instance definitions */
31767 /* OCOTP */
31768 #define OCOTP_CTRL                               OCOTP_CTRL_REG(OCOTP_BASE_PTR)
31769 #define OCOTP_CTRL_SET                           OCOTP_CTRL_SET_REG(OCOTP_BASE_PTR)
31770 #define OCOTP_CTRL_CLR                           OCOTP_CTRL_CLR_REG(OCOTP_BASE_PTR)
31771 #define OCOTP_CTRL_TOG                           OCOTP_CTRL_TOG_REG(OCOTP_BASE_PTR)
31772 #define OCOTP_TIMING                             OCOTP_TIMING_REG(OCOTP_BASE_PTR)
31773 #define OCOTP_DATA0                              OCOTP_DATA0_REG(OCOTP_BASE_PTR)
31774 #define OCOTP_DATA1                              OCOTP_DATA1_REG(OCOTP_BASE_PTR)
31775 #define OCOTP_DATA2                              OCOTP_DATA2_REG(OCOTP_BASE_PTR)
31776 #define OCOTP_DATA3                              OCOTP_DATA3_REG(OCOTP_BASE_PTR)
31777 #define OCOTP_READ_CTRL                          OCOTP_READ_CTRL_REG(OCOTP_BASE_PTR)
31778 #define OCOTP_READ_FUSE_DATA0                    OCOTP_READ_FUSE_DATA0_REG(OCOTP_BASE_PTR)
31779 #define OCOTP_READ_FUSE_DATA1                    OCOTP_READ_FUSE_DATA1_REG(OCOTP_BASE_PTR)
31780 #define OCOTP_READ_FUSE_DATA2                    OCOTP_READ_FUSE_DATA2_REG(OCOTP_BASE_PTR)
31781 #define OCOTP_READ_FUSE_DATA3                    OCOTP_READ_FUSE_DATA3_REG(OCOTP_BASE_PTR)
31782 #define OCOTP_SW_STICKY                          OCOTP_SW_STICKY_REG(OCOTP_BASE_PTR)
31783 #define OCOTP_SCS                                OCOTP_SCS_REG(OCOTP_BASE_PTR)
31784 #define OCOTP_SCS_SET                            OCOTP_SCS_SET_REG(OCOTP_BASE_PTR)
31785 #define OCOTP_SCS_CLR                            OCOTP_SCS_CLR_REG(OCOTP_BASE_PTR)
31786 #define OCOTP_SCS_TOG                            OCOTP_SCS_TOG_REG(OCOTP_BASE_PTR)
31787 #define OCOTP_CRC_ADDR                           OCOTP_CRC_ADDR_REG(OCOTP_BASE_PTR)
31788 #define OCOTP_CRC_VALUE                          OCOTP_CRC_VALUE_REG(OCOTP_BASE_PTR)
31789 #define OCOTP_VERSION                            OCOTP_VERSION_REG(OCOTP_BASE_PTR)
31790 #define OCOTP_LOCK                               OCOTP_LOCK_REG(OCOTP_BASE_PTR)
31791 #define OCOTP_TESTER0                            OCOTP_TESTER0_REG(OCOTP_BASE_PTR)
31792 #define OCOTP_TESTER1                            OCOTP_TESTER1_REG(OCOTP_BASE_PTR)
31793 #define OCOTP_TESTER2                            OCOTP_TESTER2_REG(OCOTP_BASE_PTR)
31794 #define OCOTP_TESTER3                            OCOTP_TESTER3_REG(OCOTP_BASE_PTR)
31795 #define OCOTP_TESTER4                            OCOTP_TESTER4_REG(OCOTP_BASE_PTR)
31796 #define OCOTP_TESTER5                            OCOTP_TESTER5_REG(OCOTP_BASE_PTR)
31797 #define OCOTP_BOOT_CFG0                          OCOTP_BOOT_CFG0_REG(OCOTP_BASE_PTR)
31798 #define OCOTP_BOOT_CFG1                          OCOTP_BOOT_CFG1_REG(OCOTP_BASE_PTR)
31799 #define OCOTP_BOOT_CFG2                          OCOTP_BOOT_CFG2_REG(OCOTP_BASE_PTR)
31800 #define OCOTP_BOOT_CFG3                          OCOTP_BOOT_CFG3_REG(OCOTP_BASE_PTR)
31801 #define OCOTP_BOOT_CFG4                          OCOTP_BOOT_CFG4_REG(OCOTP_BASE_PTR)
31802 #define OCOTP_MEM_TRIM0                          OCOTP_MEM_TRIM0_REG(OCOTP_BASE_PTR)
31803 #define OCOTP_MEM_TRIM1                          OCOTP_MEM_TRIM1_REG(OCOTP_BASE_PTR)
31804 #define OCOTP_ANA0                               OCOTP_ANA0_REG(OCOTP_BASE_PTR)
31805 #define OCOTP_ANA1                               OCOTP_ANA1_REG(OCOTP_BASE_PTR)
31806 #define OCOTP_OTPMK0                             OCOTP_OTPMK0_REG(OCOTP_BASE_PTR)
31807 #define OCOTP_OTPMK1                             OCOTP_OTPMK1_REG(OCOTP_BASE_PTR)
31808 #define OCOTP_OTPMK2                             OCOTP_OTPMK2_REG(OCOTP_BASE_PTR)
31809 #define OCOTP_OTPMK3                             OCOTP_OTPMK3_REG(OCOTP_BASE_PTR)
31810 #define OCOTP_OTPMK4                             OCOTP_OTPMK4_REG(OCOTP_BASE_PTR)
31811 #define OCOTP_OTPMK5                             OCOTP_OTPMK5_REG(OCOTP_BASE_PTR)
31812 #define OCOTP_OTPMK6                             OCOTP_OTPMK6_REG(OCOTP_BASE_PTR)
31813 #define OCOTP_OTPMK7                             OCOTP_OTPMK7_REG(OCOTP_BASE_PTR)
31814 #define OCOTP_SRK0                               OCOTP_SRK0_REG(OCOTP_BASE_PTR)
31815 #define OCOTP_SRK1                               OCOTP_SRK1_REG(OCOTP_BASE_PTR)
31816 #define OCOTP_SRK2                               OCOTP_SRK2_REG(OCOTP_BASE_PTR)
31817 #define OCOTP_SRK3                               OCOTP_SRK3_REG(OCOTP_BASE_PTR)
31818 #define OCOTP_SRK4                               OCOTP_SRK4_REG(OCOTP_BASE_PTR)
31819 #define OCOTP_SRK5                               OCOTP_SRK5_REG(OCOTP_BASE_PTR)
31820 #define OCOTP_SRK6                               OCOTP_SRK6_REG(OCOTP_BASE_PTR)
31821 #define OCOTP_SRK7                               OCOTP_SRK7_REG(OCOTP_BASE_PTR)
31822 #define OCOTP_SJC_RESP0                          OCOTP_SJC_RESP0_REG(OCOTP_BASE_PTR)
31823 #define OCOTP_SJC_RESP1                          OCOTP_SJC_RESP1_REG(OCOTP_BASE_PTR)
31824 #define OCOTP_USB_ID                             OCOTP_USB_ID_REG(OCOTP_BASE_PTR)
31825 #define OCOTP_FIELD_RETURN                       OCOTP_FIELD_RETURN_REG(OCOTP_BASE_PTR)
31826 #define OCOTP_MAC_ADDR0                          OCOTP_MAC_ADDR0_REG(OCOTP_BASE_PTR)
31827 #define OCOTP_MAC_ADDR1                          OCOTP_MAC_ADDR1_REG(OCOTP_BASE_PTR)
31828 #define OCOTP_MAC_ADDR2                          OCOTP_MAC_ADDR2_REG(OCOTP_BASE_PTR)
31829 #define OCOTP_SRK_REVOKE                         OCOTP_SRK_REVOKE_REG(OCOTP_BASE_PTR)
31830 #define OCOTP_MAU_KEY0                           OCOTP_MAU_KEY0_REG(OCOTP_BASE_PTR)
31831 #define OCOTP_MAU_KEY1                           OCOTP_MAU_KEY1_REG(OCOTP_BASE_PTR)
31832 #define OCOTP_MAU_KEY2                           OCOTP_MAU_KEY2_REG(OCOTP_BASE_PTR)
31833 #define OCOTP_MAU_KEY3                           OCOTP_MAU_KEY3_REG(OCOTP_BASE_PTR)
31834 #define OCOTP_MAU_KEY4                           OCOTP_MAU_KEY4_REG(OCOTP_BASE_PTR)
31835 #define OCOTP_MAU_KEY5                           OCOTP_MAU_KEY5_REG(OCOTP_BASE_PTR)
31836 #define OCOTP_MAU_KEY6                           OCOTP_MAU_KEY6_REG(OCOTP_BASE_PTR)
31837 #define OCOTP_MAU_KEY7                           OCOTP_MAU_KEY7_REG(OCOTP_BASE_PTR)
31838 #define OCOTP_GP10                               OCOTP_GP10_REG(OCOTP_BASE_PTR)
31839 #define OCOTP_GP11                               OCOTP_GP11_REG(OCOTP_BASE_PTR)
31840 #define OCOTP_GP20                               OCOTP_GP20_REG(OCOTP_BASE_PTR)
31841 #define OCOTP_GP21                               OCOTP_GP21_REG(OCOTP_BASE_PTR)
31842 #define OCOTP_CRC_GP10                           OCOTP_CRC_GP10_REG(OCOTP_BASE_PTR)
31843 #define OCOTP_CRC_GP11                           OCOTP_CRC_GP11_REG(OCOTP_BASE_PTR)
31844 #define OCOTP_CRC_GP20                           OCOTP_CRC_GP20_REG(OCOTP_BASE_PTR)
31845 #define OCOTP_CRC_GP21                           OCOTP_CRC_GP21_REG(OCOTP_BASE_PTR)
31846 /*!
31847  * @}
31848  */ /* end of group OCOTP_Register_Accessor_Macros */
31849 
31850 
31851 /*!
31852  * @}
31853  */ /* end of group OCOTP_Peripheral */
31854 
31855 /* ----------------------------------------------------------------------------
31856    -- PCIE_PHY_CMN Peripheral Access Layer
31857    ---------------------------------------------------------------------------- */
31858 
31859 /*!
31860  * @addtogroup PCIE_PHY_CMN_Peripheral_Access_Layer PCIE_PHY_CMN Peripheral Access Layer
31861  * @{
31862  */
31863 
31864 /** PCIE_PHY_CMN - Register Layout Typedef */
31865 typedef struct {
31866   uint8_t RESERVED_0[4];
31867   __IO  uint32_t REG01;                                  /**< , offset: 0x4 */
31868   __IO  uint32_t REG02;                                  /**< , offset: 0x8 */
31869   uint8_t RESERVED_1[6];
31870   __IO  uint32_t REG03;                                  /**< , offset: 0x12 */
31871   __IO  uint32_t REG04;                                  /**< , offset: 0x16 */
31872   uint8_t RESERVED_2[6];
31873   __IO  uint32_t REG05;                                  /**< , offset: 0x20 */
31874   __IO  uint32_t REG06;                                  /**< , offset: 0x24 */
31875   __IO  uint32_t REG07;                                  /**< , offset: 0x28 */
31876   __IO  uint32_t REG0B;                                  /**< , offset: 0x2C */
31877   uint8_t RESERVED_3[2];
31878   __IO  uint32_t REG08;                                  /**< , offset: 0x32 */
31879   __IO  uint32_t REG09;                                  /**< , offset: 0x36 */
31880   uint8_t RESERVED_4[6];
31881   __IO  uint32_t REG11;                                  /**< , offset: 0x40 */
31882   uint8_t RESERVED_5[28];
31883   __IO  uint32_t REG15;                                  /**< , offset: 0x60 */
31884   __IO  uint32_t REG16;                                  /**< , offset: 0x64 */
31885   __IO  uint32_t REG17;                                  /**< , offset: 0x68 */
31886   uint8_t RESERVED_6[6];
31887   __IO  uint32_t REG18;                                  /**< , offset: 0x72 */
31888   __IO  uint32_t REG19;                                  /**< , offset: 0x76 */
31889   uint8_t RESERVED_7[6];
31890   __IO  uint32_t REG1A;                                  /**< , offset: 0x80 */
31891 } PCIE_PHY_CMN_Type, *PCIE_PHY_CMN_MemMapPtr;
31892 /* ----------------------------------------------------------------------------
31893    -- PCIE_PHY_CMN - Register accessor macros
31894    ---------------------------------------------------------------------------- */
31895 
31896 /*!
31897  * @addtogroup PCIE_PHY_CMN_Register_Accessor_Macros PCIE_PHY_CMN - Register accessor macros
31898  * @{
31899  */
31900 
31901 
31902 /* PCIE_PHY_CMN - Register accessors */
31903 #define PCIE_PHY_CMN_REG01_REG(base)             ((base)->REG01)
31904 #define PCIE_PHY_CMN_REG02_REG(base)             ((base)->REG02)
31905 #define PCIE_PHY_CMN_REG03_REG(base)             ((base)->REG03)
31906 #define PCIE_PHY_CMN_REG04_REG(base)             ((base)->REG04)
31907 #define PCIE_PHY_CMN_REG05_REG(base)             ((base)->REG05)
31908 #define PCIE_PHY_CMN_REG06_REG(base)             ((base)->REG06)
31909 #define PCIE_PHY_CMN_REG07_REG(base)             ((base)->REG07)
31910 #define PCIE_PHY_CMN_REG0B_REG(base)             ((base)->REG0B)
31911 #define PCIE_PHY_CMN_REG08_REG(base)             ((base)->REG08)
31912 #define PCIE_PHY_CMN_REG09_REG(base)             ((base)->REG09)
31913 #define PCIE_PHY_CMN_REG11_REG(base)             ((base)->REG11)
31914 #define PCIE_PHY_CMN_REG15_REG(base)             ((base)->REG15)
31915 #define PCIE_PHY_CMN_REG16_REG(base)             ((base)->REG16)
31916 #define PCIE_PHY_CMN_REG17_REG(base)             ((base)->REG17)
31917 #define PCIE_PHY_CMN_REG18_REG(base)             ((base)->REG18)
31918 #define PCIE_PHY_CMN_REG19_REG(base)             ((base)->REG19)
31919 #define PCIE_PHY_CMN_REG1A_REG(base)             ((base)->REG1A)
31920 
31921 /*!
31922  * @}
31923  */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */
31924 /* ----------------------------------------------------------------------------
31925    -- PCIE_PHY_CMN Register Masks
31926    ---------------------------------------------------------------------------- */
31927 
31928 /*!
31929  * @addtogroup PCIE_PHY_CMN_Register_Masks PCIE_PHY_CMN Register Masks
31930  * @{
31931  */
31932 
31933 /* REG01 Bit Fields */
31934 #define PCIE_PHY_CMN_REG01_TCODE_MASK            0xFu
31935 #define PCIE_PHY_CMN_REG01_TCODE_SHIFT           0
31936 #define PCIE_PHY_CMN_REG01_TCODE(x)              (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG01_TCODE_SHIFT))&PCIE_PHY_CMN_REG01_TCODE_MASK)
31937 #define PCIE_PHY_CMN_REG01_RCODE_MASK            0xF0u
31938 #define PCIE_PHY_CMN_REG01_RCODE_SHIFT           4
31939 #define PCIE_PHY_CMN_REG01_RCODE(x)              (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG01_RCODE_SHIFT))&PCIE_PHY_CMN_REG01_RCODE_MASK)
31940 /* REG02 Bit Fields */
31941 #define PCIE_PHY_CMN_REG02_FORCE_MASK            0x1u
31942 #define PCIE_PHY_CMN_REG02_FORCE_SHIFT           0
31943 #define PCIE_PHY_CMN_REG02_PDIV_MASK             0xF0u
31944 #define PCIE_PHY_CMN_REG02_PDIV_SHIFT            4
31945 #define PCIE_PHY_CMN_REG02_PDIV(x)               (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG02_PDIV_SHIFT))&PCIE_PHY_CMN_REG02_PDIV_MASK)
31946 /* REG03 Bit Fields */
31947 #define PCIE_PHY_CMN_REG03_CTRL_CP_MASK          0xFu
31948 #define PCIE_PHY_CMN_REG03_CTRL_CP_SHIFT         0
31949 #define PCIE_PHY_CMN_REG03_CTRL_CP(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG03_CTRL_CP_SHIFT))&PCIE_PHY_CMN_REG03_CTRL_CP_MASK)
31950 /* REG04 Bit Fields */
31951 #define PCIE_PHY_CMN_REG04_CTRL_C_MASK           0xEu
31952 #define PCIE_PHY_CMN_REG04_CTRL_C_SHIFT          1
31953 #define PCIE_PHY_CMN_REG04_CTRL_C(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG04_CTRL_C_SHIFT))&PCIE_PHY_CMN_REG04_CTRL_C_MASK)
31954 #define PCIE_PHY_CMN_REG04_CTRL_R_MASK           0xF0u
31955 #define PCIE_PHY_CMN_REG04_CTRL_R_SHIFT          4
31956 #define PCIE_PHY_CMN_REG04_CTRL_R(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG04_CTRL_R_SHIFT))&PCIE_PHY_CMN_REG04_CTRL_R_MASK)
31957 /* REG05 Bit Fields */
31958 #define PCIE_PHY_CMN_REG05_DCC_FB_EN_MASK        0x40u
31959 #define PCIE_PHY_CMN_REG05_DCC_FB_EN_SHIFT       6
31960 #define PCIE_PHY_CMN_REG05_CKFB_MON_EN_MASK      0x80u
31961 #define PCIE_PHY_CMN_REG05_CKFB_MON_EN_SHIFT     7
31962 /* REG06 Bit Fields */
31963 #define PCIE_PHY_CMN_REG06_SD_DIV_MASK           0x7u
31964 #define PCIE_PHY_CMN_REG06_SD_DIV_SHIFT          0
31965 #define PCIE_PHY_CMN_REG06_SD_DIV(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG06_SD_DIV_SHIFT))&PCIE_PHY_CMN_REG06_SD_DIV_MASK)
31966 #define PCIE_PHY_CMN_REG06_CK100M_EN_MASK        0x10u
31967 #define PCIE_PHY_CMN_REG06_CK100M_EN_SHIFT       4
31968 #define PCIE_PHY_CMN_REG06_MDIV_HS_MASK          0x80u
31969 #define PCIE_PHY_CMN_REG06_MDIV_HS_SHIFT         7
31970 /* REG07 Bit Fields */
31971 #define PCIE_PHY_CMN_REG07_MDIV_MS_MASK          0xFFu
31972 #define PCIE_PHY_CMN_REG07_MDIV_MS_SHIFT         0
31973 #define PCIE_PHY_CMN_REG07_MDIV_MS(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG07_MDIV_MS_SHIFT))&PCIE_PHY_CMN_REG07_MDIV_MS_MASK)
31974 /* REG0B Bit Fields */
31975 #define PCIE_PHY_CMN_REG0B_SSC_MASK              0x7Fu
31976 #define PCIE_PHY_CMN_REG0B_SSC_SHIFT             0
31977 #define PCIE_PHY_CMN_REG0B_SSC(x)                (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG0B_SSC_SHIFT))&PCIE_PHY_CMN_REG0B_SSC_MASK)
31978 /* REG08 Bit Fields */
31979 #define PCIE_PHY_CMN_REG08_PI_EN_MASK            0x1u
31980 #define PCIE_PHY_CMN_REG08_PI_EN_SHIFT           0
31981 #define PCIE_PHY_CMN_REG08_PI_STR_MASK           0x1Eu
31982 #define PCIE_PHY_CMN_REG08_PI_STR_SHIFT          1
31983 #define PCIE_PHY_CMN_REG08_PI_STR(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG08_PI_STR_SHIFT))&PCIE_PHY_CMN_REG08_PI_STR_MASK)
31984 /* REG09 Bit Fields */
31985 #define PCIE_PHY_CMN_REG09_SSC_CNTL_MASK         0x60u
31986 #define PCIE_PHY_CMN_REG09_SSC_CNTL_SHIFT        5
31987 #define PCIE_PHY_CMN_REG09_SSC_CNTL(x)           (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG09_SSC_CNTL_SHIFT))&PCIE_PHY_CMN_REG09_SSC_CNTL_MASK)
31988 /* REG11 Bit Fields */
31989 #define PCIE_PHY_CMN_REG11_PREF_MASK             0xFFu
31990 #define PCIE_PHY_CMN_REG11_PREF_SHIFT            0
31991 #define PCIE_PHY_CMN_REG11_PREF(x)               (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG11_PREF_SHIFT))&PCIE_PHY_CMN_REG11_PREF_MASK)
31992 /* REG15 Bit Fields */
31993 #define PCIE_PHY_CMN_REG15_MON_EN_MASK           0x10u
31994 #define PCIE_PHY_CMN_REG15_MON_EN_SHIFT          4
31995 #define PCIE_PHY_CMN_REG15_PD_SCMN_MASK          0x60u
31996 #define PCIE_PHY_CMN_REG15_PD_SCMN_SHIFT         5
31997 #define PCIE_PHY_CMN_REG15_PD_SCMN(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG15_PD_SCMN_SHIFT))&PCIE_PHY_CMN_REG15_PD_SCMN_MASK)
31998 #define PCIE_PHY_CMN_REG15_PHY_CMNPD_EN_MASK     0x80u
31999 #define PCIE_PHY_CMN_REG15_PHY_CMNPD_EN_SHIFT    7
32000 /* REG16 Bit Fields */
32001 #define PCIE_PHY_CMN_REG16_PHY_SSC_EN_MASK       0xCu
32002 #define PCIE_PHY_CMN_REG16_PHY_SSC_EN_SHIFT      2
32003 #define PCIE_PHY_CMN_REG16_PHY_SSC_EN(x)         (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG16_PHY_SSC_EN_SHIFT))&PCIE_PHY_CMN_REG16_PHY_SSC_EN_MASK)
32004 /* REG17 Bit Fields */
32005 #define PCIE_PHY_CMN_REG17_RDIV_MASK             0xFu
32006 #define PCIE_PHY_CMN_REG17_RDIV_SHIFT            0
32007 #define PCIE_PHY_CMN_REG17_RDIV(x)               (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG17_RDIV_SHIFT))&PCIE_PHY_CMN_REG17_RDIV_MASK)
32008 #define PCIE_PHY_CMN_REG17_RDIV_EN_MASK          0x10u
32009 #define PCIE_PHY_CMN_REG17_RDIV_EN_SHIFT         4
32010 #define PCIE_PHY_CMN_REG17_TG_CODE_EN_MASK       0x80u
32011 #define PCIE_PHY_CMN_REG17_TG_CODE_EN_SHIFT      7
32012 /* REG18 Bit Fields */
32013 #define PCIE_PHY_CMN_REG18_TG_CODE_MASK          0xFFu
32014 #define PCIE_PHY_CMN_REG18_TG_CODE_SHIFT         0
32015 #define PCIE_PHY_CMN_REG18_TG_CODE(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG18_TG_CODE_SHIFT))&PCIE_PHY_CMN_REG18_TG_CODE_MASK)
32016 /* REG19 Bit Fields */
32017 #define PCIE_PHY_CMN_REG19_TOL_MASK              0x7u
32018 #define PCIE_PHY_CMN_REG19_TOL_SHIFT             0
32019 #define PCIE_PHY_CMN_REG19_TOL(x)                (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG19_TOL_SHIFT))&PCIE_PHY_CMN_REG19_TOL_MASK)
32020 #define PCIE_PHY_CMN_REG19_PD_CMN_MASK           0x8u
32021 #define PCIE_PHY_CMN_REG19_PD_CMN_SHIFT          3
32022 #define PCIE_PHY_CMN_REG19_RTOL_MASK             0xF0u
32023 #define PCIE_PHY_CMN_REG19_RTOL_SHIFT            4
32024 #define PCIE_PHY_CMN_REG19_RTOL(x)               (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG19_RTOL_SHIFT))&PCIE_PHY_CMN_REG19_RTOL_MASK)
32025 /* REG1A Bit Fields */
32026 #define PCIE_PHY_CMN_REG1A_CMNRST_MASK           0xFFu
32027 #define PCIE_PHY_CMN_REG1A_CMNRST_SHIFT          0
32028 #define PCIE_PHY_CMN_REG1A_CMNRST(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG1A_CMNRST_SHIFT))&PCIE_PHY_CMN_REG1A_CMNRST_MASK)
32029 
32030 /*!
32031  * @}
32032  */ /* end of group PCIE_PHY_CMN_Register_Masks */
32033 
32034 /* PCIE_PHY_CMN - Peripheral instance base addresses */
32035 /** Peripheral PCIE_PHY_CMN base address */
32036 #define PCIE_PHY_CMN_BASE                        (0x306D0000u)
32037 /** Peripheral PCIE_PHY_CMN base pointer */
32038 #define PCIE_PHY_CMN                             ((PCIE_PHY_CMN_Type *)PCIE_PHY_CMN_BASE)
32039 #define PCIE_PHY_CMN_BASE_PTR                    (PCIE_PHY_CMN)
32040 /** Array initializer of PCIE_PHY_CMN peripheral base addresses */
32041 #define PCIE_PHY_CMN_BASE_ADDRS                  { PCIE_PHY_CMN_BASE }
32042 /** Array initializer of PCIE_PHY_CMN peripheral base pointers */
32043 #define PCIE_PHY_CMN_BASE_PTRS                   { PCIE_PHY_CMN }
32044 /* ----------------------------------------------------------------------------
32045    -- PCIE_PHY_CMN - Register accessor macros
32046    ---------------------------------------------------------------------------- */
32047 
32048 /*!
32049  * @addtogroup PCIE_PHY_CMN_Register_Accessor_Macros PCIE_PHY_CMN - Register accessor macros
32050  * @{
32051  */
32052 
32053 
32054 /* PCIE_PHY_CMN - Register instance definitions */
32055 /* PCIE_PHY_CMN */
32056 #define PCIE_PHY_CMN_REG01                       PCIE_PHY_CMN_REG01_REG(PCIE_PHY_CMN_BASE_PTR)
32057 #define PCIE_PHY_CMN_REG02                       PCIE_PHY_CMN_REG02_REG(PCIE_PHY_CMN_BASE_PTR)
32058 #define PCIE_PHY_CMN_REG03                       PCIE_PHY_CMN_REG03_REG(PCIE_PHY_CMN_BASE_PTR)
32059 #define PCIE_PHY_CMN_REG04                       PCIE_PHY_CMN_REG04_REG(PCIE_PHY_CMN_BASE_PTR)
32060 #define PCIE_PHY_CMN_REG05                       PCIE_PHY_CMN_REG05_REG(PCIE_PHY_CMN_BASE_PTR)
32061 #define PCIE_PHY_CMN_REG06                       PCIE_PHY_CMN_REG06_REG(PCIE_PHY_CMN_BASE_PTR)
32062 #define PCIE_PHY_CMN_REG07                       PCIE_PHY_CMN_REG07_REG(PCIE_PHY_CMN_BASE_PTR)
32063 #define PCIE_PHY_CMN_REG0B                       PCIE_PHY_CMN_REG0B_REG(PCIE_PHY_CMN_BASE_PTR)
32064 #define PCIE_PHY_CMN_REG08                       PCIE_PHY_CMN_REG08_REG(PCIE_PHY_CMN_BASE_PTR)
32065 #define PCIE_PHY_CMN_REG09                       PCIE_PHY_CMN_REG09_REG(PCIE_PHY_CMN_BASE_PTR)
32066 #define PCIE_PHY_CMN_REG11                       PCIE_PHY_CMN_REG11_REG(PCIE_PHY_CMN_BASE_PTR)
32067 #define PCIE_PHY_CMN_REG15                       PCIE_PHY_CMN_REG15_REG(PCIE_PHY_CMN_BASE_PTR)
32068 #define PCIE_PHY_CMN_REG16                       PCIE_PHY_CMN_REG16_REG(PCIE_PHY_CMN_BASE_PTR)
32069 #define PCIE_PHY_CMN_REG17                       PCIE_PHY_CMN_REG17_REG(PCIE_PHY_CMN_BASE_PTR)
32070 #define PCIE_PHY_CMN_REG18                       PCIE_PHY_CMN_REG18_REG(PCIE_PHY_CMN_BASE_PTR)
32071 #define PCIE_PHY_CMN_REG19                       PCIE_PHY_CMN_REG19_REG(PCIE_PHY_CMN_BASE_PTR)
32072 #define PCIE_PHY_CMN_REG1A                       PCIE_PHY_CMN_REG1A_REG(PCIE_PHY_CMN_BASE_PTR)
32073 /*!
32074  * @}
32075  */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */
32076 
32077 
32078 /*!
32079  * @}
32080  */ /* end of group PCIE_PHY_CMN_Peripheral */
32081 
32082 /* ----------------------------------------------------------------------------
32083    -- PCIE_PHY_TRSV Peripheral Access Layer
32084    ---------------------------------------------------------------------------- */
32085 
32086 /*!
32087  * @addtogroup PCIE_PHY_TRSV_Peripheral_Access_Layer PCIE_PHY_TRSV Peripheral Access Layer
32088  * @{
32089  */
32090 
32091 /** PCIE_PHY_TRSV - Register Layout Typedef */
32092 typedef struct {
32093   uint8_t RESERVED_0[132];
32094   __IO  uint32_t REG21;                                  /**< , offset: 0x84 */
32095   __IO  uint32_t REG22;                                  /**< , offset: 0x88 */
32096   uint8_t RESERVED_1[10];
32097   __IO  uint32_t REG24;                                  /**< , offset: 0x96 */
32098   uint8_t RESERVED_2[18];
32099   __IO  uint32_t REG2B;                                  /**< , offset: 0xAC */
32100   uint8_t RESERVED_3[56];
32101   __IO  uint32_t REG3A;                                  /**< , offset: 0xE8 */
32102   uint8_t RESERVED_4[12];
32103   __IO  uint32_t REG3E;                                  /**< , offset: 0xF8 */
32104   uint8_t RESERVED_5[4];
32105   __IO  uint32_t REG25;                                  /**< , offset: 0x100 */
32106   __IO  uint32_t REG26;                                  /**< , offset: 0x104 */
32107   uint8_t RESERVED_6[14];
32108   __IO  uint32_t REG29;                                  /**< , offset: 0x116 */
32109   uint8_t RESERVED_7[10];
32110   __IO  uint32_t REG31;                                  /**< , offset: 0x124 */
32111   uint8_t RESERVED_8[10];
32112   __IO  uint32_t REG33;                                  /**< , offset: 0x132 */
32113   uint8_t RESERVED_9[14];
32114   __IO  uint32_t REG36;                                  /**< , offset: 0x144 */
32115   __IO  uint32_t REG37;                                  /**< , offset: 0x148 */
32116   uint8_t RESERVED_10[6];
32117   __IO  uint32_t REG38;                                  /**< , offset: 0x152 */
32118   __IO  uint32_t REG39;                                  /**< , offset: 0x156 */
32119   uint8_t RESERVED_11[6];
32120   __IO  uint32_t REG40;                                  /**< , offset: 0x160 */
32121   uint8_t RESERVED_12[4];
32122   __IO  uint32_t REG42;                                  /**< , offset: 0x168 */
32123 } PCIE_PHY_TRSV_Type, *PCIE_PHY_TRSV_MemMapPtr;
32124 /* ----------------------------------------------------------------------------
32125    -- PCIE_PHY_TRSV - Register accessor macros
32126    ---------------------------------------------------------------------------- */
32127 
32128 /*!
32129  * @addtogroup PCIE_PHY_TRSV_Register_Accessor_Macros PCIE_PHY_TRSV - Register accessor macros
32130  * @{
32131  */
32132 
32133 
32134 /* PCIE_PHY_TRSV - Register accessors */
32135 #define PCIE_PHY_TRSV_REG21_REG(base)            ((base)->REG21)
32136 #define PCIE_PHY_TRSV_REG22_REG(base)            ((base)->REG22)
32137 #define PCIE_PHY_TRSV_REG24_REG(base)            ((base)->REG24)
32138 #define PCIE_PHY_TRSV_REG2B_REG(base)            ((base)->REG2B)
32139 #define PCIE_PHY_TRSV_REG3A_REG(base)            ((base)->REG3A)
32140 #define PCIE_PHY_TRSV_REG3E_REG(base)            ((base)->REG3E)
32141 #define PCIE_PHY_TRSV_REG25_REG(base)            ((base)->REG25)
32142 #define PCIE_PHY_TRSV_REG26_REG(base)            ((base)->REG26)
32143 #define PCIE_PHY_TRSV_REG29_REG(base)            ((base)->REG29)
32144 #define PCIE_PHY_TRSV_REG31_REG(base)            ((base)->REG31)
32145 #define PCIE_PHY_TRSV_REG33_REG(base)            ((base)->REG33)
32146 #define PCIE_PHY_TRSV_REG36_REG(base)            ((base)->REG36)
32147 #define PCIE_PHY_TRSV_REG37_REG(base)            ((base)->REG37)
32148 #define PCIE_PHY_TRSV_REG38_REG(base)            ((base)->REG38)
32149 #define PCIE_PHY_TRSV_REG39_REG(base)            ((base)->REG39)
32150 #define PCIE_PHY_TRSV_REG40_REG(base)            ((base)->REG40)
32151 #define PCIE_PHY_TRSV_REG42_REG(base)            ((base)->REG42)
32152 
32153 /*!
32154  * @}
32155  */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */
32156 /* ----------------------------------------------------------------------------
32157    -- PCIE_PHY_TRSV Register Masks
32158    ---------------------------------------------------------------------------- */
32159 
32160 /*!
32161  * @addtogroup PCIE_PHY_TRSV_Register_Masks PCIE_PHY_TRSV Register Masks
32162  * @{
32163  */
32164 
32165 /* REG21 Bit Fields */
32166 #define PCIE_PHY_TRSV_REG21_EMP_LVL_MASK         0x1Fu
32167 #define PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT        0
32168 #define PCIE_PHY_TRSV_REG21_EMP_LVL(x)           (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT))&PCIE_PHY_TRSV_REG21_EMP_LVL_MASK)
32169 #define PCIE_PHY_TRSV_REG21_DRVR_PDH_MASK        0x80u
32170 #define PCIE_PHY_TRSV_REG21_DRVR_PDH_SHIFT       7
32171 /* REG22 Bit Fields */
32172 #define PCIE_PHY_TRSV_REG22_DRV_LVL_MASK         0x3Fu
32173 #define PCIE_PHY_TRSV_REG22_DRV_LVL_SHIFT        0
32174 #define PCIE_PHY_TRSV_REG22_DRV_LVL(x)           (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG22_DRV_LVL_SHIFT))&PCIE_PHY_TRSV_REG22_DRV_LVL_MASK)
32175 /* REG24 Bit Fields */
32176 #define PCIE_PHY_TRSV_REG24_RX_EQ_SEL_MASK       0x8u
32177 #define PCIE_PHY_TRSV_REG24_RX_EQ_SEL_SHIFT      3
32178 #define PCIE_PHY_TRSV_REG24_RX_SS_MASK           0x30u
32179 #define PCIE_PHY_TRSV_REG24_RX_SS_SHIFT          4
32180 #define PCIE_PHY_TRSV_REG24_RX_SS(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG24_RX_SS_SHIFT))&PCIE_PHY_TRSV_REG24_RX_SS_MASK)
32181 #define PCIE_PHY_TRSV_REG24_RX_EQS_MASK          0x40u
32182 #define PCIE_PHY_TRSV_REG24_RX_EQS_SHIFT         6
32183 #define PCIE_PHY_TRSV_REG24_RX_SS_PD_MASK        0x80u
32184 #define PCIE_PHY_TRSV_REG24_RX_SS_PD_SHIFT       7
32185 /* REG2B Bit Fields */
32186 #define PCIE_PHY_TRSV_REG2B_RXCDR_MASK           0xFu
32187 #define PCIE_PHY_TRSV_REG2B_RXCDR_SHIFT          0
32188 #define PCIE_PHY_TRSV_REG2B_RXCDR(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG2B_RXCDR_SHIFT))&PCIE_PHY_TRSV_REG2B_RXCDR_MASK)
32189 /* REG3A Bit Fields */
32190 #define PCIE_PHY_TRSV_REG3A_TDIMODE_MASK         0x1u
32191 #define PCIE_PHY_TRSV_REG3A_TDIMODE_SHIFT        0
32192 #define PCIE_PHY_TRSV_REG3A_RDIMODE_MASK         0x2u
32193 #define PCIE_PHY_TRSV_REG3A_RDIMODE_SHIFT        1
32194 #define PCIE_PHY_TRSV_REG3A_COMDET_EN_MASK       0x8u
32195 #define PCIE_PHY_TRSV_REG3A_COMDET_EN_SHIFT      3
32196 /* REG3E Bit Fields */
32197 #define PCIE_PHY_TRSV_REG3E_DET_CNT_MASK         0xFu
32198 #define PCIE_PHY_TRSV_REG3E_DET_CNT_SHIFT        0
32199 #define PCIE_PHY_TRSV_REG3E_DET_CNT(x)           (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG3E_DET_CNT_SHIFT))&PCIE_PHY_TRSV_REG3E_DET_CNT_MASK)
32200 /* REG25 Bit Fields */
32201 #define PCIE_PHY_TRSV_REG25_RXEQS_MASK           0x7u
32202 #define PCIE_PHY_TRSV_REG25_RXEQS_SHIFT          0
32203 #define PCIE_PHY_TRSV_REG25_RXEQS(x)             (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG25_RXEQS_SHIFT))&PCIE_PHY_TRSV_REG25_RXEQS_MASK)
32204 #define PCIE_PHY_TRSV_REG25_RXEQ_MASK            0xF0u
32205 #define PCIE_PHY_TRSV_REG25_RXEQ_SHIFT           4
32206 #define PCIE_PHY_TRSV_REG25_RXEQ(x)              (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG25_RXEQ_SHIFT))&PCIE_PHY_TRSV_REG25_RXEQ_MASK)
32207 /* REG26 Bit Fields */
32208 #define PCIE_PHY_TRSV_REG26_SQTH_MASK            0x70u
32209 #define PCIE_PHY_TRSV_REG26_SQTH_SHIFT           4
32210 #define PCIE_PHY_TRSV_REG26_SQTH(x)              (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG26_SQTH_SHIFT))&PCIE_PHY_TRSV_REG26_SQTH_MASK)
32211 /* REG29 Bit Fields */
32212 #define PCIE_PHY_TRSV_REG29_BIAS_MASK            0xFFu
32213 #define PCIE_PHY_TRSV_REG29_BIAS_SHIFT           0
32214 #define PCIE_PHY_TRSV_REG29_BIAS(x)              (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG29_BIAS_SHIFT))&PCIE_PHY_TRSV_REG29_BIAS_MASK)
32215 /* REG31 Bit Fields */
32216 #define PCIE_PHY_TRSV_REG31_PD_TSV_MASK          0x80u
32217 #define PCIE_PHY_TRSV_REG31_PD_TSV_SHIFT         7
32218 /* REG33 Bit Fields */
32219 /* REG36 Bit Fields */
32220 #define PCIE_PHY_TRSV_REG36_SR_LVL_MASK          0x7u
32221 #define PCIE_PHY_TRSV_REG36_SR_LVL_SHIFT         0
32222 #define PCIE_PHY_TRSV_REG36_SR_LVL(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG36_SR_LVL_SHIFT))&PCIE_PHY_TRSV_REG36_SR_LVL_MASK)
32223 #define PCIE_PHY_TRSV_REG36_TX_SWING_MASK        0x8u
32224 #define PCIE_PHY_TRSV_REG36_TX_SWING_SHIFT       3
32225 #define PCIE_PHY_TRSV_REG36_DRVR_CNT_MASK        0x30u
32226 #define PCIE_PHY_TRSV_REG36_DRVR_CNT_SHIFT       4
32227 #define PCIE_PHY_TRSV_REG36_DRVR_CNT(x)          (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG36_DRVR_CNT_SHIFT))&PCIE_PHY_TRSV_REG36_DRVR_CNT_MASK)
32228 /* REG37 Bit Fields */
32229 /* REG38 Bit Fields */
32230 #define PCIE_PHY_TRSV_REG38_ADD_ALIGN_MASK       0x8u
32231 #define PCIE_PHY_TRSV_REG38_ADD_ALIGN_SHIFT      3
32232 #define PCIE_PHY_TRSV_REG38_RX_INV_MASK          0x10u
32233 #define PCIE_PHY_TRSV_REG38_RX_INV_SHIFT         4
32234 #define PCIE_PHY_TRSV_REG38_TX_INV_MASK          0x20u
32235 #define PCIE_PHY_TRSV_REG38_TX_INV_SHIFT         5
32236 /* REG39 Bit Fields */
32237 #define PCIE_PHY_TRSV_REG39_TD_ORD_MASK          0x30u
32238 #define PCIE_PHY_TRSV_REG39_TD_ORD_SHIFT         4
32239 #define PCIE_PHY_TRSV_REG39_TD_ORD(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG39_TD_ORD_SHIFT))&PCIE_PHY_TRSV_REG39_TD_ORD_MASK)
32240 #define PCIE_PHY_TRSV_REG39_RD_ORD_MASK          0xC0u
32241 #define PCIE_PHY_TRSV_REG39_RD_ORD_SHIFT         6
32242 #define PCIE_PHY_TRSV_REG39_RD_ORD(x)            (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG39_RD_ORD_SHIFT))&PCIE_PHY_TRSV_REG39_RD_ORD_MASK)
32243 /* REG40 Bit Fields */
32244 #define PCIE_PHY_TRSV_REG40_PD_TRAS_MASK         0x7Cu
32245 #define PCIE_PHY_TRSV_REG40_PD_TRAS_SHIFT        2
32246 #define PCIE_PHY_TRSV_REG40_PD_TRAS(x)           (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG40_PD_TRAS_SHIFT))&PCIE_PHY_TRSV_REG40_PD_TRAS_MASK)
32247 #define PCIE_PHY_TRSV_REG40_PHY_TRSV_EN_MASK     0x80u
32248 #define PCIE_PHY_TRSV_REG40_PHY_TRSV_EN_SHIFT    7
32249 /* REG42 Bit Fields */
32250 #define PCIE_PHY_TRSV_REG42_TRSVRST_MASK         0xFFu
32251 #define PCIE_PHY_TRSV_REG42_TRSVRST_SHIFT        0
32252 #define PCIE_PHY_TRSV_REG42_TRSVRST(x)           (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG42_TRSVRST_SHIFT))&PCIE_PHY_TRSV_REG42_TRSVRST_MASK)
32253 
32254 /*!
32255  * @}
32256  */ /* end of group PCIE_PHY_TRSV_Register_Masks */
32257 
32258 /* PCIE_PHY_TRSV - Peripheral instance base addresses */
32259 /** Peripheral PCIE_PHY_TRSV base address */
32260 #define PCIE_PHY_TRSV_BASE                       (0x306D0000u)
32261 /** Peripheral PCIE_PHY_TRSV base pointer */
32262 #define PCIE_PHY_TRSV                            ((PCIE_PHY_TRSV_Type *)PCIE_PHY_TRSV_BASE)
32263 #define PCIE_PHY_TRSV_BASE_PTR                   (PCIE_PHY_TRSV)
32264 /** Array initializer of PCIE_PHY_TRSV peripheral base addresses */
32265 #define PCIE_PHY_TRSV_BASE_ADDRS                 { PCIE_PHY_TRSV_BASE }
32266 /** Array initializer of PCIE_PHY_TRSV peripheral base pointers */
32267 #define PCIE_PHY_TRSV_BASE_PTRS                  { PCIE_PHY_TRSV }
32268 /* ----------------------------------------------------------------------------
32269    -- PCIE_PHY_TRSV - Register accessor macros
32270    ---------------------------------------------------------------------------- */
32271 
32272 /*!
32273  * @addtogroup PCIE_PHY_TRSV_Register_Accessor_Macros PCIE_PHY_TRSV - Register accessor macros
32274  * @{
32275  */
32276 
32277 
32278 /* PCIE_PHY_TRSV - Register instance definitions */
32279 /* PCIE_PHY_TRSV */
32280 #define PCIE_PHY_TRSV_REG21                      PCIE_PHY_TRSV_REG21_REG(PCIE_PHY_TRSV_BASE_PTR)
32281 #define PCIE_PHY_TRSV_REG22                      PCIE_PHY_TRSV_REG22_REG(PCIE_PHY_TRSV_BASE_PTR)
32282 #define PCIE_PHY_TRSV_REG24                      PCIE_PHY_TRSV_REG24_REG(PCIE_PHY_TRSV_BASE_PTR)
32283 #define PCIE_PHY_TRSV_REG2B                      PCIE_PHY_TRSV_REG2B_REG(PCIE_PHY_TRSV_BASE_PTR)
32284 #define PCIE_PHY_TRSV_REG3A                      PCIE_PHY_TRSV_REG3A_REG(PCIE_PHY_TRSV_BASE_PTR)
32285 #define PCIE_PHY_TRSV_REG3E                      PCIE_PHY_TRSV_REG3E_REG(PCIE_PHY_TRSV_BASE_PTR)
32286 #define PCIE_PHY_TRSV_REG25                      PCIE_PHY_TRSV_REG25_REG(PCIE_PHY_TRSV_BASE_PTR)
32287 #define PCIE_PHY_TRSV_REG26                      PCIE_PHY_TRSV_REG26_REG(PCIE_PHY_TRSV_BASE_PTR)
32288 #define PCIE_PHY_TRSV_REG29                      PCIE_PHY_TRSV_REG29_REG(PCIE_PHY_TRSV_BASE_PTR)
32289 #define PCIE_PHY_TRSV_REG31                      PCIE_PHY_TRSV_REG31_REG(PCIE_PHY_TRSV_BASE_PTR)
32290 #define PCIE_PHY_TRSV_REG33                      PCIE_PHY_TRSV_REG33_REG(PCIE_PHY_TRSV_BASE_PTR)
32291 #define PCIE_PHY_TRSV_REG36                      PCIE_PHY_TRSV_REG36_REG(PCIE_PHY_TRSV_BASE_PTR)
32292 #define PCIE_PHY_TRSV_REG37                      PCIE_PHY_TRSV_REG37_REG(PCIE_PHY_TRSV_BASE_PTR)
32293 #define PCIE_PHY_TRSV_REG38                      PCIE_PHY_TRSV_REG38_REG(PCIE_PHY_TRSV_BASE_PTR)
32294 #define PCIE_PHY_TRSV_REG39                      PCIE_PHY_TRSV_REG39_REG(PCIE_PHY_TRSV_BASE_PTR)
32295 #define PCIE_PHY_TRSV_REG40                      PCIE_PHY_TRSV_REG40_REG(PCIE_PHY_TRSV_BASE_PTR)
32296 #define PCIE_PHY_TRSV_REG42                      PCIE_PHY_TRSV_REG42_REG(PCIE_PHY_TRSV_BASE_PTR)
32297 /*!
32298  * @}
32299  */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */
32300 
32301 
32302 /*!
32303  * @}
32304  */ /* end of group PCIE_PHY_TRSV_Peripheral */
32305 
32306 /* ----------------------------------------------------------------------------
32307    -- PMU Peripheral Access Layer
32308    ---------------------------------------------------------------------------- */
32309 
32310 /*!
32311  * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
32312  * @{
32313  */
32314 
32315 /** PMU - Register Layout Typedef */
32316 typedef struct {
32317   uint8_t RESERVED_0[512];
32318   __IO  uint32_t REG_1P0A;                               /**< Anadig 1.0V A Regulator Control Register, offset: 0x200 */
32319   __IO  uint32_t REG_1P0A_SET;                           /**< Anadig 1.0V A Regulator Control Register, offset: 0x204 */
32320   __IO  uint32_t REG_1P0A_CLR;                           /**< Anadig 1.0V A Regulator Control Register, offset: 0x208 */
32321   __IO  uint32_t REG_1P0A_TOG;                           /**< Anadig 1.0V A Regulator Control Register, offset: 0x20C */
32322   __IO  uint32_t REG_1P0D;                               /**< Anadig 1.0V D Regulator Control Register, offset: 0x210 */
32323   __IO  uint32_t REG_1P0D_SET;                           /**< Anadig 1.0V D Regulator Control Register, offset: 0x214 */
32324   __IO  uint32_t REG_1P0D_CLR;                           /**< Anadig 1.0V D Regulator Control Register, offset: 0x218 */
32325   __IO  uint32_t REG_1P0D_TOG;                           /**< Anadig 1.0V D Regulator Control Register, offset: 0x21C */
32326   __IO  uint32_t REG_HSIC_1P2;                           /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x220 */
32327   __IO  uint32_t REG_HSIC_1P2_SET;                       /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x224 */
32328   __IO  uint32_t REG_HSIC_1P2_CLR;                       /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x228 */
32329   __IO  uint32_t REG_HSIC_1P2_TOG;                       /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x22C */
32330   __IO  uint32_t REG_LPSR_1P0;                           /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x230 */
32331   __IO  uint32_t REG_LPSR_1P0_SET;                       /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x234 */
32332   __IO  uint32_t REG_LPSR_1P0_CLR;                       /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x238 */
32333   __IO  uint32_t REG_LPSR_1P0_TOG;                       /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x23C */
32334   uint8_t RESERVED_1[48];
32335   __IO  uint32_t REF;                                    /**< Anadig Reference Analog Control and Status Register, offset: 0x270 */
32336   __IO  uint32_t REF_SET;                                /**< Anadig Reference Analog Control and Status Register, offset: 0x274 */
32337   __IO  uint32_t REF_CLR;                                /**< Anadig Reference Analog Control and Status Register, offset: 0x278 */
32338   __IO  uint32_t REF_TOG;                                /**< Anadig Reference Analog Control and Status Register, offset: 0x27C */
32339   uint8_t RESERVED_2[176];
32340   __IO  uint32_t LOWPWR_CTRL;                            /**< Anadig Low Power Control Register, offset: 0x330 */
32341   __IO  uint32_t LOWPWR_CTRL_SET;                        /**< Anadig Low Power Control Register, offset: 0x334 */
32342   __IO  uint32_t LOWPWR_CTRL_CLR;                        /**< Anadig Low Power Control Register, offset: 0x338 */
32343   __IO  uint32_t LOWPWR_CTRL_TOG;                        /**< Anadig Low Power Control Register, offset: 0x33C */
32344 } PMU_Type, *PMU_MemMapPtr;
32345 /* ----------------------------------------------------------------------------
32346    -- PMU - Register accessor macros
32347    ---------------------------------------------------------------------------- */
32348 
32349 /*!
32350  * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros
32351  * @{
32352  */
32353 
32354 
32355 /* PMU - Register accessors */
32356 #define PMU_REG_1P0A_REG(base)                   ((base)->REG_1P0A)
32357 #define PMU_REG_1P0A_SET_REG(base)               ((base)->REG_1P0A_SET)
32358 #define PMU_REG_1P0A_CLR_REG(base)               ((base)->REG_1P0A_CLR)
32359 #define PMU_REG_1P0A_TOG_REG(base)               ((base)->REG_1P0A_TOG)
32360 #define PMU_REG_1P0D_REG(base)                   ((base)->REG_1P0D)
32361 #define PMU_REG_1P0D_SET_REG(base)               ((base)->REG_1P0D_SET)
32362 #define PMU_REG_1P0D_CLR_REG(base)               ((base)->REG_1P0D_CLR)
32363 #define PMU_REG_1P0D_TOG_REG(base)               ((base)->REG_1P0D_TOG)
32364 #define PMU_REG_HSIC_1P2_REG(base)               ((base)->REG_HSIC_1P2)
32365 #define PMU_REG_HSIC_1P2_SET_REG(base)           ((base)->REG_HSIC_1P2_SET)
32366 #define PMU_REG_HSIC_1P2_CLR_REG(base)           ((base)->REG_HSIC_1P2_CLR)
32367 #define PMU_REG_HSIC_1P2_TOG_REG(base)           ((base)->REG_HSIC_1P2_TOG)
32368 #define PMU_REG_LPSR_1P0_REG(base)               ((base)->REG_LPSR_1P0)
32369 #define PMU_REG_LPSR_1P0_SET_REG(base)           ((base)->REG_LPSR_1P0_SET)
32370 #define PMU_REG_LPSR_1P0_CLR_REG(base)           ((base)->REG_LPSR_1P0_CLR)
32371 #define PMU_REG_LPSR_1P0_TOG_REG(base)           ((base)->REG_LPSR_1P0_TOG)
32372 #define PMU_REF_REG(base)                        ((base)->REF)
32373 #define PMU_REF_SET_REG(base)                    ((base)->REF_SET)
32374 #define PMU_REF_CLR_REG(base)                    ((base)->REF_CLR)
32375 #define PMU_REF_TOG_REG(base)                    ((base)->REF_TOG)
32376 #define PMU_LOWPWR_CTRL_REG(base)                ((base)->LOWPWR_CTRL)
32377 #define PMU_LOWPWR_CTRL_SET_REG(base)            ((base)->LOWPWR_CTRL_SET)
32378 #define PMU_LOWPWR_CTRL_CLR_REG(base)            ((base)->LOWPWR_CTRL_CLR)
32379 #define PMU_LOWPWR_CTRL_TOG_REG(base)            ((base)->LOWPWR_CTRL_TOG)
32380 
32381 /*!
32382  * @}
32383  */ /* end of group PMU_Register_Accessor_Macros */
32384 /* ----------------------------------------------------------------------------
32385    -- PMU Register Masks
32386    ---------------------------------------------------------------------------- */
32387 
32388 /*!
32389  * @addtogroup PMU_Register_Masks PMU Register Masks
32390  * @{
32391  */
32392 
32393 /* REG_1P0A Bit Fields */
32394 #define PMU_REG_1P0A_ENABLE_LINREG_MASK          0x1u
32395 #define PMU_REG_1P0A_ENABLE_LINREG_SHIFT         0
32396 #define PMU_REG_1P0A_ENABLE_BO_MASK              0x2u
32397 #define PMU_REG_1P0A_ENABLE_BO_SHIFT             1
32398 #define PMU_REG_1P0A_ENABLE_ILIMIT_MASK          0x4u
32399 #define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT         2
32400 #define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK        0x8u
32401 #define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT       3
32402 #define PMU_REG_1P0A_BO_OFFSET_MASK              0x70u
32403 #define PMU_REG_1P0A_BO_OFFSET_SHIFT             4
32404 #define PMU_REG_1P0A_BO_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK)
32405 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK       0x80u
32406 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT      7
32407 #define PMU_REG_1P0A_OUTPUT_TRG_MASK             0x1F00u
32408 #define PMU_REG_1P0A_OUTPUT_TRG_SHIFT            8
32409 #define PMU_REG_1P0A_OUTPUT_TRG(x)               (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK)
32410 #define PMU_REG_1P0A_RSVD0_MASK                  0xE000u
32411 #define PMU_REG_1P0A_RSVD0_SHIFT                 13
32412 #define PMU_REG_1P0A_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK)
32413 #define PMU_REG_1P0A_BO_MASK                     0x10000u
32414 #define PMU_REG_1P0A_BO_SHIFT                    16
32415 #define PMU_REG_1P0A_OK_MASK                     0x20000u
32416 #define PMU_REG_1P0A_OK_SHIFT                    17
32417 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK     0x40000u
32418 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT    18
32419 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK     0x80000u
32420 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT    19
32421 #define PMU_REG_1P0A_REG_TEST_MASK               0xF00000u
32422 #define PMU_REG_1P0A_REG_TEST_SHIFT              20
32423 #define PMU_REG_1P0A_REG_TEST(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK)
32424 #define PMU_REG_1P0A_RSVD1_MASK                  0xFF000000u
32425 #define PMU_REG_1P0A_RSVD1_SHIFT                 24
32426 #define PMU_REG_1P0A_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK)
32427 /* REG_1P0A_SET Bit Fields */
32428 #define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK      0x1u
32429 #define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT     0
32430 #define PMU_REG_1P0A_SET_ENABLE_BO_MASK          0x2u
32431 #define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT         1
32432 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK      0x4u
32433 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT     2
32434 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK    0x8u
32435 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT   3
32436 #define PMU_REG_1P0A_SET_BO_OFFSET_MASK          0x70u
32437 #define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT         4
32438 #define PMU_REG_1P0A_SET_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK)
32439 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK   0x80u
32440 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT  7
32441 #define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK         0x1F00u
32442 #define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT        8
32443 #define PMU_REG_1P0A_SET_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK)
32444 #define PMU_REG_1P0A_SET_RSVD0_MASK              0xE000u
32445 #define PMU_REG_1P0A_SET_RSVD0_SHIFT             13
32446 #define PMU_REG_1P0A_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK)
32447 #define PMU_REG_1P0A_SET_BO_MASK                 0x10000u
32448 #define PMU_REG_1P0A_SET_BO_SHIFT                16
32449 #define PMU_REG_1P0A_SET_OK_MASK                 0x20000u
32450 #define PMU_REG_1P0A_SET_OK_SHIFT                17
32451 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
32452 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18
32453 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u
32454 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19
32455 #define PMU_REG_1P0A_SET_REG_TEST_MASK           0xF00000u
32456 #define PMU_REG_1P0A_SET_REG_TEST_SHIFT          20
32457 #define PMU_REG_1P0A_SET_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK)
32458 #define PMU_REG_1P0A_SET_RSVD1_MASK              0xFF000000u
32459 #define PMU_REG_1P0A_SET_RSVD1_SHIFT             24
32460 #define PMU_REG_1P0A_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK)
32461 /* REG_1P0A_CLR Bit Fields */
32462 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK      0x1u
32463 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT     0
32464 #define PMU_REG_1P0A_CLR_ENABLE_BO_MASK          0x2u
32465 #define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT         1
32466 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK      0x4u
32467 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT     2
32468 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK    0x8u
32469 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT   3
32470 #define PMU_REG_1P0A_CLR_BO_OFFSET_MASK          0x70u
32471 #define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT         4
32472 #define PMU_REG_1P0A_CLR_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK)
32473 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK   0x80u
32474 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT  7
32475 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK         0x1F00u
32476 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT        8
32477 #define PMU_REG_1P0A_CLR_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK)
32478 #define PMU_REG_1P0A_CLR_RSVD0_MASK              0xE000u
32479 #define PMU_REG_1P0A_CLR_RSVD0_SHIFT             13
32480 #define PMU_REG_1P0A_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK)
32481 #define PMU_REG_1P0A_CLR_BO_MASK                 0x10000u
32482 #define PMU_REG_1P0A_CLR_BO_SHIFT                16
32483 #define PMU_REG_1P0A_CLR_OK_MASK                 0x20000u
32484 #define PMU_REG_1P0A_CLR_OK_SHIFT                17
32485 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
32486 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18
32487 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
32488 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19
32489 #define PMU_REG_1P0A_CLR_REG_TEST_MASK           0xF00000u
32490 #define PMU_REG_1P0A_CLR_REG_TEST_SHIFT          20
32491 #define PMU_REG_1P0A_CLR_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK)
32492 #define PMU_REG_1P0A_CLR_RSVD1_MASK              0xFF000000u
32493 #define PMU_REG_1P0A_CLR_RSVD1_SHIFT             24
32494 #define PMU_REG_1P0A_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK)
32495 /* REG_1P0A_TOG Bit Fields */
32496 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK      0x1u
32497 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT     0
32498 #define PMU_REG_1P0A_TOG_ENABLE_BO_MASK          0x2u
32499 #define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT         1
32500 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK      0x4u
32501 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT     2
32502 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK    0x8u
32503 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT   3
32504 #define PMU_REG_1P0A_TOG_BO_OFFSET_MASK          0x70u
32505 #define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT         4
32506 #define PMU_REG_1P0A_TOG_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK)
32507 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK   0x80u
32508 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT  7
32509 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK         0x1F00u
32510 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT        8
32511 #define PMU_REG_1P0A_TOG_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK)
32512 #define PMU_REG_1P0A_TOG_RSVD0_MASK              0xE000u
32513 #define PMU_REG_1P0A_TOG_RSVD0_SHIFT             13
32514 #define PMU_REG_1P0A_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK)
32515 #define PMU_REG_1P0A_TOG_BO_MASK                 0x10000u
32516 #define PMU_REG_1P0A_TOG_BO_SHIFT                16
32517 #define PMU_REG_1P0A_TOG_OK_MASK                 0x20000u
32518 #define PMU_REG_1P0A_TOG_OK_SHIFT                17
32519 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
32520 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18
32521 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
32522 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19
32523 #define PMU_REG_1P0A_TOG_REG_TEST_MASK           0xF00000u
32524 #define PMU_REG_1P0A_TOG_REG_TEST_SHIFT          20
32525 #define PMU_REG_1P0A_TOG_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK)
32526 #define PMU_REG_1P0A_TOG_RSVD1_MASK              0xFF000000u
32527 #define PMU_REG_1P0A_TOG_RSVD1_SHIFT             24
32528 #define PMU_REG_1P0A_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK)
32529 /* REG_1P0D Bit Fields */
32530 #define PMU_REG_1P0D_ENABLE_LINREG_MASK          0x1u
32531 #define PMU_REG_1P0D_ENABLE_LINREG_SHIFT         0
32532 #define PMU_REG_1P0D_ENABLE_BO_MASK              0x2u
32533 #define PMU_REG_1P0D_ENABLE_BO_SHIFT             1
32534 #define PMU_REG_1P0D_ENABLE_ILIMIT_MASK          0x4u
32535 #define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT         2
32536 #define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK        0x8u
32537 #define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT       3
32538 #define PMU_REG_1P0D_BO_OFFSET_MASK              0x70u
32539 #define PMU_REG_1P0D_BO_OFFSET_SHIFT             4
32540 #define PMU_REG_1P0D_BO_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK)
32541 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK       0x80u
32542 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT      7
32543 #define PMU_REG_1P0D_OUTPUT_TRG_MASK             0x1F00u
32544 #define PMU_REG_1P0D_OUTPUT_TRG_SHIFT            8
32545 #define PMU_REG_1P0D_OUTPUT_TRG(x)               (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK)
32546 #define PMU_REG_1P0D_RSVD0_MASK                  0xE000u
32547 #define PMU_REG_1P0D_RSVD0_SHIFT                 13
32548 #define PMU_REG_1P0D_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK)
32549 #define PMU_REG_1P0D_BO_MASK                     0x10000u
32550 #define PMU_REG_1P0D_BO_SHIFT                    16
32551 #define PMU_REG_1P0D_OK_MASK                     0x20000u
32552 #define PMU_REG_1P0D_OK_SHIFT                    17
32553 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK     0x40000u
32554 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT    18
32555 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK     0x80000u
32556 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT    19
32557 #define PMU_REG_1P0D_REG_TEST_MASK               0xF00000u
32558 #define PMU_REG_1P0D_REG_TEST_SHIFT              20
32559 #define PMU_REG_1P0D_REG_TEST(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK)
32560 #define PMU_REG_1P0D_RSVD1_MASK                  0x7F000000u
32561 #define PMU_REG_1P0D_RSVD1_SHIFT                 24
32562 #define PMU_REG_1P0D_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK)
32563 #define PMU_REG_1P0D_OVERRIDE_MASK               0x80000000u
32564 #define PMU_REG_1P0D_OVERRIDE_SHIFT              31
32565 /* REG_1P0D_SET Bit Fields */
32566 #define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK      0x1u
32567 #define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT     0
32568 #define PMU_REG_1P0D_SET_ENABLE_BO_MASK          0x2u
32569 #define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT         1
32570 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK      0x4u
32571 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT     2
32572 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK    0x8u
32573 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT   3
32574 #define PMU_REG_1P0D_SET_BO_OFFSET_MASK          0x70u
32575 #define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT         4
32576 #define PMU_REG_1P0D_SET_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK)
32577 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK   0x80u
32578 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT  7
32579 #define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK         0x1F00u
32580 #define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT        8
32581 #define PMU_REG_1P0D_SET_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK)
32582 #define PMU_REG_1P0D_SET_RSVD0_MASK              0xE000u
32583 #define PMU_REG_1P0D_SET_RSVD0_SHIFT             13
32584 #define PMU_REG_1P0D_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK)
32585 #define PMU_REG_1P0D_SET_BO_MASK                 0x10000u
32586 #define PMU_REG_1P0D_SET_BO_SHIFT                16
32587 #define PMU_REG_1P0D_SET_OK_MASK                 0x20000u
32588 #define PMU_REG_1P0D_SET_OK_SHIFT                17
32589 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
32590 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18
32591 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u
32592 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19
32593 #define PMU_REG_1P0D_SET_REG_TEST_MASK           0xF00000u
32594 #define PMU_REG_1P0D_SET_REG_TEST_SHIFT          20
32595 #define PMU_REG_1P0D_SET_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK)
32596 #define PMU_REG_1P0D_SET_RSVD1_MASK              0x7F000000u
32597 #define PMU_REG_1P0D_SET_RSVD1_SHIFT             24
32598 #define PMU_REG_1P0D_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK)
32599 #define PMU_REG_1P0D_SET_OVERRIDE_MASK           0x80000000u
32600 #define PMU_REG_1P0D_SET_OVERRIDE_SHIFT          31
32601 /* REG_1P0D_CLR Bit Fields */
32602 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK      0x1u
32603 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT     0
32604 #define PMU_REG_1P0D_CLR_ENABLE_BO_MASK          0x2u
32605 #define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT         1
32606 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK      0x4u
32607 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT     2
32608 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK    0x8u
32609 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT   3
32610 #define PMU_REG_1P0D_CLR_BO_OFFSET_MASK          0x70u
32611 #define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT         4
32612 #define PMU_REG_1P0D_CLR_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK)
32613 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK   0x80u
32614 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT  7
32615 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK         0x1F00u
32616 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT        8
32617 #define PMU_REG_1P0D_CLR_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK)
32618 #define PMU_REG_1P0D_CLR_RSVD0_MASK              0xE000u
32619 #define PMU_REG_1P0D_CLR_RSVD0_SHIFT             13
32620 #define PMU_REG_1P0D_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK)
32621 #define PMU_REG_1P0D_CLR_BO_MASK                 0x10000u
32622 #define PMU_REG_1P0D_CLR_BO_SHIFT                16
32623 #define PMU_REG_1P0D_CLR_OK_MASK                 0x20000u
32624 #define PMU_REG_1P0D_CLR_OK_SHIFT                17
32625 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
32626 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18
32627 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
32628 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19
32629 #define PMU_REG_1P0D_CLR_REG_TEST_MASK           0xF00000u
32630 #define PMU_REG_1P0D_CLR_REG_TEST_SHIFT          20
32631 #define PMU_REG_1P0D_CLR_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK)
32632 #define PMU_REG_1P0D_CLR_RSVD1_MASK              0x7F000000u
32633 #define PMU_REG_1P0D_CLR_RSVD1_SHIFT             24
32634 #define PMU_REG_1P0D_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK)
32635 #define PMU_REG_1P0D_CLR_OVERRIDE_MASK           0x80000000u
32636 #define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT          31
32637 /* REG_1P0D_TOG Bit Fields */
32638 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK      0x1u
32639 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT     0
32640 #define PMU_REG_1P0D_TOG_ENABLE_BO_MASK          0x2u
32641 #define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT         1
32642 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK      0x4u
32643 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT     2
32644 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK    0x8u
32645 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT   3
32646 #define PMU_REG_1P0D_TOG_BO_OFFSET_MASK          0x70u
32647 #define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT         4
32648 #define PMU_REG_1P0D_TOG_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK)
32649 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK   0x80u
32650 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT  7
32651 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK         0x1F00u
32652 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT        8
32653 #define PMU_REG_1P0D_TOG_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK)
32654 #define PMU_REG_1P0D_TOG_RSVD0_MASK              0xE000u
32655 #define PMU_REG_1P0D_TOG_RSVD0_SHIFT             13
32656 #define PMU_REG_1P0D_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK)
32657 #define PMU_REG_1P0D_TOG_BO_MASK                 0x10000u
32658 #define PMU_REG_1P0D_TOG_BO_SHIFT                16
32659 #define PMU_REG_1P0D_TOG_OK_MASK                 0x20000u
32660 #define PMU_REG_1P0D_TOG_OK_SHIFT                17
32661 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
32662 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18
32663 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
32664 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19
32665 #define PMU_REG_1P0D_TOG_REG_TEST_MASK           0xF00000u
32666 #define PMU_REG_1P0D_TOG_REG_TEST_SHIFT          20
32667 #define PMU_REG_1P0D_TOG_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK)
32668 #define PMU_REG_1P0D_TOG_RSVD1_MASK              0x7F000000u
32669 #define PMU_REG_1P0D_TOG_RSVD1_SHIFT             24
32670 #define PMU_REG_1P0D_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK)
32671 #define PMU_REG_1P0D_TOG_OVERRIDE_MASK           0x80000000u
32672 #define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT          31
32673 /* REG_HSIC_1P2 Bit Fields */
32674 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK      0x1u
32675 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT     0
32676 #define PMU_REG_HSIC_1P2_ENABLE_BO_MASK          0x2u
32677 #define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT         1
32678 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK      0x4u
32679 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT     2
32680 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK    0x8u
32681 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT   3
32682 #define PMU_REG_HSIC_1P2_BO_OFFSET_MASK          0x70u
32683 #define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT         4
32684 #define PMU_REG_HSIC_1P2_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK)
32685 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK   0x80u
32686 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT  7
32687 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK         0x1F00u
32688 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT        8
32689 #define PMU_REG_HSIC_1P2_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK)
32690 #define PMU_REG_HSIC_1P2_RSVD0_MASK              0xE000u
32691 #define PMU_REG_HSIC_1P2_RSVD0_SHIFT             13
32692 #define PMU_REG_HSIC_1P2_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK)
32693 #define PMU_REG_HSIC_1P2_BO_MASK                 0x10000u
32694 #define PMU_REG_HSIC_1P2_BO_SHIFT                16
32695 #define PMU_REG_HSIC_1P2_OK_MASK                 0x20000u
32696 #define PMU_REG_HSIC_1P2_OK_SHIFT                17
32697 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u
32698 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18
32699 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u
32700 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19
32701 #define PMU_REG_HSIC_1P2_REG_TEST_MASK           0xF00000u
32702 #define PMU_REG_HSIC_1P2_REG_TEST_SHIFT          20
32703 #define PMU_REG_HSIC_1P2_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK)
32704 #define PMU_REG_HSIC_1P2_RSVD1_MASK              0x7F000000u
32705 #define PMU_REG_HSIC_1P2_RSVD1_SHIFT             24
32706 #define PMU_REG_HSIC_1P2_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK)
32707 #define PMU_REG_HSIC_1P2_OVERRIDE_MASK           0x80000000u
32708 #define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT          31
32709 /* REG_HSIC_1P2_SET Bit Fields */
32710 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK  0x1u
32711 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0
32712 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK      0x2u
32713 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT     1
32714 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK  0x4u
32715 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2
32716 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u
32717 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3
32718 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK      0x70u
32719 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT     4
32720 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK)
32721 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u
32722 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7
32723 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK     0x1F00u
32724 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT    8
32725 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK)
32726 #define PMU_REG_HSIC_1P2_SET_RSVD0_MASK          0xE000u
32727 #define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT         13
32728 #define PMU_REG_HSIC_1P2_SET_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK)
32729 #define PMU_REG_HSIC_1P2_SET_BO_MASK             0x10000u
32730 #define PMU_REG_HSIC_1P2_SET_BO_SHIFT            16
32731 #define PMU_REG_HSIC_1P2_SET_OK_MASK             0x20000u
32732 #define PMU_REG_HSIC_1P2_SET_OK_SHIFT            17
32733 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
32734 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18
32735 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u
32736 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19
32737 #define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK       0xF00000u
32738 #define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT      20
32739 #define PMU_REG_HSIC_1P2_SET_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK)
32740 #define PMU_REG_HSIC_1P2_SET_RSVD1_MASK          0x7F000000u
32741 #define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT         24
32742 #define PMU_REG_HSIC_1P2_SET_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK)
32743 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK       0x80000000u
32744 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT      31
32745 /* REG_HSIC_1P2_CLR Bit Fields */
32746 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK  0x1u
32747 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0
32748 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK      0x2u
32749 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT     1
32750 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK  0x4u
32751 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2
32752 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u
32753 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3
32754 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK      0x70u
32755 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT     4
32756 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK)
32757 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
32758 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7
32759 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK     0x1F00u
32760 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT    8
32761 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK)
32762 #define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK          0xE000u
32763 #define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT         13
32764 #define PMU_REG_HSIC_1P2_CLR_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK)
32765 #define PMU_REG_HSIC_1P2_CLR_BO_MASK             0x10000u
32766 #define PMU_REG_HSIC_1P2_CLR_BO_SHIFT            16
32767 #define PMU_REG_HSIC_1P2_CLR_OK_MASK             0x20000u
32768 #define PMU_REG_HSIC_1P2_CLR_OK_SHIFT            17
32769 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
32770 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18
32771 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
32772 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19
32773 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK       0xF00000u
32774 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT      20
32775 #define PMU_REG_HSIC_1P2_CLR_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK)
32776 #define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK          0x7F000000u
32777 #define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT         24
32778 #define PMU_REG_HSIC_1P2_CLR_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK)
32779 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK       0x80000000u
32780 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT      31
32781 /* REG_HSIC_1P2_TOG Bit Fields */
32782 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK  0x1u
32783 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0
32784 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK      0x2u
32785 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT     1
32786 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK  0x4u
32787 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2
32788 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u
32789 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3
32790 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK      0x70u
32791 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT     4
32792 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK)
32793 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
32794 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7
32795 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK     0x1F00u
32796 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT    8
32797 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK)
32798 #define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK          0xE000u
32799 #define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT         13
32800 #define PMU_REG_HSIC_1P2_TOG_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK)
32801 #define PMU_REG_HSIC_1P2_TOG_BO_MASK             0x10000u
32802 #define PMU_REG_HSIC_1P2_TOG_BO_SHIFT            16
32803 #define PMU_REG_HSIC_1P2_TOG_OK_MASK             0x20000u
32804 #define PMU_REG_HSIC_1P2_TOG_OK_SHIFT            17
32805 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
32806 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18
32807 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
32808 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19
32809 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK       0xF00000u
32810 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT      20
32811 #define PMU_REG_HSIC_1P2_TOG_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK)
32812 #define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK          0x7F000000u
32813 #define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT         24
32814 #define PMU_REG_HSIC_1P2_TOG_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK)
32815 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK       0x80000000u
32816 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT      31
32817 /* REG_LPSR_1P0 Bit Fields */
32818 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK      0x1u
32819 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT     0
32820 #define PMU_REG_LPSR_1P0_ENABLE_BO_MASK          0x2u
32821 #define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT         1
32822 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK      0x4u
32823 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT     2
32824 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK    0x8u
32825 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT   3
32826 #define PMU_REG_LPSR_1P0_BO_OFFSET_MASK          0x70u
32827 #define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT         4
32828 #define PMU_REG_LPSR_1P0_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK)
32829 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK   0x80u
32830 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT  7
32831 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK         0x1F00u
32832 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT        8
32833 #define PMU_REG_LPSR_1P0_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK)
32834 #define PMU_REG_LPSR_1P0_RSVD0_MASK              0xE000u
32835 #define PMU_REG_LPSR_1P0_RSVD0_SHIFT             13
32836 #define PMU_REG_LPSR_1P0_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK)
32837 #define PMU_REG_LPSR_1P0_BO_MASK                 0x10000u
32838 #define PMU_REG_LPSR_1P0_BO_SHIFT                16
32839 #define PMU_REG_LPSR_1P0_OK_MASK                 0x20000u
32840 #define PMU_REG_LPSR_1P0_OK_SHIFT                17
32841 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u
32842 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18
32843 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u
32844 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19
32845 #define PMU_REG_LPSR_1P0_REG_TEST_MASK           0xF00000u
32846 #define PMU_REG_LPSR_1P0_REG_TEST_SHIFT          20
32847 #define PMU_REG_LPSR_1P0_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK)
32848 #define PMU_REG_LPSR_1P0_RSVD1_MASK              0xFF000000u
32849 #define PMU_REG_LPSR_1P0_RSVD1_SHIFT             24
32850 #define PMU_REG_LPSR_1P0_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK)
32851 /* REG_LPSR_1P0_SET Bit Fields */
32852 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK  0x1u
32853 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0
32854 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK      0x2u
32855 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT     1
32856 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK  0x4u
32857 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2
32858 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u
32859 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3
32860 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK      0x70u
32861 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT     4
32862 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK)
32863 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u
32864 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7
32865 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK     0x1F00u
32866 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT    8
32867 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK)
32868 #define PMU_REG_LPSR_1P0_SET_RSVD0_MASK          0xE000u
32869 #define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT         13
32870 #define PMU_REG_LPSR_1P0_SET_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK)
32871 #define PMU_REG_LPSR_1P0_SET_BO_MASK             0x10000u
32872 #define PMU_REG_LPSR_1P0_SET_BO_SHIFT            16
32873 #define PMU_REG_LPSR_1P0_SET_OK_MASK             0x20000u
32874 #define PMU_REG_LPSR_1P0_SET_OK_SHIFT            17
32875 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
32876 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18
32877 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u
32878 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19
32879 #define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK       0xF00000u
32880 #define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT      20
32881 #define PMU_REG_LPSR_1P0_SET_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK)
32882 #define PMU_REG_LPSR_1P0_SET_RSVD1_MASK          0xFF000000u
32883 #define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT         24
32884 #define PMU_REG_LPSR_1P0_SET_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK)
32885 /* REG_LPSR_1P0_CLR Bit Fields */
32886 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK  0x1u
32887 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0
32888 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK      0x2u
32889 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT     1
32890 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK  0x4u
32891 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2
32892 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u
32893 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3
32894 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK      0x70u
32895 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT     4
32896 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK)
32897 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
32898 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7
32899 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK     0x1F00u
32900 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT    8
32901 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK)
32902 #define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK          0xE000u
32903 #define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT         13
32904 #define PMU_REG_LPSR_1P0_CLR_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK)
32905 #define PMU_REG_LPSR_1P0_CLR_BO_MASK             0x10000u
32906 #define PMU_REG_LPSR_1P0_CLR_BO_SHIFT            16
32907 #define PMU_REG_LPSR_1P0_CLR_OK_MASK             0x20000u
32908 #define PMU_REG_LPSR_1P0_CLR_OK_SHIFT            17
32909 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
32910 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18
32911 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
32912 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19
32913 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK       0xF00000u
32914 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT      20
32915 #define PMU_REG_LPSR_1P0_CLR_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK)
32916 #define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK          0xFF000000u
32917 #define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT         24
32918 #define PMU_REG_LPSR_1P0_CLR_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK)
32919 /* REG_LPSR_1P0_TOG Bit Fields */
32920 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK  0x1u
32921 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0
32922 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK      0x2u
32923 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT     1
32924 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK  0x4u
32925 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2
32926 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u
32927 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3
32928 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK      0x70u
32929 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT     4
32930 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK)
32931 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
32932 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7
32933 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK     0x1F00u
32934 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT    8
32935 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK)
32936 #define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK          0xE000u
32937 #define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT         13
32938 #define PMU_REG_LPSR_1P0_TOG_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK)
32939 #define PMU_REG_LPSR_1P0_TOG_BO_MASK             0x10000u
32940 #define PMU_REG_LPSR_1P0_TOG_BO_SHIFT            16
32941 #define PMU_REG_LPSR_1P0_TOG_OK_MASK             0x20000u
32942 #define PMU_REG_LPSR_1P0_TOG_OK_SHIFT            17
32943 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
32944 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18
32945 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
32946 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19
32947 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK       0xF00000u
32948 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT      20
32949 #define PMU_REG_LPSR_1P0_TOG_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK)
32950 #define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK          0xFF000000u
32951 #define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT         24
32952 #define PMU_REG_LPSR_1P0_TOG_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK)
32953 /* REF Bit Fields */
32954 #define PMU_REF_REFTOP_PWD_MASK                  0x1u
32955 #define PMU_REF_REFTOP_PWD_SHIFT                 0
32956 #define PMU_REF_REFTOP_PWDVBGUP_MASK             0x2u
32957 #define PMU_REF_REFTOP_PWDVBGUP_SHIFT            1
32958 #define PMU_REF_REFTOP_LOWPOWER_MASK             0x4u
32959 #define PMU_REF_REFTOP_LOWPOWER_SHIFT            2
32960 #define PMU_REF_REFTOP_SELFBIASOFF_MASK          0x8u
32961 #define PMU_REF_REFTOP_SELFBIASOFF_SHIFT         3
32962 #define PMU_REF_REFTOP_VBGADJ_MASK               0x70u
32963 #define PMU_REF_REFTOP_VBGADJ_SHIFT              4
32964 #define PMU_REF_REFTOP_VBGADJ(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK)
32965 #define PMU_REF_REFTOP_VBGUP_MASK                0x80u
32966 #define PMU_REF_REFTOP_VBGUP_SHIFT               7
32967 #define PMU_REF_REFTOP_BIAS_TST_MASK             0x300u
32968 #define PMU_REF_REFTOP_BIAS_TST_SHIFT            8
32969 #define PMU_REF_REFTOP_BIAS_TST(x)               (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK)
32970 #define PMU_REF_LPBG_SEL_MASK                    0x400u
32971 #define PMU_REF_LPBG_SEL_SHIFT                   10
32972 #define PMU_REF_LPBG_TEST_MASK                   0x800u
32973 #define PMU_REF_LPBG_TEST_SHIFT                  11
32974 #define PMU_REF_REFTOP_IBIAS_OFF_MASK            0x1000u
32975 #define PMU_REF_REFTOP_IBIAS_OFF_SHIFT           12
32976 #define PMU_REF_REFTOP_LINREGREF_EN_MASK         0x2000u
32977 #define PMU_REF_REFTOP_LINREGREF_EN_SHIFT        13
32978 #define PMU_REF_RSVD1_MASK                       0xFFFFC000u
32979 #define PMU_REF_RSVD1_SHIFT                      14
32980 #define PMU_REF_RSVD1(x)                         (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK)
32981 /* REF_SET Bit Fields */
32982 #define PMU_REF_SET_REFTOP_PWD_MASK              0x1u
32983 #define PMU_REF_SET_REFTOP_PWD_SHIFT             0
32984 #define PMU_REF_SET_REFTOP_PWDVBGUP_MASK         0x2u
32985 #define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT        1
32986 #define PMU_REF_SET_REFTOP_LOWPOWER_MASK         0x4u
32987 #define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT        2
32988 #define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK      0x8u
32989 #define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT     3
32990 #define PMU_REF_SET_REFTOP_VBGADJ_MASK           0x70u
32991 #define PMU_REF_SET_REFTOP_VBGADJ_SHIFT          4
32992 #define PMU_REF_SET_REFTOP_VBGADJ(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK)
32993 #define PMU_REF_SET_REFTOP_VBGUP_MASK            0x80u
32994 #define PMU_REF_SET_REFTOP_VBGUP_SHIFT           7
32995 #define PMU_REF_SET_REFTOP_BIAS_TST_MASK         0x300u
32996 #define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT        8
32997 #define PMU_REF_SET_REFTOP_BIAS_TST(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK)
32998 #define PMU_REF_SET_LPBG_SEL_MASK                0x400u
32999 #define PMU_REF_SET_LPBG_SEL_SHIFT               10
33000 #define PMU_REF_SET_LPBG_TEST_MASK               0x800u
33001 #define PMU_REF_SET_LPBG_TEST_SHIFT              11
33002 #define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK        0x1000u
33003 #define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT       12
33004 #define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK     0x2000u
33005 #define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT    13
33006 #define PMU_REF_SET_RSVD1_MASK                   0xFFFFC000u
33007 #define PMU_REF_SET_RSVD1_SHIFT                  14
33008 #define PMU_REF_SET_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK)
33009 /* REF_CLR Bit Fields */
33010 #define PMU_REF_CLR_REFTOP_PWD_MASK              0x1u
33011 #define PMU_REF_CLR_REFTOP_PWD_SHIFT             0
33012 #define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK         0x2u
33013 #define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT        1
33014 #define PMU_REF_CLR_REFTOP_LOWPOWER_MASK         0x4u
33015 #define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT        2
33016 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK      0x8u
33017 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT     3
33018 #define PMU_REF_CLR_REFTOP_VBGADJ_MASK           0x70u
33019 #define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT          4
33020 #define PMU_REF_CLR_REFTOP_VBGADJ(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK)
33021 #define PMU_REF_CLR_REFTOP_VBGUP_MASK            0x80u
33022 #define PMU_REF_CLR_REFTOP_VBGUP_SHIFT           7
33023 #define PMU_REF_CLR_REFTOP_BIAS_TST_MASK         0x300u
33024 #define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT        8
33025 #define PMU_REF_CLR_REFTOP_BIAS_TST(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK)
33026 #define PMU_REF_CLR_LPBG_SEL_MASK                0x400u
33027 #define PMU_REF_CLR_LPBG_SEL_SHIFT               10
33028 #define PMU_REF_CLR_LPBG_TEST_MASK               0x800u
33029 #define PMU_REF_CLR_LPBG_TEST_SHIFT              11
33030 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK        0x1000u
33031 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT       12
33032 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK     0x2000u
33033 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT    13
33034 #define PMU_REF_CLR_RSVD1_MASK                   0xFFFFC000u
33035 #define PMU_REF_CLR_RSVD1_SHIFT                  14
33036 #define PMU_REF_CLR_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK)
33037 /* REF_TOG Bit Fields */
33038 #define PMU_REF_TOG_REFTOP_PWD_MASK              0x1u
33039 #define PMU_REF_TOG_REFTOP_PWD_SHIFT             0
33040 #define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK         0x2u
33041 #define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT        1
33042 #define PMU_REF_TOG_REFTOP_LOWPOWER_MASK         0x4u
33043 #define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT        2
33044 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK      0x8u
33045 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT     3
33046 #define PMU_REF_TOG_REFTOP_VBGADJ_MASK           0x70u
33047 #define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT          4
33048 #define PMU_REF_TOG_REFTOP_VBGADJ(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK)
33049 #define PMU_REF_TOG_REFTOP_VBGUP_MASK            0x80u
33050 #define PMU_REF_TOG_REFTOP_VBGUP_SHIFT           7
33051 #define PMU_REF_TOG_REFTOP_BIAS_TST_MASK         0x300u
33052 #define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT        8
33053 #define PMU_REF_TOG_REFTOP_BIAS_TST(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK)
33054 #define PMU_REF_TOG_LPBG_SEL_MASK                0x400u
33055 #define PMU_REF_TOG_LPBG_SEL_SHIFT               10
33056 #define PMU_REF_TOG_LPBG_TEST_MASK               0x800u
33057 #define PMU_REF_TOG_LPBG_TEST_SHIFT              11
33058 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK        0x1000u
33059 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT       12
33060 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK     0x2000u
33061 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT    13
33062 #define PMU_REF_TOG_RSVD1_MASK                   0xFFFFC000u
33063 #define PMU_REF_TOG_RSVD1_SHIFT                  14
33064 #define PMU_REF_TOG_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK)
33065 /* LOWPWR_CTRL Bit Fields */
33066 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK    0x3u
33067 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT   0
33068 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x)      (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK)
33069 #define PMU_LOWPWR_CTRL_RSVD0_MASK               0xFCu
33070 #define PMU_LOWPWR_CTRL_RSVD0_SHIFT              2
33071 #define PMU_LOWPWR_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK)
33072 #define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK          0x100u
33073 #define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT         8
33074 #define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK          0x200u
33075 #define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT         9
33076 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK         0x400u
33077 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT        10
33078 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK     0x800u
33079 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT    11
33080 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK         0x1000u
33081 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT        12
33082 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK         0x2000u
33083 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT        13
33084 #define PMU_LOWPWR_CTRL_CONTROL0_MASK            0xFFC000u
33085 #define PMU_LOWPWR_CTRL_CONTROL0_SHIFT           14
33086 #define PMU_LOWPWR_CTRL_CONTROL0(x)              (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK)
33087 #define PMU_LOWPWR_CTRL_CONTROL1_MASK            0xFF000000u
33088 #define PMU_LOWPWR_CTRL_CONTROL1_SHIFT           24
33089 #define PMU_LOWPWR_CTRL_CONTROL1(x)              (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK)
33090 /* LOWPWR_CTRL_SET Bit Fields */
33091 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u
33092 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0
33093 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x)  (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK)
33094 #define PMU_LOWPWR_CTRL_SET_RSVD0_MASK           0xFCu
33095 #define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT          2
33096 #define PMU_LOWPWR_CTRL_SET_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK)
33097 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK      0x100u
33098 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT     8
33099 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK      0x200u
33100 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT     9
33101 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK     0x400u
33102 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT    10
33103 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
33104 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
33105 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK     0x1000u
33106 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT    12
33107 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK     0x2000u
33108 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT    13
33109 #define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK        0xFFC000u
33110 #define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT       14
33111 #define PMU_LOWPWR_CTRL_SET_CONTROL0(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK)
33112 #define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK        0xFF000000u
33113 #define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT       24
33114 #define PMU_LOWPWR_CTRL_SET_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK)
33115 /* LOWPWR_CTRL_CLR Bit Fields */
33116 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u
33117 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0
33118 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x)  (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK)
33119 #define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK           0xFCu
33120 #define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT          2
33121 #define PMU_LOWPWR_CTRL_CLR_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK)
33122 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK      0x100u
33123 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT     8
33124 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK      0x200u
33125 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT     9
33126 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK     0x400u
33127 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT    10
33128 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
33129 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
33130 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK     0x1000u
33131 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT    12
33132 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK     0x2000u
33133 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT    13
33134 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK        0xFFC000u
33135 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT       14
33136 #define PMU_LOWPWR_CTRL_CLR_CONTROL0(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK)
33137 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK        0xFF000000u
33138 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT       24
33139 #define PMU_LOWPWR_CTRL_CLR_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK)
33140 /* LOWPWR_CTRL_TOG Bit Fields */
33141 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u
33142 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0
33143 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x)  (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK)
33144 #define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK           0xFCu
33145 #define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT          2
33146 #define PMU_LOWPWR_CTRL_TOG_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK)
33147 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK      0x100u
33148 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT     8
33149 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK      0x200u
33150 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT     9
33151 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK     0x400u
33152 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT    10
33153 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
33154 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
33155 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK     0x1000u
33156 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT    12
33157 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK     0x2000u
33158 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT    13
33159 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK        0xFFC000u
33160 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT       14
33161 #define PMU_LOWPWR_CTRL_TOG_CONTROL0(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK)
33162 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK        0xFF000000u
33163 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT       24
33164 #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
33165 
33166 /*!
33167  * @}
33168  */ /* end of group PMU_Register_Masks */
33169 
33170 /* PMU - Peripheral instance base addresses */
33171 /** Peripheral PMU base address */
33172 #define PMU_BASE                                 (0x30360000u)
33173 /** Peripheral PMU base pointer */
33174 #define PMU                                      ((PMU_Type *)PMU_BASE)
33175 #define PMU_BASE_PTR                             (PMU)
33176 /** Array initializer of PMU peripheral base addresses */
33177 #define PMU_BASE_ADDRS                           { PMU_BASE }
33178 /** Array initializer of PMU peripheral base pointers */
33179 #define PMU_BASE_PTRS                            { PMU }
33180 /* ----------------------------------------------------------------------------
33181    -- PMU - Register accessor macros
33182    ---------------------------------------------------------------------------- */
33183 
33184 /*!
33185  * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros
33186  * @{
33187  */
33188 
33189 
33190 /* PMU - Register instance definitions */
33191 /* PMU */
33192 #define PMU_REG_1P0A                             PMU_REG_1P0A_REG(PMU_BASE_PTR)
33193 #define PMU_REG_1P0A_SET                         PMU_REG_1P0A_SET_REG(PMU_BASE_PTR)
33194 #define PMU_REG_1P0A_CLR                         PMU_REG_1P0A_CLR_REG(PMU_BASE_PTR)
33195 #define PMU_REG_1P0A_TOG                         PMU_REG_1P0A_TOG_REG(PMU_BASE_PTR)
33196 #define PMU_REG_1P0D                             PMU_REG_1P0D_REG(PMU_BASE_PTR)
33197 #define PMU_REG_1P0D_SET                         PMU_REG_1P0D_SET_REG(PMU_BASE_PTR)
33198 #define PMU_REG_1P0D_CLR                         PMU_REG_1P0D_CLR_REG(PMU_BASE_PTR)
33199 #define PMU_REG_1P0D_TOG                         PMU_REG_1P0D_TOG_REG(PMU_BASE_PTR)
33200 #define PMU_REG_HSIC_1P2                         PMU_REG_HSIC_1P2_REG(PMU_BASE_PTR)
33201 #define PMU_REG_HSIC_1P2_SET                     PMU_REG_HSIC_1P2_SET_REG(PMU_BASE_PTR)
33202 #define PMU_REG_HSIC_1P2_CLR                     PMU_REG_HSIC_1P2_CLR_REG(PMU_BASE_PTR)
33203 #define PMU_REG_HSIC_1P2_TOG                     PMU_REG_HSIC_1P2_TOG_REG(PMU_BASE_PTR)
33204 #define PMU_REG_LPSR_1P0                         PMU_REG_LPSR_1P0_REG(PMU_BASE_PTR)
33205 #define PMU_REG_LPSR_1P0_SET                     PMU_REG_LPSR_1P0_SET_REG(PMU_BASE_PTR)
33206 #define PMU_REG_LPSR_1P0_CLR                     PMU_REG_LPSR_1P0_CLR_REG(PMU_BASE_PTR)
33207 #define PMU_REG_LPSR_1P0_TOG                     PMU_REG_LPSR_1P0_TOG_REG(PMU_BASE_PTR)
33208 #define PMU_REF                                  PMU_REF_REG(PMU_BASE_PTR)
33209 #define PMU_REF_SET                              PMU_REF_SET_REG(PMU_BASE_PTR)
33210 #define PMU_REF_CLR                              PMU_REF_CLR_REG(PMU_BASE_PTR)
33211 #define PMU_REF_TOG                              PMU_REF_TOG_REG(PMU_BASE_PTR)
33212 #define PMU_LOWPWR_CTRL                          PMU_LOWPWR_CTRL_REG(PMU_BASE_PTR)
33213 #define PMU_LOWPWR_CTRL_SET                      PMU_LOWPWR_CTRL_SET_REG(PMU_BASE_PTR)
33214 #define PMU_LOWPWR_CTRL_CLR                      PMU_LOWPWR_CTRL_CLR_REG(PMU_BASE_PTR)
33215 #define PMU_LOWPWR_CTRL_TOG                      PMU_LOWPWR_CTRL_TOG_REG(PMU_BASE_PTR)
33216 /*!
33217  * @}
33218  */ /* end of group PMU_Register_Accessor_Macros */
33219 
33220 
33221 /*!
33222  * @}
33223  */ /* end of group PMU_Peripheral */
33224 
33225 /* ----------------------------------------------------------------------------
33226    -- PWM Peripheral Access Layer
33227    ---------------------------------------------------------------------------- */
33228 
33229 /*!
33230  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
33231  * @{
33232  */
33233 
33234 /** PWM - Register Layout Typedef */
33235 typedef struct {
33236   __IO  uint32_t PWMCR;                                  /**< PWM Control Register, offset: 0x0 */
33237   __IO  uint32_t PWMSR;                                  /**< PWM Status Register, offset: 0x4 */
33238   __IO  uint32_t PWMIR;                                  /**< PWM Interrupt Register, offset: 0x8 */
33239   __IO  uint32_t PWMSAR;                                 /**< PWM Sample Register, offset: 0xC */
33240   __IO  uint32_t PWMPR;                                  /**< PWM Period Register, offset: 0x10 */
33241   __I   uint32_t PWMCNR;                                 /**< PWM Counter Register, offset: 0x14 */
33242 } PWM_Type, *PWM_MemMapPtr;
33243 /* ----------------------------------------------------------------------------
33244    -- PWM - Register accessor macros
33245    ---------------------------------------------------------------------------- */
33246 
33247 /*!
33248  * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros
33249  * @{
33250  */
33251 
33252 
33253 /* PWM - Register accessors */
33254 #define PWM_PWMCR_REG(base)                      ((base)->PWMCR)
33255 #define PWM_PWMSR_REG(base)                      ((base)->PWMSR)
33256 #define PWM_PWMIR_REG(base)                      ((base)->PWMIR)
33257 #define PWM_PWMSAR_REG(base)                     ((base)->PWMSAR)
33258 #define PWM_PWMPR_REG(base)                      ((base)->PWMPR)
33259 #define PWM_PWMCNR_REG(base)                     ((base)->PWMCNR)
33260 
33261 /*!
33262  * @}
33263  */ /* end of group PWM_Register_Accessor_Macros */
33264 /* ----------------------------------------------------------------------------
33265    -- PWM Register Masks
33266    ---------------------------------------------------------------------------- */
33267 
33268 /*!
33269  * @addtogroup PWM_Register_Masks PWM Register Masks
33270  * @{
33271  */
33272 
33273 /* PWMCR Bit Fields */
33274 #define PWM_PWMCR_EN_MASK                        0x1u
33275 #define PWM_PWMCR_EN_SHIFT                       0
33276 #define PWM_PWMCR_REPEAT_MASK                    0x6u
33277 #define PWM_PWMCR_REPEAT_SHIFT                   1
33278 #define PWM_PWMCR_REPEAT(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_REPEAT_SHIFT))&PWM_PWMCR_REPEAT_MASK)
33279 #define PWM_PWMCR_SWR_MASK                       0x8u
33280 #define PWM_PWMCR_SWR_SHIFT                      3
33281 #define PWM_PWMCR_PRESCALER_MASK                 0xFFF0u
33282 #define PWM_PWMCR_PRESCALER_SHIFT                4
33283 #define PWM_PWMCR_PRESCALER(x)                   (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_PRESCALER_SHIFT))&PWM_PWMCR_PRESCALER_MASK)
33284 #define PWM_PWMCR_CLKSRC_MASK                    0x30000u
33285 #define PWM_PWMCR_CLKSRC_SHIFT                   16
33286 #define PWM_PWMCR_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_CLKSRC_SHIFT))&PWM_PWMCR_CLKSRC_MASK)
33287 #define PWM_PWMCR_POUTC_MASK                     0xC0000u
33288 #define PWM_PWMCR_POUTC_SHIFT                    18
33289 #define PWM_PWMCR_POUTC(x)                       (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_POUTC_SHIFT))&PWM_PWMCR_POUTC_MASK)
33290 #define PWM_PWMCR_HCTR_MASK                      0x100000u
33291 #define PWM_PWMCR_HCTR_SHIFT                     20
33292 #define PWM_PWMCR_BCTR_MASK                      0x200000u
33293 #define PWM_PWMCR_BCTR_SHIFT                     21
33294 #define PWM_PWMCR_DBGEN_MASK                     0x400000u
33295 #define PWM_PWMCR_DBGEN_SHIFT                    22
33296 #define PWM_PWMCR_WAITEN_MASK                    0x800000u
33297 #define PWM_PWMCR_WAITEN_SHIFT                   23
33298 #define PWM_PWMCR_DOZEN_MASK                     0x1000000u
33299 #define PWM_PWMCR_DOZEN_SHIFT                    24
33300 #define PWM_PWMCR_STOPEN_MASK                    0x2000000u
33301 #define PWM_PWMCR_STOPEN_SHIFT                   25
33302 #define PWM_PWMCR_FWM_MASK                       0xC000000u
33303 #define PWM_PWMCR_FWM_SHIFT                      26
33304 #define PWM_PWMCR_FWM(x)                         (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_FWM_SHIFT))&PWM_PWMCR_FWM_MASK)
33305 /* PWMSR Bit Fields */
33306 #define PWM_PWMSR_FIFOAV_MASK                    0x7u
33307 #define PWM_PWMSR_FIFOAV_SHIFT                   0
33308 #define PWM_PWMSR_FIFOAV(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMSR_FIFOAV_SHIFT))&PWM_PWMSR_FIFOAV_MASK)
33309 #define PWM_PWMSR_FE_MASK                        0x8u
33310 #define PWM_PWMSR_FE_SHIFT                       3
33311 #define PWM_PWMSR_ROV_MASK                       0x10u
33312 #define PWM_PWMSR_ROV_SHIFT                      4
33313 #define PWM_PWMSR_CMP_MASK                       0x20u
33314 #define PWM_PWMSR_CMP_SHIFT                      5
33315 #define PWM_PWMSR_FWE_MASK                       0x40u
33316 #define PWM_PWMSR_FWE_SHIFT                      6
33317 /* PWMIR Bit Fields */
33318 #define PWM_PWMIR_FIE_MASK                       0x1u
33319 #define PWM_PWMIR_FIE_SHIFT                      0
33320 #define PWM_PWMIR_RIE_MASK                       0x2u
33321 #define PWM_PWMIR_RIE_SHIFT                      1
33322 #define PWM_PWMIR_CIE_MASK                       0x4u
33323 #define PWM_PWMIR_CIE_SHIFT                      2
33324 /* PWMSAR Bit Fields */
33325 #define PWM_PWMSAR_SAMPLE_MASK                   0xFFFFu
33326 #define PWM_PWMSAR_SAMPLE_SHIFT                  0
33327 #define PWM_PWMSAR_SAMPLE(x)                     (((uint32_t)(((uint32_t)(x))<<PWM_PWMSAR_SAMPLE_SHIFT))&PWM_PWMSAR_SAMPLE_MASK)
33328 /* PWMPR Bit Fields */
33329 #define PWM_PWMPR_PERIOD_MASK                    0xFFFFu
33330 #define PWM_PWMPR_PERIOD_SHIFT                   0
33331 #define PWM_PWMPR_PERIOD(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMPR_PERIOD_SHIFT))&PWM_PWMPR_PERIOD_MASK)
33332 /* PWMCNR Bit Fields */
33333 #define PWM_PWMCNR_COUNT_MASK                    0xFFFFu
33334 #define PWM_PWMCNR_COUNT_SHIFT                   0
33335 #define PWM_PWMCNR_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMCNR_COUNT_SHIFT))&PWM_PWMCNR_COUNT_MASK)
33336 
33337 /*!
33338  * @}
33339  */ /* end of group PWM_Register_Masks */
33340 
33341 /* PWM - Peripheral instance base addresses */
33342 /** Peripheral PWM1 base address */
33343 #define PWM1_BASE                                (0x30660000u)
33344 /** Peripheral PWM1 base pointer */
33345 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
33346 #define PWM1_BASE_PTR                            (PWM1)
33347 /** Peripheral PWM2 base address */
33348 #define PWM2_BASE                                (0x30670000u)
33349 /** Peripheral PWM2 base pointer */
33350 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
33351 #define PWM2_BASE_PTR                            (PWM2)
33352 /** Peripheral PWM3 base address */
33353 #define PWM3_BASE                                (0x30680000u)
33354 /** Peripheral PWM3 base pointer */
33355 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
33356 #define PWM3_BASE_PTR                            (PWM3)
33357 /** Peripheral PWM4 base address */
33358 #define PWM4_BASE                                (0x30690000u)
33359 /** Peripheral PWM4 base pointer */
33360 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
33361 #define PWM4_BASE_PTR                            (PWM4)
33362 /** Array initializer of PWM peripheral base addresses */
33363 #define PWM_BASE_ADDRS                           { PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
33364 /** Array initializer of PWM peripheral base pointers */
33365 #define PWM_BASE_PTRS                            { PWM1, PWM2, PWM3, PWM4 }
33366 /** Interrupt vectors for the PWM peripheral type */
33367 #define PWM_IRQS                                 { PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn }
33368 /* ----------------------------------------------------------------------------
33369    -- PWM - Register accessor macros
33370    ---------------------------------------------------------------------------- */
33371 
33372 /*!
33373  * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros
33374  * @{
33375  */
33376 
33377 
33378 /* PWM - Register instance definitions */
33379 /* PWM1 */
33380 #define PWM1_PWMCR                               PWM_PWMCR_REG(PWM1_BASE_PTR)
33381 #define PWM1_PWMSR                               PWM_PWMSR_REG(PWM1_BASE_PTR)
33382 #define PWM1_PWMIR                               PWM_PWMIR_REG(PWM1_BASE_PTR)
33383 #define PWM1_PWMSAR                              PWM_PWMSAR_REG(PWM1_BASE_PTR)
33384 #define PWM1_PWMPR                               PWM_PWMPR_REG(PWM1_BASE_PTR)
33385 #define PWM1_PWMCNR                              PWM_PWMCNR_REG(PWM1_BASE_PTR)
33386 /* PWM2 */
33387 #define PWM2_PWMCR                               PWM_PWMCR_REG(PWM2_BASE_PTR)
33388 #define PWM2_PWMSR                               PWM_PWMSR_REG(PWM2_BASE_PTR)
33389 #define PWM2_PWMIR                               PWM_PWMIR_REG(PWM2_BASE_PTR)
33390 #define PWM2_PWMSAR                              PWM_PWMSAR_REG(PWM2_BASE_PTR)
33391 #define PWM2_PWMPR                               PWM_PWMPR_REG(PWM2_BASE_PTR)
33392 #define PWM2_PWMCNR                              PWM_PWMCNR_REG(PWM2_BASE_PTR)
33393 /* PWM3 */
33394 #define PWM3_PWMCR                               PWM_PWMCR_REG(PWM3_BASE_PTR)
33395 #define PWM3_PWMSR                               PWM_PWMSR_REG(PWM3_BASE_PTR)
33396 #define PWM3_PWMIR                               PWM_PWMIR_REG(PWM3_BASE_PTR)
33397 #define PWM3_PWMSAR                              PWM_PWMSAR_REG(PWM3_BASE_PTR)
33398 #define PWM3_PWMPR                               PWM_PWMPR_REG(PWM3_BASE_PTR)
33399 #define PWM3_PWMCNR                              PWM_PWMCNR_REG(PWM3_BASE_PTR)
33400 /* PWM4 */
33401 #define PWM4_PWMCR                               PWM_PWMCR_REG(PWM4_BASE_PTR)
33402 #define PWM4_PWMSR                               PWM_PWMSR_REG(PWM4_BASE_PTR)
33403 #define PWM4_PWMIR                               PWM_PWMIR_REG(PWM4_BASE_PTR)
33404 #define PWM4_PWMSAR                              PWM_PWMSAR_REG(PWM4_BASE_PTR)
33405 #define PWM4_PWMPR                               PWM_PWMPR_REG(PWM4_BASE_PTR)
33406 #define PWM4_PWMCNR                              PWM_PWMCNR_REG(PWM4_BASE_PTR)
33407 /*!
33408  * @}
33409  */ /* end of group PWM_Register_Accessor_Macros */
33410 
33411 
33412 /*!
33413  * @}
33414  */ /* end of group PWM_Peripheral */
33415 
33416 /* ----------------------------------------------------------------------------
33417    -- PXP Peripheral Access Layer
33418    ---------------------------------------------------------------------------- */
33419 
33420 /*!
33421  * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
33422  * @{
33423  */
33424 
33425 /** PXP - Register Layout Typedef */
33426 typedef struct {
33427   __IO  uint32_t HW_PXP_CTRL;                            /**< Control Register 0, offset: 0x0 */
33428   uint8_t RESERVED_0[12];
33429   __IO  uint32_t HW_PXP_STAT;                            /**< Status Register, offset: 0x10 */
33430   uint8_t RESERVED_1[12];
33431   __IO  uint32_t HW_PXP_OUT_CTRL;                        /**< Output Buffer Control Register, offset: 0x20 */
33432   uint8_t RESERVED_2[12];
33433   __IO  uint32_t HW_PXP_OUT_BUF;                         /**< Output Frame Buffer Pointer, offset: 0x30 */
33434   uint8_t RESERVED_3[12];
33435   __IO  uint32_t HW_PXP_OUT_BUF2;                        /**< Output Frame Buffer Pointer #2, offset: 0x40 */
33436   uint8_t RESERVED_4[12];
33437   __IO  uint32_t HW_PXP_OUT_PITCH;                       /**< Output Buffer Pitch, offset: 0x50 */
33438   uint8_t RESERVED_5[12];
33439   __IO  uint32_t HW_PXP_OUT_LRC;                         /**< Output Surface Lower Right Coordinate, offset: 0x60 */
33440   uint8_t RESERVED_6[12];
33441   __IO  uint32_t HW_PXP_OUT_PS_ULC;                      /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
33442   uint8_t RESERVED_7[12];
33443   __IO  uint32_t HW_PXP_OUT_PS_LRC;                      /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
33444   uint8_t RESERVED_8[12];
33445   __IO  uint32_t HW_PXP_OUT_AS_ULC;                      /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
33446   uint8_t RESERVED_9[12];
33447   __IO  uint32_t HW_PXP_OUT_AS_LRC;                      /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
33448   uint8_t RESERVED_10[12];
33449   __IO  uint32_t HW_PXP_PS_CTRL;                         /**< Processed Surface (PS) Control Register, offset: 0xB0 */
33450   uint8_t RESERVED_11[12];
33451   __IO  uint32_t HW_PXP_PS_BUF;                          /**< PS Input Buffer Address, offset: 0xC0 */
33452   uint8_t RESERVED_12[12];
33453   __IO  uint32_t HW_PXP_PS_UBUF;                         /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
33454   uint8_t RESERVED_13[12];
33455   __IO  uint32_t HW_PXP_PS_VBUF;                         /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
33456   uint8_t RESERVED_14[12];
33457   __IO  uint32_t HW_PXP_PS_PITCH;                        /**< Processed Surface Pitch, offset: 0xF0 */
33458   uint8_t RESERVED_15[12];
33459   __IO  uint32_t HW_PXP_PS_BACKGROUND_0;                 /**< PS Background Color, offset: 0x100 */
33460   uint8_t RESERVED_16[12];
33461   __IO  uint32_t HW_PXP_PS_SCALE;                        /**< PS Scale Factor Register, offset: 0x110 */
33462   uint8_t RESERVED_17[12];
33463   __IO  uint32_t HW_PXP_PS_OFFSET;                       /**< PS Scale Offset Register, offset: 0x120 */
33464   uint8_t RESERVED_18[12];
33465   __IO  uint32_t HW_PXP_PS_CLRKEYLOW_0;                  /**< PS Color Key Low, offset: 0x130 */
33466   uint8_t RESERVED_19[12];
33467   __IO  uint32_t HW_PXP_PS_CLRKEYHIGH_0;                 /**< PS Color Key High, offset: 0x140 */
33468   uint8_t RESERVED_20[12];
33469   __IO  uint32_t HW_PXP_AS_CTRL;                         /**< Alpha Surface Control, offset: 0x150 */
33470   uint8_t RESERVED_21[12];
33471   __IO  uint32_t HW_PXP_AS_BUF;                          /**< Alpha Surface Buffer Pointer, offset: 0x160 */
33472   uint8_t RESERVED_22[12];
33473   __IO  uint32_t HW_PXP_AS_PITCH;                        /**< Alpha Surface Pitch, offset: 0x170 */
33474   uint8_t RESERVED_23[12];
33475   __IO  uint32_t HW_PXP_AS_CLRKEYLOW_0;                  /**< Overlay Color Key Low, offset: 0x180 */
33476   uint8_t RESERVED_24[12];
33477   __IO  uint32_t HW_PXP_AS_CLRKEYHIGH_0;                 /**< Overlay Color Key High, offset: 0x190 */
33478   uint8_t RESERVED_25[12];
33479   __IO  uint32_t HW_PXP_CSC1_COEF0;                      /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
33480   uint8_t RESERVED_26[12];
33481   __IO  uint32_t HW_PXP_CSC1_COEF1;                      /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
33482   uint8_t RESERVED_27[12];
33483   __IO  uint32_t HW_PXP_CSC1_COEF2;                      /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
33484   uint8_t RESERVED_28[12];
33485   __IO  uint32_t HW_PXP_CSC2_CTRL;                       /**< Color Space Conversion Control Register., offset: 0x1D0 */
33486   uint8_t RESERVED_29[12];
33487   __IO  uint32_t HW_PXP_CSC2_COEF0;                      /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */
33488   uint8_t RESERVED_30[12];
33489   __IO  uint32_t HW_PXP_CSC2_COEF1;                      /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */
33490   uint8_t RESERVED_31[12];
33491   __IO  uint32_t HW_PXP_CSC2_COEF2;                      /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */
33492   uint8_t RESERVED_32[12];
33493   __IO  uint32_t HW_PXP_CSC2_COEF3;                      /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */
33494   uint8_t RESERVED_33[12];
33495   __IO  uint32_t HW_PXP_CSC2_COEF4;                      /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */
33496   uint8_t RESERVED_34[12];
33497   __IO  uint32_t HW_PXP_CSC2_COEF5;                      /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */
33498   uint8_t RESERVED_35[12];
33499   __IO  uint32_t HW_PXP_LUT_CTRL;                        /**< Lookup Table Control Register., offset: 0x240 */
33500   uint8_t RESERVED_36[12];
33501   __IO  uint32_t HW_PXP_LUT_ADDR;                        /**< Lookup Table Control Register., offset: 0x250 */
33502   uint8_t RESERVED_37[12];
33503   __IO  uint32_t HW_PXP_LUT_DATA;                        /**< Lookup Table Data Register., offset: 0x260 */
33504   uint8_t RESERVED_38[12];
33505   __IO  uint32_t HW_PXP_LUT_EXTMEM;                      /**< Lookup Table External Memory Address Register., offset: 0x270 */
33506   uint8_t RESERVED_39[12];
33507   __IO  uint32_t HW_PXP_CFA;                             /**< Color Filter Array Register., offset: 0x280 */
33508   uint8_t RESERVED_40[12];
33509   __IO  uint32_t HW_PXP_ALPHA_A_CTRL;                    /**< PXP Alpha Engine A Control Register., offset: 0x290 */
33510   uint8_t RESERVED_41[12];
33511   __IO  uint32_t HW_PXP_ALPHA_B_CTRL;                    /**< PXP Alpha Engine B Control Register., offset: 0x2A0 */
33512   uint8_t RESERVED_42[12];
33513   __IO  uint32_t HW_PXP_ALPHA_B_CTRL_1;                  /**< , offset: 0x2B0 */
33514   uint8_t RESERVED_43[12];
33515   __IO  uint32_t HW_PXP_PS_BACKGROUND_1;                 /**< PS Background Color 1, offset: 0x2C0 */
33516   uint8_t RESERVED_44[12];
33517   __IO  uint32_t HW_PXP_PS_CLRKEYLOW_1;                  /**< PS Color Key Low 1, offset: 0x2D0 */
33518   uint8_t RESERVED_45[12];
33519   __IO  uint32_t HW_PXP_PS_CLRKEYHIGH_1;                 /**< PS Color Key High 1, offset: 0x2E0 */
33520   uint8_t RESERVED_46[12];
33521   __IO  uint32_t HW_PXP_AS_CLRKEYLOW_1;                  /**< Overlay Color Key Low, offset: 0x2F0 */
33522   uint8_t RESERVED_47[12];
33523   __IO  uint32_t HW_PXP_AS_CLRKEYHIGH_1;                 /**< Overlay Color Key High, offset: 0x300 */
33524   uint8_t RESERVED_48[12];
33525   __IO  uint32_t HW_PXP_CTRL2;                           /**< Control Register 2, offset: 0x310 */
33526   uint8_t RESERVED_49[12];
33527   __IO  uint32_t HW_PXP_POWER_REG0;                      /**< PXP Power Control Register., offset: 0x320 */
33528   uint8_t RESERVED_50[12];
33529   __IO  uint32_t HW_PXP_POWER_REG1;                      /**< PXP Power Control Register 1., offset: 0x330 */
33530   uint8_t RESERVED_51[12];
33531   __IO  uint32_t HW_PXP_DATA_PATH_CTRL0;                 /**< , offset: 0x340 */
33532   uint8_t RESERVED_52[12];
33533   __IO  uint32_t HW_PXP_DATA_PATH_CTRL1;                 /**< , offset: 0x350 */
33534   uint8_t RESERVED_53[12];
33535   __IO  uint32_t HW_PXP_INIT_MEM_CTRL;                   /**< Initialize memory buffer control Register, offset: 0x360 */
33536   uint8_t RESERVED_54[12];
33537   __IO  uint32_t HW_PXP_INIT_MEM_DATA;                   /**< Write data Register, offset: 0x370 */
33538   uint8_t RESERVED_55[12];
33539   __IO  uint32_t HW_PXP_INIT_MEM_DATA_HIGH;              /**< Write data Register, offset: 0x380 */
33540   uint8_t RESERVED_56[12];
33541   __IO  uint32_t HW_PXP_IRQ_MASK;                        /**< PXP IRQ Mask Register, offset: 0x390 */
33542   uint8_t RESERVED_57[12];
33543   __IO  uint32_t HW_PXP_IRQ;                             /**< PXP Interrupt Register, offset: 0x3A0 */
33544   uint8_t RESERVED_58[92];
33545   __IO  uint32_t HW_PXP_NEXT;                            /**< Next Frame Pointer, offset: 0x400 */
33546   uint8_t RESERVED_59[76];
33547   __IO  uint32_t HW_PXP_INPUT_FETCH_CTRL_CH0;            /**< Pre-fetch engine Control Channel 0 Register, offset: 0x450 */
33548   uint8_t RESERVED_60[12];
33549   __IO  uint32_t HW_PXP_INPUT_FETCH_CTRL_CH1;            /**< Pre-fetch engine Control Channel 1 Register, offset: 0x460 */
33550   uint8_t RESERVED_61[12];
33551   __IO  uint32_t HW_PXP_INPUT_FETCH_STATUS_CH0;          /**< Pre-fetch engine status Channel 0 Register, offset: 0x470 */
33552   uint8_t RESERVED_62[12];
33553   __IO  uint32_t HW_PXP_INPUT_FETCH_STATUS_CH1;          /**< Store engine status Channel 1 Register, offset: 0x480 */
33554   uint8_t RESERVED_63[12];
33555   __IO  uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0; /**< , offset: 0x490 */
33556   uint8_t RESERVED_64[12];
33557   __IO  uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0; /**< , offset: 0x4A0 */
33558   uint8_t RESERVED_65[12];
33559   __IO  uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1; /**< , offset: 0x4B0 */
33560   uint8_t RESERVED_66[12];
33561   __IO  uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1; /**< , offset: 0x4C0 */
33562   uint8_t RESERVED_67[12];
33563   __IO  uint32_t HW_PXP_INPUT_FETCH_SIZE_CH0;            /**< , offset: 0x4D0 */
33564   uint8_t RESERVED_68[12];
33565   __IO  uint32_t HW_PXP_INPUT_FETCH_SIZE_CH1;            /**< , offset: 0x4E0 */
33566   uint8_t RESERVED_69[12];
33567   __IO  uint32_t HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0; /**< , offset: 0x4F0 */
33568   uint8_t RESERVED_70[12];
33569   __IO  uint32_t HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1; /**< , offset: 0x500 */
33570   uint8_t RESERVED_71[12];
33571   __IO  uint32_t HW_PXP_INPUT_FETCH_PITCH;               /**< , offset: 0x510 */
33572   uint8_t RESERVED_72[12];
33573   __IO  uint32_t HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0;      /**< , offset: 0x520 */
33574   uint8_t RESERVED_73[12];
33575   __IO  uint32_t HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1;      /**< , offset: 0x530 */
33576   uint8_t RESERVED_74[12];
33577   __IO  uint32_t HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0;    /**< , offset: 0x540 */
33578   uint8_t RESERVED_75[12];
33579   __IO  uint32_t HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1;    /**< , offset: 0x550 */
33580   uint8_t RESERVED_76[12];
33581   __IO  uint32_t HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0;     /**< , offset: 0x560 */
33582   uint8_t RESERVED_77[12];
33583   __IO  uint32_t HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1;     /**< , offset: 0x570 */
33584   uint8_t RESERVED_78[12];
33585   __IO  uint32_t HW_PXP_INPUT_FETCH_ADDR_0_CH0;          /**< , offset: 0x580 */
33586   uint8_t RESERVED_79[12];
33587   __IO  uint32_t HW_PXP_INPUT_FETCH_ADDR_1_CH0;          /**< , offset: 0x590 */
33588   uint8_t RESERVED_80[12];
33589   __IO  uint32_t HW_PXP_INPUT_FETCH_ADDR_0_CH1;          /**< , offset: 0x5A0 */
33590   uint8_t RESERVED_81[12];
33591   __IO  uint32_t HW_PXP_INPUT_FETCH_ADDR_1_CH1;          /**< , offset: 0x5B0 */
33592   uint8_t RESERVED_82[12];
33593   __IO  uint32_t HW_PXP_INPUT_STORE_CTRL_CH0;            /**< Store engine Control Channel 0 Register, offset: 0x5C0 */
33594   uint8_t RESERVED_83[12];
33595   __IO  uint32_t HW_PXP_INPUT_STORE_CTRL_CH1;            /**< Store engine Control Channel 1 Register, offset: 0x5D0 */
33596   uint8_t RESERVED_84[12];
33597   __IO  uint32_t HW_PXP_INPUT_STORE_STATUS_CH0;          /**< Store engine status Channel 0 Register, offset: 0x5E0 */
33598   uint8_t RESERVED_85[12];
33599   __IO  uint32_t HW_PXP_INPUT_STORE_STATUS_CH1;          /**< Store engine status Channel 1 Register, offset: 0x5F0 */
33600   uint8_t RESERVED_86[12];
33601   __IO  uint32_t HW_PXP_INPUT_STORE_SIZE_CH0;            /**< , offset: 0x600 */
33602   uint8_t RESERVED_87[12];
33603   __IO  uint32_t HW_PXP_INPUT_STORE_SIZE_CH1;            /**< , offset: 0x610 */
33604   uint8_t RESERVED_88[12];
33605   __IO  uint32_t HW_PXP_INPUT_STORE_PITCH;               /**< , offset: 0x620 */
33606   uint8_t RESERVED_89[12];
33607   __IO  uint32_t HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0;      /**< , offset: 0x630 */
33608   uint8_t RESERVED_90[12];
33609   __IO  uint32_t HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1;      /**< , offset: 0x640 */
33610   uint8_t RESERVED_91[76];
33611   __IO  uint32_t HW_PXP_INPUT_STORE_ADDR_0_CH0;          /**< , offset: 0x690 */
33612   uint8_t RESERVED_92[12];
33613   __IO  uint32_t HW_PXP_INPUT_STORE_ADDR_1_CH0;          /**< , offset: 0x6A0 */
33614   uint8_t RESERVED_93[12];
33615   __IO  uint32_t HW_PXP_INPUT_STORE_FILL_DATA_CH0;       /**< , offset: 0x6B0 */
33616   uint8_t RESERVED_94[12];
33617   __IO  uint32_t HW_PXP_INPUT_STORE_ADDR_0_CH1;          /**< , offset: 0x6C0 */
33618   uint8_t RESERVED_95[12];
33619   __IO  uint32_t HW_PXP_INPUT_STORE_ADDR_1_CH1;          /**< , offset: 0x6D0 */
33620   uint8_t RESERVED_96[12];
33621   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK0_H_CH0;       /**< , offset: 0x6E0 */
33622   uint8_t RESERVED_97[12];
33623   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK0_L_CH0;       /**< , offset: 0x6F0 */
33624   uint8_t RESERVED_98[12];
33625   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK1_H_CH0;       /**< , offset: 0x700 */
33626   uint8_t RESERVED_99[12];
33627   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK1_L_CH0;       /**< , offset: 0x710 */
33628   uint8_t RESERVED_100[12];
33629   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK2_H_CH0;       /**< , offset: 0x720 */
33630   uint8_t RESERVED_101[12];
33631   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK2_L_CH0;       /**< , offset: 0x730 */
33632   uint8_t RESERVED_102[12];
33633   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK3_H_CH0;       /**< , offset: 0x740 */
33634   uint8_t RESERVED_103[12];
33635   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK3_L_CH0;       /**< , offset: 0x750 */
33636   uint8_t RESERVED_104[12];
33637   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK4_H_CH0;       /**< , offset: 0x760 */
33638   uint8_t RESERVED_105[12];
33639   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK4_L_CH0;       /**< , offset: 0x770 */
33640   uint8_t RESERVED_106[12];
33641   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK5_H_CH0;       /**< , offset: 0x780 */
33642   uint8_t RESERVED_107[12];
33643   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK5_L_CH0;       /**< , offset: 0x790 */
33644   uint8_t RESERVED_108[12];
33645   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK6_H_CH0;       /**< , offset: 0x7A0 */
33646   uint8_t RESERVED_109[12];
33647   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK6_L_CH0;       /**< , offset: 0x7B0 */
33648   uint8_t RESERVED_110[12];
33649   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK7_H_CH0;       /**< , offset: 0x7C0 */
33650   uint8_t RESERVED_111[28];
33651   __IO  uint32_t HW_PXP_INPUT_STORE_D_MASK7_L_CH0;       /**< , offset: 0x7E0 */
33652   uint8_t RESERVED_112[12];
33653   __IO  uint32_t HW_PXP_INPUT_STORE_D_SHIFT_L_CH0;       /**< , offset: 0x7F0 */
33654   uint8_t RESERVED_113[12];
33655   __IO  uint32_t HW_PXP_INPUT_STORE_D_SHIFT_H_CH0;       /**< , offset: 0x800 */
33656   uint8_t RESERVED_114[12];
33657   __IO  uint32_t HW_PXP_INPUT_STORE_F_SHIFT_L_CH0;       /**< , offset: 0x810 */
33658   uint8_t RESERVED_115[12];
33659   __IO  uint32_t HW_PXP_INPUT_STORE_F_SHIFT_H_CH0;       /**< , offset: 0x820 */
33660   uint8_t RESERVED_116[12];
33661   __IO  uint32_t HW_PXP_INPUT_STORE_F_MASK_L_CH0;        /**< , offset: 0x830 */
33662   uint8_t RESERVED_117[12];
33663   __IO  uint32_t HW_PXP_INPUT_STORE_F_MASK_H_CH0;        /**< , offset: 0x840 */
33664   uint8_t RESERVED_118[12];
33665   __IO  uint32_t HW_PXP_DITHER_FETCH_CTRL_CH0;           /**< Pre-fetch engine Control Channel 0 Register, offset: 0x850 */
33666   uint8_t RESERVED_119[12];
33667   __IO  uint32_t HW_PXP_DITHER_FETCH_CTRL_CH1;           /**< Pre-fetch engine Control Channel 1 Register, offset: 0x860 */
33668   uint8_t RESERVED_120[12];
33669   __IO  uint32_t HW_PXP_DITHER_FETCH_STATUS_CH0;         /**< Pre-fetch engine status Channel 0 Register, offset: 0x870 */
33670   uint8_t RESERVED_121[12];
33671   __IO  uint32_t HW_PXP_DITHER_FETCH_STATUS_CH1;         /**< Store engine status Channel 1 Register, offset: 0x880 */
33672   uint8_t RESERVED_122[12];
33673   __IO  uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0; /**< , offset: 0x890 */
33674   uint8_t RESERVED_123[12];
33675   __IO  uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0; /**< , offset: 0x8A0 */
33676   uint8_t RESERVED_124[12];
33677   __IO  uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1; /**< , offset: 0x8B0 */
33678   uint8_t RESERVED_125[12];
33679   __IO  uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1; /**< , offset: 0x8C0 */
33680   uint8_t RESERVED_126[12];
33681   __IO  uint32_t HW_PXP_DITHER_FETCH_SIZE_CH0;           /**< , offset: 0x8D0 */
33682   uint8_t RESERVED_127[12];
33683   __IO  uint32_t HW_PXP_DITHER_FETCH_SIZE_CH1;           /**< , offset: 0x8E0 */
33684   uint8_t RESERVED_128[12];
33685   __IO  uint32_t HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0; /**< , offset: 0x8F0 */
33686   uint8_t RESERVED_129[12];
33687   __IO  uint32_t HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1; /**< , offset: 0x900 */
33688   uint8_t RESERVED_130[12];
33689   __IO  uint32_t HW_PXP_DITHER_FETCH_PITCH;              /**< , offset: 0x910 */
33690   uint8_t RESERVED_131[12];
33691   __IO  uint32_t HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0;     /**< , offset: 0x920 */
33692   uint8_t RESERVED_132[12];
33693   __IO  uint32_t HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1;     /**< , offset: 0x930 */
33694   uint8_t RESERVED_133[12];
33695   __IO  uint32_t HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0;   /**< , offset: 0x940 */
33696   uint8_t RESERVED_134[12];
33697   __IO  uint32_t HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1;   /**< , offset: 0x950 */
33698   uint8_t RESERVED_135[12];
33699   __IO  uint32_t HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0;    /**< , offset: 0x960 */
33700   uint8_t RESERVED_136[12];
33701   __IO  uint32_t HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1;    /**< , offset: 0x970 */
33702   uint8_t RESERVED_137[12];
33703   __IO  uint32_t HW_PXP_DITHER_FETCH_ADDR_0_CH0;         /**< , offset: 0x980 */
33704   uint8_t RESERVED_138[12];
33705   __IO  uint32_t HW_PXP_DITHER_FETCH_ADDR_1_CH0;         /**< , offset: 0x990 */
33706   uint8_t RESERVED_139[12];
33707   __IO  uint32_t HW_PXP_DITHER_FETCH_ADDR_0_CH1;         /**< , offset: 0x9A0 */
33708   uint8_t RESERVED_140[12];
33709   __IO  uint32_t HW_PXP_DITHER_FETCH_ADDR_1_CH1;         /**< , offset: 0x9B0 */
33710   uint8_t RESERVED_141[12];
33711   __IO  uint32_t HW_PXP_DITHER_STORE_CTRL_CH0;           /**< Store engine Control Channel 0 Register, offset: 0x9C0 */
33712   uint8_t RESERVED_142[12];
33713   __IO  uint32_t HW_PXP_DITHER_STORE_CTRL_CH1;           /**< Store engine Control Channel 1 Register, offset: 0x9D0 */
33714   uint8_t RESERVED_143[12];
33715   __IO  uint32_t HW_PXP_DITHER_STORE_STATUS_CH0;         /**< Store engine status Channel 0 Register, offset: 0x9E0 */
33716   uint8_t RESERVED_144[12];
33717   __IO  uint32_t HW_PXP_DITHER_STORE_STATUS_CH1;         /**< Store engine status Channel 1 Register, offset: 0x9F0 */
33718   uint8_t RESERVED_145[12];
33719   __IO  uint32_t HW_PXP_DITHER_STORE_SIZE_CH0;           /**< , offset: 0xA00 */
33720   uint8_t RESERVED_146[12];
33721   __IO  uint32_t HW_PXP_DITHER_STORE_SIZE_CH1;           /**< , offset: 0xA10 */
33722   uint8_t RESERVED_147[12];
33723   __IO  uint32_t HW_PXP_DITHER_STORE_PITCH;              /**< , offset: 0xA20 */
33724   uint8_t RESERVED_148[12];
33725   __IO  uint32_t HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0;     /**< , offset: 0xA30 */
33726   uint8_t RESERVED_149[12];
33727   __IO  uint32_t HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1;     /**< , offset: 0xA40 */
33728   uint8_t RESERVED_150[76];
33729   __IO  uint32_t HW_PXP_DITHER_STORE_ADDR_0_CH0;         /**< , offset: 0xA90 */
33730   uint8_t RESERVED_151[12];
33731   __IO  uint32_t HW_PXP_DITHER_STORE_ADDR_1_CH0;         /**< , offset: 0xAA0 */
33732   uint8_t RESERVED_152[12];
33733   __IO  uint32_t HW_PXP_DITHER_STORE_FILL_DATA_CH0;      /**< , offset: 0xAB0 */
33734   uint8_t RESERVED_153[12];
33735   __IO  uint32_t HW_PXP_DITHER_STORE_ADDR_0_CH1;         /**< , offset: 0xAC0 */
33736   uint8_t RESERVED_154[12];
33737   __IO  uint32_t HW_PXP_DITHER_STORE_ADDR_1_CH1;         /**< , offset: 0xAD0 */
33738   uint8_t RESERVED_155[12];
33739   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK0_H_CH0;      /**< , offset: 0xAE0 */
33740   uint8_t RESERVED_156[12];
33741   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK0_L_CH0;      /**< , offset: 0xAF0 */
33742   uint8_t RESERVED_157[12];
33743   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK1_H_CH0;      /**< , offset: 0xB00 */
33744   uint8_t RESERVED_158[12];
33745   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK1_L_CH0;      /**< , offset: 0xB10 */
33746   uint8_t RESERVED_159[12];
33747   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK2_H_CH0;      /**< , offset: 0xB20 */
33748   uint8_t RESERVED_160[12];
33749   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK2_L_CH0;      /**< , offset: 0xB30 */
33750   uint8_t RESERVED_161[12];
33751   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK3_H_CH0;      /**< , offset: 0xB40 */
33752   uint8_t RESERVED_162[12];
33753   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK3_L_CH0;      /**< , offset: 0xB50 */
33754   uint8_t RESERVED_163[12];
33755   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK4_H_CH0;      /**< , offset: 0xB60 */
33756   uint8_t RESERVED_164[12];
33757   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK4_L_CH0;      /**< , offset: 0xB70 */
33758   uint8_t RESERVED_165[12];
33759   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK5_H_CH0;      /**< , offset: 0xB80 */
33760   uint8_t RESERVED_166[12];
33761   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK5_L_CH0;      /**< , offset: 0xB90 */
33762   uint8_t RESERVED_167[12];
33763   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK6_H_CH0;      /**< , offset: 0xBA0 */
33764   uint8_t RESERVED_168[12];
33765   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK6_L_CH0;      /**< , offset: 0xBB0 */
33766   uint8_t RESERVED_169[12];
33767   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK7_H_CH0;      /**< , offset: 0xBC0 */
33768   uint8_t RESERVED_170[12];
33769   __IO  uint32_t HW_PXP_DITHER_STORE_D_MASK7_L_CH0;      /**< , offset: 0xBD0 */
33770   uint8_t RESERVED_171[12];
33771   __IO  uint32_t HW_PXP_DITHER_STORE_D_SHIFT_L_CH0;      /**< , offset: 0xBE0 */
33772   uint8_t RESERVED_172[12];
33773   __IO  uint32_t HW_PXP_DITHER_STORE_D_SHIFT_H_CH0;      /**< , offset: 0xBF0 */
33774   uint8_t RESERVED_173[12];
33775   __IO  uint32_t HW_PXP_DITHER_STORE_F_SHIFT_L_CH0;      /**< , offset: 0xC00 */
33776   uint8_t RESERVED_174[12];
33777   __IO  uint32_t HW_PXP_DITHER_STORE_F_SHIFT_H_CH0;      /**< , offset: 0xC10 */
33778   uint8_t RESERVED_175[12];
33779   __IO  uint32_t HW_PXP_DITHER_STORE_F_MASK_L_CH0;       /**< , offset: 0xC20 */
33780   uint8_t RESERVED_176[12];
33781   __IO  uint32_t HW_PXP_DITHER_STORE_F_MASK_H_CH0;       /**< , offset: 0xC30 */
33782   uint8_t RESERVED_177[2620];
33783   __IO  uint32_t HW_PXP_DITHER_CTRL;                     /**< Dither Control Register 0, offset: 0x1670 */
33784   uint8_t RESERVED_178[12];
33785   __IO  uint32_t HW_PXP_DITHER_FINAL_LUT_DATA0;          /**< Final stage lookup value Register, offset: 0x1680 */
33786   uint8_t RESERVED_179[12];
33787   __IO  uint32_t HW_PXP_DITHER_FINAL_LUT_DATA1;          /**< Final stage lookup value Register, offset: 0x1690 */
33788   uint8_t RESERVED_180[12];
33789   __IO  uint32_t HW_PXP_DITHER_FINAL_LUT_DATA2;          /**< Final stage lookup value Register, offset: 0x16A0 */
33790   uint8_t RESERVED_181[12];
33791   __IO  uint32_t HW_PXP_DITHER_FINAL_LUT_DATA3;          /**< Final stage lookup value Register, offset: 0x16B0 */
33792   uint8_t RESERVED_182[4940];
33793   __IO  uint32_t HW_PXP_HIST_A_CTRL;                     /**< Histogram Control Register., offset: 0x2A00 */
33794   uint8_t RESERVED_183[12];
33795   __IO  uint32_t HW_PXP_HIST_A_MASK;                     /**< Histogram Pixel Mask Register., offset: 0x2A10 */
33796   uint8_t RESERVED_184[12];
33797   __IO  uint32_t HW_PXP_HIST_A_BUF_SIZE;                 /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */
33798   uint8_t RESERVED_185[12];
33799   __IO  uint32_t HW_PXP_HIST_A_TOTAL_PIXEL;              /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */
33800   uint8_t RESERVED_186[12];
33801   __IO  uint32_t HW_PXP_HIST_A_ACTIVE_AREA_X;            /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */
33802   uint8_t RESERVED_187[12];
33803   __IO  uint32_t HW_PXP_HIST_A_ACTIVE_AREA_Y;            /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */
33804   uint8_t RESERVED_188[12];
33805   __IO  uint32_t HW_PXP_HIST_A_RAW_STAT0;                /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */
33806   uint8_t RESERVED_189[12];
33807   __IO  uint32_t HW_PXP_HIST_A_RAW_STAT1;                /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */
33808   uint8_t RESERVED_190[12];
33809   __IO  uint32_t HW_PXP_HIST_B_CTRL;                     /**< Histogram Control Register., offset: 0x2A80 */
33810   uint8_t RESERVED_191[12];
33811   __IO  uint32_t HW_PXP_HIST_B_MASK;                     /**< Histogram Pixel Mask Register., offset: 0x2A90 */
33812   uint8_t RESERVED_192[12];
33813   __IO  uint32_t HW_PXP_HIST_B_BUF_SIZE;                 /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */
33814   uint8_t RESERVED_193[12];
33815   __IO  uint32_t HW_PXP_HIST_B_TOTAL_PIXEL;              /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */
33816   uint8_t RESERVED_194[12];
33817   __IO  uint32_t HW_PXP_HIST_B_ACTIVE_AREA_X;            /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */
33818   uint8_t RESERVED_195[12];
33819   __IO  uint32_t HW_PXP_HIST_B_ACTIVE_AREA_Y;            /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */
33820   uint8_t RESERVED_196[12];
33821   __IO  uint32_t HW_PXP_HIST_B_RAW_STAT0;                /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */
33822   uint8_t RESERVED_197[12];
33823   __IO  uint32_t HW_PXP_HIST_B_RAW_STAT1;                /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */
33824   uint8_t RESERVED_198[12];
33825   __IO  uint32_t HW_PXP_HIST2_PARAM;                     /**< 2-level Histogram Parameter Register., offset: 0x2B00 */
33826   uint8_t RESERVED_199[12];
33827   __IO  uint32_t HW_PXP_HIST4_PARAM;                     /**< 4-level Histogram Parameter Register., offset: 0x2B10 */
33828   uint8_t RESERVED_200[12];
33829   __IO  uint32_t HW_PXP_HIST8_PARAM0;                    /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */
33830   uint8_t RESERVED_201[12];
33831   __IO  uint32_t HW_PXP_HIST8_PARAM1;                    /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */
33832   uint8_t RESERVED_202[12];
33833   __IO  uint32_t HW_PXP_HIST16_PARAM0;                   /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */
33834   uint8_t RESERVED_203[12];
33835   __IO  uint32_t HW_PXP_HIST16_PARAM1;                   /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */
33836   uint8_t RESERVED_204[12];
33837   __IO  uint32_t HW_PXP_HIST16_PARAM2;                   /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */
33838   uint8_t RESERVED_205[12];
33839   __IO  uint32_t HW_PXP_HIST16_PARAM3;                   /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */
33840   uint8_t RESERVED_206[12];
33841   __IO  uint32_t HW_PXP_HIST32_PARAM0;                   /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */
33842   uint8_t RESERVED_207[12];
33843   __IO  uint32_t HW_PXP_HIST32_PARAM1;                   /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */
33844   uint8_t RESERVED_208[12];
33845   __IO  uint32_t HW_PXP_HIST32_PARAM2;                   /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */
33846   uint8_t RESERVED_209[12];
33847   __IO  uint32_t HW_PXP_HIST32_PARAM3;                   /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */
33848   uint8_t RESERVED_210[12];
33849   __IO  uint32_t HW_PXP_HIST32_PARAM4;                   /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */
33850   uint8_t RESERVED_211[12];
33851   __IO  uint32_t HW_PXP_HIST32_PARAM5;                   /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */
33852   uint8_t RESERVED_212[12];
33853   __IO  uint32_t HW_PXP_HIST32_PARAM6;                   /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */
33854   uint8_t RESERVED_213[12];
33855   __IO  uint32_t HW_PXP_HIST32_PARAM7;                   /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */
33856   uint8_t RESERVED_214[12];
33857   __IO  uint32_t HW_PXP_COMP_CTRL;                       /**< , offset: 0x2C00 */
33858   uint8_t RESERVED_215[12];
33859   __IO  uint32_t HW_PXP_COMP_FORMAT0;                    /**< , offset: 0x2C10 */
33860   uint8_t RESERVED_216[12];
33861   __IO  uint32_t HW_PXP_COMP_FORMAT1;                    /**< , offset: 0x2C20 */
33862   uint8_t RESERVED_217[12];
33863   __IO  uint32_t HW_PXP_COMP_FORMAT2;                    /**< , offset: 0x2C30 */
33864   uint8_t RESERVED_218[12];
33865   __IO  uint32_t HW_PXP_COMP_MASK0;                      /**< , offset: 0x2C40 */
33866   uint8_t RESERVED_219[12];
33867   __IO  uint32_t HW_PXP_COMP_MASK1;                      /**< , offset: 0x2C50 */
33868   uint8_t RESERVED_220[12];
33869   __IO  uint32_t HW_PXP_COMP_BUFFER_SIZE;                /**< , offset: 0x2C60 */
33870   uint8_t RESERVED_221[12];
33871   __IO  uint32_t HW_PXP_COMP_SOURCE;                     /**< , offset: 0x2C70 */
33872   uint8_t RESERVED_222[12];
33873   __IO  uint32_t HW_PXP_COMP_TARGET;                     /**< , offset: 0x2C80 */
33874   uint8_t RESERVED_223[12];
33875   __IO  uint32_t HW_PXP_COMP_BUFFER_A;                   /**< , offset: 0x2C90 */
33876   uint8_t RESERVED_224[12];
33877   __IO  uint32_t HW_PXP_COMP_BUFFER_B;                   /**< , offset: 0x2CA0 */
33878   uint8_t RESERVED_225[12];
33879   __IO  uint32_t HW_PXP_COMP_BUFFER_C;                   /**< , offset: 0x2CB0 */
33880   uint8_t RESERVED_226[12];
33881   __IO  uint32_t HW_PXP_COMP_BUFFER_D;                   /**< , offset: 0x2CC0 */
33882   uint8_t RESERVED_227[12];
33883   __IO  uint32_t HW_PXP_COMP_DEBUG;                      /**< , offset: 0x2CD0 */
33884   uint8_t RESERVED_228[12];
33885   __IO  uint32_t HW_PXP_BUS_MUX;                         /**< , offset: 0x2CE0 */
33886   uint8_t RESERVED_229[12];
33887   __IO  uint32_t HW_PXP_HANDSHAKE_READY_MUX0;            /**< , offset: 0x2CF0 */
33888   uint8_t RESERVED_230[12];
33889   __IO  uint32_t HW_PXP_HANDSHAKE_READY_MUX1;            /**< , offset: 0x2D00 */
33890   uint8_t RESERVED_231[12];
33891   __IO  uint32_t HW_PXP_HANDSHAKE_DONE_MUX0;             /**< , offset: 0x2D10 */
33892   uint8_t RESERVED_232[12];
33893   __IO  uint32_t HW_PXP_HANDSHAKE_DONE_MUX1;             /**< , offset: 0x2D20 */
33894   uint8_t RESERVED_233[12];
33895   __IO  uint32_t HW_PXP_HANDSHAKE_CPU_FETCH;             /**< , offset: 0x2D30 */
33896   uint8_t RESERVED_234[12];
33897   __IO  uint32_t HW_PXP_HANDSHAKE_CPU_STORE;             /**< , offset: 0x2D40 */
33898 } PXP_Type, *PXP_MemMapPtr;
33899 /* ----------------------------------------------------------------------------
33900    -- PXP - Register accessor macros
33901    ---------------------------------------------------------------------------- */
33902 
33903 /*!
33904  * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros
33905  * @{
33906  */
33907 
33908 
33909 /* PXP - Register accessors */
33910 #define PXP_HW_PXP_CTRL_REG(base)                ((base)->HW_PXP_CTRL)
33911 #define PXP_HW_PXP_STAT_REG(base)                ((base)->HW_PXP_STAT)
33912 #define PXP_HW_PXP_OUT_CTRL_REG(base)            ((base)->HW_PXP_OUT_CTRL)
33913 #define PXP_HW_PXP_OUT_BUF_REG(base)             ((base)->HW_PXP_OUT_BUF)
33914 #define PXP_HW_PXP_OUT_BUF2_REG(base)            ((base)->HW_PXP_OUT_BUF2)
33915 #define PXP_HW_PXP_OUT_PITCH_REG(base)           ((base)->HW_PXP_OUT_PITCH)
33916 #define PXP_HW_PXP_OUT_LRC_REG(base)             ((base)->HW_PXP_OUT_LRC)
33917 #define PXP_HW_PXP_OUT_PS_ULC_REG(base)          ((base)->HW_PXP_OUT_PS_ULC)
33918 #define PXP_HW_PXP_OUT_PS_LRC_REG(base)          ((base)->HW_PXP_OUT_PS_LRC)
33919 #define PXP_HW_PXP_OUT_AS_ULC_REG(base)          ((base)->HW_PXP_OUT_AS_ULC)
33920 #define PXP_HW_PXP_OUT_AS_LRC_REG(base)          ((base)->HW_PXP_OUT_AS_LRC)
33921 #define PXP_HW_PXP_PS_CTRL_REG(base)             ((base)->HW_PXP_PS_CTRL)
33922 #define PXP_HW_PXP_PS_BUF_REG(base)              ((base)->HW_PXP_PS_BUF)
33923 #define PXP_HW_PXP_PS_UBUF_REG(base)             ((base)->HW_PXP_PS_UBUF)
33924 #define PXP_HW_PXP_PS_VBUF_REG(base)             ((base)->HW_PXP_PS_VBUF)
33925 #define PXP_HW_PXP_PS_PITCH_REG(base)            ((base)->HW_PXP_PS_PITCH)
33926 #define PXP_HW_PXP_PS_BACKGROUND_0_REG(base)     ((base)->HW_PXP_PS_BACKGROUND_0)
33927 #define PXP_HW_PXP_PS_SCALE_REG(base)            ((base)->HW_PXP_PS_SCALE)
33928 #define PXP_HW_PXP_PS_OFFSET_REG(base)           ((base)->HW_PXP_PS_OFFSET)
33929 #define PXP_HW_PXP_PS_CLRKEYLOW_0_REG(base)      ((base)->HW_PXP_PS_CLRKEYLOW_0)
33930 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(base)     ((base)->HW_PXP_PS_CLRKEYHIGH_0)
33931 #define PXP_HW_PXP_AS_CTRL_REG(base)             ((base)->HW_PXP_AS_CTRL)
33932 #define PXP_HW_PXP_AS_BUF_REG(base)              ((base)->HW_PXP_AS_BUF)
33933 #define PXP_HW_PXP_AS_PITCH_REG(base)            ((base)->HW_PXP_AS_PITCH)
33934 #define PXP_HW_PXP_AS_CLRKEYLOW_0_REG(base)      ((base)->HW_PXP_AS_CLRKEYLOW_0)
33935 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(base)     ((base)->HW_PXP_AS_CLRKEYHIGH_0)
33936 #define PXP_HW_PXP_CSC1_COEF0_REG(base)          ((base)->HW_PXP_CSC1_COEF0)
33937 #define PXP_HW_PXP_CSC1_COEF1_REG(base)          ((base)->HW_PXP_CSC1_COEF1)
33938 #define PXP_HW_PXP_CSC1_COEF2_REG(base)          ((base)->HW_PXP_CSC1_COEF2)
33939 #define PXP_HW_PXP_CSC2_CTRL_REG(base)           ((base)->HW_PXP_CSC2_CTRL)
33940 #define PXP_HW_PXP_CSC2_COEF0_REG(base)          ((base)->HW_PXP_CSC2_COEF0)
33941 #define PXP_HW_PXP_CSC2_COEF1_REG(base)          ((base)->HW_PXP_CSC2_COEF1)
33942 #define PXP_HW_PXP_CSC2_COEF2_REG(base)          ((base)->HW_PXP_CSC2_COEF2)
33943 #define PXP_HW_PXP_CSC2_COEF3_REG(base)          ((base)->HW_PXP_CSC2_COEF3)
33944 #define PXP_HW_PXP_CSC2_COEF4_REG(base)          ((base)->HW_PXP_CSC2_COEF4)
33945 #define PXP_HW_PXP_CSC2_COEF5_REG(base)          ((base)->HW_PXP_CSC2_COEF5)
33946 #define PXP_HW_PXP_LUT_CTRL_REG(base)            ((base)->HW_PXP_LUT_CTRL)
33947 #define PXP_HW_PXP_LUT_ADDR_REG(base)            ((base)->HW_PXP_LUT_ADDR)
33948 #define PXP_HW_PXP_LUT_DATA_REG(base)            ((base)->HW_PXP_LUT_DATA)
33949 #define PXP_HW_PXP_LUT_EXTMEM_REG(base)          ((base)->HW_PXP_LUT_EXTMEM)
33950 #define PXP_HW_PXP_CFA_REG(base)                 ((base)->HW_PXP_CFA)
33951 #define PXP_HW_PXP_ALPHA_A_CTRL_REG(base)        ((base)->HW_PXP_ALPHA_A_CTRL)
33952 #define PXP_HW_PXP_ALPHA_B_CTRL_REG(base)        ((base)->HW_PXP_ALPHA_B_CTRL)
33953 #define PXP_HW_PXP_ALPHA_B_CTRL_1_REG(base)      ((base)->HW_PXP_ALPHA_B_CTRL_1)
33954 #define PXP_HW_PXP_PS_BACKGROUND_1_REG(base)     ((base)->HW_PXP_PS_BACKGROUND_1)
33955 #define PXP_HW_PXP_PS_CLRKEYLOW_1_REG(base)      ((base)->HW_PXP_PS_CLRKEYLOW_1)
33956 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(base)     ((base)->HW_PXP_PS_CLRKEYHIGH_1)
33957 #define PXP_HW_PXP_AS_CLRKEYLOW_1_REG(base)      ((base)->HW_PXP_AS_CLRKEYLOW_1)
33958 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(base)     ((base)->HW_PXP_AS_CLRKEYHIGH_1)
33959 #define PXP_HW_PXP_CTRL2_REG(base)               ((base)->HW_PXP_CTRL2)
33960 #define PXP_HW_PXP_POWER_REG0_REG(base)          ((base)->HW_PXP_POWER_REG0)
33961 #define PXP_HW_PXP_POWER_REG1_REG(base)          ((base)->HW_PXP_POWER_REG1)
33962 #define PXP_HW_PXP_DATA_PATH_CTRL0_REG(base)     ((base)->HW_PXP_DATA_PATH_CTRL0)
33963 #define PXP_HW_PXP_DATA_PATH_CTRL1_REG(base)     ((base)->HW_PXP_DATA_PATH_CTRL1)
33964 #define PXP_HW_PXP_INIT_MEM_CTRL_REG(base)       ((base)->HW_PXP_INIT_MEM_CTRL)
33965 #define PXP_HW_PXP_INIT_MEM_DATA_REG(base)       ((base)->HW_PXP_INIT_MEM_DATA)
33966 #define PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(base)  ((base)->HW_PXP_INIT_MEM_DATA_HIGH)
33967 #define PXP_HW_PXP_IRQ_MASK_REG(base)            ((base)->HW_PXP_IRQ_MASK)
33968 #define PXP_HW_PXP_IRQ_REG(base)                 ((base)->HW_PXP_IRQ)
33969 #define PXP_HW_PXP_NEXT_REG(base)                ((base)->HW_PXP_NEXT)
33970 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH0)
33971 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH1)
33972 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH0)
33973 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH1)
33974 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0)
33975 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0)
33976 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1)
33977 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1)
33978 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH0)
33979 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH1)
33980 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0)
33981 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1)
33982 #define PXP_HW_PXP_INPUT_FETCH_PITCH_REG(base)   ((base)->HW_PXP_INPUT_FETCH_PITCH)
33983 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0)
33984 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1)
33985 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0)
33986 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1)
33987 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0)
33988 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1)
33989 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH0)
33990 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH0)
33991 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH1)
33992 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH1)
33993 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH0)
33994 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH1)
33995 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH0)
33996 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH1)
33997 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH0)
33998 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH1)
33999 #define PXP_HW_PXP_INPUT_STORE_PITCH_REG(base)   ((base)->HW_PXP_INPUT_STORE_PITCH)
34000 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0)
34001 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1)
34002 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH0)
34003 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH0)
34004 #define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_FILL_DATA_CH0)
34005 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH1)
34006 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH1)
34007 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_H_CH0)
34008 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_L_CH0)
34009 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_H_CH0)
34010 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_L_CH0)
34011 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_H_CH0)
34012 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_L_CH0)
34013 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_H_CH0)
34014 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_L_CH0)
34015 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_H_CH0)
34016 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_L_CH0)
34017 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_H_CH0)
34018 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_L_CH0)
34019 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_H_CH0)
34020 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_L_CH0)
34021 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_H_CH0)
34022 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_L_CH0)
34023 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_L_CH0)
34024 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_H_CH0)
34025 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_L_CH0)
34026 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_H_CH0)
34027 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_L_CH0)
34028 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_H_CH0)
34029 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH0)
34030 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH1)
34031 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH0)
34032 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH1)
34033 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0)
34034 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0)
34035 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1)
34036 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1)
34037 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH0)
34038 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH1)
34039 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0)
34040 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1)
34041 #define PXP_HW_PXP_DITHER_FETCH_PITCH_REG(base)  ((base)->HW_PXP_DITHER_FETCH_PITCH)
34042 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0)
34043 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1)
34044 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0)
34045 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1)
34046 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0)
34047 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1)
34048 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH0)
34049 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH0)
34050 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH1)
34051 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH1)
34052 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH0)
34053 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH1)
34054 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH0)
34055 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH1)
34056 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH0)
34057 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH1)
34058 #define PXP_HW_PXP_DITHER_STORE_PITCH_REG(base)  ((base)->HW_PXP_DITHER_STORE_PITCH)
34059 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0)
34060 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1)
34061 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH0)
34062 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH0)
34063 #define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_FILL_DATA_CH0)
34064 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH1)
34065 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH1)
34066 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_H_CH0)
34067 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_L_CH0)
34068 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_H_CH0)
34069 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_L_CH0)
34070 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_H_CH0)
34071 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_L_CH0)
34072 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_H_CH0)
34073 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_L_CH0)
34074 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_H_CH0)
34075 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_L_CH0)
34076 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_H_CH0)
34077 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_L_CH0)
34078 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_H_CH0)
34079 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_L_CH0)
34080 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_H_CH0)
34081 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_L_CH0)
34082 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_L_CH0)
34083 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_H_CH0)
34084 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_L_CH0)
34085 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_H_CH0)
34086 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_L_CH0)
34087 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_H_CH0)
34088 #define PXP_HW_PXP_DITHER_CTRL_REG(base)         ((base)->HW_PXP_DITHER_CTRL)
34089 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA0)
34090 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA1)
34091 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA2)
34092 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA3)
34093 #define PXP_HW_PXP_HIST_A_CTRL_REG(base)         ((base)->HW_PXP_HIST_A_CTRL)
34094 #define PXP_HW_PXP_HIST_A_MASK_REG(base)         ((base)->HW_PXP_HIST_A_MASK)
34095 #define PXP_HW_PXP_HIST_A_BUF_SIZE_REG(base)     ((base)->HW_PXP_HIST_A_BUF_SIZE)
34096 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(base)  ((base)->HW_PXP_HIST_A_TOTAL_PIXEL)
34097 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_X)
34098 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_Y)
34099 #define PXP_HW_PXP_HIST_A_RAW_STAT0_REG(base)    ((base)->HW_PXP_HIST_A_RAW_STAT0)
34100 #define PXP_HW_PXP_HIST_A_RAW_STAT1_REG(base)    ((base)->HW_PXP_HIST_A_RAW_STAT1)
34101 #define PXP_HW_PXP_HIST_B_CTRL_REG(base)         ((base)->HW_PXP_HIST_B_CTRL)
34102 #define PXP_HW_PXP_HIST_B_MASK_REG(base)         ((base)->HW_PXP_HIST_B_MASK)
34103 #define PXP_HW_PXP_HIST_B_BUF_SIZE_REG(base)     ((base)->HW_PXP_HIST_B_BUF_SIZE)
34104 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(base)  ((base)->HW_PXP_HIST_B_TOTAL_PIXEL)
34105 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_X)
34106 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_Y)
34107 #define PXP_HW_PXP_HIST_B_RAW_STAT0_REG(base)    ((base)->HW_PXP_HIST_B_RAW_STAT0)
34108 #define PXP_HW_PXP_HIST_B_RAW_STAT1_REG(base)    ((base)->HW_PXP_HIST_B_RAW_STAT1)
34109 #define PXP_HW_PXP_HIST2_PARAM_REG(base)         ((base)->HW_PXP_HIST2_PARAM)
34110 #define PXP_HW_PXP_HIST4_PARAM_REG(base)         ((base)->HW_PXP_HIST4_PARAM)
34111 #define PXP_HW_PXP_HIST8_PARAM0_REG(base)        ((base)->HW_PXP_HIST8_PARAM0)
34112 #define PXP_HW_PXP_HIST8_PARAM1_REG(base)        ((base)->HW_PXP_HIST8_PARAM1)
34113 #define PXP_HW_PXP_HIST16_PARAM0_REG(base)       ((base)->HW_PXP_HIST16_PARAM0)
34114 #define PXP_HW_PXP_HIST16_PARAM1_REG(base)       ((base)->HW_PXP_HIST16_PARAM1)
34115 #define PXP_HW_PXP_HIST16_PARAM2_REG(base)       ((base)->HW_PXP_HIST16_PARAM2)
34116 #define PXP_HW_PXP_HIST16_PARAM3_REG(base)       ((base)->HW_PXP_HIST16_PARAM3)
34117 #define PXP_HW_PXP_HIST32_PARAM0_REG(base)       ((base)->HW_PXP_HIST32_PARAM0)
34118 #define PXP_HW_PXP_HIST32_PARAM1_REG(base)       ((base)->HW_PXP_HIST32_PARAM1)
34119 #define PXP_HW_PXP_HIST32_PARAM2_REG(base)       ((base)->HW_PXP_HIST32_PARAM2)
34120 #define PXP_HW_PXP_HIST32_PARAM3_REG(base)       ((base)->HW_PXP_HIST32_PARAM3)
34121 #define PXP_HW_PXP_HIST32_PARAM4_REG(base)       ((base)->HW_PXP_HIST32_PARAM4)
34122 #define PXP_HW_PXP_HIST32_PARAM5_REG(base)       ((base)->HW_PXP_HIST32_PARAM5)
34123 #define PXP_HW_PXP_HIST32_PARAM6_REG(base)       ((base)->HW_PXP_HIST32_PARAM6)
34124 #define PXP_HW_PXP_HIST32_PARAM7_REG(base)       ((base)->HW_PXP_HIST32_PARAM7)
34125 #define PXP_HW_PXP_COMP_CTRL_REG(base)           ((base)->HW_PXP_COMP_CTRL)
34126 #define PXP_HW_PXP_COMP_FORMAT0_REG(base)        ((base)->HW_PXP_COMP_FORMAT0)
34127 #define PXP_HW_PXP_COMP_FORMAT1_REG(base)        ((base)->HW_PXP_COMP_FORMAT1)
34128 #define PXP_HW_PXP_COMP_FORMAT2_REG(base)        ((base)->HW_PXP_COMP_FORMAT2)
34129 #define PXP_HW_PXP_COMP_MASK0_REG(base)          ((base)->HW_PXP_COMP_MASK0)
34130 #define PXP_HW_PXP_COMP_MASK1_REG(base)          ((base)->HW_PXP_COMP_MASK1)
34131 #define PXP_HW_PXP_COMP_BUFFER_SIZE_REG(base)    ((base)->HW_PXP_COMP_BUFFER_SIZE)
34132 #define PXP_HW_PXP_COMP_SOURCE_REG(base)         ((base)->HW_PXP_COMP_SOURCE)
34133 #define PXP_HW_PXP_COMP_TARGET_REG(base)         ((base)->HW_PXP_COMP_TARGET)
34134 #define PXP_HW_PXP_COMP_BUFFER_A_REG(base)       ((base)->HW_PXP_COMP_BUFFER_A)
34135 #define PXP_HW_PXP_COMP_BUFFER_B_REG(base)       ((base)->HW_PXP_COMP_BUFFER_B)
34136 #define PXP_HW_PXP_COMP_BUFFER_C_REG(base)       ((base)->HW_PXP_COMP_BUFFER_C)
34137 #define PXP_HW_PXP_COMP_BUFFER_D_REG(base)       ((base)->HW_PXP_COMP_BUFFER_D)
34138 #define PXP_HW_PXP_COMP_DEBUG_REG(base)          ((base)->HW_PXP_COMP_DEBUG)
34139 #define PXP_HW_PXP_BUS_MUX_REG(base)             ((base)->HW_PXP_BUS_MUX)
34140 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX0)
34141 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX1)
34142 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX0)
34143 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX1)
34144 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_FETCH)
34145 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_STORE)
34146 
34147 /*!
34148  * @}
34149  */ /* end of group PXP_Register_Accessor_Macros */
34150 /* ----------------------------------------------------------------------------
34151    -- PXP Register Masks
34152    ---------------------------------------------------------------------------- */
34153 
34154 /*!
34155  * @addtogroup PXP_Register_Masks PXP Register Masks
34156  * @{
34157  */
34158 
34159 /* HW_PXP_CTRL Bit Fields */
34160 #define PXP_HW_PXP_CTRL_ENABLE_MASK              0x1u
34161 #define PXP_HW_PXP_CTRL_ENABLE_SHIFT             0
34162 #define PXP_HW_PXP_CTRL_IRQ_ENABLE_MASK          0x2u
34163 #define PXP_HW_PXP_CTRL_IRQ_ENABLE_SHIFT         1
34164 #define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_MASK     0x4u
34165 #define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT    2
34166 #define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK  0x8u
34167 #define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3
34168 #define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u
34169 #define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4
34170 #define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u
34171 #define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5
34172 #define PXP_HW_PXP_CTRL_RSVD0_MASK               0xC0u
34173 #define PXP_HW_PXP_CTRL_RSVD0_SHIFT              6
34174 #define PXP_HW_PXP_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_CTRL_RSVD0_MASK)
34175 #define PXP_HW_PXP_CTRL_ROTATE0_MASK             0x300u
34176 #define PXP_HW_PXP_CTRL_ROTATE0_SHIFT            8
34177 #define PXP_HW_PXP_CTRL_ROTATE0(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL_ROTATE0_SHIFT))&PXP_HW_PXP_CTRL_ROTATE0_MASK)
34178 #define PXP_HW_PXP_CTRL_HFLIP0_MASK              0x400u
34179 #define PXP_HW_PXP_CTRL_HFLIP0_SHIFT             10
34180 #define PXP_HW_PXP_CTRL_VFLIP0_MASK              0x800u
34181 #define PXP_HW_PXP_CTRL_VFLIP0_SHIFT             11
34182 #define PXP_HW_PXP_CTRL_ROTATE1_MASK             0x3000u
34183 #define PXP_HW_PXP_CTRL_ROTATE1_SHIFT            12
34184 #define PXP_HW_PXP_CTRL_ROTATE1(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL_ROTATE1_SHIFT))&PXP_HW_PXP_CTRL_ROTATE1_MASK)
34185 #define PXP_HW_PXP_CTRL_HFLIP1_MASK              0x4000u
34186 #define PXP_HW_PXP_CTRL_HFLIP1_SHIFT             14
34187 #define PXP_HW_PXP_CTRL_VFLIP1_MASK              0x8000u
34188 #define PXP_HW_PXP_CTRL_VFLIP1_SHIFT             15
34189 #define PXP_HW_PXP_CTRL_ENABLE_PS_AS_OUT_MASK    0x10000u
34190 #define PXP_HW_PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT   16
34191 #define PXP_HW_PXP_CTRL_ENABLE_DITHER_MASK       0x20000u
34192 #define PXP_HW_PXP_CTRL_ENABLE_DITHER_SHIFT      17
34193 #define PXP_HW_PXP_CTRL_ENABLE_WFE_A_MASK        0x40000u
34194 #define PXP_HW_PXP_CTRL_ENABLE_WFE_A_SHIFT       18
34195 #define PXP_HW_PXP_CTRL_ENABLE_WFE_B_MASK        0x80000u
34196 #define PXP_HW_PXP_CTRL_ENABLE_WFE_B_SHIFT       19
34197 #define PXP_HW_PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK 0x100000u
34198 #define PXP_HW_PXP_CTRL_ENABLE_INPUT_FETCH_STORE_SHIFT 20
34199 #define PXP_HW_PXP_CTRL_ENABLE_ALPHA_B_MASK      0x200000u
34200 #define PXP_HW_PXP_CTRL_ENABLE_ALPHA_B_SHIFT     21
34201 #define PXP_HW_PXP_CTRL_RSVD1_MASK               0x400000u
34202 #define PXP_HW_PXP_CTRL_RSVD1_SHIFT              22
34203 #define PXP_HW_PXP_CTRL_BLOCK_SIZE_MASK          0x800000u
34204 #define PXP_HW_PXP_CTRL_BLOCK_SIZE_SHIFT         23
34205 #define PXP_HW_PXP_CTRL_ENABLE_CSC2_MASK         0x1000000u
34206 #define PXP_HW_PXP_CTRL_ENABLE_CSC2_SHIFT        24
34207 #define PXP_HW_PXP_CTRL_ENABLE_LUT_MASK          0x2000000u
34208 #define PXP_HW_PXP_CTRL_ENABLE_LUT_SHIFT         25
34209 #define PXP_HW_PXP_CTRL_ENABLE_ROTATE0_MASK      0x4000000u
34210 #define PXP_HW_PXP_CTRL_ENABLE_ROTATE0_SHIFT     26
34211 #define PXP_HW_PXP_CTRL_ENABLE_ROTATE1_MASK      0x8000000u
34212 #define PXP_HW_PXP_CTRL_ENABLE_ROTATE1_SHIFT     27
34213 #define PXP_HW_PXP_CTRL_EN_REPEAT_MASK           0x10000000u
34214 #define PXP_HW_PXP_CTRL_EN_REPEAT_SHIFT          28
34215 #define PXP_HW_PXP_CTRL_RSVD4_MASK               0x20000000u
34216 #define PXP_HW_PXP_CTRL_RSVD4_SHIFT              29
34217 #define PXP_HW_PXP_CTRL_CLKGATE_MASK             0x40000000u
34218 #define PXP_HW_PXP_CTRL_CLKGATE_SHIFT            30
34219 #define PXP_HW_PXP_CTRL_SFTRST_MASK              0x80000000u
34220 #define PXP_HW_PXP_CTRL_SFTRST_SHIFT             31
34221 /* HW_PXP_STAT Bit Fields */
34222 #define PXP_HW_PXP_STAT_IRQ0_MASK                0x1u
34223 #define PXP_HW_PXP_STAT_IRQ0_SHIFT               0
34224 #define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_0_MASK   0x2u
34225 #define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_0_SHIFT  1
34226 #define PXP_HW_PXP_STAT_AXI_READ_ERROR_0_MASK    0x4u
34227 #define PXP_HW_PXP_STAT_AXI_READ_ERROR_0_SHIFT   2
34228 #define PXP_HW_PXP_STAT_NEXT_IRQ_MASK            0x8u
34229 #define PXP_HW_PXP_STAT_NEXT_IRQ_SHIFT           3
34230 #define PXP_HW_PXP_STAT_AXI_ERROR_ID_0_MASK      0xF0u
34231 #define PXP_HW_PXP_STAT_AXI_ERROR_ID_0_SHIFT     4
34232 #define PXP_HW_PXP_STAT_AXI_ERROR_ID_0(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_AXI_ERROR_ID_0_SHIFT))&PXP_HW_PXP_STAT_AXI_ERROR_ID_0_MASK)
34233 #define PXP_HW_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK 0x100u
34234 #define PXP_HW_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT 8
34235 #define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_1_MASK   0x200u
34236 #define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_1_SHIFT  9
34237 #define PXP_HW_PXP_STAT_AXI_READ_ERROR_1_MASK    0x400u
34238 #define PXP_HW_PXP_STAT_AXI_READ_ERROR_1_SHIFT   10
34239 #define PXP_HW_PXP_STAT_RSVD2_MASK               0x800u
34240 #define PXP_HW_PXP_STAT_RSVD2_SHIFT              11
34241 #define PXP_HW_PXP_STAT_AXI_ERROR_ID_1_MASK      0xF000u
34242 #define PXP_HW_PXP_STAT_AXI_ERROR_ID_1_SHIFT     12
34243 #define PXP_HW_PXP_STAT_AXI_ERROR_ID_1(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_AXI_ERROR_ID_1_SHIFT))&PXP_HW_PXP_STAT_AXI_ERROR_ID_1_MASK)
34244 #define PXP_HW_PXP_STAT_BLOCKY_MASK              0xFF0000u
34245 #define PXP_HW_PXP_STAT_BLOCKY_SHIFT             16
34246 #define PXP_HW_PXP_STAT_BLOCKY(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_BLOCKY_SHIFT))&PXP_HW_PXP_STAT_BLOCKY_MASK)
34247 #define PXP_HW_PXP_STAT_BLOCKX_MASK              0xFF000000u
34248 #define PXP_HW_PXP_STAT_BLOCKX_SHIFT             24
34249 #define PXP_HW_PXP_STAT_BLOCKX(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_BLOCKX_SHIFT))&PXP_HW_PXP_STAT_BLOCKX_MASK)
34250 /* HW_PXP_OUT_CTRL Bit Fields */
34251 #define PXP_HW_PXP_OUT_CTRL_FORMAT_MASK          0x1Fu
34252 #define PXP_HW_PXP_OUT_CTRL_FORMAT_SHIFT         0
34253 #define PXP_HW_PXP_OUT_CTRL_FORMAT(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_FORMAT_SHIFT))&PXP_HW_PXP_OUT_CTRL_FORMAT_MASK)
34254 #define PXP_HW_PXP_OUT_CTRL_RSVD0_MASK           0xE0u
34255 #define PXP_HW_PXP_OUT_CTRL_RSVD0_SHIFT          5
34256 #define PXP_HW_PXP_OUT_CTRL_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_OUT_CTRL_RSVD0_MASK)
34257 #define PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK 0x300u
34258 #define PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT 8
34259 #define PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT))&PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
34260 #define PXP_HW_PXP_OUT_CTRL_RSVD1_MASK           0x7FFC00u
34261 #define PXP_HW_PXP_OUT_CTRL_RSVD1_SHIFT          10
34262 #define PXP_HW_PXP_OUT_CTRL_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_OUT_CTRL_RSVD1_MASK)
34263 #define PXP_HW_PXP_OUT_CTRL_ALPHA_OUTPUT_MASK    0x800000u
34264 #define PXP_HW_PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT   23
34265 #define PXP_HW_PXP_OUT_CTRL_ALPHA_MASK           0xFF000000u
34266 #define PXP_HW_PXP_OUT_CTRL_ALPHA_SHIFT          24
34267 #define PXP_HW_PXP_OUT_CTRL_ALPHA(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_ALPHA_SHIFT))&PXP_HW_PXP_OUT_CTRL_ALPHA_MASK)
34268 /* HW_PXP_OUT_BUF Bit Fields */
34269 #define PXP_HW_PXP_OUT_BUF_ADDR_MASK             0xFFFFFFFFu
34270 #define PXP_HW_PXP_OUT_BUF_ADDR_SHIFT            0
34271 #define PXP_HW_PXP_OUT_BUF_ADDR(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_BUF_ADDR_SHIFT))&PXP_HW_PXP_OUT_BUF_ADDR_MASK)
34272 /* HW_PXP_OUT_BUF2 Bit Fields */
34273 #define PXP_HW_PXP_OUT_BUF2_ADDR_MASK            0xFFFFFFFFu
34274 #define PXP_HW_PXP_OUT_BUF2_ADDR_SHIFT           0
34275 #define PXP_HW_PXP_OUT_BUF2_ADDR(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_BUF2_ADDR_SHIFT))&PXP_HW_PXP_OUT_BUF2_ADDR_MASK)
34276 /* HW_PXP_OUT_PITCH Bit Fields */
34277 #define PXP_HW_PXP_OUT_PITCH_PITCH_MASK          0xFFFFu
34278 #define PXP_HW_PXP_OUT_PITCH_PITCH_SHIFT         0
34279 #define PXP_HW_PXP_OUT_PITCH_PITCH(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PITCH_PITCH_SHIFT))&PXP_HW_PXP_OUT_PITCH_PITCH_MASK)
34280 #define PXP_HW_PXP_OUT_PITCH_RSVD_MASK           0xFFFF0000u
34281 #define PXP_HW_PXP_OUT_PITCH_RSVD_SHIFT          16
34282 #define PXP_HW_PXP_OUT_PITCH_RSVD(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PITCH_RSVD_SHIFT))&PXP_HW_PXP_OUT_PITCH_RSVD_MASK)
34283 /* HW_PXP_OUT_LRC Bit Fields */
34284 #define PXP_HW_PXP_OUT_LRC_Y_MASK                0x3FFFu
34285 #define PXP_HW_PXP_OUT_LRC_Y_SHIFT               0
34286 #define PXP_HW_PXP_OUT_LRC_Y(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_Y_SHIFT))&PXP_HW_PXP_OUT_LRC_Y_MASK)
34287 #define PXP_HW_PXP_OUT_LRC_RSVD0_MASK            0xC000u
34288 #define PXP_HW_PXP_OUT_LRC_RSVD0_SHIFT           14
34289 #define PXP_HW_PXP_OUT_LRC_RSVD0(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_LRC_RSVD0_MASK)
34290 #define PXP_HW_PXP_OUT_LRC_X_MASK                0x3FFF0000u
34291 #define PXP_HW_PXP_OUT_LRC_X_SHIFT               16
34292 #define PXP_HW_PXP_OUT_LRC_X(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_X_SHIFT))&PXP_HW_PXP_OUT_LRC_X_MASK)
34293 #define PXP_HW_PXP_OUT_LRC_RSVD1_MASK            0xC0000000u
34294 #define PXP_HW_PXP_OUT_LRC_RSVD1_SHIFT           30
34295 #define PXP_HW_PXP_OUT_LRC_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_LRC_RSVD1_MASK)
34296 /* HW_PXP_OUT_PS_ULC Bit Fields */
34297 #define PXP_HW_PXP_OUT_PS_ULC_Y_MASK             0x3FFFu
34298 #define PXP_HW_PXP_OUT_PS_ULC_Y_SHIFT            0
34299 #define PXP_HW_PXP_OUT_PS_ULC_Y(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_Y_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_Y_MASK)
34300 #define PXP_HW_PXP_OUT_PS_ULC_RSVD0_MASK         0xC000u
34301 #define PXP_HW_PXP_OUT_PS_ULC_RSVD0_SHIFT        14
34302 #define PXP_HW_PXP_OUT_PS_ULC_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_RSVD0_MASK)
34303 #define PXP_HW_PXP_OUT_PS_ULC_X_MASK             0x3FFF0000u
34304 #define PXP_HW_PXP_OUT_PS_ULC_X_SHIFT            16
34305 #define PXP_HW_PXP_OUT_PS_ULC_X(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_X_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_X_MASK)
34306 #define PXP_HW_PXP_OUT_PS_ULC_RSVD1_MASK         0xC0000000u
34307 #define PXP_HW_PXP_OUT_PS_ULC_RSVD1_SHIFT        30
34308 #define PXP_HW_PXP_OUT_PS_ULC_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_RSVD1_MASK)
34309 /* HW_PXP_OUT_PS_LRC Bit Fields */
34310 #define PXP_HW_PXP_OUT_PS_LRC_Y_MASK             0x3FFFu
34311 #define PXP_HW_PXP_OUT_PS_LRC_Y_SHIFT            0
34312 #define PXP_HW_PXP_OUT_PS_LRC_Y(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_Y_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_Y_MASK)
34313 #define PXP_HW_PXP_OUT_PS_LRC_RSVD0_MASK         0xC000u
34314 #define PXP_HW_PXP_OUT_PS_LRC_RSVD0_SHIFT        14
34315 #define PXP_HW_PXP_OUT_PS_LRC_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_RSVD0_MASK)
34316 #define PXP_HW_PXP_OUT_PS_LRC_X_MASK             0x3FFF0000u
34317 #define PXP_HW_PXP_OUT_PS_LRC_X_SHIFT            16
34318 #define PXP_HW_PXP_OUT_PS_LRC_X(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_X_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_X_MASK)
34319 #define PXP_HW_PXP_OUT_PS_LRC_RSVD1_MASK         0xC0000000u
34320 #define PXP_HW_PXP_OUT_PS_LRC_RSVD1_SHIFT        30
34321 #define PXP_HW_PXP_OUT_PS_LRC_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_RSVD1_MASK)
34322 /* HW_PXP_OUT_AS_ULC Bit Fields */
34323 #define PXP_HW_PXP_OUT_AS_ULC_Y_MASK             0x3FFFu
34324 #define PXP_HW_PXP_OUT_AS_ULC_Y_SHIFT            0
34325 #define PXP_HW_PXP_OUT_AS_ULC_Y(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_Y_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_Y_MASK)
34326 #define PXP_HW_PXP_OUT_AS_ULC_RSVD0_MASK         0xC000u
34327 #define PXP_HW_PXP_OUT_AS_ULC_RSVD0_SHIFT        14
34328 #define PXP_HW_PXP_OUT_AS_ULC_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_RSVD0_MASK)
34329 #define PXP_HW_PXP_OUT_AS_ULC_X_MASK             0x3FFF0000u
34330 #define PXP_HW_PXP_OUT_AS_ULC_X_SHIFT            16
34331 #define PXP_HW_PXP_OUT_AS_ULC_X(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_X_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_X_MASK)
34332 #define PXP_HW_PXP_OUT_AS_ULC_RSVD1_MASK         0xC0000000u
34333 #define PXP_HW_PXP_OUT_AS_ULC_RSVD1_SHIFT        30
34334 #define PXP_HW_PXP_OUT_AS_ULC_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_RSVD1_MASK)
34335 /* HW_PXP_OUT_AS_LRC Bit Fields */
34336 #define PXP_HW_PXP_OUT_AS_LRC_Y_MASK             0x3FFFu
34337 #define PXP_HW_PXP_OUT_AS_LRC_Y_SHIFT            0
34338 #define PXP_HW_PXP_OUT_AS_LRC_Y(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_Y_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_Y_MASK)
34339 #define PXP_HW_PXP_OUT_AS_LRC_RSVD0_MASK         0xC000u
34340 #define PXP_HW_PXP_OUT_AS_LRC_RSVD0_SHIFT        14
34341 #define PXP_HW_PXP_OUT_AS_LRC_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_RSVD0_MASK)
34342 #define PXP_HW_PXP_OUT_AS_LRC_X_MASK             0x3FFF0000u
34343 #define PXP_HW_PXP_OUT_AS_LRC_X_SHIFT            16
34344 #define PXP_HW_PXP_OUT_AS_LRC_X(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_X_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_X_MASK)
34345 #define PXP_HW_PXP_OUT_AS_LRC_RSVD1_MASK         0xC0000000u
34346 #define PXP_HW_PXP_OUT_AS_LRC_RSVD1_SHIFT        30
34347 #define PXP_HW_PXP_OUT_AS_LRC_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_RSVD1_MASK)
34348 /* HW_PXP_PS_CTRL Bit Fields */
34349 #define PXP_HW_PXP_PS_CTRL_FORMAT_MASK           0x3Fu
34350 #define PXP_HW_PXP_PS_CTRL_FORMAT_SHIFT          0
34351 #define PXP_HW_PXP_PS_CTRL_FORMAT(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_FORMAT_SHIFT))&PXP_HW_PXP_PS_CTRL_FORMAT_MASK)
34352 #define PXP_HW_PXP_PS_CTRL_WB_SWAP_MASK          0x40u
34353 #define PXP_HW_PXP_PS_CTRL_WB_SWAP_SHIFT         6
34354 #define PXP_HW_PXP_PS_CTRL_RSVD0_MASK            0x80u
34355 #define PXP_HW_PXP_PS_CTRL_RSVD0_SHIFT           7
34356 #define PXP_HW_PXP_PS_CTRL_DECY_MASK             0x300u
34357 #define PXP_HW_PXP_PS_CTRL_DECY_SHIFT            8
34358 #define PXP_HW_PXP_PS_CTRL_DECY(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_DECY_SHIFT))&PXP_HW_PXP_PS_CTRL_DECY_MASK)
34359 #define PXP_HW_PXP_PS_CTRL_DECX_MASK             0xC00u
34360 #define PXP_HW_PXP_PS_CTRL_DECX_SHIFT            10
34361 #define PXP_HW_PXP_PS_CTRL_DECX(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_DECX_SHIFT))&PXP_HW_PXP_PS_CTRL_DECX_MASK)
34362 #define PXP_HW_PXP_PS_CTRL_RSVD1_MASK            0xFFFFF000u
34363 #define PXP_HW_PXP_PS_CTRL_RSVD1_SHIFT           12
34364 #define PXP_HW_PXP_PS_CTRL_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_PS_CTRL_RSVD1_MASK)
34365 /* HW_PXP_PS_BUF Bit Fields */
34366 #define PXP_HW_PXP_PS_BUF_ADDR_MASK              0xFFFFFFFFu
34367 #define PXP_HW_PXP_PS_BUF_ADDR_SHIFT             0
34368 #define PXP_HW_PXP_PS_BUF_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BUF_ADDR_SHIFT))&PXP_HW_PXP_PS_BUF_ADDR_MASK)
34369 /* HW_PXP_PS_UBUF Bit Fields */
34370 #define PXP_HW_PXP_PS_UBUF_ADDR_MASK             0xFFFFFFFFu
34371 #define PXP_HW_PXP_PS_UBUF_ADDR_SHIFT            0
34372 #define PXP_HW_PXP_PS_UBUF_ADDR(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_UBUF_ADDR_SHIFT))&PXP_HW_PXP_PS_UBUF_ADDR_MASK)
34373 /* HW_PXP_PS_VBUF Bit Fields */
34374 #define PXP_HW_PXP_PS_VBUF_ADDR_MASK             0xFFFFFFFFu
34375 #define PXP_HW_PXP_PS_VBUF_ADDR_SHIFT            0
34376 #define PXP_HW_PXP_PS_VBUF_ADDR(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_VBUF_ADDR_SHIFT))&PXP_HW_PXP_PS_VBUF_ADDR_MASK)
34377 /* HW_PXP_PS_PITCH Bit Fields */
34378 #define PXP_HW_PXP_PS_PITCH_PITCH_MASK           0xFFFFu
34379 #define PXP_HW_PXP_PS_PITCH_PITCH_SHIFT          0
34380 #define PXP_HW_PXP_PS_PITCH_PITCH(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_PITCH_PITCH_SHIFT))&PXP_HW_PXP_PS_PITCH_PITCH_MASK)
34381 #define PXP_HW_PXP_PS_PITCH_RSVD_MASK            0xFFFF0000u
34382 #define PXP_HW_PXP_PS_PITCH_RSVD_SHIFT           16
34383 #define PXP_HW_PXP_PS_PITCH_RSVD(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_PITCH_RSVD_SHIFT))&PXP_HW_PXP_PS_PITCH_RSVD_MASK)
34384 /* HW_PXP_PS_BACKGROUND_0 Bit Fields */
34385 #define PXP_HW_PXP_PS_BACKGROUND_0_COLOR_MASK    0xFFFFFFu
34386 #define PXP_HW_PXP_PS_BACKGROUND_0_COLOR_SHIFT   0
34387 #define PXP_HW_PXP_PS_BACKGROUND_0_COLOR(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_0_COLOR_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_0_COLOR_MASK)
34388 #define PXP_HW_PXP_PS_BACKGROUND_0_RSVD_MASK     0xFF000000u
34389 #define PXP_HW_PXP_PS_BACKGROUND_0_RSVD_SHIFT    24
34390 #define PXP_HW_PXP_PS_BACKGROUND_0_RSVD(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_0_RSVD_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_0_RSVD_MASK)
34391 /* HW_PXP_PS_SCALE Bit Fields */
34392 #define PXP_HW_PXP_PS_SCALE_XSCALE_MASK          0x7FFFu
34393 #define PXP_HW_PXP_PS_SCALE_XSCALE_SHIFT         0
34394 #define PXP_HW_PXP_PS_SCALE_XSCALE(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_SCALE_XSCALE_SHIFT))&PXP_HW_PXP_PS_SCALE_XSCALE_MASK)
34395 #define PXP_HW_PXP_PS_SCALE_RSVD1_MASK           0x8000u
34396 #define PXP_HW_PXP_PS_SCALE_RSVD1_SHIFT          15
34397 #define PXP_HW_PXP_PS_SCALE_YSCALE_MASK          0x7FFF0000u
34398 #define PXP_HW_PXP_PS_SCALE_YSCALE_SHIFT         16
34399 #define PXP_HW_PXP_PS_SCALE_YSCALE(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_SCALE_YSCALE_SHIFT))&PXP_HW_PXP_PS_SCALE_YSCALE_MASK)
34400 #define PXP_HW_PXP_PS_SCALE_RSVD2_MASK           0x80000000u
34401 #define PXP_HW_PXP_PS_SCALE_RSVD2_SHIFT          31
34402 /* HW_PXP_PS_OFFSET Bit Fields */
34403 #define PXP_HW_PXP_PS_OFFSET_XOFFSET_MASK        0xFFFu
34404 #define PXP_HW_PXP_PS_OFFSET_XOFFSET_SHIFT       0
34405 #define PXP_HW_PXP_PS_OFFSET_XOFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_XOFFSET_SHIFT))&PXP_HW_PXP_PS_OFFSET_XOFFSET_MASK)
34406 #define PXP_HW_PXP_PS_OFFSET_RSVD1_MASK          0xF000u
34407 #define PXP_HW_PXP_PS_OFFSET_RSVD1_SHIFT         12
34408 #define PXP_HW_PXP_PS_OFFSET_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_RSVD1_SHIFT))&PXP_HW_PXP_PS_OFFSET_RSVD1_MASK)
34409 #define PXP_HW_PXP_PS_OFFSET_YOFFSET_MASK        0xFFF0000u
34410 #define PXP_HW_PXP_PS_OFFSET_YOFFSET_SHIFT       16
34411 #define PXP_HW_PXP_PS_OFFSET_YOFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_YOFFSET_SHIFT))&PXP_HW_PXP_PS_OFFSET_YOFFSET_MASK)
34412 #define PXP_HW_PXP_PS_OFFSET_RSVD2_MASK          0xF0000000u
34413 #define PXP_HW_PXP_PS_OFFSET_RSVD2_SHIFT         28
34414 #define PXP_HW_PXP_PS_OFFSET_RSVD2(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_RSVD2_SHIFT))&PXP_HW_PXP_PS_OFFSET_RSVD2_MASK)
34415 /* HW_PXP_PS_CLRKEYLOW_0 Bit Fields */
34416 #define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_MASK     0xFFFFFFu
34417 #define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT    0
34418 #define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_MASK)
34419 #define PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_MASK     0xFF000000u
34420 #define PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_SHIFT    24
34421 #define PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_MASK)
34422 /* HW_PXP_PS_CLRKEYHIGH_0 Bit Fields */
34423 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_MASK    0xFFFFFFu
34424 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT   0
34425 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_MASK)
34426 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_MASK    0xFF000000u
34427 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT   24
34428 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_MASK)
34429 /* HW_PXP_AS_CTRL Bit Fields */
34430 #define PXP_HW_PXP_AS_CTRL_RSVD0_MASK            0x1u
34431 #define PXP_HW_PXP_AS_CTRL_RSVD0_SHIFT           0
34432 #define PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_MASK       0x6u
34433 #define PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_SHIFT      1
34434 #define PXP_HW_PXP_AS_CTRL_ALPHA_CTRL(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_SHIFT))&PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_MASK)
34435 #define PXP_HW_PXP_AS_CTRL_ENABLE_COLORKEY_MASK  0x8u
34436 #define PXP_HW_PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT 3
34437 #define PXP_HW_PXP_AS_CTRL_FORMAT_MASK           0xF0u
34438 #define PXP_HW_PXP_AS_CTRL_FORMAT_SHIFT          4
34439 #define PXP_HW_PXP_AS_CTRL_FORMAT(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_FORMAT_SHIFT))&PXP_HW_PXP_AS_CTRL_FORMAT_MASK)
34440 #define PXP_HW_PXP_AS_CTRL_ALPHA_MASK            0xFF00u
34441 #define PXP_HW_PXP_AS_CTRL_ALPHA_SHIFT           8
34442 #define PXP_HW_PXP_AS_CTRL_ALPHA(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_ALPHA_SHIFT))&PXP_HW_PXP_AS_CTRL_ALPHA_MASK)
34443 #define PXP_HW_PXP_AS_CTRL_ROP_MASK              0xF0000u
34444 #define PXP_HW_PXP_AS_CTRL_ROP_SHIFT             16
34445 #define PXP_HW_PXP_AS_CTRL_ROP(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_ROP_SHIFT))&PXP_HW_PXP_AS_CTRL_ROP_MASK)
34446 #define PXP_HW_PXP_AS_CTRL_ALPHA0_INVERT_MASK    0x100000u
34447 #define PXP_HW_PXP_AS_CTRL_ALPHA0_INVERT_SHIFT   20
34448 #define PXP_HW_PXP_AS_CTRL_ALPHA1_INVERT_MASK    0x200000u
34449 #define PXP_HW_PXP_AS_CTRL_ALPHA1_INVERT_SHIFT   21
34450 #define PXP_HW_PXP_AS_CTRL_RSVD1_MASK            0xFFC00000u
34451 #define PXP_HW_PXP_AS_CTRL_RSVD1_SHIFT           22
34452 #define PXP_HW_PXP_AS_CTRL_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_AS_CTRL_RSVD1_MASK)
34453 /* HW_PXP_AS_BUF Bit Fields */
34454 #define PXP_HW_PXP_AS_BUF_ADDR_MASK              0xFFFFFFFFu
34455 #define PXP_HW_PXP_AS_BUF_ADDR_SHIFT             0
34456 #define PXP_HW_PXP_AS_BUF_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_BUF_ADDR_SHIFT))&PXP_HW_PXP_AS_BUF_ADDR_MASK)
34457 /* HW_PXP_AS_PITCH Bit Fields */
34458 #define PXP_HW_PXP_AS_PITCH_PITCH_MASK           0xFFFFu
34459 #define PXP_HW_PXP_AS_PITCH_PITCH_SHIFT          0
34460 #define PXP_HW_PXP_AS_PITCH_PITCH(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_PITCH_PITCH_SHIFT))&PXP_HW_PXP_AS_PITCH_PITCH_MASK)
34461 #define PXP_HW_PXP_AS_PITCH_RSVD_MASK            0xFFFF0000u
34462 #define PXP_HW_PXP_AS_PITCH_RSVD_SHIFT           16
34463 #define PXP_HW_PXP_AS_PITCH_RSVD(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_PITCH_RSVD_SHIFT))&PXP_HW_PXP_AS_PITCH_RSVD_MASK)
34464 /* HW_PXP_AS_CLRKEYLOW_0 Bit Fields */
34465 #define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_MASK     0xFFFFFFu
34466 #define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT    0
34467 #define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_MASK)
34468 #define PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_MASK     0xFF000000u
34469 #define PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_SHIFT    24
34470 #define PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_MASK)
34471 /* HW_PXP_AS_CLRKEYHIGH_0 Bit Fields */
34472 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_MASK    0xFFFFFFu
34473 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT   0
34474 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_MASK)
34475 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_MASK    0xFF000000u
34476 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT   24
34477 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_MASK)
34478 /* HW_PXP_CSC1_COEF0 Bit Fields */
34479 #define PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_MASK      0x1FFu
34480 #define PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_SHIFT     0
34481 #define PXP_HW_PXP_CSC1_COEF0_Y_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_SHIFT))&PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_MASK)
34482 #define PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_MASK     0x3FE00u
34483 #define PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_SHIFT    9
34484 #define PXP_HW_PXP_CSC1_COEF0_UV_OFFSET(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_SHIFT))&PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_MASK)
34485 #define PXP_HW_PXP_CSC1_COEF0_C0_MASK            0x1FFC0000u
34486 #define PXP_HW_PXP_CSC1_COEF0_C0_SHIFT           18
34487 #define PXP_HW_PXP_CSC1_COEF0_C0(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF0_C0_SHIFT))&PXP_HW_PXP_CSC1_COEF0_C0_MASK)
34488 #define PXP_HW_PXP_CSC1_COEF0_RSVD1_MASK         0x20000000u
34489 #define PXP_HW_PXP_CSC1_COEF0_RSVD1_SHIFT        29
34490 #define PXP_HW_PXP_CSC1_COEF0_BYPASS_MASK        0x40000000u
34491 #define PXP_HW_PXP_CSC1_COEF0_BYPASS_SHIFT       30
34492 #define PXP_HW_PXP_CSC1_COEF0_YCBCR_MODE_MASK    0x80000000u
34493 #define PXP_HW_PXP_CSC1_COEF0_YCBCR_MODE_SHIFT   31
34494 /* HW_PXP_CSC1_COEF1 Bit Fields */
34495 #define PXP_HW_PXP_CSC1_COEF1_C4_MASK            0x7FFu
34496 #define PXP_HW_PXP_CSC1_COEF1_C4_SHIFT           0
34497 #define PXP_HW_PXP_CSC1_COEF1_C4(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_C4_SHIFT))&PXP_HW_PXP_CSC1_COEF1_C4_MASK)
34498 #define PXP_HW_PXP_CSC1_COEF1_RSVD0_MASK         0xF800u
34499 #define PXP_HW_PXP_CSC1_COEF1_RSVD0_SHIFT        11
34500 #define PXP_HW_PXP_CSC1_COEF1_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_RSVD0_SHIFT))&PXP_HW_PXP_CSC1_COEF1_RSVD0_MASK)
34501 #define PXP_HW_PXP_CSC1_COEF1_C1_MASK            0x7FF0000u
34502 #define PXP_HW_PXP_CSC1_COEF1_C1_SHIFT           16
34503 #define PXP_HW_PXP_CSC1_COEF1_C1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_C1_SHIFT))&PXP_HW_PXP_CSC1_COEF1_C1_MASK)
34504 #define PXP_HW_PXP_CSC1_COEF1_RSVD1_MASK         0xF8000000u
34505 #define PXP_HW_PXP_CSC1_COEF1_RSVD1_SHIFT        27
34506 #define PXP_HW_PXP_CSC1_COEF1_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_RSVD1_SHIFT))&PXP_HW_PXP_CSC1_COEF1_RSVD1_MASK)
34507 /* HW_PXP_CSC1_COEF2 Bit Fields */
34508 #define PXP_HW_PXP_CSC1_COEF2_C3_MASK            0x7FFu
34509 #define PXP_HW_PXP_CSC1_COEF2_C3_SHIFT           0
34510 #define PXP_HW_PXP_CSC1_COEF2_C3(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_C3_SHIFT))&PXP_HW_PXP_CSC1_COEF2_C3_MASK)
34511 #define PXP_HW_PXP_CSC1_COEF2_RSVD0_MASK         0xF800u
34512 #define PXP_HW_PXP_CSC1_COEF2_RSVD0_SHIFT        11
34513 #define PXP_HW_PXP_CSC1_COEF2_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_RSVD0_SHIFT))&PXP_HW_PXP_CSC1_COEF2_RSVD0_MASK)
34514 #define PXP_HW_PXP_CSC1_COEF2_C2_MASK            0x7FF0000u
34515 #define PXP_HW_PXP_CSC1_COEF2_C2_SHIFT           16
34516 #define PXP_HW_PXP_CSC1_COEF2_C2(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_C2_SHIFT))&PXP_HW_PXP_CSC1_COEF2_C2_MASK)
34517 #define PXP_HW_PXP_CSC1_COEF2_RSVD1_MASK         0xF8000000u
34518 #define PXP_HW_PXP_CSC1_COEF2_RSVD1_SHIFT        27
34519 #define PXP_HW_PXP_CSC1_COEF2_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_RSVD1_SHIFT))&PXP_HW_PXP_CSC1_COEF2_RSVD1_MASK)
34520 /* HW_PXP_CSC2_CTRL Bit Fields */
34521 #define PXP_HW_PXP_CSC2_CTRL_BYPASS_MASK         0x1u
34522 #define PXP_HW_PXP_CSC2_CTRL_BYPASS_SHIFT        0
34523 #define PXP_HW_PXP_CSC2_CTRL_CSC_MODE_MASK       0x6u
34524 #define PXP_HW_PXP_CSC2_CTRL_CSC_MODE_SHIFT      1
34525 #define PXP_HW_PXP_CSC2_CTRL_CSC_MODE(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_CTRL_CSC_MODE_SHIFT))&PXP_HW_PXP_CSC2_CTRL_CSC_MODE_MASK)
34526 #define PXP_HW_PXP_CSC2_CTRL_RSVD_MASK           0xFFFFFFF8u
34527 #define PXP_HW_PXP_CSC2_CTRL_RSVD_SHIFT          3
34528 #define PXP_HW_PXP_CSC2_CTRL_RSVD(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_CTRL_RSVD_SHIFT))&PXP_HW_PXP_CSC2_CTRL_RSVD_MASK)
34529 /* HW_PXP_CSC2_COEF0 Bit Fields */
34530 #define PXP_HW_PXP_CSC2_COEF0_A1_MASK            0x7FFu
34531 #define PXP_HW_PXP_CSC2_COEF0_A1_SHIFT           0
34532 #define PXP_HW_PXP_CSC2_COEF0_A1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_A1_SHIFT))&PXP_HW_PXP_CSC2_COEF0_A1_MASK)
34533 #define PXP_HW_PXP_CSC2_COEF0_RSVD0_MASK         0xF800u
34534 #define PXP_HW_PXP_CSC2_COEF0_RSVD0_SHIFT        11
34535 #define PXP_HW_PXP_CSC2_COEF0_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF0_RSVD0_MASK)
34536 #define PXP_HW_PXP_CSC2_COEF0_A2_MASK            0x7FF0000u
34537 #define PXP_HW_PXP_CSC2_COEF0_A2_SHIFT           16
34538 #define PXP_HW_PXP_CSC2_COEF0_A2(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_A2_SHIFT))&PXP_HW_PXP_CSC2_COEF0_A2_MASK)
34539 #define PXP_HW_PXP_CSC2_COEF0_RSVD1_MASK         0xF8000000u
34540 #define PXP_HW_PXP_CSC2_COEF0_RSVD1_SHIFT        27
34541 #define PXP_HW_PXP_CSC2_COEF0_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF0_RSVD1_MASK)
34542 /* HW_PXP_CSC2_COEF1 Bit Fields */
34543 #define PXP_HW_PXP_CSC2_COEF1_A3_MASK            0x7FFu
34544 #define PXP_HW_PXP_CSC2_COEF1_A3_SHIFT           0
34545 #define PXP_HW_PXP_CSC2_COEF1_A3(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_A3_SHIFT))&PXP_HW_PXP_CSC2_COEF1_A3_MASK)
34546 #define PXP_HW_PXP_CSC2_COEF1_RSVD0_MASK         0xF800u
34547 #define PXP_HW_PXP_CSC2_COEF1_RSVD0_SHIFT        11
34548 #define PXP_HW_PXP_CSC2_COEF1_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF1_RSVD0_MASK)
34549 #define PXP_HW_PXP_CSC2_COEF1_B1_MASK            0x7FF0000u
34550 #define PXP_HW_PXP_CSC2_COEF1_B1_SHIFT           16
34551 #define PXP_HW_PXP_CSC2_COEF1_B1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_B1_SHIFT))&PXP_HW_PXP_CSC2_COEF1_B1_MASK)
34552 #define PXP_HW_PXP_CSC2_COEF1_RSVD1_MASK         0xF8000000u
34553 #define PXP_HW_PXP_CSC2_COEF1_RSVD1_SHIFT        27
34554 #define PXP_HW_PXP_CSC2_COEF1_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF1_RSVD1_MASK)
34555 /* HW_PXP_CSC2_COEF2 Bit Fields */
34556 #define PXP_HW_PXP_CSC2_COEF2_B2_MASK            0x7FFu
34557 #define PXP_HW_PXP_CSC2_COEF2_B2_SHIFT           0
34558 #define PXP_HW_PXP_CSC2_COEF2_B2(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_B2_SHIFT))&PXP_HW_PXP_CSC2_COEF2_B2_MASK)
34559 #define PXP_HW_PXP_CSC2_COEF2_RSVD0_MASK         0xF800u
34560 #define PXP_HW_PXP_CSC2_COEF2_RSVD0_SHIFT        11
34561 #define PXP_HW_PXP_CSC2_COEF2_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF2_RSVD0_MASK)
34562 #define PXP_HW_PXP_CSC2_COEF2_B3_MASK            0x7FF0000u
34563 #define PXP_HW_PXP_CSC2_COEF2_B3_SHIFT           16
34564 #define PXP_HW_PXP_CSC2_COEF2_B3(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_B3_SHIFT))&PXP_HW_PXP_CSC2_COEF2_B3_MASK)
34565 #define PXP_HW_PXP_CSC2_COEF2_RSVD1_MASK         0xF8000000u
34566 #define PXP_HW_PXP_CSC2_COEF2_RSVD1_SHIFT        27
34567 #define PXP_HW_PXP_CSC2_COEF2_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF2_RSVD1_MASK)
34568 /* HW_PXP_CSC2_COEF3 Bit Fields */
34569 #define PXP_HW_PXP_CSC2_COEF3_C1_MASK            0x7FFu
34570 #define PXP_HW_PXP_CSC2_COEF3_C1_SHIFT           0
34571 #define PXP_HW_PXP_CSC2_COEF3_C1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_C1_SHIFT))&PXP_HW_PXP_CSC2_COEF3_C1_MASK)
34572 #define PXP_HW_PXP_CSC2_COEF3_RSVD0_MASK         0xF800u
34573 #define PXP_HW_PXP_CSC2_COEF3_RSVD0_SHIFT        11
34574 #define PXP_HW_PXP_CSC2_COEF3_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF3_RSVD0_MASK)
34575 #define PXP_HW_PXP_CSC2_COEF3_C2_MASK            0x7FF0000u
34576 #define PXP_HW_PXP_CSC2_COEF3_C2_SHIFT           16
34577 #define PXP_HW_PXP_CSC2_COEF3_C2(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_C2_SHIFT))&PXP_HW_PXP_CSC2_COEF3_C2_MASK)
34578 #define PXP_HW_PXP_CSC2_COEF3_RSVD1_MASK         0xF8000000u
34579 #define PXP_HW_PXP_CSC2_COEF3_RSVD1_SHIFT        27
34580 #define PXP_HW_PXP_CSC2_COEF3_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF3_RSVD1_MASK)
34581 /* HW_PXP_CSC2_COEF4 Bit Fields */
34582 #define PXP_HW_PXP_CSC2_COEF4_C3_MASK            0x7FFu
34583 #define PXP_HW_PXP_CSC2_COEF4_C3_SHIFT           0
34584 #define PXP_HW_PXP_CSC2_COEF4_C3(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_C3_SHIFT))&PXP_HW_PXP_CSC2_COEF4_C3_MASK)
34585 #define PXP_HW_PXP_CSC2_COEF4_RSVD0_MASK         0xF800u
34586 #define PXP_HW_PXP_CSC2_COEF4_RSVD0_SHIFT        11
34587 #define PXP_HW_PXP_CSC2_COEF4_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF4_RSVD0_MASK)
34588 #define PXP_HW_PXP_CSC2_COEF4_D1_MASK            0x1FF0000u
34589 #define PXP_HW_PXP_CSC2_COEF4_D1_SHIFT           16
34590 #define PXP_HW_PXP_CSC2_COEF4_D1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_D1_SHIFT))&PXP_HW_PXP_CSC2_COEF4_D1_MASK)
34591 #define PXP_HW_PXP_CSC2_COEF4_RSVD1_MASK         0xFE000000u
34592 #define PXP_HW_PXP_CSC2_COEF4_RSVD1_SHIFT        25
34593 #define PXP_HW_PXP_CSC2_COEF4_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF4_RSVD1_MASK)
34594 /* HW_PXP_CSC2_COEF5 Bit Fields */
34595 #define PXP_HW_PXP_CSC2_COEF5_D2_MASK            0x1FFu
34596 #define PXP_HW_PXP_CSC2_COEF5_D2_SHIFT           0
34597 #define PXP_HW_PXP_CSC2_COEF5_D2(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_D2_SHIFT))&PXP_HW_PXP_CSC2_COEF5_D2_MASK)
34598 #define PXP_HW_PXP_CSC2_COEF5_RSVD0_MASK         0xFE00u
34599 #define PXP_HW_PXP_CSC2_COEF5_RSVD0_SHIFT        9
34600 #define PXP_HW_PXP_CSC2_COEF5_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF5_RSVD0_MASK)
34601 #define PXP_HW_PXP_CSC2_COEF5_D3_MASK            0x1FF0000u
34602 #define PXP_HW_PXP_CSC2_COEF5_D3_SHIFT           16
34603 #define PXP_HW_PXP_CSC2_COEF5_D3(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_D3_SHIFT))&PXP_HW_PXP_CSC2_COEF5_D3_MASK)
34604 #define PXP_HW_PXP_CSC2_COEF5_RSVD1_MASK         0xFE000000u
34605 #define PXP_HW_PXP_CSC2_COEF5_RSVD1_SHIFT        25
34606 #define PXP_HW_PXP_CSC2_COEF5_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF5_RSVD1_MASK)
34607 /* HW_PXP_LUT_CTRL Bit Fields */
34608 #define PXP_HW_PXP_LUT_CTRL_DMA_START_MASK       0x1u
34609 #define PXP_HW_PXP_LUT_CTRL_DMA_START_SHIFT      0
34610 #define PXP_HW_PXP_LUT_CTRL_RSVD0_MASK           0xFEu
34611 #define PXP_HW_PXP_LUT_CTRL_RSVD0_SHIFT          1
34612 #define PXP_HW_PXP_LUT_CTRL_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD0_MASK)
34613 #define PXP_HW_PXP_LUT_CTRL_INVALID_MASK         0x100u
34614 #define PXP_HW_PXP_LUT_CTRL_INVALID_SHIFT        8
34615 #define PXP_HW_PXP_LUT_CTRL_LRU_UPD_MASK         0x200u
34616 #define PXP_HW_PXP_LUT_CTRL_LRU_UPD_SHIFT        9
34617 #define PXP_HW_PXP_LUT_CTRL_SEL_8KB_MASK         0x400u
34618 #define PXP_HW_PXP_LUT_CTRL_SEL_8KB_SHIFT        10
34619 #define PXP_HW_PXP_LUT_CTRL_RSVD1_MASK           0xF800u
34620 #define PXP_HW_PXP_LUT_CTRL_RSVD1_SHIFT          11
34621 #define PXP_HW_PXP_LUT_CTRL_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD1_MASK)
34622 #define PXP_HW_PXP_LUT_CTRL_OUT_MODE_MASK        0x30000u
34623 #define PXP_HW_PXP_LUT_CTRL_OUT_MODE_SHIFT       16
34624 #define PXP_HW_PXP_LUT_CTRL_OUT_MODE(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_OUT_MODE_SHIFT))&PXP_HW_PXP_LUT_CTRL_OUT_MODE_MASK)
34625 #define PXP_HW_PXP_LUT_CTRL_RSVD2_MASK           0xFC0000u
34626 #define PXP_HW_PXP_LUT_CTRL_RSVD2_SHIFT          18
34627 #define PXP_HW_PXP_LUT_CTRL_RSVD2(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD2_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD2_MASK)
34628 #define PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_MASK     0x3000000u
34629 #define PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_SHIFT    24
34630 #define PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_SHIFT))&PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_MASK)
34631 #define PXP_HW_PXP_LUT_CTRL_RSVD3_MASK           0x7C000000u
34632 #define PXP_HW_PXP_LUT_CTRL_RSVD3_SHIFT          26
34633 #define PXP_HW_PXP_LUT_CTRL_RSVD3(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD3_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD3_MASK)
34634 #define PXP_HW_PXP_LUT_CTRL_BYPASS_MASK          0x80000000u
34635 #define PXP_HW_PXP_LUT_CTRL_BYPASS_SHIFT         31
34636 /* HW_PXP_LUT_ADDR Bit Fields */
34637 #define PXP_HW_PXP_LUT_ADDR_ADDR_MASK            0x3FFFu
34638 #define PXP_HW_PXP_LUT_ADDR_ADDR_SHIFT           0
34639 #define PXP_HW_PXP_LUT_ADDR_ADDR(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_ADDR_ADDR_SHIFT))&PXP_HW_PXP_LUT_ADDR_ADDR_MASK)
34640 #define PXP_HW_PXP_LUT_ADDR_RSVD1_MASK           0xC000u
34641 #define PXP_HW_PXP_LUT_ADDR_RSVD1_SHIFT          14
34642 #define PXP_HW_PXP_LUT_ADDR_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_ADDR_RSVD1_SHIFT))&PXP_HW_PXP_LUT_ADDR_RSVD1_MASK)
34643 #define PXP_HW_PXP_LUT_ADDR_NUM_BYTES_MASK       0x7FFF0000u
34644 #define PXP_HW_PXP_LUT_ADDR_NUM_BYTES_SHIFT      16
34645 #define PXP_HW_PXP_LUT_ADDR_NUM_BYTES(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_ADDR_NUM_BYTES_SHIFT))&PXP_HW_PXP_LUT_ADDR_NUM_BYTES_MASK)
34646 #define PXP_HW_PXP_LUT_ADDR_RSVD2_MASK           0x80000000u
34647 #define PXP_HW_PXP_LUT_ADDR_RSVD2_SHIFT          31
34648 /* HW_PXP_LUT_DATA Bit Fields */
34649 #define PXP_HW_PXP_LUT_DATA_DATA_MASK            0xFFFFFFFFu
34650 #define PXP_HW_PXP_LUT_DATA_DATA_SHIFT           0
34651 #define PXP_HW_PXP_LUT_DATA_DATA(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_DATA_DATA_SHIFT))&PXP_HW_PXP_LUT_DATA_DATA_MASK)
34652 /* HW_PXP_LUT_EXTMEM Bit Fields */
34653 #define PXP_HW_PXP_LUT_EXTMEM_ADDR_MASK          0xFFFFFFFFu
34654 #define PXP_HW_PXP_LUT_EXTMEM_ADDR_SHIFT         0
34655 #define PXP_HW_PXP_LUT_EXTMEM_ADDR(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_EXTMEM_ADDR_SHIFT))&PXP_HW_PXP_LUT_EXTMEM_ADDR_MASK)
34656 /* HW_PXP_CFA Bit Fields */
34657 #define PXP_HW_PXP_CFA_DATA_MASK                 0xFFFFFFFFu
34658 #define PXP_HW_PXP_CFA_DATA_SHIFT                0
34659 #define PXP_HW_PXP_CFA_DATA(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CFA_DATA_SHIFT))&PXP_HW_PXP_CFA_DATA_MASK)
34660 /* HW_PXP_ALPHA_A_CTRL Bit Fields */
34661 #define PXP_HW_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK 0x1u
34662 #define PXP_HW_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT 0
34663 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK 0x6u
34664 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT 1
34665 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK)
34666 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK 0x18u
34667 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT 3
34668 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
34669 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK 0x20u
34670 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT 5
34671 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK 0x40u
34672 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT 6
34673 #define PXP_HW_PXP_ALPHA_A_CTRL_RSVD1_MASK       0x80u
34674 #define PXP_HW_PXP_ALPHA_A_CTRL_RSVD1_SHIFT      7
34675 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK 0x300u
34676 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT 8
34677 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK)
34678 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK 0xC00u
34679 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT 10
34680 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
34681 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK 0x1000u
34682 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT 12
34683 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK 0x2000u
34684 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT 13
34685 #define PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_MASK       0xC000u
34686 #define PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_SHIFT      14
34687 #define PXP_HW_PXP_ALPHA_A_CTRL_RSVD0(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_MASK)
34688 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK 0xFF0000u
34689 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT 16
34690 #define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK)
34691 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK 0xFF000000u
34692 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT 24
34693 #define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK)
34694 /* HW_PXP_ALPHA_B_CTRL Bit Fields */
34695 #define PXP_HW_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE_MASK 0x1u
34696 #define PXP_HW_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE_SHIFT 0
34697 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_MASK 0x6u
34698 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_SHIFT 1
34699 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_MASK)
34700 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_MASK 0x18u
34701 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT 3
34702 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
34703 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_MASK 0x20u
34704 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_SHIFT 5
34705 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_COLOR_MODE_MASK 0x40u
34706 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_COLOR_MODE_SHIFT 6
34707 #define PXP_HW_PXP_ALPHA_B_CTRL_RSVD1_MASK       0x80u
34708 #define PXP_HW_PXP_ALPHA_B_CTRL_RSVD1_SHIFT      7
34709 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_MASK 0x300u
34710 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_SHIFT 8
34711 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_MASK)
34712 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_MASK 0xC00u
34713 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT 10
34714 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
34715 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_MASK 0x1000u
34716 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_SHIFT 12
34717 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_COLOR_MODE_MASK 0x2000u
34718 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_COLOR_MODE_SHIFT 13
34719 #define PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_MASK       0xC000u
34720 #define PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_SHIFT      14
34721 #define PXP_HW_PXP_ALPHA_B_CTRL_RSVD0(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_MASK)
34722 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MASK 0xFF0000u
34723 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_SHIFT 16
34724 #define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MASK)
34725 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MASK 0xFF000000u
34726 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_SHIFT 24
34727 #define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MASK)
34728 /* HW_PXP_ALPHA_B_CTRL_1 Bit Fields */
34729 #define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK 0x1u
34730 #define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_ENABLE_SHIFT 0
34731 #define PXP_HW_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK 0x2u
34732 #define PXP_HW_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_SHIFT 1
34733 #define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_MASK     0xCu
34734 #define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_SHIFT    2
34735 #define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_MASK)
34736 #define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_MASK       0xF0u
34737 #define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_SHIFT      4
34738 #define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_MASK)
34739 #define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_MASK     0xFFFFFF00u
34740 #define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_SHIFT    8
34741 #define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_MASK)
34742 /* HW_PXP_PS_BACKGROUND_1 Bit Fields */
34743 #define PXP_HW_PXP_PS_BACKGROUND_1_COLOR_MASK    0xFFFFFFu
34744 #define PXP_HW_PXP_PS_BACKGROUND_1_COLOR_SHIFT   0
34745 #define PXP_HW_PXP_PS_BACKGROUND_1_COLOR(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_1_COLOR_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_1_COLOR_MASK)
34746 #define PXP_HW_PXP_PS_BACKGROUND_1_RSVD_MASK     0xFF000000u
34747 #define PXP_HW_PXP_PS_BACKGROUND_1_RSVD_SHIFT    24
34748 #define PXP_HW_PXP_PS_BACKGROUND_1_RSVD(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_1_RSVD_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_1_RSVD_MASK)
34749 /* HW_PXP_PS_CLRKEYLOW_1 Bit Fields */
34750 #define PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_MASK     0xFFFFFFu
34751 #define PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT    0
34752 #define PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_MASK)
34753 #define PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_MASK     0xFF000000u
34754 #define PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_SHIFT    24
34755 #define PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_MASK)
34756 /* HW_PXP_PS_CLRKEYHIGH_1 Bit Fields */
34757 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_MASK    0xFFFFFFu
34758 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT   0
34759 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_MASK)
34760 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_MASK    0xFF000000u
34761 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_SHIFT   24
34762 #define PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_MASK)
34763 /* HW_PXP_AS_CLRKEYLOW_1 Bit Fields */
34764 #define PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_MASK     0xFFFFFFu
34765 #define PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT    0
34766 #define PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_MASK)
34767 #define PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_MASK     0xFF000000u
34768 #define PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_SHIFT    24
34769 #define PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_MASK)
34770 /* HW_PXP_AS_CLRKEYHIGH_1 Bit Fields */
34771 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_MASK    0xFFFFFFu
34772 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT   0
34773 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_MASK)
34774 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_MASK    0xFF000000u
34775 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_SHIFT   24
34776 #define PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_MASK)
34777 /* HW_PXP_CTRL2 Bit Fields */
34778 #define PXP_HW_PXP_CTRL2_ENABLE_MASK             0x1u
34779 #define PXP_HW_PXP_CTRL2_ENABLE_SHIFT            0
34780 #define PXP_HW_PXP_CTRL2_RSVD0_MASK              0xFEu
34781 #define PXP_HW_PXP_CTRL2_RSVD0_SHIFT             1
34782 #define PXP_HW_PXP_CTRL2_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_RSVD0_SHIFT))&PXP_HW_PXP_CTRL2_RSVD0_MASK)
34783 #define PXP_HW_PXP_CTRL2_ROTATE0_MASK            0x300u
34784 #define PXP_HW_PXP_CTRL2_ROTATE0_SHIFT           8
34785 #define PXP_HW_PXP_CTRL2_ROTATE0(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_ROTATE0_SHIFT))&PXP_HW_PXP_CTRL2_ROTATE0_MASK)
34786 #define PXP_HW_PXP_CTRL2_HFLIP0_MASK             0x400u
34787 #define PXP_HW_PXP_CTRL2_HFLIP0_SHIFT            10
34788 #define PXP_HW_PXP_CTRL2_VFLIP0_MASK             0x800u
34789 #define PXP_HW_PXP_CTRL2_VFLIP0_SHIFT            11
34790 #define PXP_HW_PXP_CTRL2_ROTATE1_MASK            0x3000u
34791 #define PXP_HW_PXP_CTRL2_ROTATE1_SHIFT           12
34792 #define PXP_HW_PXP_CTRL2_ROTATE1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_ROTATE1_SHIFT))&PXP_HW_PXP_CTRL2_ROTATE1_MASK)
34793 #define PXP_HW_PXP_CTRL2_HFLIP1_MASK             0x4000u
34794 #define PXP_HW_PXP_CTRL2_HFLIP1_SHIFT            14
34795 #define PXP_HW_PXP_CTRL2_VFLIP1_MASK             0x8000u
34796 #define PXP_HW_PXP_CTRL2_VFLIP1_SHIFT            15
34797 #define PXP_HW_PXP_CTRL2_RSVD1_MASK              0x10000u
34798 #define PXP_HW_PXP_CTRL2_RSVD1_SHIFT             16
34799 #define PXP_HW_PXP_CTRL2_ENABLE_DITHER_MASK      0x20000u
34800 #define PXP_HW_PXP_CTRL2_ENABLE_DITHER_SHIFT     17
34801 #define PXP_HW_PXP_CTRL2_ENABLE_WFE_A_MASK       0x40000u
34802 #define PXP_HW_PXP_CTRL2_ENABLE_WFE_A_SHIFT      18
34803 #define PXP_HW_PXP_CTRL2_ENABLE_WFE_B_MASK       0x80000u
34804 #define PXP_HW_PXP_CTRL2_ENABLE_WFE_B_SHIFT      19
34805 #define PXP_HW_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_MASK 0x100000u
34806 #define PXP_HW_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_SHIFT 20
34807 #define PXP_HW_PXP_CTRL2_ENABLE_ALPHA_B_MASK     0x200000u
34808 #define PXP_HW_PXP_CTRL2_ENABLE_ALPHA_B_SHIFT    21
34809 #define PXP_HW_PXP_CTRL2_RSVD2_MASK              0x400000u
34810 #define PXP_HW_PXP_CTRL2_RSVD2_SHIFT             22
34811 #define PXP_HW_PXP_CTRL2_BLOCK_SIZE_MASK         0x800000u
34812 #define PXP_HW_PXP_CTRL2_BLOCK_SIZE_SHIFT        23
34813 #define PXP_HW_PXP_CTRL2_ENABLE_CSC2_MASK        0x1000000u
34814 #define PXP_HW_PXP_CTRL2_ENABLE_CSC2_SHIFT       24
34815 #define PXP_HW_PXP_CTRL2_ENABLE_LUT_MASK         0x2000000u
34816 #define PXP_HW_PXP_CTRL2_ENABLE_LUT_SHIFT        25
34817 #define PXP_HW_PXP_CTRL2_ENABLE_ROTATE0_MASK     0x4000000u
34818 #define PXP_HW_PXP_CTRL2_ENABLE_ROTATE0_SHIFT    26
34819 #define PXP_HW_PXP_CTRL2_ENABLE_ROTATE1_MASK     0x8000000u
34820 #define PXP_HW_PXP_CTRL2_ENABLE_ROTATE1_SHIFT    27
34821 #define PXP_HW_PXP_CTRL2_RSVD3_MASK              0xF0000000u
34822 #define PXP_HW_PXP_CTRL2_RSVD3_SHIFT             28
34823 #define PXP_HW_PXP_CTRL2_RSVD3(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_RSVD3_SHIFT))&PXP_HW_PXP_CTRL2_RSVD3_MASK)
34824 /* HW_PXP_POWER_REG0 Bit Fields */
34825 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK 0x7u
34826 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT 0
34827 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT))&PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK)
34828 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK 0x38u
34829 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT 3
34830 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT))&PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK)
34831 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK 0x1C0u
34832 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT 6
34833 #define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT))&PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK)
34834 #define PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK 0xE00u
34835 #define PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT 9
34836 #define PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK)
34837 #define PXP_HW_PXP_POWER_REG0_CTRL_MASK          0xFFFFF000u
34838 #define PXP_HW_PXP_POWER_REG0_CTRL_SHIFT         12
34839 #define PXP_HW_PXP_POWER_REG0_CTRL(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_CTRL_SHIFT))&PXP_HW_PXP_POWER_REG0_CTRL_MASK)
34840 /* HW_PXP_POWER_REG1 Bit Fields */
34841 #define PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK 0x7u
34842 #define PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT 0
34843 #define PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK)
34844 #define PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK 0x38u
34845 #define PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT 3
34846 #define PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK)
34847 #define PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK 0x1C0u
34848 #define PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT 6
34849 #define PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK)
34850 #define PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK 0xE00u
34851 #define PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT 9
34852 #define PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK)
34853 #define PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK 0x7000u
34854 #define PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT 12
34855 #define PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK)
34856 #define PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK 0x38000u
34857 #define PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT 15
34858 #define PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK)
34859 #define PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK 0x1C0000u
34860 #define PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT 18
34861 #define PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK)
34862 #define PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK 0xE00000u
34863 #define PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT 21
34864 #define PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK)
34865 #define PXP_HW_PXP_POWER_REG1_RSVD0_MASK         0xFF000000u
34866 #define PXP_HW_PXP_POWER_REG1_RSVD0_SHIFT        24
34867 #define PXP_HW_PXP_POWER_REG1_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_RSVD0_SHIFT))&PXP_HW_PXP_POWER_REG1_RSVD0_MASK)
34868 /* HW_PXP_DATA_PATH_CTRL0 Bit Fields */
34869 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK 0x3u
34870 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT 0
34871 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK)
34872 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK 0xCu
34873 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT 2
34874 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK)
34875 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_MASK 0x30u
34876 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_SHIFT 4
34877 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_MASK)
34878 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK 0xC0u
34879 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT 6
34880 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)
34881 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_MASK 0x300u
34882 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_SHIFT 8
34883 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_MASK)
34884 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_MASK 0xC00u
34885 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_SHIFT 10
34886 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_MASK)
34887 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_MASK 0x3000u
34888 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_SHIFT 12
34889 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_MASK)
34890 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_MASK 0xC000u
34891 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_SHIFT 14
34892 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_MASK)
34893 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK 0x30000u
34894 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT 16
34895 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK)
34896 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK 0xC0000u
34897 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT 18
34898 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK)
34899 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_MASK 0x300000u
34900 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_SHIFT 20
34901 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_MASK)
34902 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK 0xC00000u
34903 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT 22
34904 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK)
34905 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK 0x3000000u
34906 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT 24
34907 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)
34908 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_MASK 0xC000000u
34909 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_SHIFT 26
34910 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_MASK)
34911 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK 0x30000000u
34912 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT 28
34913 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK)
34914 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK 0xC0000000u
34915 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT 30
34916 #define PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK)
34917 /* HW_PXP_DATA_PATH_CTRL1 Bit Fields */
34918 #define PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK 0x3u
34919 #define PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT 0
34920 #define PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK)
34921 #define PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK 0xCu
34922 #define PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT 2
34923 #define PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK)
34924 #define PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_MASK    0xFFFFFFF0u
34925 #define PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_SHIFT   4
34926 #define PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_MASK)
34927 /* HW_PXP_INIT_MEM_CTRL Bit Fields */
34928 #define PXP_HW_PXP_INIT_MEM_CTRL_ADDR_MASK       0xFFFFu
34929 #define PXP_HW_PXP_INIT_MEM_CTRL_ADDR_SHIFT      0
34930 #define PXP_HW_PXP_INIT_MEM_CTRL_ADDR(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_CTRL_ADDR_SHIFT))&PXP_HW_PXP_INIT_MEM_CTRL_ADDR_MASK)
34931 #define PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_MASK      0x7FF0000u
34932 #define PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_SHIFT     16
34933 #define PXP_HW_PXP_INIT_MEM_CTRL_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_MASK)
34934 #define PXP_HW_PXP_INIT_MEM_CTRL_SELECT_MASK     0x78000000u
34935 #define PXP_HW_PXP_INIT_MEM_CTRL_SELECT_SHIFT    27
34936 #define PXP_HW_PXP_INIT_MEM_CTRL_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_CTRL_SELECT_SHIFT))&PXP_HW_PXP_INIT_MEM_CTRL_SELECT_MASK)
34937 #define PXP_HW_PXP_INIT_MEM_CTRL_START_MASK      0x80000000u
34938 #define PXP_HW_PXP_INIT_MEM_CTRL_START_SHIFT     31
34939 /* HW_PXP_INIT_MEM_DATA Bit Fields */
34940 #define PXP_HW_PXP_INIT_MEM_DATA_DATA_MASK       0xFFFFFFFFu
34941 #define PXP_HW_PXP_INIT_MEM_DATA_DATA_SHIFT      0
34942 #define PXP_HW_PXP_INIT_MEM_DATA_DATA(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_DATA_DATA_SHIFT))&PXP_HW_PXP_INIT_MEM_DATA_DATA_MASK)
34943 /* HW_PXP_INIT_MEM_DATA_HIGH Bit Fields */
34944 #define PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_MASK  0xFFFFFFFFu
34945 #define PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT 0
34946 #define PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT))&PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_MASK)
34947 /* HW_PXP_IRQ_MASK Bit Fields */
34948 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK 0x1u
34949 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT 0
34950 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK 0x2u
34951 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT 1
34952 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK 0x4u
34953 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_SHIFT 2
34954 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK 0x8u
34955 #define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_SHIFT 3
34956 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK 0x10u
34957 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT 4
34958 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK 0x20u
34959 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT 5
34960 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK 0x40u
34961 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_SHIFT 6
34962 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK 0x80u
34963 #define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_SHIFT 7
34964 #define PXP_HW_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK 0x100u
34965 #define PXP_HW_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_SHIFT 8
34966 #define PXP_HW_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK 0x200u
34967 #define PXP_HW_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_SHIFT 9
34968 #define PXP_HW_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK 0x400u
34969 #define PXP_HW_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT 10
34970 #define PXP_HW_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK 0x800u
34971 #define PXP_HW_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT 11
34972 #define PXP_HW_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK 0x1000u
34973 #define PXP_HW_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_SHIFT 12
34974 #define PXP_HW_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK 0x2000u
34975 #define PXP_HW_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_SHIFT 13
34976 #define PXP_HW_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK 0x4000u
34977 #define PXP_HW_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_SHIFT 14
34978 #define PXP_HW_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK 0x8000u
34979 #define PXP_HW_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT 15
34980 #define PXP_HW_PXP_IRQ_MASK_RSVD1_MASK           0x7FFF0000u
34981 #define PXP_HW_PXP_IRQ_MASK_RSVD1_SHIFT          16
34982 #define PXP_HW_PXP_IRQ_MASK_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_IRQ_MASK_RSVD1_SHIFT))&PXP_HW_PXP_IRQ_MASK_RSVD1_MASK)
34983 #define PXP_HW_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK 0x80000000u
34984 #define PXP_HW_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_SHIFT 31
34985 /* HW_PXP_IRQ Bit Fields */
34986 #define PXP_HW_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK 0x1u
34987 #define PXP_HW_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_SHIFT 0
34988 #define PXP_HW_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK 0x2u
34989 #define PXP_HW_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_SHIFT 1
34990 #define PXP_HW_PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK  0x4u
34991 #define PXP_HW_PXP_IRQ_FIRST_CH0_STORE_IRQ_SHIFT 2
34992 #define PXP_HW_PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK  0x8u
34993 #define PXP_HW_PXP_IRQ_FIRST_CH1_STORE_IRQ_SHIFT 3
34994 #define PXP_HW_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK 0x10u
34995 #define PXP_HW_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_SHIFT 4
34996 #define PXP_HW_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK 0x20u
34997 #define PXP_HW_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_SHIFT 5
34998 #define PXP_HW_PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK 0x40u
34999 #define PXP_HW_PXP_IRQ_DITHER_CH0_STORE_IRQ_SHIFT 6
35000 #define PXP_HW_PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK 0x80u
35001 #define PXP_HW_PXP_IRQ_DITHER_CH1_STORE_IRQ_SHIFT 7
35002 #define PXP_HW_PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK  0x100u
35003 #define PXP_HW_PXP_IRQ_WFE_A_CH0_STORE_IRQ_SHIFT 8
35004 #define PXP_HW_PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK  0x200u
35005 #define PXP_HW_PXP_IRQ_WFE_A_CH1_STORE_IRQ_SHIFT 9
35006 #define PXP_HW_PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK  0x400u
35007 #define PXP_HW_PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT 10
35008 #define PXP_HW_PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK  0x800u
35009 #define PXP_HW_PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT 11
35010 #define PXP_HW_PXP_IRQ_FIRST_STORE_IRQ_MASK      0x1000u
35011 #define PXP_HW_PXP_IRQ_FIRST_STORE_IRQ_SHIFT     12
35012 #define PXP_HW_PXP_IRQ_DITHER_STORE_IRQ_MASK     0x2000u
35013 #define PXP_HW_PXP_IRQ_DITHER_STORE_IRQ_SHIFT    13
35014 #define PXP_HW_PXP_IRQ_WFE_A_STORE_IRQ_MASK      0x4000u
35015 #define PXP_HW_PXP_IRQ_WFE_A_STORE_IRQ_SHIFT     14
35016 #define PXP_HW_PXP_IRQ_WFE_B_STORE_IRQ_MASK      0x8000u
35017 #define PXP_HW_PXP_IRQ_WFE_B_STORE_IRQ_SHIFT     15
35018 #define PXP_HW_PXP_IRQ_RSVD1_MASK                0x7FFF0000u
35019 #define PXP_HW_PXP_IRQ_RSVD1_SHIFT               16
35020 #define PXP_HW_PXP_IRQ_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_IRQ_RSVD1_SHIFT))&PXP_HW_PXP_IRQ_RSVD1_MASK)
35021 #define PXP_HW_PXP_IRQ_COMPRESS_DONE_IRQ_MASK    0x80000000u
35022 #define PXP_HW_PXP_IRQ_COMPRESS_DONE_IRQ_SHIFT   31
35023 /* HW_PXP_NEXT Bit Fields */
35024 #define PXP_HW_PXP_NEXT_ENABLED_MASK             0x1u
35025 #define PXP_HW_PXP_NEXT_ENABLED_SHIFT            0
35026 #define PXP_HW_PXP_NEXT_RSVD_MASK                0x2u
35027 #define PXP_HW_PXP_NEXT_RSVD_SHIFT               1
35028 #define PXP_HW_PXP_NEXT_POINTER_MASK             0xFFFFFFFCu
35029 #define PXP_HW_PXP_NEXT_POINTER_SHIFT            2
35030 #define PXP_HW_PXP_NEXT_POINTER(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_NEXT_POINTER_SHIFT))&PXP_HW_PXP_NEXT_POINTER_MASK)
35031 /* HW_PXP_INPUT_FETCH_CTRL_CH0 Bit Fields */
35032 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK 0x1u
35033 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_CH_EN_SHIFT 0
35034 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_MASK 0x2u
35035 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_SHIFT 1
35036 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_MASK 0x4u
35037 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_SHIFT 2
35038 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u
35039 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT 3
35040 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK 0x10u
35041 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT 4
35042 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_MASK 0x20u
35043 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT 5
35044 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_MASK 0x1C0u
35045 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_SHIFT 6
35046 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_MASK)
35047 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HFLIP_MASK 0x200u
35048 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT 9
35049 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_VFLIP_MASK 0x400u
35050 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_VFLIP_SHIFT 10
35051 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD3_MASK 0x800u
35052 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD3_SHIFT 11
35053 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK 0x3000u
35054 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT 12
35055 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK)
35056 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_MASK 0xC000u
35057 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_SHIFT 14
35058 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_MASK)
35059 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK 0x30000u
35060 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT 16
35061 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK)
35062 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_MASK 0xFC0000u
35063 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_SHIFT 18
35064 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_MASK)
35065 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u
35066 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24
35067 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK)
35068 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_MASK 0x7C000000u
35069 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_SHIFT 26
35070 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_MASK)
35071 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_MASK 0x80000000u
35072 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_SHIFT 31
35073 /* HW_PXP_INPUT_FETCH_CTRL_CH1 Bit Fields */
35074 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK 0x1u
35075 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_CH_EN_SHIFT 0
35076 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_MASK 0x2u
35077 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_SHIFT 1
35078 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_MASK 0x4u
35079 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_SHIFT 2
35080 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u
35081 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT 3
35082 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK 0x10u
35083 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT 4
35084 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_MASK 0x1E0u
35085 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_SHIFT 5
35086 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_MASK)
35087 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HFLIP_MASK 0x200u
35088 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HFLIP_SHIFT 9
35089 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_VFLIP_MASK 0x400u
35090 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_VFLIP_SHIFT 10
35091 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD3_MASK 0x800u
35092 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD3_SHIFT 11
35093 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK 0x3000u
35094 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT 12
35095 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK)
35096 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_MASK 0xC000u
35097 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_SHIFT 14
35098 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_MASK)
35099 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK 0x30000u
35100 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT 16
35101 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK)
35102 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_MASK 0xFC0000u
35103 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_SHIFT 18
35104 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_MASK)
35105 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u
35106 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24
35107 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK)
35108 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_MASK 0xFC000000u
35109 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_SHIFT 26
35110 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_MASK)
35111 /* HW_PXP_INPUT_FETCH_STATUS_CH0 Bit Fields */
35112 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK 0xFFFFu
35113 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT 0
35114 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK)
35115 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u
35116 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT 16
35117 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK)
35118 /* HW_PXP_INPUT_FETCH_STATUS_CH1 Bit Fields */
35119 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK 0xFFFFu
35120 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT 0
35121 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK)
35122 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u
35123 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT 16
35124 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK)
35125 /* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 Bit Fields */
35126 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu
35127 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT 0
35128 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK)
35129 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u
35130 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT 16
35131 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK)
35132 /* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 Bit Fields */
35133 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu
35134 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT 0
35135 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK)
35136 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u
35137 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT 16
35138 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK)
35139 /* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 Bit Fields */
35140 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu
35141 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT 0
35142 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK)
35143 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u
35144 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT 16
35145 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK)
35146 /* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 Bit Fields */
35147 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu
35148 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT 0
35149 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK)
35150 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u
35151 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT 16
35152 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK)
35153 /* HW_PXP_INPUT_FETCH_SIZE_CH0 Bit Fields */
35154 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK 0xFFFFu
35155 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT 0
35156 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK)
35157 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u
35158 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT 16
35159 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK)
35160 /* HW_PXP_INPUT_FETCH_SIZE_CH1 Bit Fields */
35161 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK 0xFFFFu
35162 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT 0
35163 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK)
35164 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u
35165 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT 16
35166 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK)
35167 /* HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 Bit Fields */
35168 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK 0xFFFFFFFFu
35169 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT 0
35170 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK)
35171 /* HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 Bit Fields */
35172 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK 0xFFFFFFFFu
35173 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT 0
35174 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK)
35175 /* HW_PXP_INPUT_FETCH_PITCH Bit Fields */
35176 #define PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK 0xFFFFu
35177 #define PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT 0
35178 #define PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK)
35179 #define PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK 0xFFFF0000u
35180 #define PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT 16
35181 #define PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK)
35182 /* HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 Bit Fields */
35183 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK 0x3u
35184 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT 0
35185 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK)
35186 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK 0xFCu
35187 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT 2
35188 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK)
35189 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK 0x700u
35190 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT 8
35191 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK)
35192 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK 0x800u
35193 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT 11
35194 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x1000u
35195 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 12
35196 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFE000u
35197 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT 13
35198 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK)
35199 /* HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 Bit Fields */
35200 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK 0x3u
35201 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT 0
35202 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK)
35203 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK 0xFCu
35204 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT 2
35205 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK)
35206 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK 0x700u
35207 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT 8
35208 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK)
35209 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK 0x800u
35210 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT 11
35211 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK 0x1000u
35212 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT 12
35213 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFE000u
35214 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT 13
35215 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK)
35216 /* HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 Bit Fields */
35217 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK 0x1Fu
35218 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT 0
35219 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK)
35220 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK 0xE0u
35221 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT 5
35222 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK)
35223 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK 0x1F00u
35224 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT 8
35225 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK)
35226 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK 0xE000u
35227 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT 13
35228 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK)
35229 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK 0x1F0000u
35230 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT 16
35231 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK)
35232 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK 0xE00000u
35233 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT 21
35234 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK)
35235 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK 0x1F000000u
35236 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT 24
35237 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK)
35238 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK 0xE0000000u
35239 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT 29
35240 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK)
35241 /* HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 Bit Fields */
35242 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK 0x1Fu
35243 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT 0
35244 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK)
35245 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK 0xE0u
35246 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT 5
35247 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK)
35248 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK 0x1F00u
35249 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT 8
35250 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK)
35251 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK 0xE000u
35252 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT 13
35253 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK)
35254 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK 0x1F0000u
35255 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT 16
35256 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK)
35257 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK 0xE00000u
35258 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT 21
35259 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK)
35260 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK 0x1F000000u
35261 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT 24
35262 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK)
35263 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK 0xE0000000u
35264 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT 29
35265 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK)
35266 /* HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 Bit Fields */
35267 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK 0xFu
35268 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT 0
35269 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK)
35270 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK 0xF0u
35271 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT 4
35272 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK)
35273 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK 0xF00u
35274 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT 8
35275 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK)
35276 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK 0xF000u
35277 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT 12
35278 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK)
35279 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK 0xFFFF0000u
35280 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT 16
35281 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK)
35282 /* HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 Bit Fields */
35283 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK 0xFu
35284 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT 0
35285 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK)
35286 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK 0xF0u
35287 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT 4
35288 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK)
35289 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK 0xF00u
35290 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT 8
35291 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK)
35292 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK 0xF000u
35293 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT 12
35294 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK)
35295 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK 0xFFFF0000u
35296 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT 16
35297 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK)
35298 /* HW_PXP_INPUT_FETCH_ADDR_0_CH0 Bit Fields */
35299 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu
35300 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT 0
35301 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK)
35302 /* HW_PXP_INPUT_FETCH_ADDR_1_CH0 Bit Fields */
35303 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu
35304 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT 0
35305 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK)
35306 /* HW_PXP_INPUT_FETCH_ADDR_0_CH1 Bit Fields */
35307 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu
35308 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT 0
35309 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK)
35310 /* HW_PXP_INPUT_FETCH_ADDR_1_CH1 Bit Fields */
35311 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu
35312 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT 0
35313 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK)
35314 /* HW_PXP_INPUT_STORE_CTRL_CH0 Bit Fields */
35315 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK 0x1u
35316 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_CH_EN_SHIFT 0
35317 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_MASK 0x2u
35318 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_SHIFT 1
35319 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_MASK 0x4u
35320 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_SHIFT 2
35321 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u
35322 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT 3
35323 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_MASK 0x10u
35324 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_SHIFT 4
35325 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK 0x60u
35326 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT 5
35327 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK)
35328 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD3_MASK 0x80u
35329 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD3_SHIFT 7
35330 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK 0x100u
35331 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT 8
35332 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK 0x200u
35333 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT 9
35334 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_MASK 0x400u
35335 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT 10
35336 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_MASK 0x800u
35337 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT 11
35338 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_MASK 0xF000u
35339 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_SHIFT 12
35340 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_MASK)
35341 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_MASK 0x30000u
35342 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT 16
35343 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_MASK)
35344 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_MASK 0xFC0000u
35345 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_SHIFT 18
35346 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_MASK)
35347 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK 0x1000000u
35348 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT 24
35349 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_MASK 0x7E000000u
35350 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_SHIFT 25
35351 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_MASK)
35352 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_MASK 0x80000000u
35353 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_SHIFT 31
35354 /* HW_PXP_INPUT_STORE_CTRL_CH1 Bit Fields */
35355 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK 0x1u
35356 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_CH_EN_SHIFT 0
35357 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_MASK 0x2u
35358 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_SHIFT 1
35359 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_MASK 0x4u
35360 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_SHIFT 2
35361 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u
35362 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT 3
35363 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_MASK 0x10u
35364 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_SHIFT 4
35365 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK 0x60u
35366 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT 5
35367 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK)
35368 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD3_MASK 0x80u
35369 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD3_SHIFT 7
35370 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK 0x100u
35371 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT 8
35372 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK 0x200u
35373 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT 9
35374 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_MASK 0x400u
35375 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT 10
35376 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_MASK 0xF800u
35377 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_SHIFT 11
35378 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_MASK)
35379 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK 0x30000u
35380 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT 16
35381 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK)
35382 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_MASK 0xFFFC0000u
35383 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_SHIFT 18
35384 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_MASK)
35385 /* HW_PXP_INPUT_STORE_STATUS_CH0 Bit Fields */
35386 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_MASK 0xFFFFu
35387 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT 0
35388 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_MASK)
35389 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK 0xFFFF0000u
35390 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT 16
35391 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK)
35392 /* HW_PXP_INPUT_STORE_STATUS_CH1 Bit Fields */
35393 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_MASK 0xFFFFu
35394 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT 0
35395 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_MASK)
35396 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK 0xFFFF0000u
35397 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT 16
35398 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK)
35399 /* HW_PXP_INPUT_STORE_SIZE_CH0 Bit Fields */
35400 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_MASK 0xFFFFu
35401 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_SHIFT 0
35402 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_MASK)
35403 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_MASK 0xFFFF0000u
35404 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT 16
35405 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_MASK)
35406 /* HW_PXP_INPUT_STORE_SIZE_CH1 Bit Fields */
35407 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_MASK 0xFFFFu
35408 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_SHIFT 0
35409 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_MASK)
35410 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_MASK 0xFFFF0000u
35411 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT 16
35412 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_MASK)
35413 /* HW_PXP_INPUT_STORE_PITCH Bit Fields */
35414 #define PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK 0xFFFFu
35415 #define PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_SHIFT 0
35416 #define PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK)
35417 #define PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_MASK 0xFFFF0000u
35418 #define PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_SHIFT 16
35419 #define PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_MASK)
35420 /* HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 Bit Fields */
35421 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_MASK 0x3u
35422 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT 0
35423 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_MASK)
35424 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK 0xCu
35425 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT 2
35426 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK)
35427 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK 0x10u
35428 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT 4
35429 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK 0x20u
35430 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT 5
35431 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_MASK 0x40u
35432 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT 6
35433 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x80u
35434 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 7
35435 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFFF00u
35436 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT 8
35437 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_MASK)
35438 /* HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 Bit Fields */
35439 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_MASK 0x3u
35440 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT 0
35441 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_MASK)
35442 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK 0xCu
35443 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT 2
35444 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK)
35445 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK 0x10u
35446 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT 4
35447 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK 0x20u
35448 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT 5
35449 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFFFC0u
35450 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT 6
35451 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_MASK)
35452 /* HW_PXP_INPUT_STORE_ADDR_0_CH0 Bit Fields */
35453 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu
35454 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT 0
35455 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK)
35456 /* HW_PXP_INPUT_STORE_ADDR_1_CH0 Bit Fields */
35457 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu
35458 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT 0
35459 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK)
35460 /* HW_PXP_INPUT_STORE_FILL_DATA_CH0 Bit Fields */
35461 #define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK 0xFFFFFFFFu
35462 #define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT 0
35463 #define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK)
35464 /* HW_PXP_INPUT_STORE_ADDR_0_CH1 Bit Fields */
35465 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu
35466 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT 0
35467 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK)
35468 /* HW_PXP_INPUT_STORE_ADDR_1_CH1 Bit Fields */
35469 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu
35470 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT 0
35471 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK)
35472 /* HW_PXP_INPUT_STORE_D_MASK0_H_CH0 Bit Fields */
35473 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK 0xFFFFFFFFu
35474 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT 0
35475 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK)
35476 /* HW_PXP_INPUT_STORE_D_MASK0_L_CH0 Bit Fields */
35477 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK 0xFFFFFFFFu
35478 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT 0
35479 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK)
35480 /* HW_PXP_INPUT_STORE_D_MASK1_H_CH0 Bit Fields */
35481 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK 0xFFFFFFFFu
35482 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT 0
35483 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK)
35484 /* HW_PXP_INPUT_STORE_D_MASK1_L_CH0 Bit Fields */
35485 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK 0xFFFFFFFFu
35486 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT 0
35487 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK)
35488 /* HW_PXP_INPUT_STORE_D_MASK2_H_CH0 Bit Fields */
35489 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK 0xFFFFFFFFu
35490 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT 0
35491 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK)
35492 /* HW_PXP_INPUT_STORE_D_MASK2_L_CH0 Bit Fields */
35493 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK 0xFFFFFFFFu
35494 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT 0
35495 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK)
35496 /* HW_PXP_INPUT_STORE_D_MASK3_H_CH0 Bit Fields */
35497 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK 0xFFFFFFFFu
35498 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT 0
35499 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK)
35500 /* HW_PXP_INPUT_STORE_D_MASK3_L_CH0 Bit Fields */
35501 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK 0xFFFFFFFFu
35502 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT 0
35503 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK)
35504 /* HW_PXP_INPUT_STORE_D_MASK4_H_CH0 Bit Fields */
35505 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK 0xFFFFFFFFu
35506 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT 0
35507 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK)
35508 /* HW_PXP_INPUT_STORE_D_MASK4_L_CH0 Bit Fields */
35509 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK 0xFFFFFFFFu
35510 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT 0
35511 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK)
35512 /* HW_PXP_INPUT_STORE_D_MASK5_H_CH0 Bit Fields */
35513 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK 0xFFFFFFFFu
35514 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT 0
35515 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK)
35516 /* HW_PXP_INPUT_STORE_D_MASK5_L_CH0 Bit Fields */
35517 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK 0xFFFFFFFFu
35518 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT 0
35519 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK)
35520 /* HW_PXP_INPUT_STORE_D_MASK6_H_CH0 Bit Fields */
35521 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK 0xFFFFFFFFu
35522 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT 0
35523 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK)
35524 /* HW_PXP_INPUT_STORE_D_MASK6_L_CH0 Bit Fields */
35525 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK 0xFFFFFFFFu
35526 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT 0
35527 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK)
35528 /* HW_PXP_INPUT_STORE_D_MASK7_H_CH0 Bit Fields */
35529 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK 0xFFFFFFFFu
35530 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT 0
35531 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK)
35532 /* HW_PXP_INPUT_STORE_D_MASK7_L_CH0 Bit Fields */
35533 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK 0xFFFFFFFFu
35534 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT 0
35535 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK)
35536 /* HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 Bit Fields */
35537 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK 0x3Fu
35538 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT 0
35539 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK)
35540 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_MASK 0x40u
35541 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT 6
35542 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK 0x80u
35543 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT 7
35544 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK 0x3F00u
35545 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT 8
35546 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK)
35547 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_MASK 0x4000u
35548 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT 14
35549 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK 0x8000u
35550 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT 15
35551 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK 0x3F0000u
35552 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT 16
35553 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK)
35554 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_MASK 0x400000u
35555 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT 22
35556 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK 0x800000u
35557 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT 23
35558 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK 0x3F000000u
35559 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT 24
35560 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK)
35561 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_MASK 0x40000000u
35562 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT 30
35563 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK 0x80000000u
35564 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT 31
35565 /* HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 Bit Fields */
35566 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK 0x3Fu
35567 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT 0
35568 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK)
35569 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_MASK 0x40u
35570 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT 6
35571 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK 0x80u
35572 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT 7
35573 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK 0x3F00u
35574 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT 8
35575 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK)
35576 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_MASK 0x4000u
35577 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT 14
35578 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK 0x8000u
35579 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT 15
35580 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK 0x3F0000u
35581 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT 16
35582 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK)
35583 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_MASK 0x400000u
35584 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT 22
35585 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK 0x800000u
35586 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT 23
35587 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK 0x3F000000u
35588 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT 24
35589 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK)
35590 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_MASK 0x40000000u
35591 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT 30
35592 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK 0x80000000u
35593 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT 31
35594 /* HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 Bit Fields */
35595 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK 0x3Fu
35596 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT 0
35597 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK)
35598 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK 0x40u
35599 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT 6
35600 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_MASK 0x80u
35601 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT 7
35602 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK 0x3F00u
35603 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT 8
35604 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK)
35605 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK 0x4000u
35606 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT 14
35607 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_MASK 0x8000u
35608 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT 15
35609 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK 0x3F0000u
35610 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT 16
35611 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK)
35612 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK 0x400000u
35613 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT 22
35614 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_MASK 0x800000u
35615 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT 23
35616 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK 0x3F000000u
35617 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT 24
35618 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK)
35619 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK 0x40000000u
35620 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT 30
35621 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_MASK 0x80000000u
35622 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT 31
35623 /* HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 Bit Fields */
35624 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK 0x3Fu
35625 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT 0
35626 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK)
35627 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK 0x40u
35628 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT 6
35629 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_MASK 0x80u
35630 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT 7
35631 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK 0x3F00u
35632 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT 8
35633 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK)
35634 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK 0x4000u
35635 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT 14
35636 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_MASK 0x8000u
35637 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT 15
35638 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK 0x3F0000u
35639 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT 16
35640 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK)
35641 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK 0x400000u
35642 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT 22
35643 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_MASK 0x800000u
35644 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT 23
35645 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK 0x3F000000u
35646 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT 24
35647 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK)
35648 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK 0x40000000u
35649 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT 30
35650 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_MASK 0x80000000u
35651 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT 31
35652 /* HW_PXP_INPUT_STORE_F_MASK_L_CH0 Bit Fields */
35653 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_MASK 0xFFu
35654 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_SHIFT 0
35655 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_MASK)
35656 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_MASK 0xFF00u
35657 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_SHIFT 8
35658 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_MASK)
35659 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_MASK 0xFF0000u
35660 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_SHIFT 16
35661 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_MASK)
35662 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_MASK 0xFF000000u
35663 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_SHIFT 24
35664 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_MASK)
35665 /* HW_PXP_INPUT_STORE_F_MASK_H_CH0 Bit Fields */
35666 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_MASK 0xFFu
35667 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_SHIFT 0
35668 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_MASK)
35669 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_MASK 0xFF00u
35670 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_SHIFT 8
35671 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_MASK)
35672 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_MASK 0xFF0000u
35673 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_SHIFT 16
35674 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_MASK)
35675 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_MASK 0xFF000000u
35676 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_SHIFT 24
35677 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_MASK)
35678 /* HW_PXP_DITHER_FETCH_CTRL_CH0 Bit Fields */
35679 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK 0x1u
35680 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_CH_EN_SHIFT 0
35681 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_MASK 0x2u
35682 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_SHIFT 1
35683 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_MASK 0x4u
35684 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_SHIFT 2
35685 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u
35686 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT 3
35687 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK 0x10u
35688 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT 4
35689 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_MASK 0x20u
35690 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT 5
35691 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_MASK 0x1C0u
35692 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_SHIFT 6
35693 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_MASK)
35694 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HFLIP_MASK 0x200u
35695 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HFLIP_SHIFT 9
35696 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_VFLIP_MASK 0x400u
35697 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_VFLIP_SHIFT 10
35698 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD3_MASK 0x800u
35699 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD3_SHIFT 11
35700 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK 0x3000u
35701 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT 12
35702 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK)
35703 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_MASK 0xC000u
35704 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_SHIFT 14
35705 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_MASK)
35706 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK 0x30000u
35707 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT 16
35708 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK)
35709 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_MASK 0xFC0000u
35710 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_SHIFT 18
35711 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_MASK)
35712 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u
35713 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24
35714 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK)
35715 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_MASK 0x7C000000u
35716 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_SHIFT 26
35717 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_MASK)
35718 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_MASK 0x80000000u
35719 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_SHIFT 31
35720 /* HW_PXP_DITHER_FETCH_CTRL_CH1 Bit Fields */
35721 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK 0x1u
35722 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_CH_EN_SHIFT 0
35723 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_MASK 0x2u
35724 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_SHIFT 1
35725 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_MASK 0x4u
35726 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_SHIFT 2
35727 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u
35728 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT 3
35729 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK 0x10u
35730 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT 4
35731 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_MASK 0x1E0u
35732 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_SHIFT 5
35733 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_MASK)
35734 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HFLIP_MASK 0x200u
35735 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HFLIP_SHIFT 9
35736 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_VFLIP_MASK 0x400u
35737 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_VFLIP_SHIFT 10
35738 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD3_MASK 0x800u
35739 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD3_SHIFT 11
35740 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK 0x3000u
35741 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT 12
35742 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK)
35743 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_MASK 0xC000u
35744 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_SHIFT 14
35745 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_MASK)
35746 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK 0x30000u
35747 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT 16
35748 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK)
35749 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_MASK 0xFC0000u
35750 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_SHIFT 18
35751 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_MASK)
35752 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u
35753 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24
35754 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK)
35755 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_MASK 0xFC000000u
35756 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_SHIFT 26
35757 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_MASK)
35758 /* HW_PXP_DITHER_FETCH_STATUS_CH0 Bit Fields */
35759 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK 0xFFFFu
35760 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT 0
35761 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK)
35762 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u
35763 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT 16
35764 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK)
35765 /* HW_PXP_DITHER_FETCH_STATUS_CH1 Bit Fields */
35766 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK 0xFFFFu
35767 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT 0
35768 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK)
35769 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u
35770 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT 16
35771 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK)
35772 /* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 Bit Fields */
35773 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu
35774 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT 0
35775 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK)
35776 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u
35777 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT 16
35778 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK)
35779 /* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 Bit Fields */
35780 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu
35781 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT 0
35782 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK)
35783 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u
35784 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT 16
35785 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK)
35786 /* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 Bit Fields */
35787 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu
35788 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT 0
35789 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK)
35790 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u
35791 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT 16
35792 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK)
35793 /* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 Bit Fields */
35794 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu
35795 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT 0
35796 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK)
35797 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u
35798 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT 16
35799 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK)
35800 /* HW_PXP_DITHER_FETCH_SIZE_CH0 Bit Fields */
35801 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK 0xFFFFu
35802 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT 0
35803 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK)
35804 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u
35805 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT 16
35806 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK)
35807 /* HW_PXP_DITHER_FETCH_SIZE_CH1 Bit Fields */
35808 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK 0xFFFFu
35809 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT 0
35810 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK)
35811 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u
35812 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT 16
35813 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK)
35814 /* HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 Bit Fields */
35815 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK 0xFFFFFFFFu
35816 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT 0
35817 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK)
35818 /* HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 Bit Fields */
35819 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK 0xFFFFFFFFu
35820 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT 0
35821 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK)
35822 /* HW_PXP_DITHER_FETCH_PITCH Bit Fields */
35823 #define PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_MASK 0xFFFFu
35824 #define PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT 0
35825 #define PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_MASK)
35826 #define PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_MASK 0xFFFF0000u
35827 #define PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT 16
35828 #define PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_MASK)
35829 /* HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 Bit Fields */
35830 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK 0x3u
35831 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT 0
35832 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK)
35833 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK 0xFCu
35834 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT 2
35835 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK)
35836 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK 0x700u
35837 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT 8
35838 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK)
35839 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK 0x800u
35840 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT 11
35841 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x1000u
35842 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 12
35843 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFE000u
35844 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT 13
35845 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK)
35846 /* HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 Bit Fields */
35847 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK 0x3u
35848 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT 0
35849 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK)
35850 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK 0xFCu
35851 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT 2
35852 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK)
35853 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK 0x700u
35854 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT 8
35855 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK)
35856 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK 0x800u
35857 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT 11
35858 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK 0x1000u
35859 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT 12
35860 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFE000u
35861 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT 13
35862 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK)
35863 /* HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 Bit Fields */
35864 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK 0x1Fu
35865 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT 0
35866 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK)
35867 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK 0xE0u
35868 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT 5
35869 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK)
35870 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK 0x1F00u
35871 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT 8
35872 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK)
35873 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK 0xE000u
35874 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT 13
35875 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK)
35876 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK 0x1F0000u
35877 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT 16
35878 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK)
35879 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK 0xE00000u
35880 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT 21
35881 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK)
35882 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK 0x1F000000u
35883 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT 24
35884 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK)
35885 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK 0xE0000000u
35886 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT 29
35887 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK)
35888 /* HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 Bit Fields */
35889 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK 0x1Fu
35890 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT 0
35891 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK)
35892 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK 0xE0u
35893 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT 5
35894 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK)
35895 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK 0x1F00u
35896 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT 8
35897 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK)
35898 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK 0xE000u
35899 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT 13
35900 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK)
35901 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK 0x1F0000u
35902 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT 16
35903 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK)
35904 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK 0xE00000u
35905 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT 21
35906 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK)
35907 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK 0x1F000000u
35908 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT 24
35909 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK)
35910 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK 0xE0000000u
35911 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT 29
35912 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK)
35913 /* HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 Bit Fields */
35914 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK 0xFu
35915 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT 0
35916 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK)
35917 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK 0xF0u
35918 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT 4
35919 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK)
35920 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK 0xF00u
35921 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT 8
35922 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK)
35923 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK 0xF000u
35924 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT 12
35925 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK)
35926 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK 0xFFFF0000u
35927 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT 16
35928 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK)
35929 /* HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 Bit Fields */
35930 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK 0xFu
35931 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT 0
35932 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK)
35933 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK 0xF0u
35934 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT 4
35935 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK)
35936 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK 0xF00u
35937 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT 8
35938 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK)
35939 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK 0xF000u
35940 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT 12
35941 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK)
35942 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK 0xFFFF0000u
35943 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT 16
35944 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK)
35945 /* HW_PXP_DITHER_FETCH_ADDR_0_CH0 Bit Fields */
35946 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu
35947 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT 0
35948 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK)
35949 /* HW_PXP_DITHER_FETCH_ADDR_1_CH0 Bit Fields */
35950 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu
35951 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT 0
35952 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK)
35953 /* HW_PXP_DITHER_FETCH_ADDR_0_CH1 Bit Fields */
35954 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu
35955 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT 0
35956 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK)
35957 /* HW_PXP_DITHER_FETCH_ADDR_1_CH1 Bit Fields */
35958 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu
35959 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT 0
35960 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK)
35961 /* HW_PXP_DITHER_STORE_CTRL_CH0 Bit Fields */
35962 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK 0x1u
35963 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_CH_EN_SHIFT 0
35964 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_MASK 0x2u
35965 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_SHIFT 1
35966 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_MASK 0x4u
35967 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_SHIFT 2
35968 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u
35969 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT 3
35970 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_MASK 0x10u
35971 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_SHIFT 4
35972 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK 0x60u
35973 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT 5
35974 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK)
35975 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD3_MASK 0x80u
35976 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD3_SHIFT 7
35977 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK 0x100u
35978 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT 8
35979 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK 0x200u
35980 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT 9
35981 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_MASK 0x400u
35982 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT 10
35983 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_MASK 0x800u
35984 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT 11
35985 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_MASK 0xF000u
35986 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_SHIFT 12
35987 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_MASK)
35988 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_MASK 0x30000u
35989 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT 16
35990 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_MASK)
35991 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_MASK 0xFC0000u
35992 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_SHIFT 18
35993 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_MASK)
35994 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK 0x1000000u
35995 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT 24
35996 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_MASK 0x7E000000u
35997 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_SHIFT 25
35998 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_MASK)
35999 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_MASK 0x80000000u
36000 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_SHIFT 31
36001 /* HW_PXP_DITHER_STORE_CTRL_CH1 Bit Fields */
36002 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK 0x1u
36003 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_CH_EN_SHIFT 0
36004 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_MASK 0x2u
36005 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_SHIFT 1
36006 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_MASK 0x4u
36007 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_SHIFT 2
36008 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u
36009 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT 3
36010 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_MASK 0x10u
36011 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_SHIFT 4
36012 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK 0x60u
36013 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT 5
36014 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK)
36015 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD3_MASK 0x80u
36016 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD3_SHIFT 7
36017 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK 0x100u
36018 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT 8
36019 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK 0x200u
36020 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT 9
36021 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_MASK 0x400u
36022 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT 10
36023 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_MASK 0xF800u
36024 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_SHIFT 11
36025 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_MASK)
36026 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_MASK 0x30000u
36027 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT 16
36028 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_MASK)
36029 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_MASK 0xFFFC0000u
36030 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_SHIFT 18
36031 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_MASK)
36032 /* HW_PXP_DITHER_STORE_STATUS_CH0 Bit Fields */
36033 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_MASK 0xFFFFu
36034 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT 0
36035 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_MASK)
36036 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK 0xFFFF0000u
36037 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT 16
36038 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK)
36039 /* HW_PXP_DITHER_STORE_STATUS_CH1 Bit Fields */
36040 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_MASK 0xFFFFu
36041 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT 0
36042 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_MASK)
36043 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK 0xFFFF0000u
36044 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT 16
36045 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK)
36046 /* HW_PXP_DITHER_STORE_SIZE_CH0 Bit Fields */
36047 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK 0xFFFFu
36048 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT 0
36049 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK)
36050 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK 0xFFFF0000u
36051 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT 16
36052 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK)
36053 /* HW_PXP_DITHER_STORE_SIZE_CH1 Bit Fields */
36054 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_MASK 0xFFFFu
36055 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_SHIFT 0
36056 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_MASK)
36057 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_MASK 0xFFFF0000u
36058 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT 16
36059 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_MASK)
36060 /* HW_PXP_DITHER_STORE_PITCH Bit Fields */
36061 #define PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK 0xFFFFu
36062 #define PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_SHIFT 0
36063 #define PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK)
36064 #define PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_MASK 0xFFFF0000u
36065 #define PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_SHIFT 16
36066 #define PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_MASK)
36067 /* HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 Bit Fields */
36068 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_MASK 0x3u
36069 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT 0
36070 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_MASK)
36071 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK 0xCu
36072 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT 2
36073 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK)
36074 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK 0x10u
36075 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT 4
36076 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK 0x20u
36077 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT 5
36078 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_MASK 0x40u
36079 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT 6
36080 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x80u
36081 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 7
36082 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFFF00u
36083 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT 8
36084 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_MASK)
36085 /* HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 Bit Fields */
36086 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_MASK 0x3u
36087 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT 0
36088 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_MASK)
36089 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK 0xCu
36090 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT 2
36091 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK)
36092 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK 0x10u
36093 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT 4
36094 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK 0x20u
36095 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT 5
36096 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFFFC0u
36097 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT 6
36098 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_MASK)
36099 /* HW_PXP_DITHER_STORE_ADDR_0_CH0 Bit Fields */
36100 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu
36101 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT 0
36102 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK)
36103 /* HW_PXP_DITHER_STORE_ADDR_1_CH0 Bit Fields */
36104 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu
36105 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT 0
36106 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK)
36107 /* HW_PXP_DITHER_STORE_FILL_DATA_CH0 Bit Fields */
36108 #define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK 0xFFFFFFFFu
36109 #define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT 0
36110 #define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK)
36111 /* HW_PXP_DITHER_STORE_ADDR_0_CH1 Bit Fields */
36112 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu
36113 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT 0
36114 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK)
36115 /* HW_PXP_DITHER_STORE_ADDR_1_CH1 Bit Fields */
36116 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu
36117 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT 0
36118 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK)
36119 /* HW_PXP_DITHER_STORE_D_MASK0_H_CH0 Bit Fields */
36120 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK 0xFFFFFFFFu
36121 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT 0
36122 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK)
36123 /* HW_PXP_DITHER_STORE_D_MASK0_L_CH0 Bit Fields */
36124 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK 0xFFFFFFFFu
36125 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT 0
36126 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK)
36127 /* HW_PXP_DITHER_STORE_D_MASK1_H_CH0 Bit Fields */
36128 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK 0xFFFFFFFFu
36129 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT 0
36130 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK)
36131 /* HW_PXP_DITHER_STORE_D_MASK1_L_CH0 Bit Fields */
36132 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK 0xFFFFFFFFu
36133 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT 0
36134 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK)
36135 /* HW_PXP_DITHER_STORE_D_MASK2_H_CH0 Bit Fields */
36136 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK 0xFFFFFFFFu
36137 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT 0
36138 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK)
36139 /* HW_PXP_DITHER_STORE_D_MASK2_L_CH0 Bit Fields */
36140 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK 0xFFFFFFFFu
36141 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT 0
36142 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK)
36143 /* HW_PXP_DITHER_STORE_D_MASK3_H_CH0 Bit Fields */
36144 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK 0xFFFFFFFFu
36145 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT 0
36146 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK)
36147 /* HW_PXP_DITHER_STORE_D_MASK3_L_CH0 Bit Fields */
36148 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK 0xFFFFFFFFu
36149 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT 0
36150 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK)
36151 /* HW_PXP_DITHER_STORE_D_MASK4_H_CH0 Bit Fields */
36152 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK 0xFFFFFFFFu
36153 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT 0
36154 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK)
36155 /* HW_PXP_DITHER_STORE_D_MASK4_L_CH0 Bit Fields */
36156 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK 0xFFFFFFFFu
36157 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT 0
36158 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK)
36159 /* HW_PXP_DITHER_STORE_D_MASK5_H_CH0 Bit Fields */
36160 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK 0xFFFFFFFFu
36161 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT 0
36162 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK)
36163 /* HW_PXP_DITHER_STORE_D_MASK5_L_CH0 Bit Fields */
36164 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK 0xFFFFFFFFu
36165 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT 0
36166 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK)
36167 /* HW_PXP_DITHER_STORE_D_MASK6_H_CH0 Bit Fields */
36168 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK 0xFFFFFFFFu
36169 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT 0
36170 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK)
36171 /* HW_PXP_DITHER_STORE_D_MASK6_L_CH0 Bit Fields */
36172 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK 0xFFFFFFFFu
36173 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT 0
36174 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK)
36175 /* HW_PXP_DITHER_STORE_D_MASK7_H_CH0 Bit Fields */
36176 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK 0xFFFFFFFFu
36177 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT 0
36178 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK)
36179 /* HW_PXP_DITHER_STORE_D_MASK7_L_CH0 Bit Fields */
36180 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK 0xFFFFFFFFu
36181 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT 0
36182 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK)
36183 /* HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 Bit Fields */
36184 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK 0x3Fu
36185 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT 0
36186 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK)
36187 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_MASK 0x40u
36188 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT 6
36189 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK 0x80u
36190 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT 7
36191 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK 0x3F00u
36192 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT 8
36193 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK)
36194 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_MASK 0x4000u
36195 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT 14
36196 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK 0x8000u
36197 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT 15
36198 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK 0x3F0000u
36199 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT 16
36200 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK)
36201 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_MASK 0x400000u
36202 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT 22
36203 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK 0x800000u
36204 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT 23
36205 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK 0x3F000000u
36206 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT 24
36207 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK)
36208 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_MASK 0x40000000u
36209 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT 30
36210 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK 0x80000000u
36211 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT 31
36212 /* HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 Bit Fields */
36213 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK 0x3Fu
36214 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT 0
36215 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK)
36216 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_MASK 0x40u
36217 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT 6
36218 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK 0x80u
36219 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT 7
36220 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK 0x3F00u
36221 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT 8
36222 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK)
36223 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_MASK 0x4000u
36224 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT 14
36225 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK 0x8000u
36226 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT 15
36227 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK 0x3F0000u
36228 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT 16
36229 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK)
36230 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_MASK 0x400000u
36231 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT 22
36232 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK 0x800000u
36233 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT 23
36234 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK 0x3F000000u
36235 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT 24
36236 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK)
36237 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_MASK 0x40000000u
36238 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT 30
36239 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK 0x80000000u
36240 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT 31
36241 /* HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 Bit Fields */
36242 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK 0x3Fu
36243 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT 0
36244 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK)
36245 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK 0x40u
36246 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT 6
36247 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_MASK 0x80u
36248 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT 7
36249 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK 0x3F00u
36250 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT 8
36251 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK)
36252 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK 0x4000u
36253 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT 14
36254 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_MASK 0x8000u
36255 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT 15
36256 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK 0x3F0000u
36257 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT 16
36258 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK)
36259 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK 0x400000u
36260 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT 22
36261 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_MASK 0x800000u
36262 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT 23
36263 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK 0x3F000000u
36264 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT 24
36265 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK)
36266 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK 0x40000000u
36267 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT 30
36268 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_MASK 0x80000000u
36269 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT 31
36270 /* HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 Bit Fields */
36271 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK 0x3Fu
36272 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT 0
36273 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK)
36274 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK 0x40u
36275 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT 6
36276 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_MASK 0x80u
36277 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT 7
36278 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK 0x3F00u
36279 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT 8
36280 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK)
36281 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK 0x4000u
36282 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT 14
36283 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_MASK 0x8000u
36284 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT 15
36285 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK 0x3F0000u
36286 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT 16
36287 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK)
36288 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK 0x400000u
36289 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT 22
36290 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_MASK 0x800000u
36291 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT 23
36292 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK 0x3F000000u
36293 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT 24
36294 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK)
36295 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK 0x40000000u
36296 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT 30
36297 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_MASK 0x80000000u
36298 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT 31
36299 /* HW_PXP_DITHER_STORE_F_MASK_L_CH0 Bit Fields */
36300 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_MASK 0xFFu
36301 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_SHIFT 0
36302 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_MASK)
36303 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_MASK 0xFF00u
36304 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_SHIFT 8
36305 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_MASK)
36306 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_MASK 0xFF0000u
36307 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_SHIFT 16
36308 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_MASK)
36309 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_MASK 0xFF000000u
36310 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_SHIFT 24
36311 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_MASK)
36312 /* HW_PXP_DITHER_STORE_F_MASK_H_CH0 Bit Fields */
36313 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_MASK 0xFFu
36314 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_SHIFT 0
36315 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_MASK)
36316 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_MASK 0xFF00u
36317 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_SHIFT 8
36318 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_MASK)
36319 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_MASK 0xFF0000u
36320 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_SHIFT 16
36321 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_MASK)
36322 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_MASK 0xFF000000u
36323 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_SHIFT 24
36324 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_MASK)
36325 /* HW_PXP_DITHER_CTRL Bit Fields */
36326 #define PXP_HW_PXP_DITHER_CTRL_ENABLE0_MASK      0x1u
36327 #define PXP_HW_PXP_DITHER_CTRL_ENABLE0_SHIFT     0
36328 #define PXP_HW_PXP_DITHER_CTRL_ENABLE1_MASK      0x2u
36329 #define PXP_HW_PXP_DITHER_CTRL_ENABLE1_SHIFT     1
36330 #define PXP_HW_PXP_DITHER_CTRL_ENABLE2_MASK      0x4u
36331 #define PXP_HW_PXP_DITHER_CTRL_ENABLE2_SHIFT     2
36332 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_MASK 0x38u
36333 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_SHIFT 3
36334 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_SHIFT))&PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_MASK)
36335 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_MASK 0x1C0u
36336 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_SHIFT 6
36337 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_SHIFT))&PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_MASK)
36338 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_MASK 0xE00u
36339 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_SHIFT 9
36340 #define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_SHIFT))&PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_MASK)
36341 #define PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK 0x7000u
36342 #define PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT 12
36343 #define PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT))&PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK)
36344 #define PXP_HW_PXP_DITHER_CTRL_LUT_MODE_MASK     0x18000u
36345 #define PXP_HW_PXP_DITHER_CTRL_LUT_MODE_SHIFT    15
36346 #define PXP_HW_PXP_DITHER_CTRL_LUT_MODE(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_LUT_MODE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_LUT_MODE_MASK)
36347 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK 0x60000u
36348 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT 17
36349 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK)
36350 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK 0x180000u
36351 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT 19
36352 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK)
36353 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK 0x600000u
36354 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT 21
36355 #define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK)
36356 #define PXP_HW_PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK 0x800000u
36357 #define PXP_HW_PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT 23
36358 #define PXP_HW_PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK 0x1000000u
36359 #define PXP_HW_PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT 24
36360 #define PXP_HW_PXP_DITHER_CTRL_RSVD0_MASK        0x1E000000u
36361 #define PXP_HW_PXP_DITHER_CTRL_RSVD0_SHIFT       25
36362 #define PXP_HW_PXP_DITHER_CTRL_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_CTRL_RSVD0_MASK)
36363 #define PXP_HW_PXP_DITHER_CTRL_BUSY2_MASK        0x20000000u
36364 #define PXP_HW_PXP_DITHER_CTRL_BUSY2_SHIFT       29
36365 #define PXP_HW_PXP_DITHER_CTRL_BUSY1_MASK        0x40000000u
36366 #define PXP_HW_PXP_DITHER_CTRL_BUSY1_SHIFT       30
36367 #define PXP_HW_PXP_DITHER_CTRL_BUSY0_MASK        0x80000000u
36368 #define PXP_HW_PXP_DITHER_CTRL_BUSY0_SHIFT       31
36369 /* HW_PXP_DITHER_FINAL_LUT_DATA0 Bit Fields */
36370 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK 0xFFu
36371 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT 0
36372 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK)
36373 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK 0xFF00u
36374 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT 8
36375 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK)
36376 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK 0xFF0000u
36377 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT 16
36378 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK)
36379 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK 0xFF000000u
36380 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT 24
36381 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK)
36382 /* HW_PXP_DITHER_FINAL_LUT_DATA1 Bit Fields */
36383 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK 0xFFu
36384 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT 0
36385 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK)
36386 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK 0xFF00u
36387 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT 8
36388 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK)
36389 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK 0xFF0000u
36390 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT 16
36391 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK)
36392 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK 0xFF000000u
36393 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT 24
36394 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK)
36395 /* HW_PXP_DITHER_FINAL_LUT_DATA2 Bit Fields */
36396 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK 0xFFu
36397 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT 0
36398 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK)
36399 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK 0xFF00u
36400 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT 8
36401 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK)
36402 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK 0xFF0000u
36403 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT 16
36404 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK)
36405 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK 0xFF000000u
36406 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT 24
36407 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK)
36408 /* HW_PXP_DITHER_FINAL_LUT_DATA3 Bit Fields */
36409 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK 0xFFu
36410 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT 0
36411 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK)
36412 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK 0xFF00u
36413 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT 8
36414 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK)
36415 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK 0xFF0000u
36416 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT 16
36417 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK)
36418 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK 0xFF000000u
36419 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT 24
36420 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK)
36421 /* HW_PXP_HIST_A_CTRL Bit Fields */
36422 #define PXP_HW_PXP_HIST_A_CTRL_ENABLE_MASK       0x1u
36423 #define PXP_HW_PXP_HIST_A_CTRL_ENABLE_SHIFT      0
36424 #define PXP_HW_PXP_HIST_A_CTRL_RSVD0_MASK        0xEu
36425 #define PXP_HW_PXP_HIST_A_CTRL_RSVD0_SHIFT       1
36426 #define PXP_HW_PXP_HIST_A_CTRL_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD0_MASK)
36427 #define PXP_HW_PXP_HIST_A_CTRL_CLEAR_MASK        0x10u
36428 #define PXP_HW_PXP_HIST_A_CTRL_CLEAR_SHIFT       4
36429 #define PXP_HW_PXP_HIST_A_CTRL_RSVD1_MASK        0xE0u
36430 #define PXP_HW_PXP_HIST_A_CTRL_RSVD1_SHIFT       5
36431 #define PXP_HW_PXP_HIST_A_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD1_MASK)
36432 #define PXP_HW_PXP_HIST_A_CTRL_STATUS_MASK       0x1F00u
36433 #define PXP_HW_PXP_HIST_A_CTRL_STATUS_SHIFT      8
36434 #define PXP_HW_PXP_HIST_A_CTRL_STATUS(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_STATUS_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_STATUS_MASK)
36435 #define PXP_HW_PXP_HIST_A_CTRL_RSVD2_MASK        0xE000u
36436 #define PXP_HW_PXP_HIST_A_CTRL_RSVD2_SHIFT       13
36437 #define PXP_HW_PXP_HIST_A_CTRL_RSVD2(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD2_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD2_MASK)
36438 #define PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK 0x7F0000u
36439 #define PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT 16
36440 #define PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK)
36441 #define PXP_HW_PXP_HIST_A_CTRL_RSVD3_MASK        0x800000u
36442 #define PXP_HW_PXP_HIST_A_CTRL_RSVD3_SHIFT       23
36443 #define PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK  0x7000000u
36444 #define PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT 24
36445 #define PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK)
36446 #define PXP_HW_PXP_HIST_A_CTRL_RSVD4_MASK        0xF8000000u
36447 #define PXP_HW_PXP_HIST_A_CTRL_RSVD4_SHIFT       27
36448 #define PXP_HW_PXP_HIST_A_CTRL_RSVD4(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD4_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD4_MASK)
36449 /* HW_PXP_HIST_A_MASK Bit Fields */
36450 #define PXP_HW_PXP_HIST_A_MASK_MASK_EN_MASK      0x1u
36451 #define PXP_HW_PXP_HIST_A_MASK_MASK_EN_SHIFT     0
36452 #define PXP_HW_PXP_HIST_A_MASK_RSVD0_MASK        0xEu
36453 #define PXP_HW_PXP_HIST_A_MASK_RSVD0_SHIFT       1
36454 #define PXP_HW_PXP_HIST_A_MASK_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_MASK_RSVD0_MASK)
36455 #define PXP_HW_PXP_HIST_A_MASK_MASK_MODE_MASK    0x30u
36456 #define PXP_HW_PXP_HIST_A_MASK_MASK_MODE_SHIFT   4
36457 #define PXP_HW_PXP_HIST_A_MASK_MASK_MODE(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_MODE_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_MODE_MASK)
36458 #define PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_MASK  0x1FC0u
36459 #define PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_SHIFT 6
36460 #define PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_MASK)
36461 #define PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_MASK   0xE000u
36462 #define PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_SHIFT  13
36463 #define PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_MASK)
36464 #define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_MASK  0xFF0000u
36465 #define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_SHIFT 16
36466 #define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_MASK)
36467 #define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_MASK  0xFF000000u
36468 #define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_SHIFT 24
36469 #define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_MASK)
36470 /* HW_PXP_HIST_A_BUF_SIZE Bit Fields */
36471 #define PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_MASK    0xFFFu
36472 #define PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT   0
36473 #define PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_MASK)
36474 #define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_MASK    0xF000u
36475 #define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_SHIFT   12
36476 #define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_MASK)
36477 #define PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_MASK   0xFFF0000u
36478 #define PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT  16
36479 #define PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_MASK)
36480 #define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_MASK    0xF0000000u
36481 #define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_SHIFT   28
36482 #define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_MASK)
36483 /* HW_PXP_HIST_A_TOTAL_PIXEL Bit Fields */
36484 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK 0xFFFFFFu
36485 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT 0
36486 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT))&PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK)
36487 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_MASK 0xFF000000u
36488 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_SHIFT 24
36489 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_MASK)
36490 /* HW_PXP_HIST_A_ACTIVE_AREA_X Bit Fields */
36491 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK 0xFFFu
36492 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT 0
36493 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK)
36494 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_MASK 0xF000u
36495 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_SHIFT 12
36496 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_MASK)
36497 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK 0xFFF0000u
36498 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT 16
36499 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK)
36500 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_MASK 0xF0000000u
36501 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_SHIFT 28
36502 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_MASK)
36503 /* HW_PXP_HIST_A_ACTIVE_AREA_Y Bit Fields */
36504 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK 0xFFFu
36505 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT 0
36506 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK)
36507 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_MASK 0xF000u
36508 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_SHIFT 12
36509 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_MASK)
36510 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK 0xFFF0000u
36511 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT 16
36512 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK)
36513 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_MASK 0xF0000000u
36514 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_SHIFT 28
36515 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_MASK)
36516 /* HW_PXP_HIST_A_RAW_STAT0 Bit Fields */
36517 #define PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_MASK   0xFFFFFFFFu
36518 #define PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_SHIFT  0
36519 #define PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_SHIFT))&PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_MASK)
36520 /* HW_PXP_HIST_A_RAW_STAT1 Bit Fields */
36521 #define PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_MASK   0xFFFFFFFFu
36522 #define PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_SHIFT  0
36523 #define PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_SHIFT))&PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_MASK)
36524 /* HW_PXP_HIST_B_CTRL Bit Fields */
36525 #define PXP_HW_PXP_HIST_B_CTRL_ENABLE_MASK       0x1u
36526 #define PXP_HW_PXP_HIST_B_CTRL_ENABLE_SHIFT      0
36527 #define PXP_HW_PXP_HIST_B_CTRL_RSVD0_MASK        0xEu
36528 #define PXP_HW_PXP_HIST_B_CTRL_RSVD0_SHIFT       1
36529 #define PXP_HW_PXP_HIST_B_CTRL_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD0_MASK)
36530 #define PXP_HW_PXP_HIST_B_CTRL_CLEAR_MASK        0x10u
36531 #define PXP_HW_PXP_HIST_B_CTRL_CLEAR_SHIFT       4
36532 #define PXP_HW_PXP_HIST_B_CTRL_RSVD1_MASK        0xE0u
36533 #define PXP_HW_PXP_HIST_B_CTRL_RSVD1_SHIFT       5
36534 #define PXP_HW_PXP_HIST_B_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD1_MASK)
36535 #define PXP_HW_PXP_HIST_B_CTRL_STATUS_MASK       0x1F00u
36536 #define PXP_HW_PXP_HIST_B_CTRL_STATUS_SHIFT      8
36537 #define PXP_HW_PXP_HIST_B_CTRL_STATUS(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_STATUS_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_STATUS_MASK)
36538 #define PXP_HW_PXP_HIST_B_CTRL_RSVD2_MASK        0xE000u
36539 #define PXP_HW_PXP_HIST_B_CTRL_RSVD2_SHIFT       13
36540 #define PXP_HW_PXP_HIST_B_CTRL_RSVD2(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD2_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD2_MASK)
36541 #define PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK 0x7F0000u
36542 #define PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT 16
36543 #define PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK)
36544 #define PXP_HW_PXP_HIST_B_CTRL_RSVD3_MASK        0x800000u
36545 #define PXP_HW_PXP_HIST_B_CTRL_RSVD3_SHIFT       23
36546 #define PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK  0x7000000u
36547 #define PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT 24
36548 #define PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK)
36549 #define PXP_HW_PXP_HIST_B_CTRL_RSVD4_MASK        0xF8000000u
36550 #define PXP_HW_PXP_HIST_B_CTRL_RSVD4_SHIFT       27
36551 #define PXP_HW_PXP_HIST_B_CTRL_RSVD4(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD4_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD4_MASK)
36552 /* HW_PXP_HIST_B_MASK Bit Fields */
36553 #define PXP_HW_PXP_HIST_B_MASK_MASK_EN_MASK      0x1u
36554 #define PXP_HW_PXP_HIST_B_MASK_MASK_EN_SHIFT     0
36555 #define PXP_HW_PXP_HIST_B_MASK_RSVD0_MASK        0xEu
36556 #define PXP_HW_PXP_HIST_B_MASK_RSVD0_SHIFT       1
36557 #define PXP_HW_PXP_HIST_B_MASK_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_MASK_RSVD0_MASK)
36558 #define PXP_HW_PXP_HIST_B_MASK_MASK_MODE_MASK    0x30u
36559 #define PXP_HW_PXP_HIST_B_MASK_MASK_MODE_SHIFT   4
36560 #define PXP_HW_PXP_HIST_B_MASK_MASK_MODE(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_MODE_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_MODE_MASK)
36561 #define PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_MASK  0x1FC0u
36562 #define PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_SHIFT 6
36563 #define PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_MASK)
36564 #define PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_MASK   0xE000u
36565 #define PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_SHIFT  13
36566 #define PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_MASK)
36567 #define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_MASK  0xFF0000u
36568 #define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_SHIFT 16
36569 #define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_MASK)
36570 #define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_MASK  0xFF000000u
36571 #define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_SHIFT 24
36572 #define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_MASK)
36573 /* HW_PXP_HIST_B_BUF_SIZE Bit Fields */
36574 #define PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_MASK    0xFFFu
36575 #define PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT   0
36576 #define PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_MASK)
36577 #define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_MASK    0xF000u
36578 #define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_SHIFT   12
36579 #define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_MASK)
36580 #define PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_MASK   0xFFF0000u
36581 #define PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT  16
36582 #define PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_MASK)
36583 #define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_MASK    0xF0000000u
36584 #define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_SHIFT   28
36585 #define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_MASK)
36586 /* HW_PXP_HIST_B_TOTAL_PIXEL Bit Fields */
36587 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK 0xFFFFFFu
36588 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT 0
36589 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT))&PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK)
36590 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_MASK 0xFF000000u
36591 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_SHIFT 24
36592 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_MASK)
36593 /* HW_PXP_HIST_B_ACTIVE_AREA_X Bit Fields */
36594 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK 0xFFFu
36595 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT 0
36596 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK)
36597 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_MASK 0xF000u
36598 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_SHIFT 12
36599 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_MASK)
36600 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK 0xFFF0000u
36601 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT 16
36602 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK)
36603 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_MASK 0xF0000000u
36604 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_SHIFT 28
36605 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_MASK)
36606 /* HW_PXP_HIST_B_ACTIVE_AREA_Y Bit Fields */
36607 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK 0xFFFu
36608 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT 0
36609 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK)
36610 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_MASK 0xF000u
36611 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_SHIFT 12
36612 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_MASK)
36613 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK 0xFFF0000u
36614 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT 16
36615 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK)
36616 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_MASK 0xF0000000u
36617 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_SHIFT 28
36618 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_MASK)
36619 /* HW_PXP_HIST_B_RAW_STAT0 Bit Fields */
36620 #define PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_MASK   0xFFFFFFFFu
36621 #define PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_SHIFT  0
36622 #define PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_SHIFT))&PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_MASK)
36623 /* HW_PXP_HIST_B_RAW_STAT1 Bit Fields */
36624 #define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_MASK   0xFFFFFFFFu
36625 #define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_SHIFT  0
36626 #define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_SHIFT))&PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_MASK)
36627 /* HW_PXP_HIST2_PARAM Bit Fields */
36628 #define PXP_HW_PXP_HIST2_PARAM_VALUE0_MASK       0x3Fu
36629 #define PXP_HW_PXP_HIST2_PARAM_VALUE0_SHIFT      0
36630 #define PXP_HW_PXP_HIST2_PARAM_VALUE0(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_VALUE0_SHIFT))&PXP_HW_PXP_HIST2_PARAM_VALUE0_MASK)
36631 #define PXP_HW_PXP_HIST2_PARAM_RSVD0_MASK        0xC0u
36632 #define PXP_HW_PXP_HIST2_PARAM_RSVD0_SHIFT       6
36633 #define PXP_HW_PXP_HIST2_PARAM_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_RSVD0_SHIFT))&PXP_HW_PXP_HIST2_PARAM_RSVD0_MASK)
36634 #define PXP_HW_PXP_HIST2_PARAM_VALUE1_MASK       0x3F00u
36635 #define PXP_HW_PXP_HIST2_PARAM_VALUE1_SHIFT      8
36636 #define PXP_HW_PXP_HIST2_PARAM_VALUE1(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_VALUE1_SHIFT))&PXP_HW_PXP_HIST2_PARAM_VALUE1_MASK)
36637 #define PXP_HW_PXP_HIST2_PARAM_RSVD1_MASK        0xC000u
36638 #define PXP_HW_PXP_HIST2_PARAM_RSVD1_SHIFT       14
36639 #define PXP_HW_PXP_HIST2_PARAM_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_RSVD1_SHIFT))&PXP_HW_PXP_HIST2_PARAM_RSVD1_MASK)
36640 #define PXP_HW_PXP_HIST2_PARAM_RSVD_MASK         0xFFFF0000u
36641 #define PXP_HW_PXP_HIST2_PARAM_RSVD_SHIFT        16
36642 #define PXP_HW_PXP_HIST2_PARAM_RSVD(x)           (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_RSVD_SHIFT))&PXP_HW_PXP_HIST2_PARAM_RSVD_MASK)
36643 /* HW_PXP_HIST4_PARAM Bit Fields */
36644 #define PXP_HW_PXP_HIST4_PARAM_VALUE0_MASK       0x3Fu
36645 #define PXP_HW_PXP_HIST4_PARAM_VALUE0_SHIFT      0
36646 #define PXP_HW_PXP_HIST4_PARAM_VALUE0(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE0_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE0_MASK)
36647 #define PXP_HW_PXP_HIST4_PARAM_RSVD0_MASK        0xC0u
36648 #define PXP_HW_PXP_HIST4_PARAM_RSVD0_SHIFT       6
36649 #define PXP_HW_PXP_HIST4_PARAM_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD0_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD0_MASK)
36650 #define PXP_HW_PXP_HIST4_PARAM_VALUE1_MASK       0x3F00u
36651 #define PXP_HW_PXP_HIST4_PARAM_VALUE1_SHIFT      8
36652 #define PXP_HW_PXP_HIST4_PARAM_VALUE1(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE1_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE1_MASK)
36653 #define PXP_HW_PXP_HIST4_PARAM_RSVD1_MASK        0xC000u
36654 #define PXP_HW_PXP_HIST4_PARAM_RSVD1_SHIFT       14
36655 #define PXP_HW_PXP_HIST4_PARAM_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD1_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD1_MASK)
36656 #define PXP_HW_PXP_HIST4_PARAM_VALUE2_MASK       0x3F0000u
36657 #define PXP_HW_PXP_HIST4_PARAM_VALUE2_SHIFT      16
36658 #define PXP_HW_PXP_HIST4_PARAM_VALUE2(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE2_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE2_MASK)
36659 #define PXP_HW_PXP_HIST4_PARAM_RSVD2_MASK        0xC00000u
36660 #define PXP_HW_PXP_HIST4_PARAM_RSVD2_SHIFT       22
36661 #define PXP_HW_PXP_HIST4_PARAM_RSVD2(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD2_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD2_MASK)
36662 #define PXP_HW_PXP_HIST4_PARAM_VALUE3_MASK       0x3F000000u
36663 #define PXP_HW_PXP_HIST4_PARAM_VALUE3_SHIFT      24
36664 #define PXP_HW_PXP_HIST4_PARAM_VALUE3(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE3_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE3_MASK)
36665 #define PXP_HW_PXP_HIST4_PARAM_RSVD3_MASK        0xC0000000u
36666 #define PXP_HW_PXP_HIST4_PARAM_RSVD3_SHIFT       30
36667 #define PXP_HW_PXP_HIST4_PARAM_RSVD3(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD3_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD3_MASK)
36668 /* HW_PXP_HIST8_PARAM0 Bit Fields */
36669 #define PXP_HW_PXP_HIST8_PARAM0_VALUE0_MASK      0x3Fu
36670 #define PXP_HW_PXP_HIST8_PARAM0_VALUE0_SHIFT     0
36671 #define PXP_HW_PXP_HIST8_PARAM0_VALUE0(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE0_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE0_MASK)
36672 #define PXP_HW_PXP_HIST8_PARAM0_RSVD0_MASK       0xC0u
36673 #define PXP_HW_PXP_HIST8_PARAM0_RSVD0_SHIFT      6
36674 #define PXP_HW_PXP_HIST8_PARAM0_RSVD0(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD0_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD0_MASK)
36675 #define PXP_HW_PXP_HIST8_PARAM0_VALUE1_MASK      0x3F00u
36676 #define PXP_HW_PXP_HIST8_PARAM0_VALUE1_SHIFT     8
36677 #define PXP_HW_PXP_HIST8_PARAM0_VALUE1(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE1_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE1_MASK)
36678 #define PXP_HW_PXP_HIST8_PARAM0_RSVD1_MASK       0xC000u
36679 #define PXP_HW_PXP_HIST8_PARAM0_RSVD1_SHIFT      14
36680 #define PXP_HW_PXP_HIST8_PARAM0_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD1_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD1_MASK)
36681 #define PXP_HW_PXP_HIST8_PARAM0_VALUE2_MASK      0x3F0000u
36682 #define PXP_HW_PXP_HIST8_PARAM0_VALUE2_SHIFT     16
36683 #define PXP_HW_PXP_HIST8_PARAM0_VALUE2(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE2_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE2_MASK)
36684 #define PXP_HW_PXP_HIST8_PARAM0_RSVD2_MASK       0xC00000u
36685 #define PXP_HW_PXP_HIST8_PARAM0_RSVD2_SHIFT      22
36686 #define PXP_HW_PXP_HIST8_PARAM0_RSVD2(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD2_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD2_MASK)
36687 #define PXP_HW_PXP_HIST8_PARAM0_VALUE3_MASK      0x3F000000u
36688 #define PXP_HW_PXP_HIST8_PARAM0_VALUE3_SHIFT     24
36689 #define PXP_HW_PXP_HIST8_PARAM0_VALUE3(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE3_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE3_MASK)
36690 #define PXP_HW_PXP_HIST8_PARAM0_RSVD3_MASK       0xC0000000u
36691 #define PXP_HW_PXP_HIST8_PARAM0_RSVD3_SHIFT      30
36692 #define PXP_HW_PXP_HIST8_PARAM0_RSVD3(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD3_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD3_MASK)
36693 /* HW_PXP_HIST8_PARAM1 Bit Fields */
36694 #define PXP_HW_PXP_HIST8_PARAM1_VALUE4_MASK      0x3Fu
36695 #define PXP_HW_PXP_HIST8_PARAM1_VALUE4_SHIFT     0
36696 #define PXP_HW_PXP_HIST8_PARAM1_VALUE4(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE4_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE4_MASK)
36697 #define PXP_HW_PXP_HIST8_PARAM1_RSVD4_MASK       0xC0u
36698 #define PXP_HW_PXP_HIST8_PARAM1_RSVD4_SHIFT      6
36699 #define PXP_HW_PXP_HIST8_PARAM1_RSVD4(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD4_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD4_MASK)
36700 #define PXP_HW_PXP_HIST8_PARAM1_VALUE5_MASK      0x3F00u
36701 #define PXP_HW_PXP_HIST8_PARAM1_VALUE5_SHIFT     8
36702 #define PXP_HW_PXP_HIST8_PARAM1_VALUE5(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE5_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE5_MASK)
36703 #define PXP_HW_PXP_HIST8_PARAM1_RSVD5_MASK       0xC000u
36704 #define PXP_HW_PXP_HIST8_PARAM1_RSVD5_SHIFT      14
36705 #define PXP_HW_PXP_HIST8_PARAM1_RSVD5(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD5_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD5_MASK)
36706 #define PXP_HW_PXP_HIST8_PARAM1_VALUE6_MASK      0x3F0000u
36707 #define PXP_HW_PXP_HIST8_PARAM1_VALUE6_SHIFT     16
36708 #define PXP_HW_PXP_HIST8_PARAM1_VALUE6(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE6_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE6_MASK)
36709 #define PXP_HW_PXP_HIST8_PARAM1_RSVD6_MASK       0xC00000u
36710 #define PXP_HW_PXP_HIST8_PARAM1_RSVD6_SHIFT      22
36711 #define PXP_HW_PXP_HIST8_PARAM1_RSVD6(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD6_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD6_MASK)
36712 #define PXP_HW_PXP_HIST8_PARAM1_VALUE7_MASK      0x3F000000u
36713 #define PXP_HW_PXP_HIST8_PARAM1_VALUE7_SHIFT     24
36714 #define PXP_HW_PXP_HIST8_PARAM1_VALUE7(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE7_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE7_MASK)
36715 #define PXP_HW_PXP_HIST8_PARAM1_RSVD7_MASK       0xC0000000u
36716 #define PXP_HW_PXP_HIST8_PARAM1_RSVD7_SHIFT      30
36717 #define PXP_HW_PXP_HIST8_PARAM1_RSVD7(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD7_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD7_MASK)
36718 /* HW_PXP_HIST16_PARAM0 Bit Fields */
36719 #define PXP_HW_PXP_HIST16_PARAM0_VALUE0_MASK     0x3Fu
36720 #define PXP_HW_PXP_HIST16_PARAM0_VALUE0_SHIFT    0
36721 #define PXP_HW_PXP_HIST16_PARAM0_VALUE0(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE0_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE0_MASK)
36722 #define PXP_HW_PXP_HIST16_PARAM0_RSVD0_MASK      0xC0u
36723 #define PXP_HW_PXP_HIST16_PARAM0_RSVD0_SHIFT     6
36724 #define PXP_HW_PXP_HIST16_PARAM0_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD0_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD0_MASK)
36725 #define PXP_HW_PXP_HIST16_PARAM0_VALUE1_MASK     0x3F00u
36726 #define PXP_HW_PXP_HIST16_PARAM0_VALUE1_SHIFT    8
36727 #define PXP_HW_PXP_HIST16_PARAM0_VALUE1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE1_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE1_MASK)
36728 #define PXP_HW_PXP_HIST16_PARAM0_RSVD1_MASK      0xC000u
36729 #define PXP_HW_PXP_HIST16_PARAM0_RSVD1_SHIFT     14
36730 #define PXP_HW_PXP_HIST16_PARAM0_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD1_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD1_MASK)
36731 #define PXP_HW_PXP_HIST16_PARAM0_VALUE2_MASK     0x3F0000u
36732 #define PXP_HW_PXP_HIST16_PARAM0_VALUE2_SHIFT    16
36733 #define PXP_HW_PXP_HIST16_PARAM0_VALUE2(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE2_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE2_MASK)
36734 #define PXP_HW_PXP_HIST16_PARAM0_RSVD2_MASK      0xC00000u
36735 #define PXP_HW_PXP_HIST16_PARAM0_RSVD2_SHIFT     22
36736 #define PXP_HW_PXP_HIST16_PARAM0_RSVD2(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD2_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD2_MASK)
36737 #define PXP_HW_PXP_HIST16_PARAM0_VALUE3_MASK     0x3F000000u
36738 #define PXP_HW_PXP_HIST16_PARAM0_VALUE3_SHIFT    24
36739 #define PXP_HW_PXP_HIST16_PARAM0_VALUE3(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE3_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE3_MASK)
36740 #define PXP_HW_PXP_HIST16_PARAM0_RSVD3_MASK      0xC0000000u
36741 #define PXP_HW_PXP_HIST16_PARAM0_RSVD3_SHIFT     30
36742 #define PXP_HW_PXP_HIST16_PARAM0_RSVD3(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD3_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD3_MASK)
36743 /* HW_PXP_HIST16_PARAM1 Bit Fields */
36744 #define PXP_HW_PXP_HIST16_PARAM1_VALUE4_MASK     0x3Fu
36745 #define PXP_HW_PXP_HIST16_PARAM1_VALUE4_SHIFT    0
36746 #define PXP_HW_PXP_HIST16_PARAM1_VALUE4(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE4_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE4_MASK)
36747 #define PXP_HW_PXP_HIST16_PARAM1_RSVD4_MASK      0xC0u
36748 #define PXP_HW_PXP_HIST16_PARAM1_RSVD4_SHIFT     6
36749 #define PXP_HW_PXP_HIST16_PARAM1_RSVD4(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD4_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD4_MASK)
36750 #define PXP_HW_PXP_HIST16_PARAM1_VALUE5_MASK     0x3F00u
36751 #define PXP_HW_PXP_HIST16_PARAM1_VALUE5_SHIFT    8
36752 #define PXP_HW_PXP_HIST16_PARAM1_VALUE5(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE5_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE5_MASK)
36753 #define PXP_HW_PXP_HIST16_PARAM1_RSVD5_MASK      0xC000u
36754 #define PXP_HW_PXP_HIST16_PARAM1_RSVD5_SHIFT     14
36755 #define PXP_HW_PXP_HIST16_PARAM1_RSVD5(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD5_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD5_MASK)
36756 #define PXP_HW_PXP_HIST16_PARAM1_VALUE6_MASK     0x3F0000u
36757 #define PXP_HW_PXP_HIST16_PARAM1_VALUE6_SHIFT    16
36758 #define PXP_HW_PXP_HIST16_PARAM1_VALUE6(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE6_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE6_MASK)
36759 #define PXP_HW_PXP_HIST16_PARAM1_RSVD6_MASK      0xC00000u
36760 #define PXP_HW_PXP_HIST16_PARAM1_RSVD6_SHIFT     22
36761 #define PXP_HW_PXP_HIST16_PARAM1_RSVD6(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD6_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD6_MASK)
36762 #define PXP_HW_PXP_HIST16_PARAM1_VALUE7_MASK     0x3F000000u
36763 #define PXP_HW_PXP_HIST16_PARAM1_VALUE7_SHIFT    24
36764 #define PXP_HW_PXP_HIST16_PARAM1_VALUE7(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE7_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE7_MASK)
36765 #define PXP_HW_PXP_HIST16_PARAM1_RSVD7_MASK      0xC0000000u
36766 #define PXP_HW_PXP_HIST16_PARAM1_RSVD7_SHIFT     30
36767 #define PXP_HW_PXP_HIST16_PARAM1_RSVD7(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD7_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD7_MASK)
36768 /* HW_PXP_HIST16_PARAM2 Bit Fields */
36769 #define PXP_HW_PXP_HIST16_PARAM2_VALUE8_MASK     0x3Fu
36770 #define PXP_HW_PXP_HIST16_PARAM2_VALUE8_SHIFT    0
36771 #define PXP_HW_PXP_HIST16_PARAM2_VALUE8(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE8_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE8_MASK)
36772 #define PXP_HW_PXP_HIST16_PARAM2_RSVD8_MASK      0xC0u
36773 #define PXP_HW_PXP_HIST16_PARAM2_RSVD8_SHIFT     6
36774 #define PXP_HW_PXP_HIST16_PARAM2_RSVD8(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD8_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD8_MASK)
36775 #define PXP_HW_PXP_HIST16_PARAM2_VALUE9_MASK     0x3F00u
36776 #define PXP_HW_PXP_HIST16_PARAM2_VALUE9_SHIFT    8
36777 #define PXP_HW_PXP_HIST16_PARAM2_VALUE9(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE9_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE9_MASK)
36778 #define PXP_HW_PXP_HIST16_PARAM2_RSVD9_MASK      0xC000u
36779 #define PXP_HW_PXP_HIST16_PARAM2_RSVD9_SHIFT     14
36780 #define PXP_HW_PXP_HIST16_PARAM2_RSVD9(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD9_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD9_MASK)
36781 #define PXP_HW_PXP_HIST16_PARAM2_VALUE10_MASK    0x3F0000u
36782 #define PXP_HW_PXP_HIST16_PARAM2_VALUE10_SHIFT   16
36783 #define PXP_HW_PXP_HIST16_PARAM2_VALUE10(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE10_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE10_MASK)
36784 #define PXP_HW_PXP_HIST16_PARAM2_RSVD10_MASK     0xC00000u
36785 #define PXP_HW_PXP_HIST16_PARAM2_RSVD10_SHIFT    22
36786 #define PXP_HW_PXP_HIST16_PARAM2_RSVD10(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD10_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD10_MASK)
36787 #define PXP_HW_PXP_HIST16_PARAM2_VALUE11_MASK    0x3F000000u
36788 #define PXP_HW_PXP_HIST16_PARAM2_VALUE11_SHIFT   24
36789 #define PXP_HW_PXP_HIST16_PARAM2_VALUE11(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE11_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE11_MASK)
36790 #define PXP_HW_PXP_HIST16_PARAM2_RSVD11_MASK     0xC0000000u
36791 #define PXP_HW_PXP_HIST16_PARAM2_RSVD11_SHIFT    30
36792 #define PXP_HW_PXP_HIST16_PARAM2_RSVD11(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD11_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD11_MASK)
36793 /* HW_PXP_HIST16_PARAM3 Bit Fields */
36794 #define PXP_HW_PXP_HIST16_PARAM3_VALUE12_MASK    0x3Fu
36795 #define PXP_HW_PXP_HIST16_PARAM3_VALUE12_SHIFT   0
36796 #define PXP_HW_PXP_HIST16_PARAM3_VALUE12(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE12_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE12_MASK)
36797 #define PXP_HW_PXP_HIST16_PARAM3_RSVD12_MASK     0xC0u
36798 #define PXP_HW_PXP_HIST16_PARAM3_RSVD12_SHIFT    6
36799 #define PXP_HW_PXP_HIST16_PARAM3_RSVD12(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD12_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD12_MASK)
36800 #define PXP_HW_PXP_HIST16_PARAM3_VALUE13_MASK    0x3F00u
36801 #define PXP_HW_PXP_HIST16_PARAM3_VALUE13_SHIFT   8
36802 #define PXP_HW_PXP_HIST16_PARAM3_VALUE13(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE13_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE13_MASK)
36803 #define PXP_HW_PXP_HIST16_PARAM3_RSVD13_MASK     0xC000u
36804 #define PXP_HW_PXP_HIST16_PARAM3_RSVD13_SHIFT    14
36805 #define PXP_HW_PXP_HIST16_PARAM3_RSVD13(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD13_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD13_MASK)
36806 #define PXP_HW_PXP_HIST16_PARAM3_VALUE14_MASK    0x3F0000u
36807 #define PXP_HW_PXP_HIST16_PARAM3_VALUE14_SHIFT   16
36808 #define PXP_HW_PXP_HIST16_PARAM3_VALUE14(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE14_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE14_MASK)
36809 #define PXP_HW_PXP_HIST16_PARAM3_RSVD14_MASK     0xC00000u
36810 #define PXP_HW_PXP_HIST16_PARAM3_RSVD14_SHIFT    22
36811 #define PXP_HW_PXP_HIST16_PARAM3_RSVD14(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD14_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD14_MASK)
36812 #define PXP_HW_PXP_HIST16_PARAM3_VALUE15_MASK    0x3F000000u
36813 #define PXP_HW_PXP_HIST16_PARAM3_VALUE15_SHIFT   24
36814 #define PXP_HW_PXP_HIST16_PARAM3_VALUE15(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE15_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE15_MASK)
36815 #define PXP_HW_PXP_HIST16_PARAM3_RSVD15_MASK     0xC0000000u
36816 #define PXP_HW_PXP_HIST16_PARAM3_RSVD15_SHIFT    30
36817 #define PXP_HW_PXP_HIST16_PARAM3_RSVD15(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD15_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD15_MASK)
36818 /* HW_PXP_HIST32_PARAM0 Bit Fields */
36819 #define PXP_HW_PXP_HIST32_PARAM0_VALUE0_MASK     0x3Fu
36820 #define PXP_HW_PXP_HIST32_PARAM0_VALUE0_SHIFT    0
36821 #define PXP_HW_PXP_HIST32_PARAM0_VALUE0(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE0_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE0_MASK)
36822 #define PXP_HW_PXP_HIST32_PARAM0_RSVD0_MASK      0xC0u
36823 #define PXP_HW_PXP_HIST32_PARAM0_RSVD0_SHIFT     6
36824 #define PXP_HW_PXP_HIST32_PARAM0_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD0_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD0_MASK)
36825 #define PXP_HW_PXP_HIST32_PARAM0_VALUE1_MASK     0x3F00u
36826 #define PXP_HW_PXP_HIST32_PARAM0_VALUE1_SHIFT    8
36827 #define PXP_HW_PXP_HIST32_PARAM0_VALUE1(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE1_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE1_MASK)
36828 #define PXP_HW_PXP_HIST32_PARAM0_RSVD1_MASK      0xC000u
36829 #define PXP_HW_PXP_HIST32_PARAM0_RSVD1_SHIFT     14
36830 #define PXP_HW_PXP_HIST32_PARAM0_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD1_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD1_MASK)
36831 #define PXP_HW_PXP_HIST32_PARAM0_VALUE2_MASK     0x3F0000u
36832 #define PXP_HW_PXP_HIST32_PARAM0_VALUE2_SHIFT    16
36833 #define PXP_HW_PXP_HIST32_PARAM0_VALUE2(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE2_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE2_MASK)
36834 #define PXP_HW_PXP_HIST32_PARAM0_RSVD2_MASK      0xC00000u
36835 #define PXP_HW_PXP_HIST32_PARAM0_RSVD2_SHIFT     22
36836 #define PXP_HW_PXP_HIST32_PARAM0_RSVD2(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD2_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD2_MASK)
36837 #define PXP_HW_PXP_HIST32_PARAM0_VALUE3_MASK     0x3F000000u
36838 #define PXP_HW_PXP_HIST32_PARAM0_VALUE3_SHIFT    24
36839 #define PXP_HW_PXP_HIST32_PARAM0_VALUE3(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE3_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE3_MASK)
36840 #define PXP_HW_PXP_HIST32_PARAM0_RSVD3_MASK      0xC0000000u
36841 #define PXP_HW_PXP_HIST32_PARAM0_RSVD3_SHIFT     30
36842 #define PXP_HW_PXP_HIST32_PARAM0_RSVD3(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD3_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD3_MASK)
36843 /* HW_PXP_HIST32_PARAM1 Bit Fields */
36844 #define PXP_HW_PXP_HIST32_PARAM1_VALUE4_MASK     0x3Fu
36845 #define PXP_HW_PXP_HIST32_PARAM1_VALUE4_SHIFT    0
36846 #define PXP_HW_PXP_HIST32_PARAM1_VALUE4(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE4_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE4_MASK)
36847 #define PXP_HW_PXP_HIST32_PARAM1_RSVD4_MASK      0xC0u
36848 #define PXP_HW_PXP_HIST32_PARAM1_RSVD4_SHIFT     6
36849 #define PXP_HW_PXP_HIST32_PARAM1_RSVD4(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD4_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD4_MASK)
36850 #define PXP_HW_PXP_HIST32_PARAM1_VALUE5_MASK     0x3F00u
36851 #define PXP_HW_PXP_HIST32_PARAM1_VALUE5_SHIFT    8
36852 #define PXP_HW_PXP_HIST32_PARAM1_VALUE5(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE5_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE5_MASK)
36853 #define PXP_HW_PXP_HIST32_PARAM1_RSVD5_MASK      0xC000u
36854 #define PXP_HW_PXP_HIST32_PARAM1_RSVD5_SHIFT     14
36855 #define PXP_HW_PXP_HIST32_PARAM1_RSVD5(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD5_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD5_MASK)
36856 #define PXP_HW_PXP_HIST32_PARAM1_VALUE6_MASK     0x3F0000u
36857 #define PXP_HW_PXP_HIST32_PARAM1_VALUE6_SHIFT    16
36858 #define PXP_HW_PXP_HIST32_PARAM1_VALUE6(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE6_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE6_MASK)
36859 #define PXP_HW_PXP_HIST32_PARAM1_RSVD6_MASK      0xC00000u
36860 #define PXP_HW_PXP_HIST32_PARAM1_RSVD6_SHIFT     22
36861 #define PXP_HW_PXP_HIST32_PARAM1_RSVD6(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD6_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD6_MASK)
36862 #define PXP_HW_PXP_HIST32_PARAM1_VALUE7_MASK     0x3F000000u
36863 #define PXP_HW_PXP_HIST32_PARAM1_VALUE7_SHIFT    24
36864 #define PXP_HW_PXP_HIST32_PARAM1_VALUE7(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE7_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE7_MASK)
36865 #define PXP_HW_PXP_HIST32_PARAM1_RSVD7_MASK      0xC0000000u
36866 #define PXP_HW_PXP_HIST32_PARAM1_RSVD7_SHIFT     30
36867 #define PXP_HW_PXP_HIST32_PARAM1_RSVD7(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD7_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD7_MASK)
36868 /* HW_PXP_HIST32_PARAM2 Bit Fields */
36869 #define PXP_HW_PXP_HIST32_PARAM2_VALUE8_MASK     0x3Fu
36870 #define PXP_HW_PXP_HIST32_PARAM2_VALUE8_SHIFT    0
36871 #define PXP_HW_PXP_HIST32_PARAM2_VALUE8(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE8_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE8_MASK)
36872 #define PXP_HW_PXP_HIST32_PARAM2_RSVD8_MASK      0xC0u
36873 #define PXP_HW_PXP_HIST32_PARAM2_RSVD8_SHIFT     6
36874 #define PXP_HW_PXP_HIST32_PARAM2_RSVD8(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD8_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD8_MASK)
36875 #define PXP_HW_PXP_HIST32_PARAM2_VALUE9_MASK     0x3F00u
36876 #define PXP_HW_PXP_HIST32_PARAM2_VALUE9_SHIFT    8
36877 #define PXP_HW_PXP_HIST32_PARAM2_VALUE9(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE9_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE9_MASK)
36878 #define PXP_HW_PXP_HIST32_PARAM2_RSVD9_MASK      0xC000u
36879 #define PXP_HW_PXP_HIST32_PARAM2_RSVD9_SHIFT     14
36880 #define PXP_HW_PXP_HIST32_PARAM2_RSVD9(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD9_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD9_MASK)
36881 #define PXP_HW_PXP_HIST32_PARAM2_VALUE10_MASK    0x3F0000u
36882 #define PXP_HW_PXP_HIST32_PARAM2_VALUE10_SHIFT   16
36883 #define PXP_HW_PXP_HIST32_PARAM2_VALUE10(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE10_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE10_MASK)
36884 #define PXP_HW_PXP_HIST32_PARAM2_RSVD10_MASK     0xC00000u
36885 #define PXP_HW_PXP_HIST32_PARAM2_RSVD10_SHIFT    22
36886 #define PXP_HW_PXP_HIST32_PARAM2_RSVD10(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD10_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD10_MASK)
36887 #define PXP_HW_PXP_HIST32_PARAM2_VALUE11_MASK    0x3F000000u
36888 #define PXP_HW_PXP_HIST32_PARAM2_VALUE11_SHIFT   24
36889 #define PXP_HW_PXP_HIST32_PARAM2_VALUE11(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE11_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE11_MASK)
36890 #define PXP_HW_PXP_HIST32_PARAM2_RSVD11_MASK     0xC0000000u
36891 #define PXP_HW_PXP_HIST32_PARAM2_RSVD11_SHIFT    30
36892 #define PXP_HW_PXP_HIST32_PARAM2_RSVD11(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD11_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD11_MASK)
36893 /* HW_PXP_HIST32_PARAM3 Bit Fields */
36894 #define PXP_HW_PXP_HIST32_PARAM3_VALUE12_MASK    0x3Fu
36895 #define PXP_HW_PXP_HIST32_PARAM3_VALUE12_SHIFT   0
36896 #define PXP_HW_PXP_HIST32_PARAM3_VALUE12(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE12_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE12_MASK)
36897 #define PXP_HW_PXP_HIST32_PARAM3_RSVD12_MASK     0xC0u
36898 #define PXP_HW_PXP_HIST32_PARAM3_RSVD12_SHIFT    6
36899 #define PXP_HW_PXP_HIST32_PARAM3_RSVD12(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD12_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD12_MASK)
36900 #define PXP_HW_PXP_HIST32_PARAM3_VALUE13_MASK    0x3F00u
36901 #define PXP_HW_PXP_HIST32_PARAM3_VALUE13_SHIFT   8
36902 #define PXP_HW_PXP_HIST32_PARAM3_VALUE13(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE13_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE13_MASK)
36903 #define PXP_HW_PXP_HIST32_PARAM3_RSVD13_MASK     0xC000u
36904 #define PXP_HW_PXP_HIST32_PARAM3_RSVD13_SHIFT    14
36905 #define PXP_HW_PXP_HIST32_PARAM3_RSVD13(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD13_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD13_MASK)
36906 #define PXP_HW_PXP_HIST32_PARAM3_VALUE14_MASK    0x3F0000u
36907 #define PXP_HW_PXP_HIST32_PARAM3_VALUE14_SHIFT   16
36908 #define PXP_HW_PXP_HIST32_PARAM3_VALUE14(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE14_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE14_MASK)
36909 #define PXP_HW_PXP_HIST32_PARAM3_RSVD14_MASK     0xC00000u
36910 #define PXP_HW_PXP_HIST32_PARAM3_RSVD14_SHIFT    22
36911 #define PXP_HW_PXP_HIST32_PARAM3_RSVD14(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD14_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD14_MASK)
36912 #define PXP_HW_PXP_HIST32_PARAM3_VALUE15_MASK    0x3F000000u
36913 #define PXP_HW_PXP_HIST32_PARAM3_VALUE15_SHIFT   24
36914 #define PXP_HW_PXP_HIST32_PARAM3_VALUE15(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE15_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE15_MASK)
36915 #define PXP_HW_PXP_HIST32_PARAM3_RSVD15_MASK     0xC0000000u
36916 #define PXP_HW_PXP_HIST32_PARAM3_RSVD15_SHIFT    30
36917 #define PXP_HW_PXP_HIST32_PARAM3_RSVD15(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD15_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD15_MASK)
36918 /* HW_PXP_HIST32_PARAM4 Bit Fields */
36919 #define PXP_HW_PXP_HIST32_PARAM4_VALUE16_MASK    0x3Fu
36920 #define PXP_HW_PXP_HIST32_PARAM4_VALUE16_SHIFT   0
36921 #define PXP_HW_PXP_HIST32_PARAM4_VALUE16(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE16_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE16_MASK)
36922 #define PXP_HW_PXP_HIST32_PARAM4_RSVD0_MASK      0xC0u
36923 #define PXP_HW_PXP_HIST32_PARAM4_RSVD0_SHIFT     6
36924 #define PXP_HW_PXP_HIST32_PARAM4_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD0_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD0_MASK)
36925 #define PXP_HW_PXP_HIST32_PARAM4_VALUE17_MASK    0x3F00u
36926 #define PXP_HW_PXP_HIST32_PARAM4_VALUE17_SHIFT   8
36927 #define PXP_HW_PXP_HIST32_PARAM4_VALUE17(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE17_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE17_MASK)
36928 #define PXP_HW_PXP_HIST32_PARAM4_RSVD1_MASK      0xC000u
36929 #define PXP_HW_PXP_HIST32_PARAM4_RSVD1_SHIFT     14
36930 #define PXP_HW_PXP_HIST32_PARAM4_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD1_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD1_MASK)
36931 #define PXP_HW_PXP_HIST32_PARAM4_VALUE18_MASK    0x3F0000u
36932 #define PXP_HW_PXP_HIST32_PARAM4_VALUE18_SHIFT   16
36933 #define PXP_HW_PXP_HIST32_PARAM4_VALUE18(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE18_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE18_MASK)
36934 #define PXP_HW_PXP_HIST32_PARAM4_RSVD2_MASK      0xC00000u
36935 #define PXP_HW_PXP_HIST32_PARAM4_RSVD2_SHIFT     22
36936 #define PXP_HW_PXP_HIST32_PARAM4_RSVD2(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD2_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD2_MASK)
36937 #define PXP_HW_PXP_HIST32_PARAM4_VALUE19_MASK    0x3F000000u
36938 #define PXP_HW_PXP_HIST32_PARAM4_VALUE19_SHIFT   24
36939 #define PXP_HW_PXP_HIST32_PARAM4_VALUE19(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE19_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE19_MASK)
36940 #define PXP_HW_PXP_HIST32_PARAM4_RSVD3_MASK      0xC0000000u
36941 #define PXP_HW_PXP_HIST32_PARAM4_RSVD3_SHIFT     30
36942 #define PXP_HW_PXP_HIST32_PARAM4_RSVD3(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD3_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD3_MASK)
36943 /* HW_PXP_HIST32_PARAM5 Bit Fields */
36944 #define PXP_HW_PXP_HIST32_PARAM5_VALUE20_MASK    0x3Fu
36945 #define PXP_HW_PXP_HIST32_PARAM5_VALUE20_SHIFT   0
36946 #define PXP_HW_PXP_HIST32_PARAM5_VALUE20(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE20_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE20_MASK)
36947 #define PXP_HW_PXP_HIST32_PARAM5_RSVD4_MASK      0xC0u
36948 #define PXP_HW_PXP_HIST32_PARAM5_RSVD4_SHIFT     6
36949 #define PXP_HW_PXP_HIST32_PARAM5_RSVD4(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD4_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD4_MASK)
36950 #define PXP_HW_PXP_HIST32_PARAM5_VALUE21_MASK    0x3F00u
36951 #define PXP_HW_PXP_HIST32_PARAM5_VALUE21_SHIFT   8
36952 #define PXP_HW_PXP_HIST32_PARAM5_VALUE21(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE21_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE21_MASK)
36953 #define PXP_HW_PXP_HIST32_PARAM5_RSVD5_MASK      0xC000u
36954 #define PXP_HW_PXP_HIST32_PARAM5_RSVD5_SHIFT     14
36955 #define PXP_HW_PXP_HIST32_PARAM5_RSVD5(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD5_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD5_MASK)
36956 #define PXP_HW_PXP_HIST32_PARAM5_VALUE22_MASK    0x3F0000u
36957 #define PXP_HW_PXP_HIST32_PARAM5_VALUE22_SHIFT   16
36958 #define PXP_HW_PXP_HIST32_PARAM5_VALUE22(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE22_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE22_MASK)
36959 #define PXP_HW_PXP_HIST32_PARAM5_RSVD6_MASK      0xC00000u
36960 #define PXP_HW_PXP_HIST32_PARAM5_RSVD6_SHIFT     22
36961 #define PXP_HW_PXP_HIST32_PARAM5_RSVD6(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD6_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD6_MASK)
36962 #define PXP_HW_PXP_HIST32_PARAM5_VALUE23_MASK    0x3F000000u
36963 #define PXP_HW_PXP_HIST32_PARAM5_VALUE23_SHIFT   24
36964 #define PXP_HW_PXP_HIST32_PARAM5_VALUE23(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE23_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE23_MASK)
36965 #define PXP_HW_PXP_HIST32_PARAM5_RSVD7_MASK      0xC0000000u
36966 #define PXP_HW_PXP_HIST32_PARAM5_RSVD7_SHIFT     30
36967 #define PXP_HW_PXP_HIST32_PARAM5_RSVD7(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD7_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD7_MASK)
36968 /* HW_PXP_HIST32_PARAM6 Bit Fields */
36969 #define PXP_HW_PXP_HIST32_PARAM6_VALUE24_MASK    0x3Fu
36970 #define PXP_HW_PXP_HIST32_PARAM6_VALUE24_SHIFT   0
36971 #define PXP_HW_PXP_HIST32_PARAM6_VALUE24(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE24_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE24_MASK)
36972 #define PXP_HW_PXP_HIST32_PARAM6_RSVD8_MASK      0xC0u
36973 #define PXP_HW_PXP_HIST32_PARAM6_RSVD8_SHIFT     6
36974 #define PXP_HW_PXP_HIST32_PARAM6_RSVD8(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD8_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD8_MASK)
36975 #define PXP_HW_PXP_HIST32_PARAM6_VALUE25_MASK    0x3F00u
36976 #define PXP_HW_PXP_HIST32_PARAM6_VALUE25_SHIFT   8
36977 #define PXP_HW_PXP_HIST32_PARAM6_VALUE25(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE25_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE25_MASK)
36978 #define PXP_HW_PXP_HIST32_PARAM6_RSVD9_MASK      0xC000u
36979 #define PXP_HW_PXP_HIST32_PARAM6_RSVD9_SHIFT     14
36980 #define PXP_HW_PXP_HIST32_PARAM6_RSVD9(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD9_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD9_MASK)
36981 #define PXP_HW_PXP_HIST32_PARAM6_VALUE26_MASK    0x3F0000u
36982 #define PXP_HW_PXP_HIST32_PARAM6_VALUE26_SHIFT   16
36983 #define PXP_HW_PXP_HIST32_PARAM6_VALUE26(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE26_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE26_MASK)
36984 #define PXP_HW_PXP_HIST32_PARAM6_RSVD10_MASK     0xC00000u
36985 #define PXP_HW_PXP_HIST32_PARAM6_RSVD10_SHIFT    22
36986 #define PXP_HW_PXP_HIST32_PARAM6_RSVD10(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD10_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD10_MASK)
36987 #define PXP_HW_PXP_HIST32_PARAM6_VALUE27_MASK    0x3F000000u
36988 #define PXP_HW_PXP_HIST32_PARAM6_VALUE27_SHIFT   24
36989 #define PXP_HW_PXP_HIST32_PARAM6_VALUE27(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE27_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE27_MASK)
36990 #define PXP_HW_PXP_HIST32_PARAM6_RSVD11_MASK     0xC0000000u
36991 #define PXP_HW_PXP_HIST32_PARAM6_RSVD11_SHIFT    30
36992 #define PXP_HW_PXP_HIST32_PARAM6_RSVD11(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD11_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD11_MASK)
36993 /* HW_PXP_HIST32_PARAM7 Bit Fields */
36994 #define PXP_HW_PXP_HIST32_PARAM7_VALUE28_MASK    0x3Fu
36995 #define PXP_HW_PXP_HIST32_PARAM7_VALUE28_SHIFT   0
36996 #define PXP_HW_PXP_HIST32_PARAM7_VALUE28(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE28_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE28_MASK)
36997 #define PXP_HW_PXP_HIST32_PARAM7_RSVD2_MASK      0xC0u
36998 #define PXP_HW_PXP_HIST32_PARAM7_RSVD2_SHIFT     6
36999 #define PXP_HW_PXP_HIST32_PARAM7_RSVD2(x)        (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD2_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD2_MASK)
37000 #define PXP_HW_PXP_HIST32_PARAM7_VALUE29_MASK    0x3F00u
37001 #define PXP_HW_PXP_HIST32_PARAM7_VALUE29_SHIFT   8
37002 #define PXP_HW_PXP_HIST32_PARAM7_VALUE29(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE29_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE29_MASK)
37003 #define PXP_HW_PXP_HIST32_PARAM7_RSVD13_MASK     0xC000u
37004 #define PXP_HW_PXP_HIST32_PARAM7_RSVD13_SHIFT    14
37005 #define PXP_HW_PXP_HIST32_PARAM7_RSVD13(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD13_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD13_MASK)
37006 #define PXP_HW_PXP_HIST32_PARAM7_VALUE30_MASK    0x3F0000u
37007 #define PXP_HW_PXP_HIST32_PARAM7_VALUE30_SHIFT   16
37008 #define PXP_HW_PXP_HIST32_PARAM7_VALUE30(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE30_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE30_MASK)
37009 #define PXP_HW_PXP_HIST32_PARAM7_RSVD14_MASK     0xC00000u
37010 #define PXP_HW_PXP_HIST32_PARAM7_RSVD14_SHIFT    22
37011 #define PXP_HW_PXP_HIST32_PARAM7_RSVD14(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD14_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD14_MASK)
37012 #define PXP_HW_PXP_HIST32_PARAM7_VALUE31_MASK    0x3F000000u
37013 #define PXP_HW_PXP_HIST32_PARAM7_VALUE31_SHIFT   24
37014 #define PXP_HW_PXP_HIST32_PARAM7_VALUE31(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE31_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE31_MASK)
37015 #define PXP_HW_PXP_HIST32_PARAM7_RSVD15_MASK     0xC0000000u
37016 #define PXP_HW_PXP_HIST32_PARAM7_RSVD15_SHIFT    30
37017 #define PXP_HW_PXP_HIST32_PARAM7_RSVD15(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD15_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD15_MASK)
37018 /* HW_PXP_COMP_CTRL Bit Fields */
37019 #define PXP_HW_PXP_COMP_CTRL_START_MASK          0x1u
37020 #define PXP_HW_PXP_COMP_CTRL_START_SHIFT         0
37021 #define PXP_HW_PXP_COMP_CTRL_RSVD1_MASK          0xFEu
37022 #define PXP_HW_PXP_COMP_CTRL_RSVD1_SHIFT         1
37023 #define PXP_HW_PXP_COMP_CTRL_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_COMP_CTRL_RSVD1_MASK)
37024 #define PXP_HW_PXP_COMP_CTRL_SW_RESET_MASK       0x100u
37025 #define PXP_HW_PXP_COMP_CTRL_SW_RESET_SHIFT      8
37026 #define PXP_HW_PXP_COMP_CTRL_RSVD0_MASK          0xFFFFFE00u
37027 #define PXP_HW_PXP_COMP_CTRL_RSVD0_SHIFT         9
37028 #define PXP_HW_PXP_COMP_CTRL_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_COMP_CTRL_RSVD0_MASK)
37029 /* HW_PXP_COMP_FORMAT0 Bit Fields */
37030 #define PXP_HW_PXP_COMP_FORMAT0_FLAG_32B_MASK    0x1u
37031 #define PXP_HW_PXP_COMP_FORMAT0_FLAG_32B_SHIFT   0
37032 #define PXP_HW_PXP_COMP_FORMAT0_RSVD3_MASK       0xEu
37033 #define PXP_HW_PXP_COMP_FORMAT0_RSVD3_SHIFT      1
37034 #define PXP_HW_PXP_COMP_FORMAT0_RSVD3(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD3_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD3_MASK)
37035 #define PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_MASK   0x30u
37036 #define PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_SHIFT  4
37037 #define PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_MASK)
37038 #define PXP_HW_PXP_COMP_FORMAT0_RSVD2_MASK       0xC0u
37039 #define PXP_HW_PXP_COMP_FORMAT0_RSVD2_SHIFT      6
37040 #define PXP_HW_PXP_COMP_FORMAT0_RSVD2(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD2_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD2_MASK)
37041 #define PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_MASK  0x300u
37042 #define PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_SHIFT 8
37043 #define PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_MASK)
37044 #define PXP_HW_PXP_COMP_FORMAT0_RSVD1_MASK       0xFC00u
37045 #define PXP_HW_PXP_COMP_FORMAT0_RSVD1_SHIFT      10
37046 #define PXP_HW_PXP_COMP_FORMAT0_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD1_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD1_MASK)
37047 #define PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_MASK 0x3FF0000u
37048 #define PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_SHIFT 16
37049 #define PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_MASK)
37050 #define PXP_HW_PXP_COMP_FORMAT0_ERR_PRONE_MASK   0x4000000u
37051 #define PXP_HW_PXP_COMP_FORMAT0_ERR_PRONE_SHIFT  26
37052 #define PXP_HW_PXP_COMP_FORMAT0_FIFOFULL_MASK    0x8000000u
37053 #define PXP_HW_PXP_COMP_FORMAT0_FIFOFULL_SHIFT   27
37054 #define PXP_HW_PXP_COMP_FORMAT0_RSVD0_MASK       0xF0000000u
37055 #define PXP_HW_PXP_COMP_FORMAT0_RSVD0_SHIFT      28
37056 #define PXP_HW_PXP_COMP_FORMAT0_RSVD0(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD0_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD0_MASK)
37057 /* HW_PXP_COMP_FORMAT1 Bit Fields */
37058 #define PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_MASK    0x1Fu
37059 #define PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_SHIFT   0
37060 #define PXP_HW_PXP_COMP_FORMAT1_A_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_MASK)
37061 #define PXP_HW_PXP_COMP_FORMAT1_A_LEN_MASK       0xE0u
37062 #define PXP_HW_PXP_COMP_FORMAT1_A_LEN_SHIFT      5
37063 #define PXP_HW_PXP_COMP_FORMAT1_A_LEN(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_A_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_A_LEN_MASK)
37064 #define PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_MASK    0x1F00u
37065 #define PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_SHIFT   8
37066 #define PXP_HW_PXP_COMP_FORMAT1_B_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_MASK)
37067 #define PXP_HW_PXP_COMP_FORMAT1_B_LEN_MASK       0xE000u
37068 #define PXP_HW_PXP_COMP_FORMAT1_B_LEN_SHIFT      13
37069 #define PXP_HW_PXP_COMP_FORMAT1_B_LEN(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_B_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_B_LEN_MASK)
37070 #define PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_MASK    0x1F0000u
37071 #define PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_SHIFT   16
37072 #define PXP_HW_PXP_COMP_FORMAT1_C_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_MASK)
37073 #define PXP_HW_PXP_COMP_FORMAT1_C_LEN_MASK       0xE00000u
37074 #define PXP_HW_PXP_COMP_FORMAT1_C_LEN_SHIFT      21
37075 #define PXP_HW_PXP_COMP_FORMAT1_C_LEN(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_C_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_C_LEN_MASK)
37076 #define PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_MASK    0x1F000000u
37077 #define PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_SHIFT   24
37078 #define PXP_HW_PXP_COMP_FORMAT1_D_OFFSET(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_MASK)
37079 #define PXP_HW_PXP_COMP_FORMAT1_D_LEN_MASK       0xE0000000u
37080 #define PXP_HW_PXP_COMP_FORMAT1_D_LEN_SHIFT      29
37081 #define PXP_HW_PXP_COMP_FORMAT1_D_LEN(x)         (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_D_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_D_LEN_MASK)
37082 /* HW_PXP_COMP_FORMAT2 Bit Fields */
37083 #define PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_MASK    0xFu
37084 #define PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_SHIFT   0
37085 #define PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_MASK)
37086 #define PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_MASK    0xF0u
37087 #define PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_SHIFT   4
37088 #define PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_MASK)
37089 #define PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_MASK    0xF00u
37090 #define PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_SHIFT   8
37091 #define PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_MASK)
37092 #define PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_MASK    0xF000u
37093 #define PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_SHIFT   12
37094 #define PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN(x)      (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_MASK)
37095 #define PXP_HW_PXP_COMP_FORMAT2_RSVD_MASK        0xFFFF0000u
37096 #define PXP_HW_PXP_COMP_FORMAT2_RSVD_SHIFT       16
37097 #define PXP_HW_PXP_COMP_FORMAT2_RSVD(x)          (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_RSVD_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_RSVD_MASK)
37098 /* HW_PXP_COMP_MASK0 Bit Fields */
37099 #define PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_MASK  0xFFFFFFFFu
37100 #define PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_SHIFT 0
37101 #define PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_SHIFT))&PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_MASK)
37102 /* HW_PXP_COMP_MASK1 Bit Fields */
37103 #define PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_MASK 0xFFFFFFFFu
37104 #define PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_SHIFT 0
37105 #define PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_SHIFT))&PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_MASK)
37106 /* HW_PXP_COMP_BUFFER_SIZE Bit Fields */
37107 #define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_MASK 0x1FFFu
37108 #define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_SHIFT 0
37109 #define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_MASK)
37110 #define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_MASK   0xE000u
37111 #define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_SHIFT  13
37112 #define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_MASK)
37113 #define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_MASK 0x1FFF0000u
37114 #define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_SHIFT 16
37115 #define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_MASK)
37116 #define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_MASK   0xE0000000u
37117 #define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_SHIFT  29
37118 #define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_MASK)
37119 /* HW_PXP_COMP_SOURCE Bit Fields */
37120 #define PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_MASK  0xFFFFFFFFu
37121 #define PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_SHIFT 0
37122 #define PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_SHIFT))&PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_MASK)
37123 /* HW_PXP_COMP_TARGET Bit Fields */
37124 #define PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_MASK  0xFFFFFFFFu
37125 #define PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_SHIFT 0
37126 #define PXP_HW_PXP_COMP_TARGET_TARGET_ADDR(x)    (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_SHIFT))&PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_MASK)
37127 /* HW_PXP_COMP_BUFFER_A Bit Fields */
37128 #define PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_MASK 0xFFFFFFFFu
37129 #define PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_SHIFT 0
37130 #define PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_MASK)
37131 /* HW_PXP_COMP_BUFFER_B Bit Fields */
37132 #define PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_MASK 0xFFFFFFFFu
37133 #define PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_SHIFT 0
37134 #define PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_MASK)
37135 /* HW_PXP_COMP_BUFFER_C Bit Fields */
37136 #define PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_MASK 0xFFFFFFFFu
37137 #define PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_SHIFT 0
37138 #define PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_MASK)
37139 /* HW_PXP_COMP_BUFFER_D Bit Fields */
37140 #define PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_MASK 0xFFFFFFFFu
37141 #define PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_SHIFT 0
37142 #define PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_MASK)
37143 /* HW_PXP_COMP_DEBUG Bit Fields */
37144 #define PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_MASK     0xFFu
37145 #define PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_SHIFT    0
37146 #define PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL(x)       (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_SHIFT))&PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_MASK)
37147 #define PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_MASK   0xFFFFFF00u
37148 #define PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_SHIFT  8
37149 #define PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE(x)     (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_SHIFT))&PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_MASK)
37150 /* HW_PXP_BUS_MUX Bit Fields */
37151 #define PXP_HW_PXP_BUS_MUX_RD_SEL_MASK           0xFFu
37152 #define PXP_HW_PXP_BUS_MUX_RD_SEL_SHIFT          0
37153 #define PXP_HW_PXP_BUS_MUX_RD_SEL(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_RD_SEL_SHIFT))&PXP_HW_PXP_BUS_MUX_RD_SEL_MASK)
37154 #define PXP_HW_PXP_BUS_MUX_RSVD0_MASK            0xFF00u
37155 #define PXP_HW_PXP_BUS_MUX_RSVD0_SHIFT           8
37156 #define PXP_HW_PXP_BUS_MUX_RSVD0(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_RSVD0_SHIFT))&PXP_HW_PXP_BUS_MUX_RSVD0_MASK)
37157 #define PXP_HW_PXP_BUS_MUX_WR_SEL_MASK           0xFF0000u
37158 #define PXP_HW_PXP_BUS_MUX_WR_SEL_SHIFT          16
37159 #define PXP_HW_PXP_BUS_MUX_WR_SEL(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_WR_SEL_SHIFT))&PXP_HW_PXP_BUS_MUX_WR_SEL_MASK)
37160 #define PXP_HW_PXP_BUS_MUX_RSVD1_MASK            0xFF000000u
37161 #define PXP_HW_PXP_BUS_MUX_RSVD1_SHIFT           24
37162 #define PXP_HW_PXP_BUS_MUX_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_RSVD1_SHIFT))&PXP_HW_PXP_BUS_MUX_RSVD1_MASK)
37163 /* HW_PXP_HANDSHAKE_READY_MUX0 Bit Fields */
37164 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_MASK 0xFu
37165 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT 0
37166 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_MASK)
37167 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_MASK 0xF0u
37168 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT 4
37169 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_MASK)
37170 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_MASK 0xF00u
37171 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT 8
37172 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_MASK)
37173 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_MASK 0xF000u
37174 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT 12
37175 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_MASK)
37176 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_MASK 0xF0000u
37177 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT 16
37178 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_MASK)
37179 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_MASK 0xF00000u
37180 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT 20
37181 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_MASK)
37182 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_MASK 0xF000000u
37183 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT 24
37184 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_MASK)
37185 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_MASK 0xF0000000u
37186 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT 28
37187 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_MASK)
37188 /* HW_PXP_HANDSHAKE_READY_MUX1 Bit Fields */
37189 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_MASK 0xFu
37190 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT 0
37191 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_MASK)
37192 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_MASK 0xF0u
37193 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT 4
37194 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_MASK)
37195 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_MASK 0xF00u
37196 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT 8
37197 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_MASK)
37198 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_MASK 0xF000u
37199 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT 12
37200 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_MASK)
37201 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_MASK 0xF0000u
37202 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT 16
37203 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_MASK)
37204 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_MASK 0xF00000u
37205 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT 20
37206 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_MASK)
37207 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_MASK 0xF000000u
37208 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT 24
37209 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_MASK)
37210 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_MASK 0xF0000000u
37211 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT 28
37212 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_MASK)
37213 /* HW_PXP_HANDSHAKE_DONE_MUX0 Bit Fields */
37214 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK 0xFu
37215 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT 0
37216 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK)
37217 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK 0xF0u
37218 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT 4
37219 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK)
37220 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK 0xF00u
37221 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT 8
37222 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK)
37223 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK 0xF000u
37224 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT 12
37225 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK)
37226 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK 0xF0000u
37227 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT 16
37228 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK)
37229 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK 0xF00000u
37230 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT 20
37231 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK)
37232 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK 0xF000000u
37233 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT 24
37234 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK)
37235 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK 0xF0000000u
37236 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT 28
37237 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK)
37238 /* HW_PXP_HANDSHAKE_DONE_MUX1 Bit Fields */
37239 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK 0xFu
37240 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT 0
37241 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK)
37242 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK 0xF0u
37243 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT 4
37244 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9(x)   (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK)
37245 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK 0xF00u
37246 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT 8
37247 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK)
37248 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK 0xF000u
37249 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT 12
37250 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK)
37251 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK 0xF0000u
37252 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT 16
37253 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK)
37254 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK 0xF00000u
37255 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT 20
37256 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK)
37257 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK 0xF000000u
37258 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT 24
37259 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK)
37260 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK 0xF0000000u
37261 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT 28
37262 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK)
37263 /* HW_PXP_HANDSHAKE_CPU_FETCH Bit Fields */
37264 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_MASK 0x1u
37265 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_SHIFT 0
37266 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_MASK 0x2u
37267 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_SHIFT 1
37268 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_MASK 0x4u
37269 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_SHIFT 2
37270 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_MASK 0x8u
37271 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_SHIFT 3
37272 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_MASK 0x30u
37273 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_SHIFT 4
37274 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_MASK)
37275 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_MASK 0x7FC0u
37276 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_SHIFT 6
37277 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_MASK)
37278 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_MASK 0x8000u
37279 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_SHIFT 15
37280 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_MASK 0x10000u
37281 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_SHIFT 16
37282 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_MASK 0x20000u
37283 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_SHIFT 17
37284 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_MASK 0x40000u
37285 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_SHIFT 18
37286 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_MASK 0x80000u
37287 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_SHIFT 19
37288 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_MASK 0x300000u
37289 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_SHIFT 20
37290 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_MASK)
37291 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_MASK 0x7FC00000u
37292 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_SHIFT 22
37293 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_MASK)
37294 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_MASK 0x80000000u
37295 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_SHIFT 31
37296 /* HW_PXP_HANDSHAKE_CPU_STORE Bit Fields */
37297 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_MASK 0x1u
37298 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_SHIFT 0
37299 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_MASK 0x2u
37300 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_SHIFT 1
37301 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_MASK 0x4u
37302 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_SHIFT 2
37303 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_MASK 0x8u
37304 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_SHIFT 3
37305 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_MASK 0x30u
37306 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_SHIFT 4
37307 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_MASK)
37308 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_MASK 0x7FC0u
37309 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_SHIFT 6
37310 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_MASK)
37311 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_MASK 0x8000u
37312 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_SHIFT 15
37313 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_MASK 0x10000u
37314 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_SHIFT 16
37315 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_MASK 0x20000u
37316 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_SHIFT 17
37317 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_MASK 0x40000u
37318 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_SHIFT 18
37319 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_MASK 0x80000u
37320 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_SHIFT 19
37321 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_MASK 0x300000u
37322 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_SHIFT 20
37323 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_MASK)
37324 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_MASK 0x7FC00000u
37325 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_SHIFT 22
37326 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1(x)  (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_MASK)
37327 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_MASK 0x80000000u
37328 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_SHIFT 31
37329 
37330 /*!
37331  * @}
37332  */ /* end of group PXP_Register_Masks */
37333 
37334 /* PXP - Peripheral instance base addresses */
37335 /** Peripheral PXP base address */
37336 #define PXP_BASE                                 (0x30700000u)
37337 /** Peripheral PXP base pointer */
37338 #define PXP                                      ((PXP_Type *)PXP_BASE)
37339 #define PXP_BASE_PTR                             (PXP)
37340 /** Array initializer of PXP peripheral base addresses */
37341 #define PXP_BASE_ADDRS                           { PXP_BASE }
37342 /** Array initializer of PXP peripheral base pointers */
37343 #define PXP_BASE_PTRS                            { PXP }
37344 /* ----------------------------------------------------------------------------
37345    -- PXP - Register accessor macros
37346    ---------------------------------------------------------------------------- */
37347 
37348 /*!
37349  * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros
37350  * @{
37351  */
37352 
37353 
37354 /* PXP - Register instance definitions */
37355 /* PXP */
37356 #define PXP_HW_PXP_CTRL                          PXP_HW_PXP_CTRL_REG(PXP_BASE_PTR)
37357 #define PXP_HW_PXP_STAT                          PXP_HW_PXP_STAT_REG(PXP_BASE_PTR)
37358 #define PXP_HW_PXP_OUT_CTRL                      PXP_HW_PXP_OUT_CTRL_REG(PXP_BASE_PTR)
37359 #define PXP_HW_PXP_OUT_BUF                       PXP_HW_PXP_OUT_BUF_REG(PXP_BASE_PTR)
37360 #define PXP_HW_PXP_OUT_BUF2                      PXP_HW_PXP_OUT_BUF2_REG(PXP_BASE_PTR)
37361 #define PXP_HW_PXP_OUT_PITCH                     PXP_HW_PXP_OUT_PITCH_REG(PXP_BASE_PTR)
37362 #define PXP_HW_PXP_OUT_LRC                       PXP_HW_PXP_OUT_LRC_REG(PXP_BASE_PTR)
37363 #define PXP_HW_PXP_OUT_PS_ULC                    PXP_HW_PXP_OUT_PS_ULC_REG(PXP_BASE_PTR)
37364 #define PXP_HW_PXP_OUT_PS_LRC                    PXP_HW_PXP_OUT_PS_LRC_REG(PXP_BASE_PTR)
37365 #define PXP_HW_PXP_OUT_AS_ULC                    PXP_HW_PXP_OUT_AS_ULC_REG(PXP_BASE_PTR)
37366 #define PXP_HW_PXP_OUT_AS_LRC                    PXP_HW_PXP_OUT_AS_LRC_REG(PXP_BASE_PTR)
37367 #define PXP_HW_PXP_PS_CTRL                       PXP_HW_PXP_PS_CTRL_REG(PXP_BASE_PTR)
37368 #define PXP_HW_PXP_PS_BUF                        PXP_HW_PXP_PS_BUF_REG(PXP_BASE_PTR)
37369 #define PXP_HW_PXP_PS_UBUF                       PXP_HW_PXP_PS_UBUF_REG(PXP_BASE_PTR)
37370 #define PXP_HW_PXP_PS_VBUF                       PXP_HW_PXP_PS_VBUF_REG(PXP_BASE_PTR)
37371 #define PXP_HW_PXP_PS_PITCH                      PXP_HW_PXP_PS_PITCH_REG(PXP_BASE_PTR)
37372 #define PXP_HW_PXP_PS_BACKGROUND_0               PXP_HW_PXP_PS_BACKGROUND_0_REG(PXP_BASE_PTR)
37373 #define PXP_HW_PXP_PS_SCALE                      PXP_HW_PXP_PS_SCALE_REG(PXP_BASE_PTR)
37374 #define PXP_HW_PXP_PS_OFFSET                     PXP_HW_PXP_PS_OFFSET_REG(PXP_BASE_PTR)
37375 #define PXP_HW_PXP_PS_CLRKEYLOW_0                PXP_HW_PXP_PS_CLRKEYLOW_0_REG(PXP_BASE_PTR)
37376 #define PXP_HW_PXP_PS_CLRKEYHIGH_0               PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(PXP_BASE_PTR)
37377 #define PXP_HW_PXP_AS_CTRL                       PXP_HW_PXP_AS_CTRL_REG(PXP_BASE_PTR)
37378 #define PXP_HW_PXP_AS_BUF                        PXP_HW_PXP_AS_BUF_REG(PXP_BASE_PTR)
37379 #define PXP_HW_PXP_AS_PITCH                      PXP_HW_PXP_AS_PITCH_REG(PXP_BASE_PTR)
37380 #define PXP_HW_PXP_AS_CLRKEYLOW_0                PXP_HW_PXP_AS_CLRKEYLOW_0_REG(PXP_BASE_PTR)
37381 #define PXP_HW_PXP_AS_CLRKEYHIGH_0               PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(PXP_BASE_PTR)
37382 #define PXP_HW_PXP_CSC1_COEF0                    PXP_HW_PXP_CSC1_COEF0_REG(PXP_BASE_PTR)
37383 #define PXP_HW_PXP_CSC1_COEF1                    PXP_HW_PXP_CSC1_COEF1_REG(PXP_BASE_PTR)
37384 #define PXP_HW_PXP_CSC1_COEF2                    PXP_HW_PXP_CSC1_COEF2_REG(PXP_BASE_PTR)
37385 #define PXP_HW_PXP_CSC2_CTRL                     PXP_HW_PXP_CSC2_CTRL_REG(PXP_BASE_PTR)
37386 #define PXP_HW_PXP_CSC2_COEF0                    PXP_HW_PXP_CSC2_COEF0_REG(PXP_BASE_PTR)
37387 #define PXP_HW_PXP_CSC2_COEF1                    PXP_HW_PXP_CSC2_COEF1_REG(PXP_BASE_PTR)
37388 #define PXP_HW_PXP_CSC2_COEF2                    PXP_HW_PXP_CSC2_COEF2_REG(PXP_BASE_PTR)
37389 #define PXP_HW_PXP_CSC2_COEF3                    PXP_HW_PXP_CSC2_COEF3_REG(PXP_BASE_PTR)
37390 #define PXP_HW_PXP_CSC2_COEF4                    PXP_HW_PXP_CSC2_COEF4_REG(PXP_BASE_PTR)
37391 #define PXP_HW_PXP_CSC2_COEF5                    PXP_HW_PXP_CSC2_COEF5_REG(PXP_BASE_PTR)
37392 #define PXP_HW_PXP_LUT_CTRL                      PXP_HW_PXP_LUT_CTRL_REG(PXP_BASE_PTR)
37393 #define PXP_HW_PXP_LUT_ADDR                      PXP_HW_PXP_LUT_ADDR_REG(PXP_BASE_PTR)
37394 #define PXP_HW_PXP_LUT_DATA                      PXP_HW_PXP_LUT_DATA_REG(PXP_BASE_PTR)
37395 #define PXP_HW_PXP_LUT_EXTMEM                    PXP_HW_PXP_LUT_EXTMEM_REG(PXP_BASE_PTR)
37396 #define PXP_HW_PXP_CFA                           PXP_HW_PXP_CFA_REG(PXP_BASE_PTR)
37397 #define PXP_HW_PXP_ALPHA_A_CTRL                  PXP_HW_PXP_ALPHA_A_CTRL_REG(PXP_BASE_PTR)
37398 #define PXP_HW_PXP_ALPHA_B_CTRL                  PXP_HW_PXP_ALPHA_B_CTRL_REG(PXP_BASE_PTR)
37399 #define PXP_HW_PXP_ALPHA_B_CTRL_1                PXP_HW_PXP_ALPHA_B_CTRL_1_REG(PXP_BASE_PTR)
37400 #define PXP_HW_PXP_PS_BACKGROUND_1               PXP_HW_PXP_PS_BACKGROUND_1_REG(PXP_BASE_PTR)
37401 #define PXP_HW_PXP_PS_CLRKEYLOW_1                PXP_HW_PXP_PS_CLRKEYLOW_1_REG(PXP_BASE_PTR)
37402 #define PXP_HW_PXP_PS_CLRKEYHIGH_1               PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(PXP_BASE_PTR)
37403 #define PXP_HW_PXP_AS_CLRKEYLOW_1                PXP_HW_PXP_AS_CLRKEYLOW_1_REG(PXP_BASE_PTR)
37404 #define PXP_HW_PXP_AS_CLRKEYHIGH_1               PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(PXP_BASE_PTR)
37405 #define PXP_HW_PXP_CTRL2                         PXP_HW_PXP_CTRL2_REG(PXP_BASE_PTR)
37406 #define PXP_HW_PXP_POWER_REG0                    PXP_HW_PXP_POWER_REG0_REG(PXP_BASE_PTR)
37407 #define PXP_HW_PXP_POWER_REG1                    PXP_HW_PXP_POWER_REG1_REG(PXP_BASE_PTR)
37408 #define PXP_HW_PXP_DATA_PATH_CTRL0               PXP_HW_PXP_DATA_PATH_CTRL0_REG(PXP_BASE_PTR)
37409 #define PXP_HW_PXP_DATA_PATH_CTRL1               PXP_HW_PXP_DATA_PATH_CTRL1_REG(PXP_BASE_PTR)
37410 #define PXP_HW_PXP_INIT_MEM_CTRL                 PXP_HW_PXP_INIT_MEM_CTRL_REG(PXP_BASE_PTR)
37411 #define PXP_HW_PXP_INIT_MEM_DATA                 PXP_HW_PXP_INIT_MEM_DATA_REG(PXP_BASE_PTR)
37412 #define PXP_HW_PXP_INIT_MEM_DATA_HIGH            PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(PXP_BASE_PTR)
37413 #define PXP_HW_PXP_IRQ_MASK                      PXP_HW_PXP_IRQ_MASK_REG(PXP_BASE_PTR)
37414 #define PXP_HW_PXP_IRQ                           PXP_HW_PXP_IRQ_REG(PXP_BASE_PTR)
37415 #define PXP_HW_PXP_NEXT                          PXP_HW_PXP_NEXT_REG(PXP_BASE_PTR)
37416 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0          PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(PXP_BASE_PTR)
37417 #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1          PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(PXP_BASE_PTR)
37418 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0        PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(PXP_BASE_PTR)
37419 #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1        PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(PXP_BASE_PTR)
37420 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(PXP_BASE_PTR)
37421 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(PXP_BASE_PTR)
37422 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(PXP_BASE_PTR)
37423 #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(PXP_BASE_PTR)
37424 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0          PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(PXP_BASE_PTR)
37425 #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1          PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(PXP_BASE_PTR)
37426 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(PXP_BASE_PTR)
37427 #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(PXP_BASE_PTR)
37428 #define PXP_HW_PXP_INPUT_FETCH_PITCH             PXP_HW_PXP_INPUT_FETCH_PITCH_REG(PXP_BASE_PTR)
37429 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0    PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR)
37430 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1    PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR)
37431 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0  PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(PXP_BASE_PTR)
37432 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1  PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(PXP_BASE_PTR)
37433 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0   PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(PXP_BASE_PTR)
37434 #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1   PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(PXP_BASE_PTR)
37435 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0        PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(PXP_BASE_PTR)
37436 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0        PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(PXP_BASE_PTR)
37437 #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1        PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(PXP_BASE_PTR)
37438 #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1        PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(PXP_BASE_PTR)
37439 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0          PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(PXP_BASE_PTR)
37440 #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1          PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(PXP_BASE_PTR)
37441 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0        PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(PXP_BASE_PTR)
37442 #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1        PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(PXP_BASE_PTR)
37443 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0          PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(PXP_BASE_PTR)
37444 #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1          PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(PXP_BASE_PTR)
37445 #define PXP_HW_PXP_INPUT_STORE_PITCH             PXP_HW_PXP_INPUT_STORE_PITCH_REG(PXP_BASE_PTR)
37446 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0    PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR)
37447 #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1    PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR)
37448 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0        PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(PXP_BASE_PTR)
37449 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0        PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(PXP_BASE_PTR)
37450 #define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0     PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(PXP_BASE_PTR)
37451 #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1        PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(PXP_BASE_PTR)
37452 #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1        PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(PXP_BASE_PTR)
37453 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(PXP_BASE_PTR)
37454 #define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(PXP_BASE_PTR)
37455 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(PXP_BASE_PTR)
37456 #define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(PXP_BASE_PTR)
37457 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(PXP_BASE_PTR)
37458 #define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(PXP_BASE_PTR)
37459 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(PXP_BASE_PTR)
37460 #define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(PXP_BASE_PTR)
37461 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(PXP_BASE_PTR)
37462 #define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(PXP_BASE_PTR)
37463 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(PXP_BASE_PTR)
37464 #define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(PXP_BASE_PTR)
37465 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(PXP_BASE_PTR)
37466 #define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(PXP_BASE_PTR)
37467 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(PXP_BASE_PTR)
37468 #define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0     PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(PXP_BASE_PTR)
37469 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0     PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(PXP_BASE_PTR)
37470 #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0     PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(PXP_BASE_PTR)
37471 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0     PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(PXP_BASE_PTR)
37472 #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0     PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(PXP_BASE_PTR)
37473 #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0      PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(PXP_BASE_PTR)
37474 #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0      PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(PXP_BASE_PTR)
37475 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0         PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(PXP_BASE_PTR)
37476 #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1         PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(PXP_BASE_PTR)
37477 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0       PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(PXP_BASE_PTR)
37478 #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1       PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(PXP_BASE_PTR)
37479 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(PXP_BASE_PTR)
37480 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(PXP_BASE_PTR)
37481 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(PXP_BASE_PTR)
37482 #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(PXP_BASE_PTR)
37483 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0         PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(PXP_BASE_PTR)
37484 #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1         PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(PXP_BASE_PTR)
37485 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(PXP_BASE_PTR)
37486 #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(PXP_BASE_PTR)
37487 #define PXP_HW_PXP_DITHER_FETCH_PITCH            PXP_HW_PXP_DITHER_FETCH_PITCH_REG(PXP_BASE_PTR)
37488 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0   PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR)
37489 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1   PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR)
37490 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(PXP_BASE_PTR)
37491 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(PXP_BASE_PTR)
37492 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0  PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(PXP_BASE_PTR)
37493 #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1  PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(PXP_BASE_PTR)
37494 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0       PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(PXP_BASE_PTR)
37495 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0       PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(PXP_BASE_PTR)
37496 #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1       PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(PXP_BASE_PTR)
37497 #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1       PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(PXP_BASE_PTR)
37498 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0         PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(PXP_BASE_PTR)
37499 #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1         PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(PXP_BASE_PTR)
37500 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0       PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(PXP_BASE_PTR)
37501 #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1       PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(PXP_BASE_PTR)
37502 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0         PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(PXP_BASE_PTR)
37503 #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1         PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(PXP_BASE_PTR)
37504 #define PXP_HW_PXP_DITHER_STORE_PITCH            PXP_HW_PXP_DITHER_STORE_PITCH_REG(PXP_BASE_PTR)
37505 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0   PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR)
37506 #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1   PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR)
37507 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0       PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(PXP_BASE_PTR)
37508 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0       PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(PXP_BASE_PTR)
37509 #define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0    PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(PXP_BASE_PTR)
37510 #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1       PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(PXP_BASE_PTR)
37511 #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1       PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(PXP_BASE_PTR)
37512 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(PXP_BASE_PTR)
37513 #define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(PXP_BASE_PTR)
37514 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(PXP_BASE_PTR)
37515 #define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(PXP_BASE_PTR)
37516 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(PXP_BASE_PTR)
37517 #define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(PXP_BASE_PTR)
37518 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(PXP_BASE_PTR)
37519 #define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(PXP_BASE_PTR)
37520 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(PXP_BASE_PTR)
37521 #define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(PXP_BASE_PTR)
37522 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(PXP_BASE_PTR)
37523 #define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(PXP_BASE_PTR)
37524 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(PXP_BASE_PTR)
37525 #define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(PXP_BASE_PTR)
37526 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(PXP_BASE_PTR)
37527 #define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0    PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(PXP_BASE_PTR)
37528 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0    PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(PXP_BASE_PTR)
37529 #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0    PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(PXP_BASE_PTR)
37530 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0    PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(PXP_BASE_PTR)
37531 #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0    PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(PXP_BASE_PTR)
37532 #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0     PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(PXP_BASE_PTR)
37533 #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0     PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(PXP_BASE_PTR)
37534 #define PXP_HW_PXP_DITHER_CTRL                   PXP_HW_PXP_DITHER_CTRL_REG(PXP_BASE_PTR)
37535 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0        PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(PXP_BASE_PTR)
37536 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1        PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(PXP_BASE_PTR)
37537 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2        PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(PXP_BASE_PTR)
37538 #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3        PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(PXP_BASE_PTR)
37539 #define PXP_HW_PXP_HIST_A_CTRL                   PXP_HW_PXP_HIST_A_CTRL_REG(PXP_BASE_PTR)
37540 #define PXP_HW_PXP_HIST_A_MASK                   PXP_HW_PXP_HIST_A_MASK_REG(PXP_BASE_PTR)
37541 #define PXP_HW_PXP_HIST_A_BUF_SIZE               PXP_HW_PXP_HIST_A_BUF_SIZE_REG(PXP_BASE_PTR)
37542 #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL            PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(PXP_BASE_PTR)
37543 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X          PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(PXP_BASE_PTR)
37544 #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y          PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(PXP_BASE_PTR)
37545 #define PXP_HW_PXP_HIST_A_RAW_STAT0              PXP_HW_PXP_HIST_A_RAW_STAT0_REG(PXP_BASE_PTR)
37546 #define PXP_HW_PXP_HIST_A_RAW_STAT1              PXP_HW_PXP_HIST_A_RAW_STAT1_REG(PXP_BASE_PTR)
37547 #define PXP_HW_PXP_HIST_B_CTRL                   PXP_HW_PXP_HIST_B_CTRL_REG(PXP_BASE_PTR)
37548 #define PXP_HW_PXP_HIST_B_MASK                   PXP_HW_PXP_HIST_B_MASK_REG(PXP_BASE_PTR)
37549 #define PXP_HW_PXP_HIST_B_BUF_SIZE               PXP_HW_PXP_HIST_B_BUF_SIZE_REG(PXP_BASE_PTR)
37550 #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL            PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(PXP_BASE_PTR)
37551 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X          PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(PXP_BASE_PTR)
37552 #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y          PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(PXP_BASE_PTR)
37553 #define PXP_HW_PXP_HIST_B_RAW_STAT0              PXP_HW_PXP_HIST_B_RAW_STAT0_REG(PXP_BASE_PTR)
37554 #define PXP_HW_PXP_HIST_B_RAW_STAT1              PXP_HW_PXP_HIST_B_RAW_STAT1_REG(PXP_BASE_PTR)
37555 #define PXP_HW_PXP_HIST2_PARAM                   PXP_HW_PXP_HIST2_PARAM_REG(PXP_BASE_PTR)
37556 #define PXP_HW_PXP_HIST4_PARAM                   PXP_HW_PXP_HIST4_PARAM_REG(PXP_BASE_PTR)
37557 #define PXP_HW_PXP_HIST8_PARAM0                  PXP_HW_PXP_HIST8_PARAM0_REG(PXP_BASE_PTR)
37558 #define PXP_HW_PXP_HIST8_PARAM1                  PXP_HW_PXP_HIST8_PARAM1_REG(PXP_BASE_PTR)
37559 #define PXP_HW_PXP_HIST16_PARAM0                 PXP_HW_PXP_HIST16_PARAM0_REG(PXP_BASE_PTR)
37560 #define PXP_HW_PXP_HIST16_PARAM1                 PXP_HW_PXP_HIST16_PARAM1_REG(PXP_BASE_PTR)
37561 #define PXP_HW_PXP_HIST16_PARAM2                 PXP_HW_PXP_HIST16_PARAM2_REG(PXP_BASE_PTR)
37562 #define PXP_HW_PXP_HIST16_PARAM3                 PXP_HW_PXP_HIST16_PARAM3_REG(PXP_BASE_PTR)
37563 #define PXP_HW_PXP_HIST32_PARAM0                 PXP_HW_PXP_HIST32_PARAM0_REG(PXP_BASE_PTR)
37564 #define PXP_HW_PXP_HIST32_PARAM1                 PXP_HW_PXP_HIST32_PARAM1_REG(PXP_BASE_PTR)
37565 #define PXP_HW_PXP_HIST32_PARAM2                 PXP_HW_PXP_HIST32_PARAM2_REG(PXP_BASE_PTR)
37566 #define PXP_HW_PXP_HIST32_PARAM3                 PXP_HW_PXP_HIST32_PARAM3_REG(PXP_BASE_PTR)
37567 #define PXP_HW_PXP_HIST32_PARAM4                 PXP_HW_PXP_HIST32_PARAM4_REG(PXP_BASE_PTR)
37568 #define PXP_HW_PXP_HIST32_PARAM5                 PXP_HW_PXP_HIST32_PARAM5_REG(PXP_BASE_PTR)
37569 #define PXP_HW_PXP_HIST32_PARAM6                 PXP_HW_PXP_HIST32_PARAM6_REG(PXP_BASE_PTR)
37570 #define PXP_HW_PXP_HIST32_PARAM7                 PXP_HW_PXP_HIST32_PARAM7_REG(PXP_BASE_PTR)
37571 #define PXP_HW_PXP_COMP_CTRL                     PXP_HW_PXP_COMP_CTRL_REG(PXP_BASE_PTR)
37572 #define PXP_HW_PXP_COMP_FORMAT0                  PXP_HW_PXP_COMP_FORMAT0_REG(PXP_BASE_PTR)
37573 #define PXP_HW_PXP_COMP_FORMAT1                  PXP_HW_PXP_COMP_FORMAT1_REG(PXP_BASE_PTR)
37574 #define PXP_HW_PXP_COMP_FORMAT2                  PXP_HW_PXP_COMP_FORMAT2_REG(PXP_BASE_PTR)
37575 #define PXP_HW_PXP_COMP_MASK0                    PXP_HW_PXP_COMP_MASK0_REG(PXP_BASE_PTR)
37576 #define PXP_HW_PXP_COMP_MASK1                    PXP_HW_PXP_COMP_MASK1_REG(PXP_BASE_PTR)
37577 #define PXP_HW_PXP_COMP_BUFFER_SIZE              PXP_HW_PXP_COMP_BUFFER_SIZE_REG(PXP_BASE_PTR)
37578 #define PXP_HW_PXP_COMP_SOURCE                   PXP_HW_PXP_COMP_SOURCE_REG(PXP_BASE_PTR)
37579 #define PXP_HW_PXP_COMP_TARGET                   PXP_HW_PXP_COMP_TARGET_REG(PXP_BASE_PTR)
37580 #define PXP_HW_PXP_COMP_BUFFER_A                 PXP_HW_PXP_COMP_BUFFER_A_REG(PXP_BASE_PTR)
37581 #define PXP_HW_PXP_COMP_BUFFER_B                 PXP_HW_PXP_COMP_BUFFER_B_REG(PXP_BASE_PTR)
37582 #define PXP_HW_PXP_COMP_BUFFER_C                 PXP_HW_PXP_COMP_BUFFER_C_REG(PXP_BASE_PTR)
37583 #define PXP_HW_PXP_COMP_BUFFER_D                 PXP_HW_PXP_COMP_BUFFER_D_REG(PXP_BASE_PTR)
37584 #define PXP_HW_PXP_COMP_DEBUG                    PXP_HW_PXP_COMP_DEBUG_REG(PXP_BASE_PTR)
37585 #define PXP_HW_PXP_BUS_MUX                       PXP_HW_PXP_BUS_MUX_REG(PXP_BASE_PTR)
37586 #define PXP_HW_PXP_HANDSHAKE_READY_MUX0          PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(PXP_BASE_PTR)
37587 #define PXP_HW_PXP_HANDSHAKE_READY_MUX1          PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(PXP_BASE_PTR)
37588 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0           PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(PXP_BASE_PTR)
37589 #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1           PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(PXP_BASE_PTR)
37590 #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH           PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(PXP_BASE_PTR)
37591 #define PXP_HW_PXP_HANDSHAKE_CPU_STORE           PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(PXP_BASE_PTR)
37592 /*!
37593  * @}
37594  */ /* end of group PXP_Register_Accessor_Macros */
37595 
37596 
37597 /*!
37598  * @}
37599  */ /* end of group PXP_Peripheral */
37600 
37601 /* ----------------------------------------------------------------------------
37602    -- QuadSPI Peripheral Access Layer
37603    ---------------------------------------------------------------------------- */
37604 
37605 /*!
37606  * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
37607  * @{
37608  */
37609 
37610 /** QuadSPI - Register Layout Typedef */
37611 typedef struct {
37612   __IO  uint32_t MCR;                                    /**< Module Configuration Register, offset: 0x0 */
37613   uint8_t RESERVED_0[4];
37614   __IO  uint32_t IPCR;                                   /**< IP Configuration Register, offset: 0x8 */
37615   __IO  uint32_t FLSHCR;                                 /**< Flash Configuration Register, offset: 0xC */
37616   __IO  uint32_t BUF0CR;                                 /**< Buffer0 Configuration Register, offset: 0x10 */
37617   __IO  uint32_t BUF1CR;                                 /**< Buffer1 Configuration Register, offset: 0x14 */
37618   __IO  uint32_t BUF2CR;                                 /**< Buffer2 Configuration Register, offset: 0x18 */
37619   __IO  uint32_t BUF3CR;                                 /**< Buffer3 Configuration Register, offset: 0x1C */
37620   __IO  uint32_t BFGENCR;                                /**< Buffer Generic Configuration Register, offset: 0x20 */
37621   uint8_t RESERVED_1[12];
37622   __IO  uint32_t BUF0IND;                                /**< Buffer0 Top Index Register, offset: 0x30 */
37623   __IO  uint32_t BUF1IND;                                /**< Buffer1 Top Index Register, offset: 0x34 */
37624   __IO  uint32_t BUF2IND;                                /**< Buffer2 Top Index Register, offset: 0x38 */
37625   uint8_t RESERVED_2[196];
37626   __IO  uint32_t SFAR;                                   /**< Serial Flash Address Register, offset: 0x100 */
37627   uint8_t RESERVED_3[4];
37628   __IO  uint32_t SMPR;                                   /**< Sampling Register, offset: 0x108 */
37629   __I   uint32_t RBSR;                                   /**< RX Buffer Status Register, offset: 0x10C */
37630   __IO  uint32_t RBCT;                                   /**< RX Buffer Control Register, offset: 0x110 */
37631   uint8_t RESERVED_4[60];
37632   __I   uint32_t TBSR;                                   /**< TX Buffer Status Register, offset: 0x150 */
37633   __IO  uint32_t TBDR;                                   /**< TX Buffer Data Register, offset: 0x154 */
37634   uint8_t RESERVED_5[4];
37635   __I   uint32_t SR;                                     /**< Status Register, offset: 0x15C */
37636   __IO  uint32_t FR;                                     /**< Flag Register, offset: 0x160 */
37637   __IO  uint32_t RSER;                                   /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
37638   __I   uint32_t SPNDST;                                 /**< Sequence Suspend Status Register, offset: 0x168 */
37639   __IO  uint32_t SPTRCLR;                                /**< Sequence Pointer Clear Register, offset: 0x16C */
37640   uint8_t RESERVED_6[16];
37641   __IO  uint32_t SFA1AD;                                 /**< Serial Flash A1 Top Address, offset: 0x180 */
37642   __IO  uint32_t SFA2AD;                                 /**< Serial Flash A2 Top Address, offset: 0x184 */
37643   __IO  uint32_t SFB1AD;                                 /**< Serial Flash B1Top Address, offset: 0x188 */
37644   __IO  uint32_t SFB2AD;                                 /**< Serial Flash B2Top Address, offset: 0x18C */
37645   uint8_t RESERVED_7[112];
37646   __IO  uint32_t RBDR[32];                               /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
37647   uint8_t RESERVED_8[128];
37648   __IO  uint32_t LUTKEY;                                 /**< LUT Key Register, offset: 0x300 */
37649   __IO  uint32_t LCKCR;                                  /**< LUT Lock Configuration Register, offset: 0x304 */
37650   uint8_t RESERVED_9[8];
37651   __IO  uint32_t LUT[64];                                /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
37652 } QuadSPI_Type, *QuadSPI_MemMapPtr;
37653 /* ----------------------------------------------------------------------------
37654    -- QuadSPI - Register accessor macros
37655    ---------------------------------------------------------------------------- */
37656 
37657 /*!
37658  * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros
37659  * @{
37660  */
37661 
37662 
37663 /* QuadSPI - Register accessors */
37664 #define QuadSPI_MCR_REG(base)                    ((base)->MCR)
37665 #define QuadSPI_IPCR_REG(base)                   ((base)->IPCR)
37666 #define QuadSPI_FLSHCR_REG(base)                 ((base)->FLSHCR)
37667 #define QuadSPI_BUF0CR_REG(base)                 ((base)->BUF0CR)
37668 #define QuadSPI_BUF1CR_REG(base)                 ((base)->BUF1CR)
37669 #define QuadSPI_BUF2CR_REG(base)                 ((base)->BUF2CR)
37670 #define QuadSPI_BUF3CR_REG(base)                 ((base)->BUF3CR)
37671 #define QuadSPI_BFGENCR_REG(base)                ((base)->BFGENCR)
37672 #define QuadSPI_BUF0IND_REG(base)                ((base)->BUF0IND)
37673 #define QuadSPI_BUF1IND_REG(base)                ((base)->BUF1IND)
37674 #define QuadSPI_BUF2IND_REG(base)                ((base)->BUF2IND)
37675 #define QuadSPI_SFAR_REG(base)                   ((base)->SFAR)
37676 #define QuadSPI_SMPR_REG(base)                   ((base)->SMPR)
37677 #define QuadSPI_RBSR_REG(base)                   ((base)->RBSR)
37678 #define QuadSPI_RBCT_REG(base)                   ((base)->RBCT)
37679 #define QuadSPI_TBSR_REG(base)                   ((base)->TBSR)
37680 #define QuadSPI_TBDR_REG(base)                   ((base)->TBDR)
37681 #define QuadSPI_SR_REG(base)                     ((base)->SR)
37682 #define QuadSPI_FR_REG(base)                     ((base)->FR)
37683 #define QuadSPI_RSER_REG(base)                   ((base)->RSER)
37684 #define QuadSPI_SPNDST_REG(base)                 ((base)->SPNDST)
37685 #define QuadSPI_SPTRCLR_REG(base)                ((base)->SPTRCLR)
37686 #define QuadSPI_SFA1AD_REG(base)                 ((base)->SFA1AD)
37687 #define QuadSPI_SFA2AD_REG(base)                 ((base)->SFA2AD)
37688 #define QuadSPI_SFB1AD_REG(base)                 ((base)->SFB1AD)
37689 #define QuadSPI_SFB2AD_REG(base)                 ((base)->SFB2AD)
37690 #define QuadSPI_RBDR_REG(base,index)             ((base)->RBDR[index])
37691 #define QuadSPI_LUTKEY_REG(base)                 ((base)->LUTKEY)
37692 #define QuadSPI_LCKCR_REG(base)                  ((base)->LCKCR)
37693 #define QuadSPI_LUT_REG(base,index)              ((base)->LUT[index])
37694 
37695 /*!
37696  * @}
37697  */ /* end of group QuadSPI_Register_Accessor_Macros */
37698 /* ----------------------------------------------------------------------------
37699    -- QuadSPI Register Masks
37700    ---------------------------------------------------------------------------- */
37701 
37702 /*!
37703  * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
37704  * @{
37705  */
37706 
37707 /* MCR Bit Fields */
37708 #define QuadSPI_MCR_SWRSTSD_MASK                 0x1u
37709 #define QuadSPI_MCR_SWRSTSD_SHIFT                0
37710 #define QuadSPI_MCR_SWRSTHD_MASK                 0x2u
37711 #define QuadSPI_MCR_SWRSTHD_SHIFT                1
37712 #define QuadSPI_MCR_END_CFG_MASK                 0xCu
37713 #define QuadSPI_MCR_END_CFG_SHIFT                2
37714 #define QuadSPI_MCR_END_CFG(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_END_CFG_SHIFT))&QuadSPI_MCR_END_CFG_MASK)
37715 #define QuadSPI_MCR_DQS_EN_MASK                  0x40u
37716 #define QuadSPI_MCR_DQS_EN_SHIFT                 6
37717 #define QuadSPI_MCR_DDR_EN_MASK                  0x80u
37718 #define QuadSPI_MCR_DDR_EN_SHIFT                 7
37719 #define QuadSPI_MCR_CLR_RXF_MASK                 0x400u
37720 #define QuadSPI_MCR_CLR_RXF_SHIFT                10
37721 #define QuadSPI_MCR_CLR_TXF_MASK                 0x800u
37722 #define QuadSPI_MCR_CLR_TXF_SHIFT                11
37723 #define QuadSPI_MCR_MDIS_MASK                    0x4000u
37724 #define QuadSPI_MCR_MDIS_SHIFT                   14
37725 #define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK   0x1000000u
37726 #define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT  24
37727 #define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK         0x2000000u
37728 #define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT        25
37729 #define QuadSPI_MCR_DQS_PHASE_EN_MASK            0x4000000u
37730 #define QuadSPI_MCR_DQS_PHASE_EN_SHIFT           26
37731 /* IPCR Bit Fields */
37732 #define QuadSPI_IPCR_IDATSZ_MASK                 0xFFFFu
37733 #define QuadSPI_IPCR_IDATSZ_SHIFT                0
37734 #define QuadSPI_IPCR_IDATSZ(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_IDATSZ_SHIFT))&QuadSPI_IPCR_IDATSZ_MASK)
37735 #define QuadSPI_IPCR_PAR_EN_MASK                 0x10000u
37736 #define QuadSPI_IPCR_PAR_EN_SHIFT                16
37737 #define QuadSPI_IPCR_SEQID_MASK                  0xF000000u
37738 #define QuadSPI_IPCR_SEQID_SHIFT                 24
37739 #define QuadSPI_IPCR_SEQID(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK)
37740 /* FLSHCR Bit Fields */
37741 #define QuadSPI_FLSHCR_TCSS_MASK                 0xFu
37742 #define QuadSPI_FLSHCR_TCSS_SHIFT                0
37743 #define QuadSPI_FLSHCR_TCSS(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSS_SHIFT))&QuadSPI_FLSHCR_TCSS_MASK)
37744 #define QuadSPI_FLSHCR_TCSH_MASK                 0xF00u
37745 #define QuadSPI_FLSHCR_TCSH_SHIFT                8
37746 #define QuadSPI_FLSHCR_TCSH(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK)
37747 #define QuadSPI_FLSHCR_TDH_MASK                  0x30000u
37748 #define QuadSPI_FLSHCR_TDH_SHIFT                 16
37749 #define QuadSPI_FLSHCR_TDH(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TDH_SHIFT))&QuadSPI_FLSHCR_TDH_MASK)
37750 /* BUF0CR Bit Fields */
37751 #define QuadSPI_BUF0CR_MSTRID_MASK               0xFu
37752 #define QuadSPI_BUF0CR_MSTRID_SHIFT              0
37753 #define QuadSPI_BUF0CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_MSTRID_SHIFT))&QuadSPI_BUF0CR_MSTRID_MASK)
37754 #define QuadSPI_BUF0CR_ADATSZ_MASK               0xFF00u
37755 #define QuadSPI_BUF0CR_ADATSZ_SHIFT              8
37756 #define QuadSPI_BUF0CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_ADATSZ_SHIFT))&QuadSPI_BUF0CR_ADATSZ_MASK)
37757 #define QuadSPI_BUF0CR_HP_EN_MASK                0x80000000u
37758 #define QuadSPI_BUF0CR_HP_EN_SHIFT               31
37759 /* BUF1CR Bit Fields */
37760 #define QuadSPI_BUF1CR_MSTRID_MASK               0xFu
37761 #define QuadSPI_BUF1CR_MSTRID_SHIFT              0
37762 #define QuadSPI_BUF1CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_MSTRID_SHIFT))&QuadSPI_BUF1CR_MSTRID_MASK)
37763 #define QuadSPI_BUF1CR_ADATSZ_MASK               0xFF00u
37764 #define QuadSPI_BUF1CR_ADATSZ_SHIFT              8
37765 #define QuadSPI_BUF1CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_ADATSZ_SHIFT))&QuadSPI_BUF1CR_ADATSZ_MASK)
37766 /* BUF2CR Bit Fields */
37767 #define QuadSPI_BUF2CR_MSTRID_MASK               0xFu
37768 #define QuadSPI_BUF2CR_MSTRID_SHIFT              0
37769 #define QuadSPI_BUF2CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_MSTRID_SHIFT))&QuadSPI_BUF2CR_MSTRID_MASK)
37770 #define QuadSPI_BUF2CR_ADATSZ_MASK               0xFF00u
37771 #define QuadSPI_BUF2CR_ADATSZ_SHIFT              8
37772 #define QuadSPI_BUF2CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_ADATSZ_SHIFT))&QuadSPI_BUF2CR_ADATSZ_MASK)
37773 /* BUF3CR Bit Fields */
37774 #define QuadSPI_BUF3CR_MSTRID_MASK               0xFu
37775 #define QuadSPI_BUF3CR_MSTRID_SHIFT              0
37776 #define QuadSPI_BUF3CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_MSTRID_SHIFT))&QuadSPI_BUF3CR_MSTRID_MASK)
37777 #define QuadSPI_BUF3CR_ADATSZ_MASK               0xFF00u
37778 #define QuadSPI_BUF3CR_ADATSZ_SHIFT              8
37779 #define QuadSPI_BUF3CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ADATSZ_SHIFT))&QuadSPI_BUF3CR_ADATSZ_MASK)
37780 #define QuadSPI_BUF3CR_ALLMST_MASK               0x80000000u
37781 #define QuadSPI_BUF3CR_ALLMST_SHIFT              31
37782 /* BFGENCR Bit Fields */
37783 #define QuadSPI_BFGENCR_SEQID_MASK               0xF000u
37784 #define QuadSPI_BFGENCR_SEQID_SHIFT              12
37785 #define QuadSPI_BFGENCR_SEQID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BFGENCR_SEQID_SHIFT))&QuadSPI_BFGENCR_SEQID_MASK)
37786 #define QuadSPI_BFGENCR_PAR_EN_MASK              0x10000u
37787 #define QuadSPI_BFGENCR_PAR_EN_SHIFT             16
37788 /* BUF0IND Bit Fields */
37789 #define QuadSPI_BUF0IND_TPINDX0_MASK             0xFFFFFFF8u
37790 #define QuadSPI_BUF0IND_TPINDX0_SHIFT            3
37791 #define QuadSPI_BUF0IND_TPINDX0(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0IND_TPINDX0_SHIFT))&QuadSPI_BUF0IND_TPINDX0_MASK)
37792 /* BUF1IND Bit Fields */
37793 #define QuadSPI_BUF1IND_TPINDX1_MASK             0xFFFFFFF8u
37794 #define QuadSPI_BUF1IND_TPINDX1_SHIFT            3
37795 #define QuadSPI_BUF1IND_TPINDX1(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1IND_TPINDX1_SHIFT))&QuadSPI_BUF1IND_TPINDX1_MASK)
37796 /* BUF2IND Bit Fields */
37797 #define QuadSPI_BUF2IND_TPINDX2_MASK             0xFFFFFFF8u
37798 #define QuadSPI_BUF2IND_TPINDX2_SHIFT            3
37799 #define QuadSPI_BUF2IND_TPINDX2(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK)
37800 /* SFAR Bit Fields */
37801 #define QuadSPI_SFAR_SFADR_MASK                  0xFFFFFFFFu
37802 #define QuadSPI_SFAR_SFADR_SHIFT                 0
37803 #define QuadSPI_SFAR_SFADR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK)
37804 /* SMPR Bit Fields */
37805 #define QuadSPI_SMPR_SDRSMP_MASK                 0x60u
37806 #define QuadSPI_SMPR_SDRSMP_SHIFT                5
37807 #define QuadSPI_SMPR_SDRSMP(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_SDRSMP_SHIFT))&QuadSPI_SMPR_SDRSMP_MASK)
37808 #define QuadSPI_SMPR_DDRSMP_MASK                 0x70000u
37809 #define QuadSPI_SMPR_DDRSMP_SHIFT                16
37810 #define QuadSPI_SMPR_DDRSMP(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_DDRSMP_SHIFT))&QuadSPI_SMPR_DDRSMP_MASK)
37811 /* RBSR Bit Fields */
37812 #define QuadSPI_RBSR_RDBFL_MASK                  0x3F00u
37813 #define QuadSPI_RBSR_RDBFL_SHIFT                 8
37814 #define QuadSPI_RBSR_RDBFL(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDBFL_SHIFT))&QuadSPI_RBSR_RDBFL_MASK)
37815 #define QuadSPI_RBSR_RDCTR_MASK                  0xFFFF0000u
37816 #define QuadSPI_RBSR_RDCTR_SHIFT                 16
37817 #define QuadSPI_RBSR_RDCTR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDCTR_SHIFT))&QuadSPI_RBSR_RDCTR_MASK)
37818 /* RBCT Bit Fields */
37819 #define QuadSPI_RBCT_WMRK_MASK                   0x1Fu
37820 #define QuadSPI_RBCT_WMRK_SHIFT                  0
37821 #define QuadSPI_RBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_WMRK_SHIFT))&QuadSPI_RBCT_WMRK_MASK)
37822 #define QuadSPI_RBCT_RXBRD_MASK                  0x100u
37823 #define QuadSPI_RBCT_RXBRD_SHIFT                 8
37824 /* TBSR Bit Fields */
37825 #define QuadSPI_TBSR_TRBFL_MASK                  0x1F00u
37826 #define QuadSPI_TBSR_TRBFL_SHIFT                 8
37827 #define QuadSPI_TBSR_TRBFL(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK)
37828 #define QuadSPI_TBSR_TRCTR_MASK                  0xFFFF0000u
37829 #define QuadSPI_TBSR_TRCTR_SHIFT                 16
37830 #define QuadSPI_TBSR_TRCTR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRCTR_SHIFT))&QuadSPI_TBSR_TRCTR_MASK)
37831 /* TBDR Bit Fields */
37832 #define QuadSPI_TBDR_TXDATA_MASK                 0xFFFFFFFFu
37833 #define QuadSPI_TBDR_TXDATA_SHIFT                0
37834 #define QuadSPI_TBDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBDR_TXDATA_SHIFT))&QuadSPI_TBDR_TXDATA_MASK)
37835 /* SR Bit Fields */
37836 #define QuadSPI_SR_BUSY_MASK                     0x1u
37837 #define QuadSPI_SR_BUSY_SHIFT                    0
37838 #define QuadSPI_SR_IP_ACC_MASK                   0x2u
37839 #define QuadSPI_SR_IP_ACC_SHIFT                  1
37840 #define QuadSPI_SR_AHB_ACC_MASK                  0x4u
37841 #define QuadSPI_SR_AHB_ACC_SHIFT                 2
37842 #define QuadSPI_SR_RESERVED_MASK                 0x8u
37843 #define QuadSPI_SR_RESERVED_SHIFT                3
37844 #define QuadSPI_SR_AHBGNT_MASK                   0x20u
37845 #define QuadSPI_SR_AHBGNT_SHIFT                  5
37846 #define QuadSPI_SR_AHBTRN_MASK                   0x40u
37847 #define QuadSPI_SR_AHBTRN_SHIFT                  6
37848 #define QuadSPI_SR_AHB0NE_MASK                   0x80u
37849 #define QuadSPI_SR_AHB0NE_SHIFT                  7
37850 #define QuadSPI_SR_AHB1NE_MASK                   0x100u
37851 #define QuadSPI_SR_AHB1NE_SHIFT                  8
37852 #define QuadSPI_SR_AHB2NE_MASK                   0x200u
37853 #define QuadSPI_SR_AHB2NE_SHIFT                  9
37854 #define QuadSPI_SR_AHB3NE_MASK                   0x400u
37855 #define QuadSPI_SR_AHB3NE_SHIFT                  10
37856 #define QuadSPI_SR_AHB0FUL_MASK                  0x800u
37857 #define QuadSPI_SR_AHB0FUL_SHIFT                 11
37858 #define QuadSPI_SR_AHB1FUL_MASK                  0x1000u
37859 #define QuadSPI_SR_AHB1FUL_SHIFT                 12
37860 #define QuadSPI_SR_AHB2FUL_MASK                  0x2000u
37861 #define QuadSPI_SR_AHB2FUL_SHIFT                 13
37862 #define QuadSPI_SR_AHB3FUL_MASK                  0x4000u
37863 #define QuadSPI_SR_AHB3FUL_SHIFT                 14
37864 #define QuadSPI_SR_RXWE_MASK                     0x10000u
37865 #define QuadSPI_SR_RXWE_SHIFT                    16
37866 #define QuadSPI_SR_RXFULL_MASK                   0x80000u
37867 #define QuadSPI_SR_RXFULL_SHIFT                  19
37868 #define QuadSPI_SR_RXDMA_MASK                    0x800000u
37869 #define QuadSPI_SR_RXDMA_SHIFT                   23
37870 #define QuadSPI_SR_TXEDA_MASK                    0x1000000u
37871 #define QuadSPI_SR_TXEDA_SHIFT                   24
37872 #define QuadSPI_SR_TXFULL_MASK                   0x8000000u
37873 #define QuadSPI_SR_TXFULL_SHIFT                  27
37874 #define QuadSPI_SR_DLPSMP_MASK                   0xE0000000u
37875 #define QuadSPI_SR_DLPSMP_SHIFT                  29
37876 #define QuadSPI_SR_DLPSMP(x)                     (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK)
37877 /* FR Bit Fields */
37878 #define QuadSPI_FR_TFF_MASK                      0x1u
37879 #define QuadSPI_FR_TFF_SHIFT                     0
37880 #define QuadSPI_FR_IPGEF_MASK                    0x10u
37881 #define QuadSPI_FR_IPGEF_SHIFT                   4
37882 #define QuadSPI_FR_IPIEF_MASK                    0x40u
37883 #define QuadSPI_FR_IPIEF_SHIFT                   6
37884 #define QuadSPI_FR_IPAEF_MASK                    0x80u
37885 #define QuadSPI_FR_IPAEF_SHIFT                   7
37886 #define QuadSPI_FR_IUEF_MASK                     0x800u
37887 #define QuadSPI_FR_IUEF_SHIFT                    11
37888 #define QuadSPI_FR_ABOF_MASK                     0x1000u
37889 #define QuadSPI_FR_ABOF_SHIFT                    12
37890 #define QuadSPI_FR_ABSEF_MASK                    0x8000u
37891 #define QuadSPI_FR_ABSEF_SHIFT                   15
37892 #define QuadSPI_FR_RBDF_MASK                     0x10000u
37893 #define QuadSPI_FR_RBDF_SHIFT                    16
37894 #define QuadSPI_FR_RBOF_MASK                     0x20000u
37895 #define QuadSPI_FR_RBOF_SHIFT                    17
37896 #define QuadSPI_FR_ILLINE_MASK                   0x800000u
37897 #define QuadSPI_FR_ILLINE_SHIFT                  23
37898 #define QuadSPI_FR_TBUF_MASK                     0x4000000u
37899 #define QuadSPI_FR_TBUF_SHIFT                    26
37900 #define QuadSPI_FR_TBFF_MASK                     0x8000000u
37901 #define QuadSPI_FR_TBFF_SHIFT                    27
37902 #define QuadSPI_FR_DLPFF_MASK                    0x80000000u
37903 #define QuadSPI_FR_DLPFF_SHIFT                   31
37904 /* RSER Bit Fields */
37905 #define QuadSPI_RSER_TFIE_MASK                   0x1u
37906 #define QuadSPI_RSER_TFIE_SHIFT                  0
37907 #define QuadSPI_RSER_IPGEIE_MASK                 0x10u
37908 #define QuadSPI_RSER_IPGEIE_SHIFT                4
37909 #define QuadSPI_RSER_IPIEIE_MASK                 0x40u
37910 #define QuadSPI_RSER_IPIEIE_SHIFT                6
37911 #define QuadSPI_RSER_IPAEIE_MASK                 0x80u
37912 #define QuadSPI_RSER_IPAEIE_SHIFT                7
37913 #define QuadSPI_RSER_IUEIE_MASK                  0x800u
37914 #define QuadSPI_RSER_IUEIE_SHIFT                 11
37915 #define QuadSPI_RSER_ABOIE_MASK                  0x1000u
37916 #define QuadSPI_RSER_ABOIE_SHIFT                 12
37917 #define QuadSPI_RSER_ABSEIE_MASK                 0x8000u
37918 #define QuadSPI_RSER_ABSEIE_SHIFT                15
37919 #define QuadSPI_RSER_RBDIE_MASK                  0x10000u
37920 #define QuadSPI_RSER_RBDIE_SHIFT                 16
37921 #define QuadSPI_RSER_RBOIE_MASK                  0x20000u
37922 #define QuadSPI_RSER_RBOIE_SHIFT                 17
37923 #define QuadSPI_RSER_RBDDE_MASK                  0x200000u
37924 #define QuadSPI_RSER_RBDDE_SHIFT                 21
37925 #define QuadSPI_RSER_ILLINIE_MASK                0x800000u
37926 #define QuadSPI_RSER_ILLINIE_SHIFT               23
37927 #define QuadSPI_RSER_TBUIE_MASK                  0x4000000u
37928 #define QuadSPI_RSER_TBUIE_SHIFT                 26
37929 #define QuadSPI_RSER_TBFIE_MASK                  0x8000000u
37930 #define QuadSPI_RSER_TBFIE_SHIFT                 27
37931 #define QuadSPI_RSER_RESERVED_MASK               0x30000000u
37932 #define QuadSPI_RSER_RESERVED_SHIFT              28
37933 #define QuadSPI_RSER_RESERVED(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_RESERVED_SHIFT))&QuadSPI_RSER_RESERVED_MASK)
37934 #define QuadSPI_RSER_DLPFIE_MASK                 0x80000000u
37935 #define QuadSPI_RSER_DLPFIE_SHIFT                31
37936 /* SPNDST Bit Fields */
37937 #define QuadSPI_SPNDST_SUSPND_MASK               0x1u
37938 #define QuadSPI_SPNDST_SUSPND_SHIFT              0
37939 #define QuadSPI_SPNDST_SPDBUF_MASK               0xC0u
37940 #define QuadSPI_SPNDST_SPDBUF_SHIFT              6
37941 #define QuadSPI_SPNDST_SPDBUF(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SPDBUF_SHIFT))&QuadSPI_SPNDST_SPDBUF_MASK)
37942 #define QuadSPI_SPNDST_DATLFT_MASK               0xFE00u
37943 #define QuadSPI_SPNDST_DATLFT_SHIFT              9
37944 #define QuadSPI_SPNDST_DATLFT(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_DATLFT_SHIFT))&QuadSPI_SPNDST_DATLFT_MASK)
37945 /* SPTRCLR Bit Fields */
37946 #define QuadSPI_SPTRCLR_BFPTRC_MASK              0x1u
37947 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT             0
37948 #define QuadSPI_SPTRCLR_IPPTRC_MASK              0x100u
37949 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT             8
37950 /* SFA1AD Bit Fields */
37951 #define QuadSPI_SFA1AD_TPADA1_MASK               0xFFFFFC00u
37952 #define QuadSPI_SFA1AD_TPADA1_SHIFT              10
37953 #define QuadSPI_SFA1AD_TPADA1(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA1AD_TPADA1_SHIFT))&QuadSPI_SFA1AD_TPADA1_MASK)
37954 /* SFA2AD Bit Fields */
37955 #define QuadSPI_SFA2AD_TPADA2_MASK               0xFFFFFC00u
37956 #define QuadSPI_SFA2AD_TPADA2_SHIFT              10
37957 #define QuadSPI_SFA2AD_TPADA2(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA2AD_TPADA2_SHIFT))&QuadSPI_SFA2AD_TPADA2_MASK)
37958 /* SFB1AD Bit Fields */
37959 #define QuadSPI_SFB1AD_TPADB1_MASK               0xFFFFFC00u
37960 #define QuadSPI_SFB1AD_TPADB1_SHIFT              10
37961 #define QuadSPI_SFB1AD_TPADB1(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB1AD_TPADB1_SHIFT))&QuadSPI_SFB1AD_TPADB1_MASK)
37962 /* SFB2AD Bit Fields */
37963 #define QuadSPI_SFB2AD_TPADB2_MASK               0xFFFFFC00u
37964 #define QuadSPI_SFB2AD_TPADB2_SHIFT              10
37965 #define QuadSPI_SFB2AD_TPADB2(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB2AD_TPADB2_SHIFT))&QuadSPI_SFB2AD_TPADB2_MASK)
37966 /* RBDR Bit Fields */
37967 #define QuadSPI_RBDR_RXDATA_MASK                 0xFFFFFFFFu
37968 #define QuadSPI_RBDR_RXDATA_SHIFT                0
37969 #define QuadSPI_RBDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBDR_RXDATA_SHIFT))&QuadSPI_RBDR_RXDATA_MASK)
37970 /* LUTKEY Bit Fields */
37971 #define QuadSPI_LUTKEY_KEY_MASK                  0xFFFFFFFFu
37972 #define QuadSPI_LUTKEY_KEY_SHIFT                 0
37973 #define QuadSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUTKEY_KEY_SHIFT))&QuadSPI_LUTKEY_KEY_MASK)
37974 /* LCKCR Bit Fields */
37975 #define QuadSPI_LCKCR_LOCK_MASK                  0x1u
37976 #define QuadSPI_LCKCR_LOCK_SHIFT                 0
37977 #define QuadSPI_LCKCR_UNLOCK_MASK                0x2u
37978 #define QuadSPI_LCKCR_UNLOCK_SHIFT               1
37979 /* LUT Bit Fields */
37980 #define QuadSPI_LUT_OPRND0_MASK                  0xFFu
37981 #define QuadSPI_LUT_OPRND0_SHIFT                 0
37982 #define QuadSPI_LUT_OPRND0(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND0_SHIFT))&QuadSPI_LUT_OPRND0_MASK)
37983 #define QuadSPI_LUT_PAD0_MASK                    0x300u
37984 #define QuadSPI_LUT_PAD0_SHIFT                   8
37985 #define QuadSPI_LUT_PAD0(x)                      (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD0_SHIFT))&QuadSPI_LUT_PAD0_MASK)
37986 #define QuadSPI_LUT_INSTR0_MASK                  0xFC00u
37987 #define QuadSPI_LUT_INSTR0_SHIFT                 10
37988 #define QuadSPI_LUT_INSTR0(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR0_SHIFT))&QuadSPI_LUT_INSTR0_MASK)
37989 #define QuadSPI_LUT_OPRND1_MASK                  0xFF0000u
37990 #define QuadSPI_LUT_OPRND1_SHIFT                 16
37991 #define QuadSPI_LUT_OPRND1(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND1_SHIFT))&QuadSPI_LUT_OPRND1_MASK)
37992 #define QuadSPI_LUT_PAD1_MASK                    0x3000000u
37993 #define QuadSPI_LUT_PAD1_SHIFT                   24
37994 #define QuadSPI_LUT_PAD1(x)                      (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD1_SHIFT))&QuadSPI_LUT_PAD1_MASK)
37995 #define QuadSPI_LUT_INSTR1_MASK                  0xFC000000u
37996 #define QuadSPI_LUT_INSTR1_SHIFT                 26
37997 #define QuadSPI_LUT_INSTR1(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR1_SHIFT))&QuadSPI_LUT_INSTR1_MASK)
37998 
37999 /*!
38000  * @}
38001  */ /* end of group QuadSPI_Register_Masks */
38002 
38003 /* QuadSPI - Peripheral instance base addresses */
38004 /** Peripheral QuadSPI1 base address */
38005 #define QuadSPI1_BASE                            (0x30BB0000u)
38006 /** Peripheral QuadSPI1 base pointer */
38007 #define QuadSPI1                                 ((QuadSPI_Type *)QuadSPI1_BASE)
38008 #define QuadSPI1_BASE_PTR                        (QuadSPI1)
38009 /** Peripheral QuadSPI2 base address */
38010 #define QuadSPI2_BASE                            (0x30BB4000u)
38011 /** Peripheral QuadSPI2 base pointer */
38012 #define QuadSPI2                                 ((QuadSPI_Type *)QuadSPI2_BASE)
38013 #define QuadSPI2_BASE_PTR                        (QuadSPI2)
38014 /** Array initializer of QuadSPI peripheral base addresses */
38015 #define QuadSPI_BASE_ADDRS                       { QuadSPI1_BASE, QuadSPI2_BASE }
38016 /** Array initializer of QuadSPI peripheral base pointers */
38017 #define QuadSPI_BASE_PTRS                        { QuadSPI1, QuadSPI2 }
38018 /* ----------------------------------------------------------------------------
38019    -- QuadSPI - Register accessor macros
38020    ---------------------------------------------------------------------------- */
38021 
38022 /*!
38023  * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros
38024  * @{
38025  */
38026 
38027 
38028 /* QuadSPI - Register instance definitions */
38029 /* QuadSPI1 */
38030 #define QuadSPI1_MCR                             QuadSPI_MCR_REG(QuadSPI1_BASE_PTR)
38031 #define QuadSPI1_IPCR                            QuadSPI_IPCR_REG(QuadSPI1_BASE_PTR)
38032 #define QuadSPI1_FLSHCR                          QuadSPI_FLSHCR_REG(QuadSPI1_BASE_PTR)
38033 #define QuadSPI1_BUF0CR                          QuadSPI_BUF0CR_REG(QuadSPI1_BASE_PTR)
38034 #define QuadSPI1_BUF1CR                          QuadSPI_BUF1CR_REG(QuadSPI1_BASE_PTR)
38035 #define QuadSPI1_BUF2CR                          QuadSPI_BUF2CR_REG(QuadSPI1_BASE_PTR)
38036 #define QuadSPI1_BUF3CR                          QuadSPI_BUF3CR_REG(QuadSPI1_BASE_PTR)
38037 #define QuadSPI1_BFGENCR                         QuadSPI_BFGENCR_REG(QuadSPI1_BASE_PTR)
38038 #define QuadSPI1_BUF0IND                         QuadSPI_BUF0IND_REG(QuadSPI1_BASE_PTR)
38039 #define QuadSPI1_BUF1IND                         QuadSPI_BUF1IND_REG(QuadSPI1_BASE_PTR)
38040 #define QuadSPI1_BUF2IND                         QuadSPI_BUF2IND_REG(QuadSPI1_BASE_PTR)
38041 #define QuadSPI1_SFAR                            QuadSPI_SFAR_REG(QuadSPI1_BASE_PTR)
38042 #define QuadSPI1_SMPR                            QuadSPI_SMPR_REG(QuadSPI1_BASE_PTR)
38043 #define QuadSPI1_RBSR                            QuadSPI_RBSR_REG(QuadSPI1_BASE_PTR)
38044 #define QuadSPI1_RBCT                            QuadSPI_RBCT_REG(QuadSPI1_BASE_PTR)
38045 #define QuadSPI1_TBSR                            QuadSPI_TBSR_REG(QuadSPI1_BASE_PTR)
38046 #define QuadSPI1_TBDR                            QuadSPI_TBDR_REG(QuadSPI1_BASE_PTR)
38047 #define QuadSPI1_SR                              QuadSPI_SR_REG(QuadSPI1_BASE_PTR)
38048 #define QuadSPI1_FR                              QuadSPI_FR_REG(QuadSPI1_BASE_PTR)
38049 #define QuadSPI1_RSER                            QuadSPI_RSER_REG(QuadSPI1_BASE_PTR)
38050 #define QuadSPI1_SPNDST                          QuadSPI_SPNDST_REG(QuadSPI1_BASE_PTR)
38051 #define QuadSPI1_SPTRCLR                         QuadSPI_SPTRCLR_REG(QuadSPI1_BASE_PTR)
38052 #define QuadSPI1_SFA1AD                          QuadSPI_SFA1AD_REG(QuadSPI1_BASE_PTR)
38053 #define QuadSPI1_SFA2AD                          QuadSPI_SFA2AD_REG(QuadSPI1_BASE_PTR)
38054 #define QuadSPI1_SFB1AD                          QuadSPI_SFB1AD_REG(QuadSPI1_BASE_PTR)
38055 #define QuadSPI1_SFB2AD                          QuadSPI_SFB2AD_REG(QuadSPI1_BASE_PTR)
38056 #define QuadSPI1_RBDR0                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,0)
38057 #define QuadSPI1_RBDR1                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,1)
38058 #define QuadSPI1_RBDR2                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,2)
38059 #define QuadSPI1_RBDR3                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,3)
38060 #define QuadSPI1_RBDR4                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,4)
38061 #define QuadSPI1_RBDR5                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,5)
38062 #define QuadSPI1_RBDR6                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,6)
38063 #define QuadSPI1_RBDR7                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,7)
38064 #define QuadSPI1_RBDR8                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,8)
38065 #define QuadSPI1_RBDR9                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,9)
38066 #define QuadSPI1_RBDR10                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,10)
38067 #define QuadSPI1_RBDR11                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,11)
38068 #define QuadSPI1_RBDR12                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,12)
38069 #define QuadSPI1_RBDR13                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,13)
38070 #define QuadSPI1_RBDR14                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,14)
38071 #define QuadSPI1_RBDR15                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,15)
38072 #define QuadSPI1_RBDR16                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,16)
38073 #define QuadSPI1_RBDR17                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,17)
38074 #define QuadSPI1_RBDR18                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,18)
38075 #define QuadSPI1_RBDR19                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,19)
38076 #define QuadSPI1_RBDR20                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,20)
38077 #define QuadSPI1_RBDR21                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,21)
38078 #define QuadSPI1_RBDR22                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,22)
38079 #define QuadSPI1_RBDR23                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,23)
38080 #define QuadSPI1_RBDR24                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,24)
38081 #define QuadSPI1_RBDR25                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,25)
38082 #define QuadSPI1_RBDR26                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,26)
38083 #define QuadSPI1_RBDR27                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,27)
38084 #define QuadSPI1_RBDR28                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,28)
38085 #define QuadSPI1_RBDR29                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,29)
38086 #define QuadSPI1_RBDR30                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,30)
38087 #define QuadSPI1_RBDR31                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,31)
38088 #define QuadSPI1_LUTKEY                          QuadSPI_LUTKEY_REG(QuadSPI1_BASE_PTR)
38089 #define QuadSPI1_LCKCR                           QuadSPI_LCKCR_REG(QuadSPI1_BASE_PTR)
38090 #define QuadSPI1_LUT0                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,0)
38091 #define QuadSPI1_LUT1                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,1)
38092 #define QuadSPI1_LUT2                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,2)
38093 #define QuadSPI1_LUT3                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,3)
38094 #define QuadSPI1_LUT4                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,4)
38095 #define QuadSPI1_LUT5                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,5)
38096 #define QuadSPI1_LUT6                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,6)
38097 #define QuadSPI1_LUT7                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,7)
38098 #define QuadSPI1_LUT8                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,8)
38099 #define QuadSPI1_LUT9                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,9)
38100 #define QuadSPI1_LUT10                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,10)
38101 #define QuadSPI1_LUT11                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,11)
38102 #define QuadSPI1_LUT12                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,12)
38103 #define QuadSPI1_LUT13                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,13)
38104 #define QuadSPI1_LUT14                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,14)
38105 #define QuadSPI1_LUT15                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,15)
38106 #define QuadSPI1_LUT16                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,16)
38107 #define QuadSPI1_LUT17                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,17)
38108 #define QuadSPI1_LUT18                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,18)
38109 #define QuadSPI1_LUT19                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,19)
38110 #define QuadSPI1_LUT20                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,20)
38111 #define QuadSPI1_LUT21                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,21)
38112 #define QuadSPI1_LUT22                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,22)
38113 #define QuadSPI1_LUT23                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,23)
38114 #define QuadSPI1_LUT24                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,24)
38115 #define QuadSPI1_LUT25                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,25)
38116 #define QuadSPI1_LUT26                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,26)
38117 #define QuadSPI1_LUT27                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,27)
38118 #define QuadSPI1_LUT28                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,28)
38119 #define QuadSPI1_LUT29                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,29)
38120 #define QuadSPI1_LUT30                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,30)
38121 #define QuadSPI1_LUT31                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,31)
38122 #define QuadSPI1_LUT32                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,32)
38123 #define QuadSPI1_LUT33                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,33)
38124 #define QuadSPI1_LUT34                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,34)
38125 #define QuadSPI1_LUT35                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,35)
38126 #define QuadSPI1_LUT36                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,36)
38127 #define QuadSPI1_LUT37                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,37)
38128 #define QuadSPI1_LUT38                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,38)
38129 #define QuadSPI1_LUT39                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,39)
38130 #define QuadSPI1_LUT40                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,40)
38131 #define QuadSPI1_LUT41                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,41)
38132 #define QuadSPI1_LUT42                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,42)
38133 #define QuadSPI1_LUT43                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,43)
38134 #define QuadSPI1_LUT44                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,44)
38135 #define QuadSPI1_LUT45                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,45)
38136 #define QuadSPI1_LUT46                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,46)
38137 #define QuadSPI1_LUT47                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,47)
38138 #define QuadSPI1_LUT48                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,48)
38139 #define QuadSPI1_LUT49                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,49)
38140 #define QuadSPI1_LUT50                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,50)
38141 #define QuadSPI1_LUT51                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,51)
38142 #define QuadSPI1_LUT52                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,52)
38143 #define QuadSPI1_LUT53                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,53)
38144 #define QuadSPI1_LUT54                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,54)
38145 #define QuadSPI1_LUT55                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,55)
38146 #define QuadSPI1_LUT56                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,56)
38147 #define QuadSPI1_LUT57                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,57)
38148 #define QuadSPI1_LUT58                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,58)
38149 #define QuadSPI1_LUT59                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,59)
38150 #define QuadSPI1_LUT60                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,60)
38151 #define QuadSPI1_LUT61                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,61)
38152 #define QuadSPI1_LUT62                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,62)
38153 #define QuadSPI1_LUT63                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,63)
38154 /* QuadSPI2 */
38155 #define QuadSPI2_MCR                             QuadSPI_MCR_REG(QuadSPI2_BASE_PTR)
38156 #define QuadSPI2_IPCR                            QuadSPI_IPCR_REG(QuadSPI2_BASE_PTR)
38157 #define QuadSPI2_FLSHCR                          QuadSPI_FLSHCR_REG(QuadSPI2_BASE_PTR)
38158 #define QuadSPI2_BUF0CR                          QuadSPI_BUF0CR_REG(QuadSPI2_BASE_PTR)
38159 #define QuadSPI2_BUF1CR                          QuadSPI_BUF1CR_REG(QuadSPI2_BASE_PTR)
38160 #define QuadSPI2_BUF2CR                          QuadSPI_BUF2CR_REG(QuadSPI2_BASE_PTR)
38161 #define QuadSPI2_BUF3CR                          QuadSPI_BUF3CR_REG(QuadSPI2_BASE_PTR)
38162 #define QuadSPI2_BFGENCR                         QuadSPI_BFGENCR_REG(QuadSPI2_BASE_PTR)
38163 #define QuadSPI2_BUF0IND                         QuadSPI_BUF0IND_REG(QuadSPI2_BASE_PTR)
38164 #define QuadSPI2_BUF1IND                         QuadSPI_BUF1IND_REG(QuadSPI2_BASE_PTR)
38165 #define QuadSPI2_BUF2IND                         QuadSPI_BUF2IND_REG(QuadSPI2_BASE_PTR)
38166 #define QuadSPI2_SFAR                            QuadSPI_SFAR_REG(QuadSPI2_BASE_PTR)
38167 #define QuadSPI2_SMPR                            QuadSPI_SMPR_REG(QuadSPI2_BASE_PTR)
38168 #define QuadSPI2_RBSR                            QuadSPI_RBSR_REG(QuadSPI2_BASE_PTR)
38169 #define QuadSPI2_RBCT                            QuadSPI_RBCT_REG(QuadSPI2_BASE_PTR)
38170 #define QuadSPI2_TBSR                            QuadSPI_TBSR_REG(QuadSPI2_BASE_PTR)
38171 #define QuadSPI2_TBDR                            QuadSPI_TBDR_REG(QuadSPI2_BASE_PTR)
38172 #define QuadSPI2_SR                              QuadSPI_SR_REG(QuadSPI2_BASE_PTR)
38173 #define QuadSPI2_FR                              QuadSPI_FR_REG(QuadSPI2_BASE_PTR)
38174 #define QuadSPI2_RSER                            QuadSPI_RSER_REG(QuadSPI2_BASE_PTR)
38175 #define QuadSPI2_SPNDST                          QuadSPI_SPNDST_REG(QuadSPI2_BASE_PTR)
38176 #define QuadSPI2_SPTRCLR                         QuadSPI_SPTRCLR_REG(QuadSPI2_BASE_PTR)
38177 #define QuadSPI2_SFA1AD                          QuadSPI_SFA1AD_REG(QuadSPI2_BASE_PTR)
38178 #define QuadSPI2_SFA2AD                          QuadSPI_SFA2AD_REG(QuadSPI2_BASE_PTR)
38179 #define QuadSPI2_SFB1AD                          QuadSPI_SFB1AD_REG(QuadSPI2_BASE_PTR)
38180 #define QuadSPI2_SFB2AD                          QuadSPI_SFB2AD_REG(QuadSPI2_BASE_PTR)
38181 #define QuadSPI2_RBDR0                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,0)
38182 #define QuadSPI2_RBDR1                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,1)
38183 #define QuadSPI2_RBDR2                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,2)
38184 #define QuadSPI2_RBDR3                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,3)
38185 #define QuadSPI2_RBDR4                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,4)
38186 #define QuadSPI2_RBDR5                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,5)
38187 #define QuadSPI2_RBDR6                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,6)
38188 #define QuadSPI2_RBDR7                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,7)
38189 #define QuadSPI2_RBDR8                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,8)
38190 #define QuadSPI2_RBDR9                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,9)
38191 #define QuadSPI2_RBDR10                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,10)
38192 #define QuadSPI2_RBDR11                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,11)
38193 #define QuadSPI2_RBDR12                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,12)
38194 #define QuadSPI2_RBDR13                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,13)
38195 #define QuadSPI2_RBDR14                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,14)
38196 #define QuadSPI2_RBDR15                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,15)
38197 #define QuadSPI2_RBDR16                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,16)
38198 #define QuadSPI2_RBDR17                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,17)
38199 #define QuadSPI2_RBDR18                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,18)
38200 #define QuadSPI2_RBDR19                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,19)
38201 #define QuadSPI2_RBDR20                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,20)
38202 #define QuadSPI2_RBDR21                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,21)
38203 #define QuadSPI2_RBDR22                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,22)
38204 #define QuadSPI2_RBDR23                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,23)
38205 #define QuadSPI2_RBDR24                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,24)
38206 #define QuadSPI2_RBDR25                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,25)
38207 #define QuadSPI2_RBDR26                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,26)
38208 #define QuadSPI2_RBDR27                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,27)
38209 #define QuadSPI2_RBDR28                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,28)
38210 #define QuadSPI2_RBDR29                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,29)
38211 #define QuadSPI2_RBDR30                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,30)
38212 #define QuadSPI2_RBDR31                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,31)
38213 #define QuadSPI2_LUTKEY                          QuadSPI_LUTKEY_REG(QuadSPI2_BASE_PTR)
38214 #define QuadSPI2_LCKCR                           QuadSPI_LCKCR_REG(QuadSPI2_BASE_PTR)
38215 #define QuadSPI2_LUT0                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,0)
38216 #define QuadSPI2_LUT1                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,1)
38217 #define QuadSPI2_LUT2                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,2)
38218 #define QuadSPI2_LUT3                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,3)
38219 #define QuadSPI2_LUT4                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,4)
38220 #define QuadSPI2_LUT5                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,5)
38221 #define QuadSPI2_LUT6                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,6)
38222 #define QuadSPI2_LUT7                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,7)
38223 #define QuadSPI2_LUT8                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,8)
38224 #define QuadSPI2_LUT9                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,9)
38225 #define QuadSPI2_LUT10                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,10)
38226 #define QuadSPI2_LUT11                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,11)
38227 #define QuadSPI2_LUT12                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,12)
38228 #define QuadSPI2_LUT13                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,13)
38229 #define QuadSPI2_LUT14                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,14)
38230 #define QuadSPI2_LUT15                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,15)
38231 #define QuadSPI2_LUT16                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,16)
38232 #define QuadSPI2_LUT17                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,17)
38233 #define QuadSPI2_LUT18                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,18)
38234 #define QuadSPI2_LUT19                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,19)
38235 #define QuadSPI2_LUT20                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,20)
38236 #define QuadSPI2_LUT21                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,21)
38237 #define QuadSPI2_LUT22                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,22)
38238 #define QuadSPI2_LUT23                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,23)
38239 #define QuadSPI2_LUT24                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,24)
38240 #define QuadSPI2_LUT25                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,25)
38241 #define QuadSPI2_LUT26                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,26)
38242 #define QuadSPI2_LUT27                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,27)
38243 #define QuadSPI2_LUT28                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,28)
38244 #define QuadSPI2_LUT29                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,29)
38245 #define QuadSPI2_LUT30                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,30)
38246 #define QuadSPI2_LUT31                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,31)
38247 #define QuadSPI2_LUT32                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,32)
38248 #define QuadSPI2_LUT33                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,33)
38249 #define QuadSPI2_LUT34                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,34)
38250 #define QuadSPI2_LUT35                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,35)
38251 #define QuadSPI2_LUT36                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,36)
38252 #define QuadSPI2_LUT37                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,37)
38253 #define QuadSPI2_LUT38                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,38)
38254 #define QuadSPI2_LUT39                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,39)
38255 #define QuadSPI2_LUT40                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,40)
38256 #define QuadSPI2_LUT41                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,41)
38257 #define QuadSPI2_LUT42                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,42)
38258 #define QuadSPI2_LUT43                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,43)
38259 #define QuadSPI2_LUT44                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,44)
38260 #define QuadSPI2_LUT45                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,45)
38261 #define QuadSPI2_LUT46                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,46)
38262 #define QuadSPI2_LUT47                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,47)
38263 #define QuadSPI2_LUT48                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,48)
38264 #define QuadSPI2_LUT49                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,49)
38265 #define QuadSPI2_LUT50                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,50)
38266 #define QuadSPI2_LUT51                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,51)
38267 #define QuadSPI2_LUT52                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,52)
38268 #define QuadSPI2_LUT53                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,53)
38269 #define QuadSPI2_LUT54                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,54)
38270 #define QuadSPI2_LUT55                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,55)
38271 #define QuadSPI2_LUT56                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,56)
38272 #define QuadSPI2_LUT57                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,57)
38273 #define QuadSPI2_LUT58                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,58)
38274 #define QuadSPI2_LUT59                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,59)
38275 #define QuadSPI2_LUT60                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,60)
38276 #define QuadSPI2_LUT61                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,61)
38277 #define QuadSPI2_LUT62                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,62)
38278 #define QuadSPI2_LUT63                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,63)
38279 /* QuadSPI - Register array accessors */
38280 #define QuadSPI1_RBDR(index)                     QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,index)
38281 #define QuadSPI2_RBDR(index)                     QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,index)
38282 #define QuadSPI1_LUT(index)                      QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,index)
38283 #define QuadSPI2_LUT(index)                      QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,index)
38284 /*!
38285  * @}
38286  */ /* end of group QuadSPI_Register_Accessor_Macros */
38287 
38288 
38289 /*!
38290  * @}
38291  */ /* end of group QuadSPI_Peripheral */
38292 
38293 /* ----------------------------------------------------------------------------
38294    -- RDC Peripheral Access Layer
38295    ---------------------------------------------------------------------------- */
38296 
38297 /*!
38298  * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
38299  * @{
38300  */
38301 
38302 /** RDC - Register Layout Typedef */
38303 typedef struct {
38304   __I   uint32_t VIR;                                    /**< Version Information, offset: 0x0 */
38305   uint8_t RESERVED_0[32];
38306   __IO  uint32_t STAT;                                   /**< Status, offset: 0x24 */
38307   __IO  uint32_t INTCTRL;                                /**< Interrupt and Control, offset: 0x28 */
38308   __IO  uint32_t INTSTAT;                                /**< Interrupt Status, offset: 0x2C */
38309   uint8_t RESERVED_1[464];
38310   __IO  uint32_t MDA[27];                                /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
38311   uint8_t RESERVED_2[404];
38312   __IO  uint32_t PDAP[118];                              /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
38313   uint8_t RESERVED_3[552];
38314   struct {                                         /* offset: 0x800, array step: 0x10 */
38315   __IO    uint32_t MRSA;                                   /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
38316   __IO    uint32_t MREA;                                   /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
38317   __IO    uint32_t MRC;                                    /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
38318   __IO    uint32_t MRVS;                                   /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
38319  } MR[52];
38320 } RDC_Type, *RDC_MemMapPtr;
38321 /* ----------------------------------------------------------------------------
38322    -- RDC - Register accessor macros
38323    ---------------------------------------------------------------------------- */
38324 
38325 /*!
38326  * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros
38327  * @{
38328  */
38329 
38330 
38331 /* RDC - Register accessors */
38332 #define RDC_VIR_REG(base)                        ((base)->VIR)
38333 #define RDC_STAT_REG(base)                       ((base)->STAT)
38334 #define RDC_INTCTRL_REG(base)                    ((base)->INTCTRL)
38335 #define RDC_INTSTAT_REG(base)                    ((base)->INTSTAT)
38336 #define RDC_MDA_REG(base,index)                  ((base)->MDA[index])
38337 #define RDC_PDAP_REG(base,index)                 ((base)->PDAP[index])
38338 #define RDC_MRSA_REG(base,index)                 ((base)->MR[index].MRSA)
38339 #define RDC_MREA_REG(base,index)                 ((base)->MR[index].MREA)
38340 #define RDC_MRC_REG(base,index)                  ((base)->MR[index].MRC)
38341 #define RDC_MRVS_REG(base,index)                 ((base)->MR[index].MRVS)
38342 
38343 /*!
38344  * @}
38345  */ /* end of group RDC_Register_Accessor_Macros */
38346 /* ----------------------------------------------------------------------------
38347    -- RDC Register Masks
38348    ---------------------------------------------------------------------------- */
38349 
38350 /*!
38351  * @addtogroup RDC_Register_Masks RDC Register Masks
38352  * @{
38353  */
38354 
38355 /* VIR Bit Fields */
38356 #define RDC_VIR_NDID_MASK                        0xFu
38357 #define RDC_VIR_NDID_SHIFT                       0
38358 #define RDC_VIR_NDID(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NDID_SHIFT))&RDC_VIR_NDID_MASK)
38359 #define RDC_VIR_NMSTR_MASK                       0xFF0u
38360 #define RDC_VIR_NMSTR_SHIFT                      4
38361 #define RDC_VIR_NMSTR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NMSTR_SHIFT))&RDC_VIR_NMSTR_MASK)
38362 #define RDC_VIR_NPER_MASK                        0xFF000u
38363 #define RDC_VIR_NPER_SHIFT                       12
38364 #define RDC_VIR_NPER(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NPER_SHIFT))&RDC_VIR_NPER_MASK)
38365 #define RDC_VIR_NRGN_MASK                        0xFF00000u
38366 #define RDC_VIR_NRGN_SHIFT                       20
38367 #define RDC_VIR_NRGN(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NRGN_SHIFT))&RDC_VIR_NRGN_MASK)
38368 /* STAT Bit Fields */
38369 #define RDC_STAT_DID_MASK                        0xFu
38370 #define RDC_STAT_DID_SHIFT                       0
38371 #define RDC_STAT_DID(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_STAT_DID_SHIFT))&RDC_STAT_DID_MASK)
38372 #define RDC_STAT_PDS_MASK                        0x100u
38373 #define RDC_STAT_PDS_SHIFT                       8
38374 /* INTCTRL Bit Fields */
38375 #define RDC_INTCTRL_RCI_EN_MASK                  0x1u
38376 #define RDC_INTCTRL_RCI_EN_SHIFT                 0
38377 /* INTSTAT Bit Fields */
38378 #define RDC_INTSTAT_INT_MASK                     0x1u
38379 #define RDC_INTSTAT_INT_SHIFT                    0
38380 /* MDA Bit Fields */
38381 #define RDC_MDA_DID_MASK                         0x3u
38382 #define RDC_MDA_DID_SHIFT                        0
38383 #define RDC_MDA_DID(x)                           (((uint32_t)(((uint32_t)(x))<<RDC_MDA_DID_SHIFT))&RDC_MDA_DID_MASK)
38384 #define RDC_MDA_LCK_MASK                         0x80000000u
38385 #define RDC_MDA_LCK_SHIFT                        31
38386 /* PDAP Bit Fields */
38387 #define RDC_PDAP_D0W_MASK                        0x1u
38388 #define RDC_PDAP_D0W_SHIFT                       0
38389 #define RDC_PDAP_D0R_MASK                        0x2u
38390 #define RDC_PDAP_D0R_SHIFT                       1
38391 #define RDC_PDAP_D1W_MASK                        0x4u
38392 #define RDC_PDAP_D1W_SHIFT                       2
38393 #define RDC_PDAP_D1R_MASK                        0x8u
38394 #define RDC_PDAP_D1R_SHIFT                       3
38395 #define RDC_PDAP_D2W_MASK                        0x10u
38396 #define RDC_PDAP_D2W_SHIFT                       4
38397 #define RDC_PDAP_D2R_MASK                        0x20u
38398 #define RDC_PDAP_D2R_SHIFT                       5
38399 #define RDC_PDAP_D3W_MASK                        0x40u
38400 #define RDC_PDAP_D3W_SHIFT                       6
38401 #define RDC_PDAP_D3R_MASK                        0x80u
38402 #define RDC_PDAP_D3R_SHIFT                       7
38403 #define RDC_PDAP_SREQ_MASK                       0x40000000u
38404 #define RDC_PDAP_SREQ_SHIFT                      30
38405 #define RDC_PDAP_LCK_MASK                        0x80000000u
38406 #define RDC_PDAP_LCK_SHIFT                       31
38407 /* MRSA Bit Fields */
38408 #define RDC_MRSA_SADR_MASK                       0xFFFFFF80u
38409 #define RDC_MRSA_SADR_SHIFT                      7
38410 #define RDC_MRSA_SADR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MRSA_SADR_SHIFT))&RDC_MRSA_SADR_MASK)
38411 /* MREA Bit Fields */
38412 #define RDC_MREA_EADR_MASK                       0xFFFFFF80u
38413 #define RDC_MREA_EADR_SHIFT                      7
38414 #define RDC_MREA_EADR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MREA_EADR_SHIFT))&RDC_MREA_EADR_MASK)
38415 /* MRC Bit Fields */
38416 #define RDC_MRC_D0W_MASK                         0x1u
38417 #define RDC_MRC_D0W_SHIFT                        0
38418 #define RDC_MRC_D0R_MASK                         0x2u
38419 #define RDC_MRC_D0R_SHIFT                        1
38420 #define RDC_MRC_D1W_MASK                         0x4u
38421 #define RDC_MRC_D1W_SHIFT                        2
38422 #define RDC_MRC_D1R_MASK                         0x8u
38423 #define RDC_MRC_D1R_SHIFT                        3
38424 #define RDC_MRC_D2W_MASK                         0x10u
38425 #define RDC_MRC_D2W_SHIFT                        4
38426 #define RDC_MRC_D2R_MASK                         0x20u
38427 #define RDC_MRC_D2R_SHIFT                        5
38428 #define RDC_MRC_D3W_MASK                         0x40u
38429 #define RDC_MRC_D3W_SHIFT                        6
38430 #define RDC_MRC_D3R_MASK                         0x80u
38431 #define RDC_MRC_D3R_SHIFT                        7
38432 #define RDC_MRC_ENA_MASK                         0x40000000u
38433 #define RDC_MRC_ENA_SHIFT                        30
38434 #define RDC_MRC_LCK_MASK                         0x80000000u
38435 #define RDC_MRC_LCK_SHIFT                        31
38436 /* MRVS Bit Fields */
38437 #define RDC_MRVS_VDID_MASK                       0x3u
38438 #define RDC_MRVS_VDID_SHIFT                      0
38439 #define RDC_MRVS_VDID(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VDID_SHIFT))&RDC_MRVS_VDID_MASK)
38440 #define RDC_MRVS_AD_MASK                         0x10u
38441 #define RDC_MRVS_AD_SHIFT                        4
38442 #define RDC_MRVS_VADR_MASK                       0xFFFFFFE0u
38443 #define RDC_MRVS_VADR_SHIFT                      5
38444 #define RDC_MRVS_VADR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VADR_SHIFT))&RDC_MRVS_VADR_MASK)
38445 
38446 /*!
38447  * @}
38448  */ /* end of group RDC_Register_Masks */
38449 
38450 /* RDC - Peripheral instance base addresses */
38451 /** Peripheral RDC base address */
38452 #define RDC_BASE                                 (0x303D0000u)
38453 /** Peripheral RDC base pointer */
38454 #define RDC                                      ((RDC_Type *)RDC_BASE)
38455 #define RDC_BASE_PTR                             (RDC)
38456 /** Array initializer of RDC peripheral base addresses */
38457 #define RDC_BASE_ADDRS                           { RDC_BASE }
38458 /** Array initializer of RDC peripheral base pointers */
38459 #define RDC_BASE_PTRS                            { RDC }
38460 /** Interrupt vectors for the RDC peripheral type */
38461 #define RDC_IRQS                                 { RDC_IRQn }
38462 /* ----------------------------------------------------------------------------
38463    -- RDC - Register accessor macros
38464    ---------------------------------------------------------------------------- */
38465 
38466 /*!
38467  * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros
38468  * @{
38469  */
38470 
38471 
38472 /* RDC - Register instance definitions */
38473 /* RDC */
38474 #define RDC_VIR                                  RDC_VIR_REG(RDC_BASE_PTR)
38475 #define RDC_STAT                                 RDC_STAT_REG(RDC_BASE_PTR)
38476 #define RDC_INTCTRL                              RDC_INTCTRL_REG(RDC_BASE_PTR)
38477 #define RDC_INTSTAT                              RDC_INTSTAT_REG(RDC_BASE_PTR)
38478 #define RDC_MDA0                                 RDC_MDA_REG(RDC_BASE_PTR,0)
38479 #define RDC_MDA1                                 RDC_MDA_REG(RDC_BASE_PTR,1)
38480 #define RDC_MDA2                                 RDC_MDA_REG(RDC_BASE_PTR,2)
38481 #define RDC_MDA3                                 RDC_MDA_REG(RDC_BASE_PTR,3)
38482 #define RDC_MDA4                                 RDC_MDA_REG(RDC_BASE_PTR,4)
38483 #define RDC_MDA5                                 RDC_MDA_REG(RDC_BASE_PTR,5)
38484 #define RDC_MDA6                                 RDC_MDA_REG(RDC_BASE_PTR,6)
38485 #define RDC_MDA7                                 RDC_MDA_REG(RDC_BASE_PTR,7)
38486 #define RDC_MDA8                                 RDC_MDA_REG(RDC_BASE_PTR,8)
38487 #define RDC_MDA9                                 RDC_MDA_REG(RDC_BASE_PTR,9)
38488 #define RDC_MDA10                                RDC_MDA_REG(RDC_BASE_PTR,10)
38489 #define RDC_MDA11                                RDC_MDA_REG(RDC_BASE_PTR,11)
38490 #define RDC_MDA12                                RDC_MDA_REG(RDC_BASE_PTR,12)
38491 #define RDC_MDA13                                RDC_MDA_REG(RDC_BASE_PTR,13)
38492 #define RDC_MDA14                                RDC_MDA_REG(RDC_BASE_PTR,14)
38493 #define RDC_MDA15                                RDC_MDA_REG(RDC_BASE_PTR,15)
38494 #define RDC_MDA16                                RDC_MDA_REG(RDC_BASE_PTR,16)
38495 #define RDC_MDA17                                RDC_MDA_REG(RDC_BASE_PTR,17)
38496 #define RDC_MDA18                                RDC_MDA_REG(RDC_BASE_PTR,18)
38497 #define RDC_MDA19                                RDC_MDA_REG(RDC_BASE_PTR,19)
38498 #define RDC_MDA20                                RDC_MDA_REG(RDC_BASE_PTR,20)
38499 #define RDC_MDA21                                RDC_MDA_REG(RDC_BASE_PTR,21)
38500 #define RDC_MDA22                                RDC_MDA_REG(RDC_BASE_PTR,22)
38501 #define RDC_MDA23                                RDC_MDA_REG(RDC_BASE_PTR,23)
38502 #define RDC_MDA24                                RDC_MDA_REG(RDC_BASE_PTR,24)
38503 #define RDC_MDA25                                RDC_MDA_REG(RDC_BASE_PTR,25)
38504 #define RDC_MDA26                                RDC_MDA_REG(RDC_BASE_PTR,26)
38505 #define RDC_PDAP0                                RDC_PDAP_REG(RDC_BASE_PTR,0)
38506 #define RDC_PDAP1                                RDC_PDAP_REG(RDC_BASE_PTR,1)
38507 #define RDC_PDAP2                                RDC_PDAP_REG(RDC_BASE_PTR,2)
38508 #define RDC_PDAP3                                RDC_PDAP_REG(RDC_BASE_PTR,3)
38509 #define RDC_PDAP4                                RDC_PDAP_REG(RDC_BASE_PTR,4)
38510 #define RDC_PDAP5                                RDC_PDAP_REG(RDC_BASE_PTR,5)
38511 #define RDC_PDAP6                                RDC_PDAP_REG(RDC_BASE_PTR,6)
38512 #define RDC_PDAP7                                RDC_PDAP_REG(RDC_BASE_PTR,7)
38513 #define RDC_PDAP8                                RDC_PDAP_REG(RDC_BASE_PTR,8)
38514 #define RDC_PDAP9                                RDC_PDAP_REG(RDC_BASE_PTR,9)
38515 #define RDC_PDAP10                               RDC_PDAP_REG(RDC_BASE_PTR,10)
38516 #define RDC_PDAP11                               RDC_PDAP_REG(RDC_BASE_PTR,11)
38517 #define RDC_PDAP12                               RDC_PDAP_REG(RDC_BASE_PTR,12)
38518 #define RDC_PDAP13                               RDC_PDAP_REG(RDC_BASE_PTR,13)
38519 #define RDC_PDAP14                               RDC_PDAP_REG(RDC_BASE_PTR,14)
38520 #define RDC_PDAP15                               RDC_PDAP_REG(RDC_BASE_PTR,15)
38521 #define RDC_PDAP16                               RDC_PDAP_REG(RDC_BASE_PTR,16)
38522 #define RDC_PDAP17                               RDC_PDAP_REG(RDC_BASE_PTR,17)
38523 #define RDC_PDAP18                               RDC_PDAP_REG(RDC_BASE_PTR,18)
38524 #define RDC_PDAP19                               RDC_PDAP_REG(RDC_BASE_PTR,19)
38525 #define RDC_PDAP20                               RDC_PDAP_REG(RDC_BASE_PTR,20)
38526 #define RDC_PDAP21                               RDC_PDAP_REG(RDC_BASE_PTR,21)
38527 #define RDC_PDAP22                               RDC_PDAP_REG(RDC_BASE_PTR,22)
38528 #define RDC_PDAP23                               RDC_PDAP_REG(RDC_BASE_PTR,23)
38529 #define RDC_PDAP24                               RDC_PDAP_REG(RDC_BASE_PTR,24)
38530 #define RDC_PDAP25                               RDC_PDAP_REG(RDC_BASE_PTR,25)
38531 #define RDC_PDAP26                               RDC_PDAP_REG(RDC_BASE_PTR,26)
38532 #define RDC_PDAP27                               RDC_PDAP_REG(RDC_BASE_PTR,27)
38533 #define RDC_PDAP28                               RDC_PDAP_REG(RDC_BASE_PTR,28)
38534 #define RDC_PDAP29                               RDC_PDAP_REG(RDC_BASE_PTR,29)
38535 #define RDC_PDAP30                               RDC_PDAP_REG(RDC_BASE_PTR,30)
38536 #define RDC_PDAP31                               RDC_PDAP_REG(RDC_BASE_PTR,31)
38537 #define RDC_PDAP32                               RDC_PDAP_REG(RDC_BASE_PTR,32)
38538 #define RDC_PDAP33                               RDC_PDAP_REG(RDC_BASE_PTR,33)
38539 #define RDC_PDAP34                               RDC_PDAP_REG(RDC_BASE_PTR,34)
38540 #define RDC_PDAP35                               RDC_PDAP_REG(RDC_BASE_PTR,35)
38541 #define RDC_PDAP36                               RDC_PDAP_REG(RDC_BASE_PTR,36)
38542 #define RDC_PDAP37                               RDC_PDAP_REG(RDC_BASE_PTR,37)
38543 #define RDC_PDAP38                               RDC_PDAP_REG(RDC_BASE_PTR,38)
38544 #define RDC_PDAP39                               RDC_PDAP_REG(RDC_BASE_PTR,39)
38545 #define RDC_PDAP40                               RDC_PDAP_REG(RDC_BASE_PTR,40)
38546 #define RDC_PDAP41                               RDC_PDAP_REG(RDC_BASE_PTR,41)
38547 #define RDC_PDAP42                               RDC_PDAP_REG(RDC_BASE_PTR,42)
38548 #define RDC_PDAP43                               RDC_PDAP_REG(RDC_BASE_PTR,43)
38549 #define RDC_PDAP44                               RDC_PDAP_REG(RDC_BASE_PTR,44)
38550 #define RDC_PDAP45                               RDC_PDAP_REG(RDC_BASE_PTR,45)
38551 #define RDC_PDAP46                               RDC_PDAP_REG(RDC_BASE_PTR,46)
38552 #define RDC_PDAP47                               RDC_PDAP_REG(RDC_BASE_PTR,47)
38553 #define RDC_PDAP48                               RDC_PDAP_REG(RDC_BASE_PTR,48)
38554 #define RDC_PDAP49                               RDC_PDAP_REG(RDC_BASE_PTR,49)
38555 #define RDC_PDAP50                               RDC_PDAP_REG(RDC_BASE_PTR,50)
38556 #define RDC_PDAP51                               RDC_PDAP_REG(RDC_BASE_PTR,51)
38557 #define RDC_PDAP52                               RDC_PDAP_REG(RDC_BASE_PTR,52)
38558 #define RDC_PDAP53                               RDC_PDAP_REG(RDC_BASE_PTR,53)
38559 #define RDC_PDAP54                               RDC_PDAP_REG(RDC_BASE_PTR,54)
38560 #define RDC_PDAP55                               RDC_PDAP_REG(RDC_BASE_PTR,55)
38561 #define RDC_PDAP56                               RDC_PDAP_REG(RDC_BASE_PTR,56)
38562 #define RDC_PDAP57                               RDC_PDAP_REG(RDC_BASE_PTR,57)
38563 #define RDC_PDAP58                               RDC_PDAP_REG(RDC_BASE_PTR,58)
38564 #define RDC_PDAP59                               RDC_PDAP_REG(RDC_BASE_PTR,59)
38565 #define RDC_PDAP60                               RDC_PDAP_REG(RDC_BASE_PTR,60)
38566 #define RDC_PDAP61                               RDC_PDAP_REG(RDC_BASE_PTR,61)
38567 #define RDC_PDAP62                               RDC_PDAP_REG(RDC_BASE_PTR,62)
38568 #define RDC_PDAP63                               RDC_PDAP_REG(RDC_BASE_PTR,63)
38569 #define RDC_PDAP64                               RDC_PDAP_REG(RDC_BASE_PTR,64)
38570 #define RDC_PDAP65                               RDC_PDAP_REG(RDC_BASE_PTR,65)
38571 #define RDC_PDAP66                               RDC_PDAP_REG(RDC_BASE_PTR,66)
38572 #define RDC_PDAP67                               RDC_PDAP_REG(RDC_BASE_PTR,67)
38573 #define RDC_PDAP68                               RDC_PDAP_REG(RDC_BASE_PTR,68)
38574 #define RDC_PDAP69                               RDC_PDAP_REG(RDC_BASE_PTR,69)
38575 #define RDC_PDAP70                               RDC_PDAP_REG(RDC_BASE_PTR,70)
38576 #define RDC_PDAP71                               RDC_PDAP_REG(RDC_BASE_PTR,71)
38577 #define RDC_PDAP72                               RDC_PDAP_REG(RDC_BASE_PTR,72)
38578 #define RDC_PDAP73                               RDC_PDAP_REG(RDC_BASE_PTR,73)
38579 #define RDC_PDAP74                               RDC_PDAP_REG(RDC_BASE_PTR,74)
38580 #define RDC_PDAP75                               RDC_PDAP_REG(RDC_BASE_PTR,75)
38581 #define RDC_PDAP76                               RDC_PDAP_REG(RDC_BASE_PTR,76)
38582 #define RDC_PDAP77                               RDC_PDAP_REG(RDC_BASE_PTR,77)
38583 #define RDC_PDAP78                               RDC_PDAP_REG(RDC_BASE_PTR,78)
38584 #define RDC_PDAP79                               RDC_PDAP_REG(RDC_BASE_PTR,79)
38585 #define RDC_PDAP80                               RDC_PDAP_REG(RDC_BASE_PTR,80)
38586 #define RDC_PDAP81                               RDC_PDAP_REG(RDC_BASE_PTR,81)
38587 #define RDC_PDAP82                               RDC_PDAP_REG(RDC_BASE_PTR,82)
38588 #define RDC_PDAP83                               RDC_PDAP_REG(RDC_BASE_PTR,83)
38589 #define RDC_PDAP84                               RDC_PDAP_REG(RDC_BASE_PTR,84)
38590 #define RDC_PDAP85                               RDC_PDAP_REG(RDC_BASE_PTR,85)
38591 #define RDC_PDAP86                               RDC_PDAP_REG(RDC_BASE_PTR,86)
38592 #define RDC_PDAP87                               RDC_PDAP_REG(RDC_BASE_PTR,87)
38593 #define RDC_PDAP88                               RDC_PDAP_REG(RDC_BASE_PTR,88)
38594 #define RDC_PDAP89                               RDC_PDAP_REG(RDC_BASE_PTR,89)
38595 #define RDC_PDAP90                               RDC_PDAP_REG(RDC_BASE_PTR,90)
38596 #define RDC_PDAP91                               RDC_PDAP_REG(RDC_BASE_PTR,91)
38597 #define RDC_PDAP92                               RDC_PDAP_REG(RDC_BASE_PTR,92)
38598 #define RDC_PDAP93                               RDC_PDAP_REG(RDC_BASE_PTR,93)
38599 #define RDC_PDAP94                               RDC_PDAP_REG(RDC_BASE_PTR,94)
38600 #define RDC_PDAP95                               RDC_PDAP_REG(RDC_BASE_PTR,95)
38601 #define RDC_PDAP96                               RDC_PDAP_REG(RDC_BASE_PTR,96)
38602 #define RDC_PDAP97                               RDC_PDAP_REG(RDC_BASE_PTR,97)
38603 #define RDC_PDAP98                               RDC_PDAP_REG(RDC_BASE_PTR,98)
38604 #define RDC_PDAP99                               RDC_PDAP_REG(RDC_BASE_PTR,99)
38605 #define RDC_PDAP100                              RDC_PDAP_REG(RDC_BASE_PTR,100)
38606 #define RDC_PDAP101                              RDC_PDAP_REG(RDC_BASE_PTR,101)
38607 #define RDC_PDAP102                              RDC_PDAP_REG(RDC_BASE_PTR,102)
38608 #define RDC_PDAP103                              RDC_PDAP_REG(RDC_BASE_PTR,103)
38609 #define RDC_PDAP104                              RDC_PDAP_REG(RDC_BASE_PTR,104)
38610 #define RDC_PDAP105                              RDC_PDAP_REG(RDC_BASE_PTR,105)
38611 #define RDC_PDAP106                              RDC_PDAP_REG(RDC_BASE_PTR,106)
38612 #define RDC_PDAP107                              RDC_PDAP_REG(RDC_BASE_PTR,107)
38613 #define RDC_PDAP108                              RDC_PDAP_REG(RDC_BASE_PTR,108)
38614 #define RDC_PDAP109                              RDC_PDAP_REG(RDC_BASE_PTR,109)
38615 #define RDC_PDAP110                              RDC_PDAP_REG(RDC_BASE_PTR,110)
38616 #define RDC_PDAP111                              RDC_PDAP_REG(RDC_BASE_PTR,111)
38617 #define RDC_PDAP112                              RDC_PDAP_REG(RDC_BASE_PTR,112)
38618 #define RDC_PDAP113                              RDC_PDAP_REG(RDC_BASE_PTR,113)
38619 #define RDC_PDAP114                              RDC_PDAP_REG(RDC_BASE_PTR,114)
38620 #define RDC_PDAP115                              RDC_PDAP_REG(RDC_BASE_PTR,115)
38621 #define RDC_PDAP116                              RDC_PDAP_REG(RDC_BASE_PTR,116)
38622 #define RDC_PDAP117                              RDC_PDAP_REG(RDC_BASE_PTR,117)
38623 #define RDC_MRSA0                                RDC_MRSA_REG(RDC_BASE_PTR,0)
38624 #define RDC_MREA0                                RDC_MREA_REG(RDC_BASE_PTR,0)
38625 #define RDC_MRC0                                 RDC_MRC_REG(RDC_BASE_PTR,0)
38626 #define RDC_MRVS0                                RDC_MRVS_REG(RDC_BASE_PTR,0)
38627 #define RDC_MRSA1                                RDC_MRSA_REG(RDC_BASE_PTR,1)
38628 #define RDC_MREA1                                RDC_MREA_REG(RDC_BASE_PTR,1)
38629 #define RDC_MRC1                                 RDC_MRC_REG(RDC_BASE_PTR,1)
38630 #define RDC_MRVS1                                RDC_MRVS_REG(RDC_BASE_PTR,1)
38631 #define RDC_MRSA2                                RDC_MRSA_REG(RDC_BASE_PTR,2)
38632 #define RDC_MREA2                                RDC_MREA_REG(RDC_BASE_PTR,2)
38633 #define RDC_MRC2                                 RDC_MRC_REG(RDC_BASE_PTR,2)
38634 #define RDC_MRVS2                                RDC_MRVS_REG(RDC_BASE_PTR,2)
38635 #define RDC_MRSA3                                RDC_MRSA_REG(RDC_BASE_PTR,3)
38636 #define RDC_MREA3                                RDC_MREA_REG(RDC_BASE_PTR,3)
38637 #define RDC_MRC3                                 RDC_MRC_REG(RDC_BASE_PTR,3)
38638 #define RDC_MRVS3                                RDC_MRVS_REG(RDC_BASE_PTR,3)
38639 #define RDC_MRSA4                                RDC_MRSA_REG(RDC_BASE_PTR,4)
38640 #define RDC_MREA4                                RDC_MREA_REG(RDC_BASE_PTR,4)
38641 #define RDC_MRC4                                 RDC_MRC_REG(RDC_BASE_PTR,4)
38642 #define RDC_MRVS4                                RDC_MRVS_REG(RDC_BASE_PTR,4)
38643 #define RDC_MRSA5                                RDC_MRSA_REG(RDC_BASE_PTR,5)
38644 #define RDC_MREA5                                RDC_MREA_REG(RDC_BASE_PTR,5)
38645 #define RDC_MRC5                                 RDC_MRC_REG(RDC_BASE_PTR,5)
38646 #define RDC_MRVS5                                RDC_MRVS_REG(RDC_BASE_PTR,5)
38647 #define RDC_MRSA6                                RDC_MRSA_REG(RDC_BASE_PTR,6)
38648 #define RDC_MREA6                                RDC_MREA_REG(RDC_BASE_PTR,6)
38649 #define RDC_MRC6                                 RDC_MRC_REG(RDC_BASE_PTR,6)
38650 #define RDC_MRVS6                                RDC_MRVS_REG(RDC_BASE_PTR,6)
38651 #define RDC_MRSA7                                RDC_MRSA_REG(RDC_BASE_PTR,7)
38652 #define RDC_MREA7                                RDC_MREA_REG(RDC_BASE_PTR,7)
38653 #define RDC_MRC7                                 RDC_MRC_REG(RDC_BASE_PTR,7)
38654 #define RDC_MRVS7                                RDC_MRVS_REG(RDC_BASE_PTR,7)
38655 #define RDC_MRSA8                                RDC_MRSA_REG(RDC_BASE_PTR,8)
38656 #define RDC_MREA8                                RDC_MREA_REG(RDC_BASE_PTR,8)
38657 #define RDC_MRC8                                 RDC_MRC_REG(RDC_BASE_PTR,8)
38658 #define RDC_MRVS8                                RDC_MRVS_REG(RDC_BASE_PTR,8)
38659 #define RDC_MRSA9                                RDC_MRSA_REG(RDC_BASE_PTR,9)
38660 #define RDC_MREA9                                RDC_MREA_REG(RDC_BASE_PTR,9)
38661 #define RDC_MRC9                                 RDC_MRC_REG(RDC_BASE_PTR,9)
38662 #define RDC_MRVS9                                RDC_MRVS_REG(RDC_BASE_PTR,9)
38663 #define RDC_MRSA10                               RDC_MRSA_REG(RDC_BASE_PTR,10)
38664 #define RDC_MREA10                               RDC_MREA_REG(RDC_BASE_PTR,10)
38665 #define RDC_MRC10                                RDC_MRC_REG(RDC_BASE_PTR,10)
38666 #define RDC_MRVS10                               RDC_MRVS_REG(RDC_BASE_PTR,10)
38667 #define RDC_MRSA11                               RDC_MRSA_REG(RDC_BASE_PTR,11)
38668 #define RDC_MREA11                               RDC_MREA_REG(RDC_BASE_PTR,11)
38669 #define RDC_MRC11                                RDC_MRC_REG(RDC_BASE_PTR,11)
38670 #define RDC_MRVS11                               RDC_MRVS_REG(RDC_BASE_PTR,11)
38671 #define RDC_MRSA12                               RDC_MRSA_REG(RDC_BASE_PTR,12)
38672 #define RDC_MREA12                               RDC_MREA_REG(RDC_BASE_PTR,12)
38673 #define RDC_MRC12                                RDC_MRC_REG(RDC_BASE_PTR,12)
38674 #define RDC_MRVS12                               RDC_MRVS_REG(RDC_BASE_PTR,12)
38675 #define RDC_MRSA13                               RDC_MRSA_REG(RDC_BASE_PTR,13)
38676 #define RDC_MREA13                               RDC_MREA_REG(RDC_BASE_PTR,13)
38677 #define RDC_MRC13                                RDC_MRC_REG(RDC_BASE_PTR,13)
38678 #define RDC_MRVS13                               RDC_MRVS_REG(RDC_BASE_PTR,13)
38679 #define RDC_MRSA14                               RDC_MRSA_REG(RDC_BASE_PTR,14)
38680 #define RDC_MREA14                               RDC_MREA_REG(RDC_BASE_PTR,14)
38681 #define RDC_MRC14                                RDC_MRC_REG(RDC_BASE_PTR,14)
38682 #define RDC_MRVS14                               RDC_MRVS_REG(RDC_BASE_PTR,14)
38683 #define RDC_MRSA15                               RDC_MRSA_REG(RDC_BASE_PTR,15)
38684 #define RDC_MREA15                               RDC_MREA_REG(RDC_BASE_PTR,15)
38685 #define RDC_MRC15                                RDC_MRC_REG(RDC_BASE_PTR,15)
38686 #define RDC_MRVS15                               RDC_MRVS_REG(RDC_BASE_PTR,15)
38687 #define RDC_MRSA16                               RDC_MRSA_REG(RDC_BASE_PTR,16)
38688 #define RDC_MREA16                               RDC_MREA_REG(RDC_BASE_PTR,16)
38689 #define RDC_MRC16                                RDC_MRC_REG(RDC_BASE_PTR,16)
38690 #define RDC_MRVS16                               RDC_MRVS_REG(RDC_BASE_PTR,16)
38691 #define RDC_MRSA17                               RDC_MRSA_REG(RDC_BASE_PTR,17)
38692 #define RDC_MREA17                               RDC_MREA_REG(RDC_BASE_PTR,17)
38693 #define RDC_MRC17                                RDC_MRC_REG(RDC_BASE_PTR,17)
38694 #define RDC_MRVS17                               RDC_MRVS_REG(RDC_BASE_PTR,17)
38695 #define RDC_MRSA18                               RDC_MRSA_REG(RDC_BASE_PTR,18)
38696 #define RDC_MREA18                               RDC_MREA_REG(RDC_BASE_PTR,18)
38697 #define RDC_MRC18                                RDC_MRC_REG(RDC_BASE_PTR,18)
38698 #define RDC_MRVS18                               RDC_MRVS_REG(RDC_BASE_PTR,18)
38699 #define RDC_MRSA19                               RDC_MRSA_REG(RDC_BASE_PTR,19)
38700 #define RDC_MREA19                               RDC_MREA_REG(RDC_BASE_PTR,19)
38701 #define RDC_MRC19                                RDC_MRC_REG(RDC_BASE_PTR,19)
38702 #define RDC_MRVS19                               RDC_MRVS_REG(RDC_BASE_PTR,19)
38703 #define RDC_MRSA20                               RDC_MRSA_REG(RDC_BASE_PTR,20)
38704 #define RDC_MREA20                               RDC_MREA_REG(RDC_BASE_PTR,20)
38705 #define RDC_MRC20                                RDC_MRC_REG(RDC_BASE_PTR,20)
38706 #define RDC_MRVS20                               RDC_MRVS_REG(RDC_BASE_PTR,20)
38707 #define RDC_MRSA21                               RDC_MRSA_REG(RDC_BASE_PTR,21)
38708 #define RDC_MREA21                               RDC_MREA_REG(RDC_BASE_PTR,21)
38709 #define RDC_MRC21                                RDC_MRC_REG(RDC_BASE_PTR,21)
38710 #define RDC_MRVS21                               RDC_MRVS_REG(RDC_BASE_PTR,21)
38711 #define RDC_MRSA22                               RDC_MRSA_REG(RDC_BASE_PTR,22)
38712 #define RDC_MREA22                               RDC_MREA_REG(RDC_BASE_PTR,22)
38713 #define RDC_MRC22                                RDC_MRC_REG(RDC_BASE_PTR,22)
38714 #define RDC_MRVS22                               RDC_MRVS_REG(RDC_BASE_PTR,22)
38715 #define RDC_MRSA23                               RDC_MRSA_REG(RDC_BASE_PTR,23)
38716 #define RDC_MREA23                               RDC_MREA_REG(RDC_BASE_PTR,23)
38717 #define RDC_MRC23                                RDC_MRC_REG(RDC_BASE_PTR,23)
38718 #define RDC_MRVS23                               RDC_MRVS_REG(RDC_BASE_PTR,23)
38719 #define RDC_MRSA24                               RDC_MRSA_REG(RDC_BASE_PTR,24)
38720 #define RDC_MREA24                               RDC_MREA_REG(RDC_BASE_PTR,24)
38721 #define RDC_MRC24                                RDC_MRC_REG(RDC_BASE_PTR,24)
38722 #define RDC_MRVS24                               RDC_MRVS_REG(RDC_BASE_PTR,24)
38723 #define RDC_MRSA25                               RDC_MRSA_REG(RDC_BASE_PTR,25)
38724 #define RDC_MREA25                               RDC_MREA_REG(RDC_BASE_PTR,25)
38725 #define RDC_MRC25                                RDC_MRC_REG(RDC_BASE_PTR,25)
38726 #define RDC_MRVS25                               RDC_MRVS_REG(RDC_BASE_PTR,25)
38727 #define RDC_MRSA26                               RDC_MRSA_REG(RDC_BASE_PTR,26)
38728 #define RDC_MREA26                               RDC_MREA_REG(RDC_BASE_PTR,26)
38729 #define RDC_MRC26                                RDC_MRC_REG(RDC_BASE_PTR,26)
38730 #define RDC_MRVS26                               RDC_MRVS_REG(RDC_BASE_PTR,26)
38731 #define RDC_MRSA27                               RDC_MRSA_REG(RDC_BASE_PTR,27)
38732 #define RDC_MREA27                               RDC_MREA_REG(RDC_BASE_PTR,27)
38733 #define RDC_MRC27                                RDC_MRC_REG(RDC_BASE_PTR,27)
38734 #define RDC_MRVS27                               RDC_MRVS_REG(RDC_BASE_PTR,27)
38735 #define RDC_MRSA28                               RDC_MRSA_REG(RDC_BASE_PTR,28)
38736 #define RDC_MREA28                               RDC_MREA_REG(RDC_BASE_PTR,28)
38737 #define RDC_MRC28                                RDC_MRC_REG(RDC_BASE_PTR,28)
38738 #define RDC_MRVS28                               RDC_MRVS_REG(RDC_BASE_PTR,28)
38739 #define RDC_MRSA29                               RDC_MRSA_REG(RDC_BASE_PTR,29)
38740 #define RDC_MREA29                               RDC_MREA_REG(RDC_BASE_PTR,29)
38741 #define RDC_MRC29                                RDC_MRC_REG(RDC_BASE_PTR,29)
38742 #define RDC_MRVS29                               RDC_MRVS_REG(RDC_BASE_PTR,29)
38743 #define RDC_MRSA30                               RDC_MRSA_REG(RDC_BASE_PTR,30)
38744 #define RDC_MREA30                               RDC_MREA_REG(RDC_BASE_PTR,30)
38745 #define RDC_MRC30                                RDC_MRC_REG(RDC_BASE_PTR,30)
38746 #define RDC_MRVS30                               RDC_MRVS_REG(RDC_BASE_PTR,30)
38747 #define RDC_MRSA31                               RDC_MRSA_REG(RDC_BASE_PTR,31)
38748 #define RDC_MREA31                               RDC_MREA_REG(RDC_BASE_PTR,31)
38749 #define RDC_MRC31                                RDC_MRC_REG(RDC_BASE_PTR,31)
38750 #define RDC_MRVS31                               RDC_MRVS_REG(RDC_BASE_PTR,31)
38751 #define RDC_MRSA32                               RDC_MRSA_REG(RDC_BASE_PTR,32)
38752 #define RDC_MREA32                               RDC_MREA_REG(RDC_BASE_PTR,32)
38753 #define RDC_MRC32                                RDC_MRC_REG(RDC_BASE_PTR,32)
38754 #define RDC_MRVS32                               RDC_MRVS_REG(RDC_BASE_PTR,32)
38755 #define RDC_MRSA33                               RDC_MRSA_REG(RDC_BASE_PTR,33)
38756 #define RDC_MREA33                               RDC_MREA_REG(RDC_BASE_PTR,33)
38757 #define RDC_MRC33                                RDC_MRC_REG(RDC_BASE_PTR,33)
38758 #define RDC_MRVS33                               RDC_MRVS_REG(RDC_BASE_PTR,33)
38759 #define RDC_MRSA34                               RDC_MRSA_REG(RDC_BASE_PTR,34)
38760 #define RDC_MREA34                               RDC_MREA_REG(RDC_BASE_PTR,34)
38761 #define RDC_MRC34                                RDC_MRC_REG(RDC_BASE_PTR,34)
38762 #define RDC_MRVS34                               RDC_MRVS_REG(RDC_BASE_PTR,34)
38763 #define RDC_MRSA35                               RDC_MRSA_REG(RDC_BASE_PTR,35)
38764 #define RDC_MREA35                               RDC_MREA_REG(RDC_BASE_PTR,35)
38765 #define RDC_MRC35                                RDC_MRC_REG(RDC_BASE_PTR,35)
38766 #define RDC_MRVS35                               RDC_MRVS_REG(RDC_BASE_PTR,35)
38767 #define RDC_MRSA36                               RDC_MRSA_REG(RDC_BASE_PTR,36)
38768 #define RDC_MREA36                               RDC_MREA_REG(RDC_BASE_PTR,36)
38769 #define RDC_MRC36                                RDC_MRC_REG(RDC_BASE_PTR,36)
38770 #define RDC_MRVS36                               RDC_MRVS_REG(RDC_BASE_PTR,36)
38771 #define RDC_MRSA37                               RDC_MRSA_REG(RDC_BASE_PTR,37)
38772 #define RDC_MREA37                               RDC_MREA_REG(RDC_BASE_PTR,37)
38773 #define RDC_MRC37                                RDC_MRC_REG(RDC_BASE_PTR,37)
38774 #define RDC_MRVS37                               RDC_MRVS_REG(RDC_BASE_PTR,37)
38775 #define RDC_MRSA38                               RDC_MRSA_REG(RDC_BASE_PTR,38)
38776 #define RDC_MREA38                               RDC_MREA_REG(RDC_BASE_PTR,38)
38777 #define RDC_MRC38                                RDC_MRC_REG(RDC_BASE_PTR,38)
38778 #define RDC_MRVS38                               RDC_MRVS_REG(RDC_BASE_PTR,38)
38779 #define RDC_MRSA39                               RDC_MRSA_REG(RDC_BASE_PTR,39)
38780 #define RDC_MREA39                               RDC_MREA_REG(RDC_BASE_PTR,39)
38781 #define RDC_MRC39                                RDC_MRC_REG(RDC_BASE_PTR,39)
38782 #define RDC_MRVS39                               RDC_MRVS_REG(RDC_BASE_PTR,39)
38783 #define RDC_MRSA40                               RDC_MRSA_REG(RDC_BASE_PTR,40)
38784 #define RDC_MREA40                               RDC_MREA_REG(RDC_BASE_PTR,40)
38785 #define RDC_MRC40                                RDC_MRC_REG(RDC_BASE_PTR,40)
38786 #define RDC_MRVS40                               RDC_MRVS_REG(RDC_BASE_PTR,40)
38787 #define RDC_MRSA41                               RDC_MRSA_REG(RDC_BASE_PTR,41)
38788 #define RDC_MREA41                               RDC_MREA_REG(RDC_BASE_PTR,41)
38789 #define RDC_MRC41                                RDC_MRC_REG(RDC_BASE_PTR,41)
38790 #define RDC_MRVS41                               RDC_MRVS_REG(RDC_BASE_PTR,41)
38791 #define RDC_MRSA42                               RDC_MRSA_REG(RDC_BASE_PTR,42)
38792 #define RDC_MREA42                               RDC_MREA_REG(RDC_BASE_PTR,42)
38793 #define RDC_MRC42                                RDC_MRC_REG(RDC_BASE_PTR,42)
38794 #define RDC_MRVS42                               RDC_MRVS_REG(RDC_BASE_PTR,42)
38795 #define RDC_MRSA43                               RDC_MRSA_REG(RDC_BASE_PTR,43)
38796 #define RDC_MREA43                               RDC_MREA_REG(RDC_BASE_PTR,43)
38797 #define RDC_MRC43                                RDC_MRC_REG(RDC_BASE_PTR,43)
38798 #define RDC_MRVS43                               RDC_MRVS_REG(RDC_BASE_PTR,43)
38799 #define RDC_MRSA44                               RDC_MRSA_REG(RDC_BASE_PTR,44)
38800 #define RDC_MREA44                               RDC_MREA_REG(RDC_BASE_PTR,44)
38801 #define RDC_MRC44                                RDC_MRC_REG(RDC_BASE_PTR,44)
38802 #define RDC_MRVS44                               RDC_MRVS_REG(RDC_BASE_PTR,44)
38803 #define RDC_MRSA45                               RDC_MRSA_REG(RDC_BASE_PTR,45)
38804 #define RDC_MREA45                               RDC_MREA_REG(RDC_BASE_PTR,45)
38805 #define RDC_MRC45                                RDC_MRC_REG(RDC_BASE_PTR,45)
38806 #define RDC_MRVS45                               RDC_MRVS_REG(RDC_BASE_PTR,45)
38807 #define RDC_MRSA46                               RDC_MRSA_REG(RDC_BASE_PTR,46)
38808 #define RDC_MREA46                               RDC_MREA_REG(RDC_BASE_PTR,46)
38809 #define RDC_MRC46                                RDC_MRC_REG(RDC_BASE_PTR,46)
38810 #define RDC_MRVS46                               RDC_MRVS_REG(RDC_BASE_PTR,46)
38811 #define RDC_MRSA47                               RDC_MRSA_REG(RDC_BASE_PTR,47)
38812 #define RDC_MREA47                               RDC_MREA_REG(RDC_BASE_PTR,47)
38813 #define RDC_MRC47                                RDC_MRC_REG(RDC_BASE_PTR,47)
38814 #define RDC_MRVS47                               RDC_MRVS_REG(RDC_BASE_PTR,47)
38815 #define RDC_MRSA48                               RDC_MRSA_REG(RDC_BASE_PTR,48)
38816 #define RDC_MREA48                               RDC_MREA_REG(RDC_BASE_PTR,48)
38817 #define RDC_MRC48                                RDC_MRC_REG(RDC_BASE_PTR,48)
38818 #define RDC_MRVS48                               RDC_MRVS_REG(RDC_BASE_PTR,48)
38819 #define RDC_MRSA49                               RDC_MRSA_REG(RDC_BASE_PTR,49)
38820 #define RDC_MREA49                               RDC_MREA_REG(RDC_BASE_PTR,49)
38821 #define RDC_MRC49                                RDC_MRC_REG(RDC_BASE_PTR,49)
38822 #define RDC_MRVS49                               RDC_MRVS_REG(RDC_BASE_PTR,49)
38823 #define RDC_MRSA50                               RDC_MRSA_REG(RDC_BASE_PTR,50)
38824 #define RDC_MREA50                               RDC_MREA_REG(RDC_BASE_PTR,50)
38825 #define RDC_MRC50                                RDC_MRC_REG(RDC_BASE_PTR,50)
38826 #define RDC_MRVS50                               RDC_MRVS_REG(RDC_BASE_PTR,50)
38827 #define RDC_MRSA51                               RDC_MRSA_REG(RDC_BASE_PTR,51)
38828 #define RDC_MREA51                               RDC_MREA_REG(RDC_BASE_PTR,51)
38829 #define RDC_MRC51                                RDC_MRC_REG(RDC_BASE_PTR,51)
38830 #define RDC_MRVS51                               RDC_MRVS_REG(RDC_BASE_PTR,51)
38831 /* RDC - Register array accessors */
38832 #define RDC_MDA(index)                           RDC_MDA_REG(RDC_BASE_PTR,index)
38833 #define RDC_PDAP(index)                          RDC_PDAP_REG(RDC_BASE_PTR,index)
38834 #define RDC_MRSA(index)                          RDC_MRSA_REG(RDC_BASE_PTR,index)
38835 #define RDC_MREA(index)                          RDC_MREA_REG(RDC_BASE_PTR,index)
38836 #define RDC_MRC(index)                           RDC_MRC_REG(RDC_BASE_PTR,index)
38837 #define RDC_MRVS(index)                          RDC_MRVS_REG(RDC_BASE_PTR,index)
38838 /*!
38839  * @}
38840  */ /* end of group RDC_Register_Accessor_Macros */
38841 
38842 
38843 /*!
38844  * @}
38845  */ /* end of group RDC_Peripheral */
38846 
38847 /* ----------------------------------------------------------------------------
38848    -- RDC_SEMAPHORE Peripheral Access Layer
38849    ---------------------------------------------------------------------------- */
38850 
38851 /*!
38852  * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
38853  * @{
38854  */
38855 
38856 /** RDC_SEMAPHORE - Register Layout Typedef */
38857 typedef struct {
38858   __IO  uint8_t  GATE[64];                               /**< Gate Register, array offset: 0x0, array step: 0x1 */
38859   union {                                          /* offset: 0x40 */
38860   __IO    uint16_t RSTGT_W;                                     /**< Reset Gate Write,offset: 0x40 */
38861   __IO    uint16_t RSTGT_R;                                     /**< Reset Gate Read,offset: 0x40 */
38862   };
38863 } RDC_SEMAPHORE_Type, *RDC_SEMAPHORE_MemMapPtr;
38864 /* ----------------------------------------------------------------------------
38865    -- RDC_SEMAPHORE - Register accessor macros
38866    ---------------------------------------------------------------------------- */
38867 
38868 /*!
38869  * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros
38870  * @{
38871  */
38872 
38873 
38874 /* RDC_SEMAPHORE - Register accessors */
38875 #define RDC_SEMAPHORE_GATE_REG(base,index)       ((base)->GATE[index])
38876 #define RDC_SEMAPHORE_RSTGT_W_REG(base)          ((base)->RSTGT_W)
38877 #define RDC_SEMAPHORE_RSTGT_R_REG(base)          ((base)->RSTGT_R)
38878 
38879 /*!
38880  * @}
38881  */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */
38882 /* ----------------------------------------------------------------------------
38883    -- RDC_SEMAPHORE Register Masks
38884    ---------------------------------------------------------------------------- */
38885 
38886 /*!
38887  * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
38888  * @{
38889  */
38890 
38891 /* GATE Bit Fields */
38892 #define RDC_SEMAPHORE_GATE_GTFSM_MASK            0xFu
38893 #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT           0
38894 #define RDC_SEMAPHORE_GATE_GTFSM(x)              (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_GTFSM_SHIFT))&RDC_SEMAPHORE_GATE_GTFSM_MASK)
38895 #define RDC_SEMAPHORE_GATE_LDOM_MASK             0x30u
38896 #define RDC_SEMAPHORE_GATE_LDOM_SHIFT            4
38897 #define RDC_SEMAPHORE_GATE_LDOM(x)               (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_LDOM_SHIFT))&RDC_SEMAPHORE_GATE_LDOM_MASK)
38898 /* RSTGT_W Bit Fields */
38899 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK        0xFFu
38900 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT       0
38901 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
38902 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK        0xFF00u
38903 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT       8
38904 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
38905 /* RSTGT_R Bit Fields */
38906 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK        0xFu
38907 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT       0
38908 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
38909 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK        0x30u
38910 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT       4
38911 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
38912 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK        0xFF00u
38913 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT       8
38914 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
38915 
38916 /*!
38917  * @}
38918  */ /* end of group RDC_SEMAPHORE_Register_Masks */
38919 
38920 /* RDC_SEMAPHORE - Peripheral instance base addresses */
38921 /** Peripheral RDC_SEMAPHORE1 base address */
38922 #define RDC_SEMAPHORE1_BASE                      (0x303B0000u)
38923 /** Peripheral RDC_SEMAPHORE1 base pointer */
38924 #define RDC_SEMAPHORE1                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
38925 #define RDC_SEMAPHORE1_BASE_PTR                  (RDC_SEMAPHORE1)
38926 /** Peripheral RDC_SEMAPHORE2 base address */
38927 #define RDC_SEMAPHORE2_BASE                      (0x303C0000u)
38928 /** Peripheral RDC_SEMAPHORE2 base pointer */
38929 #define RDC_SEMAPHORE2                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
38930 #define RDC_SEMAPHORE2_BASE_PTR                  (RDC_SEMAPHORE2)
38931 /** Array initializer of RDC_SEMAPHORE peripheral base addresses */
38932 #define RDC_SEMAPHORE_BASE_ADDRS                 { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
38933 /** Array initializer of RDC_SEMAPHORE peripheral base pointers */
38934 #define RDC_SEMAPHORE_BASE_PTRS                  { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
38935 /* ----------------------------------------------------------------------------
38936    -- RDC_SEMAPHORE - Register accessor macros
38937    ---------------------------------------------------------------------------- */
38938 
38939 /*!
38940  * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros
38941  * @{
38942  */
38943 
38944 
38945 /* RDC_SEMAPHORE - Register instance definitions */
38946 /* RDC_SEMAPHORE1 */
38947 #define RDC_SEMAPHORE1_GATE0                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,0)
38948 #define RDC_SEMAPHORE1_GATE1                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,1)
38949 #define RDC_SEMAPHORE1_GATE2                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,2)
38950 #define RDC_SEMAPHORE1_GATE3                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,3)
38951 #define RDC_SEMAPHORE1_GATE4                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,4)
38952 #define RDC_SEMAPHORE1_GATE5                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,5)
38953 #define RDC_SEMAPHORE1_GATE6                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,6)
38954 #define RDC_SEMAPHORE1_GATE7                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,7)
38955 #define RDC_SEMAPHORE1_GATE8                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,8)
38956 #define RDC_SEMAPHORE1_GATE9                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,9)
38957 #define RDC_SEMAPHORE1_GATE10                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,10)
38958 #define RDC_SEMAPHORE1_GATE11                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,11)
38959 #define RDC_SEMAPHORE1_GATE12                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,12)
38960 #define RDC_SEMAPHORE1_GATE13                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,13)
38961 #define RDC_SEMAPHORE1_GATE14                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,14)
38962 #define RDC_SEMAPHORE1_GATE15                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,15)
38963 #define RDC_SEMAPHORE1_GATE16                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,16)
38964 #define RDC_SEMAPHORE1_GATE17                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,17)
38965 #define RDC_SEMAPHORE1_GATE18                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,18)
38966 #define RDC_SEMAPHORE1_GATE19                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,19)
38967 #define RDC_SEMAPHORE1_GATE20                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,20)
38968 #define RDC_SEMAPHORE1_GATE21                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,21)
38969 #define RDC_SEMAPHORE1_GATE22                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,22)
38970 #define RDC_SEMAPHORE1_GATE23                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,23)
38971 #define RDC_SEMAPHORE1_GATE24                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,24)
38972 #define RDC_SEMAPHORE1_GATE25                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,25)
38973 #define RDC_SEMAPHORE1_GATE26                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,26)
38974 #define RDC_SEMAPHORE1_GATE27                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,27)
38975 #define RDC_SEMAPHORE1_GATE28                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,28)
38976 #define RDC_SEMAPHORE1_GATE29                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,29)
38977 #define RDC_SEMAPHORE1_GATE30                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,30)
38978 #define RDC_SEMAPHORE1_GATE31                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,31)
38979 #define RDC_SEMAPHORE1_GATE32                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,32)
38980 #define RDC_SEMAPHORE1_GATE33                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,33)
38981 #define RDC_SEMAPHORE1_GATE34                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,34)
38982 #define RDC_SEMAPHORE1_GATE35                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,35)
38983 #define RDC_SEMAPHORE1_GATE36                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,36)
38984 #define RDC_SEMAPHORE1_GATE37                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,37)
38985 #define RDC_SEMAPHORE1_GATE38                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,38)
38986 #define RDC_SEMAPHORE1_GATE39                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,39)
38987 #define RDC_SEMAPHORE1_GATE40                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,40)
38988 #define RDC_SEMAPHORE1_GATE41                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,41)
38989 #define RDC_SEMAPHORE1_GATE42                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,42)
38990 #define RDC_SEMAPHORE1_GATE43                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,43)
38991 #define RDC_SEMAPHORE1_GATE44                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,44)
38992 #define RDC_SEMAPHORE1_GATE45                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,45)
38993 #define RDC_SEMAPHORE1_GATE46                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,46)
38994 #define RDC_SEMAPHORE1_GATE47                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,47)
38995 #define RDC_SEMAPHORE1_GATE48                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,48)
38996 #define RDC_SEMAPHORE1_GATE49                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,49)
38997 #define RDC_SEMAPHORE1_GATE50                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,50)
38998 #define RDC_SEMAPHORE1_GATE51                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,51)
38999 #define RDC_SEMAPHORE1_GATE52                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,52)
39000 #define RDC_SEMAPHORE1_GATE53                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,53)
39001 #define RDC_SEMAPHORE1_GATE54                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,54)
39002 #define RDC_SEMAPHORE1_GATE55                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,55)
39003 #define RDC_SEMAPHORE1_GATE56                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,56)
39004 #define RDC_SEMAPHORE1_GATE57                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,57)
39005 #define RDC_SEMAPHORE1_GATE58                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,58)
39006 #define RDC_SEMAPHORE1_GATE59                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,59)
39007 #define RDC_SEMAPHORE1_GATE60                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,60)
39008 #define RDC_SEMAPHORE1_GATE61                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,61)
39009 #define RDC_SEMAPHORE1_GATE62                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,62)
39010 #define RDC_SEMAPHORE1_GATE63                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,63)
39011 #define RDC_SEMAPHORE1_RSTGT_W                   RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE1_BASE_PTR)
39012 #define RDC_SEMAPHORE1_RSTGT_R                   RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE1_BASE_PTR)
39013 /* RDC_SEMAPHORE2 */
39014 #define RDC_SEMAPHORE2_GATE0                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,0)
39015 #define RDC_SEMAPHORE2_GATE1                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,1)
39016 #define RDC_SEMAPHORE2_GATE2                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,2)
39017 #define RDC_SEMAPHORE2_GATE3                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,3)
39018 #define RDC_SEMAPHORE2_GATE4                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,4)
39019 #define RDC_SEMAPHORE2_GATE5                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,5)
39020 #define RDC_SEMAPHORE2_GATE6                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,6)
39021 #define RDC_SEMAPHORE2_GATE7                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,7)
39022 #define RDC_SEMAPHORE2_GATE8                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,8)
39023 #define RDC_SEMAPHORE2_GATE9                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,9)
39024 #define RDC_SEMAPHORE2_GATE10                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,10)
39025 #define RDC_SEMAPHORE2_GATE11                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,11)
39026 #define RDC_SEMAPHORE2_GATE12                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,12)
39027 #define RDC_SEMAPHORE2_GATE13                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,13)
39028 #define RDC_SEMAPHORE2_GATE14                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,14)
39029 #define RDC_SEMAPHORE2_GATE15                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,15)
39030 #define RDC_SEMAPHORE2_GATE16                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,16)
39031 #define RDC_SEMAPHORE2_GATE17                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,17)
39032 #define RDC_SEMAPHORE2_GATE18                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,18)
39033 #define RDC_SEMAPHORE2_GATE19                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,19)
39034 #define RDC_SEMAPHORE2_GATE20                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,20)
39035 #define RDC_SEMAPHORE2_GATE21                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,21)
39036 #define RDC_SEMAPHORE2_GATE22                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,22)
39037 #define RDC_SEMAPHORE2_GATE23                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,23)
39038 #define RDC_SEMAPHORE2_GATE24                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,24)
39039 #define RDC_SEMAPHORE2_GATE25                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,25)
39040 #define RDC_SEMAPHORE2_GATE26                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,26)
39041 #define RDC_SEMAPHORE2_GATE27                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,27)
39042 #define RDC_SEMAPHORE2_GATE28                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,28)
39043 #define RDC_SEMAPHORE2_GATE29                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,29)
39044 #define RDC_SEMAPHORE2_GATE30                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,30)
39045 #define RDC_SEMAPHORE2_GATE31                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,31)
39046 #define RDC_SEMAPHORE2_GATE32                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,32)
39047 #define RDC_SEMAPHORE2_GATE33                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,33)
39048 #define RDC_SEMAPHORE2_GATE34                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,34)
39049 #define RDC_SEMAPHORE2_GATE35                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,35)
39050 #define RDC_SEMAPHORE2_GATE36                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,36)
39051 #define RDC_SEMAPHORE2_GATE37                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,37)
39052 #define RDC_SEMAPHORE2_GATE38                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,38)
39053 #define RDC_SEMAPHORE2_GATE39                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,39)
39054 #define RDC_SEMAPHORE2_GATE40                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,40)
39055 #define RDC_SEMAPHORE2_GATE41                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,41)
39056 #define RDC_SEMAPHORE2_GATE42                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,42)
39057 #define RDC_SEMAPHORE2_GATE43                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,43)
39058 #define RDC_SEMAPHORE2_GATE44                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,44)
39059 #define RDC_SEMAPHORE2_GATE45                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,45)
39060 #define RDC_SEMAPHORE2_GATE46                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,46)
39061 #define RDC_SEMAPHORE2_GATE47                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,47)
39062 #define RDC_SEMAPHORE2_GATE48                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,48)
39063 #define RDC_SEMAPHORE2_GATE49                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,49)
39064 #define RDC_SEMAPHORE2_GATE50                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,50)
39065 #define RDC_SEMAPHORE2_GATE51                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,51)
39066 #define RDC_SEMAPHORE2_GATE52                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,52)
39067 #define RDC_SEMAPHORE2_GATE53                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,53)
39068 #define RDC_SEMAPHORE2_GATE54                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,54)
39069 #define RDC_SEMAPHORE2_GATE55                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,55)
39070 #define RDC_SEMAPHORE2_GATE56                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,56)
39071 #define RDC_SEMAPHORE2_GATE57                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,57)
39072 #define RDC_SEMAPHORE2_GATE58                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,58)
39073 #define RDC_SEMAPHORE2_GATE59                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,59)
39074 #define RDC_SEMAPHORE2_GATE60                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,60)
39075 #define RDC_SEMAPHORE2_GATE61                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,61)
39076 #define RDC_SEMAPHORE2_GATE62                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,62)
39077 #define RDC_SEMAPHORE2_GATE63                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,63)
39078 #define RDC_SEMAPHORE2_RSTGT_W                   RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE2_BASE_PTR)
39079 #define RDC_SEMAPHORE2_RSTGT_R                   RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE2_BASE_PTR)
39080 /* RDC_SEMAPHORE - Register array accessors */
39081 #define RDC_SEMAPHORE1_GATE(index)               RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,index)
39082 #define RDC_SEMAPHORE2_GATE(index)               RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,index)
39083 /*!
39084  * @}
39085  */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */
39086 
39087 
39088 /*!
39089  * @}
39090  */ /* end of group RDC_SEMAPHORE_Peripheral */
39091 
39092 /* ----------------------------------------------------------------------------
39093    -- ROMC Peripheral Access Layer
39094    ---------------------------------------------------------------------------- */
39095 
39096 /*!
39097  * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
39098  * @{
39099  */
39100 
39101 /** ROMC - Register Layout Typedef */
39102 typedef struct {
39103   uint8_t RESERVED_0[212];
39104   __IO  uint32_t ROMPATCHD[8];                           /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
39105   __IO  uint32_t ROMPATCHCNTL;                           /**< ROMC Control Register, offset: 0xF4 */
39106   __I   uint32_t ROMPATCHENH;                            /**< ROMC Enable Register High, offset: 0xF8 */
39107   __IO  uint32_t ROMPATCHENL;                            /**< ROMC Enable Register Low, offset: 0xFC */
39108   __IO  uint32_t ROMPATCHA[16];                          /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
39109   uint8_t RESERVED_1[200];
39110   __IO  uint32_t ROMPATCHSR;                             /**< ROMC Status Register, offset: 0x208 */
39111 } ROMC_Type, *ROMC_MemMapPtr;
39112 /* ----------------------------------------------------------------------------
39113    -- ROMC - Register accessor macros
39114    ---------------------------------------------------------------------------- */
39115 
39116 /*!
39117  * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros
39118  * @{
39119  */
39120 
39121 
39122 /* ROMC - Register accessors */
39123 #define ROMC_ROMPATCHD_REG(base,index)           ((base)->ROMPATCHD[index])
39124 #define ROMC_ROMPATCHCNTL_REG(base)              ((base)->ROMPATCHCNTL)
39125 #define ROMC_ROMPATCHENH_REG(base)               ((base)->ROMPATCHENH)
39126 #define ROMC_ROMPATCHENL_REG(base)               ((base)->ROMPATCHENL)
39127 #define ROMC_ROMPATCHA_REG(base,index)           ((base)->ROMPATCHA[index])
39128 #define ROMC_ROMPATCHSR_REG(base)                ((base)->ROMPATCHSR)
39129 
39130 /*!
39131  * @}
39132  */ /* end of group ROMC_Register_Accessor_Macros */
39133 /* ----------------------------------------------------------------------------
39134    -- ROMC Register Masks
39135    ---------------------------------------------------------------------------- */
39136 
39137 /*!
39138  * @addtogroup ROMC_Register_Masks ROMC Register Masks
39139  * @{
39140  */
39141 
39142 /* ROMPATCHD Bit Fields */
39143 #define ROMC_ROMPATCHD_DATAX_MASK                0xFFFFFFFFu
39144 #define ROMC_ROMPATCHD_DATAX_SHIFT               0
39145 #define ROMC_ROMPATCHD_DATAX(x)                  (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHD_DATAX_SHIFT))&ROMC_ROMPATCHD_DATAX_MASK)
39146 /* ROMPATCHCNTL Bit Fields */
39147 #define ROMC_ROMPATCHCNTL_DATAFIX_MASK           0xFFu
39148 #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT          0
39149 #define ROMC_ROMPATCHCNTL_DATAFIX(x)             (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHCNTL_DATAFIX_SHIFT))&ROMC_ROMPATCHCNTL_DATAFIX_MASK)
39150 #define ROMC_ROMPATCHCNTL_DIS_MASK               0x20000000u
39151 #define ROMC_ROMPATCHCNTL_DIS_SHIFT              29
39152 /* ROMPATCHENH Bit Fields */
39153 /* ROMPATCHENL Bit Fields */
39154 #define ROMC_ROMPATCHENL_ENABLE_MASK             0xFFFFu
39155 #define ROMC_ROMPATCHENL_ENABLE_SHIFT            0
39156 #define ROMC_ROMPATCHENL_ENABLE(x)               (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHENL_ENABLE_SHIFT))&ROMC_ROMPATCHENL_ENABLE_MASK)
39157 /* ROMPATCHA Bit Fields */
39158 #define ROMC_ROMPATCHA_THUMBX_MASK               0x1u
39159 #define ROMC_ROMPATCHA_THUMBX_SHIFT              0
39160 #define ROMC_ROMPATCHA_ADDRX_MASK                0x7FFFFEu
39161 #define ROMC_ROMPATCHA_ADDRX_SHIFT               1
39162 #define ROMC_ROMPATCHA_ADDRX(x)                  (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHA_ADDRX_SHIFT))&ROMC_ROMPATCHA_ADDRX_MASK)
39163 /* ROMPATCHSR Bit Fields */
39164 #define ROMC_ROMPATCHSR_SOURCE_MASK              0x3Fu
39165 #define ROMC_ROMPATCHSR_SOURCE_SHIFT             0
39166 #define ROMC_ROMPATCHSR_SOURCE(x)                (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHSR_SOURCE_SHIFT))&ROMC_ROMPATCHSR_SOURCE_MASK)
39167 #define ROMC_ROMPATCHSR_SW_MASK                  0x20000u
39168 #define ROMC_ROMPATCHSR_SW_SHIFT                 17
39169 
39170 /*!
39171  * @}
39172  */ /* end of group ROMC_Register_Masks */
39173 
39174 /* ROMC - Peripheral instance base addresses */
39175 /** Peripheral ROMC base address */
39176 #define ROMC_BASE                                (0x30310000u)
39177 /** Peripheral ROMC base pointer */
39178 #define ROMC                                     ((ROMC_Type *)ROMC_BASE)
39179 #define ROMC_BASE_PTR                            (ROMC)
39180 /** Array initializer of ROMC peripheral base addresses */
39181 #define ROMC_BASE_ADDRS                          { ROMC_BASE }
39182 /** Array initializer of ROMC peripheral base pointers */
39183 #define ROMC_BASE_PTRS                           { ROMC }
39184 /* ----------------------------------------------------------------------------
39185    -- ROMC - Register accessor macros
39186    ---------------------------------------------------------------------------- */
39187 
39188 /*!
39189  * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros
39190  * @{
39191  */
39192 
39193 
39194 /* ROMC - Register instance definitions */
39195 /* ROMC */
39196 #define ROMC_ROMPATCH0D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,0)
39197 #define ROMC_ROMPATCH1D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,1)
39198 #define ROMC_ROMPATCH2D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,2)
39199 #define ROMC_ROMPATCH3D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,3)
39200 #define ROMC_ROMPATCH4D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,4)
39201 #define ROMC_ROMPATCH5D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,5)
39202 #define ROMC_ROMPATCH6D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,6)
39203 #define ROMC_ROMPATCH7D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,7)
39204 #define ROMC_ROMPATCHCNTL                        ROMC_ROMPATCHCNTL_REG(ROMC_BASE_PTR)
39205 #define ROMC_ROMPATCHENH                         ROMC_ROMPATCHENH_REG(ROMC_BASE_PTR)
39206 #define ROMC_ROMPATCHENL                         ROMC_ROMPATCHENL_REG(ROMC_BASE_PTR)
39207 #define ROMC_ROMPATCH0A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,0)
39208 #define ROMC_ROMPATCH1A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,1)
39209 #define ROMC_ROMPATCH2A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,2)
39210 #define ROMC_ROMPATCH3A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,3)
39211 #define ROMC_ROMPATCH4A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,4)
39212 #define ROMC_ROMPATCH5A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,5)
39213 #define ROMC_ROMPATCH6A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,6)
39214 #define ROMC_ROMPATCH7A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,7)
39215 #define ROMC_ROMPATCH8A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,8)
39216 #define ROMC_ROMPATCH9A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,9)
39217 #define ROMC_ROMPATCH10A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,10)
39218 #define ROMC_ROMPATCH11A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,11)
39219 #define ROMC_ROMPATCH12A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,12)
39220 #define ROMC_ROMPATCH13A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,13)
39221 #define ROMC_ROMPATCH14A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,14)
39222 #define ROMC_ROMPATCH15A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,15)
39223 #define ROMC_ROMPATCHSR                          ROMC_ROMPATCHSR_REG(ROMC_BASE_PTR)
39224 /* ROMC - Register array accessors */
39225 #define ROMC_ROMPATCHD(index)                    ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,index)
39226 #define ROMC_ROMPATCHA(index)                    ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,index)
39227 /*!
39228  * @}
39229  */ /* end of group ROMC_Register_Accessor_Macros */
39230 
39231 
39232 /*!
39233  * @}
39234  */ /* end of group ROMC_Peripheral */
39235 
39236 /* ----------------------------------------------------------------------------
39237    -- SDMAARM Peripheral Access Layer
39238    ---------------------------------------------------------------------------- */
39239 
39240 /*!
39241  * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer
39242  * @{
39243  */
39244 
39245 /** SDMAARM - Register Layout Typedef */
39246 typedef struct {
39247   __IO  uint32_t MC0PTR;                                 /**< ARM platform Channel 0 Pointer, offset: 0x0 */
39248   __IO  uint32_t INTR;                                   /**< Channel Interrupts, offset: 0x4 */
39249   __IO  uint32_t STOP_STAT;                              /**< Channel Stop/Channel Status, offset: 0x8 */
39250   __IO  uint32_t HSTART;                                 /**< Channel Start, offset: 0xC */
39251   __IO  uint32_t EVTOVR;                                 /**< Channel Event Override, offset: 0x10 */
39252   __IO  uint32_t DSPOVR;                                 /**< Channel BP Override, offset: 0x14 */
39253   __IO  uint32_t HOSTOVR;                                /**< Channel ARM platform Override, offset: 0x18 */
39254   __IO  uint32_t EVTPEND;                                /**< Channel Event Pending, offset: 0x1C */
39255   uint8_t RESERVED_0[4];
39256   __I   uint32_t RESET;                                  /**< Reset Register, offset: 0x24 */
39257   __I   uint32_t EVTERR;                                 /**< DMA Request Error Register, offset: 0x28 */
39258   __IO  uint32_t INTRMASK;                               /**< Channel ARM platform Interrupt Mask, offset: 0x2C */
39259   __I   uint32_t PSW;                                    /**< Schedule Status, offset: 0x30 */
39260   __I   uint32_t EVTERRDBG;                              /**< DMA Request Error Register, offset: 0x34 */
39261   __IO  uint32_t CONFIG;                                 /**< Configuration Register, offset: 0x38 */
39262   __IO  uint32_t SDMA_LOCK;                              /**< SDMA LOCK, offset: 0x3C */
39263   __IO  uint32_t ONCE_ENB;                               /**< OnCE Enable, offset: 0x40 */
39264   __IO  uint32_t ONCE_DATA;                              /**< OnCE Data Register, offset: 0x44 */
39265   __IO  uint32_t ONCE_INSTR;                             /**< OnCE Instruction Register, offset: 0x48 */
39266   __I   uint32_t ONCE_STAT;                              /**< OnCE Status Register, offset: 0x4C */
39267   __IO  uint32_t ONCE_CMD;                               /**< OnCE Command Register, offset: 0x50 */
39268   uint8_t RESERVED_1[4];
39269   __IO  uint32_t ILLINSTADDR;                            /**< Illegal Instruction Trap Address, offset: 0x58 */
39270   __IO  uint32_t CHN0ADDR;                               /**< Channel 0 Boot Address, offset: 0x5C */
39271   __I   uint32_t EVT_MIRROR;                             /**< DMA Requests, offset: 0x60 */
39272   __I   uint32_t EVT_MIRROR2;                            /**< DMA Requests 2, offset: 0x64 */
39273   uint8_t RESERVED_2[8];
39274   __IO  uint32_t XTRIG_CONF1;                            /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */
39275   __IO  uint32_t XTRIG_CONF2;                            /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */
39276   uint8_t RESERVED_3[136];
39277   __IO  uint32_t SDMA_CHNPRI[32];                        /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */
39278   uint8_t RESERVED_4[128];
39279   __IO  uint32_t CHNENBL[48];                            /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */
39280 } SDMAARM_Type, *SDMAARM_MemMapPtr;
39281 /* ----------------------------------------------------------------------------
39282    -- SDMAARM - Register accessor macros
39283    ---------------------------------------------------------------------------- */
39284 
39285 /*!
39286  * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros
39287  * @{
39288  */
39289 
39290 
39291 /* SDMAARM - Register accessors */
39292 #define SDMAARM_MC0PTR_REG(base)                 ((base)->MC0PTR)
39293 #define SDMAARM_INTR_REG(base)                   ((base)->INTR)
39294 #define SDMAARM_STOP_STAT_REG(base)              ((base)->STOP_STAT)
39295 #define SDMAARM_HSTART_REG(base)                 ((base)->HSTART)
39296 #define SDMAARM_EVTOVR_REG(base)                 ((base)->EVTOVR)
39297 #define SDMAARM_DSPOVR_REG(base)                 ((base)->DSPOVR)
39298 #define SDMAARM_HOSTOVR_REG(base)                ((base)->HOSTOVR)
39299 #define SDMAARM_EVTPEND_REG(base)                ((base)->EVTPEND)
39300 #define SDMAARM_RESET_REG(base)                  ((base)->RESET)
39301 #define SDMAARM_EVTERR_REG(base)                 ((base)->EVTERR)
39302 #define SDMAARM_INTRMASK_REG(base)               ((base)->INTRMASK)
39303 #define SDMAARM_PSW_REG(base)                    ((base)->PSW)
39304 #define SDMAARM_EVTERRDBG_REG(base)              ((base)->EVTERRDBG)
39305 #define SDMAARM_CONFIG_REG(base)                 ((base)->CONFIG)
39306 #define SDMAARM_SDMA_LOCK_REG(base)              ((base)->SDMA_LOCK)
39307 #define SDMAARM_ONCE_ENB_REG(base)               ((base)->ONCE_ENB)
39308 #define SDMAARM_ONCE_DATA_REG(base)              ((base)->ONCE_DATA)
39309 #define SDMAARM_ONCE_INSTR_REG(base)             ((base)->ONCE_INSTR)
39310 #define SDMAARM_ONCE_STAT_REG(base)              ((base)->ONCE_STAT)
39311 #define SDMAARM_ONCE_CMD_REG(base)               ((base)->ONCE_CMD)
39312 #define SDMAARM_ILLINSTADDR_REG(base)            ((base)->ILLINSTADDR)
39313 #define SDMAARM_CHN0ADDR_REG(base)               ((base)->CHN0ADDR)
39314 #define SDMAARM_EVT_MIRROR_REG(base)             ((base)->EVT_MIRROR)
39315 #define SDMAARM_EVT_MIRROR2_REG(base)            ((base)->EVT_MIRROR2)
39316 #define SDMAARM_XTRIG_CONF1_REG(base)            ((base)->XTRIG_CONF1)
39317 #define SDMAARM_XTRIG_CONF2_REG(base)            ((base)->XTRIG_CONF2)
39318 #define SDMAARM_SDMA_CHNPRI_REG(base,index)      ((base)->SDMA_CHNPRI[index])
39319 #define SDMAARM_CHNENBL_REG(base,index)          ((base)->CHNENBL[index])
39320 
39321 /*!
39322  * @}
39323  */ /* end of group SDMAARM_Register_Accessor_Macros */
39324 /* ----------------------------------------------------------------------------
39325    -- SDMAARM Register Masks
39326    ---------------------------------------------------------------------------- */
39327 
39328 /*!
39329  * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks
39330  * @{
39331  */
39332 
39333 /* MC0PTR Bit Fields */
39334 #define SDMAARM_MC0PTR_MC0PTR_MASK               0xFFFFFFFFu
39335 #define SDMAARM_MC0PTR_MC0PTR_SHIFT              0
39336 #define SDMAARM_MC0PTR_MC0PTR(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_MC0PTR_MC0PTR_SHIFT))&SDMAARM_MC0PTR_MC0PTR_MASK)
39337 /* INTR Bit Fields */
39338 #define SDMAARM_INTR_HI_MASK                     0xFFFFFFFFu
39339 #define SDMAARM_INTR_HI_SHIFT                    0
39340 #define SDMAARM_INTR_HI(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTR_HI_SHIFT))&SDMAARM_INTR_HI_MASK)
39341 /* STOP_STAT Bit Fields */
39342 #define SDMAARM_STOP_STAT_HE_MASK                0xFFFFFFFFu
39343 #define SDMAARM_STOP_STAT_HE_SHIFT               0
39344 #define SDMAARM_STOP_STAT_HE(x)                  (((uint32_t)(((uint32_t)(x))<<SDMAARM_STOP_STAT_HE_SHIFT))&SDMAARM_STOP_STAT_HE_MASK)
39345 /* HSTART Bit Fields */
39346 #define SDMAARM_HSTART_HSTART_HE_MASK            0xFFFFFFFFu
39347 #define SDMAARM_HSTART_HSTART_HE_SHIFT           0
39348 #define SDMAARM_HSTART_HSTART_HE(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_HSTART_HSTART_HE_SHIFT))&SDMAARM_HSTART_HSTART_HE_MASK)
39349 /* EVTOVR Bit Fields */
39350 #define SDMAARM_EVTOVR_EO_MASK                   0xFFFFFFFFu
39351 #define SDMAARM_EVTOVR_EO_SHIFT                  0
39352 #define SDMAARM_EVTOVR_EO(x)                     (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTOVR_EO_SHIFT))&SDMAARM_EVTOVR_EO_MASK)
39353 /* DSPOVR Bit Fields */
39354 #define SDMAARM_DSPOVR_DO_MASK                   0xFFFFFFFFu
39355 #define SDMAARM_DSPOVR_DO_SHIFT                  0
39356 #define SDMAARM_DSPOVR_DO(x)                     (((uint32_t)(((uint32_t)(x))<<SDMAARM_DSPOVR_DO_SHIFT))&SDMAARM_DSPOVR_DO_MASK)
39357 /* HOSTOVR Bit Fields */
39358 #define SDMAARM_HOSTOVR_HO_MASK                  0xFFFFFFFFu
39359 #define SDMAARM_HOSTOVR_HO_SHIFT                 0
39360 #define SDMAARM_HOSTOVR_HO(x)                    (((uint32_t)(((uint32_t)(x))<<SDMAARM_HOSTOVR_HO_SHIFT))&SDMAARM_HOSTOVR_HO_MASK)
39361 /* EVTPEND Bit Fields */
39362 #define SDMAARM_EVTPEND_EP_MASK                  0xFFFFFFFFu
39363 #define SDMAARM_EVTPEND_EP_SHIFT                 0
39364 #define SDMAARM_EVTPEND_EP(x)                    (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTPEND_EP_SHIFT))&SDMAARM_EVTPEND_EP_MASK)
39365 /* RESET Bit Fields */
39366 #define SDMAARM_RESET_RESET_MASK                 0x1u
39367 #define SDMAARM_RESET_RESET_SHIFT                0
39368 #define SDMAARM_RESET_RESCHED_MASK               0x2u
39369 #define SDMAARM_RESET_RESCHED_SHIFT              1
39370 /* EVTERR Bit Fields */
39371 #define SDMAARM_EVTERR_CHNERR_MASK               0xFFFFFFFFu
39372 #define SDMAARM_EVTERR_CHNERR_SHIFT              0
39373 #define SDMAARM_EVTERR_CHNERR(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERR_CHNERR_SHIFT))&SDMAARM_EVTERR_CHNERR_MASK)
39374 /* INTRMASK Bit Fields */
39375 #define SDMAARM_INTRMASK_HIMASK_MASK             0xFFFFFFFFu
39376 #define SDMAARM_INTRMASK_HIMASK_SHIFT            0
39377 #define SDMAARM_INTRMASK_HIMASK(x)               (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTRMASK_HIMASK_SHIFT))&SDMAARM_INTRMASK_HIMASK_MASK)
39378 /* PSW Bit Fields */
39379 #define SDMAARM_PSW_CCR_MASK                     0xFu
39380 #define SDMAARM_PSW_CCR_SHIFT                    0
39381 #define SDMAARM_PSW_CCR(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCR_SHIFT))&SDMAARM_PSW_CCR_MASK)
39382 #define SDMAARM_PSW_CCP_MASK                     0xF0u
39383 #define SDMAARM_PSW_CCP_SHIFT                    4
39384 #define SDMAARM_PSW_CCP(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCP_SHIFT))&SDMAARM_PSW_CCP_MASK)
39385 #define SDMAARM_PSW_NCR_MASK                     0x1F00u
39386 #define SDMAARM_PSW_NCR_SHIFT                    8
39387 #define SDMAARM_PSW_NCR(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCR_SHIFT))&SDMAARM_PSW_NCR_MASK)
39388 #define SDMAARM_PSW_NCP_MASK                     0xE000u
39389 #define SDMAARM_PSW_NCP_SHIFT                    13
39390 #define SDMAARM_PSW_NCP(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCP_SHIFT))&SDMAARM_PSW_NCP_MASK)
39391 /* EVTERRDBG Bit Fields */
39392 #define SDMAARM_EVTERRDBG_CHNERR_MASK            0xFFFFFFFFu
39393 #define SDMAARM_EVTERRDBG_CHNERR_SHIFT           0
39394 #define SDMAARM_EVTERRDBG_CHNERR(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERRDBG_CHNERR_SHIFT))&SDMAARM_EVTERRDBG_CHNERR_MASK)
39395 /* CONFIG Bit Fields */
39396 #define SDMAARM_CONFIG_CSM_MASK                  0x3u
39397 #define SDMAARM_CONFIG_CSM_SHIFT                 0
39398 #define SDMAARM_CONFIG_CSM(x)                    (((uint32_t)(((uint32_t)(x))<<SDMAARM_CONFIG_CSM_SHIFT))&SDMAARM_CONFIG_CSM_MASK)
39399 #define SDMAARM_CONFIG_ACR_MASK                  0x10u
39400 #define SDMAARM_CONFIG_ACR_SHIFT                 4
39401 #define SDMAARM_CONFIG_RTDOBS_MASK               0x800u
39402 #define SDMAARM_CONFIG_RTDOBS_SHIFT              11
39403 #define SDMAARM_CONFIG_DSPDMA_MASK               0x1000u
39404 #define SDMAARM_CONFIG_DSPDMA_SHIFT              12
39405 /* SDMA_LOCK Bit Fields */
39406 #define SDMAARM_SDMA_LOCK_LOCK_MASK              0x1u
39407 #define SDMAARM_SDMA_LOCK_LOCK_SHIFT             0
39408 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK   0x2u
39409 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT  1
39410 /* ONCE_ENB Bit Fields */
39411 #define SDMAARM_ONCE_ENB_ENB_MASK                0x1u
39412 #define SDMAARM_ONCE_ENB_ENB_SHIFT               0
39413 /* ONCE_DATA Bit Fields */
39414 #define SDMAARM_ONCE_DATA_DATA_MASK              0xFFFFFFFFu
39415 #define SDMAARM_ONCE_DATA_DATA_SHIFT             0
39416 #define SDMAARM_ONCE_DATA_DATA(x)                (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_DATA_DATA_SHIFT))&SDMAARM_ONCE_DATA_DATA_MASK)
39417 /* ONCE_INSTR Bit Fields */
39418 #define SDMAARM_ONCE_INSTR_INSTR_MASK            0xFFFFu
39419 #define SDMAARM_ONCE_INSTR_INSTR_SHIFT           0
39420 #define SDMAARM_ONCE_INSTR_INSTR(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_INSTR_INSTR_SHIFT))&SDMAARM_ONCE_INSTR_INSTR_MASK)
39421 /* ONCE_STAT Bit Fields */
39422 #define SDMAARM_ONCE_STAT_ECDR_MASK              0x7u
39423 #define SDMAARM_ONCE_STAT_ECDR_SHIFT             0
39424 #define SDMAARM_ONCE_STAT_ECDR(x)                (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_ECDR_SHIFT))&SDMAARM_ONCE_STAT_ECDR_MASK)
39425 #define SDMAARM_ONCE_STAT_MST_MASK               0x80u
39426 #define SDMAARM_ONCE_STAT_MST_SHIFT              7
39427 #define SDMAARM_ONCE_STAT_SWB_MASK               0x100u
39428 #define SDMAARM_ONCE_STAT_SWB_SHIFT              8
39429 #define SDMAARM_ONCE_STAT_ODR_MASK               0x200u
39430 #define SDMAARM_ONCE_STAT_ODR_SHIFT              9
39431 #define SDMAARM_ONCE_STAT_EDR_MASK               0x400u
39432 #define SDMAARM_ONCE_STAT_EDR_SHIFT              10
39433 #define SDMAARM_ONCE_STAT_RCV_MASK               0x800u
39434 #define SDMAARM_ONCE_STAT_RCV_SHIFT              11
39435 #define SDMAARM_ONCE_STAT_PST_MASK               0xF000u
39436 #define SDMAARM_ONCE_STAT_PST_SHIFT              12
39437 #define SDMAARM_ONCE_STAT_PST(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_PST_SHIFT))&SDMAARM_ONCE_STAT_PST_MASK)
39438 /* ONCE_CMD Bit Fields */
39439 #define SDMAARM_ONCE_CMD_CMD_MASK                0xFu
39440 #define SDMAARM_ONCE_CMD_CMD_SHIFT               0
39441 #define SDMAARM_ONCE_CMD_CMD(x)                  (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_CMD_CMD_SHIFT))&SDMAARM_ONCE_CMD_CMD_MASK)
39442 /* ILLINSTADDR Bit Fields */
39443 #define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK     0x3FFFu
39444 #define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT    0
39445 #define SDMAARM_ILLINSTADDR_ILLINSTADDR(x)       (((uint32_t)(((uint32_t)(x))<<SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT))&SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK)
39446 /* CHN0ADDR Bit Fields */
39447 #define SDMAARM_CHN0ADDR_CHN0ADDR_MASK           0x3FFFu
39448 #define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT          0
39449 #define SDMAARM_CHN0ADDR_CHN0ADDR(x)             (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT))&SDMAARM_CHN0ADDR_CHN0ADDR_MASK)
39450 #define SDMAARM_CHN0ADDR_SMSZ_MASK               0x4000u
39451 #define SDMAARM_CHN0ADDR_SMSZ_SHIFT              14
39452 /* EVT_MIRROR Bit Fields */
39453 #define SDMAARM_EVT_MIRROR_EVENTS_MASK           0xFFFFFFFFu
39454 #define SDMAARM_EVT_MIRROR_EVENTS_SHIFT          0
39455 #define SDMAARM_EVT_MIRROR_EVENTS(x)             (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR_EVENTS_MASK)
39456 /* EVT_MIRROR2 Bit Fields */
39457 #define SDMAARM_EVT_MIRROR2_EVENTS_MASK          0xFFFFu
39458 #define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT         0
39459 #define SDMAARM_EVT_MIRROR2_EVENTS(x)            (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR2_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR2_EVENTS_MASK)
39460 /* XTRIG_CONF1 Bit Fields */
39461 #define SDMAARM_XTRIG_CONF1_NUM0_MASK            0x3Fu
39462 #define SDMAARM_XTRIG_CONF1_NUM0_SHIFT           0
39463 #define SDMAARM_XTRIG_CONF1_NUM0(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM0_SHIFT))&SDMAARM_XTRIG_CONF1_NUM0_MASK)
39464 #define SDMAARM_XTRIG_CONF1_CNF0_MASK            0x40u
39465 #define SDMAARM_XTRIG_CONF1_CNF0_SHIFT           6
39466 #define SDMAARM_XTRIG_CONF1_NUM1_MASK            0x3F00u
39467 #define SDMAARM_XTRIG_CONF1_NUM1_SHIFT           8
39468 #define SDMAARM_XTRIG_CONF1_NUM1(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM1_SHIFT))&SDMAARM_XTRIG_CONF1_NUM1_MASK)
39469 #define SDMAARM_XTRIG_CONF1_CNF1_MASK            0x4000u
39470 #define SDMAARM_XTRIG_CONF1_CNF1_SHIFT           14
39471 #define SDMAARM_XTRIG_CONF1_NUM2_MASK            0x3F0000u
39472 #define SDMAARM_XTRIG_CONF1_NUM2_SHIFT           16
39473 #define SDMAARM_XTRIG_CONF1_NUM2(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM2_SHIFT))&SDMAARM_XTRIG_CONF1_NUM2_MASK)
39474 #define SDMAARM_XTRIG_CONF1_CNF2_MASK            0x400000u
39475 #define SDMAARM_XTRIG_CONF1_CNF2_SHIFT           22
39476 #define SDMAARM_XTRIG_CONF1_NUM3_MASK            0x3F000000u
39477 #define SDMAARM_XTRIG_CONF1_NUM3_SHIFT           24
39478 #define SDMAARM_XTRIG_CONF1_NUM3(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM3_SHIFT))&SDMAARM_XTRIG_CONF1_NUM3_MASK)
39479 #define SDMAARM_XTRIG_CONF1_CNF3_MASK            0x40000000u
39480 #define SDMAARM_XTRIG_CONF1_CNF3_SHIFT           30
39481 /* XTRIG_CONF2 Bit Fields */
39482 #define SDMAARM_XTRIG_CONF2_NUM4_MASK            0x3Fu
39483 #define SDMAARM_XTRIG_CONF2_NUM4_SHIFT           0
39484 #define SDMAARM_XTRIG_CONF2_NUM4(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM4_SHIFT))&SDMAARM_XTRIG_CONF2_NUM4_MASK)
39485 #define SDMAARM_XTRIG_CONF2_CNF4_MASK            0x40u
39486 #define SDMAARM_XTRIG_CONF2_CNF4_SHIFT           6
39487 #define SDMAARM_XTRIG_CONF2_NUM5_MASK            0x3F00u
39488 #define SDMAARM_XTRIG_CONF2_NUM5_SHIFT           8
39489 #define SDMAARM_XTRIG_CONF2_NUM5(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM5_SHIFT))&SDMAARM_XTRIG_CONF2_NUM5_MASK)
39490 #define SDMAARM_XTRIG_CONF2_CNF5_MASK            0x4000u
39491 #define SDMAARM_XTRIG_CONF2_CNF5_SHIFT           14
39492 #define SDMAARM_XTRIG_CONF2_NUM6_MASK            0x3F0000u
39493 #define SDMAARM_XTRIG_CONF2_NUM6_SHIFT           16
39494 #define SDMAARM_XTRIG_CONF2_NUM6(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM6_SHIFT))&SDMAARM_XTRIG_CONF2_NUM6_MASK)
39495 #define SDMAARM_XTRIG_CONF2_CNF6_MASK            0x400000u
39496 #define SDMAARM_XTRIG_CONF2_CNF6_SHIFT           22
39497 #define SDMAARM_XTRIG_CONF2_NUM7_MASK            0x3F000000u
39498 #define SDMAARM_XTRIG_CONF2_NUM7_SHIFT           24
39499 #define SDMAARM_XTRIG_CONF2_NUM7(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM7_SHIFT))&SDMAARM_XTRIG_CONF2_NUM7_MASK)
39500 #define SDMAARM_XTRIG_CONF2_CNF7_MASK            0x40000000u
39501 #define SDMAARM_XTRIG_CONF2_CNF7_SHIFT           30
39502 /* SDMA_CHNPRI Bit Fields */
39503 #define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK         0x7u
39504 #define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT        0
39505 #define SDMAARM_SDMA_CHNPRI_CHNPRIn(x)           (((uint32_t)(((uint32_t)(x))<<SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT))&SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK)
39506 /* CHNENBL Bit Fields */
39507 #define SDMAARM_CHNENBL_ENBLn_MASK               0xFFFFFFFFu
39508 #define SDMAARM_CHNENBL_ENBLn_SHIFT              0
39509 #define SDMAARM_CHNENBL_ENBLn(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHNENBL_ENBLn_SHIFT))&SDMAARM_CHNENBL_ENBLn_MASK)
39510 
39511 /*!
39512  * @}
39513  */ /* end of group SDMAARM_Register_Masks */
39514 
39515 /* SDMAARM - Peripheral instance base addresses */
39516 /** Peripheral SDMAARM base address */
39517 #define SDMAARM_BASE                             (0x30BD0000u)
39518 /** Peripheral SDMAARM base pointer */
39519 #define SDMAARM                                  ((SDMAARM_Type *)SDMAARM_BASE)
39520 #define SDMAARM_BASE_PTR                         (SDMAARM)
39521 /** Array initializer of SDMAARM peripheral base addresses */
39522 #define SDMAARM_BASE_ADDRS                       { SDMAARM_BASE }
39523 /** Array initializer of SDMAARM peripheral base pointers */
39524 #define SDMAARM_BASE_PTRS                        { SDMAARM }
39525 /** Interrupt vectors for the SDMAARM peripheral type */
39526 #define SDMAARM_IRQS                             { SDMA_IRQn }
39527 /* ----------------------------------------------------------------------------
39528    -- SDMAARM - Register accessor macros
39529    ---------------------------------------------------------------------------- */
39530 
39531 /*!
39532  * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros
39533  * @{
39534  */
39535 
39536 
39537 /* SDMAARM - Register instance definitions */
39538 /* SDMAARM */
39539 #define SDMAARM_MC0PTR                           SDMAARM_MC0PTR_REG(SDMAARM_BASE_PTR)
39540 #define SDMAARM_INTR                             SDMAARM_INTR_REG(SDMAARM_BASE_PTR)
39541 #define SDMAARM_STOP_STAT                        SDMAARM_STOP_STAT_REG(SDMAARM_BASE_PTR)
39542 #define SDMAARM_HSTART                           SDMAARM_HSTART_REG(SDMAARM_BASE_PTR)
39543 #define SDMAARM_EVTOVR                           SDMAARM_EVTOVR_REG(SDMAARM_BASE_PTR)
39544 #define SDMAARM_DSPOVR                           SDMAARM_DSPOVR_REG(SDMAARM_BASE_PTR)
39545 #define SDMAARM_HOSTOVR                          SDMAARM_HOSTOVR_REG(SDMAARM_BASE_PTR)
39546 #define SDMAARM_EVTPEND                          SDMAARM_EVTPEND_REG(SDMAARM_BASE_PTR)
39547 #define SDMAARM_RESET                            SDMAARM_RESET_REG(SDMAARM_BASE_PTR)
39548 #define SDMAARM_EVTERR                           SDMAARM_EVTERR_REG(SDMAARM_BASE_PTR)
39549 #define SDMAARM_INTRMASK                         SDMAARM_INTRMASK_REG(SDMAARM_BASE_PTR)
39550 #define SDMAARM_PSW                              SDMAARM_PSW_REG(SDMAARM_BASE_PTR)
39551 #define SDMAARM_EVTERRDBG                        SDMAARM_EVTERRDBG_REG(SDMAARM_BASE_PTR)
39552 #define SDMAARM_CONFIG                           SDMAARM_CONFIG_REG(SDMAARM_BASE_PTR)
39553 #define SDMAARM_SDMA_LOCK                        SDMAARM_SDMA_LOCK_REG(SDMAARM_BASE_PTR)
39554 #define SDMAARM_ONCE_ENB                         SDMAARM_ONCE_ENB_REG(SDMAARM_BASE_PTR)
39555 #define SDMAARM_ONCE_DATA                        SDMAARM_ONCE_DATA_REG(SDMAARM_BASE_PTR)
39556 #define SDMAARM_ONCE_INSTR                       SDMAARM_ONCE_INSTR_REG(SDMAARM_BASE_PTR)
39557 #define SDMAARM_ONCE_STAT                        SDMAARM_ONCE_STAT_REG(SDMAARM_BASE_PTR)
39558 #define SDMAARM_ONCE_CMD                         SDMAARM_ONCE_CMD_REG(SDMAARM_BASE_PTR)
39559 #define SDMAARM_ILLINSTADDR                      SDMAARM_ILLINSTADDR_REG(SDMAARM_BASE_PTR)
39560 #define SDMAARM_CHN0ADDR                         SDMAARM_CHN0ADDR_REG(SDMAARM_BASE_PTR)
39561 #define SDMAARM_EVT_MIRROR                       SDMAARM_EVT_MIRROR_REG(SDMAARM_BASE_PTR)
39562 #define SDMAARM_EVT_MIRROR2                      SDMAARM_EVT_MIRROR2_REG(SDMAARM_BASE_PTR)
39563 #define SDMAARM_XTRIG_CONF1                      SDMAARM_XTRIG_CONF1_REG(SDMAARM_BASE_PTR)
39564 #define SDMAARM_XTRIG_CONF2                      SDMAARM_XTRIG_CONF2_REG(SDMAARM_BASE_PTR)
39565 #define SDMAARM_SDMA_CHNPRI0                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,0)
39566 #define SDMAARM_SDMA_CHNPRI1                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,1)
39567 #define SDMAARM_SDMA_CHNPRI2                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,2)
39568 #define SDMAARM_SDMA_CHNPRI3                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,3)
39569 #define SDMAARM_SDMA_CHNPRI4                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,4)
39570 #define SDMAARM_SDMA_CHNPRI5                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,5)
39571 #define SDMAARM_SDMA_CHNPRI6                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,6)
39572 #define SDMAARM_SDMA_CHNPRI7                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,7)
39573 #define SDMAARM_SDMA_CHNPRI8                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,8)
39574 #define SDMAARM_SDMA_CHNPRI9                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,9)
39575 #define SDMAARM_SDMA_CHNPRI10                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,10)
39576 #define SDMAARM_SDMA_CHNPRI11                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,11)
39577 #define SDMAARM_SDMA_CHNPRI12                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,12)
39578 #define SDMAARM_SDMA_CHNPRI13                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,13)
39579 #define SDMAARM_SDMA_CHNPRI14                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,14)
39580 #define SDMAARM_SDMA_CHNPRI15                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,15)
39581 #define SDMAARM_SDMA_CHNPRI16                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,16)
39582 #define SDMAARM_SDMA_CHNPRI17                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,17)
39583 #define SDMAARM_SDMA_CHNPRI18                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,18)
39584 #define SDMAARM_SDMA_CHNPRI19                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,19)
39585 #define SDMAARM_SDMA_CHNPRI20                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,20)
39586 #define SDMAARM_SDMA_CHNPRI21                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,21)
39587 #define SDMAARM_SDMA_CHNPRI22                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,22)
39588 #define SDMAARM_SDMA_CHNPRI23                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,23)
39589 #define SDMAARM_SDMA_CHNPRI24                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,24)
39590 #define SDMAARM_SDMA_CHNPRI25                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,25)
39591 #define SDMAARM_SDMA_CHNPRI26                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,26)
39592 #define SDMAARM_SDMA_CHNPRI27                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,27)
39593 #define SDMAARM_SDMA_CHNPRI28                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,28)
39594 #define SDMAARM_SDMA_CHNPRI29                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,29)
39595 #define SDMAARM_SDMA_CHNPRI30                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,30)
39596 #define SDMAARM_SDMA_CHNPRI31                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,31)
39597 #define SDMAARM_CHNENBL0                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,0)
39598 #define SDMAARM_CHNENBL1                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,1)
39599 #define SDMAARM_CHNENBL2                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,2)
39600 #define SDMAARM_CHNENBL3                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,3)
39601 #define SDMAARM_CHNENBL4                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,4)
39602 #define SDMAARM_CHNENBL5                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,5)
39603 #define SDMAARM_CHNENBL6                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,6)
39604 #define SDMAARM_CHNENBL7                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,7)
39605 #define SDMAARM_CHNENBL8                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,8)
39606 #define SDMAARM_CHNENBL9                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,9)
39607 #define SDMAARM_CHNENBL10                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,10)
39608 #define SDMAARM_CHNENBL11                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,11)
39609 #define SDMAARM_CHNENBL12                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,12)
39610 #define SDMAARM_CHNENBL13                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,13)
39611 #define SDMAARM_CHNENBL14                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,14)
39612 #define SDMAARM_CHNENBL15                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,15)
39613 #define SDMAARM_CHNENBL16                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,16)
39614 #define SDMAARM_CHNENBL17                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,17)
39615 #define SDMAARM_CHNENBL18                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,18)
39616 #define SDMAARM_CHNENBL19                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,19)
39617 #define SDMAARM_CHNENBL20                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,20)
39618 #define SDMAARM_CHNENBL21                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,21)
39619 #define SDMAARM_CHNENBL22                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,22)
39620 #define SDMAARM_CHNENBL23                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,23)
39621 #define SDMAARM_CHNENBL24                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,24)
39622 #define SDMAARM_CHNENBL25                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,25)
39623 #define SDMAARM_CHNENBL26                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,26)
39624 #define SDMAARM_CHNENBL27                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,27)
39625 #define SDMAARM_CHNENBL28                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,28)
39626 #define SDMAARM_CHNENBL29                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,29)
39627 #define SDMAARM_CHNENBL30                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,30)
39628 #define SDMAARM_CHNENBL31                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,31)
39629 #define SDMAARM_CHNENBL32                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,32)
39630 #define SDMAARM_CHNENBL33                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,33)
39631 #define SDMAARM_CHNENBL34                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,34)
39632 #define SDMAARM_CHNENBL35                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,35)
39633 #define SDMAARM_CHNENBL36                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,36)
39634 #define SDMAARM_CHNENBL37                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,37)
39635 #define SDMAARM_CHNENBL38                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,38)
39636 #define SDMAARM_CHNENBL39                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,39)
39637 #define SDMAARM_CHNENBL40                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,40)
39638 #define SDMAARM_CHNENBL41                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,41)
39639 #define SDMAARM_CHNENBL42                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,42)
39640 #define SDMAARM_CHNENBL43                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,43)
39641 #define SDMAARM_CHNENBL44                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,44)
39642 #define SDMAARM_CHNENBL45                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,45)
39643 #define SDMAARM_CHNENBL46                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,46)
39644 #define SDMAARM_CHNENBL47                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,47)
39645 /* SDMAARM - Register array accessors */
39646 #define SDMAARM_SDMA_CHNPRI(index)               SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,index)
39647 #define SDMAARM_CHNENBL(index)                   SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,index)
39648 /*!
39649  * @}
39650  */ /* end of group SDMAARM_Register_Accessor_Macros */
39651 
39652 
39653 /*!
39654  * @}
39655  */ /* end of group SDMAARM_Peripheral */
39656 
39657 /* ----------------------------------------------------------------------------
39658    -- SEMA4 Peripheral Access Layer
39659    ---------------------------------------------------------------------------- */
39660 
39661 /*!
39662  * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
39663  * @{
39664  */
39665 
39666 /** SEMA4 - Register Layout Typedef */
39667 typedef struct {
39668   __IO  uint8_t  GATE00;                                 /**< Semaphores Gate 3 Register, offset: 0x0 */
39669   __IO  uint8_t  GATE01;                                 /**< Semaphores Gate 2 Register, offset: 0x1 */
39670   __IO  uint8_t  GATE02;                                 /**< Semaphores Gate 1 Register, offset: 0x2 */
39671   __IO  uint8_t  GATE03;                                 /**< Semaphores Gate 0 Register, offset: 0x3 */
39672   __IO  uint8_t  GATE04;                                 /**< Semaphores Gate 7 Register, offset: 0x4 */
39673   __IO  uint8_t  GATE05;                                 /**< Semaphores Gate 6 Register, offset: 0x5 */
39674   __IO  uint8_t  GATE06;                                 /**< Semaphores Gate 5 Register, offset: 0x6 */
39675   __IO  uint8_t  GATE07;                                 /**< Semaphores Gate 4 Register, offset: 0x7 */
39676   __IO  uint8_t  GATE08;                                 /**< Semaphores Gate 11 Register, offset: 0x8 */
39677   __IO  uint8_t  GATE09;                                 /**< Semaphores Gate 10 Register, offset: 0x9 */
39678   __IO  uint8_t  GATE10;                                 /**< Semaphores Gate 9 Register, offset: 0xA */
39679   __IO  uint8_t  GATE11;                                 /**< Semaphores Gate 8 Register, offset: 0xB */
39680   __IO  uint8_t  GATE12;                                 /**< Semaphores Gate 15 Register, offset: 0xC */
39681   __IO  uint8_t  GATE13;                                 /**< Semaphores Gate 14 Register, offset: 0xD */
39682   __IO  uint8_t  GATE14;                                 /**< Semaphores Gate 13 Register, offset: 0xE */
39683   __IO  uint8_t  GATE15;                                 /**< Semaphores Gate 12 Register, offset: 0xF */
39684   uint8_t RESERVED_0[48];
39685   struct {                                         /* offset: 0x40, array step: 0x8 */
39686     __IO  uint16_t INE;                                    /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
39687   uint8_t RESERVED_0[6];
39688   } CPnINE[2];
39689   uint8_t RESERVED_1[48];
39690   struct {                                         /* offset: 0x80, array step: 0x8 */
39691     __I   uint16_t NTF;                                    /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
39692   uint8_t RESERVED_0[6];
39693   } CPnNTF[2];
39694   uint8_t RESERVED_2[112];
39695   __IO  uint16_t RSTGT;                                  /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
39696   uint8_t RESERVED_3[2];
39697   __IO  uint16_t RSTNTF;                                 /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
39698 } SEMA4_Type, *SEMA4_MemMapPtr;
39699 /* ----------------------------------------------------------------------------
39700    -- SEMA4 - Register accessor macros
39701    ---------------------------------------------------------------------------- */
39702 
39703 /*!
39704  * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros
39705  * @{
39706  */
39707 
39708 
39709 /* SEMA4 - Register accessors */
39710 #define SEMA4_GATE00_REG(base)                   ((base)->GATE00)
39711 #define SEMA4_GATE01_REG(base)                   ((base)->GATE01)
39712 #define SEMA4_GATE02_REG(base)                   ((base)->GATE02)
39713 #define SEMA4_GATE03_REG(base)                   ((base)->GATE03)
39714 #define SEMA4_GATE04_REG(base)                   ((base)->GATE04)
39715 #define SEMA4_GATE05_REG(base)                   ((base)->GATE05)
39716 #define SEMA4_GATE06_REG(base)                   ((base)->GATE06)
39717 #define SEMA4_GATE07_REG(base)                   ((base)->GATE07)
39718 #define SEMA4_GATE08_REG(base)                   ((base)->GATE08)
39719 #define SEMA4_GATE09_REG(base)                   ((base)->GATE09)
39720 #define SEMA4_GATE10_REG(base)                   ((base)->GATE10)
39721 #define SEMA4_GATE11_REG(base)                   ((base)->GATE11)
39722 #define SEMA4_GATE12_REG(base)                   ((base)->GATE12)
39723 #define SEMA4_GATE13_REG(base)                   ((base)->GATE13)
39724 #define SEMA4_GATE14_REG(base)                   ((base)->GATE14)
39725 #define SEMA4_GATE15_REG(base)                   ((base)->GATE15)
39726 #define SEMA4_CPINE_REG(base,index)              ((base)->CPnINE[index].INE)
39727 #define SEMA4_CPNTF_REG(base,index)              ((base)->CPnNTF[index].NTF)
39728 #define SEMA4_RSTGT_REG(base)                    ((base)->RSTGT)
39729 #define SEMA4_RSTNTF_REG(base)                   ((base)->RSTNTF)
39730 
39731 /*!
39732  * @}
39733  */ /* end of group SEMA4_Register_Accessor_Macros */
39734 /* ----------------------------------------------------------------------------
39735    -- SEMA4 Register Masks
39736    ---------------------------------------------------------------------------- */
39737 
39738 /*!
39739  * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
39740  * @{
39741  */
39742 
39743 /* GATE00 Bit Fields */
39744 #define SEMA4_GATE00_GTFSM_MASK                  0x3u
39745 #define SEMA4_GATE00_GTFSM_SHIFT                 0
39746 #define SEMA4_GATE00_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE00_GTFSM_SHIFT))&SEMA4_GATE00_GTFSM_MASK)
39747 /* GATE01 Bit Fields */
39748 #define SEMA4_GATE01_GTFSM_MASK                  0x3u
39749 #define SEMA4_GATE01_GTFSM_SHIFT                 0
39750 #define SEMA4_GATE01_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE01_GTFSM_SHIFT))&SEMA4_GATE01_GTFSM_MASK)
39751 /* GATE02 Bit Fields */
39752 #define SEMA4_GATE02_GTFSM_MASK                  0x3u
39753 #define SEMA4_GATE02_GTFSM_SHIFT                 0
39754 #define SEMA4_GATE02_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE02_GTFSM_SHIFT))&SEMA4_GATE02_GTFSM_MASK)
39755 /* GATE03 Bit Fields */
39756 #define SEMA4_GATE03_GTFSM_MASK                  0x3u
39757 #define SEMA4_GATE03_GTFSM_SHIFT                 0
39758 #define SEMA4_GATE03_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE03_GTFSM_SHIFT))&SEMA4_GATE03_GTFSM_MASK)
39759 /* GATE04 Bit Fields */
39760 #define SEMA4_GATE04_GTFSM_MASK                  0x3u
39761 #define SEMA4_GATE04_GTFSM_SHIFT                 0
39762 #define SEMA4_GATE04_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE04_GTFSM_SHIFT))&SEMA4_GATE04_GTFSM_MASK)
39763 /* GATE05 Bit Fields */
39764 #define SEMA4_GATE05_GTFSM_MASK                  0x3u
39765 #define SEMA4_GATE05_GTFSM_SHIFT                 0
39766 #define SEMA4_GATE05_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE05_GTFSM_SHIFT))&SEMA4_GATE05_GTFSM_MASK)
39767 /* GATE06 Bit Fields */
39768 #define SEMA4_GATE06_GTFSM_MASK                  0x3u
39769 #define SEMA4_GATE06_GTFSM_SHIFT                 0
39770 #define SEMA4_GATE06_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE06_GTFSM_SHIFT))&SEMA4_GATE06_GTFSM_MASK)
39771 /* GATE07 Bit Fields */
39772 #define SEMA4_GATE07_GTFSM_MASK                  0x3u
39773 #define SEMA4_GATE07_GTFSM_SHIFT                 0
39774 #define SEMA4_GATE07_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE07_GTFSM_SHIFT))&SEMA4_GATE07_GTFSM_MASK)
39775 /* GATE08 Bit Fields */
39776 #define SEMA4_GATE08_GTFSM_MASK                  0x3u
39777 #define SEMA4_GATE08_GTFSM_SHIFT                 0
39778 #define SEMA4_GATE08_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE08_GTFSM_SHIFT))&SEMA4_GATE08_GTFSM_MASK)
39779 /* GATE09 Bit Fields */
39780 #define SEMA4_GATE09_GTFSM_MASK                  0x3u
39781 #define SEMA4_GATE09_GTFSM_SHIFT                 0
39782 #define SEMA4_GATE09_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE09_GTFSM_SHIFT))&SEMA4_GATE09_GTFSM_MASK)
39783 /* GATE10 Bit Fields */
39784 #define SEMA4_GATE10_GTFSM_MASK                  0x3u
39785 #define SEMA4_GATE10_GTFSM_SHIFT                 0
39786 #define SEMA4_GATE10_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE10_GTFSM_SHIFT))&SEMA4_GATE10_GTFSM_MASK)
39787 /* GATE11 Bit Fields */
39788 #define SEMA4_GATE11_GTFSM_MASK                  0x3u
39789 #define SEMA4_GATE11_GTFSM_SHIFT                 0
39790 #define SEMA4_GATE11_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE11_GTFSM_SHIFT))&SEMA4_GATE11_GTFSM_MASK)
39791 /* GATE12 Bit Fields */
39792 #define SEMA4_GATE12_GTFSM_MASK                  0x3u
39793 #define SEMA4_GATE12_GTFSM_SHIFT                 0
39794 #define SEMA4_GATE12_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE12_GTFSM_SHIFT))&SEMA4_GATE12_GTFSM_MASK)
39795 /* GATE13 Bit Fields */
39796 #define SEMA4_GATE13_GTFSM_MASK                  0x3u
39797 #define SEMA4_GATE13_GTFSM_SHIFT                 0
39798 #define SEMA4_GATE13_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE13_GTFSM_SHIFT))&SEMA4_GATE13_GTFSM_MASK)
39799 /* GATE14 Bit Fields */
39800 #define SEMA4_GATE14_GTFSM_MASK                  0x3u
39801 #define SEMA4_GATE14_GTFSM_SHIFT                 0
39802 #define SEMA4_GATE14_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE14_GTFSM_SHIFT))&SEMA4_GATE14_GTFSM_MASK)
39803 /* GATE15 Bit Fields */
39804 #define SEMA4_GATE15_GTFSM_MASK                  0x3u
39805 #define SEMA4_GATE15_GTFSM_SHIFT                 0
39806 #define SEMA4_GATE15_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE15_GTFSM_SHIFT))&SEMA4_GATE15_GTFSM_MASK)
39807 /* CPINE Bit Fields */
39808 #define SEMA4_CPINE_INE7_MASK                    0x1u
39809 #define SEMA4_CPINE_INE7_SHIFT                   0
39810 #define SEMA4_CPINE_INE6_MASK                    0x2u
39811 #define SEMA4_CPINE_INE6_SHIFT                   1
39812 #define SEMA4_CPINE_INE5_MASK                    0x4u
39813 #define SEMA4_CPINE_INE5_SHIFT                   2
39814 #define SEMA4_CPINE_INE4_MASK                    0x8u
39815 #define SEMA4_CPINE_INE4_SHIFT                   3
39816 #define SEMA4_CPINE_INE3_MASK                    0x10u
39817 #define SEMA4_CPINE_INE3_SHIFT                   4
39818 #define SEMA4_CPINE_INE2_MASK                    0x20u
39819 #define SEMA4_CPINE_INE2_SHIFT                   5
39820 #define SEMA4_CPINE_INE1_MASK                    0x40u
39821 #define SEMA4_CPINE_INE1_SHIFT                   6
39822 #define SEMA4_CPINE_INE0_MASK                    0x80u
39823 #define SEMA4_CPINE_INE0_SHIFT                   7
39824 #define SEMA4_CPINE_INE15_MASK                   0x100u
39825 #define SEMA4_CPINE_INE15_SHIFT                  8
39826 #define SEMA4_CPINE_INE14_MASK                   0x200u
39827 #define SEMA4_CPINE_INE14_SHIFT                  9
39828 #define SEMA4_CPINE_INE13_MASK                   0x400u
39829 #define SEMA4_CPINE_INE13_SHIFT                  10
39830 #define SEMA4_CPINE_INE12_MASK                   0x800u
39831 #define SEMA4_CPINE_INE12_SHIFT                  11
39832 #define SEMA4_CPINE_INE11_MASK                   0x1000u
39833 #define SEMA4_CPINE_INE11_SHIFT                  12
39834 #define SEMA4_CPINE_INE10_MASK                   0x2000u
39835 #define SEMA4_CPINE_INE10_SHIFT                  13
39836 #define SEMA4_CPINE_INE9_MASK                    0x4000u
39837 #define SEMA4_CPINE_INE9_SHIFT                   14
39838 #define SEMA4_CPINE_INE8_MASK                    0x8000u
39839 #define SEMA4_CPINE_INE8_SHIFT                   15
39840 /* CPNTF Bit Fields */
39841 #define SEMA4_CPNTF_GN7_MASK                     0x1u
39842 #define SEMA4_CPNTF_GN7_SHIFT                    0
39843 #define SEMA4_CPNTF_GN6_MASK                     0x2u
39844 #define SEMA4_CPNTF_GN6_SHIFT                    1
39845 #define SEMA4_CPNTF_GN5_MASK                     0x4u
39846 #define SEMA4_CPNTF_GN5_SHIFT                    2
39847 #define SEMA4_CPNTF_GN4_MASK                     0x8u
39848 #define SEMA4_CPNTF_GN4_SHIFT                    3
39849 #define SEMA4_CPNTF_GN3_MASK                     0x10u
39850 #define SEMA4_CPNTF_GN3_SHIFT                    4
39851 #define SEMA4_CPNTF_GN2_MASK                     0x20u
39852 #define SEMA4_CPNTF_GN2_SHIFT                    5
39853 #define SEMA4_CPNTF_GN1_MASK                     0x40u
39854 #define SEMA4_CPNTF_GN1_SHIFT                    6
39855 #define SEMA4_CPNTF_GN0_MASK                     0x80u
39856 #define SEMA4_CPNTF_GN0_SHIFT                    7
39857 #define SEMA4_CPNTF_GN15_MASK                    0x100u
39858 #define SEMA4_CPNTF_GN15_SHIFT                   8
39859 #define SEMA4_CPNTF_GN14_MASK                    0x200u
39860 #define SEMA4_CPNTF_GN14_SHIFT                   9
39861 #define SEMA4_CPNTF_GN13_MASK                    0x400u
39862 #define SEMA4_CPNTF_GN13_SHIFT                   10
39863 #define SEMA4_CPNTF_GN12_MASK                    0x800u
39864 #define SEMA4_CPNTF_GN12_SHIFT                   11
39865 #define SEMA4_CPNTF_GN11_MASK                    0x1000u
39866 #define SEMA4_CPNTF_GN11_SHIFT                   12
39867 #define SEMA4_CPNTF_GN10_MASK                    0x2000u
39868 #define SEMA4_CPNTF_GN10_SHIFT                   13
39869 #define SEMA4_CPNTF_GN9_MASK                     0x4000u
39870 #define SEMA4_CPNTF_GN9_SHIFT                    14
39871 #define SEMA4_CPNTF_GN8_MASK                     0x8000u
39872 #define SEMA4_CPNTF_GN8_SHIFT                    15
39873 /* RSTGT Bit Fields */
39874 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    0xFFu
39875 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   0
39876 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT))&SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
39877 #define SEMA4_RSTGT_RSTGTN_MASK                  0xFF00u
39878 #define SEMA4_RSTGT_RSTGTN_SHIFT                 8
39879 #define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGTN_SHIFT))&SEMA4_RSTGT_RSTGTN_MASK)
39880 /* RSTNTF Bit Fields */
39881 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   0xFFu
39882 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  0
39883 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT))&SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
39884 #define SEMA4_RSTNTF_RSTNTN_MASK                 0xFF00u
39885 #define SEMA4_RSTNTF_RSTNTN_SHIFT                8
39886 #define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNTN_SHIFT))&SEMA4_RSTNTF_RSTNTN_MASK)
39887 
39888 /*!
39889  * @}
39890  */ /* end of group SEMA4_Register_Masks */
39891 
39892 /* SEMA4 - Peripheral instance base addresses */
39893 /** Peripheral SEMA4 base address */
39894 #define SEMA4_BASE                               (0x30AC0000u)
39895 /** Peripheral SEMA4 base pointer */
39896 #define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
39897 #define SEMA4_BASE_PTR                           (SEMA4)
39898 /** Array initializer of SEMA4 peripheral base addresses */
39899 #define SEMA4_BASE_ADDRS                         { SEMA4_BASE }
39900 /** Array initializer of SEMA4 peripheral base pointers */
39901 #define SEMA4_BASE_PTRS                          { SEMA4 }
39902 /** Interrupt vectors for the SEMA4 peripheral type */
39903 #define SEMA4_IRQS                               { SEMA4_HS_M4_IRQn }
39904 /* ----------------------------------------------------------------------------
39905    -- SEMA4 - Register accessor macros
39906    ---------------------------------------------------------------------------- */
39907 
39908 /*!
39909  * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros
39910  * @{
39911  */
39912 
39913 
39914 /* SEMA4 - Register instance definitions */
39915 /* SEMA4 */
39916 #define SEMA4_GATE00                             SEMA4_GATE00_REG(SEMA4_BASE_PTR)
39917 #define SEMA4_GATE01                             SEMA4_GATE01_REG(SEMA4_BASE_PTR)
39918 #define SEMA4_GATE02                             SEMA4_GATE02_REG(SEMA4_BASE_PTR)
39919 #define SEMA4_GATE03                             SEMA4_GATE03_REG(SEMA4_BASE_PTR)
39920 #define SEMA4_GATE04                             SEMA4_GATE04_REG(SEMA4_BASE_PTR)
39921 #define SEMA4_GATE05                             SEMA4_GATE05_REG(SEMA4_BASE_PTR)
39922 #define SEMA4_GATE06                             SEMA4_GATE06_REG(SEMA4_BASE_PTR)
39923 #define SEMA4_GATE07                             SEMA4_GATE07_REG(SEMA4_BASE_PTR)
39924 #define SEMA4_GATE08                             SEMA4_GATE08_REG(SEMA4_BASE_PTR)
39925 #define SEMA4_GATE09                             SEMA4_GATE09_REG(SEMA4_BASE_PTR)
39926 #define SEMA4_GATE10                             SEMA4_GATE10_REG(SEMA4_BASE_PTR)
39927 #define SEMA4_GATE11                             SEMA4_GATE11_REG(SEMA4_BASE_PTR)
39928 #define SEMA4_GATE12                             SEMA4_GATE12_REG(SEMA4_BASE_PTR)
39929 #define SEMA4_GATE13                             SEMA4_GATE13_REG(SEMA4_BASE_PTR)
39930 #define SEMA4_GATE14                             SEMA4_GATE14_REG(SEMA4_BASE_PTR)
39931 #define SEMA4_GATE15                             SEMA4_GATE15_REG(SEMA4_BASE_PTR)
39932 #define SEMA4_CP0INE                             SEMA4_CPINE_REG(SEMA4_BASE_PTR,0)
39933 #define SEMA4_CP1INE                             SEMA4_CPINE_REG(SEMA4_BASE_PTR,1)
39934 #define SEMA4_CP0NTF                             SEMA4_CPNTF_REG(SEMA4_BASE_PTR,0)
39935 #define SEMA4_CP1NTF                             SEMA4_CPNTF_REG(SEMA4_BASE_PTR,1)
39936 #define SEMA4_RSTGT                              SEMA4_RSTGT_REG(SEMA4_BASE_PTR)
39937 #define SEMA4_RSTNTF                             SEMA4_RSTNTF_REG(SEMA4_BASE_PTR)
39938 /* SEMA4 - Register array accessors */
39939 #define SEMA4_CPINE(index)                       SEMA4_CPINE_REG(SEMA4_BASE_PTR,index)
39940 #define SEMA4_CPNTF(index)                       SEMA4_CPNTF_REG(SEMA4_BASE_PTR,index)
39941 /*!
39942  * @}
39943  */ /* end of group SEMA4_Register_Accessor_Macros */
39944 
39945 
39946 /*!
39947  * @}
39948  */ /* end of group SEMA4_Peripheral */
39949 
39950 /* ----------------------------------------------------------------------------
39951    -- SJC Peripheral Access Layer
39952    ---------------------------------------------------------------------------- */
39953 
39954 /*!
39955  * @addtogroup SJC_Peripheral_Access_Layer SJC Peripheral Access Layer
39956  * @{
39957  */
39958 
39959 /** SJC - Register Layout Typedef */
39960 typedef struct {
39961   union {                                          /* offset: 0x0 */
39962   __I     uint32_t GPUSR1;                                      /**< General Purpose Unsecured Status Register 1,offset: 0x0 */
39963   struct {                                         /* offset: 0x1 */
39964       uint8_t RESERVED_0[1];
39965   __I     uint32_t GPUSR2;                                      /**< General Purpose Unsecured Status Register 2,offset: 0x1 */
39966     } GPUSR2;
39967   struct {                                         /* offset: 0x2 */
39968       uint8_t RESERVED_0[2];
39969   __I     uint32_t GPUSR3;                                      /**< General Purpose Unsecured Status Register 3,offset: 0x2 */
39970     } GPUSR3;
39971   struct {                                         /* offset: 0x3 */
39972       uint8_t RESERVED_0[3];
39973   __I     uint32_t GPSSR;                                       /**< General Purpose Secured Status Register,offset: 0x3 */
39974     } GPSSR;
39975   struct {                                         /* offset: 0x4 */
39976       uint8_t RESERVED_0[4];
39977   __IO    uint32_t DCR;                                         /**< Debug Control Register,offset: 0x4 */
39978     } DCR;
39979   struct {                                         /* offset: 0x5 */
39980       uint8_t RESERVED_0[5];
39981   __I     uint32_t SSR;                                         /**< Security Status Register,offset: 0x5 */
39982     } SSR;
39983   struct {                                         /* offset: 0x7 */
39984       uint8_t RESERVED_0[7];
39985   __IO    uint32_t GPCCR;                                       /**< General Purpose Clocks Control Register,offset: 0x7 */
39986     } GPCCR;
39987   };
39988 } SJC_Type, *SJC_MemMapPtr;
39989 /* ----------------------------------------------------------------------------
39990    -- SJC - Register accessor macros
39991    ---------------------------------------------------------------------------- */
39992 
39993 /*!
39994  * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros
39995  * @{
39996  */
39997 
39998 
39999 /* SJC - Register accessors */
40000 #define SJC_GPUSR1_REG(base)                     ((base)->GPUSR1)
40001 #define SJC_GPUSR2_REG(base)                     ((base)->GPUSR2.GPUSR2)
40002 #define SJC_GPUSR3_REG(base)                     ((base)->GPUSR3.GPUSR3)
40003 #define SJC_GPSSR_REG(base)                      ((base)->GPSSR.GPSSR)
40004 #define SJC_DCR_REG(base)                        ((base)->DCR.DCR)
40005 #define SJC_SSR_REG(base)                        ((base)->SSR.SSR)
40006 #define SJC_GPCCR_REG(base)                      ((base)->GPCCR.GPCCR)
40007 
40008 /*!
40009  * @}
40010  */ /* end of group SJC_Register_Accessor_Macros */
40011 /* ----------------------------------------------------------------------------
40012    -- SJC Register Masks
40013    ---------------------------------------------------------------------------- */
40014 
40015 /*!
40016  * @addtogroup SJC_Register_Masks SJC Register Masks
40017  * @{
40018  */
40019 
40020 /* GPUSR1 Bit Fields */
40021 #define SJC_GPUSR1_A_DBG_MASK                    0x1u
40022 #define SJC_GPUSR1_A_DBG_SHIFT                   0
40023 #define SJC_GPUSR1_A_WFI_MASK                    0x2u
40024 #define SJC_GPUSR1_A_WFI_SHIFT                   1
40025 #define SJC_GPUSR1_S_STAT_MASK                   0x1Cu
40026 #define SJC_GPUSR1_S_STAT_SHIFT                  2
40027 #define SJC_GPUSR1_S_STAT(x)                     (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR1_S_STAT_SHIFT))&SJC_GPUSR1_S_STAT_MASK)
40028 #define SJC_GPUSR1_PLL_LOCK_MASK                 0x100u
40029 #define SJC_GPUSR1_PLL_LOCK_SHIFT                8
40030 /* GPUSR2 Bit Fields */
40031 #define SJC_GPUSR2_STBYWFI_MASK                  0xFu
40032 #define SJC_GPUSR2_STBYWFI_SHIFT                 0
40033 #define SJC_GPUSR2_STBYWFI(x)                    (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFI_SHIFT))&SJC_GPUSR2_STBYWFI_MASK)
40034 #define SJC_GPUSR2_S_STAT_MASK                   0xF0u
40035 #define SJC_GPUSR2_S_STAT_SHIFT                  4
40036 #define SJC_GPUSR2_S_STAT(x)                     (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_S_STAT_SHIFT))&SJC_GPUSR2_S_STAT_MASK)
40037 #define SJC_GPUSR2_STBYWFE_MASK                  0xF00u
40038 #define SJC_GPUSR2_STBYWFE_SHIFT                 8
40039 #define SJC_GPUSR2_STBYWFE(x)                    (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFE_SHIFT))&SJC_GPUSR2_STBYWFE_MASK)
40040 /* GPUSR3 Bit Fields */
40041 #define SJC_GPUSR3_IPG_WAIT_MASK                 0x1u
40042 #define SJC_GPUSR3_IPG_WAIT_SHIFT                0
40043 #define SJC_GPUSR3_IPG_STOP_MASK                 0x2u
40044 #define SJC_GPUSR3_IPG_STOP_SHIFT                1
40045 #define SJC_GPUSR3_SYS_WAIT_MASK                 0x4u
40046 #define SJC_GPUSR3_SYS_WAIT_SHIFT                2
40047 /* GPSSR Bit Fields */
40048 #define SJC_GPSSR_GPSSR_MASK                     0xFFFFFFFFu
40049 #define SJC_GPSSR_GPSSR_SHIFT                    0
40050 #define SJC_GPSSR_GPSSR(x)                       (((uint32_t)(((uint32_t)(x))<<SJC_GPSSR_GPSSR_SHIFT))&SJC_GPSSR_GPSSR_MASK)
40051 /* DCR Bit Fields */
40052 #define SJC_DCR_DE_TO_ARM_MASK                   0x1u
40053 #define SJC_DCR_DE_TO_ARM_SHIFT                  0
40054 #define SJC_DCR_DE_TO_SDMA_MASK                  0x2u
40055 #define SJC_DCR_DE_TO_SDMA_SHIFT                 1
40056 #define SJC_DCR_DEBUG_OBS_MASK                   0x8u
40057 #define SJC_DCR_DEBUG_OBS_SHIFT                  3
40058 #define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK          0x20u
40059 #define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT         5
40060 #define SJC_DCR_DIRECT_ARM_REQ_EN_MASK           0x40u
40061 #define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT          6
40062 /* SSR Bit Fields */
40063 #define SJC_SSR_KTF_MASK                         0x1u
40064 #define SJC_SSR_KTF_SHIFT                        0
40065 #define SJC_SSR_KTA_MASK                         0x2u
40066 #define SJC_SSR_KTA_SHIFT                        1
40067 #define SJC_SSR_SWF_MASK                         0x4u
40068 #define SJC_SSR_SWF_SHIFT                        2
40069 #define SJC_SSR_SWE_MASK                         0x8u
40070 #define SJC_SSR_SWE_SHIFT                        3
40071 #define SJC_SSR_EBF_MASK                         0x10u
40072 #define SJC_SSR_EBF_SHIFT                        4
40073 #define SJC_SSR_EBG_MASK                         0x20u
40074 #define SJC_SSR_EBG_SHIFT                        5
40075 #define SJC_SSR_FT_MASK                          0x100u
40076 #define SJC_SSR_FT_SHIFT                         8
40077 #define SJC_SSR_SJM_MASK                         0x600u
40078 #define SJC_SSR_SJM_SHIFT                        9
40079 #define SJC_SSR_SJM(x)                           (((uint32_t)(((uint32_t)(x))<<SJC_SSR_SJM_SHIFT))&SJC_SSR_SJM_MASK)
40080 #define SJC_SSR_RSSTAT_MASK                      0x1800u
40081 #define SJC_SSR_RSSTAT_SHIFT                     11
40082 #define SJC_SSR_RSSTAT(x)                        (((uint32_t)(((uint32_t)(x))<<SJC_SSR_RSSTAT_SHIFT))&SJC_SSR_RSSTAT_MASK)
40083 #define SJC_SSR_BOOTIND_MASK                     0x4000u
40084 #define SJC_SSR_BOOTIND_SHIFT                    14
40085 /* GPCCR Bit Fields */
40086 #define SJC_GPCCR_SCLKR_MASK                     0x1u
40087 #define SJC_GPCCR_SCLKR_SHIFT                    0
40088 #define SJC_GPCCR_ACLKOFFDIS_MASK                0x2u
40089 #define SJC_GPCCR_ACLKOFFDIS_SHIFT               1
40090 
40091 /*!
40092  * @}
40093  */ /* end of group SJC_Register_Masks */
40094 
40095 /* SJC - Peripheral instance base addresses */
40096 /** Peripheral SJC base address */
40097 #define SJC_BASE                                 (0x0u)
40098 /** Peripheral SJC base pointer */
40099 #define SJC                                      ((SJC_Type *)SJC_BASE)
40100 #define SJC_BASE_PTR                             (SJC)
40101 /** Array initializer of SJC peripheral base addresses */
40102 #define SJC_BASE_ADDRS                           { SJC_BASE }
40103 /** Array initializer of SJC peripheral base pointers */
40104 #define SJC_BASE_PTRS                            { SJC }
40105 /* ----------------------------------------------------------------------------
40106    -- SJC - Register accessor macros
40107    ---------------------------------------------------------------------------- */
40108 
40109 /*!
40110  * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros
40111  * @{
40112  */
40113 
40114 
40115 /* SJC - Register instance definitions */
40116 /* SJC */
40117 #define SJC_GPUSR1                               SJC_GPUSR1_REG(SJC_BASE_PTR)
40118 #define SJC_GPUSR2                               SJC_GPUSR2_REG(SJC_BASE_PTR)
40119 #define SJC_GPUSR3                               SJC_GPUSR3_REG(SJC_BASE_PTR)
40120 #define SJC_GPSSR                                SJC_GPSSR_REG(SJC_BASE_PTR)
40121 #define SJC_DCR                                  SJC_DCR_REG(SJC_BASE_PTR)
40122 #define SJC_SSR                                  SJC_SSR_REG(SJC_BASE_PTR)
40123 #define SJC_GPCCR                                SJC_GPCCR_REG(SJC_BASE_PTR)
40124 /*!
40125  * @}
40126  */ /* end of group SJC_Register_Accessor_Macros */
40127 
40128 
40129 /*!
40130  * @}
40131  */ /* end of group SJC_Peripheral */
40132 
40133 /* ----------------------------------------------------------------------------
40134    -- SNVS Peripheral Access Layer
40135    ---------------------------------------------------------------------------- */
40136 
40137 /*!
40138  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
40139  * @{
40140  */
40141 
40142 /** SNVS - Register Layout Typedef */
40143 typedef struct {
40144   __IO  uint32_t HPLR;                                   /**<  , offset: 0x0 */
40145   __IO  uint32_t HPCOMR;                                 /**<  , offset: 0x4 */
40146   __IO  uint32_t HPCR;                                   /**<  , offset: 0x8 */
40147   uint8_t RESERVED_0[8];
40148   __IO  uint32_t HPSR;                                   /**<  , offset: 0x14 */
40149   uint8_t RESERVED_1[12];
40150   __IO  uint32_t HPRTCMR;                                /**<  , offset: 0x24 */
40151   __IO  uint32_t HPRTCLR;                                /**<  , offset: 0x28 */
40152   __IO  uint32_t HPTAMR;                                 /**<  , offset: 0x2C */
40153   __IO  uint32_t HPTALR;                                 /**<  , offset: 0x30 */
40154   __IO  uint32_t LPLR;                                   /**<  , offset: 0x34 */
40155   __IO  uint32_t LPCR;                                   /**<  , offset: 0x38 */
40156   uint8_t RESERVED_2[16];
40157   __IO  uint32_t LPSR;                                   /**<  , offset: 0x4C */
40158   uint8_t RESERVED_3[12];
40159   __IO  uint32_t LPSMCMR;                                /**<  , offset: 0x5C */
40160   __IO  uint32_t LPSMCLR;                                /**<  , offset: 0x60 */
40161   uint8_t RESERVED_4[4];
40162   __IO  uint32_t LPGPR;                                  /**<  , offset: 0x68 */
40163   uint8_t RESERVED_5[2956];
40164   __I   uint32_t HPVIDR1;                                /**<  , offset: 0xBF8 */
40165   __I   uint32_t HPVIDR2;                                /**<  , offset: 0xBFC */
40166 } SNVS_Type, *SNVS_MemMapPtr;
40167 /* ----------------------------------------------------------------------------
40168    -- SNVS - Register accessor macros
40169    ---------------------------------------------------------------------------- */
40170 
40171 /*!
40172  * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros
40173  * @{
40174  */
40175 
40176 
40177 /* SNVS - Register accessors */
40178 #define SNVS_HPLR_REG(base)                      ((base)->HPLR)
40179 #define SNVS_HPCOMR_REG(base)                    ((base)->HPCOMR)
40180 #define SNVS_HPCR_REG(base)                      ((base)->HPCR)
40181 #define SNVS_HPSR_REG(base)                      ((base)->HPSR)
40182 #define SNVS_HPRTCMR_REG(base)                   ((base)->HPRTCMR)
40183 #define SNVS_HPRTCLR_REG(base)                   ((base)->HPRTCLR)
40184 #define SNVS_HPTAMR_REG(base)                    ((base)->HPTAMR)
40185 #define SNVS_HPTALR_REG(base)                    ((base)->HPTALR)
40186 #define SNVS_LPLR_REG(base)                      ((base)->LPLR)
40187 #define SNVS_LPCR_REG(base)                      ((base)->LPCR)
40188 #define SNVS_LPSR_REG(base)                      ((base)->LPSR)
40189 #define SNVS_LPSMCMR_REG(base)                   ((base)->LPSMCMR)
40190 #define SNVS_LPSMCLR_REG(base)                   ((base)->LPSMCLR)
40191 #define SNVS_LPGPR_REG(base)                     ((base)->LPGPR)
40192 #define SNVS_HPVIDR1_REG(base)                   ((base)->HPVIDR1)
40193 #define SNVS_HPVIDR2_REG(base)                   ((base)->HPVIDR2)
40194 
40195 /*!
40196  * @}
40197  */ /* end of group SNVS_Register_Accessor_Macros */
40198 /* ----------------------------------------------------------------------------
40199    -- SNVS Register Masks
40200    ---------------------------------------------------------------------------- */
40201 
40202 /*!
40203  * @addtogroup SNVS_Register_Masks SNVS Register Masks
40204  * @{
40205  */
40206 
40207 /* HPLR Bit Fields */
40208 #define SNVS_HPLR_MC_SL_MASK                     0x10u
40209 #define SNVS_HPLR_MC_SL_SHIFT                    4
40210 #define SNVS_HPLR_GPR_SL_MASK                    0x20u
40211 #define SNVS_HPLR_GPR_SL_SHIFT                   5
40212 /* HPCOMR Bit Fields */
40213 #define SNVS_HPCOMR_LP_SWR_MASK                  0x10u
40214 #define SNVS_HPCOMR_LP_SWR_SHIFT                 4
40215 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              0x20u
40216 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             5
40217 #define SNVS_HPCOMR_NPSWA_EN_MASK                0x80000000u
40218 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               31
40219 /* HPCR Bit Fields */
40220 #define SNVS_HPCR_RTC_EN_MASK                    0x1u
40221 #define SNVS_HPCR_RTC_EN_SHIFT                   0
40222 #define SNVS_HPCR_HPTA_EN_MASK                   0x2u
40223 #define SNVS_HPCR_HPTA_EN_SHIFT                  1
40224 #define SNVS_HPCR_PI_EN_MASK                     0x8u
40225 #define SNVS_HPCR_PI_EN_SHIFT                    3
40226 #define SNVS_HPCR_PI_FREQ_MASK                   0xF0u
40227 #define SNVS_HPCR_PI_FREQ_SHIFT                  4
40228 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_PI_FREQ_SHIFT))&SNVS_HPCR_PI_FREQ_MASK)
40229 #define SNVS_HPCR_HPCALB_EN_MASK                 0x100u
40230 #define SNVS_HPCR_HPCALB_EN_SHIFT                8
40231 #define SNVS_HPCR_HPCALB_VAL_MASK                0x7C00u
40232 #define SNVS_HPCR_HPCALB_VAL_SHIFT               10
40233 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_HPCALB_VAL_SHIFT))&SNVS_HPCR_HPCALB_VAL_MASK)
40234 #define SNVS_HPCR_BTN_CONFIG_MASK                0x7000000u
40235 #define SNVS_HPCR_BTN_CONFIG_SHIFT               24
40236 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_BTN_CONFIG_SHIFT))&SNVS_HPCR_BTN_CONFIG_MASK)
40237 #define SNVS_HPCR_BTN_MASK_MASK                  0x8000000u
40238 #define SNVS_HPCR_BTN_MASK_SHIFT                 27
40239 /* HPSR Bit Fields */
40240 #define SNVS_HPSR_BTN_MASK                       0x40u
40241 #define SNVS_HPSR_BTN_SHIFT                      6
40242 #define SNVS_HPSR_BI_MASK                        0x80u
40243 #define SNVS_HPSR_BI_SHIFT                       7
40244 /* HPRTCMR Bit Fields */
40245 #define SNVS_HPRTCMR_RTC_MASK                    0xFFFFFFFFu
40246 #define SNVS_HPRTCMR_RTC_SHIFT                   0
40247 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCMR_RTC_SHIFT))&SNVS_HPRTCMR_RTC_MASK)
40248 /* HPRTCLR Bit Fields */
40249 #define SNVS_HPRTCLR_RTC_MASK                    0xFFFFFFFFu
40250 #define SNVS_HPRTCLR_RTC_SHIFT                   0
40251 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCLR_RTC_SHIFT))&SNVS_HPRTCLR_RTC_MASK)
40252 /* HPTAMR Bit Fields */
40253 #define SNVS_HPTAMR_HPTA_MASK                    0x7FFFu
40254 #define SNVS_HPTAMR_HPTA_SHIFT                   0
40255 #define SNVS_HPTAMR_HPTA(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPTAMR_HPTA_SHIFT))&SNVS_HPTAMR_HPTA_MASK)
40256 /* HPTALR Bit Fields */
40257 #define SNVS_HPTALR_HPTA_MASK                    0xFFFFFFFFu
40258 #define SNVS_HPTALR_HPTA_SHIFT                   0
40259 #define SNVS_HPTALR_HPTA(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPTALR_HPTA_SHIFT))&SNVS_HPTALR_HPTA_MASK)
40260 /* LPLR Bit Fields */
40261 #define SNVS_LPLR_MC_HL_MASK                     0x10u
40262 #define SNVS_LPLR_MC_HL_SHIFT                    4
40263 #define SNVS_LPLR_GPR_HL_MASK                    0x20u
40264 #define SNVS_LPLR_GPR_HL_SHIFT                   5
40265 /* LPCR Bit Fields */
40266 #define SNVS_LPCR_MC_ENV_MASK                    0x4u
40267 #define SNVS_LPCR_MC_ENV_SHIFT                   2
40268 #define SNVS_LPCR_DP_EN_MASK                     0x20u
40269 #define SNVS_LPCR_DP_EN_SHIFT                    5
40270 #define SNVS_LPCR_TOP_MASK                       0x40u
40271 #define SNVS_LPCR_TOP_SHIFT                      6
40272 #define SNVS_LPCR_PWR_GLITCH_EN_MASK             0x80u
40273 #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT            7
40274 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            0x30000u
40275 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           16
40276 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_BTN_PRESS_TIME_SHIFT))&SNVS_LPCR_BTN_PRESS_TIME_MASK)
40277 #define SNVS_LPCR_DEBOUNCE_MASK                  0xC0000u
40278 #define SNVS_LPCR_DEBOUNCE_SHIFT                 18
40279 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_DEBOUNCE_SHIFT))&SNVS_LPCR_DEBOUNCE_MASK)
40280 #define SNVS_LPCR_ON_TIME_MASK                   0x300000u
40281 #define SNVS_LPCR_ON_TIME_SHIFT                  20
40282 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_ON_TIME_SHIFT))&SNVS_LPCR_ON_TIME_MASK)
40283 #define SNVS_LPCR_PK_EN_MASK                     0x400000u
40284 #define SNVS_LPCR_PK_EN_SHIFT                    22
40285 #define SNVS_LPCR_PK_OVERRIDE_MASK               0x800000u
40286 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              23
40287 /* LPSR Bit Fields */
40288 #define SNVS_LPSR_MCR_MASK                       0x4u
40289 #define SNVS_LPSR_MCR_SHIFT                      2
40290 #define SNVS_LPSR_EO_MASK                        0x20000u
40291 #define SNVS_LPSR_EO_SHIFT                       17
40292 #define SNVS_LPSR_SPO_MASK                       0x40000u
40293 #define SNVS_LPSR_SPO_SHIFT                      18
40294 /* LPSMCMR Bit Fields */
40295 #define SNVS_LPSMCMR_MON_COUNTER_MASK            0xFFFFu
40296 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           0
40297 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MON_COUNTER_SHIFT))&SNVS_LPSMCMR_MON_COUNTER_MASK)
40298 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            0xFFFF0000u
40299 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           16
40300 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MC_ERA_BITS_SHIFT))&SNVS_LPSMCMR_MC_ERA_BITS_MASK)
40301 /* LPSMCLR Bit Fields */
40302 #define SNVS_LPSMCLR_MON_COUNTER_MASK            0xFFFFFFFFu
40303 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           0
40304 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCLR_MON_COUNTER_SHIFT))&SNVS_LPSMCLR_MON_COUNTER_MASK)
40305 /* LPGPR Bit Fields */
40306 #define SNVS_LPGPR_GPR_MASK                      0xFFFFFFFFu
40307 #define SNVS_LPGPR_GPR_SHIFT                     0
40308 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x))<<SNVS_LPGPR_GPR_SHIFT))&SNVS_LPGPR_GPR_MASK)
40309 /* HPVIDR1 Bit Fields */
40310 #define SNVS_HPVIDR1_MINOR_REV_MASK              0xFFu
40311 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             0
40312 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MINOR_REV_SHIFT))&SNVS_HPVIDR1_MINOR_REV_MASK)
40313 #define SNVS_HPVIDR1_MAJOR_REV_MASK              0xFF00u
40314 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             8
40315 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MAJOR_REV_SHIFT))&SNVS_HPVIDR1_MAJOR_REV_MASK)
40316 #define SNVS_HPVIDR1_IP_ID_MASK                  0xFFFF0000u
40317 #define SNVS_HPVIDR1_IP_ID_SHIFT                 16
40318 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_IP_ID_SHIFT))&SNVS_HPVIDR1_IP_ID_MASK)
40319 /* HPVIDR2 Bit Fields */
40320 #define SNVS_HPVIDR2_CONFIG_OPT_MASK             0xFFu
40321 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT            0
40322 #define SNVS_HPVIDR2_CONFIG_OPT(x)               (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_CONFIG_OPT_SHIFT))&SNVS_HPVIDR2_CONFIG_OPT_MASK)
40323 #define SNVS_HPVIDR2_ECO_REV_MASK                0xFF00u
40324 #define SNVS_HPVIDR2_ECO_REV_SHIFT               8
40325 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_ECO_REV_SHIFT))&SNVS_HPVIDR2_ECO_REV_MASK)
40326 #define SNVS_HPVIDR2_INTG_OPT_MASK               0xFF0000u
40327 #define SNVS_HPVIDR2_INTG_OPT_SHIFT              16
40328 #define SNVS_HPVIDR2_INTG_OPT(x)                 (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_INTG_OPT_SHIFT))&SNVS_HPVIDR2_INTG_OPT_MASK)
40329 #define SNVS_HPVIDR2_IP_ERA_MASK                 0xFF000000u
40330 #define SNVS_HPVIDR2_IP_ERA_SHIFT                24
40331 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_IP_ERA_SHIFT))&SNVS_HPVIDR2_IP_ERA_MASK)
40332 
40333 /*!
40334  * @}
40335  */ /* end of group SNVS_Register_Masks */
40336 
40337 /* SNVS - Peripheral instance base addresses */
40338 /** Peripheral SNVS base address */
40339 #define SNVS_BASE                                (0x30370000u)
40340 /** Peripheral SNVS base pointer */
40341 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
40342 #define SNVS_BASE_PTR                            (SNVS)
40343 /** Array initializer of SNVS peripheral base addresses */
40344 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
40345 /** Array initializer of SNVS peripheral base pointers */
40346 #define SNVS_BASE_PTRS                           { SNVS }
40347 /** Interrupt vectors for the SNVS peripheral type */
40348 #define SNVS_IRQS                                { SNVS_IRQn }
40349 /* ----------------------------------------------------------------------------
40350    -- SNVS - Register accessor macros
40351    ---------------------------------------------------------------------------- */
40352 
40353 /*!
40354  * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros
40355  * @{
40356  */
40357 
40358 
40359 /* SNVS - Register instance definitions */
40360 /* SNVS */
40361 #define SNVS_HPLR                                SNVS_HPLR_REG(SNVS_BASE_PTR)
40362 #define SNVS_HPCOMR                              SNVS_HPCOMR_REG(SNVS_BASE_PTR)
40363 #define SNVS_HPCR                                SNVS_HPCR_REG(SNVS_BASE_PTR)
40364 #define SNVS_HPSR                                SNVS_HPSR_REG(SNVS_BASE_PTR)
40365 #define SNVS_HPRTCMR                             SNVS_HPRTCMR_REG(SNVS_BASE_PTR)
40366 #define SNVS_HPRTCLR                             SNVS_HPRTCLR_REG(SNVS_BASE_PTR)
40367 #define SNVS_HPTAMR                              SNVS_HPTAMR_REG(SNVS_BASE_PTR)
40368 #define SNVS_HPTALR                              SNVS_HPTALR_REG(SNVS_BASE_PTR)
40369 #define SNVS_LPLR                                SNVS_LPLR_REG(SNVS_BASE_PTR)
40370 #define SNVS_LPCR                                SNVS_LPCR_REG(SNVS_BASE_PTR)
40371 #define SNVS_LPSR                                SNVS_LPSR_REG(SNVS_BASE_PTR)
40372 #define SNVS_LPSMCMR                             SNVS_LPSMCMR_REG(SNVS_BASE_PTR)
40373 #define SNVS_LPSMCLR                             SNVS_LPSMCLR_REG(SNVS_BASE_PTR)
40374 #define SNVS_LPGPR                               SNVS_LPGPR_REG(SNVS_BASE_PTR)
40375 #define SNVS_HPVIDR1                             SNVS_HPVIDR1_REG(SNVS_BASE_PTR)
40376 #define SNVS_HPVIDR2                             SNVS_HPVIDR2_REG(SNVS_BASE_PTR)
40377 /*!
40378  * @}
40379  */ /* end of group SNVS_Register_Accessor_Macros */
40380 
40381 
40382 /*!
40383  * @}
40384  */ /* end of group SNVS_Peripheral */
40385 
40386 /* ----------------------------------------------------------------------------
40387    -- SPBA Peripheral Access Layer
40388    ---------------------------------------------------------------------------- */
40389 
40390 /*!
40391  * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer
40392  * @{
40393  */
40394 
40395 /** SPBA - Register Layout Typedef */
40396 typedef struct {
40397   __IO  uint32_t PRR[32];                                /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */
40398 } SPBA_Type, *SPBA_MemMapPtr;
40399 /* ----------------------------------------------------------------------------
40400    -- SPBA - Register accessor macros
40401    ---------------------------------------------------------------------------- */
40402 
40403 /*!
40404  * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros
40405  * @{
40406  */
40407 
40408 
40409 /* SPBA - Register accessors */
40410 #define SPBA_PRR_REG(base,index)                 ((base)->PRR[index])
40411 
40412 /*!
40413  * @}
40414  */ /* end of group SPBA_Register_Accessor_Macros */
40415 /* ----------------------------------------------------------------------------
40416    -- SPBA Register Masks
40417    ---------------------------------------------------------------------------- */
40418 
40419 /*!
40420  * @addtogroup SPBA_Register_Masks SPBA Register Masks
40421  * @{
40422  */
40423 
40424 /* PRR Bit Fields */
40425 #define SPBA_PRR_RARA_MASK                       0x1u
40426 #define SPBA_PRR_RARA_SHIFT                      0
40427 #define SPBA_PRR_RARB_MASK                       0x2u
40428 #define SPBA_PRR_RARB_SHIFT                      1
40429 #define SPBA_PRR_RARC_MASK                       0x4u
40430 #define SPBA_PRR_RARC_SHIFT                      2
40431 #define SPBA_PRR_ROI_MASK                        0x30000u
40432 #define SPBA_PRR_ROI_SHIFT                       16
40433 #define SPBA_PRR_ROI(x)                          (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_ROI_SHIFT))&SPBA_PRR_ROI_MASK)
40434 #define SPBA_PRR_RMO_MASK                        0xC0000000u
40435 #define SPBA_PRR_RMO_SHIFT                       30
40436 #define SPBA_PRR_RMO(x)                          (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_RMO_SHIFT))&SPBA_PRR_RMO_MASK)
40437 
40438 /*!
40439  * @}
40440  */ /* end of group SPBA_Register_Masks */
40441 
40442 /* SPBA - Peripheral instance base addresses */
40443 /** Peripheral SPBA base address */
40444 #define SPBA_BASE                                (0x308F0000u)
40445 /** Peripheral SPBA base pointer */
40446 #define SPBA                                     ((SPBA_Type *)SPBA_BASE)
40447 #define SPBA_BASE_PTR                            (SPBA)
40448 /** Array initializer of SPBA peripheral base addresses */
40449 #define SPBA_BASE_ADDRS                          { SPBA_BASE }
40450 /** Array initializer of SPBA peripheral base pointers */
40451 #define SPBA_BASE_PTRS                           { SPBA }
40452 /* ----------------------------------------------------------------------------
40453    -- SPBA - Register accessor macros
40454    ---------------------------------------------------------------------------- */
40455 
40456 /*!
40457  * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros
40458  * @{
40459  */
40460 
40461 
40462 /* SPBA - Register instance definitions */
40463 /* SPBA */
40464 #define SPBA_PRR0                                SPBA_PRR_REG(SPBA_BASE_PTR,0)
40465 #define SPBA_PRR1                                SPBA_PRR_REG(SPBA_BASE_PTR,1)
40466 #define SPBA_PRR2                                SPBA_PRR_REG(SPBA_BASE_PTR,2)
40467 #define SPBA_PRR3                                SPBA_PRR_REG(SPBA_BASE_PTR,3)
40468 #define SPBA_PRR4                                SPBA_PRR_REG(SPBA_BASE_PTR,4)
40469 #define SPBA_PRR5                                SPBA_PRR_REG(SPBA_BASE_PTR,5)
40470 #define SPBA_PRR6                                SPBA_PRR_REG(SPBA_BASE_PTR,6)
40471 #define SPBA_PRR7                                SPBA_PRR_REG(SPBA_BASE_PTR,7)
40472 #define SPBA_PRR8                                SPBA_PRR_REG(SPBA_BASE_PTR,8)
40473 #define SPBA_PRR9                                SPBA_PRR_REG(SPBA_BASE_PTR,9)
40474 #define SPBA_PRR10                               SPBA_PRR_REG(SPBA_BASE_PTR,10)
40475 #define SPBA_PRR11                               SPBA_PRR_REG(SPBA_BASE_PTR,11)
40476 #define SPBA_PRR12                               SPBA_PRR_REG(SPBA_BASE_PTR,12)
40477 #define SPBA_PRR13                               SPBA_PRR_REG(SPBA_BASE_PTR,13)
40478 #define SPBA_PRR14                               SPBA_PRR_REG(SPBA_BASE_PTR,14)
40479 #define SPBA_PRR15                               SPBA_PRR_REG(SPBA_BASE_PTR,15)
40480 #define SPBA_PRR16                               SPBA_PRR_REG(SPBA_BASE_PTR,16)
40481 #define SPBA_PRR17                               SPBA_PRR_REG(SPBA_BASE_PTR,17)
40482 #define SPBA_PRR18                               SPBA_PRR_REG(SPBA_BASE_PTR,18)
40483 #define SPBA_PRR19                               SPBA_PRR_REG(SPBA_BASE_PTR,19)
40484 #define SPBA_PRR20                               SPBA_PRR_REG(SPBA_BASE_PTR,20)
40485 #define SPBA_PRR21                               SPBA_PRR_REG(SPBA_BASE_PTR,21)
40486 #define SPBA_PRR22                               SPBA_PRR_REG(SPBA_BASE_PTR,22)
40487 #define SPBA_PRR23                               SPBA_PRR_REG(SPBA_BASE_PTR,23)
40488 #define SPBA_PRR24                               SPBA_PRR_REG(SPBA_BASE_PTR,24)
40489 #define SPBA_PRR25                               SPBA_PRR_REG(SPBA_BASE_PTR,25)
40490 #define SPBA_PRR26                               SPBA_PRR_REG(SPBA_BASE_PTR,26)
40491 #define SPBA_PRR27                               SPBA_PRR_REG(SPBA_BASE_PTR,27)
40492 #define SPBA_PRR28                               SPBA_PRR_REG(SPBA_BASE_PTR,28)
40493 #define SPBA_PRR29                               SPBA_PRR_REG(SPBA_BASE_PTR,29)
40494 #define SPBA_PRR30                               SPBA_PRR_REG(SPBA_BASE_PTR,30)
40495 #define SPBA_PRR31                               SPBA_PRR_REG(SPBA_BASE_PTR,31)
40496 /* SPBA - Register array accessors */
40497 #define SPBA_PRR(index)                          SPBA_PRR_REG(SPBA_BASE_PTR,index)
40498 /*!
40499  * @}
40500  */ /* end of group SPBA_Register_Accessor_Macros */
40501 
40502 
40503 /*!
40504  * @}
40505  */ /* end of group SPBA_Peripheral */
40506 
40507 /* ----------------------------------------------------------------------------
40508    -- SRC Peripheral Access Layer
40509    ---------------------------------------------------------------------------- */
40510 
40511 /*!
40512  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
40513  * @{
40514  */
40515 
40516 /** SRC - Register Layout Typedef */
40517 typedef struct {
40518   __IO  uint32_t SCR;                                    /**< SRC Reset Control Register, offset: 0x0 */
40519   __IO  uint32_t A7RCR0;                                 /**< A7 Reset Control Register, offset: 0x4 */
40520   __IO  uint32_t A7RCR1;                                 /**< A7 Reset Control Register, offset: 0x8 */
40521   __IO  uint32_t M4RCR;                                  /**< M4 Reset Control Register, offset: 0xC */
40522   uint8_t RESERVED_0[4];
40523   __IO  uint32_t ERCR;                                   /**< EIM Reset Control Register, offset: 0x14 */
40524   uint8_t RESERVED_1[4];
40525   __IO  uint32_t HSICPHY_RCR;                            /**< HSIC PHY Reset Control Register, offset: 0x1C */
40526   __IO  uint32_t USBOPHY1_RCR;                           /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */
40527   __IO  uint32_t USBOPHY2_RCR;                           /**< USB OTG PHY2 Reset Control Register, offset: 0x24 */
40528   __IO  uint32_t MIPIPHY_RCR;                            /**< MIPI PHY Reset Control Register, offset: 0x28 */
40529   __IO  uint32_t PCIEPHY_RCR;                            /**< PCIE PHY Reset Control Register, offset: 0x2C */
40530   uint8_t RESERVED_2[40];
40531   __I   uint32_t SBMR1;                                  /**< SRC Boot Mode Register 1, offset: 0x58 */
40532   __IO  uint32_t SRSR;                                   /**< SRC Reset Status Register, offset: 0x5C */
40533   uint8_t RESERVED_3[8];
40534   __I   uint32_t SISR;                                   /**< SRC Interrupt Status Register, offset: 0x68 */
40535   __IO  uint32_t SIMR;                                   /**< SRC Interrupt Mask Register, offset: 0x6C */
40536   __I   uint32_t SBMR2;                                  /**< SRC Boot Mode Register 2, offset: 0x70 */
40537   __IO  uint32_t GPR1;                                   /**< SRC General Purpose Register 1, offset: 0x74 */
40538   __IO  uint32_t GPR2;                                   /**< SRC General Purpose Register 2, offset: 0x78 */
40539   __IO  uint32_t GPR3;                                   /**< SRC General Purpose Register 3, offset: 0x7C */
40540   __IO  uint32_t GPR4;                                   /**< SRC General Purpose Register 4, offset: 0x80 */
40541   __IO  uint32_t GPR5;                                   /**< SRC General Purpose Register 5, offset: 0x84 */
40542   __IO  uint32_t GPR6;                                   /**< SRC General Purpose Register 6, offset: 0x88 */
40543   __IO  uint32_t GPR7;                                   /**< SRC General Purpose Register 7, offset: 0x8C */
40544   __IO  uint32_t GPR8;                                   /**< SRC General Purpose Register 8, offset: 0x90 */
40545   __IO  uint32_t GPR9;                                   /**< SRC General Purpose Register 9, offset: 0x94 */
40546   __IO  uint32_t GPR10;                                  /**< SRC General Purpose Register 10, offset: 0x98 */
40547   uint8_t RESERVED_4[3940];
40548   __IO  uint32_t DDRC_RCR;                               /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */
40549 } SRC_Type, *SRC_MemMapPtr;
40550 /* ----------------------------------------------------------------------------
40551    -- SRC - Register accessor macros
40552    ---------------------------------------------------------------------------- */
40553 
40554 /*!
40555  * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros
40556  * @{
40557  */
40558 
40559 
40560 /* SRC - Register accessors */
40561 #define SRC_SCR_REG(base)                        ((base)->SCR)
40562 #define SRC_A7RCR0_REG(base)                     ((base)->A7RCR0)
40563 #define SRC_A7RCR1_REG(base)                     ((base)->A7RCR1)
40564 #define SRC_M4RCR_REG(base)                      ((base)->M4RCR)
40565 #define SRC_ERCR_REG(base)                       ((base)->ERCR)
40566 #define SRC_HSICPHY_RCR_REG(base)                ((base)->HSICPHY_RCR)
40567 #define SRC_USBOPHY1_RCR_REG(base)               ((base)->USBOPHY1_RCR)
40568 #define SRC_USBOPHY2_RCR_REG(base)               ((base)->USBOPHY2_RCR)
40569 #define SRC_MIPIPHY_RCR_REG(base)                ((base)->MIPIPHY_RCR)
40570 #define SRC_PCIEPHY_RCR_REG(base)                ((base)->PCIEPHY_RCR)
40571 #define SRC_SBMR1_REG(base)                      ((base)->SBMR1)
40572 #define SRC_SRSR_REG(base)                       ((base)->SRSR)
40573 #define SRC_SISR_REG(base)                       ((base)->SISR)
40574 #define SRC_SIMR_REG(base)                       ((base)->SIMR)
40575 #define SRC_SBMR2_REG(base)                      ((base)->SBMR2)
40576 #define SRC_GPR1_REG(base)                       ((base)->GPR1)
40577 #define SRC_GPR2_REG(base)                       ((base)->GPR2)
40578 #define SRC_GPR3_REG(base)                       ((base)->GPR3)
40579 #define SRC_GPR4_REG(base)                       ((base)->GPR4)
40580 #define SRC_GPR5_REG(base)                       ((base)->GPR5)
40581 #define SRC_GPR6_REG(base)                       ((base)->GPR6)
40582 #define SRC_GPR7_REG(base)                       ((base)->GPR7)
40583 #define SRC_GPR8_REG(base)                       ((base)->GPR8)
40584 #define SRC_GPR9_REG(base)                       ((base)->GPR9)
40585 #define SRC_GPR10_REG(base)                      ((base)->GPR10)
40586 #define SRC_DDRC_RCR_REG(base)                   ((base)->DDRC_RCR)
40587 
40588 /*!
40589  * @}
40590  */ /* end of group SRC_Register_Accessor_Macros */
40591 /* ----------------------------------------------------------------------------
40592    -- SRC Register Masks
40593    ---------------------------------------------------------------------------- */
40594 
40595 /*!
40596  * @addtogroup SRC_Register_Masks SRC Register Masks
40597  * @{
40598  */
40599 
40600 /* SCR Bit Fields */
40601 #define SRC_SCR_MASK_TEMPSENSE_RESET_MASK        0xF0u
40602 #define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT       4
40603 #define SRC_SCR_MASK_TEMPSENSE_RESET(x)          (((uint32_t)(((uint32_t)(x))<<SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT))&SRC_SCR_MASK_TEMPSENSE_RESET_MASK)
40604 #define SRC_SCR_DOMAIN0_MASK                     0x1000000u
40605 #define SRC_SCR_DOMAIN0_SHIFT                    24
40606 #define SRC_SCR_DOMAIN1_MASK                     0x2000000u
40607 #define SRC_SCR_DOMAIN1_SHIFT                    25
40608 #define SRC_SCR_DOMAIN2_MASK                     0x4000000u
40609 #define SRC_SCR_DOMAIN2_SHIFT                    26
40610 #define SRC_SCR_DOMAIN3_MASK                     0x8000000u
40611 #define SRC_SCR_DOMAIN3_SHIFT                    27
40612 #define SRC_SCR_LOCK_MASK                        0x40000000u
40613 #define SRC_SCR_LOCK_SHIFT                       30
40614 #define SRC_SCR_DOM_EN_MASK                      0x80000000u
40615 #define SRC_SCR_DOM_EN_SHIFT                     31
40616 /* A7RCR0 Bit Fields */
40617 #define SRC_A7RCR0_A7_CORE_POR_RESET0_MASK       0x1u
40618 #define SRC_A7RCR0_A7_CORE_POR_RESET0_SHIFT      0
40619 #define SRC_A7RCR0_A7_CORE_POR_RESET1_MASK       0x2u
40620 #define SRC_A7RCR0_A7_CORE_POR_RESET1_SHIFT      1
40621 #define SRC_A7RCR0_A7_CORE_RESET0_MASK           0x10u
40622 #define SRC_A7RCR0_A7_CORE_RESET0_SHIFT          4
40623 #define SRC_A7RCR0_A7_CORE_RESET1_MASK           0x20u
40624 #define SRC_A7RCR0_A7_CORE_RESET1_SHIFT          5
40625 #define SRC_A7RCR0_A7_DBG_RESET0_MASK            0x100u
40626 #define SRC_A7RCR0_A7_DBG_RESET0_SHIFT           8
40627 #define SRC_A7RCR0_A7_DBG_RESET1_MASK            0x200u
40628 #define SRC_A7RCR0_A7_DBG_RESET1_SHIFT           9
40629 #define SRC_A7RCR0_A7_ETM_RESET0_MASK            0x1000u
40630 #define SRC_A7RCR0_A7_ETM_RESET0_SHIFT           12
40631 #define SRC_A7RCR0_A7_ETM_RESET1_MASK            0x2000u
40632 #define SRC_A7RCR0_A7_ETM_RESET1_SHIFT           13
40633 #define SRC_A7RCR0_MASK_WDOG1_RST_MASK           0xF0000u
40634 #define SRC_A7RCR0_MASK_WDOG1_RST_SHIFT          16
40635 #define SRC_A7RCR0_MASK_WDOG1_RST(x)             (((uint32_t)(((uint32_t)(x))<<SRC_A7RCR0_MASK_WDOG1_RST_SHIFT))&SRC_A7RCR0_MASK_WDOG1_RST_MASK)
40636 #define SRC_A7RCR0_A7_SOC_DBG_RESET_MASK         0x100000u
40637 #define SRC_A7RCR0_A7_SOC_DBG_RESET_SHIFT        20
40638 #define SRC_A7RCR0_A7_L2RESET_MASK               0x200000u
40639 #define SRC_A7RCR0_A7_L2RESET_SHIFT              21
40640 #define SRC_A7RCR0_DOMAIN0_MASK                  0x1000000u
40641 #define SRC_A7RCR0_DOMAIN0_SHIFT                 24
40642 #define SRC_A7RCR0_DOMAIN1_MASK                  0x2000000u
40643 #define SRC_A7RCR0_DOMAIN1_SHIFT                 25
40644 #define SRC_A7RCR0_DOMAIN2_MASK                  0x4000000u
40645 #define SRC_A7RCR0_DOMAIN2_SHIFT                 26
40646 #define SRC_A7RCR0_DOMAIN3_MASK                  0x8000000u
40647 #define SRC_A7RCR0_DOMAIN3_SHIFT                 27
40648 #define SRC_A7RCR0_LOCK_MASK                     0x40000000u
40649 #define SRC_A7RCR0_LOCK_SHIFT                    30
40650 #define SRC_A7RCR0_DOM_EN_MASK                   0x80000000u
40651 #define SRC_A7RCR0_DOM_EN_SHIFT                  31
40652 /* A7RCR1 Bit Fields */
40653 #define SRC_A7RCR1_A7_CORE1_ENABLE_MASK          0x2u
40654 #define SRC_A7RCR1_A7_CORE1_ENABLE_SHIFT         1
40655 #define SRC_A7RCR1_DOMAIN0_MASK                  0x1000000u
40656 #define SRC_A7RCR1_DOMAIN0_SHIFT                 24
40657 #define SRC_A7RCR1_DOMAIN1_MASK                  0x2000000u
40658 #define SRC_A7RCR1_DOMAIN1_SHIFT                 25
40659 #define SRC_A7RCR1_DOMAIN2_MASK                  0x4000000u
40660 #define SRC_A7RCR1_DOMAIN2_SHIFT                 26
40661 #define SRC_A7RCR1_DOMAIN3_MASK                  0x8000000u
40662 #define SRC_A7RCR1_DOMAIN3_SHIFT                 27
40663 #define SRC_A7RCR1_LOCK_MASK                     0x40000000u
40664 #define SRC_A7RCR1_LOCK_SHIFT                    30
40665 #define SRC_A7RCR1_DOM_EN_MASK                   0x80000000u
40666 #define SRC_A7RCR1_DOM_EN_SHIFT                  31
40667 /* M4RCR Bit Fields */
40668 #define SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK       0x1u
40669 #define SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT      0
40670 #define SRC_M4RCR_SW_M4C_RST_MASK                0x2u
40671 #define SRC_M4RCR_SW_M4C_RST_SHIFT               1
40672 #define SRC_M4RCR_SW_M4P_RST_MASK                0x4u
40673 #define SRC_M4RCR_SW_M4P_RST_SHIFT               2
40674 #define SRC_M4RCR_ENABLE_M4_MASK                 0x8u
40675 #define SRC_M4RCR_ENABLE_M4_SHIFT                3
40676 #define SRC_M4RCR_MASK_WDOG3_RST_MASK            0xF0u
40677 #define SRC_M4RCR_MASK_WDOG3_RST_SHIFT           4
40678 #define SRC_M4RCR_MASK_WDOG3_RST(x)              (((uint32_t)(((uint32_t)(x))<<SRC_M4RCR_MASK_WDOG3_RST_SHIFT))&SRC_M4RCR_MASK_WDOG3_RST_MASK)
40679 #define SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK       0x100u
40680 #define SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT      8
40681 #define SRC_M4RCR_WDOG3_RST_OPTION_MASK          0x200u
40682 #define SRC_M4RCR_WDOG3_RST_OPTION_SHIFT         9
40683 #define SRC_M4RCR_DOMAIN0_MASK                   0x1000000u
40684 #define SRC_M4RCR_DOMAIN0_SHIFT                  24
40685 #define SRC_M4RCR_DOMAIN1_MASK                   0x2000000u
40686 #define SRC_M4RCR_DOMAIN1_SHIFT                  25
40687 #define SRC_M4RCR_DOMAIN2_MASK                   0x4000000u
40688 #define SRC_M4RCR_DOMAIN2_SHIFT                  26
40689 #define SRC_M4RCR_DOMAIN3_MASK                   0x8000000u
40690 #define SRC_M4RCR_DOMAIN3_SHIFT                  27
40691 #define SRC_M4RCR_LOCK_MASK                      0x40000000u
40692 #define SRC_M4RCR_LOCK_SHIFT                     30
40693 #define SRC_M4RCR_DOM_EN_MASK                    0x80000000u
40694 #define SRC_M4RCR_DOM_EN_SHIFT                   31
40695 /* ERCR Bit Fields */
40696 #define SRC_ERCR_EIM_RST_MASK                    0x1u
40697 #define SRC_ERCR_EIM_RST_SHIFT                   0
40698 #define SRC_ERCR_DOMAIN0_MASK                    0x1000000u
40699 #define SRC_ERCR_DOMAIN0_SHIFT                   24
40700 #define SRC_ERCR_DOMAIN1_MASK                    0x2000000u
40701 #define SRC_ERCR_DOMAIN1_SHIFT                   25
40702 #define SRC_ERCR_DOMAIN2_MASK                    0x4000000u
40703 #define SRC_ERCR_DOMAIN2_SHIFT                   26
40704 #define SRC_ERCR_DOMAIN3_MASK                    0x8000000u
40705 #define SRC_ERCR_DOMAIN3_SHIFT                   27
40706 #define SRC_ERCR_LOCK_MASK                       0x40000000u
40707 #define SRC_ERCR_LOCK_SHIFT                      30
40708 #define SRC_ERCR_DOM_EN_MASK                     0x80000000u
40709 #define SRC_ERCR_DOM_EN_SHIFT                    31
40710 /* HSICPHY_RCR Bit Fields */
40711 #define SRC_HSICPHY_RCR_HSIC_PHY_POR_MASK        0x1u
40712 #define SRC_HSICPHY_RCR_HSIC_PHY_POR_SHIFT       0
40713 #define SRC_HSICPHY_RCR_HSICPHY_PORT_RST_MASK    0x2u
40714 #define SRC_HSICPHY_RCR_HSICPHY_PORT_RST_SHIFT   1
40715 #define SRC_HSICPHY_RCR_DOMAIN0_MASK             0x1000000u
40716 #define SRC_HSICPHY_RCR_DOMAIN0_SHIFT            24
40717 #define SRC_HSICPHY_RCR_DOMAIN1_MASK             0x2000000u
40718 #define SRC_HSICPHY_RCR_DOMAIN1_SHIFT            25
40719 #define SRC_HSICPHY_RCR_DOMAIN2_MASK             0x4000000u
40720 #define SRC_HSICPHY_RCR_DOMAIN2_SHIFT            26
40721 #define SRC_HSICPHY_RCR_DOMAIN3_MASK             0x8000000u
40722 #define SRC_HSICPHY_RCR_DOMAIN3_SHIFT            27
40723 #define SRC_HSICPHY_RCR_LOCK_MASK                0x40000000u
40724 #define SRC_HSICPHY_RCR_LOCK_SHIFT               30
40725 #define SRC_HSICPHY_RCR_DOM_EN_MASK              0x80000000u
40726 #define SRC_HSICPHY_RCR_DOM_EN_SHIFT             31
40727 /* USBOPHY1_RCR Bit Fields */
40728 #define SRC_USBOPHY1_RCR_USBPHY1_POR_MASK        0x1u
40729 #define SRC_USBOPHY1_RCR_USBPHY1_POR_SHIFT       0
40730 #define SRC_USBOPHY1_RCR_USBPHY1_PORT_RST_MASK   0x2u
40731 #define SRC_USBOPHY1_RCR_USBPHY1_PORT_RST_SHIFT  1
40732 #define SRC_USBOPHY1_RCR_DOMAIN0_MASK            0x1000000u
40733 #define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT           24
40734 #define SRC_USBOPHY1_RCR_DOMAIN1_MASK            0x2000000u
40735 #define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT           25
40736 #define SRC_USBOPHY1_RCR_DOMAIN2_MASK            0x4000000u
40737 #define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT           26
40738 #define SRC_USBOPHY1_RCR_DOMAIN3_MASK            0x8000000u
40739 #define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT           27
40740 #define SRC_USBOPHY1_RCR_LOCK_MASK               0x40000000u
40741 #define SRC_USBOPHY1_RCR_LOCK_SHIFT              30
40742 #define SRC_USBOPHY1_RCR_DOM_EN_MASK             0x80000000u
40743 #define SRC_USBOPHY1_RCR_DOM_EN_SHIFT            31
40744 /* USBOPHY2_RCR Bit Fields */
40745 #define SRC_USBOPHY2_RCR_USBPHY2_POR_MASK        0x1u
40746 #define SRC_USBOPHY2_RCR_USBPHY2_POR_SHIFT       0
40747 #define SRC_USBOPHY2_RCR_USBPHY2_PORT_RST_MASK   0x2u
40748 #define SRC_USBOPHY2_RCR_USBPHY2_PORT_RST_SHIFT  1
40749 #define SRC_USBOPHY2_RCR_DOMAIN0_MASK            0x1000000u
40750 #define SRC_USBOPHY2_RCR_DOMAIN0_SHIFT           24
40751 #define SRC_USBOPHY2_RCR_DOMAIN1_MASK            0x2000000u
40752 #define SRC_USBOPHY2_RCR_DOMAIN1_SHIFT           25
40753 #define SRC_USBOPHY2_RCR_DOMAIN2_MASK            0x4000000u
40754 #define SRC_USBOPHY2_RCR_DOMAIN2_SHIFT           26
40755 #define SRC_USBOPHY2_RCR_DOMAIN3_MASK            0x8000000u
40756 #define SRC_USBOPHY2_RCR_DOMAIN3_SHIFT           27
40757 #define SRC_USBOPHY2_RCR_LOCK_MASK               0x40000000u
40758 #define SRC_USBOPHY2_RCR_LOCK_SHIFT              30
40759 #define SRC_USBOPHY2_RCR_DOM_EN_MASK             0x80000000u
40760 #define SRC_USBOPHY2_RCR_DOM_EN_SHIFT            31
40761 /* MIPIPHY_RCR Bit Fields */
40762 #define SRC_MIPIPHY_RCR_MIPI_PHY_MRST_MASK       0x1u
40763 #define SRC_MIPIPHY_RCR_MIPI_PHY_MRST_SHIFT      0
40764 #define SRC_MIPIPHY_RCR_MIPI_PHY_SRST_MASK       0x2u
40765 #define SRC_MIPIPHY_RCR_MIPI_PHY_SRST_SHIFT      1
40766 #define SRC_MIPIPHY_RCR_DOMAIN0_MASK             0x1000000u
40767 #define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT            24
40768 #define SRC_MIPIPHY_RCR_DOMAIN1_MASK             0x2000000u
40769 #define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT            25
40770 #define SRC_MIPIPHY_RCR_DOMAIN2_MASK             0x4000000u
40771 #define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT            26
40772 #define SRC_MIPIPHY_RCR_DOMAIN3_MASK             0x8000000u
40773 #define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT            27
40774 #define SRC_MIPIPHY_RCR_LOCK_MASK                0x40000000u
40775 #define SRC_MIPIPHY_RCR_LOCK_SHIFT               30
40776 #define SRC_MIPIPHY_RCR_DOM_EN_MASK              0x80000000u
40777 #define SRC_MIPIPHY_RCR_DOM_EN_SHIFT             31
40778 /* PCIEPHY_RCR Bit Fields */
40779 #define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK       0x2u
40780 #define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT      1
40781 #define SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK         0x4u
40782 #define SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT        2
40783 #define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK       0x8u
40784 #define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT      3
40785 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK 0x10u
40786 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT 4
40787 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK  0x20u
40788 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT 5
40789 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK   0x40u
40790 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT  6
40791 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK 0x80u
40792 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT 7
40793 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK 0x100u
40794 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT 8
40795 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK 0x200u
40796 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT 9
40797 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK  0x400u
40798 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT 10
40799 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK 0x800u
40800 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT 11
40801 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK 0x1000u
40802 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT 12
40803 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_MAC_MASK 0x2000u
40804 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_MAC_SHIFT 13
40805 #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK   0x4000u
40806 #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT  14
40807 #define SRC_PCIEPHY_RCR_DOMAIN0_MASK             0x1000000u
40808 #define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT            24
40809 #define SRC_PCIEPHY_RCR_DOMAIN1_MASK             0x2000000u
40810 #define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT            25
40811 #define SRC_PCIEPHY_RCR_DOMAIN2_MASK             0x4000000u
40812 #define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT            26
40813 #define SRC_PCIEPHY_RCR_DOMAIN3_MASK             0x8000000u
40814 #define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT            27
40815 #define SRC_PCIEPHY_RCR_LOCK_MASK                0x40000000u
40816 #define SRC_PCIEPHY_RCR_LOCK_SHIFT               30
40817 #define SRC_PCIEPHY_RCR_DOM_EN_MASK              0x80000000u
40818 #define SRC_PCIEPHY_RCR_DOM_EN_SHIFT             31
40819 /* SBMR1 Bit Fields */
40820 #define SRC_SBMR1_BOOT_CFG1_MASK                 0xFFu
40821 #define SRC_SBMR1_BOOT_CFG1_SHIFT                0
40822 #define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG1_SHIFT))&SRC_SBMR1_BOOT_CFG1_MASK)
40823 #define SRC_SBMR1_BOOT_CFG2_MASK                 0xFF00u
40824 #define SRC_SBMR1_BOOT_CFG2_SHIFT                8
40825 #define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG2_SHIFT))&SRC_SBMR1_BOOT_CFG2_MASK)
40826 #define SRC_SBMR1_BOOT_CFG3_MASK                 0xFF0000u
40827 #define SRC_SBMR1_BOOT_CFG3_SHIFT                16
40828 #define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG3_SHIFT))&SRC_SBMR1_BOOT_CFG3_MASK)
40829 #define SRC_SBMR1_BOOT_CFG4_MASK                 0xFF000000u
40830 #define SRC_SBMR1_BOOT_CFG4_SHIFT                24
40831 #define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG4_SHIFT))&SRC_SBMR1_BOOT_CFG4_MASK)
40832 /* SRSR Bit Fields */
40833 #define SRC_SRSR_ipp_reset_b_MASK                0x1u
40834 #define SRC_SRSR_ipp_reset_b_SHIFT               0
40835 #define SRC_SRSR_csu_reset_b_MASK                0x4u
40836 #define SRC_SRSR_csu_reset_b_SHIFT               2
40837 #define SRC_SRSR_ipp_user_reset_b_MASK           0x8u
40838 #define SRC_SRSR_ipp_user_reset_b_SHIFT          3
40839 #define SRC_SRSR_wdog1_rst_b_MASK                0x10u
40840 #define SRC_SRSR_wdog1_rst_b_SHIFT               4
40841 #define SRC_SRSR_jtag_rst_b_MASK                 0x20u
40842 #define SRC_SRSR_jtag_rst_b_SHIFT                5
40843 #define SRC_SRSR_jtag_sw_rst_MASK                0x40u
40844 #define SRC_SRSR_jtag_sw_rst_SHIFT               6
40845 #define SRC_SRSR_wdog3_rst_b_MASK                0x80u
40846 #define SRC_SRSR_wdog3_rst_b_SHIFT               7
40847 #define SRC_SRSR_wdog4_rst_b_MASK                0x100u
40848 #define SRC_SRSR_wdog4_rst_b_SHIFT               8
40849 #define SRC_SRSR_tempsense_rst_b_MASK            0x200u
40850 #define SRC_SRSR_tempsense_rst_b_SHIFT           9
40851 /* SISR Bit Fields */
40852 #define SRC_SISR_HSICPHY_PASSED_RESET_MASK       0x2u
40853 #define SRC_SISR_HSICPHY_PASSED_RESET_SHIFT      1
40854 #define SRC_SISR_OTGPHY1_PASSED_RESET_MASK       0x4u
40855 #define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT      2
40856 #define SRC_SISR_OTGPHY2_PASSED_RESET_MASK       0x8u
40857 #define SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT      3
40858 #define SRC_SISR_MIPIPHY_PASSED_RESET_MASK       0x10u
40859 #define SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT      4
40860 #define SRC_SISR_M4C_PASSED_RESET_MASK           0x100u
40861 #define SRC_SISR_M4C_PASSED_RESET_SHIFT          8
40862 #define SRC_SISR_M4P_PASSED_RESET_MASK           0x200u
40863 #define SRC_SISR_M4P_PASSED_RESET_SHIFT          9
40864 /* SIMR Bit Fields */
40865 #define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK  0x2u
40866 #define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT 1
40867 #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK  0x4u
40868 #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT 2
40869 #define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK  0x8u
40870 #define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT 3
40871 #define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK  0x10u
40872 #define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT 4
40873 #define SRC_SIMR_MASK_M4C_PASSED_RESET_MASK      0x100u
40874 #define SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT     8
40875 #define SRC_SIMR_MASK_M4P_PASSED_RESET_MASK      0x200u
40876 #define SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT     9
40877 /* SBMR2 Bit Fields */
40878 #define SRC_SBMR2_SEC_CONFIG_MASK                0x3u
40879 #define SRC_SBMR2_SEC_CONFIG_SHIFT               0
40880 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_SEC_CONFIG_SHIFT))&SRC_SBMR2_SEC_CONFIG_MASK)
40881 #define SRC_SBMR2_DIR_BT_DIS_MASK                0x8u
40882 #define SRC_SBMR2_DIR_BT_DIS_SHIFT               3
40883 #define SRC_SBMR2_BT_FUSE_SEL_MASK               0x10u
40884 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              4
40885 #define SRC_SBMR2_BMOD_MASK                      0x3000000u
40886 #define SRC_SBMR2_BMOD_SHIFT                     24
40887 #define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_BMOD_SHIFT))&SRC_SBMR2_BMOD_MASK)
40888 /* GPR1 Bit Fields */
40889 #define SRC_GPR1_PERSISTENT_ENTRY0_MASK          0xFFFFFFFFu
40890 #define SRC_GPR1_PERSISTENT_ENTRY0_SHIFT         0
40891 #define SRC_GPR1_PERSISTENT_ENTRY0(x)            (((uint32_t)(((uint32_t)(x))<<SRC_GPR1_PERSISTENT_ENTRY0_SHIFT))&SRC_GPR1_PERSISTENT_ENTRY0_MASK)
40892 /* GPR2 Bit Fields */
40893 #define SRC_GPR2_PERSISTENT_ARG0_MASK            0xFFFFFFFFu
40894 #define SRC_GPR2_PERSISTENT_ARG0_SHIFT           0
40895 #define SRC_GPR2_PERSISTENT_ARG0(x)              (((uint32_t)(((uint32_t)(x))<<SRC_GPR2_PERSISTENT_ARG0_SHIFT))&SRC_GPR2_PERSISTENT_ARG0_MASK)
40896 /* GPR3 Bit Fields */
40897 #define SRC_GPR3_PERSISTENT_ENTRY1_MASK          0xFFFFFFFFu
40898 #define SRC_GPR3_PERSISTENT_ENTRY1_SHIFT         0
40899 #define SRC_GPR3_PERSISTENT_ENTRY1(x)            (((uint32_t)(((uint32_t)(x))<<SRC_GPR3_PERSISTENT_ENTRY1_SHIFT))&SRC_GPR3_PERSISTENT_ENTRY1_MASK)
40900 /* GPR4 Bit Fields */
40901 #define SRC_GPR4_PERSISTENT_ARG1_MASK            0xFFFFFFFFu
40902 #define SRC_GPR4_PERSISTENT_ARG1_SHIFT           0
40903 #define SRC_GPR4_PERSISTENT_ARG1(x)              (((uint32_t)(((uint32_t)(x))<<SRC_GPR4_PERSISTENT_ARG1_SHIFT))&SRC_GPR4_PERSISTENT_ARG1_MASK)
40904 /* GPR5 Bit Fields */
40905 /* GPR6 Bit Fields */
40906 /* GPR7 Bit Fields */
40907 /* GPR8 Bit Fields */
40908 /* GPR9 Bit Fields */
40909 /* GPR10 Bit Fields */
40910 /* DDRC_RCR Bit Fields */
40911 #define SRC_DDRC_RCR_DDRC_PRST_MASK              0x1u
40912 #define SRC_DDRC_RCR_DDRC_PRST_SHIFT             0
40913 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK          0x2u
40914 #define SRC_DDRC_RCR_DDRC_CORE_RST_SHIFT         1
40915 #define SRC_DDRC_RCR_DOMAIN0_MASK                0x1000000u
40916 #define SRC_DDRC_RCR_DOMAIN0_SHIFT               24
40917 #define SRC_DDRC_RCR_DOMAIN1_MASK                0x2000000u
40918 #define SRC_DDRC_RCR_DOMAIN1_SHIFT               25
40919 #define SRC_DDRC_RCR_DOMAIN2_MASK                0x4000000u
40920 #define SRC_DDRC_RCR_DOMAIN2_SHIFT               26
40921 #define SRC_DDRC_RCR_DOMAIN3_MASK                0x8000000u
40922 #define SRC_DDRC_RCR_DOMAIN3_SHIFT               27
40923 #define SRC_DDRC_RCR_LOCK_MASK                   0x40000000u
40924 #define SRC_DDRC_RCR_LOCK_SHIFT                  30
40925 #define SRC_DDRC_RCR_DOM_EN_MASK                 0x80000000u
40926 #define SRC_DDRC_RCR_DOM_EN_SHIFT                31
40927 
40928 /*!
40929  * @}
40930  */ /* end of group SRC_Register_Masks */
40931 
40932 /* SRC - Peripheral instance base addresses */
40933 /** Peripheral SRC base address */
40934 #define SRC_BASE                                 (0x30390000u)
40935 /** Peripheral SRC base pointer */
40936 #define SRC                                      ((SRC_Type *)SRC_BASE)
40937 #define SRC_BASE_PTR                             (SRC)
40938 /** Array initializer of SRC peripheral base addresses */
40939 #define SRC_BASE_ADDRS                           { SRC_BASE }
40940 /** Array initializer of SRC peripheral base pointers */
40941 #define SRC_BASE_PTRS                            { SRC }
40942 /** Interrupt vectors for the SRC peripheral type */
40943 #define SRC_IRQS                                 { SRC_IRQn }
40944 /* ----------------------------------------------------------------------------
40945    -- SRC - Register accessor macros
40946    ---------------------------------------------------------------------------- */
40947 
40948 /*!
40949  * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros
40950  * @{
40951  */
40952 
40953 
40954 /* SRC - Register instance definitions */
40955 /* SRC */
40956 #define SRC_SCR                                  SRC_SCR_REG(SRC_BASE_PTR)
40957 #define SRC_A7RCR0                               SRC_A7RCR0_REG(SRC_BASE_PTR)
40958 #define SRC_A7RCR1                               SRC_A7RCR1_REG(SRC_BASE_PTR)
40959 #define SRC_M4RCR                                SRC_M4RCR_REG(SRC_BASE_PTR)
40960 #define SRC_ERCR                                 SRC_ERCR_REG(SRC_BASE_PTR)
40961 #define SRC_HSICPHY_RCR                          SRC_HSICPHY_RCR_REG(SRC_BASE_PTR)
40962 #define SRC_USBOPHY1_RCR                         SRC_USBOPHY1_RCR_REG(SRC_BASE_PTR)
40963 #define SRC_USBOPHY2_RCR                         SRC_USBOPHY2_RCR_REG(SRC_BASE_PTR)
40964 #define SRC_MIPIPHY_RCR                          SRC_MIPIPHY_RCR_REG(SRC_BASE_PTR)
40965 #define SRC_PCIEPHY_RCR                          SRC_PCIEPHY_RCR_REG(SRC_BASE_PTR)
40966 #define SRC_SBMR1                                SRC_SBMR1_REG(SRC_BASE_PTR)
40967 #define SRC_SRSR                                 SRC_SRSR_REG(SRC_BASE_PTR)
40968 #define SRC_SISR                                 SRC_SISR_REG(SRC_BASE_PTR)
40969 #define SRC_SIMR                                 SRC_SIMR_REG(SRC_BASE_PTR)
40970 #define SRC_SBMR2                                SRC_SBMR2_REG(SRC_BASE_PTR)
40971 #define SRC_GPR1                                 SRC_GPR1_REG(SRC_BASE_PTR)
40972 #define SRC_GPR2                                 SRC_GPR2_REG(SRC_BASE_PTR)
40973 #define SRC_GPR3                                 SRC_GPR3_REG(SRC_BASE_PTR)
40974 #define SRC_GPR4                                 SRC_GPR4_REG(SRC_BASE_PTR)
40975 #define SRC_GPR5                                 SRC_GPR5_REG(SRC_BASE_PTR)
40976 #define SRC_GPR6                                 SRC_GPR6_REG(SRC_BASE_PTR)
40977 #define SRC_GPR7                                 SRC_GPR7_REG(SRC_BASE_PTR)
40978 #define SRC_GPR8                                 SRC_GPR8_REG(SRC_BASE_PTR)
40979 #define SRC_GPR9                                 SRC_GPR9_REG(SRC_BASE_PTR)
40980 #define SRC_GPR10                                SRC_GPR10_REG(SRC_BASE_PTR)
40981 #define SRC_DDRC_RCR                             SRC_DDRC_RCR_REG(SRC_BASE_PTR)
40982 /*!
40983  * @}
40984  */ /* end of group SRC_Register_Accessor_Macros */
40985 
40986 
40987 /*!
40988  * @}
40989  */ /* end of group SRC_Peripheral */
40990 
40991 /* ----------------------------------------------------------------------------
40992    -- TEMPMON Peripheral Access Layer
40993    ---------------------------------------------------------------------------- */
40994 
40995 /*!
40996  * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
40997  * @{
40998  */
40999 
41000 /** TEMPMON - Register Layout Typedef */
41001 typedef struct {
41002   uint8_t RESERVED_0[768];
41003   __IO  uint32_t HW_ANADIG_TEMPSENSE0;                   /**< Anadig Tempsensor Control Register 0, offset: 0x300 */
41004   __IO  uint32_t HW_ANADIG_TEMPSENSE0_SET;               /**< Anadig Tempsensor Control Register 0, offset: 0x304 */
41005   __IO  uint32_t HW_ANADIG_TEMPSENSE0_CLR;               /**< Anadig Tempsensor Control Register 0, offset: 0x308 */
41006   __IO  uint32_t HW_ANADIG_TEMPSENSE0_TOG;               /**< Anadig Tempsensor Control Register 0, offset: 0x30C */
41007   __IO  uint32_t HW_ANADIG_TEMPSENSE1;                   /**< Anadig Tempsensor Control Register 1, offset: 0x310 */
41008   __IO  uint32_t HW_ANADIG_TEMPSENSE1_SET;               /**< Anadig Tempsensor Control Register 1, offset: 0x314 */
41009   __IO  uint32_t HW_ANADIG_TEMPSENSE1_CLR;               /**< Anadig Tempsensor Control Register 1, offset: 0x318 */
41010   __IO  uint32_t HW_ANADIG_TEMPSENSE1_TOG;               /**< Anadig Tempsensor Control Register 1, offset: 0x31C */
41011   __IO  uint32_t HW_ANADIG_TEMPSENSE_TRIM;               /**< Anadig Tempsensor Trim Control Register, offset: 0x320 */
41012   __IO  uint32_t HW_ANADIG_TEMPSENSE_TRIM_SET;           /**< Anadig Tempsensor Trim Control Register, offset: 0x324 */
41013   __IO  uint32_t HW_ANADIG_TEMPSENSE_TRIM_CLR;           /**< Anadig Tempsensor Trim Control Register, offset: 0x328 */
41014   __IO  uint32_t HW_ANADIG_TEMPSENSE_TRIM_TOG;           /**< Anadig Tempsensor Trim Control Register, offset: 0x32C */
41015 } TEMPMON_Type, *TEMPMON_MemMapPtr;
41016 /* ----------------------------------------------------------------------------
41017    -- TEMPMON - Register accessor macros
41018    ---------------------------------------------------------------------------- */
41019 
41020 /*!
41021  * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros
41022  * @{
41023  */
41024 
41025 
41026 /* TEMPMON - Register accessors */
41027 #define TEMPMON_HW_ANADIG_TEMPSENSE0_REG(base)   ((base)->HW_ANADIG_TEMPSENSE0)
41028 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_SET)
41029 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_CLR)
41030 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_TOG)
41031 #define TEMPMON_HW_ANADIG_TEMPSENSE1_REG(base)   ((base)->HW_ANADIG_TEMPSENSE1)
41032 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_SET)
41033 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_CLR)
41034 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_TOG)
41035 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM)
41036 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_SET)
41037 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_CLR)
41038 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_TOG)
41039 
41040 /*!
41041  * @}
41042  */ /* end of group TEMPMON_Register_Accessor_Macros */
41043 /* ----------------------------------------------------------------------------
41044    -- TEMPMON Register Masks
41045    ---------------------------------------------------------------------------- */
41046 
41047 /*!
41048  * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks
41049  * @{
41050  */
41051 
41052 /* HW_ANADIG_TEMPSENSE0 Bit Fields */
41053 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
41054 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
41055 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK)
41056 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u
41057 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9
41058 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK)
41059 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u
41060 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18
41061 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK)
41062 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK  0xF8000000u
41063 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27
41064 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK)
41065 /* HW_ANADIG_TEMPSENSE0_SET Bit Fields */
41066 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu
41067 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0
41068 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK)
41069 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u
41070 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9
41071 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK)
41072 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u
41073 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18
41074 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK)
41075 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u
41076 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27
41077 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK)
41078 /* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */
41079 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu
41080 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0
41081 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK)
41082 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u
41083 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9
41084 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK)
41085 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u
41086 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18
41087 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK)
41088 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u
41089 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27
41090 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)
41091 /* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */
41092 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu
41093 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0
41094 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK)
41095 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u
41096 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9
41097 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK)
41098 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u
41099 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18
41100 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK)
41101 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u
41102 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27
41103 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK)
41104 /* HW_ANADIG_TEMPSENSE1 Bit Fields */
41105 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu
41106 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0
41107 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
41108 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u
41109 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9
41110 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u
41111 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10
41112 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u
41113 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11
41114 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK  0xF000u
41115 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12
41116 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK)
41117 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u
41118 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16
41119 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK)
41120 /* HW_ANADIG_TEMPSENSE1_SET Bit Fields */
41121 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu
41122 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0
41123 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK)
41124 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u
41125 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9
41126 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u
41127 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10
41128 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u
41129 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11
41130 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u
41131 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12
41132 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK)
41133 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u
41134 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16
41135 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
41136 /* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */
41137 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu
41138 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0
41139 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK)
41140 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u
41141 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9
41142 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u
41143 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10
41144 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u
41145 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11
41146 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u
41147 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12
41148 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK)
41149 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u
41150 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16
41151 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
41152 /* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */
41153 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu
41154 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0
41155 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK)
41156 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u
41157 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9
41158 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u
41159 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10
41160 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u
41161 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11
41162 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u
41163 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12
41164 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK)
41165 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u
41166 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16
41167 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
41168 /* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */
41169 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu
41170 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0
41171 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK)
41172 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u
41173 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5
41174 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK)
41175 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u
41176 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7
41177 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u
41178 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8
41179 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK)
41180 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u
41181 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17
41182 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK)
41183 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u
41184 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20
41185 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK)
41186 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u
41187 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24
41188 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK)
41189 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u
41190 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29
41191 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK)
41192 /* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */
41193 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu
41194 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0
41195 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK)
41196 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u
41197 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5
41198 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK)
41199 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u
41200 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7
41201 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u
41202 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8
41203 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK)
41204 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u
41205 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17
41206 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK)
41207 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u
41208 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20
41209 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK)
41210 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u
41211 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24
41212 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK)
41213 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u
41214 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29
41215 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK)
41216 /* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */
41217 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu
41218 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0
41219 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK)
41220 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u
41221 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5
41222 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK)
41223 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u
41224 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7
41225 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u
41226 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8
41227 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK)
41228 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u
41229 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17
41230 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK)
41231 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u
41232 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20
41233 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK)
41234 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u
41235 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24
41236 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK)
41237 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u
41238 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29
41239 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK)
41240 /* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */
41241 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu
41242 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0
41243 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK)
41244 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u
41245 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5
41246 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK)
41247 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u
41248 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7
41249 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u
41250 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8
41251 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK)
41252 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u
41253 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17
41254 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK)
41255 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u
41256 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20
41257 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK)
41258 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u
41259 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24
41260 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK)
41261 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u
41262 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
41263 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
41264 
41265 /*!
41266  * @}
41267  */ /* end of group TEMPMON_Register_Masks */
41268 
41269 /* TEMPMON - Peripheral instance base addresses */
41270 /** Peripheral TEMPMON base address */
41271 #define TEMPMON_BASE                             (0x30360000u)
41272 /** Peripheral TEMPMON base pointer */
41273 #define TEMPMON                                  ((TEMPMON_Type *)TEMPMON_BASE)
41274 #define TEMPMON_BASE_PTR                         (TEMPMON)
41275 /** Array initializer of TEMPMON peripheral base addresses */
41276 #define TEMPMON_BASE_ADDRS                       { TEMPMON_BASE }
41277 /** Array initializer of TEMPMON peripheral base pointers */
41278 #define TEMPMON_BASE_PTRS                        { TEMPMON }
41279 /* ----------------------------------------------------------------------------
41280    -- TEMPMON - Register accessor macros
41281    ---------------------------------------------------------------------------- */
41282 
41283 /*!
41284  * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros
41285  * @{
41286  */
41287 
41288 
41289 /* TEMPMON - Register instance definitions */
41290 /* TEMPMON */
41291 #define TEMPMON_HW_ANADIG_TEMPSENSE0             TEMPMON_HW_ANADIG_TEMPSENSE0_REG(TEMPMON_BASE_PTR)
41292 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET         TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(TEMPMON_BASE_PTR)
41293 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR         TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(TEMPMON_BASE_PTR)
41294 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG         TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(TEMPMON_BASE_PTR)
41295 #define TEMPMON_HW_ANADIG_TEMPSENSE1             TEMPMON_HW_ANADIG_TEMPSENSE1_REG(TEMPMON_BASE_PTR)
41296 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET         TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(TEMPMON_BASE_PTR)
41297 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR         TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(TEMPMON_BASE_PTR)
41298 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG         TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(TEMPMON_BASE_PTR)
41299 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM         TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(TEMPMON_BASE_PTR)
41300 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET     TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(TEMPMON_BASE_PTR)
41301 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR     TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(TEMPMON_BASE_PTR)
41302 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG     TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(TEMPMON_BASE_PTR)
41303 /*!
41304  * @}
41305  */ /* end of group TEMPMON_Register_Accessor_Macros */
41306 
41307 
41308 /*!
41309  * @}
41310  */ /* end of group TEMPMON_Peripheral */
41311 
41312 /* ----------------------------------------------------------------------------
41313    -- UART Peripheral Access Layer
41314    ---------------------------------------------------------------------------- */
41315 
41316 /*!
41317  * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
41318  * @{
41319  */
41320 
41321 /** UART - Register Layout Typedef */
41322 typedef struct {
41323   __I   uint32_t URXD;                                   /**< UART Receiver Register, offset: 0x0 */
41324   uint8_t RESERVED_0[60];
41325   __O   uint32_t UTXD;                                   /**< UART Transmitter Register, offset: 0x40 */
41326   uint8_t RESERVED_1[60];
41327   __IO  uint32_t UCR1;                                   /**< UART Control Register 1, offset: 0x80 */
41328   __IO  uint32_t UCR2;                                   /**< UART Control Register 2, offset: 0x84 */
41329   __IO  uint32_t UCR3;                                   /**< UART Control Register 3, offset: 0x88 */
41330   __IO  uint32_t UCR4;                                   /**< UART Control Register 4, offset: 0x8C */
41331   __IO  uint32_t UFCR;                                   /**< UART FIFO Control Register, offset: 0x90 */
41332   __IO  uint32_t USR1;                                   /**< UART Status Register 1, offset: 0x94 */
41333   __IO  uint32_t USR2;                                   /**< UART Status Register 2, offset: 0x98 */
41334   __IO  uint32_t UESC;                                   /**< UART Escape Character Register, offset: 0x9C */
41335   __IO  uint32_t UTIM;                                   /**< UART Escape Timer Register, offset: 0xA0 */
41336   __IO  uint32_t UBIR;                                   /**< UART BRM Incremental Register, offset: 0xA4 */
41337   __IO  uint32_t UBMR;                                   /**< UART BRM Modulator Register, offset: 0xA8 */
41338   __I   uint32_t UBRC;                                   /**< UART Baud Rate Count Register, offset: 0xAC */
41339   __IO  uint32_t ONEMS;                                  /**< UART One Millisecond Register, offset: 0xB0 */
41340   __IO  uint32_t UTS;                                    /**< UART Test Register, offset: 0xB4 */
41341   __IO  uint32_t UMCR;                                   /**< UART RS-485 Mode Control Register, offset: 0xB8 */
41342 } UART_Type, *UART_MemMapPtr;
41343 /* ----------------------------------------------------------------------------
41344    -- UART - Register accessor macros
41345    ---------------------------------------------------------------------------- */
41346 
41347 /*!
41348  * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
41349  * @{
41350  */
41351 
41352 
41353 /* UART - Register accessors */
41354 #define UART_URXD_REG(base)                      ((base)->URXD)
41355 #define UART_UTXD_REG(base)                      ((base)->UTXD)
41356 #define UART_UCR1_REG(base)                      ((base)->UCR1)
41357 #define UART_UCR2_REG(base)                      ((base)->UCR2)
41358 #define UART_UCR3_REG(base)                      ((base)->UCR3)
41359 #define UART_UCR4_REG(base)                      ((base)->UCR4)
41360 #define UART_UFCR_REG(base)                      ((base)->UFCR)
41361 #define UART_USR1_REG(base)                      ((base)->USR1)
41362 #define UART_USR2_REG(base)                      ((base)->USR2)
41363 #define UART_UESC_REG(base)                      ((base)->UESC)
41364 #define UART_UTIM_REG(base)                      ((base)->UTIM)
41365 #define UART_UBIR_REG(base)                      ((base)->UBIR)
41366 #define UART_UBMR_REG(base)                      ((base)->UBMR)
41367 #define UART_UBRC_REG(base)                      ((base)->UBRC)
41368 #define UART_ONEMS_REG(base)                     ((base)->ONEMS)
41369 #define UART_UTS_REG(base)                       ((base)->UTS)
41370 #define UART_UMCR_REG(base)                      ((base)->UMCR)
41371 
41372 /*!
41373  * @}
41374  */ /* end of group UART_Register_Accessor_Macros */
41375 /* ----------------------------------------------------------------------------
41376    -- UART Register Masks
41377    ---------------------------------------------------------------------------- */
41378 
41379 /*!
41380  * @addtogroup UART_Register_Masks UART Register Masks
41381  * @{
41382  */
41383 
41384 /* URXD Bit Fields */
41385 #define UART_URXD_RX_DATA_MASK                   0xFFu
41386 #define UART_URXD_RX_DATA_SHIFT                  0
41387 #define UART_URXD_RX_DATA(x)                     (((uint32_t)(((uint32_t)(x))<<UART_URXD_RX_DATA_SHIFT))&UART_URXD_RX_DATA_MASK)
41388 #define UART_URXD_PRERR_MASK                     0x400u
41389 #define UART_URXD_PRERR_SHIFT                    10
41390 #define UART_URXD_BRK_MASK                       0x800u
41391 #define UART_URXD_BRK_SHIFT                      11
41392 #define UART_URXD_FRMERR_MASK                    0x1000u
41393 #define UART_URXD_FRMERR_SHIFT                   12
41394 #define UART_URXD_OVRRUN_MASK                    0x2000u
41395 #define UART_URXD_OVRRUN_SHIFT                   13
41396 #define UART_URXD_ERR_MASK                       0x4000u
41397 #define UART_URXD_ERR_SHIFT                      14
41398 #define UART_URXD_CHARRDY_MASK                   0x8000u
41399 #define UART_URXD_CHARRDY_SHIFT                  15
41400 /* UTXD Bit Fields */
41401 #define UART_UTXD_TX_DATA_MASK                   0xFFu
41402 #define UART_UTXD_TX_DATA_SHIFT                  0
41403 #define UART_UTXD_TX_DATA(x)                     (((uint32_t)(((uint32_t)(x))<<UART_UTXD_TX_DATA_SHIFT))&UART_UTXD_TX_DATA_MASK)
41404 /* UCR1 Bit Fields */
41405 #define UART_UCR1_UARTEN_MASK                    0x1u
41406 #define UART_UCR1_UARTEN_SHIFT                   0
41407 #define UART_UCR1_DOZE_MASK                      0x2u
41408 #define UART_UCR1_DOZE_SHIFT                     1
41409 #define UART_UCR1_ATDMAEN_MASK                   0x4u
41410 #define UART_UCR1_ATDMAEN_SHIFT                  2
41411 #define UART_UCR1_TXDMAEN_MASK                   0x8u
41412 #define UART_UCR1_TXDMAEN_SHIFT                  3
41413 #define UART_UCR1_SNDBRK_MASK                    0x10u
41414 #define UART_UCR1_SNDBRK_SHIFT                   4
41415 #define UART_UCR1_RTSDEN_MASK                    0x20u
41416 #define UART_UCR1_RTSDEN_SHIFT                   5
41417 #define UART_UCR1_TXMPTYEN_MASK                  0x40u
41418 #define UART_UCR1_TXMPTYEN_SHIFT                 6
41419 #define UART_UCR1_IREN_MASK                      0x80u
41420 #define UART_UCR1_IREN_SHIFT                     7
41421 #define UART_UCR1_RXDMAEN_MASK                   0x100u
41422 #define UART_UCR1_RXDMAEN_SHIFT                  8
41423 #define UART_UCR1_RRDYEN_MASK                    0x200u
41424 #define UART_UCR1_RRDYEN_SHIFT                   9
41425 #define UART_UCR1_ICD_MASK                       0xC00u
41426 #define UART_UCR1_ICD_SHIFT                      10
41427 #define UART_UCR1_ICD(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UCR1_ICD_SHIFT))&UART_UCR1_ICD_MASK)
41428 #define UART_UCR1_IDEN_MASK                      0x1000u
41429 #define UART_UCR1_IDEN_SHIFT                     12
41430 #define UART_UCR1_TRDYEN_MASK                    0x2000u
41431 #define UART_UCR1_TRDYEN_SHIFT                   13
41432 #define UART_UCR1_ADBR_MASK                      0x4000u
41433 #define UART_UCR1_ADBR_SHIFT                     14
41434 #define UART_UCR1_ADEN_MASK                      0x8000u
41435 #define UART_UCR1_ADEN_SHIFT                     15
41436 /* UCR2 Bit Fields */
41437 #define UART_UCR2_SRST_MASK                      0x1u
41438 #define UART_UCR2_SRST_SHIFT                     0
41439 #define UART_UCR2_RXEN_MASK                      0x2u
41440 #define UART_UCR2_RXEN_SHIFT                     1
41441 #define UART_UCR2_TXEN_MASK                      0x4u
41442 #define UART_UCR2_TXEN_SHIFT                     2
41443 #define UART_UCR2_ATEN_MASK                      0x8u
41444 #define UART_UCR2_ATEN_SHIFT                     3
41445 #define UART_UCR2_RTSEN_MASK                     0x10u
41446 #define UART_UCR2_RTSEN_SHIFT                    4
41447 #define UART_UCR2_WS_MASK                        0x20u
41448 #define UART_UCR2_WS_SHIFT                       5
41449 #define UART_UCR2_STPB_MASK                      0x40u
41450 #define UART_UCR2_STPB_SHIFT                     6
41451 #define UART_UCR2_PROE_MASK                      0x80u
41452 #define UART_UCR2_PROE_SHIFT                     7
41453 #define UART_UCR2_PREN_MASK                      0x100u
41454 #define UART_UCR2_PREN_SHIFT                     8
41455 #define UART_UCR2_RTEC_MASK                      0x600u
41456 #define UART_UCR2_RTEC_SHIFT                     9
41457 #define UART_UCR2_RTEC(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UCR2_RTEC_SHIFT))&UART_UCR2_RTEC_MASK)
41458 #define UART_UCR2_ESCEN_MASK                     0x800u
41459 #define UART_UCR2_ESCEN_SHIFT                    11
41460 #define UART_UCR2_CTS_MASK                       0x1000u
41461 #define UART_UCR2_CTS_SHIFT                      12
41462 #define UART_UCR2_CTSC_MASK                      0x2000u
41463 #define UART_UCR2_CTSC_SHIFT                     13
41464 #define UART_UCR2_IRTS_MASK                      0x4000u
41465 #define UART_UCR2_IRTS_SHIFT                     14
41466 #define UART_UCR2_ESCI_MASK                      0x8000u
41467 #define UART_UCR2_ESCI_SHIFT                     15
41468 /* UCR3 Bit Fields */
41469 #define UART_UCR3_ACIEN_MASK                     0x1u
41470 #define UART_UCR3_ACIEN_SHIFT                    0
41471 #define UART_UCR3_INVT_MASK                      0x2u
41472 #define UART_UCR3_INVT_SHIFT                     1
41473 #define UART_UCR3_RXDMUXSEL_MASK                 0x4u
41474 #define UART_UCR3_RXDMUXSEL_SHIFT                2
41475 #define UART_UCR3_DTRDEN_MASK                    0x8u
41476 #define UART_UCR3_DTRDEN_SHIFT                   3
41477 #define UART_UCR3_AWAKEN_MASK                    0x10u
41478 #define UART_UCR3_AWAKEN_SHIFT                   4
41479 #define UART_UCR3_AIRINTEN_MASK                  0x20u
41480 #define UART_UCR3_AIRINTEN_SHIFT                 5
41481 #define UART_UCR3_RXDSEN_MASK                    0x40u
41482 #define UART_UCR3_RXDSEN_SHIFT                   6
41483 #define UART_UCR3_ADNIMP_MASK                    0x80u
41484 #define UART_UCR3_ADNIMP_SHIFT                   7
41485 #define UART_UCR3_RI_MASK                        0x100u
41486 #define UART_UCR3_RI_SHIFT                       8
41487 #define UART_UCR3_DCD_MASK                       0x200u
41488 #define UART_UCR3_DCD_SHIFT                      9
41489 #define UART_UCR3_DSR_MASK                       0x400u
41490 #define UART_UCR3_DSR_SHIFT                      10
41491 #define UART_UCR3_FRAERREN_MASK                  0x800u
41492 #define UART_UCR3_FRAERREN_SHIFT                 11
41493 #define UART_UCR3_PARERREN_MASK                  0x1000u
41494 #define UART_UCR3_PARERREN_SHIFT                 12
41495 #define UART_UCR3_DTREN_MASK                     0x2000u
41496 #define UART_UCR3_DTREN_SHIFT                    13
41497 #define UART_UCR3_DPEC_MASK                      0xC000u
41498 #define UART_UCR3_DPEC_SHIFT                     14
41499 #define UART_UCR3_DPEC(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UCR3_DPEC_SHIFT))&UART_UCR3_DPEC_MASK)
41500 /* UCR4 Bit Fields */
41501 #define UART_UCR4_DREN_MASK                      0x1u
41502 #define UART_UCR4_DREN_SHIFT                     0
41503 #define UART_UCR4_OREN_MASK                      0x2u
41504 #define UART_UCR4_OREN_SHIFT                     1
41505 #define UART_UCR4_BKEN_MASK                      0x4u
41506 #define UART_UCR4_BKEN_SHIFT                     2
41507 #define UART_UCR4_TCEN_MASK                      0x8u
41508 #define UART_UCR4_TCEN_SHIFT                     3
41509 #define UART_UCR4_LPBYP_MASK                     0x10u
41510 #define UART_UCR4_LPBYP_SHIFT                    4
41511 #define UART_UCR4_IRSC_MASK                      0x20u
41512 #define UART_UCR4_IRSC_SHIFT                     5
41513 #define UART_UCR4_IDDMAEN_MASK                   0x40u
41514 #define UART_UCR4_IDDMAEN_SHIFT                  6
41515 #define UART_UCR4_WKEN_MASK                      0x80u
41516 #define UART_UCR4_WKEN_SHIFT                     7
41517 #define UART_UCR4_ENIRI_MASK                     0x100u
41518 #define UART_UCR4_ENIRI_SHIFT                    8
41519 #define UART_UCR4_INVR_MASK                      0x200u
41520 #define UART_UCR4_INVR_SHIFT                     9
41521 #define UART_UCR4_CTSTL_MASK                     0xFC00u
41522 #define UART_UCR4_CTSTL_SHIFT                    10
41523 #define UART_UCR4_CTSTL(x)                       (((uint32_t)(((uint32_t)(x))<<UART_UCR4_CTSTL_SHIFT))&UART_UCR4_CTSTL_MASK)
41524 /* UFCR Bit Fields */
41525 #define UART_UFCR_RXTL_MASK                      0x3Fu
41526 #define UART_UFCR_RXTL_SHIFT                     0
41527 #define UART_UFCR_RXTL(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RXTL_SHIFT))&UART_UFCR_RXTL_MASK)
41528 #define UART_UFCR_DCEDTE_MASK                    0x40u
41529 #define UART_UFCR_DCEDTE_SHIFT                   6
41530 #define UART_UFCR_RFDIV_MASK                     0x380u
41531 #define UART_UFCR_RFDIV_SHIFT                    7
41532 #define UART_UFCR_RFDIV(x)                       (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RFDIV_SHIFT))&UART_UFCR_RFDIV_MASK)
41533 #define UART_UFCR_TXTL_MASK                      0xFC00u
41534 #define UART_UFCR_TXTL_SHIFT                     10
41535 #define UART_UFCR_TXTL(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UFCR_TXTL_SHIFT))&UART_UFCR_TXTL_MASK)
41536 /* USR1 Bit Fields */
41537 #define UART_USR1_SAD_MASK                       0x8u
41538 #define UART_USR1_SAD_SHIFT                      3
41539 #define UART_USR1_AWAKE_MASK                     0x10u
41540 #define UART_USR1_AWAKE_SHIFT                    4
41541 #define UART_USR1_AIRINT_MASK                    0x20u
41542 #define UART_USR1_AIRINT_SHIFT                   5
41543 #define UART_USR1_RXDS_MASK                      0x40u
41544 #define UART_USR1_RXDS_SHIFT                     6
41545 #define UART_USR1_DTRD_MASK                      0x80u
41546 #define UART_USR1_DTRD_SHIFT                     7
41547 #define UART_USR1_AGTIM_MASK                     0x100u
41548 #define UART_USR1_AGTIM_SHIFT                    8
41549 #define UART_USR1_RRDY_MASK                      0x200u
41550 #define UART_USR1_RRDY_SHIFT                     9
41551 #define UART_USR1_FRAMERR_MASK                   0x400u
41552 #define UART_USR1_FRAMERR_SHIFT                  10
41553 #define UART_USR1_ESCF_MASK                      0x800u
41554 #define UART_USR1_ESCF_SHIFT                     11
41555 #define UART_USR1_RTSD_MASK                      0x1000u
41556 #define UART_USR1_RTSD_SHIFT                     12
41557 #define UART_USR1_TRDY_MASK                      0x2000u
41558 #define UART_USR1_TRDY_SHIFT                     13
41559 #define UART_USR1_RTSS_MASK                      0x4000u
41560 #define UART_USR1_RTSS_SHIFT                     14
41561 #define UART_USR1_PARITYERR_MASK                 0x8000u
41562 #define UART_USR1_PARITYERR_SHIFT                15
41563 /* USR2 Bit Fields */
41564 #define UART_USR2_RDR_MASK                       0x1u
41565 #define UART_USR2_RDR_SHIFT                      0
41566 #define UART_USR2_ORE_MASK                       0x2u
41567 #define UART_USR2_ORE_SHIFT                      1
41568 #define UART_USR2_BRCD_MASK                      0x4u
41569 #define UART_USR2_BRCD_SHIFT                     2
41570 #define UART_USR2_TXDC_MASK                      0x8u
41571 #define UART_USR2_TXDC_SHIFT                     3
41572 #define UART_USR2_RTSF_MASK                      0x10u
41573 #define UART_USR2_RTSF_SHIFT                     4
41574 #define UART_USR2_DCDIN_MASK                     0x20u
41575 #define UART_USR2_DCDIN_SHIFT                    5
41576 #define UART_USR2_DCDDELT_MASK                   0x40u
41577 #define UART_USR2_DCDDELT_SHIFT                  6
41578 #define UART_USR2_WAKE_MASK                      0x80u
41579 #define UART_USR2_WAKE_SHIFT                     7
41580 #define UART_USR2_IRINT_MASK                     0x100u
41581 #define UART_USR2_IRINT_SHIFT                    8
41582 #define UART_USR2_RIIN_MASK                      0x200u
41583 #define UART_USR2_RIIN_SHIFT                     9
41584 #define UART_USR2_RIDELT_MASK                    0x400u
41585 #define UART_USR2_RIDELT_SHIFT                   10
41586 #define UART_USR2_ACST_MASK                      0x800u
41587 #define UART_USR2_ACST_SHIFT                     11
41588 #define UART_USR2_IDLE_MASK                      0x1000u
41589 #define UART_USR2_IDLE_SHIFT                     12
41590 #define UART_USR2_DTRF_MASK                      0x2000u
41591 #define UART_USR2_DTRF_SHIFT                     13
41592 #define UART_USR2_TXFE_MASK                      0x4000u
41593 #define UART_USR2_TXFE_SHIFT                     14
41594 #define UART_USR2_ADET_MASK                      0x8000u
41595 #define UART_USR2_ADET_SHIFT                     15
41596 /* UESC Bit Fields */
41597 #define UART_UESC_ESC_CHAR_MASK                  0xFFu
41598 #define UART_UESC_ESC_CHAR_SHIFT                 0
41599 #define UART_UESC_ESC_CHAR(x)                    (((uint32_t)(((uint32_t)(x))<<UART_UESC_ESC_CHAR_SHIFT))&UART_UESC_ESC_CHAR_MASK)
41600 /* UTIM Bit Fields */
41601 #define UART_UTIM_TIM_MASK                       0xFFFu
41602 #define UART_UTIM_TIM_SHIFT                      0
41603 #define UART_UTIM_TIM(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UTIM_TIM_SHIFT))&UART_UTIM_TIM_MASK)
41604 /* UBIR Bit Fields */
41605 #define UART_UBIR_INC_MASK                       0xFFFFu
41606 #define UART_UBIR_INC_SHIFT                      0
41607 #define UART_UBIR_INC(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UBIR_INC_SHIFT))&UART_UBIR_INC_MASK)
41608 /* UBMR Bit Fields */
41609 #define UART_UBMR_MOD_MASK                       0xFFFFu
41610 #define UART_UBMR_MOD_SHIFT                      0
41611 #define UART_UBMR_MOD(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UBMR_MOD_SHIFT))&UART_UBMR_MOD_MASK)
41612 /* UBRC Bit Fields */
41613 #define UART_UBRC_BCNT_MASK                      0xFFFFu
41614 #define UART_UBRC_BCNT_SHIFT                     0
41615 #define UART_UBRC_BCNT(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UBRC_BCNT_SHIFT))&UART_UBRC_BCNT_MASK)
41616 /* ONEMS Bit Fields */
41617 #define UART_ONEMS_ONEMS_MASK                    0xFFFFFFu
41618 #define UART_ONEMS_ONEMS_SHIFT                   0
41619 #define UART_ONEMS_ONEMS(x)                      (((uint32_t)(((uint32_t)(x))<<UART_ONEMS_ONEMS_SHIFT))&UART_ONEMS_ONEMS_MASK)
41620 /* UTS Bit Fields */
41621 #define UART_UTS_SOFTRST_MASK                    0x1u
41622 #define UART_UTS_SOFTRST_SHIFT                   0
41623 #define UART_UTS_RXFULL_MASK                     0x8u
41624 #define UART_UTS_RXFULL_SHIFT                    3
41625 #define UART_UTS_TXFULL_MASK                     0x10u
41626 #define UART_UTS_TXFULL_SHIFT                    4
41627 #define UART_UTS_RXEMPTY_MASK                    0x20u
41628 #define UART_UTS_RXEMPTY_SHIFT                   5
41629 #define UART_UTS_TXEMPTY_MASK                    0x40u
41630 #define UART_UTS_TXEMPTY_SHIFT                   6
41631 #define UART_UTS_RXDBG_MASK                      0x200u
41632 #define UART_UTS_RXDBG_SHIFT                     9
41633 #define UART_UTS_LOOPIR_MASK                     0x400u
41634 #define UART_UTS_LOOPIR_SHIFT                    10
41635 #define UART_UTS_DBGEN_MASK                      0x800u
41636 #define UART_UTS_DBGEN_SHIFT                     11
41637 #define UART_UTS_LOOP_MASK                       0x1000u
41638 #define UART_UTS_LOOP_SHIFT                      12
41639 #define UART_UTS_FRCPERR_MASK                    0x2000u
41640 #define UART_UTS_FRCPERR_SHIFT                   13
41641 /* UMCR Bit Fields */
41642 #define UART_UMCR_MDEN_MASK                      0x1u
41643 #define UART_UMCR_MDEN_SHIFT                     0
41644 #define UART_UMCR_SLAM_MASK                      0x2u
41645 #define UART_UMCR_SLAM_SHIFT                     1
41646 #define UART_UMCR_TXB8_MASK                      0x4u
41647 #define UART_UMCR_TXB8_SHIFT                     2
41648 #define UART_UMCR_SADEN_MASK                     0x8u
41649 #define UART_UMCR_SADEN_SHIFT                    3
41650 #define UART_UMCR_SLADDR_MASK                    0xFF00u
41651 #define UART_UMCR_SLADDR_SHIFT                   8
41652 #define UART_UMCR_SLADDR(x)                      (((uint32_t)(((uint32_t)(x))<<UART_UMCR_SLADDR_SHIFT))&UART_UMCR_SLADDR_MASK)
41653 
41654 /*!
41655  * @}
41656  */ /* end of group UART_Register_Masks */
41657 
41658 /* UART - Peripheral instance base addresses */
41659 /** Peripheral UART1 base address */
41660 #define UART1_BASE                               (0x30860000u)
41661 /** Peripheral UART1 base pointer */
41662 #define UART1                                    ((UART_Type *)UART1_BASE)
41663 #define UART1_BASE_PTR                           (UART1)
41664 /** Peripheral UART2 base address */
41665 #define UART2_BASE                               (0x30890000u)
41666 /** Peripheral UART2 base pointer */
41667 #define UART2                                    ((UART_Type *)UART2_BASE)
41668 #define UART2_BASE_PTR                           (UART2)
41669 /** Peripheral UART3 base address */
41670 #define UART3_BASE                               (0x30880000u)
41671 /** Peripheral UART3 base pointer */
41672 #define UART3                                    ((UART_Type *)UART3_BASE)
41673 #define UART3_BASE_PTR                           (UART3)
41674 /** Peripheral UART4 base address */
41675 #define UART4_BASE                               (0x30A60000u)
41676 /** Peripheral UART4 base pointer */
41677 #define UART4                                    ((UART_Type *)UART4_BASE)
41678 #define UART4_BASE_PTR                           (UART4)
41679 /** Peripheral UART5 base address */
41680 #define UART5_BASE                               (0x30A70000u)
41681 /** Peripheral UART5 base pointer */
41682 #define UART5                                    ((UART_Type *)UART5_BASE)
41683 #define UART5_BASE_PTR                           (UART5)
41684 /** Peripheral UART6 base address */
41685 #define UART6_BASE                               (0x30A80000u)
41686 /** Peripheral UART6 base pointer */
41687 #define UART6                                    ((UART_Type *)UART6_BASE)
41688 #define UART6_BASE_PTR                           (UART6)
41689 /** Peripheral UART7 base address */
41690 #define UART7_BASE                               (0x30A90000u)
41691 /** Peripheral UART7 base pointer */
41692 #define UART7                                    ((UART_Type *)UART7_BASE)
41693 #define UART7_BASE_PTR                           (UART7)
41694 /** Array initializer of UART peripheral base addresses */
41695 #define UART_BASE_ADDRS                          { UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE }
41696 /** Array initializer of UART peripheral base pointers */
41697 #define UART_BASE_PTRS                           { UART1, UART2, UART3, UART4, UART5, UART6, UART7 }
41698 /** Interrupt vectors for the UART peripheral type */
41699 #define UART_IRQS                                { UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn }
41700 /* ----------------------------------------------------------------------------
41701    -- UART - Register accessor macros
41702    ---------------------------------------------------------------------------- */
41703 
41704 /*!
41705  * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
41706  * @{
41707  */
41708 
41709 
41710 /* UART - Register instance definitions */
41711 /* UART1 */
41712 #define UART1_URXD                               UART_URXD_REG(UART1_BASE_PTR)
41713 #define UART1_UTXD                               UART_UTXD_REG(UART1_BASE_PTR)
41714 #define UART1_UCR1                               UART_UCR1_REG(UART1_BASE_PTR)
41715 #define UART1_UCR2                               UART_UCR2_REG(UART1_BASE_PTR)
41716 #define UART1_UCR3                               UART_UCR3_REG(UART1_BASE_PTR)
41717 #define UART1_UCR4                               UART_UCR4_REG(UART1_BASE_PTR)
41718 #define UART1_UFCR                               UART_UFCR_REG(UART1_BASE_PTR)
41719 #define UART1_USR1                               UART_USR1_REG(UART1_BASE_PTR)
41720 #define UART1_USR2                               UART_USR2_REG(UART1_BASE_PTR)
41721 #define UART1_UESC                               UART_UESC_REG(UART1_BASE_PTR)
41722 #define UART1_UTIM                               UART_UTIM_REG(UART1_BASE_PTR)
41723 #define UART1_UBIR                               UART_UBIR_REG(UART1_BASE_PTR)
41724 #define UART1_UBMR                               UART_UBMR_REG(UART1_BASE_PTR)
41725 #define UART1_UBRC                               UART_UBRC_REG(UART1_BASE_PTR)
41726 #define UART1_ONEMS                              UART_ONEMS_REG(UART1_BASE_PTR)
41727 #define UART1_UTS                                UART_UTS_REG(UART1_BASE_PTR)
41728 #define UART1_UMCR                               UART_UMCR_REG(UART1_BASE_PTR)
41729 /* UART2 */
41730 #define UART2_URXD                               UART_URXD_REG(UART2_BASE_PTR)
41731 #define UART2_UTXD                               UART_UTXD_REG(UART2_BASE_PTR)
41732 #define UART2_UCR1                               UART_UCR1_REG(UART2_BASE_PTR)
41733 #define UART2_UCR2                               UART_UCR2_REG(UART2_BASE_PTR)
41734 #define UART2_UCR3                               UART_UCR3_REG(UART2_BASE_PTR)
41735 #define UART2_UCR4                               UART_UCR4_REG(UART2_BASE_PTR)
41736 #define UART2_UFCR                               UART_UFCR_REG(UART2_BASE_PTR)
41737 #define UART2_USR1                               UART_USR1_REG(UART2_BASE_PTR)
41738 #define UART2_USR2                               UART_USR2_REG(UART2_BASE_PTR)
41739 #define UART2_UESC                               UART_UESC_REG(UART2_BASE_PTR)
41740 #define UART2_UTIM                               UART_UTIM_REG(UART2_BASE_PTR)
41741 #define UART2_UBIR                               UART_UBIR_REG(UART2_BASE_PTR)
41742 #define UART2_UBMR                               UART_UBMR_REG(UART2_BASE_PTR)
41743 #define UART2_UBRC                               UART_UBRC_REG(UART2_BASE_PTR)
41744 #define UART2_ONEMS                              UART_ONEMS_REG(UART2_BASE_PTR)
41745 #define UART2_UTS                                UART_UTS_REG(UART2_BASE_PTR)
41746 #define UART2_UMCR                               UART_UMCR_REG(UART2_BASE_PTR)
41747 /* UART3 */
41748 #define UART3_URXD                               UART_URXD_REG(UART3_BASE_PTR)
41749 #define UART3_UTXD                               UART_UTXD_REG(UART3_BASE_PTR)
41750 #define UART3_UCR1                               UART_UCR1_REG(UART3_BASE_PTR)
41751 #define UART3_UCR2                               UART_UCR2_REG(UART3_BASE_PTR)
41752 #define UART3_UCR3                               UART_UCR3_REG(UART3_BASE_PTR)
41753 #define UART3_UCR4                               UART_UCR4_REG(UART3_BASE_PTR)
41754 #define UART3_UFCR                               UART_UFCR_REG(UART3_BASE_PTR)
41755 #define UART3_USR1                               UART_USR1_REG(UART3_BASE_PTR)
41756 #define UART3_USR2                               UART_USR2_REG(UART3_BASE_PTR)
41757 #define UART3_UESC                               UART_UESC_REG(UART3_BASE_PTR)
41758 #define UART3_UTIM                               UART_UTIM_REG(UART3_BASE_PTR)
41759 #define UART3_UBIR                               UART_UBIR_REG(UART3_BASE_PTR)
41760 #define UART3_UBMR                               UART_UBMR_REG(UART3_BASE_PTR)
41761 #define UART3_UBRC                               UART_UBRC_REG(UART3_BASE_PTR)
41762 #define UART3_ONEMS                              UART_ONEMS_REG(UART3_BASE_PTR)
41763 #define UART3_UTS                                UART_UTS_REG(UART3_BASE_PTR)
41764 #define UART3_UMCR                               UART_UMCR_REG(UART3_BASE_PTR)
41765 /* UART4 */
41766 #define UART4_URXD                               UART_URXD_REG(UART4_BASE_PTR)
41767 #define UART4_UTXD                               UART_UTXD_REG(UART4_BASE_PTR)
41768 #define UART4_UCR1                               UART_UCR1_REG(UART4_BASE_PTR)
41769 #define UART4_UCR2                               UART_UCR2_REG(UART4_BASE_PTR)
41770 #define UART4_UCR3                               UART_UCR3_REG(UART4_BASE_PTR)
41771 #define UART4_UCR4                               UART_UCR4_REG(UART4_BASE_PTR)
41772 #define UART4_UFCR                               UART_UFCR_REG(UART4_BASE_PTR)
41773 #define UART4_USR1                               UART_USR1_REG(UART4_BASE_PTR)
41774 #define UART4_USR2                               UART_USR2_REG(UART4_BASE_PTR)
41775 #define UART4_UESC                               UART_UESC_REG(UART4_BASE_PTR)
41776 #define UART4_UTIM                               UART_UTIM_REG(UART4_BASE_PTR)
41777 #define UART4_UBIR                               UART_UBIR_REG(UART4_BASE_PTR)
41778 #define UART4_UBMR                               UART_UBMR_REG(UART4_BASE_PTR)
41779 #define UART4_UBRC                               UART_UBRC_REG(UART4_BASE_PTR)
41780 #define UART4_ONEMS                              UART_ONEMS_REG(UART4_BASE_PTR)
41781 #define UART4_UTS                                UART_UTS_REG(UART4_BASE_PTR)
41782 #define UART4_UMCR                               UART_UMCR_REG(UART4_BASE_PTR)
41783 /* UART5 */
41784 #define UART5_URXD                               UART_URXD_REG(UART5_BASE_PTR)
41785 #define UART5_UTXD                               UART_UTXD_REG(UART5_BASE_PTR)
41786 #define UART5_UCR1                               UART_UCR1_REG(UART5_BASE_PTR)
41787 #define UART5_UCR2                               UART_UCR2_REG(UART5_BASE_PTR)
41788 #define UART5_UCR3                               UART_UCR3_REG(UART5_BASE_PTR)
41789 #define UART5_UCR4                               UART_UCR4_REG(UART5_BASE_PTR)
41790 #define UART5_UFCR                               UART_UFCR_REG(UART5_BASE_PTR)
41791 #define UART5_USR1                               UART_USR1_REG(UART5_BASE_PTR)
41792 #define UART5_USR2                               UART_USR2_REG(UART5_BASE_PTR)
41793 #define UART5_UESC                               UART_UESC_REG(UART5_BASE_PTR)
41794 #define UART5_UTIM                               UART_UTIM_REG(UART5_BASE_PTR)
41795 #define UART5_UBIR                               UART_UBIR_REG(UART5_BASE_PTR)
41796 #define UART5_UBMR                               UART_UBMR_REG(UART5_BASE_PTR)
41797 #define UART5_UBRC                               UART_UBRC_REG(UART5_BASE_PTR)
41798 #define UART5_ONEMS                              UART_ONEMS_REG(UART5_BASE_PTR)
41799 #define UART5_UTS                                UART_UTS_REG(UART5_BASE_PTR)
41800 #define UART5_UMCR                               UART_UMCR_REG(UART5_BASE_PTR)
41801 /* UART6 */
41802 #define UART6_URXD                               UART_URXD_REG(UART6_BASE_PTR)
41803 #define UART6_UTXD                               UART_UTXD_REG(UART6_BASE_PTR)
41804 #define UART6_UCR1                               UART_UCR1_REG(UART6_BASE_PTR)
41805 #define UART6_UCR2                               UART_UCR2_REG(UART6_BASE_PTR)
41806 #define UART6_UCR3                               UART_UCR3_REG(UART6_BASE_PTR)
41807 #define UART6_UCR4                               UART_UCR4_REG(UART6_BASE_PTR)
41808 #define UART6_UFCR                               UART_UFCR_REG(UART6_BASE_PTR)
41809 #define UART6_USR1                               UART_USR1_REG(UART6_BASE_PTR)
41810 #define UART6_USR2                               UART_USR2_REG(UART6_BASE_PTR)
41811 #define UART6_UESC                               UART_UESC_REG(UART6_BASE_PTR)
41812 #define UART6_UTIM                               UART_UTIM_REG(UART6_BASE_PTR)
41813 #define UART6_UBIR                               UART_UBIR_REG(UART6_BASE_PTR)
41814 #define UART6_UBMR                               UART_UBMR_REG(UART6_BASE_PTR)
41815 #define UART6_UBRC                               UART_UBRC_REG(UART6_BASE_PTR)
41816 #define UART6_ONEMS                              UART_ONEMS_REG(UART6_BASE_PTR)
41817 #define UART6_UTS                                UART_UTS_REG(UART6_BASE_PTR)
41818 #define UART6_UMCR                               UART_UMCR_REG(UART6_BASE_PTR)
41819 /* UART7 */
41820 #define UART7_URXD                               UART_URXD_REG(UART7_BASE_PTR)
41821 #define UART7_UTXD                               UART_UTXD_REG(UART7_BASE_PTR)
41822 #define UART7_UCR1                               UART_UCR1_REG(UART7_BASE_PTR)
41823 #define UART7_UCR2                               UART_UCR2_REG(UART7_BASE_PTR)
41824 #define UART7_UCR3                               UART_UCR3_REG(UART7_BASE_PTR)
41825 #define UART7_UCR4                               UART_UCR4_REG(UART7_BASE_PTR)
41826 #define UART7_UFCR                               UART_UFCR_REG(UART7_BASE_PTR)
41827 #define UART7_USR1                               UART_USR1_REG(UART7_BASE_PTR)
41828 #define UART7_USR2                               UART_USR2_REG(UART7_BASE_PTR)
41829 #define UART7_UESC                               UART_UESC_REG(UART7_BASE_PTR)
41830 #define UART7_UTIM                               UART_UTIM_REG(UART7_BASE_PTR)
41831 #define UART7_UBIR                               UART_UBIR_REG(UART7_BASE_PTR)
41832 #define UART7_UBMR                               UART_UBMR_REG(UART7_BASE_PTR)
41833 #define UART7_UBRC                               UART_UBRC_REG(UART7_BASE_PTR)
41834 #define UART7_ONEMS                              UART_ONEMS_REG(UART7_BASE_PTR)
41835 #define UART7_UTS                                UART_UTS_REG(UART7_BASE_PTR)
41836 #define UART7_UMCR                               UART_UMCR_REG(UART7_BASE_PTR)
41837 /*!
41838  * @}
41839  */ /* end of group UART_Register_Accessor_Macros */
41840 
41841 
41842 /*!
41843  * @}
41844  */ /* end of group UART_Peripheral */
41845 
41846 /* ----------------------------------------------------------------------------
41847    -- USB Peripheral Access Layer
41848    ---------------------------------------------------------------------------- */
41849 
41850 /*!
41851  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
41852  * @{
41853  */
41854 
41855 /** USB - Register Layout Typedef */
41856 typedef struct {
41857   __I   uint32_t ID;                                     /**< Identification register, offset: 0x0 */
41858   __I   uint32_t HWGENERAL;                              /**< Hardware General, offset: 0x4 */
41859   __I   uint32_t HWHOST;                                 /**< Host Hardware Parameters, offset: 0x8 */
41860   __I   uint32_t HWDEVICE;                               /**< Device Hardware Parameters, offset: 0xC */
41861   __I   uint32_t HWTXBUF;                                /**< TX Buffer Hardware Parameters, offset: 0x10 */
41862   __I   uint32_t HWRXBUF;                                /**< RX Buffer Hardware Parameters, offset: 0x14 */
41863   uint8_t RESERVED_0[104];
41864   __IO  uint32_t GPTIMER0LD;                             /**< General Purpose Timer #0 Load, offset: 0x80 */
41865   __IO  uint32_t GPTIMER0CTRL;                           /**< General Purpose Timer #0 Controller, offset: 0x84 */
41866   __IO  uint32_t GPTIMER1LD;                             /**< General Purpose Timer #1 Load, offset: 0x88 */
41867   __IO  uint32_t GPTIMER1CTRL;                           /**< General Purpose Timer #1 Controller, offset: 0x8C */
41868   __IO  uint32_t SBUSCFG;                                /**< System Bus Config, offset: 0x90 */
41869   uint8_t RESERVED_1[108];
41870   __I   uint8_t  CAPLENGTH;                              /**< Capability Registers Length, offset: 0x100 */
41871   uint8_t RESERVED_2[1];
41872   __I   uint16_t HCIVERSION;                             /**< Host Controller Interface Version, offset: 0x102 */
41873   __I   uint32_t HCSPARAMS;                              /**< Host Controller Structural Parameters, offset: 0x104 */
41874   __I   uint32_t HCCPARAMS;                              /**< Host Controller Capability Parameters, offset: 0x108 */
41875   uint8_t RESERVED_3[20];
41876   __I   uint16_t DCIVERSION;                             /**< Device Controller Interface Version, offset: 0x120 */
41877   uint8_t RESERVED_4[2];
41878   __I   uint32_t DCCPARAMS;                              /**< Device Controller Capability Parameters, offset: 0x124 */
41879   uint8_t RESERVED_5[24];
41880   __IO  uint32_t USBCMD;                                 /**< USB Command Register, offset: 0x140 */
41881   __IO  uint32_t USBSTS;                                 /**< USB Status Register, offset: 0x144 */
41882   __IO  uint32_t USBINTR;                                /**< Interrupt Enable Register, offset: 0x148 */
41883   __IO  uint32_t FRINDEX;                                /**< USB Frame Index, offset: 0x14C */
41884   uint8_t RESERVED_6[4];
41885   union {                                          /* offset: 0x154 */
41886   __IO    uint32_t PERIODICLISTBASE;                            /**< Frame List Base Address,offset: 0x154 */
41887   __IO    uint32_t DEVICEADDR;                                  /**< Device Address,offset: 0x154 */
41888   struct {                                         /* offset: 0x158 */
41889       uint8_t RESERVED_0[4];
41890   __IO    uint32_t ASYNCLISTADDR;                               /**< Next Asynch. Address,offset: 0x158 */
41891     } ASYNCLISTADDR;
41892   struct {                                         /* offset: 0x158 */
41893       uint8_t RESERVED_0[4];
41894   __IO    uint32_t ENDPTLISTADDR;                               /**< Endpoint List Address,offset: 0x158 */
41895     } ENDPTLISTADDR;
41896   };
41897   uint8_t RESERVED_7[4];
41898   __IO  uint32_t BURSTSIZE;                              /**< Programmable Burst Size, offset: 0x160 */
41899   __IO  uint32_t TXFILLTUNING;                           /**< TX FIFO Fill Tuning, offset: 0x164 */
41900   uint8_t RESERVED_8[16];
41901   __IO  uint32_t ENDPTNAK;                               /**< Endpoint NAK, offset: 0x178 */
41902   __IO  uint32_t ENDPTNAKEN;                             /**< Endpoint NAK Enable, offset: 0x17C */
41903   __IO  uint32_t CONFIGFLAG;                             /**< Configure Flag Register, offset: 0x180 */
41904   __IO  uint32_t PORTSC1;                                /**< Port Status & Control, offset: 0x184 */
41905   uint8_t RESERVED_9[28];
41906   __IO  uint32_t OTGSC;                                  /**< On-The-Go Status & control, offset: 0x1A4 */
41907   __IO  uint32_t USBMODE;                                /**< USB Device Mode, offset: 0x1A8 */
41908   __IO  uint32_t ENDPTSETUPSTAT;                         /**< Endpoint Setup Status, offset: 0x1AC */
41909   __IO  uint32_t ENDPTPRIME;                             /**< Endpoint Prime, offset: 0x1B0 */
41910   __IO  uint32_t ENDPTFLUSH;                             /**< Endpoint Flush, offset: 0x1B4 */
41911   __I   uint32_t ENDPTSTAT;                              /**< Endpoint Status, offset: 0x1B8 */
41912   __IO  uint32_t ENDPTCOMPLETE;                          /**< Endpoint Complete, offset: 0x1BC */
41913   __IO  uint32_t ENDPTCTRL0;                             /**< Endpoint Control0, offset: 0x1C0 */
41914   __IO  uint32_t ENDPTCTRL1;                             /**< Endpoint Control 1, offset: 0x1C4 */
41915   __IO  uint32_t ENDPTCTRL2;                             /**< Endpoint Control 2, offset: 0x1C8 */
41916   __IO  uint32_t ENDPTCTRL3;                             /**< Endpoint Control 3, offset: 0x1CC */
41917   __IO  uint32_t ENDPTCTRL4;                             /**< Endpoint Control 4, offset: 0x1D0 */
41918   __IO  uint32_t ENDPTCTRL5;                             /**< Endpoint Control 5, offset: 0x1D4 */
41919   __IO  uint32_t ENDPTCTRL6;                             /**< Endpoint Control 6, offset: 0x1D8 */
41920   __IO  uint32_t ENDPTCTRL7;                             /**< Endpoint Control 7, offset: 0x1DC */
41921 } USB_Type, *USB_MemMapPtr;
41922 /* ----------------------------------------------------------------------------
41923    -- USB - Register accessor macros
41924    ---------------------------------------------------------------------------- */
41925 
41926 /*!
41927  * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
41928  * @{
41929  */
41930 
41931 
41932 /* USB - Register accessors */
41933 #define USB_ID_REG(base)                         ((base)->ID)
41934 #define USB_HWGENERAL_REG(base)                  ((base)->HWGENERAL)
41935 #define USB_HWHOST_REG(base)                     ((base)->HWHOST)
41936 #define USB_HWDEVICE_REG(base)                   ((base)->HWDEVICE)
41937 #define USB_HWTXBUF_REG(base)                    ((base)->HWTXBUF)
41938 #define USB_HWRXBUF_REG(base)                    ((base)->HWRXBUF)
41939 #define USB_GPTIMER0LD_REG(base)                 ((base)->GPTIMER0LD)
41940 #define USB_GPTIMER0CTRL_REG(base)               ((base)->GPTIMER0CTRL)
41941 #define USB_GPTIMER1LD_REG(base)                 ((base)->GPTIMER1LD)
41942 #define USB_GPTIMER1CTRL_REG(base)               ((base)->GPTIMER1CTRL)
41943 #define USB_SBUSCFG_REG(base)                    ((base)->SBUSCFG)
41944 #define USB_CAPLENGTH_REG(base)                  ((base)->CAPLENGTH)
41945 #define USB_HCIVERSION_REG(base)                 ((base)->HCIVERSION)
41946 #define USB_HCSPARAMS_REG(base)                  ((base)->HCSPARAMS)
41947 #define USB_HCCPARAMS_REG(base)                  ((base)->HCCPARAMS)
41948 #define USB_DCIVERSION_REG(base)                 ((base)->DCIVERSION)
41949 #define USB_DCCPARAMS_REG(base)                  ((base)->DCCPARAMS)
41950 #define USB_USBCMD_REG(base)                     ((base)->USBCMD)
41951 #define USB_USBSTS_REG(base)                     ((base)->USBSTS)
41952 #define USB_USBINTR_REG(base)                    ((base)->USBINTR)
41953 #define USB_FRINDEX_REG(base)                    ((base)->FRINDEX)
41954 #define USB_PERIODICLISTBASE_REG(base)           ((base)->PERIODICLISTBASE)
41955 #define USB_DEVICEADDR_REG(base)                 ((base)->DEVICEADDR)
41956 #define USB_ASYNCLISTADDR_REG(base)              ((base)->ASYNCLISTADDR.ASYNCLISTADDR)
41957 #define USB_ENDPTLISTADDR_REG(base)              ((base)->ENDPTLISTADDR.ENDPTLISTADDR)
41958 #define USB_BURSTSIZE_REG(base)                  ((base)->BURSTSIZE)
41959 #define USB_TXFILLTUNING_REG(base)               ((base)->TXFILLTUNING)
41960 #define USB_ENDPTNAK_REG(base)                   ((base)->ENDPTNAK)
41961 #define USB_ENDPTNAKEN_REG(base)                 ((base)->ENDPTNAKEN)
41962 #define USB_CONFIGFLAG_REG(base)                 ((base)->CONFIGFLAG)
41963 #define USB_PORTSC1_REG(base)                    ((base)->PORTSC1)
41964 #define USB_OTGSC_REG(base)                      ((base)->OTGSC)
41965 #define USB_USBMODE_REG(base)                    ((base)->USBMODE)
41966 #define USB_ENDPTSETUPSTAT_REG(base)             ((base)->ENDPTSETUPSTAT)
41967 #define USB_ENDPTPRIME_REG(base)                 ((base)->ENDPTPRIME)
41968 #define USB_ENDPTFLUSH_REG(base)                 ((base)->ENDPTFLUSH)
41969 #define USB_ENDPTSTAT_REG(base)                  ((base)->ENDPTSTAT)
41970 #define USB_ENDPTCOMPLETE_REG(base)              ((base)->ENDPTCOMPLETE)
41971 #define USB_ENDPTCTRL0_REG(base)                 ((base)->ENDPTCTRL0)
41972 #define USB_ENDPTCTRL1_REG(base)                 ((base)->ENDPTCTRL1)
41973 #define USB_ENDPTCTRL2_REG(base)                 ((base)->ENDPTCTRL2)
41974 #define USB_ENDPTCTRL3_REG(base)                 ((base)->ENDPTCTRL3)
41975 #define USB_ENDPTCTRL4_REG(base)                 ((base)->ENDPTCTRL4)
41976 #define USB_ENDPTCTRL5_REG(base)                 ((base)->ENDPTCTRL5)
41977 #define USB_ENDPTCTRL6_REG(base)                 ((base)->ENDPTCTRL6)
41978 #define USB_ENDPTCTRL7_REG(base)                 ((base)->ENDPTCTRL7)
41979 
41980 /*!
41981  * @}
41982  */ /* end of group USB_Register_Accessor_Macros */
41983 /* ----------------------------------------------------------------------------
41984    -- USB Register Masks
41985    ---------------------------------------------------------------------------- */
41986 
41987 /*!
41988  * @addtogroup USB_Register_Masks USB Register Masks
41989  * @{
41990  */
41991 
41992 /* ID Bit Fields */
41993 #define USB_ID_ID_MASK                           0x3Fu
41994 #define USB_ID_ID_SHIFT                          0
41995 #define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x))<<USB_ID_ID_SHIFT))&USB_ID_ID_MASK)
41996 #define USB_ID_NID_MASK                          0x3F00u
41997 #define USB_ID_NID_SHIFT                         8
41998 #define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x))<<USB_ID_NID_SHIFT))&USB_ID_NID_MASK)
41999 #define USB_ID_REVISION_MASK                     0xFF0000u
42000 #define USB_ID_REVISION_SHIFT                    16
42001 #define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x))<<USB_ID_REVISION_SHIFT))&USB_ID_REVISION_MASK)
42002 /* HWGENERAL Bit Fields */
42003 #define USB_HWGENERAL_PHYW_MASK                  0x30u
42004 #define USB_HWGENERAL_PHYW_SHIFT                 4
42005 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_PHYW_SHIFT))&USB_HWGENERAL_PHYW_MASK)
42006 #define USB_HWGENERAL_PHYM_MASK                  0x1C0u
42007 #define USB_HWGENERAL_PHYM_SHIFT                 6
42008 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_PHYM_SHIFT))&USB_HWGENERAL_PHYM_MASK)
42009 #define USB_HWGENERAL_SM_MASK                    0x600u
42010 #define USB_HWGENERAL_SM_SHIFT                   9
42011 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_SM_SHIFT))&USB_HWGENERAL_SM_MASK)
42012 /* HWHOST Bit Fields */
42013 #define USB_HWHOST_HC_MASK                       0x1u
42014 #define USB_HWHOST_HC_SHIFT                      0
42015 #define USB_HWHOST_NPORT_MASK                    0xEu
42016 #define USB_HWHOST_NPORT_SHIFT                   1
42017 #define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x))<<USB_HWHOST_NPORT_SHIFT))&USB_HWHOST_NPORT_MASK)
42018 /* HWDEVICE Bit Fields */
42019 #define USB_HWDEVICE_DC_MASK                     0x1u
42020 #define USB_HWDEVICE_DC_SHIFT                    0
42021 #define USB_HWDEVICE_DEVEP_MASK                  0x3Eu
42022 #define USB_HWDEVICE_DEVEP_SHIFT                 1
42023 #define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HWDEVICE_DEVEP_SHIFT))&USB_HWDEVICE_DEVEP_MASK)
42024 /* HWTXBUF Bit Fields */
42025 #define USB_HWTXBUF_TXBURST_MASK                 0xFFu
42026 #define USB_HWTXBUF_TXBURST_SHIFT                0
42027 #define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HWTXBUF_TXBURST_SHIFT))&USB_HWTXBUF_TXBURST_MASK)
42028 #define USB_HWTXBUF_TXCHANADD_MASK               0xFF0000u
42029 #define USB_HWTXBUF_TXCHANADD_SHIFT              16
42030 #define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x))<<USB_HWTXBUF_TXCHANADD_SHIFT))&USB_HWTXBUF_TXCHANADD_MASK)
42031 /* HWRXBUF Bit Fields */
42032 #define USB_HWRXBUF_RXBURST_MASK                 0xFFu
42033 #define USB_HWRXBUF_RXBURST_SHIFT                0
42034 #define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HWRXBUF_RXBURST_SHIFT))&USB_HWRXBUF_RXBURST_MASK)
42035 #define USB_HWRXBUF_RXADD_MASK                   0xFF00u
42036 #define USB_HWRXBUF_RXADD_SHIFT                  8
42037 #define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x))<<USB_HWRXBUF_RXADD_SHIFT))&USB_HWRXBUF_RXADD_MASK)
42038 /* GPTIMER0LD Bit Fields */
42039 #define USB_GPTIMER0LD_GPTLD_MASK                0xFFFFFFu
42040 #define USB_GPTIMER0LD_GPTLD_SHIFT               0
42041 #define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER0LD_GPTLD_SHIFT))&USB_GPTIMER0LD_GPTLD_MASK)
42042 /* GPTIMER0CTRL Bit Fields */
42043 #define USB_GPTIMER0CTRL_GPTCNT_MASK             0xFFFFFFu
42044 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT            0
42045 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER0CTRL_GPTCNT_SHIFT))&USB_GPTIMER0CTRL_GPTCNT_MASK)
42046 #define USB_GPTIMER0CTRL_GPTMODE_MASK            0x1000000u
42047 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           24
42048 #define USB_GPTIMER0CTRL_GPTRST_MASK             0x40000000u
42049 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            30
42050 #define USB_GPTIMER0CTRL_GPTRUN_MASK             0x80000000u
42051 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            31
42052 /* GPTIMER1LD Bit Fields */
42053 #define USB_GPTIMER1LD_GPTLD_MASK                0xFFFFFFu
42054 #define USB_GPTIMER1LD_GPTLD_SHIFT               0
42055 #define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER1LD_GPTLD_SHIFT))&USB_GPTIMER1LD_GPTLD_MASK)
42056 /* GPTIMER1CTRL Bit Fields */
42057 #define USB_GPTIMER1CTRL_GPTCNT_MASK             0xFFFFFFu
42058 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT            0
42059 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER1CTRL_GPTCNT_SHIFT))&USB_GPTIMER1CTRL_GPTCNT_MASK)
42060 #define USB_GPTIMER1CTRL_GPTMODE_MASK            0x1000000u
42061 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           24
42062 #define USB_GPTIMER1CTRL_GPTRST_MASK             0x40000000u
42063 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            30
42064 #define USB_GPTIMER1CTRL_GPTRUN_MASK             0x80000000u
42065 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            31
42066 /* SBUSCFG Bit Fields */
42067 #define USB_SBUSCFG_AHBBRST_MASK                 0x7u
42068 #define USB_SBUSCFG_AHBBRST_SHIFT                0
42069 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x))<<USB_SBUSCFG_AHBBRST_SHIFT))&USB_SBUSCFG_AHBBRST_MASK)
42070 /* CAPLENGTH Bit Fields */
42071 #define USB_CAPLENGTH_CAPLENGTH_MASK             0xFFu
42072 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            0
42073 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x))<<USB_CAPLENGTH_CAPLENGTH_SHIFT))&USB_CAPLENGTH_CAPLENGTH_MASK)
42074 /* HCIVERSION Bit Fields */
42075 #define USB_HCIVERSION_HCIVERSION_MASK           0xFFFFu
42076 #define USB_HCIVERSION_HCIVERSION_SHIFT          0
42077 #define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x))<<USB_HCIVERSION_HCIVERSION_SHIFT))&USB_HCIVERSION_HCIVERSION_MASK)
42078 /* HCSPARAMS Bit Fields */
42079 #define USB_HCSPARAMS_N_PORTS_MASK               0xFu
42080 #define USB_HCSPARAMS_N_PORTS_SHIFT              0
42081 #define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PORTS_SHIFT))&USB_HCSPARAMS_N_PORTS_MASK)
42082 #define USB_HCSPARAMS_PPC_MASK                   0x10u
42083 #define USB_HCSPARAMS_PPC_SHIFT                  4
42084 #define USB_HCSPARAMS_N_PCC_MASK                 0xF00u
42085 #define USB_HCSPARAMS_N_PCC_SHIFT                8
42086 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PCC_SHIFT))&USB_HCSPARAMS_N_PCC_MASK)
42087 #define USB_HCSPARAMS_N_CC_MASK                  0xF000u
42088 #define USB_HCSPARAMS_N_CC_SHIFT                 12
42089 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_CC_SHIFT))&USB_HCSPARAMS_N_CC_MASK)
42090 #define USB_HCSPARAMS_PI_MASK                    0x10000u
42091 #define USB_HCSPARAMS_PI_SHIFT                   16
42092 #define USB_HCSPARAMS_N_PTT_MASK                 0xF00000u
42093 #define USB_HCSPARAMS_N_PTT_SHIFT                20
42094 #define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PTT_SHIFT))&USB_HCSPARAMS_N_PTT_MASK)
42095 #define USB_HCSPARAMS_N_TT_MASK                  0xF000000u
42096 #define USB_HCSPARAMS_N_TT_SHIFT                 24
42097 #define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_TT_SHIFT))&USB_HCSPARAMS_N_TT_MASK)
42098 /* HCCPARAMS Bit Fields */
42099 #define USB_HCCPARAMS_ADC_MASK                   0x1u
42100 #define USB_HCCPARAMS_ADC_SHIFT                  0
42101 #define USB_HCCPARAMS_PFL_MASK                   0x2u
42102 #define USB_HCCPARAMS_PFL_SHIFT                  1
42103 #define USB_HCCPARAMS_ASP_MASK                   0x4u
42104 #define USB_HCCPARAMS_ASP_SHIFT                  2
42105 #define USB_HCCPARAMS_IST_MASK                   0xF0u
42106 #define USB_HCCPARAMS_IST_SHIFT                  4
42107 #define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x))<<USB_HCCPARAMS_IST_SHIFT))&USB_HCCPARAMS_IST_MASK)
42108 #define USB_HCCPARAMS_EECP_MASK                  0xFF00u
42109 #define USB_HCCPARAMS_EECP_SHIFT                 8
42110 #define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HCCPARAMS_EECP_SHIFT))&USB_HCCPARAMS_EECP_MASK)
42111 /* DCIVERSION Bit Fields */
42112 #define USB_DCIVERSION_DCIVERSION_MASK           0xFFFFu
42113 #define USB_DCIVERSION_DCIVERSION_SHIFT          0
42114 #define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x))<<USB_DCIVERSION_DCIVERSION_SHIFT))&USB_DCIVERSION_DCIVERSION_MASK)
42115 /* DCCPARAMS Bit Fields */
42116 #define USB_DCCPARAMS_DEN_MASK                   0x1Fu
42117 #define USB_DCCPARAMS_DEN_SHIFT                  0
42118 #define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x))<<USB_DCCPARAMS_DEN_SHIFT))&USB_DCCPARAMS_DEN_MASK)
42119 #define USB_DCCPARAMS_DC_MASK                    0x80u
42120 #define USB_DCCPARAMS_DC_SHIFT                   7
42121 #define USB_DCCPARAMS_HC_MASK                    0x100u
42122 #define USB_DCCPARAMS_HC_SHIFT                   8
42123 /* USBCMD Bit Fields */
42124 #define USB_USBCMD_RS_MASK                       0x1u
42125 #define USB_USBCMD_RS_SHIFT                      0
42126 #define USB_USBCMD_RST_MASK                      0x2u
42127 #define USB_USBCMD_RST_SHIFT                     1
42128 #define USB_USBCMD_FS_1_MASK                     0xCu
42129 #define USB_USBCMD_FS_1_SHIFT                    2
42130 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_FS_1_SHIFT))&USB_USBCMD_FS_1_MASK)
42131 #define USB_USBCMD_PSE_MASK                      0x10u
42132 #define USB_USBCMD_PSE_SHIFT                     4
42133 #define USB_USBCMD_ASE_MASK                      0x20u
42134 #define USB_USBCMD_ASE_SHIFT                     5
42135 #define USB_USBCMD_IAA_MASK                      0x40u
42136 #define USB_USBCMD_IAA_SHIFT                     6
42137 #define USB_USBCMD_ASP_MASK                      0x300u
42138 #define USB_USBCMD_ASP_SHIFT                     8
42139 #define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_ASP_SHIFT))&USB_USBCMD_ASP_MASK)
42140 #define USB_USBCMD_ASPE_MASK                     0x800u
42141 #define USB_USBCMD_ASPE_SHIFT                    11
42142 #define USB_USBCMD_SUTW_MASK                     0x2000u
42143 #define USB_USBCMD_SUTW_SHIFT                    13
42144 #define USB_USBCMD_ATDTW_MASK                    0x4000u
42145 #define USB_USBCMD_ATDTW_SHIFT                   14
42146 #define USB_USBCMD_FS_2_MASK                     0x8000u
42147 #define USB_USBCMD_FS_2_SHIFT                    15
42148 #define USB_USBCMD_ITC_MASK                      0xFF0000u
42149 #define USB_USBCMD_ITC_SHIFT                     16
42150 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_ITC_SHIFT))&USB_USBCMD_ITC_MASK)
42151 /* USBSTS Bit Fields */
42152 #define USB_USBSTS_UI_MASK                       0x1u
42153 #define USB_USBSTS_UI_SHIFT                      0
42154 #define USB_USBSTS_UEI_MASK                      0x2u
42155 #define USB_USBSTS_UEI_SHIFT                     1
42156 #define USB_USBSTS_PCI_MASK                      0x4u
42157 #define USB_USBSTS_PCI_SHIFT                     2
42158 #define USB_USBSTS_FRI_MASK                      0x8u
42159 #define USB_USBSTS_FRI_SHIFT                     3
42160 #define USB_USBSTS_SEI_MASK                      0x10u
42161 #define USB_USBSTS_SEI_SHIFT                     4
42162 #define USB_USBSTS_AAI_MASK                      0x20u
42163 #define USB_USBSTS_AAI_SHIFT                     5
42164 #define USB_USBSTS_URI_MASK                      0x40u
42165 #define USB_USBSTS_URI_SHIFT                     6
42166 #define USB_USBSTS_SRI_MASK                      0x80u
42167 #define USB_USBSTS_SRI_SHIFT                     7
42168 #define USB_USBSTS_SLI_MASK                      0x100u
42169 #define USB_USBSTS_SLI_SHIFT                     8
42170 #define USB_USBSTS_ULPII_MASK                    0x400u
42171 #define USB_USBSTS_ULPII_SHIFT                   10
42172 #define USB_USBSTS_HCH_MASK                      0x1000u
42173 #define USB_USBSTS_HCH_SHIFT                     12
42174 #define USB_USBSTS_RCL_MASK                      0x2000u
42175 #define USB_USBSTS_RCL_SHIFT                     13
42176 #define USB_USBSTS_PS_MASK                       0x4000u
42177 #define USB_USBSTS_PS_SHIFT                      14
42178 #define USB_USBSTS_AS_MASK                       0x8000u
42179 #define USB_USBSTS_AS_SHIFT                      15
42180 #define USB_USBSTS_NAKI_MASK                     0x10000u
42181 #define USB_USBSTS_NAKI_SHIFT                    16
42182 #define USB_USBSTS_TI0_MASK                      0x1000000u
42183 #define USB_USBSTS_TI0_SHIFT                     24
42184 #define USB_USBSTS_TI1_MASK                      0x2000000u
42185 #define USB_USBSTS_TI1_SHIFT                     25
42186 /* USBINTR Bit Fields */
42187 #define USB_USBINTR_UE_MASK                      0x1u
42188 #define USB_USBINTR_UE_SHIFT                     0
42189 #define USB_USBINTR_UEE_MASK                     0x2u
42190 #define USB_USBINTR_UEE_SHIFT                    1
42191 #define USB_USBINTR_PCE_MASK                     0x4u
42192 #define USB_USBINTR_PCE_SHIFT                    2
42193 #define USB_USBINTR_FRE_MASK                     0x8u
42194 #define USB_USBINTR_FRE_SHIFT                    3
42195 #define USB_USBINTR_SEE_MASK                     0x10u
42196 #define USB_USBINTR_SEE_SHIFT                    4
42197 #define USB_USBINTR_AAE_MASK                     0x20u
42198 #define USB_USBINTR_AAE_SHIFT                    5
42199 #define USB_USBINTR_URE_MASK                     0x40u
42200 #define USB_USBINTR_URE_SHIFT                    6
42201 #define USB_USBINTR_SRE_MASK                     0x80u
42202 #define USB_USBINTR_SRE_SHIFT                    7
42203 #define USB_USBINTR_SLE_MASK                     0x100u
42204 #define USB_USBINTR_SLE_SHIFT                    8
42205 #define USB_USBINTR_ULPIE_MASK                   0x400u
42206 #define USB_USBINTR_ULPIE_SHIFT                  10
42207 #define USB_USBINTR_NAKE_MASK                    0x10000u
42208 #define USB_USBINTR_NAKE_SHIFT                   16
42209 #define USB_USBINTR_UAIE_MASK                    0x40000u
42210 #define USB_USBINTR_UAIE_SHIFT                   18
42211 #define USB_USBINTR_UPIE_MASK                    0x80000u
42212 #define USB_USBINTR_UPIE_SHIFT                   19
42213 #define USB_USBINTR_TIE0_MASK                    0x1000000u
42214 #define USB_USBINTR_TIE0_SHIFT                   24
42215 #define USB_USBINTR_TIE1_MASK                    0x2000000u
42216 #define USB_USBINTR_TIE1_SHIFT                   25
42217 /* FRINDEX Bit Fields */
42218 #define USB_FRINDEX_FRINDEX_MASK                 0x3FFFu
42219 #define USB_FRINDEX_FRINDEX_SHIFT                0
42220 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x))<<USB_FRINDEX_FRINDEX_SHIFT))&USB_FRINDEX_FRINDEX_MASK)
42221 /* PERIODICLISTBASE Bit Fields */
42222 #define USB_PERIODICLISTBASE_BASEADR_MASK        0xFFFFF000u
42223 #define USB_PERIODICLISTBASE_BASEADR_SHIFT       12
42224 #define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x))<<USB_PERIODICLISTBASE_BASEADR_SHIFT))&USB_PERIODICLISTBASE_BASEADR_MASK)
42225 /* DEVICEADDR Bit Fields */
42226 #define USB_DEVICEADDR_USBADRA_MASK              0x1000000u
42227 #define USB_DEVICEADDR_USBADRA_SHIFT             24
42228 #define USB_DEVICEADDR_USBADR_MASK               0xFE000000u
42229 #define USB_DEVICEADDR_USBADR_SHIFT              25
42230 #define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x))<<USB_DEVICEADDR_USBADR_SHIFT))&USB_DEVICEADDR_USBADR_MASK)
42231 /* ASYNCLISTADDR Bit Fields */
42232 #define USB_ASYNCLISTADDR_ASYBASE_MASK           0xFFFFFFE0u
42233 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT          5
42234 #define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x))<<USB_ASYNCLISTADDR_ASYBASE_SHIFT))&USB_ASYNCLISTADDR_ASYBASE_MASK)
42235 /* ENDPTLISTADDR Bit Fields */
42236 #define USB_ENDPTLISTADDR_EPBASE_MASK            0xFFFFF800u
42237 #define USB_ENDPTLISTADDR_EPBASE_SHIFT           11
42238 #define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x))<<USB_ENDPTLISTADDR_EPBASE_SHIFT))&USB_ENDPTLISTADDR_EPBASE_MASK)
42239 /* BURSTSIZE Bit Fields */
42240 #define USB_BURSTSIZE_RXPBURST_MASK              0xFFu
42241 #define USB_BURSTSIZE_RXPBURST_SHIFT             0
42242 #define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x))<<USB_BURSTSIZE_RXPBURST_SHIFT))&USB_BURSTSIZE_RXPBURST_MASK)
42243 #define USB_BURSTSIZE_TXPBURST_MASK              0x1FF00u
42244 #define USB_BURSTSIZE_TXPBURST_SHIFT             8
42245 #define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x))<<USB_BURSTSIZE_TXPBURST_SHIFT))&USB_BURSTSIZE_TXPBURST_MASK)
42246 /* TXFILLTUNING Bit Fields */
42247 #define USB_TXFILLTUNING_TXSCHOH_MASK            0xFFu
42248 #define USB_TXFILLTUNING_TXSCHOH_SHIFT           0
42249 #define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXSCHOH_SHIFT))&USB_TXFILLTUNING_TXSCHOH_MASK)
42250 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK        0x1F00u
42251 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       8
42252 #define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USB_TXFILLTUNING_TXSCHHEALTH_MASK)
42253 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK        0x3F0000u
42254 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       16
42255 #define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USB_TXFILLTUNING_TXFIFOTHRES_MASK)
42256 /* ENDPTNAK Bit Fields */
42257 #define USB_ENDPTNAK_EPRN_MASK                   0xFFu
42258 #define USB_ENDPTNAK_EPRN_SHIFT                  0
42259 #define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAK_EPRN_SHIFT))&USB_ENDPTNAK_EPRN_MASK)
42260 #define USB_ENDPTNAK_EPTN_MASK                   0xFF0000u
42261 #define USB_ENDPTNAK_EPTN_SHIFT                  16
42262 #define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAK_EPTN_SHIFT))&USB_ENDPTNAK_EPTN_MASK)
42263 /* ENDPTNAKEN Bit Fields */
42264 #define USB_ENDPTNAKEN_EPRNE_MASK                0xFFu
42265 #define USB_ENDPTNAKEN_EPRNE_SHIFT               0
42266 #define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAKEN_EPRNE_SHIFT))&USB_ENDPTNAKEN_EPRNE_MASK)
42267 #define USB_ENDPTNAKEN_EPTNE_MASK                0xFF0000u
42268 #define USB_ENDPTNAKEN_EPTNE_SHIFT               16
42269 #define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAKEN_EPTNE_SHIFT))&USB_ENDPTNAKEN_EPTNE_MASK)
42270 /* CONFIGFLAG Bit Fields */
42271 #define USB_CONFIGFLAG_CF_MASK                   0x1u
42272 #define USB_CONFIGFLAG_CF_SHIFT                  0
42273 /* PORTSC1 Bit Fields */
42274 #define USB_PORTSC1_CCS_MASK                     0x1u
42275 #define USB_PORTSC1_CCS_SHIFT                    0
42276 #define USB_PORTSC1_CSC_MASK                     0x2u
42277 #define USB_PORTSC1_CSC_SHIFT                    1
42278 #define USB_PORTSC1_PE_MASK                      0x4u
42279 #define USB_PORTSC1_PE_SHIFT                     2
42280 #define USB_PORTSC1_PEC_MASK                     0x8u
42281 #define USB_PORTSC1_PEC_SHIFT                    3
42282 #define USB_PORTSC1_OCA_MASK                     0x10u
42283 #define USB_PORTSC1_OCA_SHIFT                    4
42284 #define USB_PORTSC1_OCC_MASK                     0x20u
42285 #define USB_PORTSC1_OCC_SHIFT                    5
42286 #define USB_PORTSC1_FPR_MASK                     0x40u
42287 #define USB_PORTSC1_FPR_SHIFT                    6
42288 #define USB_PORTSC1_SUSP_MASK                    0x80u
42289 #define USB_PORTSC1_SUSP_SHIFT                   7
42290 #define USB_PORTSC1_PR_MASK                      0x100u
42291 #define USB_PORTSC1_PR_SHIFT                     8
42292 #define USB_PORTSC1_HSP_MASK                     0x200u
42293 #define USB_PORTSC1_HSP_SHIFT                    9
42294 #define USB_PORTSC1_LS_MASK                      0xC00u
42295 #define USB_PORTSC1_LS_SHIFT                     10
42296 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_LS_SHIFT))&USB_PORTSC1_LS_MASK)
42297 #define USB_PORTSC1_PP_MASK                      0x1000u
42298 #define USB_PORTSC1_PP_SHIFT                     12
42299 #define USB_PORTSC1_PO_MASK                      0x2000u
42300 #define USB_PORTSC1_PO_SHIFT                     13
42301 #define USB_PORTSC1_PIC_MASK                     0xC000u
42302 #define USB_PORTSC1_PIC_SHIFT                    14
42303 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PIC_SHIFT))&USB_PORTSC1_PIC_MASK)
42304 #define USB_PORTSC1_PTC_MASK                     0xF0000u
42305 #define USB_PORTSC1_PTC_SHIFT                    16
42306 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PTC_SHIFT))&USB_PORTSC1_PTC_MASK)
42307 #define USB_PORTSC1_WKCN_MASK                    0x100000u
42308 #define USB_PORTSC1_WKCN_SHIFT                   20
42309 #define USB_PORTSC1_WKDC_MASK                    0x200000u
42310 #define USB_PORTSC1_WKDC_SHIFT                   21
42311 #define USB_PORTSC1_WKOC_MASK                    0x400000u
42312 #define USB_PORTSC1_WKOC_SHIFT                   22
42313 #define USB_PORTSC1_PHCD_MASK                    0x800000u
42314 #define USB_PORTSC1_PHCD_SHIFT                   23
42315 #define USB_PORTSC1_PFSC_MASK                    0x1000000u
42316 #define USB_PORTSC1_PFSC_SHIFT                   24
42317 #define USB_PORTSC1_PTS_2_MASK                   0x2000000u
42318 #define USB_PORTSC1_PTS_2_SHIFT                  25
42319 #define USB_PORTSC1_PSPD_MASK                    0xC000000u
42320 #define USB_PORTSC1_PSPD_SHIFT                   26
42321 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PSPD_SHIFT))&USB_PORTSC1_PSPD_MASK)
42322 #define USB_PORTSC1_PTW_MASK                     0x10000000u
42323 #define USB_PORTSC1_PTW_SHIFT                    28
42324 #define USB_PORTSC1_STS_MASK                     0x20000000u
42325 #define USB_PORTSC1_STS_SHIFT                    29
42326 #define USB_PORTSC1_PTS_1_MASK                   0xC0000000u
42327 #define USB_PORTSC1_PTS_1_SHIFT                  30
42328 #define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PTS_1_SHIFT))&USB_PORTSC1_PTS_1_MASK)
42329 /* OTGSC Bit Fields */
42330 #define USB_OTGSC_VD_MASK                        0x1u
42331 #define USB_OTGSC_VD_SHIFT                       0
42332 #define USB_OTGSC_VC_MASK                        0x2u
42333 #define USB_OTGSC_VC_SHIFT                       1
42334 #define USB_OTGSC_OT_MASK                        0x8u
42335 #define USB_OTGSC_OT_SHIFT                       3
42336 #define USB_OTGSC_DP_MASK                        0x10u
42337 #define USB_OTGSC_DP_SHIFT                       4
42338 #define USB_OTGSC_IDPU_MASK                      0x20u
42339 #define USB_OTGSC_IDPU_SHIFT                     5
42340 #define USB_OTGSC_ID_MASK                        0x100u
42341 #define USB_OTGSC_ID_SHIFT                       8
42342 #define USB_OTGSC_AVV_MASK                       0x200u
42343 #define USB_OTGSC_AVV_SHIFT                      9
42344 #define USB_OTGSC_ASV_MASK                       0x400u
42345 #define USB_OTGSC_ASV_SHIFT                      10
42346 #define USB_OTGSC_BSV_MASK                       0x800u
42347 #define USB_OTGSC_BSV_SHIFT                      11
42348 #define USB_OTGSC_BSE_MASK                       0x1000u
42349 #define USB_OTGSC_BSE_SHIFT                      12
42350 #define USB_OTGSC_TOG_1MS_MASK                   0x2000u
42351 #define USB_OTGSC_TOG_1MS_SHIFT                  13
42352 #define USB_OTGSC_DPS_MASK                       0x4000u
42353 #define USB_OTGSC_DPS_SHIFT                      14
42354 #define USB_OTGSC_IDIS_MASK                      0x10000u
42355 #define USB_OTGSC_IDIS_SHIFT                     16
42356 #define USB_OTGSC_AVVIS_MASK                     0x20000u
42357 #define USB_OTGSC_AVVIS_SHIFT                    17
42358 #define USB_OTGSC_ASVIS_MASK                     0x40000u
42359 #define USB_OTGSC_ASVIS_SHIFT                    18
42360 #define USB_OTGSC_BSVIS_MASK                     0x80000u
42361 #define USB_OTGSC_BSVIS_SHIFT                    19
42362 #define USB_OTGSC_BSEIS_MASK                     0x100000u
42363 #define USB_OTGSC_BSEIS_SHIFT                    20
42364 #define USB_OTGSC_STATUS_1MS_MASK                0x200000u
42365 #define USB_OTGSC_STATUS_1MS_SHIFT               21
42366 #define USB_OTGSC_DPIS_MASK                      0x400000u
42367 #define USB_OTGSC_DPIS_SHIFT                     22
42368 #define USB_OTGSC_IDIE_MASK                      0x1000000u
42369 #define USB_OTGSC_IDIE_SHIFT                     24
42370 #define USB_OTGSC_AVVIE_MASK                     0x2000000u
42371 #define USB_OTGSC_AVVIE_SHIFT                    25
42372 #define USB_OTGSC_ASVIE_MASK                     0x4000000u
42373 #define USB_OTGSC_ASVIE_SHIFT                    26
42374 #define USB_OTGSC_BSVIE_MASK                     0x8000000u
42375 #define USB_OTGSC_BSVIE_SHIFT                    27
42376 #define USB_OTGSC_BSEIE_MASK                     0x10000000u
42377 #define USB_OTGSC_BSEIE_SHIFT                    28
42378 #define USB_OTGSC_EN_1MS_MASK                    0x20000000u
42379 #define USB_OTGSC_EN_1MS_SHIFT                   29
42380 #define USB_OTGSC_DPIE_MASK                      0x40000000u
42381 #define USB_OTGSC_DPIE_SHIFT                     30
42382 /* USBMODE Bit Fields */
42383 #define USB_USBMODE_CM_MASK                      0x3u
42384 #define USB_USBMODE_CM_SHIFT                     0
42385 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBMODE_CM_SHIFT))&USB_USBMODE_CM_MASK)
42386 #define USB_USBMODE_ES_MASK                      0x4u
42387 #define USB_USBMODE_ES_SHIFT                     2
42388 #define USB_USBMODE_SLOM_MASK                    0x8u
42389 #define USB_USBMODE_SLOM_SHIFT                   3
42390 #define USB_USBMODE_SDIS_MASK                    0x10u
42391 #define USB_USBMODE_SDIS_SHIFT                   4
42392 /* ENDPTSETUPSTAT Bit Fields */
42393 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   0xFFFFu
42394 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  0
42395 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
42396 /* ENDPTPRIME Bit Fields */
42397 #define USB_ENDPTPRIME_PERB_MASK                 0xFFu
42398 #define USB_ENDPTPRIME_PERB_SHIFT                0
42399 #define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTPRIME_PERB_SHIFT))&USB_ENDPTPRIME_PERB_MASK)
42400 #define USB_ENDPTPRIME_PETB_MASK                 0xFF0000u
42401 #define USB_ENDPTPRIME_PETB_SHIFT                16
42402 #define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTPRIME_PETB_SHIFT))&USB_ENDPTPRIME_PETB_MASK)
42403 /* ENDPTFLUSH Bit Fields */
42404 #define USB_ENDPTFLUSH_FERB_MASK                 0xFFu
42405 #define USB_ENDPTFLUSH_FERB_SHIFT                0
42406 #define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTFLUSH_FERB_SHIFT))&USB_ENDPTFLUSH_FERB_MASK)
42407 #define USB_ENDPTFLUSH_FETB_MASK                 0xFF0000u
42408 #define USB_ENDPTFLUSH_FETB_SHIFT                16
42409 #define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTFLUSH_FETB_SHIFT))&USB_ENDPTFLUSH_FETB_MASK)
42410 /* ENDPTSTAT Bit Fields */
42411 #define USB_ENDPTSTAT_ERBR_MASK                  0xFFu
42412 #define USB_ENDPTSTAT_ERBR_SHIFT                 0
42413 #define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSTAT_ERBR_SHIFT))&USB_ENDPTSTAT_ERBR_MASK)
42414 #define USB_ENDPTSTAT_ETBR_MASK                  0xFF0000u
42415 #define USB_ENDPTSTAT_ETBR_SHIFT                 16
42416 #define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSTAT_ETBR_SHIFT))&USB_ENDPTSTAT_ETBR_MASK)
42417 /* ENDPTCOMPLETE Bit Fields */
42418 #define USB_ENDPTCOMPLETE_ERCE_MASK              0xFFu
42419 #define USB_ENDPTCOMPLETE_ERCE_SHIFT             0
42420 #define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCOMPLETE_ERCE_SHIFT))&USB_ENDPTCOMPLETE_ERCE_MASK)
42421 #define USB_ENDPTCOMPLETE_ETCE_MASK              0xFF0000u
42422 #define USB_ENDPTCOMPLETE_ETCE_SHIFT             16
42423 #define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCOMPLETE_ETCE_SHIFT))&USB_ENDPTCOMPLETE_ETCE_MASK)
42424 /* ENDPTCTRL0 Bit Fields */
42425 #define USB_ENDPTCTRL0_RXS_MASK                  0x1u
42426 #define USB_ENDPTCTRL0_RXS_SHIFT                 0
42427 #define USB_ENDPTCTRL0_RXT_MASK                  0xCu
42428 #define USB_ENDPTCTRL0_RXT_SHIFT                 2
42429 #define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL0_RXT_SHIFT))&USB_ENDPTCTRL0_RXT_MASK)
42430 #define USB_ENDPTCTRL0_RXE_MASK                  0x80u
42431 #define USB_ENDPTCTRL0_RXE_SHIFT                 7
42432 #define USB_ENDPTCTRL0_TXS_MASK                  0x10000u
42433 #define USB_ENDPTCTRL0_TXS_SHIFT                 16
42434 #define USB_ENDPTCTRL0_TXT_MASK                  0xC0000u
42435 #define USB_ENDPTCTRL0_TXT_SHIFT                 18
42436 #define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL0_TXT_SHIFT))&USB_ENDPTCTRL0_TXT_MASK)
42437 #define USB_ENDPTCTRL0_TXE_MASK                  0x800000u
42438 #define USB_ENDPTCTRL0_TXE_SHIFT                 23
42439 /* ENDPTCTRL1 Bit Fields */
42440 #define USB_ENDPTCTRL1_RXS_MASK                  0x1u
42441 #define USB_ENDPTCTRL1_RXS_SHIFT                 0
42442 #define USB_ENDPTCTRL1_RXD_MASK                  0x2u
42443 #define USB_ENDPTCTRL1_RXD_SHIFT                 1
42444 #define USB_ENDPTCTRL1_RXT_MASK                  0xCu
42445 #define USB_ENDPTCTRL1_RXT_SHIFT                 2
42446 #define USB_ENDPTCTRL1_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL1_RXT_SHIFT))&USB_ENDPTCTRL1_RXT_MASK)
42447 #define USB_ENDPTCTRL1_RXI_MASK                  0x20u
42448 #define USB_ENDPTCTRL1_RXI_SHIFT                 5
42449 #define USB_ENDPTCTRL1_RXR_MASK                  0x40u
42450 #define USB_ENDPTCTRL1_RXR_SHIFT                 6
42451 #define USB_ENDPTCTRL1_RXE_MASK                  0x80u
42452 #define USB_ENDPTCTRL1_RXE_SHIFT                 7
42453 #define USB_ENDPTCTRL1_TXS_MASK                  0x10000u
42454 #define USB_ENDPTCTRL1_TXS_SHIFT                 16
42455 #define USB_ENDPTCTRL1_TXD_MASK                  0x20000u
42456 #define USB_ENDPTCTRL1_TXD_SHIFT                 17
42457 #define USB_ENDPTCTRL1_TXT_MASK                  0xC0000u
42458 #define USB_ENDPTCTRL1_TXT_SHIFT                 18
42459 #define USB_ENDPTCTRL1_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL1_TXT_SHIFT))&USB_ENDPTCTRL1_TXT_MASK)
42460 #define USB_ENDPTCTRL1_TXI_MASK                  0x200000u
42461 #define USB_ENDPTCTRL1_TXI_SHIFT                 21
42462 #define USB_ENDPTCTRL1_TXR_MASK                  0x400000u
42463 #define USB_ENDPTCTRL1_TXR_SHIFT                 22
42464 #define USB_ENDPTCTRL1_TXE_MASK                  0x800000u
42465 #define USB_ENDPTCTRL1_TXE_SHIFT                 23
42466 /* ENDPTCTRL2 Bit Fields */
42467 #define USB_ENDPTCTRL2_RXS_MASK                  0x1u
42468 #define USB_ENDPTCTRL2_RXS_SHIFT                 0
42469 #define USB_ENDPTCTRL2_RXD_MASK                  0x2u
42470 #define USB_ENDPTCTRL2_RXD_SHIFT                 1
42471 #define USB_ENDPTCTRL2_RXT_MASK                  0xCu
42472 #define USB_ENDPTCTRL2_RXT_SHIFT                 2
42473 #define USB_ENDPTCTRL2_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL2_RXT_SHIFT))&USB_ENDPTCTRL2_RXT_MASK)
42474 #define USB_ENDPTCTRL2_RXI_MASK                  0x20u
42475 #define USB_ENDPTCTRL2_RXI_SHIFT                 5
42476 #define USB_ENDPTCTRL2_RXR_MASK                  0x40u
42477 #define USB_ENDPTCTRL2_RXR_SHIFT                 6
42478 #define USB_ENDPTCTRL2_RXE_MASK                  0x80u
42479 #define USB_ENDPTCTRL2_RXE_SHIFT                 7
42480 #define USB_ENDPTCTRL2_TXS_MASK                  0x10000u
42481 #define USB_ENDPTCTRL2_TXS_SHIFT                 16
42482 #define USB_ENDPTCTRL2_TXD_MASK                  0x20000u
42483 #define USB_ENDPTCTRL2_TXD_SHIFT                 17
42484 #define USB_ENDPTCTRL2_TXT_MASK                  0xC0000u
42485 #define USB_ENDPTCTRL2_TXT_SHIFT                 18
42486 #define USB_ENDPTCTRL2_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL2_TXT_SHIFT))&USB_ENDPTCTRL2_TXT_MASK)
42487 #define USB_ENDPTCTRL2_TXI_MASK                  0x200000u
42488 #define USB_ENDPTCTRL2_TXI_SHIFT                 21
42489 #define USB_ENDPTCTRL2_TXR_MASK                  0x400000u
42490 #define USB_ENDPTCTRL2_TXR_SHIFT                 22
42491 #define USB_ENDPTCTRL2_TXE_MASK                  0x800000u
42492 #define USB_ENDPTCTRL2_TXE_SHIFT                 23
42493 /* ENDPTCTRL3 Bit Fields */
42494 #define USB_ENDPTCTRL3_RXS_MASK                  0x1u
42495 #define USB_ENDPTCTRL3_RXS_SHIFT                 0
42496 #define USB_ENDPTCTRL3_RXD_MASK                  0x2u
42497 #define USB_ENDPTCTRL3_RXD_SHIFT                 1
42498 #define USB_ENDPTCTRL3_RXT_MASK                  0xCu
42499 #define USB_ENDPTCTRL3_RXT_SHIFT                 2
42500 #define USB_ENDPTCTRL3_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL3_RXT_SHIFT))&USB_ENDPTCTRL3_RXT_MASK)
42501 #define USB_ENDPTCTRL3_RXI_MASK                  0x20u
42502 #define USB_ENDPTCTRL3_RXI_SHIFT                 5
42503 #define USB_ENDPTCTRL3_RXR_MASK                  0x40u
42504 #define USB_ENDPTCTRL3_RXR_SHIFT                 6
42505 #define USB_ENDPTCTRL3_RXE_MASK                  0x80u
42506 #define USB_ENDPTCTRL3_RXE_SHIFT                 7
42507 #define USB_ENDPTCTRL3_TXS_MASK                  0x10000u
42508 #define USB_ENDPTCTRL3_TXS_SHIFT                 16
42509 #define USB_ENDPTCTRL3_TXD_MASK                  0x20000u
42510 #define USB_ENDPTCTRL3_TXD_SHIFT                 17
42511 #define USB_ENDPTCTRL3_TXT_MASK                  0xC0000u
42512 #define USB_ENDPTCTRL3_TXT_SHIFT                 18
42513 #define USB_ENDPTCTRL3_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL3_TXT_SHIFT))&USB_ENDPTCTRL3_TXT_MASK)
42514 #define USB_ENDPTCTRL3_TXI_MASK                  0x200000u
42515 #define USB_ENDPTCTRL3_TXI_SHIFT                 21
42516 #define USB_ENDPTCTRL3_TXR_MASK                  0x400000u
42517 #define USB_ENDPTCTRL3_TXR_SHIFT                 22
42518 #define USB_ENDPTCTRL3_TXE_MASK                  0x800000u
42519 #define USB_ENDPTCTRL3_TXE_SHIFT                 23
42520 /* ENDPTCTRL4 Bit Fields */
42521 #define USB_ENDPTCTRL4_RXS_MASK                  0x1u
42522 #define USB_ENDPTCTRL4_RXS_SHIFT                 0
42523 #define USB_ENDPTCTRL4_RXD_MASK                  0x2u
42524 #define USB_ENDPTCTRL4_RXD_SHIFT                 1
42525 #define USB_ENDPTCTRL4_RXT_MASK                  0xCu
42526 #define USB_ENDPTCTRL4_RXT_SHIFT                 2
42527 #define USB_ENDPTCTRL4_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL4_RXT_SHIFT))&USB_ENDPTCTRL4_RXT_MASK)
42528 #define USB_ENDPTCTRL4_RXI_MASK                  0x20u
42529 #define USB_ENDPTCTRL4_RXI_SHIFT                 5
42530 #define USB_ENDPTCTRL4_RXR_MASK                  0x40u
42531 #define USB_ENDPTCTRL4_RXR_SHIFT                 6
42532 #define USB_ENDPTCTRL4_RXE_MASK                  0x80u
42533 #define USB_ENDPTCTRL4_RXE_SHIFT                 7
42534 #define USB_ENDPTCTRL4_TXS_MASK                  0x10000u
42535 #define USB_ENDPTCTRL4_TXS_SHIFT                 16
42536 #define USB_ENDPTCTRL4_TXD_MASK                  0x20000u
42537 #define USB_ENDPTCTRL4_TXD_SHIFT                 17
42538 #define USB_ENDPTCTRL4_TXT_MASK                  0xC0000u
42539 #define USB_ENDPTCTRL4_TXT_SHIFT                 18
42540 #define USB_ENDPTCTRL4_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL4_TXT_SHIFT))&USB_ENDPTCTRL4_TXT_MASK)
42541 #define USB_ENDPTCTRL4_TXI_MASK                  0x200000u
42542 #define USB_ENDPTCTRL4_TXI_SHIFT                 21
42543 #define USB_ENDPTCTRL4_TXR_MASK                  0x400000u
42544 #define USB_ENDPTCTRL4_TXR_SHIFT                 22
42545 #define USB_ENDPTCTRL4_TXE_MASK                  0x800000u
42546 #define USB_ENDPTCTRL4_TXE_SHIFT                 23
42547 /* ENDPTCTRL5 Bit Fields */
42548 #define USB_ENDPTCTRL5_RXS_MASK                  0x1u
42549 #define USB_ENDPTCTRL5_RXS_SHIFT                 0
42550 #define USB_ENDPTCTRL5_RXD_MASK                  0x2u
42551 #define USB_ENDPTCTRL5_RXD_SHIFT                 1
42552 #define USB_ENDPTCTRL5_RXT_MASK                  0xCu
42553 #define USB_ENDPTCTRL5_RXT_SHIFT                 2
42554 #define USB_ENDPTCTRL5_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL5_RXT_SHIFT))&USB_ENDPTCTRL5_RXT_MASK)
42555 #define USB_ENDPTCTRL5_RXI_MASK                  0x20u
42556 #define USB_ENDPTCTRL5_RXI_SHIFT                 5
42557 #define USB_ENDPTCTRL5_RXR_MASK                  0x40u
42558 #define USB_ENDPTCTRL5_RXR_SHIFT                 6
42559 #define USB_ENDPTCTRL5_RXE_MASK                  0x80u
42560 #define USB_ENDPTCTRL5_RXE_SHIFT                 7
42561 #define USB_ENDPTCTRL5_TXS_MASK                  0x10000u
42562 #define USB_ENDPTCTRL5_TXS_SHIFT                 16
42563 #define USB_ENDPTCTRL5_TXD_MASK                  0x20000u
42564 #define USB_ENDPTCTRL5_TXD_SHIFT                 17
42565 #define USB_ENDPTCTRL5_TXT_MASK                  0xC0000u
42566 #define USB_ENDPTCTRL5_TXT_SHIFT                 18
42567 #define USB_ENDPTCTRL5_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL5_TXT_SHIFT))&USB_ENDPTCTRL5_TXT_MASK)
42568 #define USB_ENDPTCTRL5_TXI_MASK                  0x200000u
42569 #define USB_ENDPTCTRL5_TXI_SHIFT                 21
42570 #define USB_ENDPTCTRL5_TXR_MASK                  0x400000u
42571 #define USB_ENDPTCTRL5_TXR_SHIFT                 22
42572 #define USB_ENDPTCTRL5_TXE_MASK                  0x800000u
42573 #define USB_ENDPTCTRL5_TXE_SHIFT                 23
42574 /* ENDPTCTRL6 Bit Fields */
42575 #define USB_ENDPTCTRL6_RXS_MASK                  0x1u
42576 #define USB_ENDPTCTRL6_RXS_SHIFT                 0
42577 #define USB_ENDPTCTRL6_RXD_MASK                  0x2u
42578 #define USB_ENDPTCTRL6_RXD_SHIFT                 1
42579 #define USB_ENDPTCTRL6_RXT_MASK                  0xCu
42580 #define USB_ENDPTCTRL6_RXT_SHIFT                 2
42581 #define USB_ENDPTCTRL6_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL6_RXT_SHIFT))&USB_ENDPTCTRL6_RXT_MASK)
42582 #define USB_ENDPTCTRL6_RXI_MASK                  0x20u
42583 #define USB_ENDPTCTRL6_RXI_SHIFT                 5
42584 #define USB_ENDPTCTRL6_RXR_MASK                  0x40u
42585 #define USB_ENDPTCTRL6_RXR_SHIFT                 6
42586 #define USB_ENDPTCTRL6_RXE_MASK                  0x80u
42587 #define USB_ENDPTCTRL6_RXE_SHIFT                 7
42588 #define USB_ENDPTCTRL6_TXS_MASK                  0x10000u
42589 #define USB_ENDPTCTRL6_TXS_SHIFT                 16
42590 #define USB_ENDPTCTRL6_TXD_MASK                  0x20000u
42591 #define USB_ENDPTCTRL6_TXD_SHIFT                 17
42592 #define USB_ENDPTCTRL6_TXT_MASK                  0xC0000u
42593 #define USB_ENDPTCTRL6_TXT_SHIFT                 18
42594 #define USB_ENDPTCTRL6_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL6_TXT_SHIFT))&USB_ENDPTCTRL6_TXT_MASK)
42595 #define USB_ENDPTCTRL6_TXI_MASK                  0x200000u
42596 #define USB_ENDPTCTRL6_TXI_SHIFT                 21
42597 #define USB_ENDPTCTRL6_TXR_MASK                  0x400000u
42598 #define USB_ENDPTCTRL6_TXR_SHIFT                 22
42599 #define USB_ENDPTCTRL6_TXE_MASK                  0x800000u
42600 #define USB_ENDPTCTRL6_TXE_SHIFT                 23
42601 /* ENDPTCTRL7 Bit Fields */
42602 #define USB_ENDPTCTRL7_RXS_MASK                  0x1u
42603 #define USB_ENDPTCTRL7_RXS_SHIFT                 0
42604 #define USB_ENDPTCTRL7_RXD_MASK                  0x2u
42605 #define USB_ENDPTCTRL7_RXD_SHIFT                 1
42606 #define USB_ENDPTCTRL7_RXT_MASK                  0xCu
42607 #define USB_ENDPTCTRL7_RXT_SHIFT                 2
42608 #define USB_ENDPTCTRL7_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL7_RXT_SHIFT))&USB_ENDPTCTRL7_RXT_MASK)
42609 #define USB_ENDPTCTRL7_RXI_MASK                  0x20u
42610 #define USB_ENDPTCTRL7_RXI_SHIFT                 5
42611 #define USB_ENDPTCTRL7_RXR_MASK                  0x40u
42612 #define USB_ENDPTCTRL7_RXR_SHIFT                 6
42613 #define USB_ENDPTCTRL7_RXE_MASK                  0x80u
42614 #define USB_ENDPTCTRL7_RXE_SHIFT                 7
42615 #define USB_ENDPTCTRL7_TXS_MASK                  0x10000u
42616 #define USB_ENDPTCTRL7_TXS_SHIFT                 16
42617 #define USB_ENDPTCTRL7_TXD_MASK                  0x20000u
42618 #define USB_ENDPTCTRL7_TXD_SHIFT                 17
42619 #define USB_ENDPTCTRL7_TXT_MASK                  0xC0000u
42620 #define USB_ENDPTCTRL7_TXT_SHIFT                 18
42621 #define USB_ENDPTCTRL7_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL7_TXT_SHIFT))&USB_ENDPTCTRL7_TXT_MASK)
42622 #define USB_ENDPTCTRL7_TXI_MASK                  0x200000u
42623 #define USB_ENDPTCTRL7_TXI_SHIFT                 21
42624 #define USB_ENDPTCTRL7_TXR_MASK                  0x400000u
42625 #define USB_ENDPTCTRL7_TXR_SHIFT                 22
42626 #define USB_ENDPTCTRL7_TXE_MASK                  0x800000u
42627 #define USB_ENDPTCTRL7_TXE_SHIFT                 23
42628 
42629 /*!
42630  * @}
42631  */ /* end of group USB_Register_Masks */
42632 
42633 /* USB - Peripheral instance base addresses */
42634 /** Peripheral USB1 base address */
42635 #define USB1_BASE                                (0x30B10000u)
42636 /** Peripheral USB1 base pointer */
42637 #define USB1                                     ((USB_Type *)USB1_BASE)
42638 #define USB1_BASE_PTR                            (USB1)
42639 /** Peripheral USB2 base address */
42640 #define USB2_BASE                                (0x30B20000u)
42641 /** Peripheral USB2 base pointer */
42642 #define USB2                                     ((USB_Type *)USB2_BASE)
42643 #define USB2_BASE_PTR                            (USB2)
42644 /** Peripheral USB3 base address */
42645 #define USB3_BASE                                (0x30B30000u)
42646 /** Peripheral USB3 base pointer */
42647 #define USB3                                     ((USB_Type *)USB3_BASE)
42648 #define USB3_BASE_PTR                            (USB3)
42649 /** Array initializer of USB peripheral base addresses */
42650 #define USB_BASE_ADDRS                           { USB1_BASE, USB2_BASE, USB3_BASE }
42651 /** Array initializer of USB peripheral base pointers */
42652 #define USB_BASE_PTRS                            { USB1, USB2, USB3 }
42653 /* ----------------------------------------------------------------------------
42654    -- USB - Register accessor macros
42655    ---------------------------------------------------------------------------- */
42656 
42657 /*!
42658  * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
42659  * @{
42660  */
42661 
42662 
42663 /* USB - Register instance definitions */
42664 /* USB1 */
42665 #define USB1_ID                                  USB_ID_REG(USB1_BASE_PTR)
42666 #define USB1_HWGENERAL                           USB_HWGENERAL_REG(USB1_BASE_PTR)
42667 #define USB1_HWHOST                              USB_HWHOST_REG(USB1_BASE_PTR)
42668 #define USB1_HWDEVICE                            USB_HWDEVICE_REG(USB1_BASE_PTR)
42669 #define USB1_HWTXBUF                             USB_HWTXBUF_REG(USB1_BASE_PTR)
42670 #define USB1_HWRXBUF                             USB_HWRXBUF_REG(USB1_BASE_PTR)
42671 #define USB1_GPTIMER0LD                          USB_GPTIMER0LD_REG(USB1_BASE_PTR)
42672 #define USB1_GPTIMER0CTRL                        USB_GPTIMER0CTRL_REG(USB1_BASE_PTR)
42673 #define USB1_GPTIMER1LD                          USB_GPTIMER1LD_REG(USB1_BASE_PTR)
42674 #define USB1_GPTIMER1CTRL                        USB_GPTIMER1CTRL_REG(USB1_BASE_PTR)
42675 #define USB1_SBUSCFG                             USB_SBUSCFG_REG(USB1_BASE_PTR)
42676 #define USB1_CAPLENGTH                           USB_CAPLENGTH_REG(USB1_BASE_PTR)
42677 #define USB1_HCIVERSION                          USB_HCIVERSION_REG(USB1_BASE_PTR)
42678 #define USB1_HCSPARAMS                           USB_HCSPARAMS_REG(USB1_BASE_PTR)
42679 #define USB1_HCCPARAMS                           USB_HCCPARAMS_REG(USB1_BASE_PTR)
42680 #define USB1_DCIVERSION                          USB_DCIVERSION_REG(USB1_BASE_PTR)
42681 #define USB1_DCCPARAMS                           USB_DCCPARAMS_REG(USB1_BASE_PTR)
42682 #define USB1_USBCMD                              USB_USBCMD_REG(USB1_BASE_PTR)
42683 #define USB1_USBSTS                              USB_USBSTS_REG(USB1_BASE_PTR)
42684 #define USB1_USBINTR                             USB_USBINTR_REG(USB1_BASE_PTR)
42685 #define USB1_FRINDEX                             USB_FRINDEX_REG(USB1_BASE_PTR)
42686 #define USB1_PERIODICLISTBASE                    USB_PERIODICLISTBASE_REG(USB1_BASE_PTR)
42687 #define USB1_DEVICEADDR                          USB_DEVICEADDR_REG(USB1_BASE_PTR)
42688 #define USB1_ASYNCLISTADDR                       USB_ASYNCLISTADDR_REG(USB1_BASE_PTR)
42689 #define USB1_ENDPTLISTADDR                       USB_ENDPTLISTADDR_REG(USB1_BASE_PTR)
42690 #define USB1_BURSTSIZE                           USB_BURSTSIZE_REG(USB1_BASE_PTR)
42691 #define USB1_TXFILLTUNING                        USB_TXFILLTUNING_REG(USB1_BASE_PTR)
42692 #define USB1_ENDPTNAK                            USB_ENDPTNAK_REG(USB1_BASE_PTR)
42693 #define USB1_ENDPTNAKEN                          USB_ENDPTNAKEN_REG(USB1_BASE_PTR)
42694 #define USB1_CONFIGFLAG                          USB_CONFIGFLAG_REG(USB1_BASE_PTR)
42695 #define USB1_PORTSC1                             USB_PORTSC1_REG(USB1_BASE_PTR)
42696 #define USB1_OTGSC                               USB_OTGSC_REG(USB1_BASE_PTR)
42697 #define USB1_USBMODE                             USB_USBMODE_REG(USB1_BASE_PTR)
42698 #define USB1_ENDPTSETUPSTAT                      USB_ENDPTSETUPSTAT_REG(USB1_BASE_PTR)
42699 #define USB1_ENDPTPRIME                          USB_ENDPTPRIME_REG(USB1_BASE_PTR)
42700 #define USB1_ENDPTFLUSH                          USB_ENDPTFLUSH_REG(USB1_BASE_PTR)
42701 #define USB1_ENDPTSTAT                           USB_ENDPTSTAT_REG(USB1_BASE_PTR)
42702 #define USB1_ENDPTCOMPLETE                       USB_ENDPTCOMPLETE_REG(USB1_BASE_PTR)
42703 #define USB1_ENDPTCTRL0                          USB_ENDPTCTRL0_REG(USB1_BASE_PTR)
42704 #define USB1_ENDPTCTRL1                          USB_ENDPTCTRL1_REG(USB1_BASE_PTR)
42705 #define USB1_ENDPTCTRL2                          USB_ENDPTCTRL2_REG(USB1_BASE_PTR)
42706 #define USB1_ENDPTCTRL3                          USB_ENDPTCTRL3_REG(USB1_BASE_PTR)
42707 #define USB1_ENDPTCTRL4                          USB_ENDPTCTRL4_REG(USB1_BASE_PTR)
42708 #define USB1_ENDPTCTRL5                          USB_ENDPTCTRL5_REG(USB1_BASE_PTR)
42709 #define USB1_ENDPTCTRL6                          USB_ENDPTCTRL6_REG(USB1_BASE_PTR)
42710 #define USB1_ENDPTCTRL7                          USB_ENDPTCTRL7_REG(USB1_BASE_PTR)
42711 /* USB2 */
42712 #define USB2_ID                                  USB_ID_REG(USB2_BASE_PTR)
42713 #define USB2_HWGENERAL                           USB_HWGENERAL_REG(USB2_BASE_PTR)
42714 #define USB2_HWHOST                              USB_HWHOST_REG(USB2_BASE_PTR)
42715 #define USB2_HWDEVICE                            USB_HWDEVICE_REG(USB2_BASE_PTR)
42716 #define USB2_HWTXBUF                             USB_HWTXBUF_REG(USB2_BASE_PTR)
42717 #define USB2_HWRXBUF                             USB_HWRXBUF_REG(USB2_BASE_PTR)
42718 #define USB2_GPTIMER0LD                          USB_GPTIMER0LD_REG(USB2_BASE_PTR)
42719 #define USB2_GPTIMER0CTRL                        USB_GPTIMER0CTRL_REG(USB2_BASE_PTR)
42720 #define USB2_GPTIMER1LD                          USB_GPTIMER1LD_REG(USB2_BASE_PTR)
42721 #define USB2_GPTIMER1CTRL                        USB_GPTIMER1CTRL_REG(USB2_BASE_PTR)
42722 #define USB2_SBUSCFG                             USB_SBUSCFG_REG(USB2_BASE_PTR)
42723 #define USB2_CAPLENGTH                           USB_CAPLENGTH_REG(USB2_BASE_PTR)
42724 #define USB2_HCIVERSION                          USB_HCIVERSION_REG(USB2_BASE_PTR)
42725 #define USB2_HCSPARAMS                           USB_HCSPARAMS_REG(USB2_BASE_PTR)
42726 #define USB2_HCCPARAMS                           USB_HCCPARAMS_REG(USB2_BASE_PTR)
42727 #define USB2_DCIVERSION                          USB_DCIVERSION_REG(USB2_BASE_PTR)
42728 #define USB2_DCCPARAMS                           USB_DCCPARAMS_REG(USB2_BASE_PTR)
42729 #define USB2_USBCMD                              USB_USBCMD_REG(USB2_BASE_PTR)
42730 #define USB2_USBSTS                              USB_USBSTS_REG(USB2_BASE_PTR)
42731 #define USB2_USBINTR                             USB_USBINTR_REG(USB2_BASE_PTR)
42732 #define USB2_FRINDEX                             USB_FRINDEX_REG(USB2_BASE_PTR)
42733 #define USB2_PERIODICLISTBASE                    USB_PERIODICLISTBASE_REG(USB2_BASE_PTR)
42734 #define USB2_DEVICEADDR                          USB_DEVICEADDR_REG(USB2_BASE_PTR)
42735 #define USB2_ASYNCLISTADDR                       USB_ASYNCLISTADDR_REG(USB2_BASE_PTR)
42736 #define USB2_ENDPTLISTADDR                       USB_ENDPTLISTADDR_REG(USB2_BASE_PTR)
42737 #define USB2_BURSTSIZE                           USB_BURSTSIZE_REG(USB2_BASE_PTR)
42738 #define USB2_TXFILLTUNING                        USB_TXFILLTUNING_REG(USB2_BASE_PTR)
42739 #define USB2_ENDPTNAK                            USB_ENDPTNAK_REG(USB2_BASE_PTR)
42740 #define USB2_ENDPTNAKEN                          USB_ENDPTNAKEN_REG(USB2_BASE_PTR)
42741 #define USB2_CONFIGFLAG                          USB_CONFIGFLAG_REG(USB2_BASE_PTR)
42742 #define USB2_PORTSC1                             USB_PORTSC1_REG(USB2_BASE_PTR)
42743 #define USB2_OTGSC                               USB_OTGSC_REG(USB2_BASE_PTR)
42744 #define USB2_USBMODE                             USB_USBMODE_REG(USB2_BASE_PTR)
42745 #define USB2_ENDPTSETUPSTAT                      USB_ENDPTSETUPSTAT_REG(USB2_BASE_PTR)
42746 #define USB2_ENDPTPRIME                          USB_ENDPTPRIME_REG(USB2_BASE_PTR)
42747 #define USB2_ENDPTFLUSH                          USB_ENDPTFLUSH_REG(USB2_BASE_PTR)
42748 #define USB2_ENDPTSTAT                           USB_ENDPTSTAT_REG(USB2_BASE_PTR)
42749 #define USB2_ENDPTCOMPLETE                       USB_ENDPTCOMPLETE_REG(USB2_BASE_PTR)
42750 #define USB2_ENDPTCTRL0                          USB_ENDPTCTRL0_REG(USB2_BASE_PTR)
42751 #define USB2_ENDPTCTRL1                          USB_ENDPTCTRL1_REG(USB2_BASE_PTR)
42752 #define USB2_ENDPTCTRL2                          USB_ENDPTCTRL2_REG(USB2_BASE_PTR)
42753 #define USB2_ENDPTCTRL3                          USB_ENDPTCTRL3_REG(USB2_BASE_PTR)
42754 #define USB2_ENDPTCTRL4                          USB_ENDPTCTRL4_REG(USB2_BASE_PTR)
42755 #define USB2_ENDPTCTRL5                          USB_ENDPTCTRL5_REG(USB2_BASE_PTR)
42756 #define USB2_ENDPTCTRL6                          USB_ENDPTCTRL6_REG(USB2_BASE_PTR)
42757 #define USB2_ENDPTCTRL7                          USB_ENDPTCTRL7_REG(USB2_BASE_PTR)
42758 /* USB3 */
42759 #define USB3_ID                                  USB_ID_REG(USB3_BASE_PTR)
42760 #define USB3_HWGENERAL                           USB_HWGENERAL_REG(USB3_BASE_PTR)
42761 #define USB3_HWHOST                              USB_HWHOST_REG(USB3_BASE_PTR)
42762 #define USB3_HWDEVICE                            USB_HWDEVICE_REG(USB3_BASE_PTR)
42763 #define USB3_HWTXBUF                             USB_HWTXBUF_REG(USB3_BASE_PTR)
42764 #define USB3_HWRXBUF                             USB_HWRXBUF_REG(USB3_BASE_PTR)
42765 #define USB3_GPTIMER0LD                          USB_GPTIMER0LD_REG(USB3_BASE_PTR)
42766 #define USB3_GPTIMER0CTRL                        USB_GPTIMER0CTRL_REG(USB3_BASE_PTR)
42767 #define USB3_GPTIMER1LD                          USB_GPTIMER1LD_REG(USB3_BASE_PTR)
42768 #define USB3_GPTIMER1CTRL                        USB_GPTIMER1CTRL_REG(USB3_BASE_PTR)
42769 #define USB3_SBUSCFG                             USB_SBUSCFG_REG(USB3_BASE_PTR)
42770 #define USB3_CAPLENGTH                           USB_CAPLENGTH_REG(USB3_BASE_PTR)
42771 #define USB3_HCIVERSION                          USB_HCIVERSION_REG(USB3_BASE_PTR)
42772 #define USB3_HCSPARAMS                           USB_HCSPARAMS_REG(USB3_BASE_PTR)
42773 #define USB3_HCCPARAMS                           USB_HCCPARAMS_REG(USB3_BASE_PTR)
42774 #define USB3_DCIVERSION                          USB_DCIVERSION_REG(USB3_BASE_PTR)
42775 #define USB3_DCCPARAMS                           USB_DCCPARAMS_REG(USB3_BASE_PTR)
42776 #define USB3_USBCMD                              USB_USBCMD_REG(USB3_BASE_PTR)
42777 #define USB3_USBSTS                              USB_USBSTS_REG(USB3_BASE_PTR)
42778 #define USB3_USBINTR                             USB_USBINTR_REG(USB3_BASE_PTR)
42779 #define USB3_FRINDEX                             USB_FRINDEX_REG(USB3_BASE_PTR)
42780 #define USB3_PERIODICLISTBASE                    USB_PERIODICLISTBASE_REG(USB3_BASE_PTR)
42781 #define USB3_DEVICEADDR                          USB_DEVICEADDR_REG(USB3_BASE_PTR)
42782 #define USB3_ASYNCLISTADDR                       USB_ASYNCLISTADDR_REG(USB3_BASE_PTR)
42783 #define USB3_ENDPTLISTADDR                       USB_ENDPTLISTADDR_REG(USB3_BASE_PTR)
42784 #define USB3_BURSTSIZE                           USB_BURSTSIZE_REG(USB3_BASE_PTR)
42785 #define USB3_TXFILLTUNING                        USB_TXFILLTUNING_REG(USB3_BASE_PTR)
42786 #define USB3_ENDPTNAK                            USB_ENDPTNAK_REG(USB3_BASE_PTR)
42787 #define USB3_ENDPTNAKEN                          USB_ENDPTNAKEN_REG(USB3_BASE_PTR)
42788 #define USB3_CONFIGFLAG                          USB_CONFIGFLAG_REG(USB3_BASE_PTR)
42789 #define USB3_PORTSC1                             USB_PORTSC1_REG(USB3_BASE_PTR)
42790 #define USB3_OTGSC                               USB_OTGSC_REG(USB3_BASE_PTR)
42791 #define USB3_USBMODE                             USB_USBMODE_REG(USB3_BASE_PTR)
42792 #define USB3_ENDPTSETUPSTAT                      USB_ENDPTSETUPSTAT_REG(USB3_BASE_PTR)
42793 #define USB3_ENDPTPRIME                          USB_ENDPTPRIME_REG(USB3_BASE_PTR)
42794 #define USB3_ENDPTFLUSH                          USB_ENDPTFLUSH_REG(USB3_BASE_PTR)
42795 #define USB3_ENDPTSTAT                           USB_ENDPTSTAT_REG(USB3_BASE_PTR)
42796 #define USB3_ENDPTCOMPLETE                       USB_ENDPTCOMPLETE_REG(USB3_BASE_PTR)
42797 #define USB3_ENDPTCTRL0                          USB_ENDPTCTRL0_REG(USB3_BASE_PTR)
42798 #define USB3_ENDPTCTRL1                          USB_ENDPTCTRL1_REG(USB3_BASE_PTR)
42799 #define USB3_ENDPTCTRL2                          USB_ENDPTCTRL2_REG(USB3_BASE_PTR)
42800 #define USB3_ENDPTCTRL3                          USB_ENDPTCTRL3_REG(USB3_BASE_PTR)
42801 #define USB3_ENDPTCTRL4                          USB_ENDPTCTRL4_REG(USB3_BASE_PTR)
42802 #define USB3_ENDPTCTRL5                          USB_ENDPTCTRL5_REG(USB3_BASE_PTR)
42803 #define USB3_ENDPTCTRL6                          USB_ENDPTCTRL6_REG(USB3_BASE_PTR)
42804 #define USB3_ENDPTCTRL7                          USB_ENDPTCTRL7_REG(USB3_BASE_PTR)
42805 /*!
42806  * @}
42807  */ /* end of group USB_Register_Accessor_Macros */
42808 
42809 
42810 /*!
42811  * @}
42812  */ /* end of group USB_Peripheral */
42813 
42814 /* ----------------------------------------------------------------------------
42815    -- USBNC Peripheral Access Layer
42816    ---------------------------------------------------------------------------- */
42817 
42818 /*!
42819  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
42820  * @{
42821  */
42822 
42823 /** USBNC - Register Layout Typedef */
42824 typedef struct {
42825   uint8_t RESERVED_0[512];
42826   __IO  uint32_t OTG1_CTRL1;                             /**< , offset: 0x200 */
42827   __IO  uint32_t OTG1_CTRL2;                             /**< , offset: 0x204 */
42828   uint8_t RESERVED_1[40];
42829   __IO  uint32_t OTG1_PHY_CFG1;                          /**< , offset: 0x230 */
42830   __IO  uint32_t OTG1_PHY_CFG2;                          /**< , offset: 0x234 */
42831   uint8_t RESERVED_2[4];
42832   __I   uint32_t OTG1_PHY_STATUS;                        /**< , offset: 0x23C */
42833   uint8_t RESERVED_3[16];
42834   __IO  uint32_t ADP_CFG1;                               /**< , offset: 0x250 */
42835   __IO  uint32_t ADP_CFG2;                               /**< , offset: 0x254 */
42836   __I   uint32_t ADP_STATUS;                             /**< , offset: 0x258 */
42837   uint8_t RESERVED_4[65444];
42838   __IO  uint32_t OTG2_CTRL1;                             /**< , offset: 0x10200 */
42839   __IO  uint32_t OTG2_CTRL2;                             /**< , offset: 0x10204 */
42840   uint8_t RESERVED_5[40];
42841   __IO  uint32_t OTG2_PHY_CFG1;                          /**< , offset: 0x10230 */
42842   __IO  uint32_t OTG2_PHY_CFG2;                          /**< , offset: 0x10234 */
42843   uint8_t RESERVED_6[4];
42844   __I   uint32_t OTG2_PHY_STATUS;                        /**< , offset: 0x1023C */
42845   uint8_t RESERVED_7[65472];
42846   __IO  uint32_t HSIC_CTRL1;                             /**< , offset: 0x20200 */
42847   __IO  uint32_t HSIC_CTRL2;                             /**< , offset: 0x20204 */
42848   uint8_t RESERVED_8[56];
42849   __IO  uint32_t UH_HSICPHY_CFG1;                        /**< , offset: 0x20240 */
42850 } USBNC_Type, *USBNC_MemMapPtr;
42851 /* ----------------------------------------------------------------------------
42852    -- USBNC - Register accessor macros
42853    ---------------------------------------------------------------------------- */
42854 
42855 /*!
42856  * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros
42857  * @{
42858  */
42859 
42860 
42861 /* USBNC - Register accessors */
42862 #define USBNC_OTG1_CTRL1_REG(base)               ((base)->OTG1_CTRL1)
42863 #define USBNC_OTG1_CTRL2_REG(base)               ((base)->OTG1_CTRL2)
42864 #define USBNC_OTG1_PHY_CFG1_REG(base)            ((base)->OTG1_PHY_CFG1)
42865 #define USBNC_OTG1_PHY_CFG2_REG(base)            ((base)->OTG1_PHY_CFG2)
42866 #define USBNC_OTG1_PHY_STATUS_REG(base)          ((base)->OTG1_PHY_STATUS)
42867 #define USBNC_ADP_CFG1_REG(base)                 ((base)->ADP_CFG1)
42868 #define USBNC_ADP_CFG2_REG(base)                 ((base)->ADP_CFG2)
42869 #define USBNC_ADP_STATUS_REG(base)               ((base)->ADP_STATUS)
42870 #define USBNC_OTG2_CTRL1_REG(base)               ((base)->OTG2_CTRL1)
42871 #define USBNC_OTG2_CTRL2_REG(base)               ((base)->OTG2_CTRL2)
42872 #define USBNC_OTG2_PHY_CFG1_REG(base)            ((base)->OTG2_PHY_CFG1)
42873 #define USBNC_OTG2_PHY_CFG2_REG(base)            ((base)->OTG2_PHY_CFG2)
42874 #define USBNC_OTG2_PHY_STATUS_REG(base)          ((base)->OTG2_PHY_STATUS)
42875 #define USBNC_HSIC_CTRL1_REG(base)               ((base)->HSIC_CTRL1)
42876 #define USBNC_HSIC_CTRL2_REG(base)               ((base)->HSIC_CTRL2)
42877 #define USBNC_UH_HSICPHY_CFG1_REG(base)          ((base)->UH_HSICPHY_CFG1)
42878 
42879 /*!
42880  * @}
42881  */ /* end of group USBNC_Register_Accessor_Macros */
42882 /* ----------------------------------------------------------------------------
42883    -- USBNC Register Masks
42884    ---------------------------------------------------------------------------- */
42885 
42886 /*!
42887  * @addtogroup USBNC_Register_Masks USBNC Register Masks
42888  * @{
42889  */
42890 
42891 /* OTG1_CTRL1 Bit Fields */
42892 #define USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK       0x80u
42893 #define USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT      7
42894 #define USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK       0x100u
42895 #define USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT      8
42896 #define USBNC_OTG1_CTRL1_PWR_POL_MASK            0x200u
42897 #define USBNC_OTG1_CTRL1_PWR_POL_SHIFT           9
42898 #define USBNC_OTG1_CTRL1_WIE_MASK                0x400u
42899 #define USBNC_OTG1_CTRL1_WIE_SHIFT               10
42900 #define USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK         0x4000u
42901 #define USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT        14
42902 #define USBNC_OTG1_CTRL1_WKUP_SW_MASK            0x8000u
42903 #define USBNC_OTG1_CTRL1_WKUP_SW_SHIFT           15
42904 #define USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK         0x10000u
42905 #define USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT        16
42906 #define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK       0x20000u
42907 #define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT      17
42908 #define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK       0x20000000u
42909 #define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT      29
42910 #define USBNC_OTG1_CTRL1_WIR_MASK                0x80000000u
42911 #define USBNC_OTG1_CTRL1_WIR_SHIFT               31
42912 /* OTG1_CTRL2 Bit Fields */
42913 #define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK    0x3u
42914 #define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT   0
42915 #define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK)
42916 #define USBNC_OTG1_CTRL2_AUTURESUME_EN_MASK      0x4u
42917 #define USBNC_OTG1_CTRL2_AUTURESUME_EN_SHIFT     2
42918 #define USBNC_OTG1_CTRL2_LOWSPEED_EN_MASK        0x8u
42919 #define USBNC_OTG1_CTRL2_LOWSPEED_EN_SHIFT       3
42920 #define USBNC_OTG1_CTRL2_DIG_ID_SEL_MASK         0x100000u
42921 #define USBNC_OTG1_CTRL2_DIG_ID_SEL_SHIFT        20
42922 #define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_MASK       0x80000000u
42923 #define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_SHIFT      31
42924 /* OTG1_PHY_CFG1 Bit Fields */
42925 #define USBNC_OTG1_PHY_CFG1_COMMONONN_MASK       0x1u
42926 #define USBNC_OTG1_PHY_CFG1_COMMONONN_SHIFT      0
42927 #define USBNC_OTG1_PHY_CFG1_FSEL_MASK            0xEu
42928 #define USBNC_OTG1_PHY_CFG1_FSEL_SHIFT           1
42929 #define USBNC_OTG1_PHY_CFG1_FSEL(x)              (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_FSEL_SHIFT))&USBNC_OTG1_PHY_CFG1_FSEL_MASK)
42930 #define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK    0x70u
42931 #define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT   4
42932 #define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK)
42933 #define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK       0x380u
42934 #define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT      7
42935 #define USBNC_OTG1_PHY_CFG1_SQRXTUNE0(x)         (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK)
42936 #define USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK        0x1C00u
42937 #define USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT       10
42938 #define USBNC_OTG1_PHY_CFG1_OTGTUNE0(x)          (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK)
42939 #define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK     0x6000u
42940 #define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT    13
42941 #define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK)
42942 #define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK     0xF0000u
42943 #define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT    16
42944 #define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK)
42945 #define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK     0xF00000u
42946 #define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT    20
42947 #define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK)
42948 #define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK     0x3000000u
42949 #define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT    24
42950 #define USBNC_OTG1_PHY_CFG1_TXRISETUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK)
42951 #define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK      0xC000000u
42952 #define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT     26
42953 #define USBNC_OTG1_PHY_CFG1_TXRESTUNE0(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK)
42954 #define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK 0x30000000u
42955 #define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT 28
42956 #define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0(x)  (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK)
42957 #define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_MASK 0x40000000u
42958 #define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT 30
42959 #define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_MASK 0x80000000u
42960 #define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_SHIFT 31
42961 /* OTG1_PHY_CFG2 Bit Fields */
42962 #define USBNC_OTG1_PHY_CFG2_CHRGSEL_MASK         0x1u
42963 #define USBNC_OTG1_PHY_CFG2_CHRGSEL_SHIFT        0
42964 #define USBNC_OTG1_PHY_CFG2_VDATDETENB0_MASK     0x2u
42965 #define USBNC_OTG1_PHY_CFG2_VDATDETENB0_SHIFT    1
42966 #define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_MASK     0x4u
42967 #define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_SHIFT    2
42968 #define USBNC_OTG1_PHY_CFG2_DCDENB_MASK          0x8u
42969 #define USBNC_OTG1_PHY_CFG2_DCDENB_SHIFT         3
42970 #define USBNC_OTG1_PHY_CFG2_ACAENB0_MASK         0x10u
42971 #define USBNC_OTG1_PHY_CFG2_ACAENB0_SHIFT        4
42972 #define USBNC_OTG1_PHY_CFG2_SLEEPM0_MASK         0x20u
42973 #define USBNC_OTG1_PHY_CFG2_SLEEPM0_SHIFT        5
42974 #define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_MASK    0x40u
42975 #define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_SHIFT   6
42976 #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_MASK   0x100u
42977 #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_SHIFT  8
42978 #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_MASK  0x200u
42979 #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_SHIFT 9
42980 #define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_MASK     0x400u
42981 #define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_SHIFT    10
42982 #define USBNC_OTG1_PHY_CFG2_ADPCHRG0_MASK        0x800u
42983 #define USBNC_OTG1_PHY_CFG2_ADPCHRG0_SHIFT       11
42984 #define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_MASK     0x1000u
42985 #define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_SHIFT    12
42986 #define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_MASK      0x2000u
42987 #define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_SHIFT     13
42988 #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_MASK  0x4000u
42989 #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT 14
42990 #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_MASK      0x8000u
42991 #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_SHIFT     15
42992 #define USBNC_OTG1_PHY_CFG2_DRVVBUS0_MASK        0x10000u
42993 #define USBNC_OTG1_PHY_CFG2_DRVVBUS0_SHIFT       16
42994 /* OTG1_PHY_STATUS Bit Fields */
42995 #define USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK    0x3u
42996 #define USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT   0
42997 #define USBNC_OTG1_PHY_STATUS_LINE_STATE(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT))&USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK)
42998 #define USBNC_OTG1_PHY_STATUS_SESS_VLD_MASK      0x4u
42999 #define USBNC_OTG1_PHY_STATUS_SESS_VLD_SHIFT     2
43000 #define USBNC_OTG1_PHY_STATUS_VBUS_VLD_MASK      0x8u
43001 #define USBNC_OTG1_PHY_STATUS_VBUS_VLD_SHIFT     3
43002 #define USBNC_OTG1_PHY_STATUS_ID_DIG_MASK        0x10u
43003 #define USBNC_OTG1_PHY_STATUS_ID_DIG_SHIFT       4
43004 #define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_MASK 0x20u
43005 #define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_SHIFT 5
43006 #define USBNC_OTG1_PHY_STATUS_RIDC0_MASK         0x1000000u
43007 #define USBNC_OTG1_PHY_STATUS_RIDC0_SHIFT        24
43008 #define USBNC_OTG1_PHY_STATUS_RIDB0_MASK         0x2000000u
43009 #define USBNC_OTG1_PHY_STATUS_RIDB0_SHIFT        25
43010 #define USBNC_OTG1_PHY_STATUS_RIDA0_MASK         0x4000000u
43011 #define USBNC_OTG1_PHY_STATUS_RIDA0_SHIFT        26
43012 #define USBNC_OTG1_PHY_STATUS_RIDGND0_MASK       0x8000000u
43013 #define USBNC_OTG1_PHY_STATUS_RIDGND0_SHIFT      27
43014 #define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_MASK     0x10000000u
43015 #define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_SHIFT    28
43016 #define USBNC_OTG1_PHY_STATUS_CHRGDET_MASK       0x20000000u
43017 #define USBNC_OTG1_PHY_STATUS_CHRGDET_SHIFT      29
43018 #define USBNC_OTG1_PHY_STATUS_ADPPRB0_MASK       0x40000000u
43019 #define USBNC_OTG1_PHY_STATUS_ADPPRB0_SHIFT      30
43020 #define USBNC_OTG1_PHY_STATUS_ADPSNS0_MASK       0x80000000u
43021 #define USBNC_OTG1_PHY_STATUS_ADPSNS0_SHIFT      31
43022 /* ADP_CFG1 Bit Fields */
43023 #define USBNC_ADP_CFG1_ADP_WAIT_MASK             0x3FFFFu
43024 #define USBNC_ADP_CFG1_ADP_WAIT_SHIFT            0
43025 #define USBNC_ADP_CFG1_ADP_WAIT(x)               (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG1_ADP_WAIT_SHIFT))&USBNC_ADP_CFG1_ADP_WAIT_MASK)
43026 #define USBNC_ADP_CFG1_TIMER_EN_MASK             0x100000u
43027 #define USBNC_ADP_CFG1_TIMER_EN_SHIFT            20
43028 #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK       0x200000u
43029 #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT      21
43030 #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK       0x400000u
43031 #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT      22
43032 #define USBNC_ADP_CFG1_ADP_PRB_EN_MASK           0x800000u
43033 #define USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT          23
43034 /* ADP_CFG2 Bit Fields */
43035 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK       0x7Fu
43036 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT      0
43037 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x)         (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK)
43038 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK       0x80u
43039 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT      7
43040 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK      0xFF00u
43041 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT     8
43042 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK)
43043 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK      0xFF0000u
43044 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT     16
43045 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT))&USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK)
43046 /* ADP_STATUS Bit Fields */
43047 #define USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK       0xFFu
43048 #define USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT      0
43049 #define USBNC_ADP_STATUS_ADP_PRB_TIMR(x)         (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT))&USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK)
43050 #define USBNC_ADP_STATUS_ADP_CNT_MASK            0x3FFFF00u
43051 #define USBNC_ADP_STATUS_ADP_CNT_SHIFT           8
43052 #define USBNC_ADP_STATUS_ADP_CNT(x)              (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_STATUS_ADP_CNT_SHIFT))&USBNC_ADP_STATUS_ADP_CNT_MASK)
43053 #define USBNC_ADP_STATUS_ADP_SNS_INT_MASK        0x4000000u
43054 #define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT       26
43055 #define USBNC_ADP_STATUS_ADP_PRB_INT_MASK        0x8000000u
43056 #define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT       27
43057 /* OTG2_CTRL1 Bit Fields */
43058 #define USBNC_OTG2_CTRL1_OVER_CUR_DIS_MASK       0x80u
43059 #define USBNC_OTG2_CTRL1_OVER_CUR_DIS_SHIFT      7
43060 #define USBNC_OTG2_CTRL1_OVER_CUR_POL_MASK       0x100u
43061 #define USBNC_OTG2_CTRL1_OVER_CUR_POL_SHIFT      8
43062 #define USBNC_OTG2_CTRL1_PWR_POL_MASK            0x200u
43063 #define USBNC_OTG2_CTRL1_PWR_POL_SHIFT           9
43064 #define USBNC_OTG2_CTRL1_WIE_MASK                0x400u
43065 #define USBNC_OTG2_CTRL1_WIE_SHIFT               10
43066 #define USBNC_OTG2_CTRL1_WKUP_SW_EN_MASK         0x4000u
43067 #define USBNC_OTG2_CTRL1_WKUP_SW_EN_SHIFT        14
43068 #define USBNC_OTG2_CTRL1_WKUP_SW_MASK            0x8000u
43069 #define USBNC_OTG2_CTRL1_WKUP_SW_SHIFT           15
43070 #define USBNC_OTG2_CTRL1_WKUP_ID_EN_MASK         0x10000u
43071 #define USBNC_OTG2_CTRL1_WKUP_ID_EN_SHIFT        16
43072 #define USBNC_OTG2_CTRL1_WKUP_VBUS_EN_MASK       0x20000u
43073 #define USBNC_OTG2_CTRL1_WKUP_VBUS_EN_SHIFT      17
43074 #define USBNC_OTG2_CTRL1_WKUP_DPDM_EN_MASK       0x20000000u
43075 #define USBNC_OTG2_CTRL1_WKUP_DPDM_EN_SHIFT      29
43076 #define USBNC_OTG2_CTRL1_WIR_MASK                0x80000000u
43077 #define USBNC_OTG2_CTRL1_WIR_SHIFT               31
43078 /* OTG2_CTRL2 Bit Fields */
43079 #define USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_MASK    0x3u
43080 #define USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_SHIFT   0
43081 #define USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_MASK)
43082 #define USBNC_OTG2_CTRL2_AUTURESUME_EN_MASK      0x4u
43083 #define USBNC_OTG2_CTRL2_AUTURESUME_EN_SHIFT     2
43084 #define USBNC_OTG2_CTRL2_LOWSPEED_EN_MASK        0x8u
43085 #define USBNC_OTG2_CTRL2_LOWSPEED_EN_SHIFT       3
43086 #define USBNC_OTG2_CTRL2_DIG_ID_SEL_MASK         0x100000u
43087 #define USBNC_OTG2_CTRL2_DIG_ID_SEL_SHIFT        20
43088 #define USBNC_OTG2_CTRL2_UTMI_CLK_VLD_MASK       0x80000000u
43089 #define USBNC_OTG2_CTRL2_UTMI_CLK_VLD_SHIFT      31
43090 /* OTG2_PHY_CFG1 Bit Fields */
43091 #define USBNC_OTG2_PHY_CFG1_COMMONONN_MASK       0x1u
43092 #define USBNC_OTG2_PHY_CFG1_COMMONONN_SHIFT      0
43093 #define USBNC_OTG2_PHY_CFG1_FSEL_MASK            0xEu
43094 #define USBNC_OTG2_PHY_CFG1_FSEL_SHIFT           1
43095 #define USBNC_OTG2_PHY_CFG1_FSEL(x)              (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_FSEL_SHIFT))&USBNC_OTG2_PHY_CFG1_FSEL_MASK)
43096 #define USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_MASK    0x70u
43097 #define USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_SHIFT   4
43098 #define USBNC_OTG2_PHY_CFG1_COMPDISTUNE0(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_MASK)
43099 #define USBNC_OTG2_PHY_CFG1_SQRXTUNE0_MASK       0x380u
43100 #define USBNC_OTG2_PHY_CFG1_SQRXTUNE0_SHIFT      7
43101 #define USBNC_OTG2_PHY_CFG1_SQRXTUNE0(x)         (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_SQRXTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_SQRXTUNE0_MASK)
43102 #define USBNC_OTG2_PHY_CFG1_OTGTUNE0_MASK        0x1C00u
43103 #define USBNC_OTG2_PHY_CFG1_OTGTUNE0_SHIFT       10
43104 #define USBNC_OTG2_PHY_CFG1_OTGTUNE0(x)          (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_OTGTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_OTGTUNE0_MASK)
43105 #define USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_MASK     0x6000u
43106 #define USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_SHIFT    13
43107 #define USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_MASK)
43108 #define USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_MASK     0xF0000u
43109 #define USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_SHIFT    16
43110 #define USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_MASK)
43111 #define USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_MASK     0xF00000u
43112 #define USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_SHIFT    20
43113 #define USBNC_OTG2_PHY_CFG1_TXVREFTUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_MASK)
43114 #define USBNC_OTG2_PHY_CFG1_TXRISETUNE0_MASK     0x3000000u
43115 #define USBNC_OTG2_PHY_CFG1_TXRISETUNE0_SHIFT    24
43116 #define USBNC_OTG2_PHY_CFG1_TXRISETUNE0(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXRISETUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXRISETUNE0_MASK)
43117 #define USBNC_OTG2_PHY_CFG1_TXRESTUNE0_MASK      0xC000000u
43118 #define USBNC_OTG2_PHY_CFG1_TXRESTUNE0_SHIFT     26
43119 #define USBNC_OTG2_PHY_CFG1_TXRESTUNE0(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXRESTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXRESTUNE0_MASK)
43120 #define USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_MASK 0x30000000u
43121 #define USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT 28
43122 #define USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0(x)  (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_MASK)
43123 #define USBNC_OTG2_PHY_CFG1_TXPREEMPPULSETUNE0_MASK 0x40000000u
43124 #define USBNC_OTG2_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT 30
43125 #define USBNC_OTG2_PHY_CFG1_CHRGDET_Megamix_MASK 0x80000000u
43126 #define USBNC_OTG2_PHY_CFG1_CHRGDET_Megamix_SHIFT 31
43127 /* OTG2_PHY_CFG2 Bit Fields */
43128 #define USBNC_OTG2_PHY_CFG2_CHRGSEL_MASK         0x1u
43129 #define USBNC_OTG2_PHY_CFG2_CHRGSEL_SHIFT        0
43130 #define USBNC_OTG2_PHY_CFG2_VDATDETENB0_MASK     0x2u
43131 #define USBNC_OTG2_PHY_CFG2_VDATDETENB0_SHIFT    1
43132 #define USBNC_OTG2_PHY_CFG2_VDATSRCENB0_MASK     0x4u
43133 #define USBNC_OTG2_PHY_CFG2_VDATSRCENB0_SHIFT    2
43134 #define USBNC_OTG2_PHY_CFG2_DCDENB_MASK          0x8u
43135 #define USBNC_OTG2_PHY_CFG2_DCDENB_SHIFT         3
43136 #define USBNC_OTG2_PHY_CFG2_ACAENB0_MASK         0x10u
43137 #define USBNC_OTG2_PHY_CFG2_ACAENB0_SHIFT        4
43138 #define USBNC_OTG2_PHY_CFG2_SLEEPM0_MASK         0x20u
43139 #define USBNC_OTG2_PHY_CFG2_SLEEPM0_SHIFT        5
43140 #define USBNC_OTG2_PHY_CFG2_LOOPBACKENB0_MASK    0x40u
43141 #define USBNC_OTG2_PHY_CFG2_LOOPBACKENB0_SHIFT   6
43142 #define USBNC_OTG2_PHY_CFG2_TXBITSTUFFEN0_MASK   0x100u
43143 #define USBNC_OTG2_PHY_CFG2_TXBITSTUFFEN0_SHIFT  8
43144 #define USBNC_OTG2_PHY_CFG2_TXBITSTUFFENH0_MASK  0x200u
43145 #define USBNC_OTG2_PHY_CFG2_TXBITSTUFFENH0_SHIFT 9
43146 #define USBNC_OTG2_PHY_CFG2_OTGDISABLE0_MASK     0x400u
43147 #define USBNC_OTG2_PHY_CFG2_OTGDISABLE0_SHIFT    10
43148 #define USBNC_OTG2_PHY_CFG2_ADPCHRG0_MASK        0x800u
43149 #define USBNC_OTG2_PHY_CFG2_ADPCHRG0_SHIFT       11
43150 #define USBNC_OTG2_PHY_CFG2_ADPDISCHRG0_MASK     0x1000u
43151 #define USBNC_OTG2_PHY_CFG2_ADPDISCHRG0_SHIFT    12
43152 #define USBNC_OTG2_PHY_CFG2_ADPPRBENB0_MASK      0x2000u
43153 #define USBNC_OTG2_PHY_CFG2_ADPPRBENB0_SHIFT     13
43154 #define USBNC_OTG2_PHY_CFG2_VBUSVLDEXTSEL0_MASK  0x4000u
43155 #define USBNC_OTG2_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT 14
43156 #define USBNC_OTG2_PHY_CFG2_VBUSVLDEXT_MASK      0x8000u
43157 #define USBNC_OTG2_PHY_CFG2_VBUSVLDEXT_SHIFT     15
43158 #define USBNC_OTG2_PHY_CFG2_DRVVBUS0_MASK        0x10000u
43159 #define USBNC_OTG2_PHY_CFG2_DRVVBUS0_SHIFT       16
43160 /* OTG2_PHY_STATUS Bit Fields */
43161 #define USBNC_OTG2_PHY_STATUS_LINE_STATE_MASK    0x3u
43162 #define USBNC_OTG2_PHY_STATUS_LINE_STATE_SHIFT   0
43163 #define USBNC_OTG2_PHY_STATUS_LINE_STATE(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_STATUS_LINE_STATE_SHIFT))&USBNC_OTG2_PHY_STATUS_LINE_STATE_MASK)
43164 #define USBNC_OTG2_PHY_STATUS_SESS_VLD_MASK      0x4u
43165 #define USBNC_OTG2_PHY_STATUS_SESS_VLD_SHIFT     2
43166 #define USBNC_OTG2_PHY_STATUS_VBUS_VLD_MASK      0x8u
43167 #define USBNC_OTG2_PHY_STATUS_VBUS_VLD_SHIFT     3
43168 #define USBNC_OTG2_PHY_STATUS_ID_DIG_MASK        0x10u
43169 #define USBNC_OTG2_PHY_STATUS_ID_DIG_SHIFT       4
43170 #define USBNC_OTG2_PHY_STATUS_HOST_DISCONNECT_MASK 0x20u
43171 #define USBNC_OTG2_PHY_STATUS_HOST_DISCONNECT_SHIFT 5
43172 #define USBNC_OTG2_PHY_STATUS_RIDC0_MASK         0x1000000u
43173 #define USBNC_OTG2_PHY_STATUS_RIDC0_SHIFT        24
43174 #define USBNC_OTG2_PHY_STATUS_RIDB0_MASK         0x2000000u
43175 #define USBNC_OTG2_PHY_STATUS_RIDB0_SHIFT        25
43176 #define USBNC_OTG2_PHY_STATUS_RIDA0_MASK         0x4000000u
43177 #define USBNC_OTG2_PHY_STATUS_RIDA0_SHIFT        26
43178 #define USBNC_OTG2_PHY_STATUS_RIDGND0_MASK       0x8000000u
43179 #define USBNC_OTG2_PHY_STATUS_RIDGND0_SHIFT      27
43180 #define USBNC_OTG2_PHY_STATUS_RIDFLOAT0_MASK     0x10000000u
43181 #define USBNC_OTG2_PHY_STATUS_RIDFLOAT0_SHIFT    28
43182 #define USBNC_OTG2_PHY_STATUS_CHRGDET_MASK       0x20000000u
43183 #define USBNC_OTG2_PHY_STATUS_CHRGDET_SHIFT      29
43184 #define USBNC_OTG2_PHY_STATUS_ADPPRB0_MASK       0x40000000u
43185 #define USBNC_OTG2_PHY_STATUS_ADPPRB0_SHIFT      30
43186 #define USBNC_OTG2_PHY_STATUS_ADPSNS0_MASK       0x80000000u
43187 #define USBNC_OTG2_PHY_STATUS_ADPSNS0_SHIFT      31
43188 /* HSIC_CTRL1 Bit Fields */
43189 #define USBNC_HSIC_CTRL1_OVER_CUR_DIS_MASK       0x80u
43190 #define USBNC_HSIC_CTRL1_OVER_CUR_DIS_SHIFT      7
43191 #define USBNC_HSIC_CTRL1_OVER_CUR_POL_MASK       0x100u
43192 #define USBNC_HSIC_CTRL1_OVER_CUR_POL_SHIFT      8
43193 #define USBNC_HSIC_CTRL1_PWR_POL_MASK            0x200u
43194 #define USBNC_HSIC_CTRL1_PWR_POL_SHIFT           9
43195 #define USBNC_HSIC_CTRL1_WIE_MASK                0x400u
43196 #define USBNC_HSIC_CTRL1_WIE_SHIFT               10
43197 #define USBNC_HSIC_CTRL1_WKUP_SW_EN_MASK         0x4000u
43198 #define USBNC_HSIC_CTRL1_WKUP_SW_EN_SHIFT        14
43199 #define USBNC_HSIC_CTRL1_WKUP_SW_MASK            0x8000u
43200 #define USBNC_HSIC_CTRL1_WKUP_SW_SHIFT           15
43201 #define USBNC_HSIC_CTRL1_WKUP_ID_EN_MASK         0x10000u
43202 #define USBNC_HSIC_CTRL1_WKUP_ID_EN_SHIFT        16
43203 #define USBNC_HSIC_CTRL1_WKUP_VBUS_EN_MASK       0x20000u
43204 #define USBNC_HSIC_CTRL1_WKUP_VBUS_EN_SHIFT      17
43205 #define USBNC_HSIC_CTRL1_WKUP_DPDM_EN_MASK       0x20000000u
43206 #define USBNC_HSIC_CTRL1_WKUP_DPDM_EN_SHIFT      29
43207 #define USBNC_HSIC_CTRL1_WIR_MASK                0x80000000u
43208 #define USBNC_HSIC_CTRL1_WIR_SHIFT               31
43209 /* HSIC_CTRL2 Bit Fields */
43210 #define USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_MASK    0x3u
43211 #define USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_SHIFT   0
43212 #define USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL(x)      (((uint32_t)(((uint32_t)(x))<<USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_MASK)
43213 #define USBNC_HSIC_CTRL2_AUTURESUME_EN_MASK      0x4u
43214 #define USBNC_HSIC_CTRL2_AUTURESUME_EN_SHIFT     2
43215 #define USBNC_HSIC_CTRL2_LOWSPEED_EN_MASK        0x8u
43216 #define USBNC_HSIC_CTRL2_LOWSPEED_EN_SHIFT       3
43217 #define USBNC_HSIC_CTRL2_DIG_ID_SEL_MASK         0x100000u
43218 #define USBNC_HSIC_CTRL2_DIG_ID_SEL_SHIFT        20
43219 #define USBNC_HSIC_CTRL2_UTMI_CLK_VLD_MASK       0x80000000u
43220 #define USBNC_HSIC_CTRL2_UTMI_CLK_VLD_SHIFT      31
43221 /* UH_HSICPHY_CFG1 Bit Fields */
43222 #define USBNC_UH_HSICPHY_CFG1_COMMONONN_MASK     0x1u
43223 #define USBNC_UH_HSICPHY_CFG1_COMMONONN_SHIFT    0
43224 #define USBNC_UH_HSICPHY_CFG1_LOOPBACKENB_MASK   0x2u
43225 #define USBNC_UH_HSICPHY_CFG1_LOOPBACKENB_SHIFT  1
43226 #define USBNC_UH_HSICPHY_CFG1_DPPULLDOWN_MASK    0x4u
43227 #define USBNC_UH_HSICPHY_CFG1_DPPULLDOWN_SHIFT   2
43228 #define USBNC_UH_HSICPHY_CFG1_DMPULLDOWN_MASK    0x8u
43229 #define USBNC_UH_HSICPHY_CFG1_DMPULLDOWN_SHIFT   3
43230 #define USBNC_UH_HSICPHY_CFG1_SLEEPM_MASK        0x10u
43231 #define USBNC_UH_HSICPHY_CFG1_SLEEPM_SHIFT       4
43232 #define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFEN_MASK  0x20u
43233 #define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFEN_SHIFT 5
43234 #define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFENH_MASK 0x40u
43235 #define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFENH_SHIFT 6
43236 #define USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_MASK     0x300u
43237 #define USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_SHIFT    8
43238 #define USBNC_UH_HSICPHY_CFG1_TXRPUTUNE(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_SHIFT))&USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_MASK)
43239 #define USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_MASK     0xC00u
43240 #define USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_SHIFT    10
43241 #define USBNC_UH_HSICPHY_CFG1_TXRPDTUNE(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_SHIFT))&USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_MASK)
43242 #define USBNC_UH_HSICPHY_CFG1_TXSRTUNE_MASK      0xF000u
43243 #define USBNC_UH_HSICPHY_CFG1_TXSRTUNE_SHIFT     12
43244 #define USBNC_UH_HSICPHY_CFG1_TXSRTUNE(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_TXSRTUNE_SHIFT))&USBNC_UH_HSICPHY_CFG1_TXSRTUNE_MASK)
43245 #define USBNC_UH_HSICPHY_CFG1_REFCLKDIV_MASK     0x7F0000u
43246 #define USBNC_UH_HSICPHY_CFG1_REFCLKDIV_SHIFT    16
43247 #define USBNC_UH_HSICPHY_CFG1_REFCLKDIV(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_REFCLKDIV_SHIFT))&USBNC_UH_HSICPHY_CFG1_REFCLKDIV_MASK)
43248 #define USBNC_UH_HSICPHY_CFG1_REFCLKSEL_MASK     0x3000000u
43249 #define USBNC_UH_HSICPHY_CFG1_REFCLKSEL_SHIFT    24
43250 #define USBNC_UH_HSICPHY_CFG1_REFCLKSEL(x)       (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_REFCLKSEL_SHIFT))&USBNC_UH_HSICPHY_CFG1_REFCLKSEL_MASK)
43251 
43252 /*!
43253  * @}
43254  */ /* end of group USBNC_Register_Masks */
43255 
43256 /* USBNC - Peripheral instance base addresses */
43257 /** Peripheral USBNC base address */
43258 #define USBNC_BASE                               (0x30B10000u)
43259 /** Peripheral USBNC base pointer */
43260 #define USBNC                                    ((USBNC_Type *)USBNC_BASE)
43261 #define USBNC_BASE_PTR                           (USBNC)
43262 /** Array initializer of USBNC peripheral base addresses */
43263 #define USBNC_BASE_ADDRS                         { USBNC_BASE }
43264 /** Array initializer of USBNC peripheral base pointers */
43265 #define USBNC_BASE_PTRS                          { USBNC }
43266 /* ----------------------------------------------------------------------------
43267    -- USBNC - Register accessor macros
43268    ---------------------------------------------------------------------------- */
43269 
43270 /*!
43271  * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros
43272  * @{
43273  */
43274 
43275 
43276 /* USBNC - Register instance definitions */
43277 /* USBNC */
43278 #define USBNC_OTG1_CTRL1                         USBNC_OTG1_CTRL1_REG(USBNC_BASE_PTR)
43279 #define USBNC_OTG1_CTRL2                         USBNC_OTG1_CTRL2_REG(USBNC_BASE_PTR)
43280 #define USBNC_OTG1_PHY_CFG1                      USBNC_OTG1_PHY_CFG1_REG(USBNC_BASE_PTR)
43281 #define USBNC_OTG1_PHY_CFG2                      USBNC_OTG1_PHY_CFG2_REG(USBNC_BASE_PTR)
43282 #define USBNC_OTG1_PHY_STATUS                    USBNC_OTG1_PHY_STATUS_REG(USBNC_BASE_PTR)
43283 #define USBNC_ADP_CFG1                           USBNC_ADP_CFG1_REG(USBNC_BASE_PTR)
43284 #define USBNC_ADP_CFG2                           USBNC_ADP_CFG2_REG(USBNC_BASE_PTR)
43285 #define USBNC_ADP_STATUS                         USBNC_ADP_STATUS_REG(USBNC_BASE_PTR)
43286 #define USBNC_OTG2_CTRL1                         USBNC_OTG2_CTRL1_REG(USBNC_BASE_PTR)
43287 #define USBNC_OTG2_CTRL2                         USBNC_OTG2_CTRL2_REG(USBNC_BASE_PTR)
43288 #define USBNC_OTG2_PHY_CFG1                      USBNC_OTG2_PHY_CFG1_REG(USBNC_BASE_PTR)
43289 #define USBNC_OTG2_PHY_CFG2                      USBNC_OTG2_PHY_CFG2_REG(USBNC_BASE_PTR)
43290 #define USBNC_OTG2_PHY_STATUS                    USBNC_OTG2_PHY_STATUS_REG(USBNC_BASE_PTR)
43291 #define USBNC_HSIC_CTRL1                         USBNC_HSIC_CTRL1_REG(USBNC_BASE_PTR)
43292 #define USBNC_HSIC_CTRL2                         USBNC_HSIC_CTRL2_REG(USBNC_BASE_PTR)
43293 #define USBNC_UH_HSICPHY_CFG1                    USBNC_UH_HSICPHY_CFG1_REG(USBNC_BASE_PTR)
43294 /*!
43295  * @}
43296  */ /* end of group USBNC_Register_Accessor_Macros */
43297 
43298 
43299 /*!
43300  * @}
43301  */ /* end of group USBNC_Peripheral */
43302 
43303 /* ----------------------------------------------------------------------------
43304    -- WDOG Peripheral Access Layer
43305    ---------------------------------------------------------------------------- */
43306 
43307 /*!
43308  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
43309  * @{
43310  */
43311 
43312 /** WDOG - Register Layout Typedef */
43313 typedef struct {
43314   __IO  uint16_t WCR;                                    /**< Watchdog Control Register, offset: 0x0 */
43315   __IO  uint16_t WSR;                                    /**< Watchdog Service Register, offset: 0x2 */
43316   __I   uint16_t WRSR;                                   /**< Watchdog Reset Status Register, offset: 0x4 */
43317   __IO  uint16_t WICR;                                   /**< Watchdog Interrupt Control Register, offset: 0x6 */
43318   __IO  uint16_t WMCR;                                   /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
43319 } WDOG_Type, *WDOG_MemMapPtr;
43320 /* ----------------------------------------------------------------------------
43321    -- WDOG - Register accessor macros
43322    ---------------------------------------------------------------------------- */
43323 
43324 /*!
43325  * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
43326  * @{
43327  */
43328 
43329 
43330 /* WDOG - Register accessors */
43331 #define WDOG_WCR_REG(base)                       ((base)->WCR)
43332 #define WDOG_WSR_REG(base)                       ((base)->WSR)
43333 #define WDOG_WRSR_REG(base)                      ((base)->WRSR)
43334 #define WDOG_WICR_REG(base)                      ((base)->WICR)
43335 #define WDOG_WMCR_REG(base)                      ((base)->WMCR)
43336 
43337 /*!
43338  * @}
43339  */ /* end of group WDOG_Register_Accessor_Macros */
43340 /* ----------------------------------------------------------------------------
43341    -- WDOG Register Masks
43342    ---------------------------------------------------------------------------- */
43343 
43344 /*!
43345  * @addtogroup WDOG_Register_Masks WDOG Register Masks
43346  * @{
43347  */
43348 
43349 /* WCR Bit Fields */
43350 #define WDOG_WCR_WDZST_MASK                      0x1u
43351 #define WDOG_WCR_WDZST_SHIFT                     0
43352 #define WDOG_WCR_WDBG_MASK                       0x2u
43353 #define WDOG_WCR_WDBG_SHIFT                      1
43354 #define WDOG_WCR_WDE_MASK                        0x4u
43355 #define WDOG_WCR_WDE_SHIFT                       2
43356 #define WDOG_WCR_WDT_MASK                        0x8u
43357 #define WDOG_WCR_WDT_SHIFT                       3
43358 #define WDOG_WCR_SRS_MASK                        0x10u
43359 #define WDOG_WCR_SRS_SHIFT                       4
43360 #define WDOG_WCR_WDA_MASK                        0x20u
43361 #define WDOG_WCR_WDA_SHIFT                       5
43362 #define WDOG_WCR_SRE_MASK                        0x40u
43363 #define WDOG_WCR_SRE_SHIFT                       6
43364 #define WDOG_WCR_WDW_MASK                        0x80u
43365 #define WDOG_WCR_WDW_SHIFT                       7
43366 #define WDOG_WCR_WT_MASK                         0xFF00u
43367 #define WDOG_WCR_WT_SHIFT                        8
43368 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x))<<WDOG_WCR_WT_SHIFT))&WDOG_WCR_WT_MASK)
43369 /* WSR Bit Fields */
43370 #define WDOG_WSR_WSR_MASK                        0xFFFFu
43371 #define WDOG_WSR_WSR_SHIFT                       0
43372 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_WSR_WSR_SHIFT))&WDOG_WSR_WSR_MASK)
43373 /* WRSR Bit Fields */
43374 #define WDOG_WRSR_SFTW_MASK                      0x1u
43375 #define WDOG_WRSR_SFTW_SHIFT                     0
43376 #define WDOG_WRSR_TOUT_MASK                      0x2u
43377 #define WDOG_WRSR_TOUT_SHIFT                     1
43378 #define WDOG_WRSR_POR_MASK                       0x10u
43379 #define WDOG_WRSR_POR_SHIFT                      4
43380 /* WICR Bit Fields */
43381 #define WDOG_WICR_WICT_MASK                      0xFFu
43382 #define WDOG_WICR_WICT_SHIFT                     0
43383 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x))<<WDOG_WICR_WICT_SHIFT))&WDOG_WICR_WICT_MASK)
43384 #define WDOG_WICR_WTIS_MASK                      0x4000u
43385 #define WDOG_WICR_WTIS_SHIFT                     14
43386 #define WDOG_WICR_WIE_MASK                       0x8000u
43387 #define WDOG_WICR_WIE_SHIFT                      15
43388 /* WMCR Bit Fields */
43389 #define WDOG_WMCR_PDE_MASK                       0x1u
43390 #define WDOG_WMCR_PDE_SHIFT                      0
43391 
43392 /*!
43393  * @}
43394  */ /* end of group WDOG_Register_Masks */
43395 
43396 /* WDOG - Peripheral instance base addresses */
43397 /** Peripheral WDOG1 base address */
43398 #define WDOG1_BASE                               (0x30280000u)
43399 /** Peripheral WDOG1 base pointer */
43400 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
43401 #define WDOG1_BASE_PTR                           (WDOG1)
43402 /** Peripheral WDOG2 base address */
43403 #define WDOG2_BASE                               (0x30290000u)
43404 /** Peripheral WDOG2 base pointer */
43405 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
43406 #define WDOG2_BASE_PTR                           (WDOG2)
43407 /** Peripheral WDOG3 base address */
43408 #define WDOG3_BASE                               (0x302A0000u)
43409 /** Peripheral WDOG3 base pointer */
43410 #define WDOG3                                    ((WDOG_Type *)WDOG3_BASE)
43411 #define WDOG3_BASE_PTR                           (WDOG3)
43412 /** Peripheral WDOG4 base address */
43413 #define WDOG4_BASE                               (0x302B0000u)
43414 /** Peripheral WDOG4 base pointer */
43415 #define WDOG4                                    ((WDOG_Type *)WDOG4_BASE)
43416 #define WDOG4_BASE_PTR                           (WDOG4)
43417 /** Array initializer of WDOG peripheral base addresses */
43418 #define WDOG_BASE_ADDRS                          { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE }
43419 /** Array initializer of WDOG peripheral base pointers */
43420 #define WDOG_BASE_PTRS                           { WDOG1, WDOG2, WDOG3, WDOG4 }
43421 /** Interrupt vectors for the WDOG peripheral type */
43422 #define WDOG_IRQS                                { WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn, WDOG4_IRQn }
43423 /* ----------------------------------------------------------------------------
43424    -- WDOG - Register accessor macros
43425    ---------------------------------------------------------------------------- */
43426 
43427 /*!
43428  * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
43429  * @{
43430  */
43431 
43432 
43433 /* WDOG - Register instance definitions */
43434 /* WDOG1 */
43435 #define WDOG1_WCR                                WDOG_WCR_REG(WDOG1_BASE_PTR)
43436 #define WDOG1_WSR                                WDOG_WSR_REG(WDOG1_BASE_PTR)
43437 #define WDOG1_WRSR                               WDOG_WRSR_REG(WDOG1_BASE_PTR)
43438 #define WDOG1_WICR                               WDOG_WICR_REG(WDOG1_BASE_PTR)
43439 #define WDOG1_WMCR                               WDOG_WMCR_REG(WDOG1_BASE_PTR)
43440 /* WDOG2 */
43441 #define WDOG2_WCR                                WDOG_WCR_REG(WDOG2_BASE_PTR)
43442 #define WDOG2_WSR                                WDOG_WSR_REG(WDOG2_BASE_PTR)
43443 #define WDOG2_WRSR                               WDOG_WRSR_REG(WDOG2_BASE_PTR)
43444 #define WDOG2_WICR                               WDOG_WICR_REG(WDOG2_BASE_PTR)
43445 #define WDOG2_WMCR                               WDOG_WMCR_REG(WDOG2_BASE_PTR)
43446 /* WDOG3 */
43447 #define WDOG3_WCR                                WDOG_WCR_REG(WDOG3_BASE_PTR)
43448 #define WDOG3_WSR                                WDOG_WSR_REG(WDOG3_BASE_PTR)
43449 #define WDOG3_WRSR                               WDOG_WRSR_REG(WDOG3_BASE_PTR)
43450 #define WDOG3_WICR                               WDOG_WICR_REG(WDOG3_BASE_PTR)
43451 #define WDOG3_WMCR                               WDOG_WMCR_REG(WDOG3_BASE_PTR)
43452 /* WDOG4 */
43453 #define WDOG4_WCR                                WDOG_WCR_REG(WDOG4_BASE_PTR)
43454 #define WDOG4_WSR                                WDOG_WSR_REG(WDOG4_BASE_PTR)
43455 #define WDOG4_WRSR                               WDOG_WRSR_REG(WDOG4_BASE_PTR)
43456 #define WDOG4_WICR                               WDOG_WICR_REG(WDOG4_BASE_PTR)
43457 #define WDOG4_WMCR                               WDOG_WMCR_REG(WDOG4_BASE_PTR)
43458 /*!
43459  * @}
43460  */ /* end of group WDOG_Register_Accessor_Macros */
43461 
43462 
43463 /*!
43464  * @}
43465  */ /* end of group WDOG_Peripheral */
43466 
43467 /* ----------------------------------------------------------------------------
43468    -- XTALOSC Peripheral Access Layer
43469    ---------------------------------------------------------------------------- */
43470 
43471 /*!
43472  * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer
43473  * @{
43474  */
43475 
43476 /** XTALOSC - Register Layout Typedef */
43477 typedef struct {
43478   __IO  uint32_t CTRL_24M;                               /**< Anadig 24M Oscillator Control Register, offset: 0x0 */
43479   __IO  uint32_t CTRL_24M_SET;                           /**< Anadig 24M Oscillator Control Register, offset: 0x4 */
43480   __IO  uint32_t CTRL_24M_CLR;                           /**< Anadig 24M Oscillator Control Register, offset: 0x8 */
43481   __IO  uint32_t CTRL_24M_TOG;                           /**< Anadig 24M Oscillator Control Register, offset: 0xC */
43482   __IO  uint32_t RCOSC_CONFIG0;                          /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x10 */
43483   __IO  uint32_t RCOSC_CONFIG0_SET;                      /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x14 */
43484   __IO  uint32_t RCOSC_CONFIG0_CLR;                      /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x18 */
43485   __IO  uint32_t RCOSC_CONFIG0_TOG;                      /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x1C */
43486   __IO  uint32_t RCOSC_CONFIG1;                          /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x20 */
43487   __IO  uint32_t RCOSC_CONFIG1_SET;                      /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x24 */
43488   __IO  uint32_t RCOSC_CONFIG1_CLR;                      /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x28 */
43489   __IO  uint32_t RCOSC_CONFIG1_TOG;                      /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x2C */
43490   __IO  uint32_t RCOSC_CONFIG2;                          /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x30 */
43491   __IO  uint32_t RCOSC_CONFIG2_SET;                      /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x34 */
43492   __IO  uint32_t RCOSC_CONFIG2_CLR;                      /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x38 */
43493   __IO  uint32_t RCOSC_CONFIG2_TOG;                      /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x3C */
43494   uint8_t RESERVED_0[16];
43495   __IO  uint32_t OSC_32K;                                /**< 32K Oscillator Control Register, offset: 0x50 */
43496   __IO  uint32_t OSC_32K_SET;                            /**< 32K Oscillator Control Register, offset: 0x54 */
43497   __IO  uint32_t OSC_32K_CLR;                            /**< 32K Oscillator Control Register, offset: 0x58 */
43498   __IO  uint32_t OSC_32K_TOG;                            /**< 32K Oscillator Control Register, offset: 0x5C */
43499 } XTALOSC_Type, *XTALOSC_MemMapPtr;
43500 /* ----------------------------------------------------------------------------
43501    -- XTALOSC - Register accessor macros
43502    ---------------------------------------------------------------------------- */
43503 
43504 /*!
43505  * @addtogroup XTALOSC_Register_Accessor_Macros XTALOSC - Register accessor macros
43506  * @{
43507  */
43508 
43509 
43510 /* XTALOSC - Register accessors */
43511 #define XTALOSC_CTRL_24M_REG(base)               ((base)->CTRL_24M)
43512 #define XTALOSC_CTRL_24M_SET_REG(base)           ((base)->CTRL_24M_SET)
43513 #define XTALOSC_CTRL_24M_CLR_REG(base)           ((base)->CTRL_24M_CLR)
43514 #define XTALOSC_CTRL_24M_TOG_REG(base)           ((base)->CTRL_24M_TOG)
43515 #define XTALOSC_RCOSC_CONFIG0_REG(base)          ((base)->RCOSC_CONFIG0)
43516 #define XTALOSC_RCOSC_CONFIG0_SET_REG(base)      ((base)->RCOSC_CONFIG0_SET)
43517 #define XTALOSC_RCOSC_CONFIG0_CLR_REG(base)      ((base)->RCOSC_CONFIG0_CLR)
43518 #define XTALOSC_RCOSC_CONFIG0_TOG_REG(base)      ((base)->RCOSC_CONFIG0_TOG)
43519 #define XTALOSC_RCOSC_CONFIG1_REG(base)          ((base)->RCOSC_CONFIG1)
43520 #define XTALOSC_RCOSC_CONFIG1_SET_REG(base)      ((base)->RCOSC_CONFIG1_SET)
43521 #define XTALOSC_RCOSC_CONFIG1_CLR_REG(base)      ((base)->RCOSC_CONFIG1_CLR)
43522 #define XTALOSC_RCOSC_CONFIG1_TOG_REG(base)      ((base)->RCOSC_CONFIG1_TOG)
43523 #define XTALOSC_RCOSC_CONFIG2_REG(base)          ((base)->RCOSC_CONFIG2)
43524 #define XTALOSC_RCOSC_CONFIG2_SET_REG(base)      ((base)->RCOSC_CONFIG2_SET)
43525 #define XTALOSC_RCOSC_CONFIG2_CLR_REG(base)      ((base)->RCOSC_CONFIG2_CLR)
43526 #define XTALOSC_RCOSC_CONFIG2_TOG_REG(base)      ((base)->RCOSC_CONFIG2_TOG)
43527 #define XTALOSC_OSC_32K_REG(base)                ((base)->OSC_32K)
43528 #define XTALOSC_OSC_32K_SET_REG(base)            ((base)->OSC_32K_SET)
43529 #define XTALOSC_OSC_32K_CLR_REG(base)            ((base)->OSC_32K_CLR)
43530 #define XTALOSC_OSC_32K_TOG_REG(base)            ((base)->OSC_32K_TOG)
43531 
43532 /*!
43533  * @}
43534  */ /* end of group XTALOSC_Register_Accessor_Macros */
43535 /* ----------------------------------------------------------------------------
43536    -- XTALOSC Register Masks
43537    ---------------------------------------------------------------------------- */
43538 
43539 /*!
43540  * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks
43541  * @{
43542  */
43543 
43544 /* CTRL_24M Bit Fields */
43545 #define XTALOSC_CTRL_24M_XTAL_24M_PWD_MASK       0x1u
43546 #define XTALOSC_CTRL_24M_XTAL_24M_PWD_SHIFT      0
43547 #define XTALOSC_CTRL_24M_XTAL_24M_EN_MASK        0x2u
43548 #define XTALOSC_CTRL_24M_XTAL_24M_EN_SHIFT       1
43549 #define XTALOSC_CTRL_24M_OSC_XTALOK_MASK         0x4u
43550 #define XTALOSC_CTRL_24M_OSC_XTALOK_SHIFT        2
43551 #define XTALOSC_CTRL_24M_OSC_XTALOK_EN_MASK      0x8u
43552 #define XTALOSC_CTRL_24M_OSC_XTALOK_EN_SHIFT     3
43553 #define XTALOSC_CTRL_24M_CLKGATE_CTRL_MASK       0x10u
43554 #define XTALOSC_CTRL_24M_CLKGATE_CTRL_SHIFT      4
43555 #define XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK      0xE0u
43556 #define XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT     5
43557 #define XTALOSC_CTRL_24M_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK)
43558 #define XTALOSC_CTRL_24M_RCOSC_CG_OVERRIDE_MASK  0x100u
43559 #define XTALOSC_CTRL_24M_RCOSC_CG_OVERRIDE_SHIFT 8
43560 #define XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_MASK 0x600u
43561 #define XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_SHIFT 9
43562 #define XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_MASK)
43563 #define XTALOSC_CTRL_24M_XTALOSC_PWRUP_STAT_MASK 0x800u
43564 #define XTALOSC_CTRL_24M_XTALOSC_PWRUP_STAT_SHIFT 11
43565 #define XTALOSC_CTRL_24M_OSC_SEL_MASK            0x1000u
43566 #define XTALOSC_CTRL_24M_OSC_SEL_SHIFT           12
43567 #define XTALOSC_CTRL_24M_RC_OSC_EN_MASK          0x2000u
43568 #define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT         13
43569 #define XTALOSC_CTRL_24M_XTAL_MISC_MASK          0x7FFF8000u
43570 #define XTALOSC_CTRL_24M_XTAL_MISC_SHIFT         15
43571 #define XTALOSC_CTRL_24M_XTAL_MISC(x)            (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_XTAL_MISC_MASK)
43572 /* CTRL_24M_SET Bit Fields */
43573 #define XTALOSC_CTRL_24M_SET_XTAL_24M_PWD_MASK   0x1u
43574 #define XTALOSC_CTRL_24M_SET_XTAL_24M_PWD_SHIFT  0
43575 #define XTALOSC_CTRL_24M_SET_XTAL_24M_EN_MASK    0x2u
43576 #define XTALOSC_CTRL_24M_SET_XTAL_24M_EN_SHIFT   1
43577 #define XTALOSC_CTRL_24M_SET_OSC_XTALOK_MASK     0x4u
43578 #define XTALOSC_CTRL_24M_SET_OSC_XTALOK_SHIFT    2
43579 #define XTALOSC_CTRL_24M_SET_OSC_XTALOK_EN_MASK  0x8u
43580 #define XTALOSC_CTRL_24M_SET_OSC_XTALOK_EN_SHIFT 3
43581 #define XTALOSC_CTRL_24M_SET_CLKGATE_CTRL_MASK   0x10u
43582 #define XTALOSC_CTRL_24M_SET_CLKGATE_CTRL_SHIFT  4
43583 #define XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_MASK  0xE0u
43584 #define XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_SHIFT 5
43585 #define XTALOSC_CTRL_24M_SET_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_MASK)
43586 #define XTALOSC_CTRL_24M_SET_RCOSC_CG_OVERRIDE_MASK 0x100u
43587 #define XTALOSC_CTRL_24M_SET_RCOSC_CG_OVERRIDE_SHIFT 8
43588 #define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_MASK 0x600u
43589 #define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_SHIFT 9
43590 #define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_MASK)
43591 #define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_STAT_MASK 0x800u
43592 #define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_STAT_SHIFT 11
43593 #define XTALOSC_CTRL_24M_SET_OSC_SEL_MASK        0x1000u
43594 #define XTALOSC_CTRL_24M_SET_OSC_SEL_SHIFT       12
43595 #define XTALOSC_CTRL_24M_SET_RC_OSC_EN_MASK      0x2000u
43596 #define XTALOSC_CTRL_24M_SET_RC_OSC_EN_SHIFT     13
43597 #define XTALOSC_CTRL_24M_SET_XTAL_MISC_MASK      0x7FFF8000u
43598 #define XTALOSC_CTRL_24M_SET_XTAL_MISC_SHIFT     15
43599 #define XTALOSC_CTRL_24M_SET_XTAL_MISC(x)        (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_SET_XTAL_MISC_MASK)
43600 /* CTRL_24M_CLR Bit Fields */
43601 #define XTALOSC_CTRL_24M_CLR_XTAL_24M_PWD_MASK   0x1u
43602 #define XTALOSC_CTRL_24M_CLR_XTAL_24M_PWD_SHIFT  0
43603 #define XTALOSC_CTRL_24M_CLR_XTAL_24M_EN_MASK    0x2u
43604 #define XTALOSC_CTRL_24M_CLR_XTAL_24M_EN_SHIFT   1
43605 #define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_MASK     0x4u
43606 #define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_SHIFT    2
43607 #define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_EN_MASK  0x8u
43608 #define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_EN_SHIFT 3
43609 #define XTALOSC_CTRL_24M_CLR_CLKGATE_CTRL_MASK   0x10u
43610 #define XTALOSC_CTRL_24M_CLR_CLKGATE_CTRL_SHIFT  4
43611 #define XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_MASK  0xE0u
43612 #define XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_SHIFT 5
43613 #define XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_MASK)
43614 #define XTALOSC_CTRL_24M_CLR_RCOSC_CG_OVERRIDE_MASK 0x100u
43615 #define XTALOSC_CTRL_24M_CLR_RCOSC_CG_OVERRIDE_SHIFT 8
43616 #define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_MASK 0x600u
43617 #define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_SHIFT 9
43618 #define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_MASK)
43619 #define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_STAT_MASK 0x800u
43620 #define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_STAT_SHIFT 11
43621 #define XTALOSC_CTRL_24M_CLR_OSC_SEL_MASK        0x1000u
43622 #define XTALOSC_CTRL_24M_CLR_OSC_SEL_SHIFT       12
43623 #define XTALOSC_CTRL_24M_CLR_RC_OSC_EN_MASK      0x2000u
43624 #define XTALOSC_CTRL_24M_CLR_RC_OSC_EN_SHIFT     13
43625 #define XTALOSC_CTRL_24M_CLR_XTAL_MISC_MASK      0x7FFF8000u
43626 #define XTALOSC_CTRL_24M_CLR_XTAL_MISC_SHIFT     15
43627 #define XTALOSC_CTRL_24M_CLR_XTAL_MISC(x)        (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_CLR_XTAL_MISC_MASK)
43628 /* CTRL_24M_TOG Bit Fields */
43629 #define XTALOSC_CTRL_24M_TOG_XTAL_24M_PWD_MASK   0x1u
43630 #define XTALOSC_CTRL_24M_TOG_XTAL_24M_PWD_SHIFT  0
43631 #define XTALOSC_CTRL_24M_TOG_XTAL_24M_EN_MASK    0x2u
43632 #define XTALOSC_CTRL_24M_TOG_XTAL_24M_EN_SHIFT   1
43633 #define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_MASK     0x4u
43634 #define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_SHIFT    2
43635 #define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_EN_MASK  0x8u
43636 #define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_EN_SHIFT 3
43637 #define XTALOSC_CTRL_24M_TOG_CLKGATE_CTRL_MASK   0x10u
43638 #define XTALOSC_CTRL_24M_TOG_CLKGATE_CTRL_SHIFT  4
43639 #define XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_MASK  0xE0u
43640 #define XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_SHIFT 5
43641 #define XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_MASK)
43642 #define XTALOSC_CTRL_24M_TOG_RCOSC_CG_OVERRIDE_MASK 0x100u
43643 #define XTALOSC_CTRL_24M_TOG_RCOSC_CG_OVERRIDE_SHIFT 8
43644 #define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_MASK 0x600u
43645 #define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_SHIFT 9
43646 #define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_MASK)
43647 #define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_STAT_MASK 0x800u
43648 #define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_STAT_SHIFT 11
43649 #define XTALOSC_CTRL_24M_TOG_OSC_SEL_MASK        0x1000u
43650 #define XTALOSC_CTRL_24M_TOG_OSC_SEL_SHIFT       12
43651 #define XTALOSC_CTRL_24M_TOG_RC_OSC_EN_MASK      0x2000u
43652 #define XTALOSC_CTRL_24M_TOG_RC_OSC_EN_SHIFT     13
43653 #define XTALOSC_CTRL_24M_TOG_XTAL_MISC_MASK      0x7FFF8000u
43654 #define XTALOSC_CTRL_24M_TOG_XTAL_MISC_SHIFT     15
43655 #define XTALOSC_CTRL_24M_TOG_XTAL_MISC(x)        (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_TOG_XTAL_MISC_MASK)
43656 /* RCOSC_CONFIG0 Bit Fields */
43657 #define XTALOSC_RCOSC_CONFIG0_TUNE_START_MASK    0x1u
43658 #define XTALOSC_RCOSC_CONFIG0_TUNE_START_SHIFT   0
43659 #define XTALOSC_RCOSC_CONFIG0_TUNE_ENABLE_MASK   0x2u
43660 #define XTALOSC_RCOSC_CONFIG0_TUNE_ENABLE_SHIFT  1
43661 #define XTALOSC_RCOSC_CONFIG0_TUNE_BYPASS_MASK   0x4u
43662 #define XTALOSC_RCOSC_CONFIG0_TUNE_BYPASS_SHIFT  2
43663 #define XTALOSC_RCOSC_CONFIG0_TUNE_INVERT_MASK   0x8u
43664 #define XTALOSC_RCOSC_CONFIG0_TUNE_INVERT_SHIFT  3
43665 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_MASK   0xFF0u
43666 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_SHIFT  4
43667 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG(x)     (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_MASK)
43668 #define XTALOSC_RCOSC_CONFIG0_HYST_PLUS_MASK     0xF000u
43669 #define XTALOSC_RCOSC_CONFIG0_HYST_PLUS_SHIFT    12
43670 #define XTALOSC_RCOSC_CONFIG0_HYST_PLUS(x)       (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_HYST_PLUS_MASK)
43671 #define XTALOSC_RCOSC_CONFIG0_HYST_MINUS_MASK    0xF0000u
43672 #define XTALOSC_RCOSC_CONFIG0_HYST_MINUS_SHIFT   16
43673 #define XTALOSC_RCOSC_CONFIG0_HYST_MINUS(x)      (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_HYST_MINUS_MASK)
43674 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_MASK 0xFF000000u
43675 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24
43676 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
43677 /* RCOSC_CONFIG0_SET Bit Fields */
43678 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_START_MASK 0x1u
43679 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_START_SHIFT 0
43680 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_ENABLE_MASK 0x2u
43681 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_ENABLE_SHIFT 1
43682 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_BYPASS_MASK 0x4u
43683 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_BYPASS_SHIFT 2
43684 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_INVERT_MASK 0x8u
43685 #define XTALOSC_RCOSC_CONFIG0_SET_TUNE_INVERT_SHIFT 3
43686 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_MASK 0xFF0u
43687 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_SHIFT 4
43688 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_MASK)
43689 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_MASK 0xF000u
43690 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_SHIFT 12
43691 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS(x)   (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_MASK)
43692 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_MASK 0xF0000u
43693 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_SHIFT 16
43694 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_MASK)
43695 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK 0xFF000000u
43696 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT 24
43697 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
43698 /* RCOSC_CONFIG0_CLR Bit Fields */
43699 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_START_MASK 0x1u
43700 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_START_SHIFT 0
43701 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_ENABLE_MASK 0x2u
43702 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_ENABLE_SHIFT 1
43703 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_BYPASS_MASK 0x4u
43704 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_BYPASS_SHIFT 2
43705 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_INVERT_MASK 0x8u
43706 #define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_INVERT_SHIFT 3
43707 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_MASK 0xFF0u
43708 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT 4
43709 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
43710 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_MASK 0xF000u
43711 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_SHIFT 12
43712 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS(x)   (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_MASK)
43713 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_MASK 0xF0000u
43714 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_SHIFT 16
43715 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_MASK)
43716 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK 0xFF000000u
43717 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT 24
43718 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
43719 /* RCOSC_CONFIG0_TOG Bit Fields */
43720 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_START_MASK 0x1u
43721 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_START_SHIFT 0
43722 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_ENABLE_MASK 0x2u
43723 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_ENABLE_SHIFT 1
43724 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_BYPASS_MASK 0x4u
43725 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_BYPASS_SHIFT 2
43726 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_INVERT_MASK 0x8u
43727 #define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_INVERT_SHIFT 3
43728 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_MASK 0xFF0u
43729 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT 4
43730 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
43731 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_MASK 0xF000u
43732 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_SHIFT 12
43733 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS(x)   (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_MASK)
43734 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_MASK 0xF0000u
43735 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_SHIFT 16
43736 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_MASK)
43737 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK 0xFF000000u
43738 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT 24
43739 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
43740 /* RCOSC_CONFIG1 Bit Fields */
43741 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_MASK  0xFFFu
43742 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_SHIFT 0
43743 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_MASK)
43744 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_MASK  0xFFF00000u
43745 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_SHIFT 20
43746 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_MASK)
43747 /* RCOSC_CONFIG1_SET Bit Fields */
43748 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_MASK 0xFFFu
43749 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT 0
43750 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
43751 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_MASK 0xFFF00000u
43752 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT 20
43753 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
43754 /* RCOSC_CONFIG1_CLR Bit Fields */
43755 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_MASK 0xFFFu
43756 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT 0
43757 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
43758 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_MASK 0xFFF00000u
43759 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT 20
43760 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
43761 /* RCOSC_CONFIG1_TOG Bit Fields */
43762 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_MASK 0xFFFu
43763 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT 0
43764 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
43765 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_MASK 0xFFF00000u
43766 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT 20
43767 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
43768 /* RCOSC_CONFIG2 Bit Fields */
43769 #define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_MASK  0xFFFu
43770 #define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_SHIFT 0
43771 #define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_MASK)
43772 #define XTALOSC_RCOSC_CONFIG2_ENABLE_1M_MASK     0x10000u
43773 #define XTALOSC_RCOSC_CONFIG2_ENABLE_1M_SHIFT    16
43774 #define XTALOSC_RCOSC_CONFIG2_MUX_1M_MASK        0x20000u
43775 #define XTALOSC_RCOSC_CONFIG2_MUX_1M_SHIFT       17
43776 #define XTALOSC_RCOSC_CONFIG2_CLK_1M_ERR_FL_MASK 0x80000000u
43777 #define XTALOSC_RCOSC_CONFIG2_CLK_1M_ERR_FL_SHIFT 31
43778 /* RCOSC_CONFIG2_SET Bit Fields */
43779 #define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_MASK 0xFFFu
43780 #define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT 0
43781 #define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
43782 #define XTALOSC_RCOSC_CONFIG2_SET_ENABLE_1M_MASK 0x10000u
43783 #define XTALOSC_RCOSC_CONFIG2_SET_ENABLE_1M_SHIFT 16
43784 #define XTALOSC_RCOSC_CONFIG2_SET_MUX_1M_MASK    0x20000u
43785 #define XTALOSC_RCOSC_CONFIG2_SET_MUX_1M_SHIFT   17
43786 #define XTALOSC_RCOSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK 0x80000000u
43787 #define XTALOSC_RCOSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT 31
43788 /* RCOSC_CONFIG2_CLR Bit Fields */
43789 #define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_MASK 0xFFFu
43790 #define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT 0
43791 #define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
43792 #define XTALOSC_RCOSC_CONFIG2_CLR_ENABLE_1M_MASK 0x10000u
43793 #define XTALOSC_RCOSC_CONFIG2_CLR_ENABLE_1M_SHIFT 16
43794 #define XTALOSC_RCOSC_CONFIG2_CLR_MUX_1M_MASK    0x20000u
43795 #define XTALOSC_RCOSC_CONFIG2_CLR_MUX_1M_SHIFT   17
43796 #define XTALOSC_RCOSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK 0x80000000u
43797 #define XTALOSC_RCOSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT 31
43798 /* RCOSC_CONFIG2_TOG Bit Fields */
43799 #define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_MASK 0xFFFu
43800 #define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT 0
43801 #define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
43802 #define XTALOSC_RCOSC_CONFIG2_TOG_ENABLE_1M_MASK 0x10000u
43803 #define XTALOSC_RCOSC_CONFIG2_TOG_ENABLE_1M_SHIFT 16
43804 #define XTALOSC_RCOSC_CONFIG2_TOG_MUX_1M_MASK    0x20000u
43805 #define XTALOSC_RCOSC_CONFIG2_TOG_MUX_1M_SHIFT   17
43806 #define XTALOSC_RCOSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK 0x80000000u
43807 #define XTALOSC_RCOSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT 31
43808 /* OSC_32K Bit Fields */
43809 #define XTALOSC_OSC_32K_RTC_XTAL_SOURCE_MASK     0x1u
43810 #define XTALOSC_OSC_32K_RTC_XTAL_SOURCE_SHIFT    0
43811 /* OSC_32K_SET Bit Fields */
43812 #define XTALOSC_OSC_32K_SET_RTC_XTAL_SOURCE_MASK 0x1u
43813 #define XTALOSC_OSC_32K_SET_RTC_XTAL_SOURCE_SHIFT 0
43814 /* OSC_32K_CLR Bit Fields */
43815 #define XTALOSC_OSC_32K_CLR_RTC_XTAL_SOURCE_MASK 0x1u
43816 #define XTALOSC_OSC_32K_CLR_RTC_XTAL_SOURCE_SHIFT 0
43817 /* OSC_32K_TOG Bit Fields */
43818 #define XTALOSC_OSC_32K_TOG_RTC_XTAL_SOURCE_MASK 0x1u
43819 #define XTALOSC_OSC_32K_TOG_RTC_XTAL_SOURCE_SHIFT 0
43820 
43821 /*!
43822  * @}
43823  */ /* end of group XTALOSC_Register_Masks */
43824 
43825 /* XTALOSC - Peripheral instance base addresses */
43826 /** Peripheral XTALOSC base address */
43827 #define XTALOSC_BASE                             (0x30360000u)
43828 /** Peripheral XTALOSC base pointer */
43829 #define XTALOSC                                  ((XTALOSC_Type *)XTALOSC_BASE)
43830 #define XTALOSC_BASE_PTR                         (XTALOSC)
43831 /** Array initializer of XTALOSC peripheral base addresses */
43832 #define XTALOSC_BASE_ADDRS                       { XTALOSC_BASE }
43833 /** Array initializer of XTALOSC peripheral base pointers */
43834 #define XTALOSC_BASE_PTRS                        { XTALOSC }
43835 /* ----------------------------------------------------------------------------
43836    -- XTALOSC - Register accessor macros
43837    ---------------------------------------------------------------------------- */
43838 
43839 /*!
43840  * @addtogroup XTALOSC_Register_Accessor_Macros XTALOSC - Register accessor macros
43841  * @{
43842  */
43843 
43844 
43845 /* XTALOSC - Register instance definitions */
43846 /* XTALOSC */
43847 #define XTALOSC_CTRL_24M                         XTALOSC_CTRL_24M_REG(XTALOSC_BASE_PTR)
43848 #define XTALOSC_CTRL_24M_SET                     XTALOSC_CTRL_24M_SET_REG(XTALOSC_BASE_PTR)
43849 #define XTALOSC_CTRL_24M_CLR                     XTALOSC_CTRL_24M_CLR_REG(XTALOSC_BASE_PTR)
43850 #define XTALOSC_CTRL_24M_TOG                     XTALOSC_CTRL_24M_TOG_REG(XTALOSC_BASE_PTR)
43851 #define XTALOSC_RCOSC_CONFIG0                    XTALOSC_RCOSC_CONFIG0_REG(XTALOSC_BASE_PTR)
43852 #define XTALOSC_RCOSC_CONFIG0_SET                XTALOSC_RCOSC_CONFIG0_SET_REG(XTALOSC_BASE_PTR)
43853 #define XTALOSC_RCOSC_CONFIG0_CLR                XTALOSC_RCOSC_CONFIG0_CLR_REG(XTALOSC_BASE_PTR)
43854 #define XTALOSC_RCOSC_CONFIG0_TOG                XTALOSC_RCOSC_CONFIG0_TOG_REG(XTALOSC_BASE_PTR)
43855 #define XTALOSC_RCOSC_CONFIG1                    XTALOSC_RCOSC_CONFIG1_REG(XTALOSC_BASE_PTR)
43856 #define XTALOSC_RCOSC_CONFIG1_SET                XTALOSC_RCOSC_CONFIG1_SET_REG(XTALOSC_BASE_PTR)
43857 #define XTALOSC_RCOSC_CONFIG1_CLR                XTALOSC_RCOSC_CONFIG1_CLR_REG(XTALOSC_BASE_PTR)
43858 #define XTALOSC_RCOSC_CONFIG1_TOG                XTALOSC_RCOSC_CONFIG1_TOG_REG(XTALOSC_BASE_PTR)
43859 #define XTALOSC_RCOSC_CONFIG2                    XTALOSC_RCOSC_CONFIG2_REG(XTALOSC_BASE_PTR)
43860 #define XTALOSC_RCOSC_CONFIG2_SET                XTALOSC_RCOSC_CONFIG2_SET_REG(XTALOSC_BASE_PTR)
43861 #define XTALOSC_RCOSC_CONFIG2_CLR                XTALOSC_RCOSC_CONFIG2_CLR_REG(XTALOSC_BASE_PTR)
43862 #define XTALOSC_RCOSC_CONFIG2_TOG                XTALOSC_RCOSC_CONFIG2_TOG_REG(XTALOSC_BASE_PTR)
43863 #define XTALOSC_OSC_32K                          XTALOSC_OSC_32K_REG(XTALOSC_BASE_PTR)
43864 #define XTALOSC_OSC_32K_SET                      XTALOSC_OSC_32K_SET_REG(XTALOSC_BASE_PTR)
43865 #define XTALOSC_OSC_32K_CLR                      XTALOSC_OSC_32K_CLR_REG(XTALOSC_BASE_PTR)
43866 #define XTALOSC_OSC_32K_TOG                      XTALOSC_OSC_32K_TOG_REG(XTALOSC_BASE_PTR)
43867 /*!
43868  * @}
43869  */ /* end of group XTALOSC_Register_Accessor_Macros */
43870 
43871 
43872 /*!
43873  * @}
43874  */ /* end of group XTALOSC_Peripheral */
43875 
43876 /* ----------------------------------------------------------------------------
43877    -- uSDHC Peripheral Access Layer
43878    ---------------------------------------------------------------------------- */
43879 
43880 /*!
43881  * @addtogroup uSDHC_Peripheral_Access_Layer uSDHC Peripheral Access Layer
43882  * @{
43883  */
43884 
43885 /** uSDHC - Register Layout Typedef */
43886 typedef struct {
43887   __IO  uint32_t DS_ADDR;                                /**< DMA System Address, offset: 0x0 */
43888   __IO  uint32_t BLK_ATT;                                /**< Block Attributes, offset: 0x4 */
43889   __IO  uint32_t CMD_ARG;                                /**< Command Argument, offset: 0x8 */
43890   __IO  uint32_t CMD_XFR_TYP;                            /**< Command Transfer Type, offset: 0xC */
43891   __I   uint32_t CMD_RSP0;                               /**< Command Response0, offset: 0x10 */
43892   __I   uint32_t CMD_RSP1;                               /**< Command Response1, offset: 0x14 */
43893   __I   uint32_t CMD_RSP2;                               /**< Command Response2, offset: 0x18 */
43894   __I   uint32_t CMD_RSP3;                               /**< Command Response3, offset: 0x1C */
43895   __IO  uint32_t DATA_BUFF_ACC_PORT;                     /**< Data Buffer Access Port, offset: 0x20 */
43896   __I   uint32_t PRES_STATE;                             /**< Present State, offset: 0x24 */
43897   __IO  uint32_t PROT_CTRL;                              /**< Protocol Control, offset: 0x28 */
43898   __IO  uint32_t SYS_CTRL;                               /**< System Control, offset: 0x2C */
43899   __IO  uint32_t INT_STATUS;                             /**< Interrupt Status, offset: 0x30 */
43900   __IO  uint32_t INT_STATUS_EN;                          /**< Interrupt Status Enable, offset: 0x34 */
43901   __IO  uint32_t INT_SIGNAL_EN;                          /**< Interrupt Signal Enable, offset: 0x38 */
43902   __I   uint32_t AUTOCMD12_ERR_STATUS;                   /**< Auto CMD12 Error Status, offset: 0x3C */
43903   __I   uint32_t HOST_CTRL_CAP;                          /**< Host Controller Capabilities, offset: 0x40 */
43904   __IO  uint32_t WTMK_LVL;                               /**< Watermark Level, offset: 0x44 */
43905   __IO  uint32_t MIX_CTRL;                               /**< Mixer Control, offset: 0x48 */
43906   uint8_t RESERVED_0[4];
43907   __O   uint32_t FORCE_EVENT;                            /**< Force Event, offset: 0x50 */
43908   __I   uint32_t ADMA_ERR_STATUS;                        /**< ADMA Error Status Register, offset: 0x54 */
43909   __IO  uint32_t ADMA_SYS_ADDR;                          /**< ADMA System Address, offset: 0x58 */
43910   uint8_t RESERVED_1[4];
43911   __IO  uint32_t DLL_CTRL;                               /**< DLL (Delay Line) Control, offset: 0x60 */
43912   __I   uint32_t DLL_STATUS;                             /**< DLL Status, offset: 0x64 */
43913   __IO  uint32_t CLK_TUNE_CTRL_STATUS;                   /**< CLK Tuning Control and Status, offset: 0x68 */
43914   uint8_t RESERVED_2[4];
43915   __IO  uint32_t STROBE_DLL_CTRL;                        /**< Strobe DLL Control, offset: 0x70 */
43916   __I   uint32_t STROBE_DLL_STATUS;                      /**< Strobe DLL Status, offset: 0x74 */
43917   uint8_t RESERVED_3[72];
43918   __IO  uint32_t VEND_SPEC;                              /**< Vendor Specific Register, offset: 0xC0 */
43919   __IO  uint32_t MMC_BOOT;                               /**< MMC Boot Register, offset: 0xC4 */
43920   __IO  uint32_t VEND_SPEC2;                             /**< Vendor Specific 2 Register, offset: 0xC8 */
43921   __IO  uint32_t TUNING_CTRL;                            /**< Tuning Control Register, offset: 0xCC */
43922 } uSDHC_Type, *uSDHC_MemMapPtr;
43923 /* ----------------------------------------------------------------------------
43924    -- uSDHC - Register accessor macros
43925    ---------------------------------------------------------------------------- */
43926 
43927 /*!
43928  * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros
43929  * @{
43930  */
43931 
43932 
43933 /* uSDHC - Register accessors */
43934 #define uSDHC_DS_ADDR_REG(base)                  ((base)->DS_ADDR)
43935 #define uSDHC_BLK_ATT_REG(base)                  ((base)->BLK_ATT)
43936 #define uSDHC_CMD_ARG_REG(base)                  ((base)->CMD_ARG)
43937 #define uSDHC_CMD_XFR_TYP_REG(base)              ((base)->CMD_XFR_TYP)
43938 #define uSDHC_CMD_RSP0_REG(base)                 ((base)->CMD_RSP0)
43939 #define uSDHC_CMD_RSP1_REG(base)                 ((base)->CMD_RSP1)
43940 #define uSDHC_CMD_RSP2_REG(base)                 ((base)->CMD_RSP2)
43941 #define uSDHC_CMD_RSP3_REG(base)                 ((base)->CMD_RSP3)
43942 #define uSDHC_DATA_BUFF_ACC_PORT_REG(base)       ((base)->DATA_BUFF_ACC_PORT)
43943 #define uSDHC_PRES_STATE_REG(base)               ((base)->PRES_STATE)
43944 #define uSDHC_PROT_CTRL_REG(base)                ((base)->PROT_CTRL)
43945 #define uSDHC_SYS_CTRL_REG(base)                 ((base)->SYS_CTRL)
43946 #define uSDHC_INT_STATUS_REG(base)               ((base)->INT_STATUS)
43947 #define uSDHC_INT_STATUS_EN_REG(base)            ((base)->INT_STATUS_EN)
43948 #define uSDHC_INT_SIGNAL_EN_REG(base)            ((base)->INT_SIGNAL_EN)
43949 #define uSDHC_AUTOCMD12_ERR_STATUS_REG(base)     ((base)->AUTOCMD12_ERR_STATUS)
43950 #define uSDHC_HOST_CTRL_CAP_REG(base)            ((base)->HOST_CTRL_CAP)
43951 #define uSDHC_WTMK_LVL_REG(base)                 ((base)->WTMK_LVL)
43952 #define uSDHC_MIX_CTRL_REG(base)                 ((base)->MIX_CTRL)
43953 #define uSDHC_FORCE_EVENT_REG(base)              ((base)->FORCE_EVENT)
43954 #define uSDHC_ADMA_ERR_STATUS_REG(base)          ((base)->ADMA_ERR_STATUS)
43955 #define uSDHC_ADMA_SYS_ADDR_REG(base)            ((base)->ADMA_SYS_ADDR)
43956 #define uSDHC_DLL_CTRL_REG(base)                 ((base)->DLL_CTRL)
43957 #define uSDHC_DLL_STATUS_REG(base)               ((base)->DLL_STATUS)
43958 #define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base)     ((base)->CLK_TUNE_CTRL_STATUS)
43959 #define uSDHC_STROBE_DLL_CTRL_REG(base)          ((base)->STROBE_DLL_CTRL)
43960 #define uSDHC_STROBE_DLL_STATUS_REG(base)        ((base)->STROBE_DLL_STATUS)
43961 #define uSDHC_VEND_SPEC_REG(base)                ((base)->VEND_SPEC)
43962 #define uSDHC_MMC_BOOT_REG(base)                 ((base)->MMC_BOOT)
43963 #define uSDHC_VEND_SPEC2_REG(base)               ((base)->VEND_SPEC2)
43964 #define uSDHC_TUNING_CTRL_REG(base)              ((base)->TUNING_CTRL)
43965 
43966 /*!
43967  * @}
43968  */ /* end of group uSDHC_Register_Accessor_Macros */
43969 /* ----------------------------------------------------------------------------
43970    -- uSDHC Register Masks
43971    ---------------------------------------------------------------------------- */
43972 
43973 /*!
43974  * @addtogroup uSDHC_Register_Masks uSDHC Register Masks
43975  * @{
43976  */
43977 
43978 /* DS_ADDR Bit Fields */
43979 #define uSDHC_DS_ADDR_DS_ADDR_MASK               0xFFFFFFFCu
43980 #define uSDHC_DS_ADDR_DS_ADDR_SHIFT              2
43981 #define uSDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_DS_ADDR_DS_ADDR_SHIFT))&uSDHC_DS_ADDR_DS_ADDR_MASK)
43982 /* BLK_ATT Bit Fields */
43983 #define uSDHC_BLK_ATT_BLKSIZE_MASK               0x1FFFu
43984 #define uSDHC_BLK_ATT_BLKSIZE_SHIFT              0
43985 #define uSDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKSIZE_SHIFT))&uSDHC_BLK_ATT_BLKSIZE_MASK)
43986 #define uSDHC_BLK_ATT_BLKCNT_MASK                0xFFFF0000u
43987 #define uSDHC_BLK_ATT_BLKCNT_SHIFT               16
43988 #define uSDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKCNT_SHIFT))&uSDHC_BLK_ATT_BLKCNT_MASK)
43989 /* CMD_ARG Bit Fields */
43990 #define uSDHC_CMD_ARG_CMDARG_MASK                0xFFFFFFFFu
43991 #define uSDHC_CMD_ARG_CMDARG_SHIFT               0
43992 #define uSDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_ARG_CMDARG_SHIFT))&uSDHC_CMD_ARG_CMDARG_MASK)
43993 /* CMD_XFR_TYP Bit Fields */
43994 #define uSDHC_CMD_XFR_TYP_RSPTYP_MASK            0x30000u
43995 #define uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT           16
43996 #define uSDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT))&uSDHC_CMD_XFR_TYP_RSPTYP_MASK)
43997 #define uSDHC_CMD_XFR_TYP_CCCEN_MASK             0x80000u
43998 #define uSDHC_CMD_XFR_TYP_CCCEN_SHIFT            19
43999 #define uSDHC_CMD_XFR_TYP_CICEN_MASK             0x100000u
44000 #define uSDHC_CMD_XFR_TYP_CICEN_SHIFT            20
44001 #define uSDHC_CMD_XFR_TYP_DPSEL_MASK             0x200000u
44002 #define uSDHC_CMD_XFR_TYP_DPSEL_SHIFT            21
44003 #define uSDHC_CMD_XFR_TYP_CMDTYP_MASK            0xC00000u
44004 #define uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT           22
44005 #define uSDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT))&uSDHC_CMD_XFR_TYP_CMDTYP_MASK)
44006 #define uSDHC_CMD_XFR_TYP_CMDINX_MASK            0x3F000000u
44007 #define uSDHC_CMD_XFR_TYP_CMDINX_SHIFT           24
44008 #define uSDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDINX_SHIFT))&uSDHC_CMD_XFR_TYP_CMDINX_MASK)
44009 /* CMD_RSP0 Bit Fields */
44010 #define uSDHC_CMD_RSP0_CMDRSP0_MASK              0xFFFFFFFFu
44011 #define uSDHC_CMD_RSP0_CMDRSP0_SHIFT             0
44012 #define uSDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP0_CMDRSP0_SHIFT))&uSDHC_CMD_RSP0_CMDRSP0_MASK)
44013 /* CMD_RSP1 Bit Fields */
44014 #define uSDHC_CMD_RSP1_CMDRSP1_MASK              0xFFFFFFFFu
44015 #define uSDHC_CMD_RSP1_CMDRSP1_SHIFT             0
44016 #define uSDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP1_CMDRSP1_SHIFT))&uSDHC_CMD_RSP1_CMDRSP1_MASK)
44017 /* CMD_RSP2 Bit Fields */
44018 #define uSDHC_CMD_RSP2_CMDRSP2_MASK              0xFFFFFFFFu
44019 #define uSDHC_CMD_RSP2_CMDRSP2_SHIFT             0
44020 #define uSDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP2_CMDRSP2_SHIFT))&uSDHC_CMD_RSP2_CMDRSP2_MASK)
44021 /* CMD_RSP3 Bit Fields */
44022 #define uSDHC_CMD_RSP3_CMDRSP3_MASK              0xFFFFFFFFu
44023 #define uSDHC_CMD_RSP3_CMDRSP3_SHIFT             0
44024 #define uSDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP3_CMDRSP3_SHIFT))&uSDHC_CMD_RSP3_CMDRSP3_MASK)
44025 /* DATA_BUFF_ACC_PORT Bit Fields */
44026 #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    0xFFFFFFFFu
44027 #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   0
44028 #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT))&uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
44029 /* PRES_STATE Bit Fields */
44030 #define uSDHC_PRES_STATE_CIHB_MASK               0x1u
44031 #define uSDHC_PRES_STATE_CIHB_SHIFT              0
44032 #define uSDHC_PRES_STATE_CDIHB_MASK              0x2u
44033 #define uSDHC_PRES_STATE_CDIHB_SHIFT             1
44034 #define uSDHC_PRES_STATE_DLA_MASK                0x4u
44035 #define uSDHC_PRES_STATE_DLA_SHIFT               2
44036 #define uSDHC_PRES_STATE_SDSTB_MASK              0x8u
44037 #define uSDHC_PRES_STATE_SDSTB_SHIFT             3
44038 #define uSDHC_PRES_STATE_IPGOFF_MASK             0x10u
44039 #define uSDHC_PRES_STATE_IPGOFF_SHIFT            4
44040 #define uSDHC_PRES_STATE_HCKOFF_MASK             0x20u
44041 #define uSDHC_PRES_STATE_HCKOFF_SHIFT            5
44042 #define uSDHC_PRES_STATE_PEROFF_MASK             0x40u
44043 #define uSDHC_PRES_STATE_PEROFF_SHIFT            6
44044 #define uSDHC_PRES_STATE_SDOFF_MASK              0x80u
44045 #define uSDHC_PRES_STATE_SDOFF_SHIFT             7
44046 #define uSDHC_PRES_STATE_WTA_MASK                0x100u
44047 #define uSDHC_PRES_STATE_WTA_SHIFT               8
44048 #define uSDHC_PRES_STATE_RTA_MASK                0x200u
44049 #define uSDHC_PRES_STATE_RTA_SHIFT               9
44050 #define uSDHC_PRES_STATE_BWEN_MASK               0x400u
44051 #define uSDHC_PRES_STATE_BWEN_SHIFT              10
44052 #define uSDHC_PRES_STATE_BREN_MASK               0x800u
44053 #define uSDHC_PRES_STATE_BREN_SHIFT              11
44054 #define uSDHC_PRES_STATE_RTR_MASK                0x1000u
44055 #define uSDHC_PRES_STATE_RTR_SHIFT               12
44056 #define uSDHC_PRES_STATE_TSCD_MASK               0x8000u
44057 #define uSDHC_PRES_STATE_TSCD_SHIFT              15
44058 #define uSDHC_PRES_STATE_CINST_MASK              0x10000u
44059 #define uSDHC_PRES_STATE_CINST_SHIFT             16
44060 #define uSDHC_PRES_STATE_CDPL_MASK               0x40000u
44061 #define uSDHC_PRES_STATE_CDPL_SHIFT              18
44062 #define uSDHC_PRES_STATE_WPSPL_MASK              0x80000u
44063 #define uSDHC_PRES_STATE_WPSPL_SHIFT             19
44064 #define uSDHC_PRES_STATE_CLSL_MASK               0x800000u
44065 #define uSDHC_PRES_STATE_CLSL_SHIFT              23
44066 #define uSDHC_PRES_STATE_DLSL_MASK               0xFF000000u
44067 #define uSDHC_PRES_STATE_DLSL_SHIFT              24
44068 #define uSDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_PRES_STATE_DLSL_SHIFT))&uSDHC_PRES_STATE_DLSL_MASK)
44069 /* PROT_CTRL Bit Fields */
44070 #define uSDHC_PROT_CTRL_LCTL_MASK                0x1u
44071 #define uSDHC_PROT_CTRL_LCTL_SHIFT               0
44072 #define uSDHC_PROT_CTRL_DTW_MASK                 0x6u
44073 #define uSDHC_PROT_CTRL_DTW_SHIFT                1
44074 #define uSDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DTW_SHIFT))&uSDHC_PROT_CTRL_DTW_MASK)
44075 #define uSDHC_PROT_CTRL_D3CD_MASK                0x8u
44076 #define uSDHC_PROT_CTRL_D3CD_SHIFT               3
44077 #define uSDHC_PROT_CTRL_EMODE_MASK               0x30u
44078 #define uSDHC_PROT_CTRL_EMODE_SHIFT              4
44079 #define uSDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_EMODE_SHIFT))&uSDHC_PROT_CTRL_EMODE_MASK)
44080 #define uSDHC_PROT_CTRL_CDTL_MASK                0x40u
44081 #define uSDHC_PROT_CTRL_CDTL_SHIFT               6
44082 #define uSDHC_PROT_CTRL_CDSS_MASK                0x80u
44083 #define uSDHC_PROT_CTRL_CDSS_SHIFT               7
44084 #define uSDHC_PROT_CTRL_DMASEL_MASK              0x300u
44085 #define uSDHC_PROT_CTRL_DMASEL_SHIFT             8
44086 #define uSDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DMASEL_SHIFT))&uSDHC_PROT_CTRL_DMASEL_MASK)
44087 #define uSDHC_PROT_CTRL_SABGREQ_MASK             0x10000u
44088 #define uSDHC_PROT_CTRL_SABGREQ_SHIFT            16
44089 #define uSDHC_PROT_CTRL_CREQ_MASK                0x20000u
44090 #define uSDHC_PROT_CTRL_CREQ_SHIFT               17
44091 #define uSDHC_PROT_CTRL_RWCTL_MASK               0x40000u
44092 #define uSDHC_PROT_CTRL_RWCTL_SHIFT              18
44093 #define uSDHC_PROT_CTRL_IABG_MASK                0x80000u
44094 #define uSDHC_PROT_CTRL_IABG_SHIFT               19
44095 #define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     0x100000u
44096 #define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    20
44097 #define uSDHC_PROT_CTRL_WECINT_MASK              0x1000000u
44098 #define uSDHC_PROT_CTRL_WECINT_SHIFT             24
44099 #define uSDHC_PROT_CTRL_WECINS_MASK              0x2000000u
44100 #define uSDHC_PROT_CTRL_WECINS_SHIFT             25
44101 #define uSDHC_PROT_CTRL_WECRM_MASK               0x4000000u
44102 #define uSDHC_PROT_CTRL_WECRM_SHIFT              26
44103 #define uSDHC_PROT_CTRL_BURST_LEN_EN_MASK        0x38000000u
44104 #define uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       27
44105 #define uSDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT))&uSDHC_PROT_CTRL_BURST_LEN_EN_MASK)
44106 #define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    0x40000000u
44107 #define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   30
44108 /* SYS_CTRL Bit Fields */
44109 #define uSDHC_SYS_CTRL_DVS_MASK                  0xF0u
44110 #define uSDHC_SYS_CTRL_DVS_SHIFT                 4
44111 #define uSDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DVS_SHIFT))&uSDHC_SYS_CTRL_DVS_MASK)
44112 #define uSDHC_SYS_CTRL_SDCLKFS_MASK              0xFF00u
44113 #define uSDHC_SYS_CTRL_SDCLKFS_SHIFT             8
44114 #define uSDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_SDCLKFS_SHIFT))&uSDHC_SYS_CTRL_SDCLKFS_MASK)
44115 #define uSDHC_SYS_CTRL_DTOCV_MASK                0xF0000u
44116 #define uSDHC_SYS_CTRL_DTOCV_SHIFT               16
44117 #define uSDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DTOCV_SHIFT))&uSDHC_SYS_CTRL_DTOCV_MASK)
44118 #define uSDHC_SYS_CTRL_IPP_RST_N_MASK            0x800000u
44119 #define uSDHC_SYS_CTRL_IPP_RST_N_SHIFT           23
44120 #define uSDHC_SYS_CTRL_RSTA_MASK                 0x1000000u
44121 #define uSDHC_SYS_CTRL_RSTA_SHIFT                24
44122 #define uSDHC_SYS_CTRL_RSTC_MASK                 0x2000000u
44123 #define uSDHC_SYS_CTRL_RSTC_SHIFT                25
44124 #define uSDHC_SYS_CTRL_RSTD_MASK                 0x4000000u
44125 #define uSDHC_SYS_CTRL_RSTD_SHIFT                26
44126 #define uSDHC_SYS_CTRL_INITA_MASK                0x8000000u
44127 #define uSDHC_SYS_CTRL_INITA_SHIFT               27
44128 #define uSDHC_SYS_CTRL_RSTT_MASK                 0x10000000u
44129 #define uSDHC_SYS_CTRL_RSTT_SHIFT                28
44130 /* INT_STATUS Bit Fields */
44131 #define uSDHC_INT_STATUS_CC_MASK                 0x1u
44132 #define uSDHC_INT_STATUS_CC_SHIFT                0
44133 #define uSDHC_INT_STATUS_TC_MASK                 0x2u
44134 #define uSDHC_INT_STATUS_TC_SHIFT                1
44135 #define uSDHC_INT_STATUS_BGE_MASK                0x4u
44136 #define uSDHC_INT_STATUS_BGE_SHIFT               2
44137 #define uSDHC_INT_STATUS_DINT_MASK               0x8u
44138 #define uSDHC_INT_STATUS_DINT_SHIFT              3
44139 #define uSDHC_INT_STATUS_BWR_MASK                0x10u
44140 #define uSDHC_INT_STATUS_BWR_SHIFT               4
44141 #define uSDHC_INT_STATUS_BRR_MASK                0x20u
44142 #define uSDHC_INT_STATUS_BRR_SHIFT               5
44143 #define uSDHC_INT_STATUS_CINS_MASK               0x40u
44144 #define uSDHC_INT_STATUS_CINS_SHIFT              6
44145 #define uSDHC_INT_STATUS_CRM_MASK                0x80u
44146 #define uSDHC_INT_STATUS_CRM_SHIFT               7
44147 #define uSDHC_INT_STATUS_CINT_MASK               0x100u
44148 #define uSDHC_INT_STATUS_CINT_SHIFT              8
44149 #define uSDHC_INT_STATUS_RTE_MASK                0x1000u
44150 #define uSDHC_INT_STATUS_RTE_SHIFT               12
44151 #define uSDHC_INT_STATUS_TP_MASK                 0x4000u
44152 #define uSDHC_INT_STATUS_TP_SHIFT                14
44153 #define uSDHC_INT_STATUS_CTOE_MASK               0x10000u
44154 #define uSDHC_INT_STATUS_CTOE_SHIFT              16
44155 #define uSDHC_INT_STATUS_CCE_MASK                0x20000u
44156 #define uSDHC_INT_STATUS_CCE_SHIFT               17
44157 #define uSDHC_INT_STATUS_CEBE_MASK               0x40000u
44158 #define uSDHC_INT_STATUS_CEBE_SHIFT              18
44159 #define uSDHC_INT_STATUS_CIE_MASK                0x80000u
44160 #define uSDHC_INT_STATUS_CIE_SHIFT               19
44161 #define uSDHC_INT_STATUS_DTOE_MASK               0x100000u
44162 #define uSDHC_INT_STATUS_DTOE_SHIFT              20
44163 #define uSDHC_INT_STATUS_DCE_MASK                0x200000u
44164 #define uSDHC_INT_STATUS_DCE_SHIFT               21
44165 #define uSDHC_INT_STATUS_DEBE_MASK               0x400000u
44166 #define uSDHC_INT_STATUS_DEBE_SHIFT              22
44167 #define uSDHC_INT_STATUS_AC12E_MASK              0x1000000u
44168 #define uSDHC_INT_STATUS_AC12E_SHIFT             24
44169 #define uSDHC_INT_STATUS_TNE_MASK                0x4000000u
44170 #define uSDHC_INT_STATUS_TNE_SHIFT               26
44171 #define uSDHC_INT_STATUS_DMAE_MASK               0x10000000u
44172 #define uSDHC_INT_STATUS_DMAE_SHIFT              28
44173 /* INT_STATUS_EN Bit Fields */
44174 #define uSDHC_INT_STATUS_EN_CCSEN_MASK           0x1u
44175 #define uSDHC_INT_STATUS_EN_CCSEN_SHIFT          0
44176 #define uSDHC_INT_STATUS_EN_TCSEN_MASK           0x2u
44177 #define uSDHC_INT_STATUS_EN_TCSEN_SHIFT          1
44178 #define uSDHC_INT_STATUS_EN_BGESEN_MASK          0x4u
44179 #define uSDHC_INT_STATUS_EN_BGESEN_SHIFT         2
44180 #define uSDHC_INT_STATUS_EN_DINTSEN_MASK         0x8u
44181 #define uSDHC_INT_STATUS_EN_DINTSEN_SHIFT        3
44182 #define uSDHC_INT_STATUS_EN_BWRSEN_MASK          0x10u
44183 #define uSDHC_INT_STATUS_EN_BWRSEN_SHIFT         4
44184 #define uSDHC_INT_STATUS_EN_BRRSEN_MASK          0x20u
44185 #define uSDHC_INT_STATUS_EN_BRRSEN_SHIFT         5
44186 #define uSDHC_INT_STATUS_EN_CINSSEN_MASK         0x40u
44187 #define uSDHC_INT_STATUS_EN_CINSSEN_SHIFT        6
44188 #define uSDHC_INT_STATUS_EN_CRMSEN_MASK          0x80u
44189 #define uSDHC_INT_STATUS_EN_CRMSEN_SHIFT         7
44190 #define uSDHC_INT_STATUS_EN_CINTSEN_MASK         0x100u
44191 #define uSDHC_INT_STATUS_EN_CINTSEN_SHIFT        8
44192 #define uSDHC_INT_STATUS_EN_RTESEN_MASK          0x1000u
44193 #define uSDHC_INT_STATUS_EN_RTESEN_SHIFT         12
44194 #define uSDHC_INT_STATUS_EN_TPSEN_MASK           0x4000u
44195 #define uSDHC_INT_STATUS_EN_TPSEN_SHIFT          14
44196 #define uSDHC_INT_STATUS_EN_CTOESEN_MASK         0x10000u
44197 #define uSDHC_INT_STATUS_EN_CTOESEN_SHIFT        16
44198 #define uSDHC_INT_STATUS_EN_CCESEN_MASK          0x20000u
44199 #define uSDHC_INT_STATUS_EN_CCESEN_SHIFT         17
44200 #define uSDHC_INT_STATUS_EN_CEBESEN_MASK         0x40000u
44201 #define uSDHC_INT_STATUS_EN_CEBESEN_SHIFT        18
44202 #define uSDHC_INT_STATUS_EN_CIESEN_MASK          0x80000u
44203 #define uSDHC_INT_STATUS_EN_CIESEN_SHIFT         19
44204 #define uSDHC_INT_STATUS_EN_DTOESEN_MASK         0x100000u
44205 #define uSDHC_INT_STATUS_EN_DTOESEN_SHIFT        20
44206 #define uSDHC_INT_STATUS_EN_DCESEN_MASK          0x200000u
44207 #define uSDHC_INT_STATUS_EN_DCESEN_SHIFT         21
44208 #define uSDHC_INT_STATUS_EN_DEBESEN_MASK         0x400000u
44209 #define uSDHC_INT_STATUS_EN_DEBESEN_SHIFT        22
44210 #define uSDHC_INT_STATUS_EN_AC12ESEN_MASK        0x1000000u
44211 #define uSDHC_INT_STATUS_EN_AC12ESEN_SHIFT       24
44212 #define uSDHC_INT_STATUS_EN_TNESEN_MASK          0x4000000u
44213 #define uSDHC_INT_STATUS_EN_TNESEN_SHIFT         26
44214 #define uSDHC_INT_STATUS_EN_DMAESEN_MASK         0x10000000u
44215 #define uSDHC_INT_STATUS_EN_DMAESEN_SHIFT        28
44216 /* INT_SIGNAL_EN Bit Fields */
44217 #define uSDHC_INT_SIGNAL_EN_CCIEN_MASK           0x1u
44218 #define uSDHC_INT_SIGNAL_EN_CCIEN_SHIFT          0
44219 #define uSDHC_INT_SIGNAL_EN_TCIEN_MASK           0x2u
44220 #define uSDHC_INT_SIGNAL_EN_TCIEN_SHIFT          1
44221 #define uSDHC_INT_SIGNAL_EN_BGEIEN_MASK          0x4u
44222 #define uSDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         2
44223 #define uSDHC_INT_SIGNAL_EN_DINTIEN_MASK         0x8u
44224 #define uSDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        3
44225 #define uSDHC_INT_SIGNAL_EN_BWRIEN_MASK          0x10u
44226 #define uSDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         4
44227 #define uSDHC_INT_SIGNAL_EN_BRRIEN_MASK          0x20u
44228 #define uSDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         5
44229 #define uSDHC_INT_SIGNAL_EN_CINSIEN_MASK         0x40u
44230 #define uSDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        6
44231 #define uSDHC_INT_SIGNAL_EN_CRMIEN_MASK          0x80u
44232 #define uSDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         7
44233 #define uSDHC_INT_SIGNAL_EN_CINTIEN_MASK         0x100u
44234 #define uSDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        8
44235 #define uSDHC_INT_SIGNAL_EN_RTEIEN_MASK          0x1000u
44236 #define uSDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         12
44237 #define uSDHC_INT_SIGNAL_EN_TPIEN_MASK           0x4000u
44238 #define uSDHC_INT_SIGNAL_EN_TPIEN_SHIFT          14
44239 #define uSDHC_INT_SIGNAL_EN_CTOEIEN_MASK         0x10000u
44240 #define uSDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        16
44241 #define uSDHC_INT_SIGNAL_EN_CCEIEN_MASK          0x20000u
44242 #define uSDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         17
44243 #define uSDHC_INT_SIGNAL_EN_CEBEIEN_MASK         0x40000u
44244 #define uSDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        18
44245 #define uSDHC_INT_SIGNAL_EN_CIEIEN_MASK          0x80000u
44246 #define uSDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         19
44247 #define uSDHC_INT_SIGNAL_EN_DTOEIEN_MASK         0x100000u
44248 #define uSDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        20
44249 #define uSDHC_INT_SIGNAL_EN_DCEIEN_MASK          0x200000u
44250 #define uSDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         21
44251 #define uSDHC_INT_SIGNAL_EN_DEBEIEN_MASK         0x400000u
44252 #define uSDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        22
44253 #define uSDHC_INT_SIGNAL_EN_AC12EIEN_MASK        0x1000000u
44254 #define uSDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       24
44255 #define uSDHC_INT_SIGNAL_EN_TNEIEN_MASK          0x4000000u
44256 #define uSDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         26
44257 #define uSDHC_INT_SIGNAL_EN_DMAEIEN_MASK         0x10000000u
44258 #define uSDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        28
44259 /* AUTOCMD12_ERR_STATUS Bit Fields */
44260 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   0x1u
44261 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  0
44262 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  0x2u
44263 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT 1
44264 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  0x4u
44265 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT 2
44266 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   0x8u
44267 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  3
44268 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   0x10u
44269 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  4
44270 #define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK 0x80u
44271 #define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT 7
44272 #define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK 0x400000u
44273 #define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT 22
44274 #define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK 0x800000u
44275 #define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT 23
44276 /* HOST_CTRL_CAP Bit Fields */
44277 #define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   0x1u
44278 #define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  0
44279 #define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  0x2u
44280 #define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT 1
44281 #define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   0x4u
44282 #define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  2
44283 #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK 0xF00u
44284 #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT 8
44285 #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT))&uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
44286 #define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK 0x2000u
44287 #define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT 13
44288 #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK   0xC000u
44289 #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT  14
44290 #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE(x)     (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT))&uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
44291 #define uSDHC_HOST_CTRL_CAP_MBL_MASK             0x70000u
44292 #define uSDHC_HOST_CTRL_CAP_MBL_SHIFT            16
44293 #define uSDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_MBL_SHIFT))&uSDHC_HOST_CTRL_CAP_MBL_MASK)
44294 #define uSDHC_HOST_CTRL_CAP_ADMAS_MASK           0x100000u
44295 #define uSDHC_HOST_CTRL_CAP_ADMAS_SHIFT          20
44296 #define uSDHC_HOST_CTRL_CAP_HSS_MASK             0x200000u
44297 #define uSDHC_HOST_CTRL_CAP_HSS_SHIFT            21
44298 #define uSDHC_HOST_CTRL_CAP_DMAS_MASK            0x400000u
44299 #define uSDHC_HOST_CTRL_CAP_DMAS_SHIFT           22
44300 #define uSDHC_HOST_CTRL_CAP_SRS_MASK             0x800000u
44301 #define uSDHC_HOST_CTRL_CAP_SRS_SHIFT            23
44302 #define uSDHC_HOST_CTRL_CAP_VS33_MASK            0x1000000u
44303 #define uSDHC_HOST_CTRL_CAP_VS33_SHIFT           24
44304 #define uSDHC_HOST_CTRL_CAP_VS30_MASK            0x2000000u
44305 #define uSDHC_HOST_CTRL_CAP_VS30_SHIFT           25
44306 #define uSDHC_HOST_CTRL_CAP_VS18_MASK            0x4000000u
44307 #define uSDHC_HOST_CTRL_CAP_VS18_SHIFT           26
44308 /* WTMK_LVL Bit Fields */
44309 #define uSDHC_WTMK_LVL_RD_WML_MASK               0xFFu
44310 #define uSDHC_WTMK_LVL_RD_WML_SHIFT              0
44311 #define uSDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_WML_SHIFT))&uSDHC_WTMK_LVL_RD_WML_MASK)
44312 #define uSDHC_WTMK_LVL_RD_BRST_LEN_MASK          0x1F00u
44313 #define uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         8
44314 #define uSDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_RD_BRST_LEN_MASK)
44315 #define uSDHC_WTMK_LVL_WR_WML_MASK               0xFF0000u
44316 #define uSDHC_WTMK_LVL_WR_WML_SHIFT              16
44317 #define uSDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_WML_SHIFT))&uSDHC_WTMK_LVL_WR_WML_MASK)
44318 #define uSDHC_WTMK_LVL_WR_BRST_LEN_MASK          0x1F000000u
44319 #define uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         24
44320 #define uSDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_WR_BRST_LEN_MASK)
44321 /* MIX_CTRL Bit Fields */
44322 #define uSDHC_MIX_CTRL_DMAEN_MASK                0x1u
44323 #define uSDHC_MIX_CTRL_DMAEN_SHIFT               0
44324 #define uSDHC_MIX_CTRL_BCEN_MASK                 0x2u
44325 #define uSDHC_MIX_CTRL_BCEN_SHIFT                1
44326 #define uSDHC_MIX_CTRL_AC12EN_MASK               0x4u
44327 #define uSDHC_MIX_CTRL_AC12EN_SHIFT              2
44328 #define uSDHC_MIX_CTRL_DDR_EN_MASK               0x8u
44329 #define uSDHC_MIX_CTRL_DDR_EN_SHIFT              3
44330 #define uSDHC_MIX_CTRL_DTDSEL_MASK               0x10u
44331 #define uSDHC_MIX_CTRL_DTDSEL_SHIFT              4
44332 #define uSDHC_MIX_CTRL_MSBSEL_MASK               0x20u
44333 #define uSDHC_MIX_CTRL_MSBSEL_SHIFT              5
44334 #define uSDHC_MIX_CTRL_NIBBLE_POS_MASK           0x40u
44335 #define uSDHC_MIX_CTRL_NIBBLE_POS_SHIFT          6
44336 #define uSDHC_MIX_CTRL_AC23EN_MASK               0x80u
44337 #define uSDHC_MIX_CTRL_AC23EN_SHIFT              7
44338 #define uSDHC_MIX_CTRL_EXE_TUNE_MASK             0x400000u
44339 #define uSDHC_MIX_CTRL_EXE_TUNE_SHIFT            22
44340 #define uSDHC_MIX_CTRL_SMP_CLK_SEL_MASK          0x800000u
44341 #define uSDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         23
44342 #define uSDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         0x1000000u
44343 #define uSDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        24
44344 #define uSDHC_MIX_CTRL_FBCLK_SEL_MASK            0x2000000u
44345 #define uSDHC_MIX_CTRL_FBCLK_SEL_SHIFT           25
44346 #define uSDHC_MIX_CTRL_HS400_MODE_MASK           0x4000000u
44347 #define uSDHC_MIX_CTRL_HS400_MODE_SHIFT          26
44348 /* FORCE_EVENT Bit Fields */
44349 #define uSDHC_FORCE_EVENT_FEVTAC12NE_MASK        0x1u
44350 #define uSDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       0
44351 #define uSDHC_FORCE_EVENT_FEVTAC12TOE_MASK       0x2u
44352 #define uSDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      1
44353 #define uSDHC_FORCE_EVENT_FEVTAC12CE_MASK        0x4u
44354 #define uSDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       2
44355 #define uSDHC_FORCE_EVENT_FEVTAC12EBE_MASK       0x8u
44356 #define uSDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      3
44357 #define uSDHC_FORCE_EVENT_FEVTAC12IE_MASK        0x10u
44358 #define uSDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       4
44359 #define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     0x80u
44360 #define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    7
44361 #define uSDHC_FORCE_EVENT_FEVTCTOE_MASK          0x10000u
44362 #define uSDHC_FORCE_EVENT_FEVTCTOE_SHIFT         16
44363 #define uSDHC_FORCE_EVENT_FEVTCCE_MASK           0x20000u
44364 #define uSDHC_FORCE_EVENT_FEVTCCE_SHIFT          17
44365 #define uSDHC_FORCE_EVENT_FEVTCEBE_MASK          0x40000u
44366 #define uSDHC_FORCE_EVENT_FEVTCEBE_SHIFT         18
44367 #define uSDHC_FORCE_EVENT_FEVTCIE_MASK           0x80000u
44368 #define uSDHC_FORCE_EVENT_FEVTCIE_SHIFT          19
44369 #define uSDHC_FORCE_EVENT_FEVTDTOE_MASK          0x100000u
44370 #define uSDHC_FORCE_EVENT_FEVTDTOE_SHIFT         20
44371 #define uSDHC_FORCE_EVENT_FEVTDCE_MASK           0x200000u
44372 #define uSDHC_FORCE_EVENT_FEVTDCE_SHIFT          21
44373 #define uSDHC_FORCE_EVENT_FEVTDEBE_MASK          0x400000u
44374 #define uSDHC_FORCE_EVENT_FEVTDEBE_SHIFT         22
44375 #define uSDHC_FORCE_EVENT_FEVTAC12E_MASK         0x1000000u
44376 #define uSDHC_FORCE_EVENT_FEVTAC12E_SHIFT        24
44377 #define uSDHC_FORCE_EVENT_FEVTTNE_MASK           0x4000000u
44378 #define uSDHC_FORCE_EVENT_FEVTTNE_SHIFT          26
44379 #define uSDHC_FORCE_EVENT_FEVTDMAE_MASK          0x10000000u
44380 #define uSDHC_FORCE_EVENT_FEVTDMAE_SHIFT         28
44381 #define uSDHC_FORCE_EVENT_FEVTCINT_MASK          0x80000000u
44382 #define uSDHC_FORCE_EVENT_FEVTCINT_SHIFT         31
44383 /* ADMA_ERR_STATUS Bit Fields */
44384 #define uSDHC_ADMA_ERR_STATUS_ADMAES_MASK        0x3u
44385 #define uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       0
44386 #define uSDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT))&uSDHC_ADMA_ERR_STATUS_ADMAES_MASK)
44387 #define uSDHC_ADMA_ERR_STATUS_ADMALME_MASK       0x4u
44388 #define uSDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      2
44389 #define uSDHC_ADMA_ERR_STATUS_ADMADCE_MASK       0x8u
44390 #define uSDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      3
44391 /* ADMA_SYS_ADDR Bit Fields */
44392 #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        0xFFFFFFFCu
44393 #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       2
44394 #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT))&uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
44395 /* DLL_CTRL Bit Fields */
44396 #define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      0x1u
44397 #define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     0
44398 #define uSDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       0x2u
44399 #define uSDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      1
44400 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u
44401 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2
44402 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK 0x78u
44403 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT 3
44404 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
44405 #define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK 0x80u
44406 #define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT 7
44407 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u
44408 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT 8
44409 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u
44410 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9
44411 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
44412 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK 0x70000u
44413 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT 16
44414 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
44415 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u
44416 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20
44417 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
44418 #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u
44419 #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT 28
44420 #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
44421 /* DLL_STATUS Bit Fields */
44422 #define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   0x1u
44423 #define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  0
44424 #define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   0x2u
44425 #define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  1
44426 #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    0x1FCu
44427 #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   2
44428 #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
44429 #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    0xFE00u
44430 #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   9
44431 #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
44432 /* CLK_TUNE_CTRL_STATUS Bit Fields */
44433 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK 0xFu
44434 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT 0
44435 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
44436 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK 0xF0u
44437 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT 4
44438 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
44439 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK 0x7F00u
44440 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT 8
44441 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
44442 #define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  0x8000u
44443 #define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT 15
44444 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK 0xF0000u
44445 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT 16
44446 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
44447 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK 0xF00000u
44448 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT 20
44449 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
44450 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK 0x7F000000u
44451 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT 24
44452 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
44453 #define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  0x80000000u
44454 #define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT 31
44455 /* STROBE_DLL_CTRL Bit Fields */
44456 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK 0x1u
44457 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT 0
44458 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK 0x2u
44459 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT 1
44460 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u
44461 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2
44462 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK 0x38u
44463 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
44464 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
44465 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK 0x40u
44466 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT 6
44467 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK 0x80u
44468 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT 7
44469 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u
44470 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT 8
44471 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u
44472 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9
44473 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
44474 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u
44475 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20
44476 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
44477 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u
44478 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT 28
44479 #define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
44480 /* STROBE_DLL_STATUS Bit Fields */
44481 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK 0x1u
44482 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT 0
44483 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK 0x2u
44484 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT 1
44485 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK 0x1FCu
44486 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT 2
44487 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT))&uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
44488 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK 0xFE00u
44489 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT 9
44490 #define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT))&uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
44491 /* VEND_SPEC Bit Fields */
44492 #define uSDHC_VEND_SPEC_EXT_DMA_EN_MASK          0x1u
44493 #define uSDHC_VEND_SPEC_EXT_DMA_EN_SHIFT         0
44494 #define uSDHC_VEND_SPEC_VSELECT_MASK             0x2u
44495 #define uSDHC_VEND_SPEC_VSELECT_SHIFT            1
44496 #define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     0x4u
44497 #define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    2
44498 #define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  0x8u
44499 #define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT 3
44500 #define uSDHC_VEND_SPEC_DAT3_CD_POL_MASK         0x10u
44501 #define uSDHC_VEND_SPEC_DAT3_CD_POL_SHIFT        4
44502 #define uSDHC_VEND_SPEC_CD_POL_MASK              0x20u
44503 #define uSDHC_VEND_SPEC_CD_POL_SHIFT             5
44504 #define uSDHC_VEND_SPEC_WP_POL_MASK              0x40u
44505 #define uSDHC_VEND_SPEC_WP_POL_SHIFT             6
44506 #define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK     0x80u
44507 #define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT    7
44508 #define uSDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        0x100u
44509 #define uSDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       8
44510 #define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK     0x800u
44511 #define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT    11
44512 #define uSDHC_VEND_SPEC_HCLK_SOFT_EN_MASK        0x1000u
44513 #define uSDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT       12
44514 #define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK  0x2000u
44515 #define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT 13
44516 #define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK    0x4000u
44517 #define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT   14
44518 #define uSDHC_VEND_SPEC_CRC_CHK_DIS_MASK         0x8000u
44519 #define uSDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        15
44520 #define uSDHC_VEND_SPEC_INT_ST_VAL_MASK          0xFF0000u
44521 #define uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT         16
44522 #define uSDHC_VEND_SPEC_INT_ST_VAL(x)            (((uint32_t)(((uint32_t)(x))<<uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT))&uSDHC_VEND_SPEC_INT_ST_VAL_MASK)
44523 #define uSDHC_VEND_SPEC_CMD_BYTE_EN_MASK         0x80000000u
44524 #define uSDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        31
44525 /* MMC_BOOT Bit Fields */
44526 #define uSDHC_MMC_BOOT_DTOCV_ACK_MASK            0xFu
44527 #define uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT           0
44528 #define uSDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT))&uSDHC_MMC_BOOT_DTOCV_ACK_MASK)
44529 #define uSDHC_MMC_BOOT_BOOT_ACK_MASK             0x10u
44530 #define uSDHC_MMC_BOOT_BOOT_ACK_SHIFT            4
44531 #define uSDHC_MMC_BOOT_BOOT_MODE_MASK            0x20u
44532 #define uSDHC_MMC_BOOT_BOOT_MODE_SHIFT           5
44533 #define uSDHC_MMC_BOOT_BOOT_EN_MASK              0x40u
44534 #define uSDHC_MMC_BOOT_BOOT_EN_SHIFT             6
44535 #define uSDHC_MMC_BOOT_AUTO_SABG_EN_MASK         0x80u
44536 #define uSDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        7
44537 #define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     0x100u
44538 #define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    8
44539 #define uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         0xFFFF0000u
44540 #define uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        16
44541 #define uSDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT))&uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
44542 /* VEND_SPEC2 Bit Fields */
44543 #define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK  0x1u
44544 #define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT 0
44545 #define uSDHC_VEND_SPEC2_SDR104_OE_DIS_MASK      0x2u
44546 #define uSDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT     1
44547 #define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK     0x4u
44548 #define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT    2
44549 #define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   0x8u
44550 #define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  3
44551 #define uSDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     0x10u
44552 #define uSDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    4
44553 #define uSDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     0x20u
44554 #define uSDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    5
44555 #define uSDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      0x40u
44556 #define uSDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     6
44557 #define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK 0x80u
44558 #define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT 7
44559 #define uSDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK 0x400u
44560 #define uSDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT 10
44561 #define uSDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK 0x800u
44562 #define uSDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT 11
44563 /* TUNING_CTRL Bit Fields */
44564 #define uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK  0xFFu
44565 #define uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT 0
44566 #define uSDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
44567 #define uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK    0xFF00u
44568 #define uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   8
44569 #define uSDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT))&uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
44570 #define uSDHC_TUNING_CTRL_TUNING_STEP_MASK       0x70000u
44571 #define uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT      16
44572 #define uSDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_STEP_MASK)
44573 #define uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK     0x700000u
44574 #define uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    20
44575 #define uSDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT))&uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
44576 #define uSDHC_TUNING_CTRL_STD_TUNING_EN_MASK     0x1000000u
44577 #define uSDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    24
44578 
44579 /*!
44580  * @}
44581  */ /* end of group uSDHC_Register_Masks */
44582 
44583 /* uSDHC - Peripheral instance base addresses */
44584 /** Peripheral uSDHC1 base address */
44585 #define uSDHC1_BASE                              (0x30B40000u)
44586 /** Peripheral uSDHC1 base pointer */
44587 #define uSDHC1                                   ((uSDHC_Type *)uSDHC1_BASE)
44588 #define uSDHC1_BASE_PTR                          (uSDHC1)
44589 /** Peripheral uSDHC2 base address */
44590 #define uSDHC2_BASE                              (0x30B50000u)
44591 /** Peripheral uSDHC2 base pointer */
44592 #define uSDHC2                                   ((uSDHC_Type *)uSDHC2_BASE)
44593 #define uSDHC2_BASE_PTR                          (uSDHC2)
44594 /** Peripheral uSDHC3 base address */
44595 #define uSDHC3_BASE                              (0x30B60000u)
44596 /** Peripheral uSDHC3 base pointer */
44597 #define uSDHC3                                   ((uSDHC_Type *)uSDHC3_BASE)
44598 #define uSDHC3_BASE_PTR                          (uSDHC3)
44599 /** Array initializer of uSDHC peripheral base addresses */
44600 #define uSDHC_BASE_ADDRS                         { uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE }
44601 /** Array initializer of uSDHC peripheral base pointers */
44602 #define uSDHC_BASE_PTRS                          { uSDHC1, uSDHC2, uSDHC3 }
44603 /** Interrupt vectors for the uSDHC peripheral type */
44604 #define uSDHC_IRQS                               { uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn }
44605 /* ----------------------------------------------------------------------------
44606    -- uSDHC - Register accessor macros
44607    ---------------------------------------------------------------------------- */
44608 
44609 /*!
44610  * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros
44611  * @{
44612  */
44613 
44614 
44615 /* uSDHC - Register instance definitions */
44616 /* uSDHC1 */
44617 #define uSDHC1_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC1_BASE_PTR)
44618 #define uSDHC1_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC1_BASE_PTR)
44619 #define uSDHC1_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC1_BASE_PTR)
44620 #define uSDHC1_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC1_BASE_PTR)
44621 #define uSDHC1_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC1_BASE_PTR)
44622 #define uSDHC1_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC1_BASE_PTR)
44623 #define uSDHC1_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC1_BASE_PTR)
44624 #define uSDHC1_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC1_BASE_PTR)
44625 #define uSDHC1_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC1_BASE_PTR)
44626 #define uSDHC1_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC1_BASE_PTR)
44627 #define uSDHC1_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC1_BASE_PTR)
44628 #define uSDHC1_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC1_BASE_PTR)
44629 #define uSDHC1_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC1_BASE_PTR)
44630 #define uSDHC1_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC1_BASE_PTR)
44631 #define uSDHC1_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC1_BASE_PTR)
44632 #define uSDHC1_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC1_BASE_PTR)
44633 #define uSDHC1_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC1_BASE_PTR)
44634 #define uSDHC1_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC1_BASE_PTR)
44635 #define uSDHC1_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC1_BASE_PTR)
44636 #define uSDHC1_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC1_BASE_PTR)
44637 #define uSDHC1_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC1_BASE_PTR)
44638 #define uSDHC1_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC1_BASE_PTR)
44639 #define uSDHC1_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC1_BASE_PTR)
44640 #define uSDHC1_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC1_BASE_PTR)
44641 #define uSDHC1_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC1_BASE_PTR)
44642 #define uSDHC1_STROBE_DLL_CTRL                   uSDHC_STROBE_DLL_CTRL_REG(uSDHC1_BASE_PTR)
44643 #define uSDHC1_STROBE_DLL_STATUS                 uSDHC_STROBE_DLL_STATUS_REG(uSDHC1_BASE_PTR)
44644 #define uSDHC1_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC1_BASE_PTR)
44645 #define uSDHC1_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC1_BASE_PTR)
44646 #define uSDHC1_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC1_BASE_PTR)
44647 #define uSDHC1_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC1_BASE_PTR)
44648 /* uSDHC2 */
44649 #define uSDHC2_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC2_BASE_PTR)
44650 #define uSDHC2_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC2_BASE_PTR)
44651 #define uSDHC2_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC2_BASE_PTR)
44652 #define uSDHC2_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC2_BASE_PTR)
44653 #define uSDHC2_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC2_BASE_PTR)
44654 #define uSDHC2_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC2_BASE_PTR)
44655 #define uSDHC2_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC2_BASE_PTR)
44656 #define uSDHC2_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC2_BASE_PTR)
44657 #define uSDHC2_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC2_BASE_PTR)
44658 #define uSDHC2_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC2_BASE_PTR)
44659 #define uSDHC2_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC2_BASE_PTR)
44660 #define uSDHC2_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC2_BASE_PTR)
44661 #define uSDHC2_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC2_BASE_PTR)
44662 #define uSDHC2_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC2_BASE_PTR)
44663 #define uSDHC2_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC2_BASE_PTR)
44664 #define uSDHC2_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC2_BASE_PTR)
44665 #define uSDHC2_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC2_BASE_PTR)
44666 #define uSDHC2_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC2_BASE_PTR)
44667 #define uSDHC2_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC2_BASE_PTR)
44668 #define uSDHC2_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC2_BASE_PTR)
44669 #define uSDHC2_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC2_BASE_PTR)
44670 #define uSDHC2_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC2_BASE_PTR)
44671 #define uSDHC2_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC2_BASE_PTR)
44672 #define uSDHC2_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC2_BASE_PTR)
44673 #define uSDHC2_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC2_BASE_PTR)
44674 #define uSDHC2_STROBE_DLL_CTRL                   uSDHC_STROBE_DLL_CTRL_REG(uSDHC2_BASE_PTR)
44675 #define uSDHC2_STROBE_DLL_STATUS                 uSDHC_STROBE_DLL_STATUS_REG(uSDHC2_BASE_PTR)
44676 #define uSDHC2_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC2_BASE_PTR)
44677 #define uSDHC2_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC2_BASE_PTR)
44678 #define uSDHC2_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC2_BASE_PTR)
44679 #define uSDHC2_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC2_BASE_PTR)
44680 /* uSDHC3 */
44681 #define uSDHC3_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC3_BASE_PTR)
44682 #define uSDHC3_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC3_BASE_PTR)
44683 #define uSDHC3_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC3_BASE_PTR)
44684 #define uSDHC3_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC3_BASE_PTR)
44685 #define uSDHC3_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC3_BASE_PTR)
44686 #define uSDHC3_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC3_BASE_PTR)
44687 #define uSDHC3_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC3_BASE_PTR)
44688 #define uSDHC3_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC3_BASE_PTR)
44689 #define uSDHC3_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC3_BASE_PTR)
44690 #define uSDHC3_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC3_BASE_PTR)
44691 #define uSDHC3_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC3_BASE_PTR)
44692 #define uSDHC3_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC3_BASE_PTR)
44693 #define uSDHC3_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC3_BASE_PTR)
44694 #define uSDHC3_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC3_BASE_PTR)
44695 #define uSDHC3_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC3_BASE_PTR)
44696 #define uSDHC3_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC3_BASE_PTR)
44697 #define uSDHC3_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC3_BASE_PTR)
44698 #define uSDHC3_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC3_BASE_PTR)
44699 #define uSDHC3_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC3_BASE_PTR)
44700 #define uSDHC3_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC3_BASE_PTR)
44701 #define uSDHC3_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC3_BASE_PTR)
44702 #define uSDHC3_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC3_BASE_PTR)
44703 #define uSDHC3_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC3_BASE_PTR)
44704 #define uSDHC3_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC3_BASE_PTR)
44705 #define uSDHC3_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC3_BASE_PTR)
44706 #define uSDHC3_STROBE_DLL_CTRL                   uSDHC_STROBE_DLL_CTRL_REG(uSDHC3_BASE_PTR)
44707 #define uSDHC3_STROBE_DLL_STATUS                 uSDHC_STROBE_DLL_STATUS_REG(uSDHC3_BASE_PTR)
44708 #define uSDHC3_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC3_BASE_PTR)
44709 #define uSDHC3_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC3_BASE_PTR)
44710 #define uSDHC3_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC3_BASE_PTR)
44711 #define uSDHC3_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC3_BASE_PTR)
44712 /*!
44713  * @}
44714  */ /* end of group uSDHC_Register_Accessor_Macros */
44715 
44716 
44717 /*!
44718  * @}
44719  */ /* end of group uSDHC_Peripheral */
44720 
44721 /*
44722 ** End of section using anonymous unions
44723 */
44724 
44725 #if defined(__ARMCC_VERSION)
44726   #pragma pop
44727 #elif defined(__GNUC__)
44728   /* leave anonymous unions enabled */
44729 #elif defined(__IAR_SYSTEMS_ICC__)
44730   #pragma language=default
44731 #else
44732   #error Not supported compiler type
44733 #endif
44734 
44735 /*!
44736  * @}
44737  */ /* end of group Peripheral_defines */
44738 
44739 
44740 /* ----------------------------------------------------------------------------
44741    -- Backward Compatibility
44742    ---------------------------------------------------------------------------- */
44743 
44744 /*!
44745  * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
44746  * @{
44747  */
44748 
44749 /* No backward compatibility issues. */
44750 
44751 /*!
44752  * @}
44753  */ /* end of group Backward_Compatibility_Symbols */
44754 
44755 #else /* #if !defined(MCU_MCIMX7D) */
44756   /* There is already included the same memory map. Check if it is compatible (has the same major version) */
44757   #if (MCU_MEM_MAP_VERSION != 0x0100u)
44758     #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
44759       #warning There are included two not compatible versions of memory maps. Please check possible differences.
44760     #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
44761   #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
44762 
44763 #endif  /* #if !defined(MCU_MCIMX7D) */
44764 
44765 /* MCIMX7D_M4.h, eof. */
44766