1 /****************************************************************************** 2 * Filename: hw_pmud_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_PMUD_H__ 34 #define __HW_PMUD_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // PMUD component 40 // 41 //***************************************************************************** 42 // Control 43 #define PMUD_O_CTL 0x00000000U 44 45 // Internal. Only to be used through TI provided API. 46 #define PMUD_O_MEASCFG 0x00000004U 47 48 // Last Measured Battery Voltage 49 #define PMUD_O_BAT 0x00000028U 50 51 // Battery Update 52 #define PMUD_O_BATUPD 0x0000002CU 53 54 // Last measured Temperature in Degree Celsius 55 #define PMUD_O_TEMP 0x00000030U 56 57 // Temperature Update 58 #define PMUD_O_TEMPUPD 0x00000034U 59 60 // Event Mask 61 #define PMUD_O_EVENTMASK 0x00000048U 62 63 // Event 64 #define PMUD_O_EVENT 0x0000004CU 65 66 // Battery Upper Limit 67 #define PMUD_O_BATTUL 0x00000050U 68 69 // Battery Lower Limit 70 #define PMUD_O_BATTLL 0x00000054U 71 72 // Temperature Upper Limit 73 #define PMUD_O_TEMPUL 0x00000058U 74 75 // Temperature Lower Limit 76 #define PMUD_O_TEMPLL 0x0000005CU 77 78 // Internal. Only to be used through TI provided API. 79 #define PMUD_O_PREFSYS 0x00000080U 80 81 // Internal. Only to be used through TI provided API. 82 #define PMUD_O_PREG0 0x00000090U 83 84 // Internal. Only to be used through TI provided API. 85 #define PMUD_O_PREG1 0x00000094U 86 87 // Internal. Only to be used through TI provided API. 88 #define PMUD_O_PREG2 0x00000098U 89 90 // DCDC configuration 91 #define PMUD_O_DCDCCFG 0x0000009CU 92 93 // DCDC status 94 #define PMUD_O_DCDCSTAT 0x000000A0U 95 96 //***************************************************************************** 97 // 98 // Register: PMUD_O_CTL 99 // 100 //***************************************************************************** 101 // Field: [2] HYST_EN 102 // 103 // Enables hysteresis on both battery and temperature measurements. 104 // ENUMs: 105 // EN Enable 106 // DIS Disable 107 #define PMUD_CTL_HYST_EN 0x00000004U 108 #define PMUD_CTL_HYST_EN_M 0x00000004U 109 #define PMUD_CTL_HYST_EN_S 2U 110 #define PMUD_CTL_HYST_EN_EN 0x00000004U 111 #define PMUD_CTL_HYST_EN_DIS 0x00000000U 112 113 // Field: [1] CALC_EN 114 // 115 // Configuration of the calculation block that converts the digital 116 // battery/temperature level to a Volt/Celsius value. 117 // ENUMs: 118 // EN Calculation enabled 119 // DIS Calculation disabled 120 #define PMUD_CTL_CALC_EN 0x00000002U 121 #define PMUD_CTL_CALC_EN_M 0x00000002U 122 #define PMUD_CTL_CALC_EN_S 1U 123 #define PMUD_CTL_CALC_EN_EN 0x00000002U 124 #define PMUD_CTL_CALC_EN_DIS 0x00000000U 125 126 // Field: [0] MEAS_EN 127 // 128 // Configuration of the measurement block that interfaces with the analog 129 // domain. 130 // ENUMs: 131 // EN Measurements enabled (battery voltage and 132 // temperature) 133 // DIS Measurements disabled 134 #define PMUD_CTL_MEAS_EN 0x00000001U 135 #define PMUD_CTL_MEAS_EN_M 0x00000001U 136 #define PMUD_CTL_MEAS_EN_S 0U 137 #define PMUD_CTL_MEAS_EN_EN 0x00000001U 138 #define PMUD_CTL_MEAS_EN_DIS 0x00000000U 139 140 //***************************************************************************** 141 // 142 // Register: PMUD_O_MEASCFG 143 // 144 //***************************************************************************** 145 // Field: [1:0] PER 146 // 147 // Internal. Only to be used through TI provided API. 148 // ENUMs: 149 // _32CYC Internal. Only to be used through TI provided API. 150 // _16CYC Internal. Only to be used through TI provided API. 151 // _8CYC Internal. Only to be used through TI provided API. 152 // CONT Internal. Only to be used through TI provided API. 153 #define PMUD_MEASCFG_PER_W 2U 154 #define PMUD_MEASCFG_PER_M 0x00000003U 155 #define PMUD_MEASCFG_PER_S 0U 156 #define PMUD_MEASCFG_PER__32CYC 0x00000003U 157 #define PMUD_MEASCFG_PER__16CYC 0x00000002U 158 #define PMUD_MEASCFG_PER__8CYC 0x00000001U 159 #define PMUD_MEASCFG_PER_CONT 0x00000000U 160 161 //***************************************************************************** 162 // 163 // Register: PMUD_O_BAT 164 // 165 //***************************************************************************** 166 // Field: [10:8] INT 167 // 168 // Integer part: 169 // 170 // 0x0: Battery voltage = 0V + fractional part 171 // ... 172 // 0x3: Battery voltage = 3V + fractional part 173 // 0x4: Battery voltage = 4V + fractional part 174 #define PMUD_BAT_INT_W 3U 175 #define PMUD_BAT_INT_M 0x00000700U 176 #define PMUD_BAT_INT_S 8U 177 178 // Field: [7:0] FRAC 179 // 180 // Fractional part, standard binary fractional encoding. 181 // 182 // 0x00: .0V 183 // ... 184 // 0x20: 1/8 = .125V 185 // 0x40: 1/4 = .25V 186 // 0x80: 1/2 = .5V 187 // ... 188 // 0xA0: 1/2 + 1/8 = .625V 189 // ... 190 // 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V 191 #define PMUD_BAT_FRAC_W 8U 192 #define PMUD_BAT_FRAC_M 0x000000FFU 193 #define PMUD_BAT_FRAC_S 0U 194 195 //***************************************************************************** 196 // 197 // Register: PMUD_O_BATUPD 198 // 199 //***************************************************************************** 200 // Field: [0] STA 201 // 202 // Battery update status. Write 1 to clear the status. 203 // ENUMs: 204 // UPD New battery voltage present 205 // NOUPD No update since last clear 206 #define PMUD_BATUPD_STA 0x00000001U 207 #define PMUD_BATUPD_STA_M 0x00000001U 208 #define PMUD_BATUPD_STA_S 0U 209 #define PMUD_BATUPD_STA_UPD 0x00000001U 210 #define PMUD_BATUPD_STA_NOUPD 0x00000000U 211 212 //***************************************************************************** 213 // 214 // Register: PMUD_O_TEMP 215 // 216 //***************************************************************************** 217 // Field: [16:8] INT 218 // 219 // Integer part of temperature value (signed) 220 // Total value = INT + FRAC 221 // 2's complement encoding 222 // 223 // 0x100: Min value (-256°C) 224 // 0x1D8: -40°C 225 // 0x1FF: -1°C 226 // 0x00: 0°C 227 // 0x1B: 27°C 228 // 0x55: 85°C 229 // 0xFF: Max value (255°C) 230 #define PMUD_TEMP_INT_W 9U 231 #define PMUD_TEMP_INT_M 0x0001FF00U 232 #define PMUD_TEMP_INT_S 8U 233 234 // Field: [7:6] FRAC 235 // 236 // Fractional part of temperature value. 237 // Total value = INT + FRAC 238 // The encoding is an extension of the 2's complement encoding. 239 // 240 // 00: 0.0°C 241 // 01: 0.25°C 242 // 10: 0.5°C 243 // 11: 0.75°C 244 // 245 // For example: 246 // 000000001,00 = ( 1+0,00) = 1,00 247 // 000000000,11 = ( 0+0,75) = 0,75 248 // 000000000,10 = ( 0+0,50) = 0,50 249 // 000000000,01 = ( 0+0,25) = 0,25 250 // 000000000,00 = ( 0+0,00) = 0,00 251 // 111111111,11 = (-1+0,75) = -0,25 252 // 111111111,10 = (-1+0,50) = -0,50 253 // 111111111,01 = (-1+0,25) = -0,75 254 // 111111111,00 = (-1+0,00) = -1,00 255 // 111111110,11 = (-2+0,75) = -1,25 256 #define PMUD_TEMP_FRAC_W 2U 257 #define PMUD_TEMP_FRAC_M 0x000000C0U 258 #define PMUD_TEMP_FRAC_S 6U 259 260 //***************************************************************************** 261 // 262 // Register: PMUD_O_TEMPUPD 263 // 264 //***************************************************************************** 265 // Field: [0] STA 266 // 267 // Temperature update status. Write 1 to clear the status. 268 // ENUMs: 269 // UPD New temperature value present 270 // NOUPD No temperature update since last clear 271 #define PMUD_TEMPUPD_STA 0x00000001U 272 #define PMUD_TEMPUPD_STA_M 0x00000001U 273 #define PMUD_TEMPUPD_STA_S 0U 274 #define PMUD_TEMPUPD_STA_UPD 0x00000001U 275 #define PMUD_TEMPUPD_STA_NOUPD 0x00000000U 276 277 //***************************************************************************** 278 // 279 // Register: PMUD_O_EVENTMASK 280 // 281 //***************************************************************************** 282 // Field: [5] TEMP_UPDATE_MASK 283 // 284 // 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON 285 // 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON 286 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK 0x00000020U 287 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020U 288 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK_S 5U 289 290 // Field: [4] BATT_UPDATE_MASK 291 // 292 // 1: EVENT.BATT_UPDATE contributes to combined event from BATMON 293 // 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON 294 #define PMUD_EVENTMASK_BATT_UPDATE_MASK 0x00000010U 295 #define PMUD_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010U 296 #define PMUD_EVENTMASK_BATT_UPDATE_MASK_S 4U 297 298 // Field: [3] TEMP_BELOW_LL_MASK 299 // 300 // 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON 301 // 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON 302 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008U 303 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008U 304 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_S 3U 305 306 // Field: [2] TEMP_OVER_UL_MASK 307 // 308 // 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON 309 // 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON 310 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004U 311 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004U 312 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_S 2U 313 314 // Field: [1] BATT_BELOW_LL_MASK 315 // 316 // 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON 317 // 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON 318 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002U 319 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002U 320 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_S 1U 321 322 // Field: [0] BATT_OVER_UL_MASK 323 // 324 // 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON 325 // 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON 326 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK 0x00000001U 327 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001U 328 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK_S 0U 329 330 //***************************************************************************** 331 // 332 // Register: PMUD_O_EVENT 333 // 334 //***************************************************************************** 335 // Field: [5] TEMP_UPDATE 336 // 337 // Alias to TEMPUPD.STA 338 #define PMUD_EVENT_TEMP_UPDATE 0x00000020U 339 #define PMUD_EVENT_TEMP_UPDATE_M 0x00000020U 340 #define PMUD_EVENT_TEMP_UPDATE_S 5U 341 342 // Field: [4] BATT_UPDATE 343 // 344 // Alias to BATUPD.STA 345 #define PMUD_EVENT_BATT_UPDATE 0x00000010U 346 #define PMUD_EVENT_BATT_UPDATE_M 0x00000010U 347 #define PMUD_EVENT_BATT_UPDATE_S 4U 348 349 // Field: [3] TEMP_BELOW_LL 350 // 351 // Read: 352 // 1: Temperature level is below the lower limit set by TEMPLL. 353 // 0: Temperature level is not below the lower limit set by TEMPLL. 354 // Write: 355 // 1: Clears the flag 356 // 0: No change in the flag 357 #define PMUD_EVENT_TEMP_BELOW_LL 0x00000008U 358 #define PMUD_EVENT_TEMP_BELOW_LL_M 0x00000008U 359 #define PMUD_EVENT_TEMP_BELOW_LL_S 3U 360 361 // Field: [2] TEMP_OVER_UL 362 // 363 // Read: 364 // 1: Temperature level is above the upper limit set by TEMPUL. 365 // 0: Temperature level is not above the upper limit set by TEMPUL. 366 // Write: 367 // 1: Clears the flag 368 // 0: No change in the flag 369 #define PMUD_EVENT_TEMP_OVER_UL 0x00000004U 370 #define PMUD_EVENT_TEMP_OVER_UL_M 0x00000004U 371 #define PMUD_EVENT_TEMP_OVER_UL_S 2U 372 373 // Field: [1] BATT_BELOW_LL 374 // 375 // Read: 376 // 1: Battery level is below the lower limit set by BATTLL. 377 // 0: Battery level is not below the lower limit set by BATTLL. 378 // Write: 379 // 1: Clears the flag 380 // 0: No change in the flag 381 #define PMUD_EVENT_BATT_BELOW_LL 0x00000002U 382 #define PMUD_EVENT_BATT_BELOW_LL_M 0x00000002U 383 #define PMUD_EVENT_BATT_BELOW_LL_S 1U 384 385 // Field: [0] BATT_OVER_UL 386 // 387 // Read: 388 // 1: Battery level is above the upper limit set by BATTUL. 389 // 0: Battery level is not above the upper limit set by BATTUL. 390 // Write: 391 // 1: Clears the flag 392 // 0: No change in the flag 393 #define PMUD_EVENT_BATT_OVER_UL 0x00000001U 394 #define PMUD_EVENT_BATT_OVER_UL_M 0x00000001U 395 #define PMUD_EVENT_BATT_OVER_UL_S 0U 396 397 //***************************************************************************** 398 // 399 // Register: PMUD_O_BATTUL 400 // 401 //***************************************************************************** 402 // Field: [10:8] INT 403 // 404 // Integer part: 405 // Total battery voltage = INT + FRAC (integer and fractional part) 406 // 407 // 0x0: Battery voltage = 0V + fractional part 408 // ... 409 // 0x3: Battery voltage = 3V + fractional part 410 // 0x4: Battery voltage = 4V + fractional part 411 #define PMUD_BATTUL_INT_W 3U 412 #define PMUD_BATTUL_INT_M 0x00000700U 413 #define PMUD_BATTUL_INT_S 8U 414 415 // Field: [7:0] FRAC 416 // 417 // Fractional part, standard binary fractional encoding. 418 // 419 // 0x00: .0V 420 // ... 421 // 0x20: 1/8 = .125V 422 // 0x40: 1/4 = .25V 423 // 0x80: 1/2 = .5V 424 // ... 425 // 0xA0: 1/2 + 1/8 = .625V 426 // ... 427 // 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V 428 #define PMUD_BATTUL_FRAC_W 8U 429 #define PMUD_BATTUL_FRAC_M 0x000000FFU 430 #define PMUD_BATTUL_FRAC_S 0U 431 432 //***************************************************************************** 433 // 434 // Register: PMUD_O_BATTLL 435 // 436 //***************************************************************************** 437 // Field: [10:8] INT 438 // 439 // Integer part: 440 // Total battery voltage = INT + FRAC (integer and fractional part) 441 // 442 // 0x0: Battery voltage = 0V + fractional part 443 // ... 444 // 0x3: Battery voltage = 3V + fractional part 445 // 0x4: Battery voltage = 4V + fractional part 446 #define PMUD_BATTLL_INT_W 3U 447 #define PMUD_BATTLL_INT_M 0x00000700U 448 #define PMUD_BATTLL_INT_S 8U 449 450 // Field: [7:0] FRAC 451 // 452 // Fractional part, standard binary fractional encoding. 453 // 454 // 0x00: .0V 455 // ... 456 // 0x20: 1/8 = .125V 457 // 0x40: 1/4 = .25V 458 // 0x80: 1/2 = .5V 459 // ... 460 // 0xA0: 1/2 + 1/8 = .625V 461 // ... 462 // 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V 463 #define PMUD_BATTLL_FRAC_W 8U 464 #define PMUD_BATTLL_FRAC_M 0x000000FFU 465 #define PMUD_BATTLL_FRAC_S 0U 466 467 //***************************************************************************** 468 // 469 // Register: PMUD_O_TEMPUL 470 // 471 //***************************************************************************** 472 // Field: [16:8] INT 473 // 474 // Integer part (signed) of temperature upper limit. 475 // Total value = INT + FRAC 476 // 2's complement encoding 477 // 478 // 0x100: Min value (-256°C) 479 // 0x1D8: -40°C 480 // 0x1FF: -1°C 481 // 0x00: 0°C 482 // 0x1B: 27°C 483 // 0x55: 85°C 484 // 0xFF: Max value (255°C) 485 #define PMUD_TEMPUL_INT_W 9U 486 #define PMUD_TEMPUL_INT_M 0x0001FF00U 487 #define PMUD_TEMPUL_INT_S 8U 488 489 // Field: [7:6] FRAC 490 // 491 // Fractional part of temperature upper limit. 492 // Total value = INT + FRAC 493 // The encoding is an extension of the 2's complement encoding. 494 // 495 // 00: 0.0°C 496 // 01: 0.25°C 497 // 10: 0.5°C 498 // 11: 0.75°C 499 // 500 // For example: 501 // 000000001,00 = ( 1+0,00) = 1,00 502 // 000000000,11 = ( 0+0,75) = 0,75 503 // 000000000,10 = ( 0+0,50) = 0,50 504 // 000000000,01 = ( 0+0,25) = 0,25 505 // 000000000,00 = ( 0+0,00) = 0,00 506 // 111111111,11 = (-1+0,75) = -0,25 507 // 111111111,10 = (-1+0,50) = -0,50 508 // 111111111,01 = (-1+0,25) = -0,75 509 // 111111111,00 = (-1+0,00) = -1,00 510 // 111111110,11 = (-2+0,75) = -1,25 511 #define PMUD_TEMPUL_FRAC_W 2U 512 #define PMUD_TEMPUL_FRAC_M 0x000000C0U 513 #define PMUD_TEMPUL_FRAC_S 6U 514 515 //***************************************************************************** 516 // 517 // Register: PMUD_O_TEMPLL 518 // 519 //***************************************************************************** 520 // Field: [16:8] INT 521 // 522 // Integer part (signed) of temperature lower limit. 523 // Total value = INT + FRAC 524 // 2's complement encoding 525 // 526 // 0x100: Min value (-256°C) 527 // 0x1D8: -40°C 528 // 0x1FF: -1°C 529 // 0x00: 0°C 530 // 0x1B: 27°C 531 // 0x55: 85°C 532 // 0xFF: Max value (255°C) 533 #define PMUD_TEMPLL_INT_W 9U 534 #define PMUD_TEMPLL_INT_M 0x0001FF00U 535 #define PMUD_TEMPLL_INT_S 8U 536 537 // Field: [7:6] FRAC 538 // 539 // Fractional part of temperature lower limit. 540 // Total value = INT + FRAC 541 // The encoding is an extension of the 2's complement encoding. 542 // 543 // 00: 0.0°C 544 // 01: 0.25°C 545 // 10: 0.5°C 546 // 11: 0.75°C 547 // 548 // For example: 549 // 000000001,00 = ( 1+0,00) = 1,00 550 // 000000000,11 = ( 0+0,75) = 0,75 551 // 000000000,10 = ( 0+0,50) = 0,50 552 // 000000000,01 = ( 0+0,25) = 0,25 553 // 000000000,00 = ( 0+0,00) = 0,00 554 // 111111111,11 = (-1+0,75) = -0,25 555 // 111111111,10 = (-1+0,50) = -0,50 556 // 111111111,01 = (-1+0,25) = -0,75 557 // 111111111,00 = (-1+0,00) = -1,00 558 // 111111110,11 = (-2+0,75) = -1,25 559 #define PMUD_TEMPLL_FRAC_W 2U 560 #define PMUD_TEMPLL_FRAC_M 0x000000C0U 561 #define PMUD_TEMPLL_FRAC_S 6U 562 563 //***************************************************************************** 564 // 565 // Register: PMUD_O_PREFSYS 566 // 567 //***************************************************************************** 568 // Field: [15:11] SPARE 569 // 570 // Internal. Only to be used through TI provided API. 571 #define PMUD_PREFSYS_SPARE_W 5U 572 #define PMUD_PREFSYS_SPARE_M 0x0000F800U 573 #define PMUD_PREFSYS_SPARE_S 11U 574 575 // Field: [10] TEST10 576 // 577 // Internal. Only to be used through TI provided API. 578 // ENUMs: 579 // SET Internal. Only to be used through TI provided API. 580 // CLR Internal. Only to be used through TI provided API. 581 #define PMUD_PREFSYS_TEST10 0x00000400U 582 #define PMUD_PREFSYS_TEST10_M 0x00000400U 583 #define PMUD_PREFSYS_TEST10_S 10U 584 #define PMUD_PREFSYS_TEST10_SET 0x00000400U 585 #define PMUD_PREFSYS_TEST10_CLR 0x00000000U 586 587 // Field: [9] TEST9 588 // 589 // Internal. Only to be used through TI provided API. 590 // ENUMs: 591 // SET Internal. Only to be used through TI provided API. 592 // CLR Internal. Only to be used through TI provided API. 593 #define PMUD_PREFSYS_TEST9 0x00000200U 594 #define PMUD_PREFSYS_TEST9_M 0x00000200U 595 #define PMUD_PREFSYS_TEST9_S 9U 596 #define PMUD_PREFSYS_TEST9_SET 0x00000200U 597 #define PMUD_PREFSYS_TEST9_CLR 0x00000000U 598 599 // Field: [8] TEST8 600 // 601 // Internal. Only to be used through TI provided API. 602 // ENUMs: 603 // SET Internal. Only to be used through TI provided API. 604 // CLR Internal. Only to be used through TI provided API. 605 #define PMUD_PREFSYS_TEST8 0x00000100U 606 #define PMUD_PREFSYS_TEST8_M 0x00000100U 607 #define PMUD_PREFSYS_TEST8_S 8U 608 #define PMUD_PREFSYS_TEST8_SET 0x00000100U 609 #define PMUD_PREFSYS_TEST8_CLR 0x00000000U 610 611 // Field: [7] TEST7 612 // 613 // Internal. Only to be used through TI provided API. 614 // ENUMs: 615 // SET Internal. Only to be used through TI provided API. 616 // CLR Internal. Only to be used through TI provided API. 617 #define PMUD_PREFSYS_TEST7 0x00000080U 618 #define PMUD_PREFSYS_TEST7_M 0x00000080U 619 #define PMUD_PREFSYS_TEST7_S 7U 620 #define PMUD_PREFSYS_TEST7_SET 0x00000080U 621 #define PMUD_PREFSYS_TEST7_CLR 0x00000000U 622 623 // Field: [6] TEST6 624 // 625 // Internal. Only to be used through TI provided API. 626 // ENUMs: 627 // SET Internal. Only to be used through TI provided API. 628 // CLR Internal. Only to be used through TI provided API. 629 #define PMUD_PREFSYS_TEST6 0x00000040U 630 #define PMUD_PREFSYS_TEST6_M 0x00000040U 631 #define PMUD_PREFSYS_TEST6_S 6U 632 #define PMUD_PREFSYS_TEST6_SET 0x00000040U 633 #define PMUD_PREFSYS_TEST6_CLR 0x00000000U 634 635 // Field: [5] TEST5 636 // 637 // Internal. Only to be used through TI provided API. 638 // ENUMs: 639 // SET Internal. Only to be used through TI provided API. 640 // CLR Internal. Only to be used through TI provided API. 641 #define PMUD_PREFSYS_TEST5 0x00000020U 642 #define PMUD_PREFSYS_TEST5_M 0x00000020U 643 #define PMUD_PREFSYS_TEST5_S 5U 644 #define PMUD_PREFSYS_TEST5_SET 0x00000020U 645 #define PMUD_PREFSYS_TEST5_CLR 0x00000000U 646 647 // Field: [4] TEST4 648 // 649 // Internal. Only to be used through TI provided API. 650 // ENUMs: 651 // SET Internal. Only to be used through TI provided API. 652 // CLR Internal. Only to be used through TI provided API. 653 #define PMUD_PREFSYS_TEST4 0x00000010U 654 #define PMUD_PREFSYS_TEST4_M 0x00000010U 655 #define PMUD_PREFSYS_TEST4_S 4U 656 #define PMUD_PREFSYS_TEST4_SET 0x00000010U 657 #define PMUD_PREFSYS_TEST4_CLR 0x00000000U 658 659 // Field: [3] TEST3 660 // 661 // Internal. Only to be used through TI provided API. 662 // ENUMs: 663 // SET Internal. Only to be used through TI provided API. 664 // CLR Internal. Only to be used through TI provided API. 665 #define PMUD_PREFSYS_TEST3 0x00000008U 666 #define PMUD_PREFSYS_TEST3_M 0x00000008U 667 #define PMUD_PREFSYS_TEST3_S 3U 668 #define PMUD_PREFSYS_TEST3_SET 0x00000008U 669 #define PMUD_PREFSYS_TEST3_CLR 0x00000000U 670 671 // Field: [2] TEST2 672 // 673 // Internal. Only to be used through TI provided API. 674 // ENUMs: 675 // SET Internal. Only to be used through TI provided API. 676 // CLR Internal. Only to be used through TI provided API. 677 #define PMUD_PREFSYS_TEST2 0x00000004U 678 #define PMUD_PREFSYS_TEST2_M 0x00000004U 679 #define PMUD_PREFSYS_TEST2_S 2U 680 #define PMUD_PREFSYS_TEST2_SET 0x00000004U 681 #define PMUD_PREFSYS_TEST2_CLR 0x00000000U 682 683 // Field: [1] TEST1 684 // 685 // Internal. Only to be used through TI provided API. 686 // ENUMs: 687 // SET Internal. Only to be used through TI provided API. 688 // CLR Internal. Only to be used through TI provided API. 689 #define PMUD_PREFSYS_TEST1 0x00000002U 690 #define PMUD_PREFSYS_TEST1_M 0x00000002U 691 #define PMUD_PREFSYS_TEST1_S 1U 692 #define PMUD_PREFSYS_TEST1_SET 0x00000002U 693 #define PMUD_PREFSYS_TEST1_CLR 0x00000000U 694 695 // Field: [0] TEST0 696 // 697 // Internal. Only to be used through TI provided API. 698 // ENUMs: 699 // SET Internal. Only to be used through TI provided API. 700 // CLR Internal. Only to be used through TI provided API. 701 #define PMUD_PREFSYS_TEST0 0x00000001U 702 #define PMUD_PREFSYS_TEST0_M 0x00000001U 703 #define PMUD_PREFSYS_TEST0_S 0U 704 #define PMUD_PREFSYS_TEST0_SET 0x00000001U 705 #define PMUD_PREFSYS_TEST0_CLR 0x00000000U 706 707 //***************************************************************************** 708 // 709 // Register: PMUD_O_PREG0 710 // 711 //***************************************************************************** 712 // Field: [11] LOW_IPEAK_DIS 713 // 714 // Internal. Only to be used through TI provided API. 715 // ENUMs: 716 // SET Internal. Only to be used through TI provided API. 717 // CLR Internal. Only to be used through TI provided API. 718 #define PMUD_PREG0_LOW_IPEAK_DIS 0x00000800U 719 #define PMUD_PREG0_LOW_IPEAK_DIS_M 0x00000800U 720 #define PMUD_PREG0_LOW_IPEAK_DIS_S 11U 721 #define PMUD_PREG0_LOW_IPEAK_DIS_SET 0x00000800U 722 #define PMUD_PREG0_LOW_IPEAK_DIS_CLR 0x00000000U 723 724 // Field: [10] SOCLDO_ITESTEN 725 // 726 // Internal. Only to be used through TI provided API. 727 // ENUMs: 728 // EN Internal. Only to be used through TI provided API. 729 // DIS Internal. Only to be used through TI provided API. 730 #define PMUD_PREG0_SOCLDO_ITESTEN 0x00000400U 731 #define PMUD_PREG0_SOCLDO_ITESTEN_M 0x00000400U 732 #define PMUD_PREG0_SOCLDO_ITESTEN_S 10U 733 #define PMUD_PREG0_SOCLDO_ITESTEN_EN 0x00000400U 734 #define PMUD_PREG0_SOCLDO_ITESTEN_DIS 0x00000000U 735 736 // Field: [9:7] SOCLDO_ATBSEL 737 // 738 // Internal. Only to be used through TI provided API. 739 // ENUMs: 740 // VDD_AON Internal. Only to be used through TI provided API. 741 // SOCLDO_VREF_AMP_OUT Internal. Only to be used through TI provided API. 742 // SOCLDO_ITEST Internal. Only to be used through TI provided API. 743 // NC Internal. Only to be used through TI provided API. 744 #define PMUD_PREG0_SOCLDO_ATBSEL_W 3U 745 #define PMUD_PREG0_SOCLDO_ATBSEL_M 0x00000380U 746 #define PMUD_PREG0_SOCLDO_ATBSEL_S 7U 747 #define PMUD_PREG0_SOCLDO_ATBSEL_VDD_AON 0x00000200U 748 #define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_VREF_AMP_OUT 0x00000100U 749 #define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_ITEST 0x00000080U 750 #define PMUD_PREG0_SOCLDO_ATBSEL_NC 0x00000000U 751 752 // Field: [6:5] UDIGLDO_ATBSEL 753 // 754 // Internal. Only to be used through TI provided API. 755 // ENUMs: 756 // VAL3 Internal. Only to be used through TI provided API. 757 // VAL2 Internal. Only to be used through TI provided API. 758 // VAL1 Internal. Only to be used through TI provided API. 759 // VAL0 Internal. Only to be used through TI provided API. 760 #define PMUD_PREG0_UDIGLDO_ATBSEL_W 2U 761 #define PMUD_PREG0_UDIGLDO_ATBSEL_M 0x00000060U 762 #define PMUD_PREG0_UDIGLDO_ATBSEL_S 5U 763 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL3 0x00000060U 764 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL2 0x00000040U 765 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL1 0x00000020U 766 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL0 0x00000000U 767 768 // Field: [4:2] DIGLDO_ATBSEL 769 // 770 // Internal. Only to be used through TI provided API. 771 // ENUMs: 772 // VAL4 Internal. Only to be used through TI provided API. 773 // VAL2 Internal. Only to be used through TI provided API. 774 // VAL1 Internal. Only to be used through TI provided API. 775 // VAL0 Internal. Only to be used through TI provided API. 776 #define PMUD_PREG0_DIGLDO_ATBSEL_W 3U 777 #define PMUD_PREG0_DIGLDO_ATBSEL_M 0x0000001CU 778 #define PMUD_PREG0_DIGLDO_ATBSEL_S 2U 779 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL4 0x00000010U 780 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL2 0x00000008U 781 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL1 0x00000004U 782 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL0 0x00000000U 783 784 // Field: [1] SPARE 785 // 786 // Internal. Only to be used through TI provided API. 787 #define PMUD_PREG0_SPARE 0x00000002U 788 #define PMUD_PREG0_SPARE_M 0x00000002U 789 #define PMUD_PREG0_SPARE_S 1U 790 791 // Field: [0] UDIGLDO_EN 792 // 793 // Internal. Only to be used through TI provided API. 794 // ENUMs: 795 // EN Internal. Only to be used through TI provided API. 796 // DIS Internal. Only to be used through TI provided API. 797 #define PMUD_PREG0_UDIGLDO_EN 0x00000001U 798 #define PMUD_PREG0_UDIGLDO_EN_M 0x00000001U 799 #define PMUD_PREG0_UDIGLDO_EN_S 0U 800 #define PMUD_PREG0_UDIGLDO_EN_EN 0x00000001U 801 #define PMUD_PREG0_UDIGLDO_EN_DIS 0x00000000U 802 803 //***************************************************************************** 804 // 805 // Register: PMUD_O_PREG1 806 // 807 //***************************************************************************** 808 // Field: [19] TEST_DCDC_NMOS 809 // 810 // Internal. Only to be used through TI provided API. 811 // ENUMs: 812 // EN Internal. Only to be used through TI provided API. 813 // DIS Internal. Only to be used through TI provided API. 814 #define PMUD_PREG1_TEST_DCDC_NMOS 0x00080000U 815 #define PMUD_PREG1_TEST_DCDC_NMOS_M 0x00080000U 816 #define PMUD_PREG1_TEST_DCDC_NMOS_S 19U 817 #define PMUD_PREG1_TEST_DCDC_NMOS_EN 0x00080000U 818 #define PMUD_PREG1_TEST_DCDC_NMOS_DIS 0x00000000U 819 820 // Field: [18] TEST_DCDC_PMOS 821 // 822 // Internal. Only to be used through TI provided API. 823 // ENUMs: 824 // EN Internal. Only to be used through TI provided API. 825 // DIS Internal. Only to be used through TI provided API. 826 #define PMUD_PREG1_TEST_DCDC_PMOS 0x00040000U 827 #define PMUD_PREG1_TEST_DCDC_PMOS_M 0x00040000U 828 #define PMUD_PREG1_TEST_DCDC_PMOS_S 18U 829 #define PMUD_PREG1_TEST_DCDC_PMOS_EN 0x00040000U 830 #define PMUD_PREG1_TEST_DCDC_PMOS_DIS 0x00000000U 831 832 // Field: [17] DITHER_EN 833 // 834 // Internal. Only to be used through TI provided API. 835 // ENUMs: 836 // EN Internal. Only to be used through TI provided API. 837 // DIS Internal. Only to be used through TI provided API. 838 #define PMUD_PREG1_DITHER_EN 0x00020000U 839 #define PMUD_PREG1_DITHER_EN_M 0x00020000U 840 #define PMUD_PREG1_DITHER_EN_S 17U 841 #define PMUD_PREG1_DITHER_EN_EN 0x00020000U 842 #define PMUD_PREG1_DITHER_EN_DIS 0x00000000U 843 844 // Field: [16] GLDO_AON 845 // 846 // Internal. Only to be used through TI provided API. 847 // ENUMs: 848 // EN Internal. Only to be used through TI provided API. 849 // DIS Internal. Only to be used through TI provided API. 850 #define PMUD_PREG1_GLDO_AON 0x00010000U 851 #define PMUD_PREG1_GLDO_AON_M 0x00010000U 852 #define PMUD_PREG1_GLDO_AON_S 16U 853 #define PMUD_PREG1_GLDO_AON_EN 0x00010000U 854 #define PMUD_PREG1_GLDO_AON_DIS 0x00000000U 855 856 // Field: [15] RCHG_BLK_VTRIG_EN 857 // 858 // Internal. Only to be used through TI provided API. 859 // ENUMs: 860 // EN Internal. Only to be used through TI provided API. 861 // DIS Internal. Only to be used through TI provided API. 862 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN 0x00008000U 863 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_M 0x00008000U 864 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_S 15U 865 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_EN 0x00008000U 866 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_DIS 0x00000000U 867 868 // Field: [14] RCHG_BLK_ATEST_EN 869 // 870 // Internal. Only to be used through TI provided API. 871 // ENUMs: 872 // EN Internal. Only to be used through TI provided API. 873 // DIS Internal. Only to be used through TI provided API. 874 #define PMUD_PREG1_RCHG_BLK_ATEST_EN 0x00004000U 875 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_M 0x00004000U 876 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_S 14U 877 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_EN 0x00004000U 878 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_DIS 0x00000000U 879 880 // Field: [13] RCHG_FORCE_SAMP_VREF 881 // 882 // Internal. Only to be used through TI provided API. 883 // ENUMs: 884 // EN Internal. Only to be used through TI provided API. 885 // DIS Internal. Only to be used through TI provided API. 886 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF 0x00002000U 887 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_M 0x00002000U 888 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_S 13U 889 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_EN 0x00002000U 890 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_DIS 0x00000000U 891 892 // Field: [12] RCHG_COMP_CLK_DIS 893 // 894 // Internal. Only to be used through TI provided API. 895 // ENUMs: 896 // DIS Internal. Only to be used through TI provided API. 897 // EN Internal. Only to be used through TI provided API. 898 #define PMUD_PREG1_RCHG_COMP_CLK_DIS 0x00001000U 899 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_M 0x00001000U 900 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_S 12U 901 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_DIS 0x00001000U 902 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_EN 0x00000000U 903 904 // Field: [7] SPARE 905 // 906 // Internal. Only to be used through TI provided API. 907 #define PMUD_PREG1_SPARE 0x00000080U 908 #define PMUD_PREG1_SPARE_M 0x00000080U 909 #define PMUD_PREG1_SPARE_S 7U 910 911 // Field: [6] VDDR_ATBSEL 912 // 913 // Internal. Only to be used through TI provided API. 914 // ENUMs: 915 // EN Internal. Only to be used through TI provided API. 916 // DIS Internal. Only to be used through TI provided API. 917 #define PMUD_PREG1_VDDR_ATBSEL 0x00000040U 918 #define PMUD_PREG1_VDDR_ATBSEL_M 0x00000040U 919 #define PMUD_PREG1_VDDR_ATBSEL_S 6U 920 #define PMUD_PREG1_VDDR_ATBSEL_EN 0x00000040U 921 #define PMUD_PREG1_VDDR_ATBSEL_DIS 0x00000000U 922 923 // Field: [5] GLDO_EA_BIAS_DIS 924 // 925 // Internal. Only to be used through TI provided API. 926 // ENUMs: 927 // OFF Internal. Only to be used through TI provided API. 928 // ON Internal. Only to be used through TI provided API. 929 #define PMUD_PREG1_GLDO_EA_BIAS_DIS 0x00000020U 930 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_M 0x00000020U 931 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_S 5U 932 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_OFF 0x00000020U 933 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_ON 0x00000000U 934 935 // Field: [4:1] GLDO_ATBSEL 936 // 937 // Internal. Only to be used through TI provided API. 938 // ENUMs: 939 // VDDROK Internal. Only to be used through TI provided API. 940 // IB1U Internal. Only to be used through TI provided API. 941 // PASSGATE Internal. Only to be used through TI provided API. 942 // ERRAMP_OUT Internal. Only to be used through TI provided API. 943 // NC Internal. Only to be used through TI provided API. 944 #define PMUD_PREG1_GLDO_ATBSEL_W 4U 945 #define PMUD_PREG1_GLDO_ATBSEL_M 0x0000001EU 946 #define PMUD_PREG1_GLDO_ATBSEL_S 1U 947 #define PMUD_PREG1_GLDO_ATBSEL_VDDROK 0x00000010U 948 #define PMUD_PREG1_GLDO_ATBSEL_IB1U 0x00000008U 949 #define PMUD_PREG1_GLDO_ATBSEL_PASSGATE 0x00000004U 950 #define PMUD_PREG1_GLDO_ATBSEL_ERRAMP_OUT 0x00000002U 951 #define PMUD_PREG1_GLDO_ATBSEL_NC 0x00000000U 952 953 //***************************************************************************** 954 // 955 // Register: PMUD_O_PREG2 956 // 957 //***************************************************************************** 958 // Field: [5] RSTNMASK 959 // 960 // Internal. Only to be used through TI provided API. 961 // ENUMs: 962 // BM Internal. Only to be used through TI provided API. 963 // BNM Internal. Only to be used through TI provided API. 964 #define PMUD_PREG2_RSTNMASK 0x00000020U 965 #define PMUD_PREG2_RSTNMASK_M 0x00000020U 966 #define PMUD_PREG2_RSTNMASK_S 5U 967 #define PMUD_PREG2_RSTNMASK_BM 0x00000020U 968 #define PMUD_PREG2_RSTNMASK_BNM 0x00000000U 969 970 // Field: [4] DCDC_RCHG_ATBSEL 971 // 972 // Internal. Only to be used through TI provided API. 973 // ENUMs: 974 // RCHG_BLK Internal. Only to be used through TI provided API. 975 // DCDC_GLDO Internal. Only to be used through TI provided API. 976 #define PMUD_PREG2_DCDC_RCHG_ATBSEL 0x00000010U 977 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_M 0x00000010U 978 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_S 4U 979 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_RCHG_BLK 0x00000010U 980 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_DCDC_GLDO 0x00000000U 981 982 // Field: [3:0] PMUREG_ATBSEL 983 // 984 // Internal. Only to be used through TI provided API. 985 // ENUMs: 986 // DCDC_ATEST0_RCHG_ATEST1 Internal. Only to be used through TI provided API. 987 // SOCLDOI_A0 Internal. Only to be used through TI provided API. 988 // RESERVED Internal. Only to be used through TI provided API. 989 // SOCLDOV_A1 Internal. Only to be used through TI provided API. 990 // NC Internal. Only to be used through TI provided API. 991 #define PMUD_PREG2_PMUREG_ATBSEL_W 4U 992 #define PMUD_PREG2_PMUREG_ATBSEL_M 0x0000000FU 993 #define PMUD_PREG2_PMUREG_ATBSEL_S 0U 994 #define PMUD_PREG2_PMUREG_ATBSEL_DCDC_ATEST0_RCHG_ATEST1 0x00000008U 995 #define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOI_A0 0x00000004U 996 #define PMUD_PREG2_PMUREG_ATBSEL_RESERVED 0x00000002U 997 #define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOV_A1 0x00000001U 998 #define PMUD_PREG2_PMUREG_ATBSEL_NC 0x00000000U 999 1000 //***************************************************************************** 1001 // 1002 // Register: PMUD_O_DCDCCFG 1003 // 1004 //***************************************************************************** 1005 // Field: [22:16] LM_HIGHTH 1006 // 1007 // DCDC load meter high threshold value for adaptive IPEAK adjustment. DCDC 1008 // load meter output is in percentage scale so the applicable values are 'd1 to 1009 // 'd100. Values from 'd101 to 'd127 are invalid and not to be used. 1010 #define PMUD_DCDCCFG_LM_HIGHTH_W 7U 1011 #define PMUD_DCDCCFG_LM_HIGHTH_M 0x007F0000U 1012 #define PMUD_DCDCCFG_LM_HIGHTH_S 16U 1013 1014 // Field: [14:8] LM_LOWTH 1015 // 1016 // DCDC load meter low threshold value for adaptive IPEAK adjustment. DCDC load 1017 // meter output is in percentage scale so the applicable values are 'd1 to 1018 // 'd100. Values from 'd101 to 'd127 are invalid and not to be used. 1019 #define PMUD_DCDCCFG_LM_LOWTH_W 7U 1020 #define PMUD_DCDCCFG_LM_LOWTH_M 0x00007F00U 1021 #define PMUD_DCDCCFG_LM_LOWTH_S 8U 1022 1023 // Field: [4] ADP_IPEAK_EN 1024 // 1025 // This bit is used to enable adaptive IPEAK adjustment scheme in hardware. 1026 // When this bit is set, DCDC IPEAK value is automatically adjusted to suitable 1027 // value by sensing the DCDC load meter output for better DCDC operational 1028 // efficiency. 1029 // ENUMs: 1030 // EN Enable 1031 // DIS Disable 1032 #define PMUD_DCDCCFG_ADP_IPEAK_EN 0x00000010U 1033 #define PMUD_DCDCCFG_ADP_IPEAK_EN_M 0x00000010U 1034 #define PMUD_DCDCCFG_ADP_IPEAK_EN_S 4U 1035 #define PMUD_DCDCCFG_ADP_IPEAK_EN_EN 0x00000010U 1036 #define PMUD_DCDCCFG_ADP_IPEAK_EN_DIS 0x00000000U 1037 1038 // Field: [0] LMEN 1039 // 1040 // This bit is used to enable DCDC load meter. Software can obtain DCDC load 1041 // meter value from DCDCSTAT regiser and adjust IPEAK setting in SYS0.TDCDC 1042 // register accordingly. 1043 // ENUMs: 1044 // EN Enable 1045 // DIS Disable 1046 #define PMUD_DCDCCFG_LMEN 0x00000001U 1047 #define PMUD_DCDCCFG_LMEN_M 0x00000001U 1048 #define PMUD_DCDCCFG_LMEN_S 0U 1049 #define PMUD_DCDCCFG_LMEN_EN 0x00000001U 1050 #define PMUD_DCDCCFG_LMEN_DIS 0x00000000U 1051 1052 //***************************************************************************** 1053 // 1054 // Register: PMUD_O_DCDCSTAT 1055 // 1056 //***************************************************************************** 1057 // Field: [10:8] IPEAK 1058 // 1059 // DCDC IPEAK value. This value is same as what is programmed in 1060 // SYS0:TMUTE4.IPEAK when adaptive IPEAK adjustment scheme is not enabled, and 1061 // it shows current IPEAK value applied by hardware when adaptive IPEAK 1062 // adjustment scheme is enabled. 1063 // Note: Software can only support IPEAK = 1 1064 #define PMUD_DCDCSTAT_IPEAK_W 3U 1065 #define PMUD_DCDCSTAT_IPEAK_M 0x00000700U 1066 #define PMUD_DCDCSTAT_IPEAK_S 8U 1067 1068 // Field: [6:0] LOAD 1069 // 1070 // This indicates DCDC load meter output value in percentage scale. 1071 // Applicable range is 'd1 to 'd100. 1072 #define PMUD_DCDCSTAT_LOAD_W 7U 1073 #define PMUD_DCDCSTAT_LOAD_M 0x0000007FU 1074 #define PMUD_DCDCSTAT_LOAD_S 0U 1075 1076 1077 #endif // __PMUD__ 1078
