1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2021 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K344_PMC.h
10  * @version 1.9
11  * @date 2021-10-27
12  * @brief Peripheral Access Layer for S32K344_PMC
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K344_PMC_H_)  /* Check if memory map has not been already included */
58 #define S32K344_PMC_H_
59 
60 #include "S32K344_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- PMC Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
68  * @{
69  */
70 
71 /** PMC - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t LVSC;                              /**< Low Voltage Status and Control Register, offset: 0x0 */
74   __IO uint32_t CONFIG;                            /**< PMC Configuration Register, offset: 0x4 */
75   uint8_t RESERVED_0[4];
76   __I  uint32_t VERID;                             /**< Version ID register, offset: 0xC */
77 } PMC_Type, *PMC_MemMapPtr;
78 
79 /** Number of instances of the PMC module. */
80 #define PMC_INSTANCE_COUNT                       (1u)
81 
82 /* PMC - Peripheral instance base addresses */
83 /** Peripheral PMC base address */
84 #define IP_PMC_BASE                              (0x402E8000u)
85 /** Peripheral PMC base pointer */
86 #define IP_PMC                                   ((PMC_Type *)IP_PMC_BASE)
87 /** Array initializer of PMC peripheral base addresses */
88 #define IP_PMC_BASE_ADDRS                        { IP_PMC_BASE }
89 /** Array initializer of PMC peripheral base pointers */
90 #define IP_PMC_BASE_PTRS                         { IP_PMC }
91 
92 /* ----------------------------------------------------------------------------
93    -- PMC Register Masks
94    ---------------------------------------------------------------------------- */
95 
96 /*!
97  * @addtogroup PMC_Register_Masks PMC Register Masks
98  * @{
99  */
100 
101 /*! @name LVSC - Low Voltage Status and Control Register */
102 /*! @{ */
103 
104 #define PMC_LVSC_HVDAF_MASK                      (0x1U)
105 #define PMC_LVSC_HVDAF_SHIFT                     (0U)
106 #define PMC_LVSC_HVDAF_WIDTH                     (1U)
107 #define PMC_LVSC_HVDAF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVDAF_SHIFT)) & PMC_LVSC_HVDAF_MASK)
108 
109 #define PMC_LVSC_HVDBF_MASK                      (0x2U)
110 #define PMC_LVSC_HVDBF_SHIFT                     (1U)
111 #define PMC_LVSC_HVDBF_WIDTH                     (1U)
112 #define PMC_LVSC_HVDBF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVDBF_SHIFT)) & PMC_LVSC_HVDBF_MASK)
113 
114 #define PMC_LVSC_HVD25F_MASK                     (0x4U)
115 #define PMC_LVSC_HVD25F_SHIFT                    (2U)
116 #define PMC_LVSC_HVD25F_WIDTH                    (1U)
117 #define PMC_LVSC_HVD25F(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVD25F_SHIFT)) & PMC_LVSC_HVD25F_MASK)
118 
119 #define PMC_LVSC_HVD11F_MASK                     (0x8U)
120 #define PMC_LVSC_HVD11F_SHIFT                    (3U)
121 #define PMC_LVSC_HVD11F_WIDTH                    (1U)
122 #define PMC_LVSC_HVD11F(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVD11F_SHIFT)) & PMC_LVSC_HVD11F_MASK)
123 
124 #define PMC_LVSC_LVD5AF_MASK                     (0x10U)
125 #define PMC_LVSC_LVD5AF_SHIFT                    (4U)
126 #define PMC_LVSC_LVD5AF_WIDTH                    (1U)
127 #define PMC_LVSC_LVD5AF(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVD5AF_SHIFT)) & PMC_LVSC_LVD5AF_MASK)
128 
129 #define PMC_LVSC_LVD15F_MASK                     (0x20U)
130 #define PMC_LVSC_LVD15F_SHIFT                    (5U)
131 #define PMC_LVSC_LVD15F_WIDTH                    (1U)
132 #define PMC_LVSC_LVD15F(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVD15F_SHIFT)) & PMC_LVSC_LVD15F_MASK)
133 
134 #define PMC_LVSC_HVDAS_MASK                      (0x100U)
135 #define PMC_LVSC_HVDAS_SHIFT                     (8U)
136 #define PMC_LVSC_HVDAS_WIDTH                     (1U)
137 #define PMC_LVSC_HVDAS(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVDAS_SHIFT)) & PMC_LVSC_HVDAS_MASK)
138 
139 #define PMC_LVSC_HVDBS_MASK                      (0x200U)
140 #define PMC_LVSC_HVDBS_SHIFT                     (9U)
141 #define PMC_LVSC_HVDBS_WIDTH                     (1U)
142 #define PMC_LVSC_HVDBS(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVDBS_SHIFT)) & PMC_LVSC_HVDBS_MASK)
143 
144 #define PMC_LVSC_HVD25S_MASK                     (0x400U)
145 #define PMC_LVSC_HVD25S_SHIFT                    (10U)
146 #define PMC_LVSC_HVD25S_WIDTH                    (1U)
147 #define PMC_LVSC_HVD25S(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVD25S_SHIFT)) & PMC_LVSC_HVD25S_MASK)
148 
149 #define PMC_LVSC_HVD11S_MASK                     (0x800U)
150 #define PMC_LVSC_HVD11S_SHIFT                    (11U)
151 #define PMC_LVSC_HVD11S_WIDTH                    (1U)
152 #define PMC_LVSC_HVD11S(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_HVD11S_SHIFT)) & PMC_LVSC_HVD11S_MASK)
153 
154 #define PMC_LVSC_LVD5AS_MASK                     (0x1000U)
155 #define PMC_LVSC_LVD5AS_SHIFT                    (12U)
156 #define PMC_LVSC_LVD5AS_WIDTH                    (1U)
157 #define PMC_LVSC_LVD5AS(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVD5AS_SHIFT)) & PMC_LVSC_LVD5AS_MASK)
158 
159 #define PMC_LVSC_LVD15S_MASK                     (0x2000U)
160 #define PMC_LVSC_LVD15S_SHIFT                    (13U)
161 #define PMC_LVSC_LVD15S_WIDTH                    (1U)
162 #define PMC_LVSC_LVD15S(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVD15S_SHIFT)) & PMC_LVSC_LVD15S_MASK)
163 
164 #define PMC_LVSC_LVRAF_MASK                      (0x10000U)
165 #define PMC_LVSC_LVRAF_SHIFT                     (16U)
166 #define PMC_LVSC_LVRAF_WIDTH                     (1U)
167 #define PMC_LVSC_LVRAF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVRAF_SHIFT)) & PMC_LVSC_LVRAF_MASK)
168 
169 #define PMC_LVSC_LVRALPF_MASK                    (0x20000U)
170 #define PMC_LVSC_LVRALPF_SHIFT                   (17U)
171 #define PMC_LVSC_LVRALPF_WIDTH                   (1U)
172 #define PMC_LVSC_LVRALPF(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVRALPF_SHIFT)) & PMC_LVSC_LVRALPF_MASK)
173 
174 #define PMC_LVSC_LVRBF_MASK                      (0x40000U)
175 #define PMC_LVSC_LVRBF_SHIFT                     (18U)
176 #define PMC_LVSC_LVRBF_WIDTH                     (1U)
177 #define PMC_LVSC_LVRBF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVRBF_SHIFT)) & PMC_LVSC_LVRBF_MASK)
178 
179 #define PMC_LVSC_LVRBLPF_MASK                    (0x80000U)
180 #define PMC_LVSC_LVRBLPF_SHIFT                   (19U)
181 #define PMC_LVSC_LVRBLPF_WIDTH                   (1U)
182 #define PMC_LVSC_LVRBLPF(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVRBLPF_SHIFT)) & PMC_LVSC_LVRBLPF_MASK)
183 
184 #define PMC_LVSC_LVR25F_MASK                     (0x100000U)
185 #define PMC_LVSC_LVR25F_SHIFT                    (20U)
186 #define PMC_LVSC_LVR25F_WIDTH                    (1U)
187 #define PMC_LVSC_LVR25F(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVR25F_SHIFT)) & PMC_LVSC_LVR25F_MASK)
188 
189 #define PMC_LVSC_LVR25LPF_MASK                   (0x200000U)
190 #define PMC_LVSC_LVR25LPF_SHIFT                  (21U)
191 #define PMC_LVSC_LVR25LPF_WIDTH                  (1U)
192 #define PMC_LVSC_LVR25LPF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVR25LPF_SHIFT)) & PMC_LVSC_LVR25LPF_MASK)
193 
194 #define PMC_LVSC_LVR11F_MASK                     (0x400000U)
195 #define PMC_LVSC_LVR11F_SHIFT                    (22U)
196 #define PMC_LVSC_LVR11F_WIDTH                    (1U)
197 #define PMC_LVSC_LVR11F(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVR11F_SHIFT)) & PMC_LVSC_LVR11F_MASK)
198 
199 #define PMC_LVSC_LVR11LPF_MASK                   (0x800000U)
200 #define PMC_LVSC_LVR11LPF_SHIFT                  (23U)
201 #define PMC_LVSC_LVR11LPF_WIDTH                  (1U)
202 #define PMC_LVSC_LVR11LPF(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_LVR11LPF_SHIFT)) & PMC_LVSC_LVR11LPF_MASK)
203 
204 #define PMC_LVSC_GNG25OSCF_MASK                  (0x1000000U)
205 #define PMC_LVSC_GNG25OSCF_SHIFT                 (24U)
206 #define PMC_LVSC_GNG25OSCF_WIDTH                 (1U)
207 #define PMC_LVSC_GNG25OSCF(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_GNG25OSCF_SHIFT)) & PMC_LVSC_GNG25OSCF_MASK)
208 
209 #define PMC_LVSC_GNG11OSCF_MASK                  (0x2000000U)
210 #define PMC_LVSC_GNG11OSCF_SHIFT                 (25U)
211 #define PMC_LVSC_GNG11OSCF_WIDTH                 (1U)
212 #define PMC_LVSC_GNG11OSCF(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_GNG11OSCF_SHIFT)) & PMC_LVSC_GNG11OSCF_MASK)
213 
214 #define PMC_LVSC_PORF_MASK                       (0x80000000U)
215 #define PMC_LVSC_PORF_SHIFT                      (31U)
216 #define PMC_LVSC_PORF_WIDTH                      (1U)
217 #define PMC_LVSC_PORF(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_LVSC_PORF_SHIFT)) & PMC_LVSC_PORF_MASK)
218 /*! @} */
219 
220 /*! @name CONFIG - PMC Configuration Register */
221 /*! @{ */
222 
223 #define PMC_CONFIG_LMEN_MASK                     (0x1U)
224 #define PMC_CONFIG_LMEN_SHIFT                    (0U)
225 #define PMC_CONFIG_LMEN_WIDTH                    (1U)
226 #define PMC_CONFIG_LMEN(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LMEN_SHIFT)) & PMC_CONFIG_LMEN_MASK)
227 
228 #define PMC_CONFIG_LMBCTLEN_MASK                 (0x2U)
229 #define PMC_CONFIG_LMBCTLEN_SHIFT                (1U)
230 #define PMC_CONFIG_LMBCTLEN_WIDTH                (1U)
231 #define PMC_CONFIG_LMBCTLEN(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LMBCTLEN_SHIFT)) & PMC_CONFIG_LMBCTLEN_MASK)
232 
233 #define PMC_CONFIG_FASTREC_MASK                  (0x4U)
234 #define PMC_CONFIG_FASTREC_SHIFT                 (2U)
235 #define PMC_CONFIG_FASTREC_WIDTH                 (1U)
236 #define PMC_CONFIG_FASTREC(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_FASTREC_SHIFT)) & PMC_CONFIG_FASTREC_MASK)
237 
238 #define PMC_CONFIG_LPM25EN_MASK                  (0x8U)
239 #define PMC_CONFIG_LPM25EN_SHIFT                 (3U)
240 #define PMC_CONFIG_LPM25EN_WIDTH                 (1U)
241 #define PMC_CONFIG_LPM25EN(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LPM25EN_SHIFT)) & PMC_CONFIG_LPM25EN_MASK)
242 
243 #define PMC_CONFIG_LVRBLPEN_MASK                 (0x10U)
244 #define PMC_CONFIG_LVRBLPEN_SHIFT                (4U)
245 #define PMC_CONFIG_LVRBLPEN_WIDTH                (1U)
246 #define PMC_CONFIG_LVRBLPEN(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LVRBLPEN_SHIFT)) & PMC_CONFIG_LVRBLPEN_MASK)
247 
248 #define PMC_CONFIG_HVDIE_MASK                    (0x100U)
249 #define PMC_CONFIG_HVDIE_SHIFT                   (8U)
250 #define PMC_CONFIG_HVDIE_WIDTH                   (1U)
251 #define PMC_CONFIG_HVDIE(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_HVDIE_SHIFT)) & PMC_CONFIG_HVDIE_MASK)
252 
253 #define PMC_CONFIG_LVDIE_MASK                    (0x200U)
254 #define PMC_CONFIG_LVDIE_SHIFT                   (9U)
255 #define PMC_CONFIG_LVDIE_WIDTH                   (1U)
256 #define PMC_CONFIG_LVDIE(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LVDIE_SHIFT)) & PMC_CONFIG_LVDIE_MASK)
257 
258 #define PMC_CONFIG_LMAUTOEN_MASK                 (0x10000U)
259 #define PMC_CONFIG_LMAUTOEN_SHIFT                (16U)
260 #define PMC_CONFIG_LMAUTOEN_WIDTH                (1U)
261 #define PMC_CONFIG_LMAUTOEN(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LMAUTOEN_SHIFT)) & PMC_CONFIG_LMAUTOEN_MASK)
262 
263 #define PMC_CONFIG_LMSTAT_MASK                   (0x20000U)
264 #define PMC_CONFIG_LMSTAT_SHIFT                  (17U)
265 #define PMC_CONFIG_LMSTAT_WIDTH                  (1U)
266 #define PMC_CONFIG_LMSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_CONFIG_LMSTAT_SHIFT)) & PMC_CONFIG_LMSTAT_MASK)
267 /*! @} */
268 
269 /*! @name VERID - Version ID register */
270 /*! @{ */
271 
272 #define PMC_VERID_LMFEAT_MASK                    (0x1U)
273 #define PMC_VERID_LMFEAT_SHIFT                   (0U)
274 #define PMC_VERID_LMFEAT_WIDTH                   (1U)
275 #define PMC_VERID_LMFEAT(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_VERID_LMFEAT_SHIFT)) & PMC_VERID_LMFEAT_MASK)
276 
277 #define PMC_VERID_MINOR_MASK                     (0xFF0000U)
278 #define PMC_VERID_MINOR_SHIFT                    (16U)
279 #define PMC_VERID_MINOR_WIDTH                    (8U)
280 #define PMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MINOR_SHIFT)) & PMC_VERID_MINOR_MASK)
281 
282 #define PMC_VERID_MAJOR_MASK                     (0xFF000000U)
283 #define PMC_VERID_MAJOR_SHIFT                    (24U)
284 #define PMC_VERID_MAJOR_WIDTH                    (8U)
285 #define PMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MAJOR_SHIFT)) & PMC_VERID_MAJOR_MASK)
286 /*! @} */
287 
288 /*!
289  * @}
290  */ /* end of group PMC_Register_Masks */
291 
292 /*!
293  * @}
294  */ /* end of group PMC_Peripheral_Access_Layer */
295 
296 #endif  /* #if !defined(S32K344_PMC_H_) */
297