1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_PLL.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_PLL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_PLL_H_) /* Check if memory map has not been already included */ 58 #define S32K344_PLL_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PLL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PLL_Peripheral_Access_Layer PLL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PLL - Size of Registers Arrays */ 72 #define PLL_PLLODIV_COUNT 2u 73 74 /** PLL - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t PLLCR; /**< PLL Control, offset: 0x0 */ 77 __IO uint32_t PLLSR; /**< PLL Status, offset: 0x4 */ 78 __IO uint32_t PLLDV; /**< PLL Divider, offset: 0x8 */ 79 __IO uint32_t PLLFM; /**< PLL Frequency Modulation, offset: 0xC */ 80 __IO uint32_t PLLFD; /**< PLL Fractional Divider, offset: 0x10 */ 81 uint8_t RESERVED_0[4]; 82 __IO uint32_t PLLCAL2; /**< PLL Calibration Register 2, offset: 0x18 */ 83 uint8_t RESERVED_1[100]; 84 __IO uint32_t PLLODIV[PLL_PLLODIV_COUNT]; /**< PLL Output Divider, array offset: 0x80, array step: 0x4 */ 85 } PLL_Type, *PLL_MemMapPtr; 86 87 /** Number of instances of the PLL module. */ 88 #define PLL_INSTANCE_COUNT (1u) 89 90 /* PLL - Peripheral instance base addresses */ 91 /** Peripheral PLL base address */ 92 #define IP_PLL_BASE (0x402E0000u) 93 /** Peripheral PLL base pointer */ 94 #define IP_PLL ((PLL_Type *)IP_PLL_BASE) 95 /** Array initializer of PLL peripheral base addresses */ 96 #define IP_PLL_BASE_ADDRS { IP_PLL_BASE } 97 /** Array initializer of PLL peripheral base pointers */ 98 #define IP_PLL_BASE_PTRS { IP_PLL } 99 100 /* ---------------------------------------------------------------------------- 101 -- PLL Register Masks 102 ---------------------------------------------------------------------------- */ 103 104 /*! 105 * @addtogroup PLL_Register_Masks PLL Register Masks 106 * @{ 107 */ 108 109 /*! @name PLLCR - PLL Control */ 110 /*! @{ */ 111 112 #define PLL_PLLCR_PLLPD_MASK (0x80000000U) 113 #define PLL_PLLCR_PLLPD_SHIFT (31U) 114 #define PLL_PLLCR_PLLPD_WIDTH (1U) 115 #define PLL_PLLCR_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLCR_PLLPD_SHIFT)) & PLL_PLLCR_PLLPD_MASK) 116 /*! @} */ 117 118 /*! @name PLLSR - PLL Status */ 119 /*! @{ */ 120 121 #define PLL_PLLSR_LOCK_MASK (0x4U) 122 #define PLL_PLLSR_LOCK_SHIFT (2U) 123 #define PLL_PLLSR_LOCK_WIDTH (1U) 124 #define PLL_PLLSR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLSR_LOCK_SHIFT)) & PLL_PLLSR_LOCK_MASK) 125 126 #define PLL_PLLSR_LOL_MASK (0x8U) 127 #define PLL_PLLSR_LOL_SHIFT (3U) 128 #define PLL_PLLSR_LOL_WIDTH (1U) 129 #define PLL_PLLSR_LOL(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLSR_LOL_SHIFT)) & PLL_PLLSR_LOL_MASK) 130 /*! @} */ 131 132 /*! @name PLLDV - PLL Divider */ 133 /*! @{ */ 134 135 #define PLL_PLLDV_MFI_MASK (0xFFU) 136 #define PLL_PLLDV_MFI_SHIFT (0U) 137 #define PLL_PLLDV_MFI_WIDTH (8U) 138 #define PLL_PLLDV_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLDV_MFI_SHIFT)) & PLL_PLLDV_MFI_MASK) 139 140 #define PLL_PLLDV_RDIV_MASK (0x7000U) 141 #define PLL_PLLDV_RDIV_SHIFT (12U) 142 #define PLL_PLLDV_RDIV_WIDTH (3U) 143 #define PLL_PLLDV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLDV_RDIV_SHIFT)) & PLL_PLLDV_RDIV_MASK) 144 145 #define PLL_PLLDV_ODIV2_MASK (0x7E000000U) 146 #define PLL_PLLDV_ODIV2_SHIFT (25U) 147 #define PLL_PLLDV_ODIV2_WIDTH (6U) 148 #define PLL_PLLDV_ODIV2(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLDV_ODIV2_SHIFT)) & PLL_PLLDV_ODIV2_MASK) 149 /*! @} */ 150 151 /*! @name PLLFM - PLL Frequency Modulation */ 152 /*! @{ */ 153 154 #define PLL_PLLFM_STEPNO_MASK (0x7FFU) 155 #define PLL_PLLFM_STEPNO_SHIFT (0U) 156 #define PLL_PLLFM_STEPNO_WIDTH (11U) 157 #define PLL_PLLFM_STEPNO(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFM_STEPNO_SHIFT)) & PLL_PLLFM_STEPNO_MASK) 158 159 #define PLL_PLLFM_STEPSIZE_MASK (0x3FF0000U) 160 #define PLL_PLLFM_STEPSIZE_SHIFT (16U) 161 #define PLL_PLLFM_STEPSIZE_WIDTH (10U) 162 #define PLL_PLLFM_STEPSIZE(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFM_STEPSIZE_SHIFT)) & PLL_PLLFM_STEPSIZE_MASK) 163 164 #define PLL_PLLFM_SPREADCTL_MASK (0x20000000U) 165 #define PLL_PLLFM_SPREADCTL_SHIFT (29U) 166 #define PLL_PLLFM_SPREADCTL_WIDTH (1U) 167 #define PLL_PLLFM_SPREADCTL(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFM_SPREADCTL_SHIFT)) & PLL_PLLFM_SPREADCTL_MASK) 168 169 #define PLL_PLLFM_SSCGBYP_MASK (0x40000000U) 170 #define PLL_PLLFM_SSCGBYP_SHIFT (30U) 171 #define PLL_PLLFM_SSCGBYP_WIDTH (1U) 172 #define PLL_PLLFM_SSCGBYP(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFM_SSCGBYP_SHIFT)) & PLL_PLLFM_SSCGBYP_MASK) 173 /*! @} */ 174 175 /*! @name PLLFD - PLL Fractional Divider */ 176 /*! @{ */ 177 178 #define PLL_PLLFD_MFN_MASK (0x7FFFU) 179 #define PLL_PLLFD_MFN_SHIFT (0U) 180 #define PLL_PLLFD_MFN_WIDTH (15U) 181 #define PLL_PLLFD_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFD_MFN_SHIFT)) & PLL_PLLFD_MFN_MASK) 182 183 #define PLL_PLLFD_SDM3_MASK (0x10000000U) 184 #define PLL_PLLFD_SDM3_SHIFT (28U) 185 #define PLL_PLLFD_SDM3_WIDTH (1U) 186 #define PLL_PLLFD_SDM3(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFD_SDM3_SHIFT)) & PLL_PLLFD_SDM3_MASK) 187 188 #define PLL_PLLFD_SDM2_MASK (0x20000000U) 189 #define PLL_PLLFD_SDM2_SHIFT (29U) 190 #define PLL_PLLFD_SDM2_WIDTH (1U) 191 #define PLL_PLLFD_SDM2(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFD_SDM2_SHIFT)) & PLL_PLLFD_SDM2_MASK) 192 193 #define PLL_PLLFD_SDMEN_MASK (0x40000000U) 194 #define PLL_PLLFD_SDMEN_SHIFT (30U) 195 #define PLL_PLLFD_SDMEN_WIDTH (1U) 196 #define PLL_PLLFD_SDMEN(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLFD_SDMEN_SHIFT)) & PLL_PLLFD_SDMEN_MASK) 197 /*! @} */ 198 199 /*! @name PLLCAL2 - PLL Calibration Register 2 */ 200 /*! @{ */ 201 202 #define PLL_PLLCAL2_ULKCTL_MASK (0x180U) 203 #define PLL_PLLCAL2_ULKCTL_SHIFT (7U) 204 #define PLL_PLLCAL2_ULKCTL_WIDTH (2U) 205 #define PLL_PLLCAL2_ULKCTL(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLCAL2_ULKCTL_SHIFT)) & PLL_PLLCAL2_ULKCTL_MASK) 206 /*! @} */ 207 208 /*! @name PLLODIV - PLL Output Divider */ 209 /*! @{ */ 210 211 #define PLL_PLLODIV_DIV_MASK (0xF0000U) 212 #define PLL_PLLODIV_DIV_SHIFT (16U) 213 #define PLL_PLLODIV_DIV_WIDTH (4U) 214 #define PLL_PLLODIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLODIV_DIV_SHIFT)) & PLL_PLLODIV_DIV_MASK) 215 216 #define PLL_PLLODIV_DE_MASK (0x80000000U) 217 #define PLL_PLLODIV_DE_SHIFT (31U) 218 #define PLL_PLLODIV_DE_WIDTH (1U) 219 #define PLL_PLLODIV_DE(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLODIV_DE_SHIFT)) & PLL_PLLODIV_DE_MASK) 220 /*! @} */ 221 222 /*! 223 * @} 224 */ /* end of group PLL_Register_Masks */ 225 226 /*! 227 * @} 228 */ /* end of group PLL_Peripheral_Access_Layer */ 229 230 #endif /* #if !defined(S32K344_PLL_H_) */ 231
