1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /******************************************************************************* 11 * @file mss_scb_nwc_regs.h 12 * @author Microchip-FPGA Embedded Systems Solutions 13 * @brief SCB registers and associated structures relating to the NWC 14 * 15 */ 16 17 18 #ifndef MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ 19 #define MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ 20 21 #include "mpfs_hal/mss_hal.h" 22 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #ifndef __I 29 #define __I const volatile 30 #endif 31 #ifndef __IO 32 #define __IO volatile 33 #endif 34 #ifndef __O 35 #define __O volatile 36 #endif 37 38 /*------------ NWC PLL definition -----------*/ 39 typedef struct 40 { 41 __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */ 42 __IO uint32_t PLL_CTRL; /*!< Offset: 0x4 */ 43 __IO uint32_t PLL_REF_FB; /*!< Offset: 0x8 */ 44 __IO uint32_t PLL_FRACN; /*!< Offset: 0xc */ 45 __IO uint32_t PLL_DIV_0_1; /*!< Offset: 0x10 */ 46 __IO uint32_t PLL_DIV_2_3; /*!< Offset: 0x14 */ 47 __IO uint32_t PLL_CTRL2; /*!< Offset: 0x18 */ 48 __IO uint32_t PLL_CAL; /*!< Offset: 0x1c */ 49 __IO uint32_t PLL_PHADJ; /*!< Offset: 0x20 */ 50 __IO uint32_t SSCG_REG_0; /*!< Offset: 0x24 */ 51 __IO uint32_t SSCG_REG_1; /*!< Offset: 0x28 */ 52 __IO uint32_t SSCG_REG_2; /*!< Offset: 0x2c */ 53 __IO uint32_t SSCG_REG_3; /*!< Offset: 0x30 */ 54 } PLL_TypeDef; 55 56 /*------------ NWC PLL MUX definition -----------*/ 57 58 typedef struct 59 { 60 __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */ 61 __IO uint32_t BCLKMUX; /*!< Offset: 0x4 */ 62 __IO uint32_t PLL_CKMUX; /*!< Offset: 0x8 */ 63 __IO uint32_t MSSCLKMUX; /*!< Offset: 0xc */ 64 __IO uint32_t SPARE0; /*!< Offset: 0x10 */ 65 __IO uint32_t FMETER_ADDR; /*!< Offset: 0x14 */ 66 __IO uint32_t FMETER_DATAW; /*!< Offset: 0x18 */ 67 __IO uint32_t FMETER_DATAR; /*!< Offset: 0x1c */ 68 __IO uint32_t TEST_CTRL; /*!< Offset: 0x20 */ 69 } IOSCB_CFM_MSS; 70 71 typedef struct 72 { 73 __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */ 74 __IO uint32_t RFCKMUX; /*!< Offset: 0x4 */ 75 __IO uint32_t SGMII_CLKMUX; /*!< Offset: 0x8 */ 76 __IO uint32_t SPARE0; /*!< Offset: 0xc */ 77 __IO uint32_t CLK_XCVR; /*!< Offset: 0x10 */ 78 __IO uint32_t TEST_CTRL; /*!< Offset: 0x14 */ 79 } IOSCB_CFM_SGMII; 80 81 82 typedef struct 83 { 84 __IO uint32_t SOFT_RESET_IOCALIB; /*!< Offset: 0x00 */ 85 __IO uint32_t IOC_REG0; /*!< Offset: 0x04 */ 86 __I uint32_t IOC_REG1; /*!< Offset: 0x08 */ 87 __I uint32_t IOC_REG2; /*!< Offset: 0x0c */ 88 __I uint32_t IOC_REG3; /*!< Offset: 0x10 */ 89 __I uint32_t IOC_REG4; /*!< Offset: 0x14 */ 90 __I uint32_t IOC_REG5; /*!< Offset: 0x18 */ 91 __IO uint32_t IOC_REG6; /*!< Offset: 0x1c */ 92 } IOSCB_IO_CALIB_STRUCT; 93 94 95 #define MSS_SCB_MSS_PLL_BASE (0x3E001000U) /*!< ( MSS_SCB_MSS_PLL_BASE ) Base Address */ 96 #define MSS_SCB_DDR_PLL_BASE (0x3E010000U) /*!< ( MSS_SCB_DDR_PLL_BASE ) Base Address */ 97 #define MSS_SCB_SGMII_PLL_BASE (0x3E080000U) /*!< ( MSS_SCB_SGMII_PLL_BASE ) Base Address */ 98 99 #define MSS_SCB_MSS_MUX_BASE (0x3E002000U) /*!< ( MSS_SCB_MSS_MUX_BASE ) Base Address */ 100 #define MSS_SCB_SGMII_MUX_BASE (0x3E200000U) /*!< ( MSS_SCB_SGMII_PLL_BASE ) Base Address */ 101 102 #define IOSCB_IO_CALIB_SGMII_BASE (0x3E800000U) /*!< ( IOSCB_IO_CALIB_SGMII_BASE ) Base Address */ 103 #define IOSCB_IO_CALIB_DDR_BASE (0x3E040000U) /*!< ( IOSCB_IO_CALIB_SGMII_BASE ) Base Address */ 104 105 106 extern PLL_TypeDef * const MSS_SCB_MSS_PLL; 107 extern PLL_TypeDef * const MSS_SCB_DDR_PLL; 108 extern PLL_TypeDef * const MSS_SCB_SGMII_PLL; 109 extern IOSCB_CFM_MSS * const MSS_SCB_CFM_MSS_MUX; 110 extern IOSCB_CFM_SGMII * const MSS_SCB_CFM_SGMII_MUX; 111 extern IOSCB_IO_CALIB_STRUCT * const IOSCB_IO_CALIB_SGMII; 112 extern IOSCB_IO_CALIB_STRUCT * const IOSCB_IO_CALIB_DDR; 113 114 115 #ifdef __cplusplus 116 } 117 #endif 118 119 #endif /* MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ */ 120
