1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 16 /* Platform Type */ 17 #define PLAT_SOCFPGA_STRATIX10 1 18 #define PLAT_SOCFPGA_AGILEX 2 19 #define PLAT_SOCFPGA_N5X 3 20 21 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 22 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 23 24 /* 25 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 26 * is done and HPS should trigger warm reset via RMR_EL3. 27 */ 28 #define L2_RESET_DONE_REG 0xFFD12218 29 30 /* Magic word to indicate L2 reset is completed */ 31 #define L2_RESET_DONE_STATUS 0x1228E5E7 32 33 /* Define next boot image name and offset */ 34 #define PLAT_NS_IMAGE_OFFSET 0x10000000 35 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 36 37 /******************************************************************************* 38 * Platform binary types for linking 39 ******************************************************************************/ 40 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 41 #define PLATFORM_LINKER_ARCH aarch64 42 43 /* SoCFPGA supports up to 124GB RAM */ 44 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 45 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 46 47 48 /******************************************************************************* 49 * Generic platform constants 50 ******************************************************************************/ 51 #define PLAT_PRIMARY_CPU 0 52 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 53 54 /* Size of cacheable stacks */ 55 #define PLATFORM_STACK_SIZE 0x2000 56 57 /* PSCI related constant */ 58 #define PLAT_NUM_POWER_DOMAINS 5 59 #define PLAT_MAX_PWR_LVL 1 60 #define PLAT_MAX_RET_STATE 1 61 #define PLAT_MAX_OFF_STATE 2 62 #define PLATFORM_SYSTEM_COUNT U(1) 63 #define PLATFORM_CLUSTER_COUNT U(1) 64 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 65 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 66 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 67 PLATFORM_CLUSTER0_CORE_COUNT) 68 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 69 70 /* Interrupt related constant */ 71 72 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 73 74 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 75 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 76 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 77 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 78 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 79 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 80 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 81 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 82 83 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 84 #define TSP_SEC_MEM_BASE BL32_BASE 85 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 86 /******************************************************************************* 87 * Platform memory map related constants 88 ******************************************************************************/ 89 #define DRAM_BASE (0x0) 90 #define DRAM_SIZE (0x80000000) 91 92 #define OCRAM_BASE (0xFFE00000) 93 #define OCRAM_SIZE (0x00040000) 94 95 #define MEM64_BASE (0x0100000000) 96 #define MEM64_SIZE (0x1F00000000) 97 98 #define DEVICE1_BASE (0x80000000) 99 #define DEVICE1_SIZE (0x60000000) 100 101 #define DEVICE2_BASE (0xF7000000) 102 #define DEVICE2_SIZE (0x08E00000) 103 104 #define DEVICE3_BASE (0xFFFC0000) 105 #define DEVICE3_SIZE (0x00008000) 106 107 #define DEVICE4_BASE (0x2000000000) 108 #define DEVICE4_SIZE (0x0100000000) 109 110 /******************************************************************************* 111 * BL31 specific defines. 112 ******************************************************************************/ 113 /* 114 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 115 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 116 * little space for growth. 117 */ 118 119 120 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 121 122 #define BL1_RO_BASE (0xffe00000) 123 #define BL1_RO_LIMIT (0xffe0f000) 124 #define BL1_RW_BASE (0xffe10000) 125 #define BL1_RW_LIMIT (0xffe1ffff) 126 #define BL1_RW_SIZE (0x14000) 127 128 #define BL2_BASE (0xffe00000) 129 #define BL2_LIMIT (0xffe1b000) 130 131 #define BL31_BASE (0x1000) 132 #define BL31_LIMIT (0x81000) 133 134 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 135 136 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 137 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 138 139 #define PLAT_SEC_WARM_ENTRY 0 140 141 /******************************************************************************* 142 * Platform specific page table and MMU setup constants 143 ******************************************************************************/ 144 #define MAX_XLAT_TABLES 8 145 #define MAX_MMAP_REGIONS 16 146 147 /******************************************************************************* 148 * Declarations and constants to access the mailboxes safely. Each mailbox is 149 * aligned on the biggest cache line size in the platform. This is known only 150 * to the platform as it might have a combination of integrated and external 151 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 152 * line at any cache level. They could belong to different cpus/clusters & 153 * get written while being protected by different locks causing corruption of 154 * a valid mailbox address. 155 ******************************************************************************/ 156 #define CACHE_WRITEBACK_SHIFT 6 157 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 158 159 #define PLAT_GIC_BASE (0xFFFC0000) 160 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 161 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 162 #define PLAT_GICR_BASE 0 163 164 /******************************************************************************* 165 * UART related constants 166 ******************************************************************************/ 167 #define PLAT_UART0_BASE (0xFFC02000) 168 #define PLAT_UART1_BASE (0xFFC02100) 169 170 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 171 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 172 173 #ifndef SIMICS_BUILD 174 #define PLAT_BAUDRATE (115200) 175 #define PLAT_UART_CLOCK (100000000) 176 177 #else 178 #define PLAT_BAUDRATE (4800) 179 #define PLAT_UART_CLOCK (76800) 180 181 #endif 182 183 /******************************************************************************* 184 * PHY related constants 185 ******************************************************************************/ 186 187 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 188 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 189 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 190 191 /******************************************************************************* 192 * System counter frequency related constants 193 ******************************************************************************/ 194 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 195 #define PLAT_SYS_COUNTER_CONVERT_TO_MHZ (1000000) 196 197 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 198 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 199 200 /* 201 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 202 * terminology. On a GICv2 system or mode, the lists will be merged and treated 203 * as Group 0 interrupts. 204 */ 205 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 206 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 207 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 208 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 209 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 210 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 211 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 212 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 213 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 214 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 215 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 216 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 217 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 218 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 219 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 220 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 221 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 222 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 223 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 224 225 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 226 227 #define MAX_IO_HANDLES 4 228 #define MAX_IO_DEVICES 4 229 #define MAX_IO_BLOCK_DEVICES 2 230 231 #ifndef __ASSEMBLER__ 232 struct socfpga_bl31_params { 233 param_header_t h; 234 image_info_t *bl31_image_info; 235 entry_point_info_t *bl32_ep_info; 236 image_info_t *bl32_image_info; 237 entry_point_info_t *bl33_ep_info; 238 image_info_t *bl33_image_info; 239 }; 240 #endif 241 242 #endif /* PLATFORM_DEF_H */ 243 244