1 /* 2 * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <sgi_sdei.h> 12 #include <sgi_soc_platform_def_v2.h> 13 14 #if (CSS_SGI_PLATFORM_VARIANT == 1) 15 #define PLAT_ARM_CLUSTER_COUNT U(8) 16 #elif (CSS_SGI_PLATFORM_VARIANT == 2) 17 #define PLAT_ARM_CLUSTER_COUNT U(4) 18 #else 19 #define PLAT_ARM_CLUSTER_COUNT U(16) 20 #endif 21 22 #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) 23 #define CSS_SGI_MAX_PE_PER_CPU U(1) 24 25 #define PLAT_CSS_MHU_BASE UL(0x2A920000) 26 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 27 28 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 29 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 30 31 /* TZC Related Constants */ 32 #define PLAT_ARM_TZC_BASE UL(0x10720000) 33 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 34 35 #define TZC400_OFFSET UL(0x1000000) 36 37 #if (CSS_SGI_PLATFORM_VARIANT == 1) 38 #define TZC400_COUNT U(2) 39 #elif (CSS_SGI_PLATFORM_VARIANT == 2) 40 #define TZC400_COUNT U(4) 41 #else 42 #define TZC400_COUNT U(8) 43 #endif 44 45 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 46 (n * TZC400_OFFSET)) 47 48 #define TZC_NSAID_ALL_AP U(0) 49 #define TZC_NSAID_PCI U(1) 50 #define TZC_NSAID_HDLCD0 U(2) 51 #define TZC_NSAID_DMA U(5) 52 #define TZC_NSAID_DMA2 U(8) 53 #define TZC_NSAID_CLCD U(7) 54 #define TZC_NSAID_AP U(9) 55 #define TZC_NSAID_VIRTIO U(15) 56 57 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 58 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ 59 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ 60 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ 61 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \ 62 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \ 63 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ 64 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ 65 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) 66 67 /* 68 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 69 */ 70 #ifdef __aarch64__ 71 #if (CSS_SGI_PLATFORM_VARIANT == 2) 72 #define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */ 73 #else 74 #define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */ 75 #endif 76 77 #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ 78 CSS_SGI_CHIP_COUNT) 79 #define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ 80 CSS_SGI_CHIP_COUNT) 81 #else 82 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 83 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 84 #endif 85 86 /* GIC related constants */ 87 #define PLAT_ARM_GICD_BASE UL(0x30000000) 88 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 89 90 /* Virtual address used by dynamic mem_protect for chunk_base */ 91 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) 92 93 #if (CSS_SGI_PLATFORM_VARIANT == 1) 94 #define PLAT_ARM_GICR_BASE UL(0x30100000) 95 #elif (CSS_SGI_PLATFORM_VARIANT == 3) 96 #define PLAT_ARM_GICR_BASE UL(0x30300000) 97 #else 98 #define PLAT_ARM_GICR_BASE UL(0x301C0000) 99 #endif 100 101 /* Interrupt priority level for shutdown/reboot */ 102 #define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY 103 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI) 104 105 /* 106 * Number of Secure Partitions supported. 107 * SPMC at EL3, uses this count to configure the maximum number of supported 108 * secure partitions. 109 */ 110 #define SECURE_PARTITION_COUNT 1 111 112 /* 113 * Number of NWd Partitions supported. 114 * SPMC at EL3, uses this count to configure the maximum number of supported 115 * nwld partitions. 116 */ 117 #define NS_PARTITION_COUNT 1 118 119 /* 120 * Number of Logical Partitions supported. 121 * SPMC at EL3, uses this count to configure the maximum number of supported 122 * logical partitions. 123 */ 124 #define MAX_EL3_LP_DESCS_COUNT 1 125 126 #endif /* PLATFORM_DEF_H */ 127
