1 /* 2 * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 #endif 58 59 /* 60 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 61 * max size of BL32 image. 62 */ 63 #if defined(SPD_spmd) 64 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 65 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 66 #endif 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* No SCP in FVP */ 72 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 73 74 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 75 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 76 77 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 78 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 79 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 80 81 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 82 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 83 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 84 85 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 86 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 87 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 88 89 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 90 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 91 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 92 93 /* Range of kernel DTB load address */ 94 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 95 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 96 97 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 98 FVP_DTB_DRAM_MAP_START, \ 99 FVP_DTB_DRAM_MAP_SIZE, \ 100 MT_MEMORY | MT_RO | MT_NS) 101 102 #if SPMC_AT_EL3 103 /* 104 * Number of Secure Partitions supported. 105 * SPMC at EL3, uses this count to configure the maximum number of supported 106 * secure partitions. 107 */ 108 #define SECURE_PARTITION_COUNT 1 109 110 /* 111 * Number of Normal World Partitions supported. 112 * SPMC at EL3, uses this count to configure the maximum number of supported 113 * NWd partitions. 114 */ 115 #define NS_PARTITION_COUNT 1 116 117 /* 118 * Number of Logical Partitions supported. 119 * SPMC at EL3, uses this count to configure the maximum number of supported 120 * logical partitions. 121 */ 122 #define MAX_EL3_LP_DESCS_COUNT 1 123 124 #endif /* SPMC_AT_EL3 */ 125 126 /* 127 * Load address of BL33 for this platform port 128 */ 129 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 130 131 #if TRANSFER_LIST 132 #define FW_HANDOFF_SIZE 0x4000 133 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - FW_HANDOFF_SIZE) 134 #endif 135 136 /* 137 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 138 * plat_arm_mmap array defined for each BL stage. 139 */ 140 #if defined(IMAGE_BL31) 141 # if SPM_MM 142 # define PLAT_ARM_MMAP_ENTRIES 10 143 # define MAX_XLAT_TABLES 9 144 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 145 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 146 # elif SPMC_AT_EL3 147 # define PLAT_ARM_MMAP_ENTRIES 13 148 # define MAX_XLAT_TABLES 11 149 # else 150 # define PLAT_ARM_MMAP_ENTRIES 9 151 # if USE_DEBUGFS 152 # if ENABLE_RME 153 # define MAX_XLAT_TABLES 9 154 # else 155 # define MAX_XLAT_TABLES 8 156 # endif 157 # else 158 # if ENABLE_RME 159 # define MAX_XLAT_TABLES 8 160 # elif DRTM_SUPPORT 161 # define MAX_XLAT_TABLES 8 162 # else 163 # define MAX_XLAT_TABLES 7 164 # endif 165 # endif 166 # endif 167 #elif defined(IMAGE_BL32) 168 # if SPMC_AT_EL3 169 # define PLAT_ARM_MMAP_ENTRIES 270 170 # define MAX_XLAT_TABLES 10 171 # else 172 # define PLAT_ARM_MMAP_ENTRIES 9 173 # define MAX_XLAT_TABLES 6 174 # endif 175 #elif !USE_ROMLIB 176 # if ENABLE_RME && defined(IMAGE_BL2) 177 # define PLAT_ARM_MMAP_ENTRIES 12 178 # define MAX_XLAT_TABLES 6 179 # else 180 # define PLAT_ARM_MMAP_ENTRIES 11 181 # define MAX_XLAT_TABLES 5 182 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 183 #else 184 # define PLAT_ARM_MMAP_ENTRIES 12 185 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 186 defined(IMAGE_BL2) && MEASURED_BOOT 187 # define MAX_XLAT_TABLES 7 188 # else 189 # define MAX_XLAT_TABLES 6 190 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 191 #endif 192 193 /* 194 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 195 * plus a little space for growth. 196 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 197 * area. 198 */ 199 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO 200 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 201 #else 202 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 203 #endif 204 205 /* 206 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 207 */ 208 209 #if USE_ROMLIB 210 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 211 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 212 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 213 #else 214 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 215 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 216 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 217 #endif 218 219 /* 220 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 221 * Maximum size of BL2 increases as Trusted SRAM size increases. 222 */ 223 #if CRYPTO_SUPPORT 224 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 225 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 226 (2 * PAGE_SIZE) - \ 227 FVP_BL2_ROMLIB_OPTIMIZATION) 228 #else 229 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 230 (3 * PAGE_SIZE) - \ 231 FVP_BL2_ROMLIB_OPTIMIZATION) 232 #endif 233 #elif ARM_BL31_IN_DRAM 234 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 235 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 236 #else 237 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 238 #endif 239 240 #if RESET_TO_BL31 241 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 242 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 243 ARM_SHARED_RAM_SIZE - \ 244 ARM_L0_GPT_SIZE) 245 #else 246 /* 247 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 248 * calculated using the current BL31 PROGBITS debug size plus the sizes of 249 * BL2 and BL1-RW. 250 * Size of the BL31 PROGBITS increases as the SRAM size increases. 251 */ 252 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 253 ARM_SHARED_RAM_SIZE - \ 254 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 255 #endif /* RESET_TO_BL31 */ 256 257 #ifndef __aarch64__ 258 #if RESET_TO_SP_MIN 259 /* Size of Trusted SRAM - the first 4KB of shared memory */ 260 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 261 ARM_SHARED_RAM_SIZE) 262 #else 263 /* 264 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 265 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 266 * BL2 and BL1-RW 267 */ 268 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 269 #endif /* RESET_TO_SP_MIN */ 270 #endif 271 272 /* 273 * Size of cacheable stacks 274 */ 275 #if defined(IMAGE_BL1) 276 # if CRYPTO_SUPPORT 277 # define PLATFORM_STACK_SIZE UL(0x1000) 278 # else 279 # define PLATFORM_STACK_SIZE UL(0x500) 280 # endif /* CRYPTO_SUPPORT */ 281 #elif defined(IMAGE_BL2) 282 # if CRYPTO_SUPPORT 283 # define PLATFORM_STACK_SIZE UL(0x1000) 284 # else 285 # define PLATFORM_STACK_SIZE UL(0x600) 286 # endif /* CRYPTO_SUPPORT */ 287 #elif defined(IMAGE_BL2U) 288 # define PLATFORM_STACK_SIZE UL(0x400) 289 #elif defined(IMAGE_BL31) 290 # if DRTM_SUPPORT 291 # define PLATFORM_STACK_SIZE UL(0x1000) 292 # else 293 # define PLATFORM_STACK_SIZE UL(0x800) 294 # endif /* DRTM_SUPPORT */ 295 #elif defined(IMAGE_BL32) 296 # if SPMC_AT_EL3 297 # define PLATFORM_STACK_SIZE UL(0x1000) 298 # else 299 # define PLATFORM_STACK_SIZE UL(0x440) 300 # endif /* SPMC_AT_EL3 */ 301 #elif defined(IMAGE_RMM) 302 # define PLATFORM_STACK_SIZE UL(0x440) 303 #endif 304 305 #define MAX_IO_DEVICES 3 306 #define MAX_IO_HANDLES 4 307 308 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 309 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 310 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 311 312 #if ARM_GPT_SUPPORT 313 /* 314 * Offset of the FIP in the GPT image. BL1 component uses this option 315 * as it does not load the partition table to get the FIP base 316 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 317 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 318 */ 319 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 320 #endif /* ARM_GPT_SUPPORT */ 321 322 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 323 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 324 325 /* 326 * PL011 related constants 327 */ 328 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 329 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 330 331 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 332 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 333 334 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 335 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 336 337 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 338 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 339 340 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 341 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 342 343 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 344 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 345 346 /* CCI related constants */ 347 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 348 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 349 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 350 351 /* CCI-500/CCI-550 on Base platform */ 352 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 353 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 354 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 355 356 /* CCN related constants. Only CCN 502 is currently supported */ 357 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 358 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 359 360 /* System timer related constants */ 361 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 362 363 /* Mailbox base address */ 364 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 365 366 367 /* TrustZone controller related constants 368 * 369 * Currently only filters 0 and 2 are connected on Base FVP. 370 * Filter 0 : CPU clusters (no access to DRAM by default) 371 * Filter 1 : not connected 372 * Filter 2 : LCDs (access to VRAM allowed by default) 373 * Filter 3 : not connected 374 * Programming unconnected filters will have no effect at the 375 * moment. These filter could, however, be connected in future. 376 * So care should be taken not to configure the unused filters. 377 * 378 * Allow only non-secure access to all DRAM to supported devices. 379 * Give access to the CPUs and Virtio. Some devices 380 * would normally use the default ID so allow that too. 381 */ 382 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 383 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 384 385 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 386 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 387 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 388 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 389 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 390 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 391 392 /* 393 * GIC related constants to cater for both GICv2 and GICv3 instances of an 394 * FVP. They could be overridden at runtime in case the FVP implements the 395 * legacy VE memory map. 396 */ 397 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 398 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 399 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 400 401 /* 402 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 403 * terminology. On a GICv2 system or mode, the lists will be merged and treated 404 * as Group 0 interrupts. 405 */ 406 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 407 ARM_G1S_IRQ_PROPS(grp), \ 408 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 409 GIC_INTR_CFG_LEVEL), \ 410 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 411 GIC_INTR_CFG_LEVEL) 412 413 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 414 415 #if SDEI_IN_FCONF 416 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 417 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 418 #else 419 #if PLATFORM_TEST_RAS_FFH 420 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 421 ARM_SDEI_PRIVATE_EVENTS, \ 422 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 423 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 424 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 425 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 426 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 427 #else 428 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 429 #endif 430 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 431 #endif 432 433 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 434 PLAT_SP_IMAGE_NS_BUF_SIZE) 435 436 #define PLAT_SP_PRI 0x20 437 438 /* 439 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 440 */ 441 #ifdef __aarch64__ 442 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 443 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 444 #else 445 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 446 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 447 #endif 448 449 /* 450 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 451 */ 452 #if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) 453 /* Account for additional measurements of secure partitions and SPM. */ 454 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 455 #else 456 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 457 #endif 458 459 /* 460 * Maximum size of Event Log buffer used for DRTM 461 */ 462 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 463 464 /* 465 * Number of MMAP entries used by DRTM implementation 466 */ 467 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 468 469 #endif /* PLATFORM_DEF_H */ 470
