1 /* 2 * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 #if ENABLE_RME 47 #define PLAT_ARM_RMM_BASE (RMM_BASE) 48 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 49 #endif 50 51 /* 52 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 53 * max size of BL32 image. 54 */ 55 #if defined(SPD_spmd) 56 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 57 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 58 #endif 59 60 /* virtual address used by dynamic mem_protect for chunk_base */ 61 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 62 63 /* No SCP in FVP */ 64 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 65 66 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 67 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 68 69 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 70 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 71 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 72 73 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 74 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 75 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 76 77 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 78 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 79 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 80 81 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 82 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 83 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 84 85 /* Range of kernel DTB load address */ 86 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 87 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 88 89 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 90 FVP_DTB_DRAM_MAP_START, \ 91 FVP_DTB_DRAM_MAP_SIZE, \ 92 MT_MEMORY | MT_RO | MT_NS) 93 94 #if SPMC_AT_EL3 95 /* 96 * Number of Secure Partitions supported. 97 * SPMC at EL3, uses this count to configure the maximum number of supported 98 * secure partitions. 99 */ 100 #define SECURE_PARTITION_COUNT 1 101 102 /* 103 * Number of Normal World Partitions supported. 104 * SPMC at EL3, uses this count to configure the maximum number of supported 105 * NWd partitions. 106 */ 107 #define NS_PARTITION_COUNT 1 108 109 /* 110 * Number of Logical Partitions supported. 111 * SPMC at EL3, uses this count to configure the maximum number of supported 112 * logical partitions. 113 */ 114 #define MAX_EL3_LP_DESCS_COUNT 1 115 116 #endif /* SPMC_AT_EL3 */ 117 118 /* 119 * Load address of BL33 for this platform port 120 */ 121 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 122 123 /* 124 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 125 * plat_arm_mmap array defined for each BL stage. 126 */ 127 #if defined(IMAGE_BL31) 128 # if SPM_MM 129 # define PLAT_ARM_MMAP_ENTRIES 10 130 # define MAX_XLAT_TABLES 9 131 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 132 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 133 # elif SPMC_AT_EL3 134 # define PLAT_ARM_MMAP_ENTRIES 13 135 # define MAX_XLAT_TABLES 11 136 # else 137 # define PLAT_ARM_MMAP_ENTRIES 9 138 # if USE_DEBUGFS 139 # if ENABLE_RME 140 # define MAX_XLAT_TABLES 9 141 # else 142 # define MAX_XLAT_TABLES 8 143 # endif 144 # else 145 # if ENABLE_RME 146 # define MAX_XLAT_TABLES 8 147 # else 148 # define MAX_XLAT_TABLES 7 149 # endif 150 # endif 151 # endif 152 #elif defined(IMAGE_BL32) 153 # if SPMC_AT_EL3 154 # define PLAT_ARM_MMAP_ENTRIES 270 155 # define MAX_XLAT_TABLES 10 156 # else 157 # define PLAT_ARM_MMAP_ENTRIES 9 158 # define MAX_XLAT_TABLES 6 159 # endif 160 #elif !USE_ROMLIB 161 # define PLAT_ARM_MMAP_ENTRIES 11 162 # define MAX_XLAT_TABLES 5 163 #else 164 # define PLAT_ARM_MMAP_ENTRIES 12 165 # define MAX_XLAT_TABLES 6 166 #endif 167 168 /* 169 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 170 * plus a little space for growth. 171 */ 172 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 173 174 /* 175 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 176 */ 177 178 #if USE_ROMLIB 179 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 180 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 181 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 182 #else 183 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 184 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 185 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 186 #endif 187 188 /* 189 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 190 * little space for growth. 191 */ 192 #if TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB 193 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 194 #elif CRYPTO_SUPPORT 195 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 196 #elif ARM_BL31_IN_DRAM 197 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 198 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 199 #else 200 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 201 #endif 202 203 #if RESET_TO_BL31 204 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 205 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 206 ARM_SHARED_RAM_SIZE - \ 207 ARM_L0_GPT_SIZE) 208 #else 209 /* 210 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 211 * calculated using the current BL31 PROGBITS debug size plus the sizes of 212 * BL2 and BL1-RW 213 */ 214 #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) 215 #endif /* RESET_TO_BL31 */ 216 217 #ifndef __aarch64__ 218 #if RESET_TO_SP_MIN 219 /* Size of Trusted SRAM - the first 4KB of shared memory */ 220 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 221 ARM_SHARED_RAM_SIZE) 222 #else 223 /* 224 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 225 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 226 * BL2 and BL1-RW 227 */ 228 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 229 #endif /* RESET_TO_SP_MIN */ 230 #endif 231 232 /* 233 * Size of cacheable stacks 234 */ 235 #if defined(IMAGE_BL1) 236 # if CRYPTO_SUPPORT 237 # define PLATFORM_STACK_SIZE UL(0x1000) 238 # else 239 # define PLATFORM_STACK_SIZE UL(0x500) 240 # endif /* CRYPTO_SUPPORT */ 241 #elif defined(IMAGE_BL2) 242 # if CRYPTO_SUPPORT 243 # define PLATFORM_STACK_SIZE UL(0x1000) 244 # else 245 # define PLATFORM_STACK_SIZE UL(0x600) 246 # endif /* CRYPTO_SUPPORT */ 247 #elif defined(IMAGE_BL2U) 248 # define PLATFORM_STACK_SIZE UL(0x400) 249 #elif defined(IMAGE_BL31) 250 # define PLATFORM_STACK_SIZE UL(0x800) 251 #elif defined(IMAGE_BL32) 252 # define PLATFORM_STACK_SIZE UL(0x440) 253 #elif defined(IMAGE_RMM) 254 # define PLATFORM_STACK_SIZE UL(0x440) 255 #endif 256 257 #define MAX_IO_DEVICES 3 258 #define MAX_IO_HANDLES 4 259 260 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 261 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 262 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 263 264 #if ARM_GPT_SUPPORT 265 /* 266 * Offset of the FIP in the GPT image. BL1 component uses this option 267 * as it does not load the partition table to get the FIP base 268 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 269 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 270 */ 271 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 272 #endif /* ARM_GPT_SUPPORT */ 273 274 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 275 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 276 277 /* 278 * PL011 related constants 279 */ 280 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 281 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 282 283 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 284 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 285 286 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 287 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 288 289 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 290 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 291 292 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 293 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 294 295 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 296 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 297 298 /* CCI related constants */ 299 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 300 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 301 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 302 303 /* CCI-500/CCI-550 on Base platform */ 304 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 305 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 306 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 307 308 /* CCN related constants. Only CCN 502 is currently supported */ 309 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 310 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 311 312 /* System timer related constants */ 313 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 314 315 /* Mailbox base address */ 316 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 317 318 319 /* TrustZone controller related constants 320 * 321 * Currently only filters 0 and 2 are connected on Base FVP. 322 * Filter 0 : CPU clusters (no access to DRAM by default) 323 * Filter 1 : not connected 324 * Filter 2 : LCDs (access to VRAM allowed by default) 325 * Filter 3 : not connected 326 * Programming unconnected filters will have no effect at the 327 * moment. These filter could, however, be connected in future. 328 * So care should be taken not to configure the unused filters. 329 * 330 * Allow only non-secure access to all DRAM to supported devices. 331 * Give access to the CPUs and Virtio. Some devices 332 * would normally use the default ID so allow that too. 333 */ 334 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 335 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 336 337 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 338 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 339 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 340 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 341 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 342 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 343 344 /* 345 * GIC related constants to cater for both GICv2 and GICv3 instances of an 346 * FVP. They could be overridden at runtime in case the FVP implements the 347 * legacy VE memory map. 348 */ 349 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 350 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 351 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 352 353 /* 354 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 355 * terminology. On a GICv2 system or mode, the lists will be merged and treated 356 * as Group 0 interrupts. 357 */ 358 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 359 ARM_G1S_IRQ_PROPS(grp), \ 360 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 361 GIC_INTR_CFG_LEVEL), \ 362 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 363 GIC_INTR_CFG_LEVEL) 364 365 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 366 367 #if SDEI_IN_FCONF 368 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 369 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 370 #else 371 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 372 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 373 #endif 374 375 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 376 PLAT_SP_IMAGE_NS_BUF_SIZE) 377 378 #define PLAT_SP_PRI PLAT_RAS_PRI 379 380 /* 381 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 382 */ 383 #ifdef __aarch64__ 384 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 385 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 386 #else 387 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 388 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 389 #endif 390 391 /* 392 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 393 */ 394 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 395 396 #endif /* PLATFORM_DEF_H */ 397
