1 /* 2 * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 #endif 58 59 /* 60 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 61 * max size of BL32 image. 62 */ 63 #if defined(SPD_spmd) 64 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 65 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 66 #endif 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* No SCP in FVP */ 72 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 73 74 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 75 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 76 77 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 78 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 79 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 80 81 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 82 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 83 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 84 85 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 86 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 87 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 88 89 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 90 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 91 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 92 93 /* Range of kernel DTB load address */ 94 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 95 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 96 97 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 98 FVP_DTB_DRAM_MAP_START, \ 99 FVP_DTB_DRAM_MAP_SIZE, \ 100 MT_MEMORY | MT_RO | MT_NS) 101 102 #if SPMC_AT_EL3 103 /* 104 * Number of Secure Partitions supported. 105 * SPMC at EL3, uses this count to configure the maximum number of supported 106 * secure partitions. 107 */ 108 #define SECURE_PARTITION_COUNT 1 109 110 /* 111 * Number of Normal World Partitions supported. 112 * SPMC at EL3, uses this count to configure the maximum number of supported 113 * NWd partitions. 114 */ 115 #define NS_PARTITION_COUNT 1 116 117 /* 118 * Number of Logical Partitions supported. 119 * SPMC at EL3, uses this count to configure the maximum number of supported 120 * logical partitions. 121 */ 122 #define MAX_EL3_LP_DESCS_COUNT 1 123 124 #endif /* SPMC_AT_EL3 */ 125 126 /* 127 * Load address of BL33 for this platform port 128 */ 129 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 130 131 /* 132 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 133 * plat_arm_mmap array defined for each BL stage. 134 */ 135 #if defined(IMAGE_BL31) 136 # if SPM_MM 137 # define PLAT_ARM_MMAP_ENTRIES 10 138 # define MAX_XLAT_TABLES 9 139 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 140 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 141 # elif SPMC_AT_EL3 142 # define PLAT_ARM_MMAP_ENTRIES 13 143 # define MAX_XLAT_TABLES 11 144 # else 145 # define PLAT_ARM_MMAP_ENTRIES 9 146 # if USE_DEBUGFS 147 # if ENABLE_RME 148 # define MAX_XLAT_TABLES 9 149 # else 150 # define MAX_XLAT_TABLES 8 151 # endif 152 # else 153 # if ENABLE_RME 154 # define MAX_XLAT_TABLES 8 155 # elif DRTM_SUPPORT 156 # define MAX_XLAT_TABLES 8 157 # else 158 # define MAX_XLAT_TABLES 7 159 # endif 160 # endif 161 # endif 162 #elif defined(IMAGE_BL32) 163 # if SPMC_AT_EL3 164 # define PLAT_ARM_MMAP_ENTRIES 270 165 # define MAX_XLAT_TABLES 10 166 # else 167 # define PLAT_ARM_MMAP_ENTRIES 9 168 # define MAX_XLAT_TABLES 6 169 # endif 170 #elif !USE_ROMLIB 171 # define PLAT_ARM_MMAP_ENTRIES 11 172 # define MAX_XLAT_TABLES 5 173 #else 174 # define PLAT_ARM_MMAP_ENTRIES 12 175 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 176 defined(IMAGE_BL2) && MEASURED_BOOT 177 # define MAX_XLAT_TABLES 7 178 # else 179 # define MAX_XLAT_TABLES 6 180 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 181 #endif 182 183 /* 184 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 185 * plus a little space for growth. 186 */ 187 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 188 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 189 #else 190 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 191 #endif 192 193 /* 194 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 195 */ 196 197 #if USE_ROMLIB 198 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 199 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 200 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 201 #else 202 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 203 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 204 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 205 #endif 206 207 /* 208 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 209 * little space for growth. 210 */ 211 #if CRYPTO_SUPPORT 212 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 213 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 214 #else 215 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 216 #endif 217 #elif ARM_BL31_IN_DRAM 218 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 219 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 220 #else 221 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 222 #endif 223 224 #if RESET_TO_BL31 225 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 226 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 227 ARM_SHARED_RAM_SIZE - \ 228 ARM_L0_GPT_SIZE) 229 #else 230 /* 231 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 232 * calculated using the current BL31 PROGBITS debug size plus the sizes of 233 * BL2 and BL1-RW 234 */ 235 #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) 236 #endif /* RESET_TO_BL31 */ 237 238 #ifndef __aarch64__ 239 #if RESET_TO_SP_MIN 240 /* Size of Trusted SRAM - the first 4KB of shared memory */ 241 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 242 ARM_SHARED_RAM_SIZE) 243 #else 244 /* 245 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 246 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 247 * BL2 and BL1-RW 248 */ 249 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 250 #endif /* RESET_TO_SP_MIN */ 251 #endif 252 253 /* 254 * Size of cacheable stacks 255 */ 256 #if defined(IMAGE_BL1) 257 # if CRYPTO_SUPPORT 258 # define PLATFORM_STACK_SIZE UL(0x1000) 259 # else 260 # define PLATFORM_STACK_SIZE UL(0x500) 261 # endif /* CRYPTO_SUPPORT */ 262 #elif defined(IMAGE_BL2) 263 # if CRYPTO_SUPPORT 264 # define PLATFORM_STACK_SIZE UL(0x1000) 265 # else 266 # define PLATFORM_STACK_SIZE UL(0x600) 267 # endif /* CRYPTO_SUPPORT */ 268 #elif defined(IMAGE_BL2U) 269 # define PLATFORM_STACK_SIZE UL(0x400) 270 #elif defined(IMAGE_BL31) 271 # if DRTM_SUPPORT 272 # define PLATFORM_STACK_SIZE UL(0x1000) 273 # else 274 # define PLATFORM_STACK_SIZE UL(0x800) 275 # endif /* DRTM_SUPPORT */ 276 #elif defined(IMAGE_BL32) 277 # if SPMC_AT_EL3 278 # define PLATFORM_STACK_SIZE UL(0x1000) 279 # else 280 # define PLATFORM_STACK_SIZE UL(0x440) 281 # endif /* SPMC_AT_EL3 */ 282 #elif defined(IMAGE_RMM) 283 # define PLATFORM_STACK_SIZE UL(0x440) 284 #endif 285 286 #define MAX_IO_DEVICES 3 287 #define MAX_IO_HANDLES 4 288 289 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 290 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 291 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 292 293 #if ARM_GPT_SUPPORT 294 /* 295 * Offset of the FIP in the GPT image. BL1 component uses this option 296 * as it does not load the partition table to get the FIP base 297 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 298 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 299 */ 300 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 301 #endif /* ARM_GPT_SUPPORT */ 302 303 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 304 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 305 306 /* 307 * PL011 related constants 308 */ 309 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 310 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 311 312 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 313 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 314 315 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 316 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 317 318 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 319 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 320 321 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 322 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 323 324 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 325 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 326 327 /* CCI related constants */ 328 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 329 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 330 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 331 332 /* CCI-500/CCI-550 on Base platform */ 333 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 334 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 335 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 336 337 /* CCN related constants. Only CCN 502 is currently supported */ 338 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 339 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 340 341 /* System timer related constants */ 342 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 343 344 /* Mailbox base address */ 345 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 346 347 348 /* TrustZone controller related constants 349 * 350 * Currently only filters 0 and 2 are connected on Base FVP. 351 * Filter 0 : CPU clusters (no access to DRAM by default) 352 * Filter 1 : not connected 353 * Filter 2 : LCDs (access to VRAM allowed by default) 354 * Filter 3 : not connected 355 * Programming unconnected filters will have no effect at the 356 * moment. These filter could, however, be connected in future. 357 * So care should be taken not to configure the unused filters. 358 * 359 * Allow only non-secure access to all DRAM to supported devices. 360 * Give access to the CPUs and Virtio. Some devices 361 * would normally use the default ID so allow that too. 362 */ 363 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 364 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 365 366 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 367 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 368 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 369 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 370 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 371 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 372 373 /* 374 * GIC related constants to cater for both GICv2 and GICv3 instances of an 375 * FVP. They could be overridden at runtime in case the FVP implements the 376 * legacy VE memory map. 377 */ 378 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 379 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 380 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 381 382 /* 383 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 384 * terminology. On a GICv2 system or mode, the lists will be merged and treated 385 * as Group 0 interrupts. 386 */ 387 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 388 ARM_G1S_IRQ_PROPS(grp), \ 389 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 390 GIC_INTR_CFG_LEVEL), \ 391 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 392 GIC_INTR_CFG_LEVEL) 393 394 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 395 396 #if SDEI_IN_FCONF 397 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 398 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 399 #else 400 #if PLATFORM_TEST_RAS_FFH 401 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 402 ARM_SDEI_PRIVATE_EVENTS, \ 403 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 404 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 405 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 406 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 407 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 408 #else 409 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 410 #endif 411 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 412 #endif 413 414 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 415 PLAT_SP_IMAGE_NS_BUF_SIZE) 416 417 #define PLAT_SP_PRI 0x20 418 419 /* 420 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 421 */ 422 #ifdef __aarch64__ 423 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 424 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 425 #else 426 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 427 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 428 #endif 429 430 /* 431 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 432 */ 433 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 434 435 /* 436 * Maximum size of Event Log buffer used for DRTM 437 */ 438 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 439 440 /* 441 * Number of MMAP entries used by DRTM implementation 442 */ 443 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 444 445 #endif /* PLATFORM_DEF_H */ 446
