1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2024 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_pit.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.pit"
14 #endif
15
16 /*******************************************************************************
17 * Prototypes
18 ******************************************************************************/
19 /*!
20 * @brief Gets the instance from the base address to be used to gate or ungate the module clock
21 *
22 * @param base PIT peripheral base address
23 *
24 * @return The PIT instance
25 */
26 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
27 static uint32_t PIT_GetInstance(PIT_Type *base);
28 #endif
29
30 /*******************************************************************************
31 * Variables
32 ******************************************************************************/
33 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
34 /*! @brief Pointers to PIT bases for each instance. */
35 static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
36
37 /*! @brief Pointers to PIT clocks for each instance. */
38 static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
39 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
40
41 /*******************************************************************************
42 * Code
43 ******************************************************************************/
44 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
PIT_GetInstance(PIT_Type * base)45 static uint32_t PIT_GetInstance(PIT_Type *base)
46 {
47 uint32_t instance;
48
49 /* Find the instance index from base address mappings. */
50 for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
51 {
52 if (s_pitBases[instance] == base)
53 {
54 break;
55 }
56 }
57
58 assert(instance < ARRAY_SIZE(s_pitBases));
59
60 return instance;
61 }
62 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
63
64 /*!
65 * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
66 *
67 * note This API should be called at the beginning of the application using the PIT driver.
68 *
69 * param base PIT peripheral base address
70 * param config Pointer to the user's PIT config structure
71 */
PIT_Init(PIT_Type * base,const pit_config_t * config)72 void PIT_Init(PIT_Type *base, const pit_config_t *config)
73 {
74 assert(NULL != config);
75
76 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
77 /* Ungate the PIT clock*/
78 CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
79 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
80
81 #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
82 #if defined(FSL_FEATURE_PIT_HAS_ERRATA_7914) && FSL_FEATURE_PIT_HAS_ERRATA_7914
83 /*
84 * If a write to the MCR[MDIS] bit occurs within two bus clock cycles of enabling the PIT clock
85 * in the SIM_CG register, the write will be ignored and the PIT will fail to enable.
86 * Insert a read of the MCR register before writing to the MCR register. This guarantees a minimum
87 * delay of two bus clocks to guarantee the write is not ignored.
88 */
89 (void)base->MCR;
90 #endif
91 /* Enable PIT timers */
92 base->MCR &= ~PIT_MCR_MDIS_MASK;
93 #endif
94
95 #if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT)
96 /* Clear all status bits for all channels to make sure the status of all TCTRL registers is clean. */
97 for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++)
98 {
99 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK);
100 }
101 #endif /* FSL_FEATURE_PIT_TIMER_COUNT */
102
103 /* Config timer operation when in debug mode */
104 if (true == config->enableRunInDebug)
105 {
106 base->MCR &= ~PIT_MCR_FRZ_MASK;
107 }
108 else
109 {
110 base->MCR |= PIT_MCR_FRZ_MASK;
111 }
112 }
113
114 /*!
115 * brief Gates the PIT clock and disables the PIT module.
116 *
117 * param base PIT peripheral base address
118 */
PIT_Deinit(PIT_Type * base)119 void PIT_Deinit(PIT_Type *base)
120 {
121 #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
122 /* Disable PIT timers */
123 base->MCR |= PIT_MCR_MDIS_MASK;
124 #endif
125
126 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
127 /* Gate the PIT clock*/
128 CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
129 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
130 }
131
132 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
133
134 /*!
135 * brief Reads the current lifetime counter value.
136 *
137 * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
138 * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
139 * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
140 * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
141 * has the value of timer 0.
142 *
143 * param base PIT peripheral base address
144 *
145 * return Current lifetime timer value
146 */
PIT_GetLifetimeTimerCount(PIT_Type * base)147 uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
148 {
149 uint32_t valueH = 0U;
150 uint32_t valueL = 0U;
151
152 /* LTMR64H should be read before LTMR64L */
153 valueH = base->LTMR64H;
154 valueL = base->LTMR64L;
155
156 return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
157 }
158
159 #endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
160
