1 /* 2 * Copyright (c) 2021-2023 IoT.bzh 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ 9 10 /** 11 * @brief Utility macro to build IPSR property entry. 12 * IPSR: Peripheral Function Select Register 13 * Each IPSR bank can hold 8 cellules of 4 bits coded function. 14 * 15 * @param bank the IPSR register bank. 16 * @param shift the bit shift for this alternate function. 17 * @param func the 4 bits encoded alternate function. 18 * 19 * Function code [ 0 : 3 ] 20 * Function shift [ 4 : 8 ] 21 * Empty [ 9 ] 22 * IPSR bank [ 10 : 14 ] 23 * Register index [ 15 : 17 ] (S4 only) 24 */ 25 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func)) 26 27 /* Arbitrary number to encode non capable gpio pin */ 28 #define PIN_NOGPSR_START 1024U 29 30 /** 31 * @brief Utility macro to encode a GPIO capable pin 32 * 33 * @param bank the GPIO bank 34 * @param pin the pin within the GPIO bank (0..31) 35 */ 36 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) 37 38 /** 39 * @brief Utility macro to encode a non capable GPIO pin 40 * 41 * @param pin the encoded pin number 42 */ 43 #define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin) 44 45 /* Renesas Gen4 has IPSR registers at different base address 46 * reg is here an index for the base address. 47 * Each base address has 4 IPSR banks. 48 */ 49 #define IPnSR(bank, reg, shift, func) \ 50 IPSR(((reg) << 5U) | (bank), shift, func) 51 52 #define IP0SR0(shift, func) IPnSR(0, 0, shift, func) 53 #define IP1SR0(shift, func) IPnSR(1, 0, shift, func) 54 #define IP2SR0(shift, func) IPnSR(2, 0, shift, func) 55 #define IP3SR0(shift, func) IPnSR(3, 0, shift, func) 56 #define IP0SR1(shift, func) IPnSR(0, 1, shift, func) 57 #define IP1SR1(shift, func) IPnSR(1, 1, shift, func) 58 #define IP2SR1(shift, func) IPnSR(2, 1, shift, func) 59 #define IP3SR1(shift, func) IPnSR(3, 1, shift, func) 60 #define IP0SR2(shift, func) IPnSR(0, 2, shift, func) 61 #define IP1SR2(shift, func) IPnSR(1, 2, shift, func) 62 #define IP2SR2(shift, func) IPnSR(2, 2, shift, func) 63 #define IP3SR2(shift, func) IPnSR(3, 2, shift, func) 64 #define IP0SR3(shift, func) IPnSR(0, 3, shift, func) 65 #define IP1SR3(shift, func) IPnSR(1, 3, shift, func) 66 #define IP2SR3(shift, func) IPnSR(2, 3, shift, func) 67 #define IP3SR3(shift, func) IPnSR(3, 3, shift, func) 68 #define IP0SR4(shift, func) IPnSR(0, 4, shift, func) 69 #define IP1SR4(shift, func) IPnSR(1, 4, shift, func) 70 #define IP2SR4(shift, func) IPnSR(2, 4, shift, func) 71 #define IP3SR4(shift, func) IPnSR(3, 4, shift, func) 72 #define IP0SR5(shift, func) IPnSR(0, 5, shift, func) 73 #define IP1SR5(shift, func) IPnSR(1, 5, shift, func) 74 #define IP2SR5(shift, func) IPnSR(2, 5, shift, func) 75 #define IP3SR5(shift, func) IPnSR(3, 5, shift, func) 76 #define IP0SR6(shift, func) IPnSR(0, 6, shift, func) 77 #define IP1SR6(shift, func) IPnSR(1, 6, shift, func) 78 #define IP2SR6(shift, func) IPnSR(2, 6, shift, func) 79 #define IP3SR6(shift, func) IPnSR(3, 6, shift, func) 80 #define IP0SR7(shift, func) IPnSR(0, 7, shift, func) 81 #define IP1SR7(shift, func) IPnSR(1, 7, shift, func) 82 #define IP2SR7(shift, func) IPnSR(2, 7, shift, func) 83 #define IP3SR7(shift, func) IPnSR(3, 7, shift, func) 84 85 /** 86 * @brief Macro to define a dummy IPSR flag for a pin 87 * 88 * This macro is used to define a dummy IPSR flag for a pin in the R-Car PFC 89 * driver. It is intended for pins that do not have a specific function 90 * defined in IPSR but always act as a peripheral. The dummy IPSR flag ensures 91 * that the driver sets the 'peripheral' bit for such pins. 92 * 93 * @see RCAR_PIN_FLAGS_FUNC_DUMMY 94 */ 95 #define IPSR_DUMMY IPnSR(0x1f, 7, 0x1f, 0xf) 96 97 #define PIN_VOLTAGE_NONE 0 98 #define PIN_VOLTAGE_1P8V 1 99 #define PIN_VOLTAGE_3P3V 2 100 101 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ */ 102
