1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_pint.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.pint"
14 #endif
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
21 /*! @brief Irq number array */
22 static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS +
23 FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
24
25 /*! @brief Callback function array for SECPINT(s). */
26 static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS];
27 #else
28 /*! @brief Irq number array */
29 static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
30 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
31
32 /*! @brief Callback function array for PINT(s). */
33 static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
34
35 /*******************************************************************************
36 * Code
37 ******************************************************************************/
38
39 /*!
40 * brief Initialize PINT peripheral.
41
42 * This function initializes the PINT peripheral and enables the clock.
43 *
44 * param base Base address of the PINT peripheral.
45 *
46 * retval None.
47 */
PINT_Init(PINT_Type * base)48 void PINT_Init(PINT_Type *base)
49 {
50 uint32_t i;
51 uint32_t pmcfg = 0;
52 uint8_t pintcount = 0;
53 assert(base != NULL);
54
55 if (base == PINT)
56 {
57 pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS;
58 /* clear PINT callback array*/
59 for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
60 {
61 s_pintCallback[i] = NULL;
62 }
63 }
64 else
65 {
66 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
67 pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS;
68 /* clear SECPINT callback array*/
69 for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
70 {
71 s_secpintCallback[i] = NULL;
72 }
73 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
74 }
75
76 /* Disable all bit slices for pint*/
77 for (i = 0; i < pintcount; i++)
78 {
79 pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
80 }
81
82 #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
83
84 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
85 /* Enable the clock. */
86 CLOCK_EnableClock(kCLOCK_GpioInt);
87 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
88 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
89 /* Reset the module. */
90 RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
91 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
92
93 #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
94
95 if (base == PINT)
96 {
97 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
98 /* Enable the clock. */
99 CLOCK_EnableClock(kCLOCK_Gpio0);
100 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
101 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
102 /* Reset the module. */
103 RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
104 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
105 }
106 else
107 {
108 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
109 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
110 /* Enable the clock. */
111 CLOCK_EnableClock(kCLOCK_Gpio_Sec);
112 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
113 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
114 /* Reset the module. */
115 RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
116 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
117 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
118 }
119
120 #else
121
122 if (base == PINT)
123 {
124 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
125 /* Enable the clock. */
126 CLOCK_EnableClock(kCLOCK_Pint);
127 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
128 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
129 /* Reset the module. */
130 RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
131 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
132 }
133 else
134 {
135 /* if need config SECURE PINT device,then enable secure pint interrupt clock */
136 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
137 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
138 /* Enable the clock. */
139 CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int);
140 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
141 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
142 /* Reset the module. */
143 RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
144 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
145 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
146 }
147 #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
148
149 /* Disable all pattern match bit slices */
150 base->PMCFG = pmcfg;
151 }
152
153 /*!
154 * brief Configure PINT peripheral pin interrupt.
155
156 * This function configures a given pin interrupt.
157 *
158 * param base Base address of the PINT peripheral.
159 * param intr Pin interrupt.
160 * param enable Selects detection logic.
161 * param callback Callback.
162 *
163 * retval None.
164 */
PINT_PinInterruptConfig(PINT_Type * base,pint_pin_int_t intr,pint_pin_enable_t enable,pint_cb_t callback)165 void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
166 {
167 assert(base != NULL);
168
169 /* Clear Rise and Fall flags first */
170 PINT_PinInterruptClrRiseFlag(base, intr);
171 PINT_PinInterruptClrFallFlag(base, intr);
172
173 /* Security PINT uses additional callback array */
174 if (base == PINT)
175 {
176 s_pintCallback[intr] = callback;
177 }
178 else
179 {
180 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
181 s_secpintCallback[intr] = callback;
182 #endif
183 }
184
185 /* select level or edge sensitive */
186 base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) |
187 ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U);
188
189 /* enable rising or level interrupt */
190 if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U)
191 {
192 base->SIENR = 1UL << (uint32_t)intr;
193 }
194 else
195 {
196 base->CIENR = 1UL << (uint32_t)intr;
197 }
198
199 /* Enable falling or select high level */
200 if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U)
201 {
202 base->SIENF = 1UL << (uint32_t)intr;
203 }
204 else
205 {
206 base->CIENF = 1UL << (uint32_t)intr;
207 }
208 }
209
210 /*!
211 * brief Get PINT peripheral pin interrupt configuration.
212
213 * This function returns the configuration of a given pin interrupt.
214 *
215 * param base Base address of the PINT peripheral.
216 * param pintr Pin interrupt.
217 * param enable Pointer to store the detection logic.
218 * param callback Callback.
219 *
220 * retval None.
221 */
PINT_PinInterruptGetConfig(PINT_Type * base,pint_pin_int_t pintr,pint_pin_enable_t * enable,pint_cb_t * callback)222 void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
223 {
224 uint32_t mask;
225 bool level;
226
227 assert(base != NULL);
228
229 *enable = kPINT_PinIntEnableNone;
230 level = false;
231
232 mask = 1UL << (uint32_t)pintr;
233 if ((base->ISEL & mask) != 0U)
234 {
235 /* Pin interrupt is level sensitive */
236 level = true;
237 }
238
239 if ((base->IENR & mask) != 0U)
240 {
241 if (level)
242 {
243 /* Level interrupt is enabled */
244 *enable = kPINT_PinIntEnableLowLevel;
245 }
246 else
247 {
248 /* Rising edge interrupt */
249 *enable = kPINT_PinIntEnableRiseEdge;
250 }
251 }
252
253 if ((base->IENF & mask) != 0U)
254 {
255 if (level)
256 {
257 /* Level interrupt is active high */
258 *enable = kPINT_PinIntEnableHighLevel;
259 }
260 else
261 {
262 /* Either falling or both edge */
263 if (*enable == kPINT_PinIntEnableRiseEdge)
264 {
265 /* Rising and faling edge */
266 *enable = kPINT_PinIntEnableBothEdges;
267 }
268 else
269 {
270 /* Falling edge */
271 *enable = kPINT_PinIntEnableFallEdge;
272 }
273 }
274 }
275
276 /* Security PINT uses additional callback array */
277 if (base == PINT)
278 {
279 *callback = s_pintCallback[pintr];
280 }
281 else
282 {
283 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
284 *callback = s_secpintCallback[pintr];
285 #endif
286 }
287 }
288
289 /*!
290 * brief Configure PINT pattern match.
291
292 * This function configures a given pattern match bit slice.
293 *
294 * param base Base address of the PINT peripheral.
295 * param bslice Pattern match bit slice number.
296 * param cfg Pointer to bit slice configuration.
297 *
298 * retval None.
299 */
PINT_PatternMatchConfig(PINT_Type * base,pint_pmatch_bslice_t bslice,pint_pmatch_cfg_t * cfg)300 void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
301 {
302 uint32_t src_shift;
303 uint32_t cfg_shift;
304 uint32_t pmcfg;
305 uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;
306 uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;
307
308 assert(base != NULL);
309
310 src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);
311 cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);
312
313 /* Input source selection for selected bit slice */
314 base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift);
315
316 /* Bit slice configuration */
317 pmcfg = base->PMCFG;
318 pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift);
319
320 /* If end point is true, enable the bits */
321 if ((uint32_t)bslice != 7UL)
322 {
323 if (cfg->end_point)
324 {
325 pmcfg |= (1UL << (uint32_t)bslice);
326 }
327 else
328 {
329 pmcfg &= ~(1UL << (uint32_t)bslice);
330 }
331 }
332
333 base->PMCFG = pmcfg;
334
335 /* Save callback pointer */
336 if (base == PINT)
337 {
338 if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS)
339 {
340 s_pintCallback[bslice] = cfg->callback;
341 }
342 }
343 else
344 {
345 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
346 if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
347 {
348 s_secpintCallback[bslice] = cfg->callback;
349 }
350 #endif
351 }
352 }
353
354 /*!
355 * brief Get PINT pattern match configuration.
356
357 * This function returns the configuration of a given pattern match bit slice.
358 *
359 * param base Base address of the PINT peripheral.
360 * param bslice Pattern match bit slice number.
361 * param cfg Pointer to bit slice configuration.
362 *
363 * retval None.
364 */
PINT_PatternMatchGetConfig(PINT_Type * base,pint_pmatch_bslice_t bslice,pint_pmatch_cfg_t * cfg)365 void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
366 {
367 uint32_t src_shift;
368 uint32_t cfg_shift;
369 uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;
370 uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;
371
372 assert(base != NULL);
373
374 src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);
375 cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);
376
377 cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift);
378 cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift);
379
380 if ((uint32_t)bslice == 7U)
381 {
382 cfg->end_point = true;
383 }
384 else
385 {
386 cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false;
387 }
388
389 if (base == PINT)
390 {
391 if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS)
392 {
393 cfg->callback = s_pintCallback[bslice];
394 }
395 }
396 else
397 {
398 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
399 if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
400 {
401 cfg->callback = s_secpintCallback[bslice];
402 }
403 #endif
404 }
405 }
406
407 /*!
408 * brief Reset pattern match detection logic.
409
410 * This function resets the pattern match detection logic if any of the product term is matching.
411 *
412 * param base Base address of the PINT peripheral.
413 *
414 * retval pmstatus Each bit position indicates the match status of corresponding bit slice.
415 * = 0 Match was detected. = 1 Match was not detected.
416 */
PINT_PatternMatchResetDetectLogic(PINT_Type * base)417 uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
418 {
419 uint32_t pmctrl;
420 uint32_t pmstatus;
421 uint32_t pmsrc;
422
423 pmctrl = base->PMCTRL;
424 pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
425 if (pmstatus != 0UL)
426 {
427 /* Reset Pattern match engine detection logic */
428 pmsrc = base->PMSRC;
429 base->PMSRC = pmsrc;
430 }
431 return (pmstatus);
432 }
433
434 /*!
435 * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive.
436
437 * This function clears the selected pin interrupt status.
438 *
439 * @param base Base address of the PINT peripheral.
440 * @param pintr Pin interrupt.
441 *
442 * @retval None.
443 */
PINT_PinInterruptClrStatus(PINT_Type * base,pint_pin_int_t pintr)444 void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
445 {
446 uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr);
447 uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr);
448
449 /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */
450 if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))
451 {
452 base->IST = (1UL << (uint32_t)pintr);
453 }
454 }
455
456 /*!
457 * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive.
458
459 * This function clears the status of all pin interrupts.
460 *
461 * @param base Base address of the PINT peripheral.
462 *
463 * @retval None.
464 */
PINT_PinInterruptClrStatusAll(PINT_Type * base)465 void PINT_PinInterruptClrStatusAll(PINT_Type *base)
466 {
467 uint32_t pinIntMode = 0;
468 uint32_t pinIntStatus = 0;
469 uint32_t pinIntCount = 0;
470 uint32_t mask = 0;
471 uint32_t i;
472
473 if (base == PINT)
474 {
475 pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS;
476 }
477 else
478 {
479 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
480 pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS;
481 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
482 }
483
484 for (i = 0; i < pinIntCount; i++)
485 {
486 pinIntMode = base->ISEL & (1UL << i);
487 pinIntStatus = base->IST & (1UL << i);
488
489 /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */
490 if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))
491 {
492 mask |= 1UL << i;
493 }
494 }
495
496 base->IST = mask;
497 }
498
499 /*!
500 * brief Enable callback.
501
502 * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
503 * as soon as they are enabled, the callback function is not enabled until this function is called.
504 *
505 * param base Base address of the PINT peripheral.
506 *
507 * retval None.
508 */
PINT_EnableCallback(PINT_Type * base)509 void PINT_EnableCallback(PINT_Type *base)
510 {
511 uint32_t i;
512
513 assert(base != NULL);
514
515 if (base == PINT)
516 {
517 #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
518 for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
519 {
520 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
521 }
522 NVIC_ClearPendingIRQ(s_pintIRQ[0]);
523 (void)EnableIRQ(s_pintIRQ[0]);
524 #else
525 for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
526 {
527 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
528 NVIC_ClearPendingIRQ(s_pintIRQ[i]);
529 (void)EnableIRQ(s_pintIRQ[i]);
530 }
531 #endif
532 }
533 else
534 {
535 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
536 for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
537 {
538 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
539 NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
540 (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
541 }
542 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
543 }
544 }
545
546 /*!
547 * brief enable callback by pin index.
548
549 * This function enables callback by pin index instead of enabling all pins.
550 *
551 * param base Base address of the peripheral.
552 * param pinIdx pin index.
553 *
554 * retval None.
555 */
PINT_EnableCallbackByIndex(PINT_Type * base,pint_pin_int_t pintIdx)556 void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
557 {
558 assert(base != NULL);
559
560 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
561
562 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
563 /* Get the right security pint irq index in array */
564 if (base == SECPINT)
565 {
566 pintIdx =
567 (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS);
568 }
569 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
570
571 #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
572 NVIC_ClearPendingIRQ(s_pintIRQ[0]);
573 (void)EnableIRQ(s_pintIRQ[0]);
574 #else
575 NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
576 (void)EnableIRQ(s_pintIRQ[pintIdx]);
577 #endif
578 }
579
580 /*!
581 * brief Disable callback.
582
583 * This function disables the interrupt for the selected PINT peripheral. Although the pins are still
584 * being monitored but the callback function is not called.
585 *
586 * param base Base address of the peripheral.
587 *
588 * retval None.
589 */
PINT_DisableCallback(PINT_Type * base)590 void PINT_DisableCallback(PINT_Type *base)
591 {
592 uint32_t i;
593
594 assert(base != NULL);
595
596 if (base == PINT)
597 {
598 #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
599 (void)DisableIRQ(s_pintIRQ[0]);
600 for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
601 {
602 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
603 }
604 NVIC_ClearPendingIRQ(s_pintIRQ[0]);
605 #else
606 for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
607 {
608 (void)DisableIRQ(s_pintIRQ[i]);
609 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
610 NVIC_ClearPendingIRQ(s_pintIRQ[i]);
611 }
612 #endif
613 }
614 else
615 {
616 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
617 for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
618 {
619 (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
620 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
621 NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
622 }
623 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
624 }
625 }
626
627 /*!
628 * brief disable callback by pin index.
629
630 * This function disables callback by pin index instead of disabling all pins.
631 *
632 * param base Base address of the peripheral.
633 * param pinIdx pin index.
634 *
635 * retval None.
636 */
PINT_DisableCallbackByIndex(PINT_Type * base,pint_pin_int_t pintIdx)637 void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
638 {
639 assert(base != NULL);
640
641 if (base == PINT)
642 {
643 #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1)
644 (void)DisableIRQ(s_pintIRQ[0]);
645 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
646 NVIC_ClearPendingIRQ(s_pintIRQ[0]);
647 #else
648 (void)DisableIRQ(s_pintIRQ[pintIdx]);
649 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
650 NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
651 #endif
652 }
653 else
654 {
655 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
656 (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
657 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
658 NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]);
659 #endif
660 }
661 }
662
663 /*!
664 * brief Deinitialize PINT peripheral.
665
666 * This function disables the PINT clock.
667 *
668 * param base Base address of the PINT peripheral.
669 *
670 * retval None.
671 */
PINT_Deinit(PINT_Type * base)672 void PINT_Deinit(PINT_Type *base)
673 {
674 uint32_t i;
675
676 assert(base != NULL);
677
678 /* Cleanup */
679 PINT_DisableCallback(base);
680 if (base == PINT)
681 {
682 /* clear PINT callback array*/
683 for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
684 {
685 s_pintCallback[i] = NULL;
686 }
687 }
688 else
689 {
690 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
691 /* clear SECPINT callback array */
692 for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
693 {
694 s_secpintCallback[i] = NULL;
695 }
696 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
697 }
698
699 #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
700
701 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
702 /* Enable the clock. */
703 CLOCK_DisableClock(kCLOCK_GpioInt);
704 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
705 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
706 /* Reset the module. */
707 RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
708 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
709
710 #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
711
712 if (base == PINT)
713 {
714 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
715 /* Enable the clock. */
716 CLOCK_DisableClock(kCLOCK_Gpio0);
717 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
718 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
719 /* Reset the module. */
720 RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
721 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
722 }
723 else
724 {
725 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
726 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
727 /* Enable the clock. */
728 CLOCK_DisableClock(kCLOCK_Gpio_Sec);
729 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
730 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
731 /* Reset the module. */
732 RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
733 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
734 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
735 }
736
737 #else
738
739 if (base == PINT)
740 {
741 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
742 /* Enable the clock. */
743 CLOCK_DisableClock(kCLOCK_Pint);
744 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
745 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
746 /* Reset the module. */
747 RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
748 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
749 }
750 else
751 {
752 /* if need config SECURE PINT device,then enable secure pint interrupt clock */
753 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
754 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
755 /* Enable the clock. */
756 CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int);
757 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
758 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
759 /* Reset the module. */
760 RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
761 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
762 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
763 }
764 #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
765 }
766 #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
767 /* IRQ handler functions overloading weak symbols in the startup */
768 void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void);
SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)769 void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)
770 {
771 uint32_t pmstatus = 0;
772
773 /* Reset pattern match detection */
774 pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
775 /* Call user function */
776 if (s_secpintCallback[kPINT_SecPinInt0] != NULL)
777 {
778 s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus);
779 }
780 if ((SECPINT->ISEL & 0x1U) == 0x0U)
781 {
782 /* Edge sensitive: clear Pin interrupt after callback */
783 PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0);
784 }
785 SDK_ISR_EXIT_BARRIER;
786 }
787
788 #if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
789 /* IRQ handler functions overloading weak symbols in the startup */
790 void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void);
SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)791 void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)
792 {
793 uint32_t pmstatus;
794
795 /* Reset pattern match detection */
796 pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
797 /* Call user function */
798 if (s_secpintCallback[kPINT_SecPinInt1] != NULL)
799 {
800 s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus);
801 }
802 if ((SECPINT->ISEL & 0x1U) == 0x0U)
803 {
804 /* Edge sensitive: clear Pin interrupt after callback */
805 PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1);
806 }
807 SDK_ISR_EXIT_BARRIER;
808 }
809 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
810 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
811
812 void PINT0_DriverIRQHandler(void);
PINT0_DriverIRQHandler(void)813 void PINT0_DriverIRQHandler(void)
814 {
815 uint32_t flags = (PINT->IST & PINT_IST_PSTAT_MASK) | PINT_PatternMatchGetStatusAll(PINT);
816 uint32_t pmstatus;
817
818 for (uint8_t i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
819 {
820 if ((flags & (1UL << i)) != 0UL)
821 {
822 /* Reset pattern match detection */
823 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
824 /* Call user function */
825 if (s_pintCallback[i] != NULL)
826 {
827 s_pintCallback[i]((pint_pin_int_t)i, pmstatus);
828 }
829 if ((PINT->ISEL & (1UL << i)) == 0x0UL)
830 {
831 /* Edge sensitive: clear Pin interrupt after callback */
832 PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)i);
833 }
834 }
835 }
836
837 SDK_ISR_EXIT_BARRIER;
838 }
839
840 /* IRQ handler functions overloading weak symbols in the startup */
841 void PIN_INT0_DriverIRQHandler(void);
PIN_INT0_DriverIRQHandler(void)842 void PIN_INT0_DriverIRQHandler(void)
843 {
844 uint32_t pmstatus;
845
846 /* Reset pattern match detection */
847 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
848 /* Call user function */
849 if (s_pintCallback[kPINT_PinInt0] != NULL)
850 {
851 s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
852 }
853 if ((PINT->ISEL & 0x1U) == 0x0U)
854 {
855 /* Edge sensitive: clear Pin interrupt after callback */
856 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
857 }
858 SDK_ISR_EXIT_BARRIER;
859 }
860
861 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
862 void PIN_INT1_DriverIRQHandler(void);
PIN_INT1_DriverIRQHandler(void)863 void PIN_INT1_DriverIRQHandler(void)
864 {
865 uint32_t pmstatus;
866
867 /* Reset pattern match detection */
868 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
869 /* Call user function */
870 if (s_pintCallback[kPINT_PinInt1] != NULL)
871 {
872 s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
873 }
874 if ((PINT->ISEL & 0x2U) == 0x0U)
875 {
876 /* Edge sensitive: clear Pin interrupt after callback */
877 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
878 }
879 SDK_ISR_EXIT_BARRIER;
880 }
881 #endif
882
883 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
884 void PIN_INT2_DriverIRQHandler(void);
PIN_INT2_DriverIRQHandler(void)885 void PIN_INT2_DriverIRQHandler(void)
886 {
887 uint32_t pmstatus;
888
889 /* Reset pattern match detection */
890 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
891 /* Call user function */
892 if (s_pintCallback[kPINT_PinInt2] != NULL)
893 {
894 s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
895 }
896 if ((PINT->ISEL & 0x4U) == 0x0U)
897 {
898 /* Edge sensitive: clear Pin interrupt after callback */
899 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
900 }
901 SDK_ISR_EXIT_BARRIER;
902 }
903 #endif
904
905 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
906 void PIN_INT3_DriverIRQHandler(void);
PIN_INT3_DriverIRQHandler(void)907 void PIN_INT3_DriverIRQHandler(void)
908 {
909 uint32_t pmstatus;
910
911 /* Reset pattern match detection */
912 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
913 /* Call user function */
914 if (s_pintCallback[kPINT_PinInt3] != NULL)
915 {
916 s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
917 }
918 if ((PINT->ISEL & 0x8U) == 0x0U)
919 {
920 /* Edge sensitive: clear Pin interrupt after callback */
921 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
922 }
923 SDK_ISR_EXIT_BARRIER;
924 }
925 #endif
926
927 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
928 void PIN_INT4_DriverIRQHandler(void);
PIN_INT4_DriverIRQHandler(void)929 void PIN_INT4_DriverIRQHandler(void)
930 {
931 uint32_t pmstatus;
932
933 /* Reset pattern match detection */
934 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
935 /* Call user function */
936 if (s_pintCallback[kPINT_PinInt4] != NULL)
937 {
938 s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
939 }
940 if ((PINT->ISEL & 0x10U) == 0x0U)
941 {
942 /* Edge sensitive: clear Pin interrupt after callback */
943 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
944 }
945 SDK_ISR_EXIT_BARRIER;
946 }
947 #endif
948
949 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
950 #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
951 void PIN_INT5_DAC1_IRQHandler(void);
PIN_INT5_DAC1_IRQHandler(void)952 void PIN_INT5_DAC1_IRQHandler(void)
953 #else
954 void PIN_INT5_DriverIRQHandler(void);
955 void PIN_INT5_DriverIRQHandler(void)
956 #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
957 {
958 uint32_t pmstatus;
959
960 /* Reset pattern match detection */
961 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
962 /* Call user function */
963 if (s_pintCallback[kPINT_PinInt5] != NULL)
964 {
965 s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
966 }
967 if ((PINT->ISEL & 0x20U) == 0x0U)
968 {
969 /* Edge sensitive: clear Pin interrupt after callback */
970 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
971 }
972 SDK_ISR_EXIT_BARRIER;
973 }
974 #endif
975
976 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
977 #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
978 void PIN_INT6_USART3_IRQHandler(void);
PIN_INT6_USART3_IRQHandler(void)979 void PIN_INT6_USART3_IRQHandler(void)
980 #else
981 void PIN_INT6_DriverIRQHandler(void);
982 void PIN_INT6_DriverIRQHandler(void)
983 #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
984 {
985 uint32_t pmstatus;
986
987 /* Reset pattern match detection */
988 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
989 /* Call user function */
990 if (s_pintCallback[kPINT_PinInt6] != NULL)
991 {
992 s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
993 }
994 if ((PINT->ISEL & 0x40U) == 0x0U)
995 {
996 /* Edge sensitive: clear Pin interrupt after callback */
997 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
998 }
999 SDK_ISR_EXIT_BARRIER;
1000 }
1001 #endif
1002
1003 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
1004 #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
1005 void PIN_INT7_USART4_IRQHandler(void);
PIN_INT7_USART4_IRQHandler(void)1006 void PIN_INT7_USART4_IRQHandler(void)
1007 #else
1008 void PIN_INT7_DriverIRQHandler(void);
1009 void PIN_INT7_DriverIRQHandler(void)
1010 #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
1011 {
1012 uint32_t pmstatus;
1013
1014 /* Reset pattern match detection */
1015 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
1016 /* Call user function */
1017 if (s_pintCallback[kPINT_PinInt7] != NULL)
1018 {
1019 s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
1020 }
1021 if ((PINT->ISEL & 0x80U) == 0x0U)
1022 {
1023 /* Edge sensitive: clear Pin interrupt after callback */
1024 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
1025 }
1026 SDK_ISR_EXIT_BARRIER;
1027 }
1028 #endif
1029
