1 /**
2  * \file
3  *
4  * \brief Peripheral I/O description for SAML21J18B
5  *
6  * Copyright (c) 2017 Atmel Corporation,
7  *                    a wholly owned subsidiary of Microchip Technology Inc.
8  *
9  * \asf_license_start
10  *
11  * \page License
12  *
13  * Licensed under the Apache License, Version 2.0 (the "License");
14  * you may not use this file except in compliance with the License.
15  * You may obtain a copy of the Licence at
16  *
17  *     http://www.apache.org/licenses/LICENSE-2.0
18  *
19  * Unless required by applicable law or agreed to in writing, software
20  * distributed under the License is distributed on an "AS IS" BASIS,
21  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22  * See the License for the specific language governing permissions and
23  * limitations under the License.
24  *
25  * \asf_license_stop
26  *
27  */
28 
29 #ifndef _SAML21J18B_PIO_
30 #define _SAML21J18B_PIO_
31 
32 #define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
33 #define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
34 #define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
35 #define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
36 #define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
37 #define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
38 #define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
39 #define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
40 #define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
41 #define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
42 #define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
43 #define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
44 #define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
45 #define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
46 #define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
47 #define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
48 #define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
49 #define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
50 #define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
51 #define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
52 #define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
53 #define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
54 #define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
55 #define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
56 #define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
57 #define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
58 #define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
59 #define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
60 #define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
61 #define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
62 #define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
63 #define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
64 #define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
65 #define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
66 #define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
67 #define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
68 #define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
69 #define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
70 #define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
71 #define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
72 #define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
73 #define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
74 #define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
75 #define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
76 #define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
77 #define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
78 #define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
79 #define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
80 #define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
81 #define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
82 #define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
83 #define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
84 #define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
85 #define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
86 #define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
87 #define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
88 #define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
89 #define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
90 #define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
91 #define PORT_PB00              (_UL(1) <<  0) /**< \brief PORT Mask  for PB00 */
92 #define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
93 #define PORT_PB01              (_UL(1) <<  1) /**< \brief PORT Mask  for PB01 */
94 #define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
95 #define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
96 #define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
97 #define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
98 #define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
99 #define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
100 #define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
101 #define PORT_PB05              (_UL(1) <<  5) /**< \brief PORT Mask  for PB05 */
102 #define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
103 #define PORT_PB06              (_UL(1) <<  6) /**< \brief PORT Mask  for PB06 */
104 #define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
105 #define PORT_PB07              (_UL(1) <<  7) /**< \brief PORT Mask  for PB07 */
106 #define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
107 #define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
108 #define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
109 #define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
110 #define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
111 #define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
112 #define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
113 #define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
114 #define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
115 #define PORT_PB12              (_UL(1) << 12) /**< \brief PORT Mask  for PB12 */
116 #define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
117 #define PORT_PB13              (_UL(1) << 13) /**< \brief PORT Mask  for PB13 */
118 #define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
119 #define PORT_PB14              (_UL(1) << 14) /**< \brief PORT Mask  for PB14 */
120 #define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
121 #define PORT_PB15              (_UL(1) << 15) /**< \brief PORT Mask  for PB15 */
122 #define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
123 #define PORT_PB16              (_UL(1) << 16) /**< \brief PORT Mask  for PB16 */
124 #define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
125 #define PORT_PB17              (_UL(1) << 17) /**< \brief PORT Mask  for PB17 */
126 #define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
127 #define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
128 #define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
129 #define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
130 #define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
131 #define PORT_PB30              (_UL(1) << 30) /**< \brief PORT Mask  for PB30 */
132 #define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
133 #define PORT_PB31              (_UL(1) << 31) /**< \brief PORT Mask  for PB31 */
134 /* ========== PORT definition for RSTC peripheral ========== */
135 #define PIN_PA00A_RSTC_EXTWAKE0         _L(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */
136 #define MUX_PA00A_RSTC_EXTWAKE0         _L(0)
137 #define PINMUX_PA00A_RSTC_EXTWAKE0  ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0)
138 #define PORT_PA00A_RSTC_EXTWAKE0  (_UL(1) <<  0)
139 #define PIN_PA01A_RSTC_EXTWAKE1         _L(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */
140 #define MUX_PA01A_RSTC_EXTWAKE1         _L(0)
141 #define PINMUX_PA01A_RSTC_EXTWAKE1  ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1)
142 #define PORT_PA01A_RSTC_EXTWAKE1  (_UL(1) <<  1)
143 #define PIN_PA02A_RSTC_EXTWAKE2         _L(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */
144 #define MUX_PA02A_RSTC_EXTWAKE2         _L(0)
145 #define PINMUX_PA02A_RSTC_EXTWAKE2  ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2)
146 #define PORT_PA02A_RSTC_EXTWAKE2  (_UL(1) <<  2)
147 #define PIN_PA03A_RSTC_EXTWAKE3         _L(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */
148 #define MUX_PA03A_RSTC_EXTWAKE3         _L(0)
149 #define PINMUX_PA03A_RSTC_EXTWAKE3  ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3)
150 #define PORT_PA03A_RSTC_EXTWAKE3  (_UL(1) <<  3)
151 #define PIN_PA04A_RSTC_EXTWAKE4         _L(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */
152 #define MUX_PA04A_RSTC_EXTWAKE4         _L(0)
153 #define PINMUX_PA04A_RSTC_EXTWAKE4  ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4)
154 #define PORT_PA04A_RSTC_EXTWAKE4  (_UL(1) <<  4)
155 #define PIN_PA05A_RSTC_EXTWAKE5         _L(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */
156 #define MUX_PA05A_RSTC_EXTWAKE5         _L(0)
157 #define PINMUX_PA05A_RSTC_EXTWAKE5  ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5)
158 #define PORT_PA05A_RSTC_EXTWAKE5  (_UL(1) <<  5)
159 #define PIN_PA06A_RSTC_EXTWAKE6         _L(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */
160 #define MUX_PA06A_RSTC_EXTWAKE6         _L(0)
161 #define PINMUX_PA06A_RSTC_EXTWAKE6  ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6)
162 #define PORT_PA06A_RSTC_EXTWAKE6  (_UL(1) <<  6)
163 #define PIN_PA07A_RSTC_EXTWAKE7         _L(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */
164 #define MUX_PA07A_RSTC_EXTWAKE7         _L(0)
165 #define PINMUX_PA07A_RSTC_EXTWAKE7  ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7)
166 #define PORT_PA07A_RSTC_EXTWAKE7  (_UL(1) <<  7)
167 /* ========== PORT definition for SUPC peripheral ========== */
168 #define PIN_PB01H_SUPC_OUT0            _L(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */
169 #define MUX_PB01H_SUPC_OUT0             _L(7)
170 #define PINMUX_PB01H_SUPC_OUT0     ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0)
171 #define PORT_PB01H_SUPC_OUT0   (_UL(1) <<  1)
172 #define PIN_PB02H_SUPC_OUT1            _L(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */
173 #define MUX_PB02H_SUPC_OUT1             _L(7)
174 #define PINMUX_PB02H_SUPC_OUT1     ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1)
175 #define PORT_PB02H_SUPC_OUT1   (_UL(1) <<  2)
176 #define PIN_PB00H_SUPC_PSOK            _L(32) /**< \brief SUPC signal: PSOK on PB00 mux H */
177 #define MUX_PB00H_SUPC_PSOK             _L(7)
178 #define PINMUX_PB00H_SUPC_PSOK     ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK)
179 #define PORT_PB00H_SUPC_PSOK   (_UL(1) <<  0)
180 #define PIN_PB03H_SUPC_VBAT            _L(35) /**< \brief SUPC signal: VBAT on PB03 mux H */
181 #define MUX_PB03H_SUPC_VBAT             _L(7)
182 #define PINMUX_PB03H_SUPC_VBAT     ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT)
183 #define PORT_PB03H_SUPC_VBAT   (_UL(1) <<  3)
184 /* ========== PORT definition for GCLK peripheral ========== */
185 #define PIN_PB14H_GCLK_IO0             _L(46) /**< \brief GCLK signal: IO0 on PB14 mux H */
186 #define MUX_PB14H_GCLK_IO0              _L(7)
187 #define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
188 #define PORT_PB14H_GCLK_IO0    (_UL(1) << 14)
189 #define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
190 #define MUX_PB22H_GCLK_IO0              _L(7)
191 #define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
192 #define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
193 #define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
194 #define MUX_PA14H_GCLK_IO0              _L(7)
195 #define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
196 #define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
197 #define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
198 #define MUX_PA27H_GCLK_IO0              _L(7)
199 #define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
200 #define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
201 #define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
202 #define MUX_PA30H_GCLK_IO0              _L(7)
203 #define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
204 #define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
205 #define PIN_PB15H_GCLK_IO1             _L(47) /**< \brief GCLK signal: IO1 on PB15 mux H */
206 #define MUX_PB15H_GCLK_IO1              _L(7)
207 #define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
208 #define PORT_PB15H_GCLK_IO1    (_UL(1) << 15)
209 #define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
210 #define MUX_PB23H_GCLK_IO1              _L(7)
211 #define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
212 #define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
213 #define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
214 #define MUX_PA15H_GCLK_IO1              _L(7)
215 #define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
216 #define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
217 #define PIN_PB16H_GCLK_IO2             _L(48) /**< \brief GCLK signal: IO2 on PB16 mux H */
218 #define MUX_PB16H_GCLK_IO2              _L(7)
219 #define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
220 #define PORT_PB16H_GCLK_IO2    (_UL(1) << 16)
221 #define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
222 #define MUX_PA16H_GCLK_IO2              _L(7)
223 #define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
224 #define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
225 #define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
226 #define MUX_PA17H_GCLK_IO3              _L(7)
227 #define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
228 #define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
229 #define PIN_PB17H_GCLK_IO3             _L(49) /**< \brief GCLK signal: IO3 on PB17 mux H */
230 #define MUX_PB17H_GCLK_IO3              _L(7)
231 #define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
232 #define PORT_PB17H_GCLK_IO3    (_UL(1) << 17)
233 #define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
234 #define MUX_PA10H_GCLK_IO4              _L(7)
235 #define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
236 #define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
237 #define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
238 #define MUX_PA20H_GCLK_IO4              _L(7)
239 #define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
240 #define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
241 #define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
242 #define MUX_PB10H_GCLK_IO4              _L(7)
243 #define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
244 #define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
245 #define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
246 #define MUX_PA11H_GCLK_IO5              _L(7)
247 #define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
248 #define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
249 #define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
250 #define MUX_PA21H_GCLK_IO5              _L(7)
251 #define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
252 #define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
253 #define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
254 #define MUX_PB11H_GCLK_IO5              _L(7)
255 #define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
256 #define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
257 #define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
258 #define MUX_PA22H_GCLK_IO6              _L(7)
259 #define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
260 #define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
261 #define PIN_PB12H_GCLK_IO6             _L(44) /**< \brief GCLK signal: IO6 on PB12 mux H */
262 #define MUX_PB12H_GCLK_IO6              _L(7)
263 #define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
264 #define PORT_PB12H_GCLK_IO6    (_UL(1) << 12)
265 #define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
266 #define MUX_PA23H_GCLK_IO7              _L(7)
267 #define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
268 #define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
269 #define PIN_PB13H_GCLK_IO7             _L(45) /**< \brief GCLK signal: IO7 on PB13 mux H */
270 #define MUX_PB13H_GCLK_IO7              _L(7)
271 #define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
272 #define PORT_PB13H_GCLK_IO7    (_UL(1) << 13)
273 /* ========== PORT definition for EIC peripheral ========== */
274 #define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
275 #define MUX_PA16A_EIC_EXTINT0           _L(0)
276 #define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
277 #define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
278 #define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
279 #define PIN_PB00A_EIC_EXTINT0          _L(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
280 #define MUX_PB00A_EIC_EXTINT0           _L(0)
281 #define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
282 #define PORT_PB00A_EIC_EXTINT0  (_UL(1) <<  0)
283 #define PIN_PB00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
284 #define PIN_PB16A_EIC_EXTINT0          _L(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
285 #define MUX_PB16A_EIC_EXTINT0           _L(0)
286 #define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
287 #define PORT_PB16A_EIC_EXTINT0  (_UL(1) << 16)
288 #define PIN_PB16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
289 #define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
290 #define MUX_PA00A_EIC_EXTINT0           _L(0)
291 #define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
292 #define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
293 #define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
294 #define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
295 #define MUX_PA17A_EIC_EXTINT1           _L(0)
296 #define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
297 #define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
298 #define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
299 #define PIN_PB01A_EIC_EXTINT1          _L(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
300 #define MUX_PB01A_EIC_EXTINT1           _L(0)
301 #define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
302 #define PORT_PB01A_EIC_EXTINT1  (_UL(1) <<  1)
303 #define PIN_PB01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
304 #define PIN_PB17A_EIC_EXTINT1          _L(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
305 #define MUX_PB17A_EIC_EXTINT1           _L(0)
306 #define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
307 #define PORT_PB17A_EIC_EXTINT1  (_UL(1) << 17)
308 #define PIN_PB17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
309 #define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
310 #define MUX_PA01A_EIC_EXTINT1           _L(0)
311 #define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
312 #define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
313 #define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
314 #define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
315 #define MUX_PA02A_EIC_EXTINT2           _L(0)
316 #define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
317 #define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
318 #define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
319 #define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
320 #define MUX_PA18A_EIC_EXTINT2           _L(0)
321 #define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
322 #define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
323 #define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
324 #define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
325 #define MUX_PB02A_EIC_EXTINT2           _L(0)
326 #define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
327 #define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
328 #define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
329 #define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
330 #define MUX_PA03A_EIC_EXTINT3           _L(0)
331 #define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
332 #define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
333 #define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
334 #define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
335 #define MUX_PA19A_EIC_EXTINT3           _L(0)
336 #define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
337 #define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
338 #define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
339 #define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
340 #define MUX_PB03A_EIC_EXTINT3           _L(0)
341 #define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
342 #define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
343 #define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
344 #define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
345 #define MUX_PA04A_EIC_EXTINT4           _L(0)
346 #define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
347 #define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
348 #define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
349 #define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
350 #define MUX_PA20A_EIC_EXTINT4           _L(0)
351 #define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
352 #define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
353 #define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
354 #define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
355 #define MUX_PB04A_EIC_EXTINT4           _L(0)
356 #define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
357 #define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
358 #define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
359 #define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
360 #define MUX_PA05A_EIC_EXTINT5           _L(0)
361 #define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
362 #define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
363 #define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
364 #define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
365 #define MUX_PA21A_EIC_EXTINT5           _L(0)
366 #define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
367 #define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
368 #define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
369 #define PIN_PB05A_EIC_EXTINT5          _L(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
370 #define MUX_PB05A_EIC_EXTINT5           _L(0)
371 #define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
372 #define PORT_PB05A_EIC_EXTINT5  (_UL(1) <<  5)
373 #define PIN_PB05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
374 #define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
375 #define MUX_PA06A_EIC_EXTINT6           _L(0)
376 #define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
377 #define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
378 #define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
379 #define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
380 #define MUX_PA22A_EIC_EXTINT6           _L(0)
381 #define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
382 #define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
383 #define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
384 #define PIN_PB06A_EIC_EXTINT6          _L(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
385 #define MUX_PB06A_EIC_EXTINT6           _L(0)
386 #define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
387 #define PORT_PB06A_EIC_EXTINT6  (_UL(1) <<  6)
388 #define PIN_PB06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
389 #define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
390 #define MUX_PB22A_EIC_EXTINT6           _L(0)
391 #define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
392 #define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
393 #define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
394 #define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
395 #define MUX_PA07A_EIC_EXTINT7           _L(0)
396 #define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
397 #define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
398 #define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
399 #define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
400 #define MUX_PA23A_EIC_EXTINT7           _L(0)
401 #define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
402 #define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
403 #define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
404 #define PIN_PB07A_EIC_EXTINT7          _L(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
405 #define MUX_PB07A_EIC_EXTINT7           _L(0)
406 #define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
407 #define PORT_PB07A_EIC_EXTINT7  (_UL(1) <<  7)
408 #define PIN_PB07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
409 #define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
410 #define MUX_PB23A_EIC_EXTINT7           _L(0)
411 #define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
412 #define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
413 #define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
414 #define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
415 #define MUX_PA28A_EIC_EXTINT8           _L(0)
416 #define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
417 #define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
418 #define PIN_PA28A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
419 #define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
420 #define MUX_PB08A_EIC_EXTINT8           _L(0)
421 #define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
422 #define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
423 #define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
424 #define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
425 #define MUX_PA09A_EIC_EXTINT9           _L(0)
426 #define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
427 #define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
428 #define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
429 #define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
430 #define MUX_PB09A_EIC_EXTINT9           _L(0)
431 #define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
432 #define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
433 #define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
434 #define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
435 #define MUX_PA10A_EIC_EXTINT10          _L(0)
436 #define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
437 #define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
438 #define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
439 #define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
440 #define MUX_PA30A_EIC_EXTINT10          _L(0)
441 #define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
442 #define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
443 #define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
444 #define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
445 #define MUX_PB10A_EIC_EXTINT10          _L(0)
446 #define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
447 #define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
448 #define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
449 #define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
450 #define MUX_PA11A_EIC_EXTINT11          _L(0)
451 #define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
452 #define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
453 #define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
454 #define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
455 #define MUX_PA31A_EIC_EXTINT11          _L(0)
456 #define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
457 #define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
458 #define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
459 #define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
460 #define MUX_PB11A_EIC_EXTINT11          _L(0)
461 #define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
462 #define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
463 #define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
464 #define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
465 #define MUX_PA12A_EIC_EXTINT12          _L(0)
466 #define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
467 #define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
468 #define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
469 #define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
470 #define MUX_PA24A_EIC_EXTINT12          _L(0)
471 #define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
472 #define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
473 #define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
474 #define PIN_PB12A_EIC_EXTINT12         _L(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
475 #define MUX_PB12A_EIC_EXTINT12          _L(0)
476 #define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
477 #define PORT_PB12A_EIC_EXTINT12  (_UL(1) << 12)
478 #define PIN_PB12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
479 #define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
480 #define MUX_PA13A_EIC_EXTINT13          _L(0)
481 #define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
482 #define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
483 #define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
484 #define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
485 #define MUX_PA25A_EIC_EXTINT13          _L(0)
486 #define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
487 #define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
488 #define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
489 #define PIN_PB13A_EIC_EXTINT13         _L(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
490 #define MUX_PB13A_EIC_EXTINT13          _L(0)
491 #define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
492 #define PORT_PB13A_EIC_EXTINT13  (_UL(1) << 13)
493 #define PIN_PB13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
494 #define PIN_PB14A_EIC_EXTINT14         _L(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
495 #define MUX_PB14A_EIC_EXTINT14          _L(0)
496 #define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
497 #define PORT_PB14A_EIC_EXTINT14  (_UL(1) << 14)
498 #define PIN_PB14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
499 #define PIN_PB30A_EIC_EXTINT14         _L(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
500 #define MUX_PB30A_EIC_EXTINT14          _L(0)
501 #define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
502 #define PORT_PB30A_EIC_EXTINT14  (_UL(1) << 30)
503 #define PIN_PB30A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
504 #define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
505 #define MUX_PA14A_EIC_EXTINT14          _L(0)
506 #define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
507 #define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
508 #define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
509 #define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
510 #define MUX_PA27A_EIC_EXTINT15          _L(0)
511 #define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
512 #define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
513 #define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
514 #define PIN_PB15A_EIC_EXTINT15         _L(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
515 #define MUX_PB15A_EIC_EXTINT15          _L(0)
516 #define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
517 #define PORT_PB15A_EIC_EXTINT15  (_UL(1) << 15)
518 #define PIN_PB15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
519 #define PIN_PB31A_EIC_EXTINT15         _L(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
520 #define MUX_PB31A_EIC_EXTINT15          _L(0)
521 #define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
522 #define PORT_PB31A_EIC_EXTINT15  (_UL(1) << 31)
523 #define PIN_PB31A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
524 #define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
525 #define MUX_PA15A_EIC_EXTINT15          _L(0)
526 #define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
527 #define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
528 #define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
529 #define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
530 #define MUX_PA08A_EIC_NMI               _L(0)
531 #define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
532 #define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
533 /* ========== PORT definition for TAL peripheral ========== */
534 #define PIN_PA27G_TAL_BRK              _L(27) /**< \brief TAL signal: BRK on PA27 mux G */
535 #define MUX_PA27G_TAL_BRK               _L(6)
536 #define PINMUX_PA27G_TAL_BRK       ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK)
537 #define PORT_PA27G_TAL_BRK     (_UL(1) << 27)
538 /* ========== PORT definition for USB peripheral ========== */
539 #define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
540 #define MUX_PA24G_USB_DM                _L(6)
541 #define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
542 #define PORT_PA24G_USB_DM      (_UL(1) << 24)
543 #define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
544 #define MUX_PA25G_USB_DP                _L(6)
545 #define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
546 #define PORT_PA25G_USB_DP      (_UL(1) << 25)
547 #define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
548 #define MUX_PA23G_USB_SOF_1KHZ          _L(6)
549 #define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
550 #define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
551 /* ========== PORT definition for SERCOM0 peripheral ========== */
552 #define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
553 #define MUX_PA04D_SERCOM0_PAD0          _L(3)
554 #define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
555 #define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
556 #define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
557 #define MUX_PA08C_SERCOM0_PAD0          _L(2)
558 #define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
559 #define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
560 #define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
561 #define MUX_PA05D_SERCOM0_PAD1          _L(3)
562 #define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
563 #define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
564 #define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
565 #define MUX_PA09C_SERCOM0_PAD1          _L(2)
566 #define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
567 #define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
568 #define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
569 #define MUX_PA06D_SERCOM0_PAD2          _L(3)
570 #define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
571 #define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
572 #define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
573 #define MUX_PA10C_SERCOM0_PAD2          _L(2)
574 #define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
575 #define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
576 #define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
577 #define MUX_PA07D_SERCOM0_PAD3          _L(3)
578 #define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
579 #define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
580 #define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
581 #define MUX_PA11C_SERCOM0_PAD3          _L(2)
582 #define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
583 #define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
584 /* ========== PORT definition for SERCOM1 peripheral ========== */
585 #define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
586 #define MUX_PA16C_SERCOM1_PAD0          _L(2)
587 #define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
588 #define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
589 #define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
590 #define MUX_PA00D_SERCOM1_PAD0          _L(3)
591 #define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
592 #define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
593 #define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
594 #define MUX_PA17C_SERCOM1_PAD1          _L(2)
595 #define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
596 #define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
597 #define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
598 #define MUX_PA01D_SERCOM1_PAD1          _L(3)
599 #define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
600 #define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
601 #define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
602 #define MUX_PA30D_SERCOM1_PAD2          _L(3)
603 #define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
604 #define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
605 #define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
606 #define MUX_PA18C_SERCOM1_PAD2          _L(2)
607 #define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
608 #define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
609 #define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
610 #define MUX_PA31D_SERCOM1_PAD3          _L(3)
611 #define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
612 #define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
613 #define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
614 #define MUX_PA19C_SERCOM1_PAD3          _L(2)
615 #define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
616 #define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
617 /* ========== PORT definition for SERCOM2 peripheral ========== */
618 #define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
619 #define MUX_PA08D_SERCOM2_PAD0          _L(3)
620 #define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
621 #define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
622 #define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
623 #define MUX_PA12C_SERCOM2_PAD0          _L(2)
624 #define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
625 #define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
626 #define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
627 #define MUX_PA09D_SERCOM2_PAD1          _L(3)
628 #define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
629 #define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
630 #define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
631 #define MUX_PA13C_SERCOM2_PAD1          _L(2)
632 #define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
633 #define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
634 #define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
635 #define MUX_PA10D_SERCOM2_PAD2          _L(3)
636 #define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
637 #define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
638 #define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
639 #define MUX_PA14C_SERCOM2_PAD2          _L(2)
640 #define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
641 #define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
642 #define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
643 #define MUX_PA11D_SERCOM2_PAD3          _L(3)
644 #define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
645 #define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
646 #define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
647 #define MUX_PA15C_SERCOM2_PAD3          _L(2)
648 #define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
649 #define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
650 /* ========== PORT definition for SERCOM3 peripheral ========== */
651 #define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
652 #define MUX_PA16D_SERCOM3_PAD0          _L(3)
653 #define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
654 #define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
655 #define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
656 #define MUX_PA22C_SERCOM3_PAD0          _L(2)
657 #define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
658 #define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
659 #define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
660 #define MUX_PA17D_SERCOM3_PAD1          _L(3)
661 #define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
662 #define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
663 #define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
664 #define MUX_PA23C_SERCOM3_PAD1          _L(2)
665 #define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
666 #define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
667 #define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
668 #define MUX_PA18D_SERCOM3_PAD2          _L(3)
669 #define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
670 #define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
671 #define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
672 #define MUX_PA20D_SERCOM3_PAD2          _L(3)
673 #define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
674 #define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
675 #define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
676 #define MUX_PA24C_SERCOM3_PAD2          _L(2)
677 #define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
678 #define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
679 #define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
680 #define MUX_PA19D_SERCOM3_PAD3          _L(3)
681 #define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
682 #define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
683 #define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
684 #define MUX_PA21D_SERCOM3_PAD3          _L(3)
685 #define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
686 #define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
687 #define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
688 #define MUX_PA25C_SERCOM3_PAD3          _L(2)
689 #define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
690 #define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
691 /* ========== PORT definition for SERCOM4 peripheral ========== */
692 #define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
693 #define MUX_PA12D_SERCOM4_PAD0          _L(3)
694 #define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
695 #define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
696 #define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
697 #define MUX_PB08D_SERCOM4_PAD0          _L(3)
698 #define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
699 #define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
700 #define PIN_PB12C_SERCOM4_PAD0         _L(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
701 #define MUX_PB12C_SERCOM4_PAD0          _L(2)
702 #define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
703 #define PORT_PB12C_SERCOM4_PAD0  (_UL(1) << 12)
704 #define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
705 #define MUX_PA13D_SERCOM4_PAD1          _L(3)
706 #define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
707 #define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
708 #define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
709 #define MUX_PB09D_SERCOM4_PAD1          _L(3)
710 #define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
711 #define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
712 #define PIN_PB13C_SERCOM4_PAD1         _L(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
713 #define MUX_PB13C_SERCOM4_PAD1          _L(2)
714 #define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
715 #define PORT_PB13C_SERCOM4_PAD1  (_UL(1) << 13)
716 #define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
717 #define MUX_PA14D_SERCOM4_PAD2          _L(3)
718 #define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
719 #define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
720 #define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
721 #define MUX_PB10D_SERCOM4_PAD2          _L(3)
722 #define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
723 #define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
724 #define PIN_PB14C_SERCOM4_PAD2         _L(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
725 #define MUX_PB14C_SERCOM4_PAD2          _L(2)
726 #define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
727 #define PORT_PB14C_SERCOM4_PAD2  (_UL(1) << 14)
728 #define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
729 #define MUX_PA15D_SERCOM4_PAD3          _L(3)
730 #define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
731 #define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
732 #define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
733 #define MUX_PB11D_SERCOM4_PAD3          _L(3)
734 #define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
735 #define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
736 #define PIN_PB15C_SERCOM4_PAD3         _L(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
737 #define MUX_PB15C_SERCOM4_PAD3          _L(2)
738 #define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
739 #define PORT_PB15C_SERCOM4_PAD3  (_UL(1) << 15)
740 #define PIN_PC19F_SERCOM4_PAD0            83L  /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */
741 #define MUX_PC19F_SERCOM4_PAD0            5L
742 #define PINMUX_PC19F_SERCOM4_PAD0  ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0)
743 #define PORT_PC19F_SERCOM4_PAD0    (1ul << 19)
744 #define PIN_PC18F_SERCOM4_PAD3            82L  /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */
745 #define MUX_PC18F_SERCOM4_PAD3             5L
746 #define PINMUX_PC18F_SERCOM4_PAD3  ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3)
747 #define PORT_PC18F_SERCOM4_PAD3    (1ul << 18)
748 #define PIN_PB30F_SERCOM4_PAD2            62L  /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
749 #define MUX_PB30F_SERCOM4_PAD2             5L
750 #define PINMUX_PB30F_SERCOM4_PAD2  ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
751 #define PORT_PB30F_SERCOM4_PAD2    (1ul << 30)
752 /* ========== PORT definition for TCC0 peripheral ========== */
753 #define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
754 #define MUX_PA04E_TCC0_WO0              _L(4)
755 #define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
756 #define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
757 #define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
758 #define MUX_PA08E_TCC0_WO0              _L(4)
759 #define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
760 #define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
761 #define PIN_PB30E_TCC0_WO0             _L(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */
762 #define MUX_PB30E_TCC0_WO0              _L(4)
763 #define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
764 #define PORT_PB30E_TCC0_WO0    (_UL(1) << 30)
765 #define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
766 #define MUX_PA05E_TCC0_WO1              _L(4)
767 #define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
768 #define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
769 #define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
770 #define MUX_PA09E_TCC0_WO1              _L(4)
771 #define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
772 #define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
773 #define PIN_PB31E_TCC0_WO1             _L(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */
774 #define MUX_PB31E_TCC0_WO1              _L(4)
775 #define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
776 #define PORT_PB31E_TCC0_WO1    (_UL(1) << 31)
777 #define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
778 #define MUX_PA10F_TCC0_WO2              _L(5)
779 #define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
780 #define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
781 #define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
782 #define MUX_PA18F_TCC0_WO2              _L(5)
783 #define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
784 #define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
785 #define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
786 #define MUX_PA11F_TCC0_WO3              _L(5)
787 #define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
788 #define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
789 #define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
790 #define MUX_PA19F_TCC0_WO3              _L(5)
791 #define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
792 #define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
793 #define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
794 #define MUX_PA22F_TCC0_WO4              _L(5)
795 #define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
796 #define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
797 #define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
798 #define MUX_PB10F_TCC0_WO4              _L(5)
799 #define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
800 #define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
801 #define PIN_PB16F_TCC0_WO4             _L(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */
802 #define MUX_PB16F_TCC0_WO4              _L(5)
803 #define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
804 #define PORT_PB16F_TCC0_WO4    (_UL(1) << 16)
805 #define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
806 #define MUX_PA14F_TCC0_WO4              _L(5)
807 #define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
808 #define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
809 #define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
810 #define MUX_PA15F_TCC0_WO5              _L(5)
811 #define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
812 #define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
813 #define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
814 #define MUX_PA23F_TCC0_WO5              _L(5)
815 #define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
816 #define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
817 #define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
818 #define MUX_PB11F_TCC0_WO5              _L(5)
819 #define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
820 #define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
821 #define PIN_PB17F_TCC0_WO5             _L(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */
822 #define MUX_PB17F_TCC0_WO5              _L(5)
823 #define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
824 #define PORT_PB17F_TCC0_WO5    (_UL(1) << 17)
825 #define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
826 #define MUX_PA12F_TCC0_WO6              _L(5)
827 #define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
828 #define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
829 #define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
830 #define MUX_PA16F_TCC0_WO6              _L(5)
831 #define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
832 #define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
833 #define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
834 #define MUX_PA20F_TCC0_WO6              _L(5)
835 #define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
836 #define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
837 #define PIN_PB12F_TCC0_WO6             _L(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */
838 #define MUX_PB12F_TCC0_WO6              _L(5)
839 #define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
840 #define PORT_PB12F_TCC0_WO6    (_UL(1) << 12)
841 #define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
842 #define MUX_PA13F_TCC0_WO7              _L(5)
843 #define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
844 #define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
845 #define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
846 #define MUX_PA17F_TCC0_WO7              _L(5)
847 #define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
848 #define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
849 #define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
850 #define MUX_PA21F_TCC0_WO7              _L(5)
851 #define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
852 #define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
853 #define PIN_PB13F_TCC0_WO7             _L(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */
854 #define MUX_PB13F_TCC0_WO7              _L(5)
855 #define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
856 #define PORT_PB13F_TCC0_WO7    (_UL(1) << 13)
857 /* ========== PORT definition for TCC1 peripheral ========== */
858 #define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
859 #define MUX_PA06E_TCC1_WO0              _L(4)
860 #define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
861 #define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
862 #define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
863 #define MUX_PA10E_TCC1_WO0              _L(4)
864 #define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
865 #define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
866 #define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
867 #define MUX_PA30E_TCC1_WO0              _L(4)
868 #define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
869 #define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
870 #define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
871 #define MUX_PA07E_TCC1_WO1              _L(4)
872 #define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
873 #define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
874 #define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
875 #define MUX_PA11E_TCC1_WO1              _L(4)
876 #define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
877 #define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
878 #define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
879 #define MUX_PA31E_TCC1_WO1              _L(4)
880 #define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
881 #define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
882 #define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
883 #define MUX_PA08F_TCC1_WO2              _L(5)
884 #define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
885 #define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
886 #define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
887 #define MUX_PA24F_TCC1_WO2              _L(5)
888 #define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
889 #define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
890 #define PIN_PB30F_TCC1_WO2             _L(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */
891 #define MUX_PB30F_TCC1_WO2              _L(5)
892 #define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
893 #define PORT_PB30F_TCC1_WO2    (_UL(1) << 30)
894 #define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
895 #define MUX_PA09F_TCC1_WO3              _L(5)
896 #define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
897 #define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
898 #define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
899 #define MUX_PA25F_TCC1_WO3              _L(5)
900 #define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
901 #define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
902 #define PIN_PB31F_TCC1_WO3             _L(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */
903 #define MUX_PB31F_TCC1_WO3              _L(5)
904 #define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
905 #define PORT_PB31F_TCC1_WO3    (_UL(1) << 31)
906 /* ========== PORT definition for TCC2 peripheral ========== */
907 #define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
908 #define MUX_PA12E_TCC2_WO0              _L(4)
909 #define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
910 #define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
911 #define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
912 #define MUX_PA16E_TCC2_WO0              _L(4)
913 #define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
914 #define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
915 #define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
916 #define MUX_PA00E_TCC2_WO0              _L(4)
917 #define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
918 #define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
919 #define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
920 #define MUX_PA13E_TCC2_WO1              _L(4)
921 #define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
922 #define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
923 #define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
924 #define MUX_PA17E_TCC2_WO1              _L(4)
925 #define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
926 #define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
927 #define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
928 #define MUX_PA01E_TCC2_WO1              _L(4)
929 #define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
930 #define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
931 /* ========== PORT definition for TC0 peripheral ========== */
932 #define PIN_PA22E_TC0_WO0              _L(22) /**< \brief TC0 signal: WO0 on PA22 mux E */
933 #define MUX_PA22E_TC0_WO0               _L(4)
934 #define PINMUX_PA22E_TC0_WO0       ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0)
935 #define PORT_PA22E_TC0_WO0     (_UL(1) << 22)
936 #define PIN_PB08E_TC0_WO0              _L(40) /**< \brief TC0 signal: WO0 on PB08 mux E */
937 #define MUX_PB08E_TC0_WO0               _L(4)
938 #define PINMUX_PB08E_TC0_WO0       ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0)
939 #define PORT_PB08E_TC0_WO0     (_UL(1) <<  8)
940 #define PIN_PB12E_TC0_WO0              _L(44) /**< \brief TC0 signal: WO0 on PB12 mux E */
941 #define MUX_PB12E_TC0_WO0               _L(4)
942 #define PINMUX_PB12E_TC0_WO0       ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0)
943 #define PORT_PB12E_TC0_WO0     (_UL(1) << 12)
944 #define PIN_PA23E_TC0_WO1              _L(23) /**< \brief TC0 signal: WO1 on PA23 mux E */
945 #define MUX_PA23E_TC0_WO1               _L(4)
946 #define PINMUX_PA23E_TC0_WO1       ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1)
947 #define PORT_PA23E_TC0_WO1     (_UL(1) << 23)
948 #define PIN_PB09E_TC0_WO1              _L(41) /**< \brief TC0 signal: WO1 on PB09 mux E */
949 #define MUX_PB09E_TC0_WO1               _L(4)
950 #define PINMUX_PB09E_TC0_WO1       ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1)
951 #define PORT_PB09E_TC0_WO1     (_UL(1) <<  9)
952 #define PIN_PB13E_TC0_WO1              _L(45) /**< \brief TC0 signal: WO1 on PB13 mux E */
953 #define MUX_PB13E_TC0_WO1               _L(4)
954 #define PINMUX_PB13E_TC0_WO1       ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1)
955 #define PORT_PB13E_TC0_WO1     (_UL(1) << 13)
956 /* ========== PORT definition for TC1 peripheral ========== */
957 #define PIN_PA24E_TC1_WO0              _L(24) /**< \brief TC1 signal: WO0 on PA24 mux E */
958 #define MUX_PA24E_TC1_WO0               _L(4)
959 #define PINMUX_PA24E_TC1_WO0       ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0)
960 #define PORT_PA24E_TC1_WO0     (_UL(1) << 24)
961 #define PIN_PB10E_TC1_WO0              _L(42) /**< \brief TC1 signal: WO0 on PB10 mux E */
962 #define MUX_PB10E_TC1_WO0               _L(4)
963 #define PINMUX_PB10E_TC1_WO0       ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0)
964 #define PORT_PB10E_TC1_WO0     (_UL(1) << 10)
965 #define PIN_PB14E_TC1_WO0              _L(46) /**< \brief TC1 signal: WO0 on PB14 mux E */
966 #define MUX_PB14E_TC1_WO0               _L(4)
967 #define PINMUX_PB14E_TC1_WO0       ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0)
968 #define PORT_PB14E_TC1_WO0     (_UL(1) << 14)
969 #define PIN_PA25E_TC1_WO1              _L(25) /**< \brief TC1 signal: WO1 on PA25 mux E */
970 #define MUX_PA25E_TC1_WO1               _L(4)
971 #define PINMUX_PA25E_TC1_WO1       ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1)
972 #define PORT_PA25E_TC1_WO1     (_UL(1) << 25)
973 #define PIN_PB11E_TC1_WO1              _L(43) /**< \brief TC1 signal: WO1 on PB11 mux E */
974 #define MUX_PB11E_TC1_WO1               _L(4)
975 #define PINMUX_PB11E_TC1_WO1       ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1)
976 #define PORT_PB11E_TC1_WO1     (_UL(1) << 11)
977 #define PIN_PB15E_TC1_WO1              _L(47) /**< \brief TC1 signal: WO1 on PB15 mux E */
978 #define MUX_PB15E_TC1_WO1               _L(4)
979 #define PINMUX_PB15E_TC1_WO1       ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1)
980 #define PORT_PB15E_TC1_WO1     (_UL(1) << 15)
981 /* ========== PORT definition for TC2 peripheral ========== */
982 #define PIN_PB02E_TC2_WO0              _L(34) /**< \brief TC2 signal: WO0 on PB02 mux E */
983 #define MUX_PB02E_TC2_WO0               _L(4)
984 #define PINMUX_PB02E_TC2_WO0       ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0)
985 #define PORT_PB02E_TC2_WO0     (_UL(1) <<  2)
986 #define PIN_PB16E_TC2_WO0              _L(48) /**< \brief TC2 signal: WO0 on PB16 mux E */
987 #define MUX_PB16E_TC2_WO0               _L(4)
988 #define PINMUX_PB16E_TC2_WO0       ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0)
989 #define PORT_PB16E_TC2_WO0     (_UL(1) << 16)
990 #define PIN_PB03E_TC2_WO1              _L(35) /**< \brief TC2 signal: WO1 on PB03 mux E */
991 #define MUX_PB03E_TC2_WO1               _L(4)
992 #define PINMUX_PB03E_TC2_WO1       ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1)
993 #define PORT_PB03E_TC2_WO1     (_UL(1) <<  3)
994 #define PIN_PB17E_TC2_WO1              _L(49) /**< \brief TC2 signal: WO1 on PB17 mux E */
995 #define MUX_PB17E_TC2_WO1               _L(4)
996 #define PINMUX_PB17E_TC2_WO1       ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1)
997 #define PORT_PB17E_TC2_WO1     (_UL(1) << 17)
998 /* ========== PORT definition for TC3 peripheral ========== */
999 #define PIN_PA20E_TC3_WO0              _L(20) /**< \brief TC3 signal: WO0 on PA20 mux E */
1000 #define MUX_PA20E_TC3_WO0               _L(4)
1001 #define PINMUX_PA20E_TC3_WO0       ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0)
1002 #define PORT_PA20E_TC3_WO0     (_UL(1) << 20)
1003 #define PIN_PB00E_TC3_WO0              _L(32) /**< \brief TC3 signal: WO0 on PB00 mux E */
1004 #define MUX_PB00E_TC3_WO0               _L(4)
1005 #define PINMUX_PB00E_TC3_WO0       ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0)
1006 #define PORT_PB00E_TC3_WO0     (_UL(1) <<  0)
1007 #define PIN_PB22E_TC3_WO0              _L(54) /**< \brief TC3 signal: WO0 on PB22 mux E */
1008 #define MUX_PB22E_TC3_WO0               _L(4)
1009 #define PINMUX_PB22E_TC3_WO0       ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0)
1010 #define PORT_PB22E_TC3_WO0     (_UL(1) << 22)
1011 #define PIN_PA21E_TC3_WO1              _L(21) /**< \brief TC3 signal: WO1 on PA21 mux E */
1012 #define MUX_PA21E_TC3_WO1               _L(4)
1013 #define PINMUX_PA21E_TC3_WO1       ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1)
1014 #define PORT_PA21E_TC3_WO1     (_UL(1) << 21)
1015 #define PIN_PB01E_TC3_WO1              _L(33) /**< \brief TC3 signal: WO1 on PB01 mux E */
1016 #define MUX_PB01E_TC3_WO1               _L(4)
1017 #define PINMUX_PB01E_TC3_WO1       ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1)
1018 #define PORT_PB01E_TC3_WO1     (_UL(1) <<  1)
1019 #define PIN_PB23E_TC3_WO1              _L(55) /**< \brief TC3 signal: WO1 on PB23 mux E */
1020 #define MUX_PB23E_TC3_WO1               _L(4)
1021 #define PINMUX_PB23E_TC3_WO1       ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1)
1022 #define PORT_PB23E_TC3_WO1     (_UL(1) << 23)
1023 /* ========== PORT definition for DAC peripheral ========== */
1024 #define PIN_PA02B_DAC_VOUT0             _L(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
1025 #define MUX_PA02B_DAC_VOUT0             _L(1)
1026 #define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
1027 #define PORT_PA02B_DAC_VOUT0   (_UL(1) <<  2)
1028 #define PIN_PA05B_DAC_VOUT1             _L(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
1029 #define MUX_PA05B_DAC_VOUT1             _L(1)
1030 #define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
1031 #define PORT_PA05B_DAC_VOUT1   (_UL(1) <<  5)
1032 #define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
1033 #define MUX_PA03B_DAC_VREFP             _L(1)
1034 #define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
1035 #define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
1036 /* ========== PORT definition for SERCOM5 peripheral ========== */
1037 #define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
1038 #define MUX_PA22D_SERCOM5_PAD0          _L(3)
1039 #define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
1040 #define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
1041 #define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
1042 #define MUX_PB02D_SERCOM5_PAD0          _L(3)
1043 #define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
1044 #define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
1045 #define PIN_PB30D_SERCOM5_PAD0         _L(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
1046 #define MUX_PB30D_SERCOM5_PAD0          _L(3)
1047 #define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
1048 #define PORT_PB30D_SERCOM5_PAD0  (_UL(1) << 30)
1049 #define PIN_PB16C_SERCOM5_PAD0         _L(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
1050 #define MUX_PB16C_SERCOM5_PAD0          _L(2)
1051 #define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
1052 #define PORT_PB16C_SERCOM5_PAD0  (_UL(1) << 16)
1053 #define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
1054 #define MUX_PA23D_SERCOM5_PAD1          _L(3)
1055 #define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
1056 #define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
1057 #define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
1058 #define MUX_PB03D_SERCOM5_PAD1          _L(3)
1059 #define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
1060 #define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
1061 #define PIN_PB31D_SERCOM5_PAD1         _L(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
1062 #define MUX_PB31D_SERCOM5_PAD1          _L(3)
1063 #define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
1064 #define PORT_PB31D_SERCOM5_PAD1  (_UL(1) << 31)
1065 #define PIN_PB17C_SERCOM5_PAD1         _L(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
1066 #define MUX_PB17C_SERCOM5_PAD1          _L(2)
1067 #define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
1068 #define PORT_PB17C_SERCOM5_PAD1  (_UL(1) << 17)
1069 #define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
1070 #define MUX_PA24D_SERCOM5_PAD2          _L(3)
1071 #define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
1072 #define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
1073 #define PIN_PB00D_SERCOM5_PAD2         _L(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
1074 #define MUX_PB00D_SERCOM5_PAD2          _L(3)
1075 #define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
1076 #define PORT_PB00D_SERCOM5_PAD2  (_UL(1) <<  0)
1077 #define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
1078 #define MUX_PB22D_SERCOM5_PAD2          _L(3)
1079 #define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
1080 #define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
1081 #define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
1082 #define MUX_PA20C_SERCOM5_PAD2          _L(2)
1083 #define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
1084 #define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
1085 #define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
1086 #define MUX_PA25D_SERCOM5_PAD3          _L(3)
1087 #define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
1088 #define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
1089 #define PIN_PB01D_SERCOM5_PAD3         _L(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
1090 #define MUX_PB01D_SERCOM5_PAD3          _L(3)
1091 #define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
1092 #define PORT_PB01D_SERCOM5_PAD3  (_UL(1) <<  1)
1093 #define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
1094 #define MUX_PB23D_SERCOM5_PAD3          _L(3)
1095 #define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
1096 #define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
1097 #define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
1098 #define MUX_PA21C_SERCOM5_PAD3          _L(2)
1099 #define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
1100 #define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
1101 /* ========== PORT definition for TC4 peripheral ========== */
1102 #define PIN_PA18E_TC4_WO0              _L(18) /**< \brief TC4 signal: WO0 on PA18 mux E */
1103 #define MUX_PA18E_TC4_WO0               _L(4)
1104 #define PINMUX_PA18E_TC4_WO0       ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0)
1105 #define PORT_PA18E_TC4_WO0     (_UL(1) << 18)
1106 #define PIN_PA14E_TC4_WO0              _L(14) /**< \brief TC4 signal: WO0 on PA14 mux E */
1107 #define MUX_PA14E_TC4_WO0               _L(4)
1108 #define PINMUX_PA14E_TC4_WO0       ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0)
1109 #define PORT_PA14E_TC4_WO0     (_UL(1) << 14)
1110 #define PIN_PA19E_TC4_WO1              _L(19) /**< \brief TC4 signal: WO1 on PA19 mux E */
1111 #define MUX_PA19E_TC4_WO1               _L(4)
1112 #define PINMUX_PA19E_TC4_WO1       ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1)
1113 #define PORT_PA19E_TC4_WO1     (_UL(1) << 19)
1114 #define PIN_PA15E_TC4_WO1              _L(15) /**< \brief TC4 signal: WO1 on PA15 mux E */
1115 #define MUX_PA15E_TC4_WO1               _L(4)
1116 #define PINMUX_PA15E_TC4_WO1       ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1)
1117 #define PORT_PA15E_TC4_WO1     (_UL(1) << 15)
1118 /* ========== PORT definition for ADC peripheral ========== */
1119 #define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
1120 #define MUX_PA02B_ADC_AIN0              _L(1)
1121 #define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
1122 #define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
1123 #define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
1124 #define MUX_PA03B_ADC_AIN1              _L(1)
1125 #define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
1126 #define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
1127 #define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
1128 #define MUX_PB08B_ADC_AIN2              _L(1)
1129 #define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
1130 #define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
1131 #define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
1132 #define MUX_PB09B_ADC_AIN3              _L(1)
1133 #define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
1134 #define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
1135 #define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
1136 #define MUX_PA04B_ADC_AIN4              _L(1)
1137 #define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
1138 #define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
1139 #define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
1140 #define MUX_PA05B_ADC_AIN5              _L(1)
1141 #define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
1142 #define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
1143 #define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
1144 #define MUX_PA06B_ADC_AIN6              _L(1)
1145 #define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
1146 #define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
1147 #define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
1148 #define MUX_PA07B_ADC_AIN7              _L(1)
1149 #define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
1150 #define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
1151 #define PIN_PB00B_ADC_AIN8             _L(32) /**< \brief ADC signal: AIN8 on PB00 mux B */
1152 #define MUX_PB00B_ADC_AIN8              _L(1)
1153 #define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
1154 #define PORT_PB00B_ADC_AIN8    (_UL(1) <<  0)
1155 #define PIN_PB01B_ADC_AIN9             _L(33) /**< \brief ADC signal: AIN9 on PB01 mux B */
1156 #define MUX_PB01B_ADC_AIN9              _L(1)
1157 #define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
1158 #define PORT_PB01B_ADC_AIN9    (_UL(1) <<  1)
1159 #define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
1160 #define MUX_PB02B_ADC_AIN10             _L(1)
1161 #define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
1162 #define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
1163 #define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
1164 #define MUX_PB03B_ADC_AIN11             _L(1)
1165 #define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
1166 #define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
1167 #define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
1168 #define MUX_PB04B_ADC_AIN12             _L(1)
1169 #define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
1170 #define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
1171 #define PIN_PB05B_ADC_AIN13            _L(37) /**< \brief ADC signal: AIN13 on PB05 mux B */
1172 #define MUX_PB05B_ADC_AIN13             _L(1)
1173 #define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
1174 #define PORT_PB05B_ADC_AIN13   (_UL(1) <<  5)
1175 #define PIN_PB06B_ADC_AIN14            _L(38) /**< \brief ADC signal: AIN14 on PB06 mux B */
1176 #define MUX_PB06B_ADC_AIN14             _L(1)
1177 #define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
1178 #define PORT_PB06B_ADC_AIN14   (_UL(1) <<  6)
1179 #define PIN_PB07B_ADC_AIN15            _L(39) /**< \brief ADC signal: AIN15 on PB07 mux B */
1180 #define MUX_PB07B_ADC_AIN15             _L(1)
1181 #define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
1182 #define PORT_PB07B_ADC_AIN15   (_UL(1) <<  7)
1183 #define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
1184 #define MUX_PA08B_ADC_AIN16             _L(1)
1185 #define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
1186 #define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
1187 #define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
1188 #define MUX_PA09B_ADC_AIN17             _L(1)
1189 #define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
1190 #define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
1191 #define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
1192 #define MUX_PA10B_ADC_AIN18             _L(1)
1193 #define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
1194 #define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
1195 #define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
1196 #define MUX_PA11B_ADC_AIN19             _L(1)
1197 #define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
1198 #define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
1199 #define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
1200 #define MUX_PA04B_ADC_VREFP             _L(1)
1201 #define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
1202 #define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
1203 /* ========== PORT definition for AC peripheral ========== */
1204 #define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
1205 #define MUX_PA04B_AC_AIN0               _L(1)
1206 #define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
1207 #define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
1208 #define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
1209 #define MUX_PA05B_AC_AIN1               _L(1)
1210 #define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
1211 #define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
1212 #define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
1213 #define MUX_PA06B_AC_AIN2               _L(1)
1214 #define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
1215 #define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
1216 #define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
1217 #define MUX_PA07B_AC_AIN3               _L(1)
1218 #define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
1219 #define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
1220 #define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
1221 #define MUX_PA12H_AC_CMP0               _L(7)
1222 #define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
1223 #define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
1224 #define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
1225 #define MUX_PA18H_AC_CMP0               _L(7)
1226 #define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
1227 #define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
1228 #define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
1229 #define MUX_PA13H_AC_CMP1               _L(7)
1230 #define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
1231 #define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
1232 #define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
1233 #define MUX_PA19H_AC_CMP1               _L(7)
1234 #define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
1235 #define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
1236 /* ========== PORT definition for OPAMP peripheral ========== */
1237 #define PIN_PA02B_OPAMP_OANEG0          _L(2) /**< \brief OPAMP signal: OANEG0 on PA02 mux B */
1238 #define MUX_PA02B_OPAMP_OANEG0          _L(1)
1239 #define PINMUX_PA02B_OPAMP_OANEG0  ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0)
1240 #define PORT_PA02B_OPAMP_OANEG0  (_UL(1) <<  2)
1241 #define PIN_PB05B_OPAMP_OANEG1         _L(37) /**< \brief OPAMP signal: OANEG1 on PB05 mux B */
1242 #define MUX_PB05B_OPAMP_OANEG1          _L(1)
1243 #define PINMUX_PB05B_OPAMP_OANEG1  ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1)
1244 #define PORT_PB05B_OPAMP_OANEG1  (_UL(1) <<  5)
1245 #define PIN_PB06B_OPAMP_OANEG2         _L(38) /**< \brief OPAMP signal: OANEG2 on PB06 mux B */
1246 #define MUX_PB06B_OPAMP_OANEG2          _L(1)
1247 #define PINMUX_PB06B_OPAMP_OANEG2  ((PIN_PB06B_OPAMP_OANEG2 << 16) | MUX_PB06B_OPAMP_OANEG2)
1248 #define PORT_PB06B_OPAMP_OANEG2  (_UL(1) <<  6)
1249 #define PIN_PA07B_OPAMP_OAOUT0          _L(7) /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */
1250 #define MUX_PA07B_OPAMP_OAOUT0          _L(1)
1251 #define PINMUX_PA07B_OPAMP_OAOUT0  ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0)
1252 #define PORT_PA07B_OPAMP_OAOUT0  (_UL(1) <<  7)
1253 #define PIN_PB08B_OPAMP_OAOUT1         _L(40) /**< \brief OPAMP signal: OAOUT1 on PB08 mux B */
1254 #define MUX_PB08B_OPAMP_OAOUT1          _L(1)
1255 #define PINMUX_PB08B_OPAMP_OAOUT1  ((PIN_PB08B_OPAMP_OAOUT1 << 16) | MUX_PB08B_OPAMP_OAOUT1)
1256 #define PORT_PB08B_OPAMP_OAOUT1  (_UL(1) <<  8)
1257 #define PIN_PA04B_OPAMP_OAOUT2          _L(4) /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */
1258 #define MUX_PA04B_OPAMP_OAOUT2          _L(1)
1259 #define PINMUX_PA04B_OPAMP_OAOUT2  ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2)
1260 #define PORT_PA04B_OPAMP_OAOUT2  (_UL(1) <<  4)
1261 #define PIN_PA06B_OPAMP_OAPOS0          _L(6) /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */
1262 #define MUX_PA06B_OPAMP_OAPOS0          _L(1)
1263 #define PINMUX_PA06B_OPAMP_OAPOS0  ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0)
1264 #define PORT_PA06B_OPAMP_OAPOS0  (_UL(1) <<  6)
1265 #define PIN_PB09B_OPAMP_OAPOS1         _L(41) /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */
1266 #define MUX_PB09B_OPAMP_OAPOS1          _L(1)
1267 #define PINMUX_PB09B_OPAMP_OAPOS1  ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1)
1268 #define PORT_PB09B_OPAMP_OAPOS1  (_UL(1) <<  9)
1269 #define PIN_PA05B_OPAMP_OAPOS2          _L(5) /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */
1270 #define MUX_PA05B_OPAMP_OAPOS2          _L(1)
1271 #define PINMUX_PA05B_OPAMP_OAPOS2  ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2)
1272 #define PORT_PA05B_OPAMP_OAPOS2  (_UL(1) <<  5)
1273 /* ========== PORT definition for CCL peripheral ========== */
1274 #define PIN_PA04I_CCL_IN0               _L(4) /**< \brief CCL signal: IN0 on PA04 mux I */
1275 #define MUX_PA04I_CCL_IN0               _L(8)
1276 #define PINMUX_PA04I_CCL_IN0       ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0)
1277 #define PORT_PA04I_CCL_IN0     (_UL(1) <<  4)
1278 #define PIN_PA16I_CCL_IN0              _L(16) /**< \brief CCL signal: IN0 on PA16 mux I */
1279 #define MUX_PA16I_CCL_IN0               _L(8)
1280 #define PINMUX_PA16I_CCL_IN0       ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0)
1281 #define PORT_PA16I_CCL_IN0     (_UL(1) << 16)
1282 #define PIN_PB22I_CCL_IN0              _L(54) /**< \brief CCL signal: IN0 on PB22 mux I */
1283 #define MUX_PB22I_CCL_IN0               _L(8)
1284 #define PINMUX_PB22I_CCL_IN0       ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0)
1285 #define PORT_PB22I_CCL_IN0     (_UL(1) << 22)
1286 #define PIN_PA05I_CCL_IN1               _L(5) /**< \brief CCL signal: IN1 on PA05 mux I */
1287 #define MUX_PA05I_CCL_IN1               _L(8)
1288 #define PINMUX_PA05I_CCL_IN1       ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1)
1289 #define PORT_PA05I_CCL_IN1     (_UL(1) <<  5)
1290 #define PIN_PA17I_CCL_IN1              _L(17) /**< \brief CCL signal: IN1 on PA17 mux I */
1291 #define MUX_PA17I_CCL_IN1               _L(8)
1292 #define PINMUX_PA17I_CCL_IN1       ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1)
1293 #define PORT_PA17I_CCL_IN1     (_UL(1) << 17)
1294 #define PIN_PB00I_CCL_IN1              _L(32) /**< \brief CCL signal: IN1 on PB00 mux I */
1295 #define MUX_PB00I_CCL_IN1               _L(8)
1296 #define PINMUX_PB00I_CCL_IN1       ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1)
1297 #define PORT_PB00I_CCL_IN1     (_UL(1) <<  0)
1298 #define PIN_PA06I_CCL_IN2               _L(6) /**< \brief CCL signal: IN2 on PA06 mux I */
1299 #define MUX_PA06I_CCL_IN2               _L(8)
1300 #define PINMUX_PA06I_CCL_IN2       ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2)
1301 #define PORT_PA06I_CCL_IN2     (_UL(1) <<  6)
1302 #define PIN_PA18I_CCL_IN2              _L(18) /**< \brief CCL signal: IN2 on PA18 mux I */
1303 #define MUX_PA18I_CCL_IN2               _L(8)
1304 #define PINMUX_PA18I_CCL_IN2       ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2)
1305 #define PORT_PA18I_CCL_IN2     (_UL(1) << 18)
1306 #define PIN_PB01I_CCL_IN2              _L(33) /**< \brief CCL signal: IN2 on PB01 mux I */
1307 #define MUX_PB01I_CCL_IN2               _L(8)
1308 #define PINMUX_PB01I_CCL_IN2       ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2)
1309 #define PORT_PB01I_CCL_IN2     (_UL(1) <<  1)
1310 #define PIN_PA08I_CCL_IN3               _L(8) /**< \brief CCL signal: IN3 on PA08 mux I */
1311 #define MUX_PA08I_CCL_IN3               _L(8)
1312 #define PINMUX_PA08I_CCL_IN3       ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3)
1313 #define PORT_PA08I_CCL_IN3     (_UL(1) <<  8)
1314 #define PIN_PA30I_CCL_IN3              _L(30) /**< \brief CCL signal: IN3 on PA30 mux I */
1315 #define MUX_PA30I_CCL_IN3               _L(8)
1316 #define PINMUX_PA30I_CCL_IN3       ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3)
1317 #define PORT_PA30I_CCL_IN3     (_UL(1) << 30)
1318 #define PIN_PA09I_CCL_IN4               _L(9) /**< \brief CCL signal: IN4 on PA09 mux I */
1319 #define MUX_PA09I_CCL_IN4               _L(8)
1320 #define PINMUX_PA09I_CCL_IN4       ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4)
1321 #define PORT_PA09I_CCL_IN4     (_UL(1) <<  9)
1322 #define PIN_PA10I_CCL_IN5              _L(10) /**< \brief CCL signal: IN5 on PA10 mux I */
1323 #define MUX_PA10I_CCL_IN5               _L(8)
1324 #define PINMUX_PA10I_CCL_IN5       ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5)
1325 #define PORT_PA10I_CCL_IN5     (_UL(1) << 10)
1326 #define PIN_PB10I_CCL_IN5              _L(42) /**< \brief CCL signal: IN5 on PB10 mux I */
1327 #define MUX_PB10I_CCL_IN5               _L(8)
1328 #define PINMUX_PB10I_CCL_IN5       ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5)
1329 #define PORT_PB10I_CCL_IN5     (_UL(1) << 10)
1330 #define PIN_PA22I_CCL_IN6              _L(22) /**< \brief CCL signal: IN6 on PA22 mux I */
1331 #define MUX_PA22I_CCL_IN6               _L(8)
1332 #define PINMUX_PA22I_CCL_IN6       ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6)
1333 #define PORT_PA22I_CCL_IN6     (_UL(1) << 22)
1334 #define PIN_PB06I_CCL_IN6              _L(38) /**< \brief CCL signal: IN6 on PB06 mux I */
1335 #define MUX_PB06I_CCL_IN6               _L(8)
1336 #define PINMUX_PB06I_CCL_IN6       ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6)
1337 #define PORT_PB06I_CCL_IN6     (_UL(1) <<  6)
1338 #define PIN_PA23I_CCL_IN7              _L(23) /**< \brief CCL signal: IN7 on PA23 mux I */
1339 #define MUX_PA23I_CCL_IN7               _L(8)
1340 #define PINMUX_PA23I_CCL_IN7       ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7)
1341 #define PORT_PA23I_CCL_IN7     (_UL(1) << 23)
1342 #define PIN_PB07I_CCL_IN7              _L(39) /**< \brief CCL signal: IN7 on PB07 mux I */
1343 #define MUX_PB07I_CCL_IN7               _L(8)
1344 #define PINMUX_PB07I_CCL_IN7       ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7)
1345 #define PORT_PB07I_CCL_IN7     (_UL(1) <<  7)
1346 #define PIN_PA24I_CCL_IN8              _L(24) /**< \brief CCL signal: IN8 on PA24 mux I */
1347 #define MUX_PA24I_CCL_IN8               _L(8)
1348 #define PINMUX_PA24I_CCL_IN8       ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8)
1349 #define PORT_PA24I_CCL_IN8     (_UL(1) << 24)
1350 #define PIN_PB08I_CCL_IN8              _L(40) /**< \brief CCL signal: IN8 on PB08 mux I */
1351 #define MUX_PB08I_CCL_IN8               _L(8)
1352 #define PINMUX_PB08I_CCL_IN8       ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8)
1353 #define PORT_PB08I_CCL_IN8     (_UL(1) <<  8)
1354 #define PIN_PB14I_CCL_IN9              _L(46) /**< \brief CCL signal: IN9 on PB14 mux I */
1355 #define MUX_PB14I_CCL_IN9               _L(8)
1356 #define PINMUX_PB14I_CCL_IN9       ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9)
1357 #define PORT_PB14I_CCL_IN9     (_UL(1) << 14)
1358 #define PIN_PB15I_CCL_IN10             _L(47) /**< \brief CCL signal: IN10 on PB15 mux I */
1359 #define MUX_PB15I_CCL_IN10              _L(8)
1360 #define PINMUX_PB15I_CCL_IN10      ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10)
1361 #define PORT_PB15I_CCL_IN10    (_UL(1) << 15)
1362 #define PIN_PB16I_CCL_IN11             _L(48) /**< \brief CCL signal: IN11 on PB16 mux I */
1363 #define MUX_PB16I_CCL_IN11              _L(8)
1364 #define PINMUX_PB16I_CCL_IN11      ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11)
1365 #define PORT_PB16I_CCL_IN11    (_UL(1) << 16)
1366 #define PIN_PA07I_CCL_OUT0              _L(7) /**< \brief CCL signal: OUT0 on PA07 mux I */
1367 #define MUX_PA07I_CCL_OUT0              _L(8)
1368 #define PINMUX_PA07I_CCL_OUT0      ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0)
1369 #define PORT_PA07I_CCL_OUT0    (_UL(1) <<  7)
1370 #define PIN_PA19I_CCL_OUT0             _L(19) /**< \brief CCL signal: OUT0 on PA19 mux I */
1371 #define MUX_PA19I_CCL_OUT0              _L(8)
1372 #define PINMUX_PA19I_CCL_OUT0      ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0)
1373 #define PORT_PA19I_CCL_OUT0    (_UL(1) << 19)
1374 #define PIN_PB02I_CCL_OUT0             _L(34) /**< \brief CCL signal: OUT0 on PB02 mux I */
1375 #define MUX_PB02I_CCL_OUT0              _L(8)
1376 #define PINMUX_PB02I_CCL_OUT0      ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0)
1377 #define PORT_PB02I_CCL_OUT0    (_UL(1) <<  2)
1378 #define PIN_PB23I_CCL_OUT0             _L(55) /**< \brief CCL signal: OUT0 on PB23 mux I */
1379 #define MUX_PB23I_CCL_OUT0              _L(8)
1380 #define PINMUX_PB23I_CCL_OUT0      ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0)
1381 #define PORT_PB23I_CCL_OUT0    (_UL(1) << 23)
1382 #define PIN_PA11I_CCL_OUT1             _L(11) /**< \brief CCL signal: OUT1 on PA11 mux I */
1383 #define MUX_PA11I_CCL_OUT1              _L(8)
1384 #define PINMUX_PA11I_CCL_OUT1      ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1)
1385 #define PORT_PA11I_CCL_OUT1    (_UL(1) << 11)
1386 #define PIN_PA31I_CCL_OUT1             _L(31) /**< \brief CCL signal: OUT1 on PA31 mux I */
1387 #define MUX_PA31I_CCL_OUT1              _L(8)
1388 #define PINMUX_PA31I_CCL_OUT1      ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1)
1389 #define PORT_PA31I_CCL_OUT1    (_UL(1) << 31)
1390 #define PIN_PB11I_CCL_OUT1             _L(43) /**< \brief CCL signal: OUT1 on PB11 mux I */
1391 #define MUX_PB11I_CCL_OUT1              _L(8)
1392 #define PINMUX_PB11I_CCL_OUT1      ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1)
1393 #define PORT_PB11I_CCL_OUT1    (_UL(1) << 11)
1394 #define PIN_PA25I_CCL_OUT2             _L(25) /**< \brief CCL signal: OUT2 on PA25 mux I */
1395 #define MUX_PA25I_CCL_OUT2              _L(8)
1396 #define PINMUX_PA25I_CCL_OUT2      ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2)
1397 #define PORT_PA25I_CCL_OUT2    (_UL(1) << 25)
1398 #define PIN_PB09I_CCL_OUT2             _L(41) /**< \brief CCL signal: OUT2 on PB09 mux I */
1399 #define MUX_PB09I_CCL_OUT2              _L(8)
1400 #define PINMUX_PB09I_CCL_OUT2      ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2)
1401 #define PORT_PB09I_CCL_OUT2    (_UL(1) <<  9)
1402 #define PIN_PB17I_CCL_OUT3             _L(49) /**< \brief CCL signal: OUT3 on PB17 mux I */
1403 #define MUX_PB17I_CCL_OUT3              _L(8)
1404 #define PINMUX_PB17I_CCL_OUT3      ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3)
1405 #define PORT_PB17I_CCL_OUT3    (_UL(1) << 17)
1406 
1407 #endif /* _SAML21J18B_PIO_ */
1408