1 /* 2 * Xilinx Processor System Gigabit Ethernet controller (GEM) driver 3 * 4 * PHY management interface and related data 5 * 6 * Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 #ifndef _ZEPHYR_DRIVERS_ETHERNET_PHY_XLNX_GEM_H_ 11 #define _ZEPHYR_DRIVERS_ETHERNET_PHY_XLNX_GEM_H_ 12 13 #include <kernel.h> 14 #include <zephyr/types.h> 15 16 /* Event codes used to indicate a particular state change to the driver */ 17 #define PHY_XLNX_GEM_EVENT_LINK_SPEED_CHANGED (1 << 0) 18 #define PHY_XLNX_GEM_EVENT_LINK_STATE_CHANGED (1 << 1) 19 #define PHY_XLNX_GEM_EVENT_AUTONEG_COMPLETE (1 << 2) 20 21 /* PHY register addresses & constants that are not vendor-specific */ 22 #define PHY_IDENTIFIER_1_REGISTER 2 23 #define PHY_IDENTIFIER_2_REGISTER 3 24 25 /* PHY registers & constants -> Marvell Alaska specific */ 26 27 /* Marvell PHY ID bits [3..0] = revision -> discard during ID check */ 28 #define PHY_MRVL_PHY_ID_MODEL_MASK 0xFFFFFFF0 29 #define PHY_MRVL_PHY_ID_MODEL_88E1111 0x01410CC0 30 #define PHY_MRVL_PHY_ID_MODEL_88E151X 0x01410DD0 31 32 #define PHY_MRVL_BASE_REGISTERS_PAGE 0 33 #define PHY_MRVL_COPPER_CONTROL_REGISTER 0 34 #define PHY_MRVL_COPPER_STATUS_REGISTER 1 35 #define PHY_MRVL_COPPER_AUTONEG_ADV_REGISTER 4 36 #define PHY_MRVL_COPPER_LINK_PARTNER_ABILITY_REGISTER 5 37 #define PHY_MRVL_1000BASET_CONTROL_REGISTER 9 38 #define PHY_MRVL_COPPER_CONTROL_1_REGISTER 16 39 #define PHY_MRVL_COPPER_STATUS_1_REGISTER 17 40 #define PHY_MRVL_COPPER_INT_ENABLE_REGISTER 18 41 #define PHY_MRVL_COPPER_INT_STATUS_REGISTER 19 42 #define PHY_MRVL_COPPER_PAGE_SWITCH_REGISTER 22 43 #define PHY_MRVL_GENERAL_CONTROL_1_REGISTER 20 44 #define PHY_MRVL_GENERAL_CONTROL_1_PAGE 18 45 46 #define PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT (1 << 15) 47 48 #define PHY_MRVL_COPPER_CONTROL_RESET_BIT (1 << 15) 49 #define PHY_MRVL_COPPER_CONTROL_AUTONEG_ENABLE_BIT (1 << 12) 50 51 #define PHY_MRVL_ADV_1000BASET_FDX_BIT (1 << 9) 52 #define PHY_MRVL_ADV_1000BASET_HDX_BIT (1 << 8) 53 #define PHY_MRVL_ADV_100BASET_FDX_BIT (1 << 8) 54 #define PHY_MRVL_ADV_100BASET_HDX_BIT (1 << 7) 55 #define PHY_MRVL_ADV_10BASET_FDX_BIT (1 << 6) 56 #define PHY_MRVL_ADV_10BASET_HDX_BIT (1 << 5) 57 #define PHY_MRVL_ADV_SELECTOR_802_3 0x0001 58 59 #define PHY_MRVL_MDIX_CONFIG_MASK 0x0003 60 #define PHY_MRVL_MDIX_CONFIG_SHIFT 5 61 #define PHY_MRVL_MDIX_AUTO_CROSSOVER_ENABLE 0x0003 62 #define PHY_MRVL_MODE_CONFIG_MASK 0x0003 63 #define PHY_MRVL_MODE_CONFIG_SHIFT 0 64 65 #define PHY_MRVL_COPPER_SPEED_CHANGED_INT_BIT (1 << 14) 66 #define PHY_MRVL_COPPER_DUPLEX_CHANGED_INT_BIT (1 << 13) 67 #define PHY_MRVL_COPPER_AUTONEG_COMPLETED_INT_BIT (1 << 11) 68 #define PHY_MRVL_COPPER_LINK_STATUS_CHANGED_INT_BIT (1 << 10) 69 #define PHY_MRVL_COPPER_LINK_STATUS_BIT_SHIFT 5 70 71 #define PHY_MRVL_LINK_SPEED_SHIFT 14 72 #define PHY_MRVL_LINK_SPEED_MASK 0x3 73 #define PHY_MRVL_LINK_SPEED_10MBIT 0 74 #define PHY_MRVL_LINK_SPEED_100MBIT 1 75 #define PHY_MRVL_LINK_SPEED_1GBIT 2 76 77 /*TI TLK105 & DP83822*/ 78 79 /* TI PHY ID bits [3..0] = revision -> discard during ID check */ 80 #define PHY_TI_PHY_ID_MODEL_MASK 0xFFFFFFF0 81 #define PHY_TI_PHY_ID_MODEL_DP83822 0x2000A240 82 #define PHY_TI_PHY_ID_MODEL_TLK105 0x2000A210 83 84 #define PHY_TI_PHY_SPECIFIC_CONTROL_REGISTER 0x0010 85 #define PHY_TI_BASIC_MODE_CONTROL_REGISTER 0x0000 86 #define PHY_TI_BASIC_MODE_STATUS_REGISTER 0x0001 87 #define PHY_TI_AUTONEG_ADV_REGISTER 0x0004 88 #define PHY_TI_CONTROL_REGISTER_1 0x0009 89 #define PHY_TI_PHY_STATUS_REGISTER 0x0010 90 #define PHY_TI_MII_INTERRUPT_STATUS_REGISTER_1 0x0012 91 #define PHY_TI_LED_CONTROL_REGISTER 0x0018 92 #define PHY_TI_PHY_CONTROL_REGISTER 0x0019 93 94 #define PHY_TI_BASIC_MODE_CONTROL_RESET_BIT (1 << 15) 95 #define PHY_TI_BASIC_MODE_CONTROL_AUTONEG_ENABLE_BIT (1 << 12) 96 97 #define PHY_TI_BASIC_MODE_STATUS_LINK_STATUS_BIT (1 << 2) 98 99 #define PHY_TI_LINK_STATUS_CHANGED_INT_BIT (1 << 13) 100 #define PHY_TI_SPEED_CHANGED_INT_BIT (1 << 12) 101 #define PHY_TI_DUPLEX_CHANGED_INT_BIT (1 << 11) 102 #define PHY_TI_AUTONEG_COMPLETED_INT_BIT (1 << 10) 103 104 #define PHY_TI_ADV_SELECTOR_802_3 0x0001 105 #define PHY_TI_ADV_100BASET_FDX_BIT (1 << 8) 106 #define PHY_TI_ADV_100BASET_HDX_BIT (1 << 7) 107 #define PHY_TI_ADV_10BASET_FDX_BIT (1 << 6) 108 #define PHY_TI_ADV_10BASET_HDX_BIT (1 << 5) 109 110 #define PHY_TI_CR1_ROBUST_AUTO_MDIX_BIT (1 << 5) 111 112 #define PHY_TI_PHY_CONTROL_AUTO_MDIX_ENABLE_BIT (1 << 15) 113 #define PHY_TI_PHY_CONTROL_FORCE_MDIX_BIT (1 << 14) 114 #define PHY_TI_PHY_CONTROL_LED_CONFIG_LINK_ONLY_BIT (1 << 5) 115 116 #define PHY_TI_LED_CONTROL_BLINK_RATE_SHIFT 9 117 #define PHY_TI_LED_CONTROL_BLINK_RATE_20HZ 0 118 #define PHY_TI_LED_CONTROL_BLINK_RATE_10HZ 1 119 #define PHY_TI_LED_CONTROL_BLINK_RATE_5HZ 2 120 #define PHY_TI_LED_CONTROL_BLINK_RATE_2HZ 3 121 122 #define PHY_TI_PHY_STATUS_LINK_BIT (1 << 0) 123 #define PHY_TI_PHY_STATUS_SPEED_BIT (1 << 1) 124 125 /** 126 * @brief Vendor-specific PHY management function pointer table struct 127 * 128 * Contains the PHY management function pointers for a specific PHY 129 * make or model. 130 */ 131 struct phy_xlnx_gem_api { 132 void (*phy_reset_func)(const struct device *dev); 133 void (*phy_configure_func)(const struct device *dev); 134 uint16_t (*phy_poll_status_change_func)(const struct device *dev); 135 uint8_t (*phy_poll_link_status_func)(const struct device *dev); 136 enum eth_xlnx_link_speed (*phy_poll_link_speed_func)(const struct device *dev); 137 }; 138 139 /** 140 * @brief Supported PHY list entry struct 141 * 142 * Contains the PHY management function pointers for a specific PHY 143 * make or model. 144 */ 145 struct phy_xlnx_gem_supported_dev { 146 uint32_t phy_id; 147 uint32_t phy_id_mask; 148 struct phy_xlnx_gem_api *api; 149 const char *identifier; 150 }; 151 152 /* PHY identification function -> generic, not vendor-specific */ 153 int phy_xlnx_gem_detect(const struct device *dev); 154 155 #endif /* _ZEPHYR_DRIVERS_ETHERNET_PHY_XLNX_GEM_H_ */ 156 157 /* EOF */ 158
