1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _FSL_PHY_H_ 9 #define _FSL_PHY_H_ 10 11 #include "fsl_enet.h" 12 13 /*! 14 * @addtogroup phy_driver 15 * @{ 16 */ 17 18 /******************************************************************************* 19 * Definitions 20 ******************************************************************************/ 21 22 /*! @brief PHY driver version */ 23 #define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ 24 25 /*! @brief Defines the PHY registers. */ 26 #define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ 27 #define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ 28 #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ 29 #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ 30 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ 31 #define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ 32 #define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ 33 34 #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ 35 36 /*! @brief Defines the mask flag in basic control register. */ 37 #define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ 38 #define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ 39 #define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ 40 #define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ 41 #define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ 42 #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ 43 #define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ 44 45 /*!@brief Defines the mask flag of operation mode in control two register*/ 46 #define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ 47 #define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 48 #define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ 49 #define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ 50 #define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ 51 #define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ 52 #define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ 53 #define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ 54 #define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ 55 #define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) 56 57 /*! @brief Defines the mask flag in basic status register. */ 58 #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ 59 #define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ 60 #define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ 61 62 /*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ 63 #define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ 64 #define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ 65 #define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ 66 #define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ 67 #define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ 68 69 /*! @brief Defines the PHY status. */ 70 enum 71 { 72 kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ 73 kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ 74 }; 75 76 /*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ 77 typedef enum _phy_speed 78 { 79 kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ 80 kPHY_Speed100M /*!< ENET PHY 100M speed. */ 81 } phy_speed_t; 82 83 /*! @brief Defines the PHY link duplex. */ 84 typedef enum _phy_duplex 85 { 86 kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ 87 kPHY_FullDuplex /*!< ENET PHY full duplex. */ 88 } phy_duplex_t; 89 90 /*! @brief Defines the PHY loopback mode. */ 91 typedef enum _phy_loop 92 { 93 kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ 94 kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ 95 } phy_loop_t; 96 97 /******************************************************************************* 98 * API 99 ******************************************************************************/ 100 101 #if defined(__cplusplus) 102 extern "C" { 103 #endif 104 105 /*! 106 * @name PHY Driver 107 * @{ 108 */ 109 110 /*! 111 * @brief Initializes PHY. 112 * 113 * This function initialize the SMI interface and initialize PHY. 114 * The SMI is the MII management interface between PHY and MAC, which should be 115 * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. 116 * 117 * @param base ENET peripheral base address. 118 * @param phyAddr The PHY address. 119 * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. 120 * @retval kStatus_Success PHY initialize success 121 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 122 * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail 123 */ 124 status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); 125 126 /*! 127 * @brief PHY Write function. This function write data over the SMI to 128 * the specified PHY register. This function is called by all PHY interfaces. 129 * 130 * @param base ENET peripheral base address. 131 * @param phyAddr The PHY address. 132 * @param phyReg The PHY register. 133 * @param data The data written to the PHY register. 134 * @retval kStatus_Success PHY write success 135 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 136 */ 137 status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); 138 139 /*! 140 * @brief PHY Read function. This interface read data over the SMI from the 141 * specified PHY register. This function is called by all PHY interfaces. 142 * 143 * @param base ENET peripheral base address. 144 * @param phyAddr The PHY address. 145 * @param phyReg The PHY register. 146 * @param dataPtr The address to store the data read from the PHY register. 147 * @retval kStatus_Success PHY read success 148 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 149 */ 150 status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); 151 152 /*! 153 * @brief Enables/disables PHY loopback. 154 * 155 * @param base ENET peripheral base address. 156 * @param phyAddr The PHY address. 157 * @param mode The loopback mode to be enabled, please see "phy_loop_t". 158 * the two loopback mode should not be both set. when one loopback mode is set 159 * the other one should be disabled. 160 * @param speed PHY speed for loopback mode. 161 * @param enable True to enable, false to disable. 162 * @retval kStatus_Success PHY loopback success 163 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 164 */ 165 status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); 166 167 /*! 168 * @brief Gets the PHY link status. 169 * 170 * @param base ENET peripheral base address. 171 * @param phyAddr The PHY address. 172 * @param status The link up or down status of the PHY. 173 * - true the link is up. 174 * - false the link is down. 175 * @retval kStatus_Success PHY get link status success 176 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 177 */ 178 status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); 179 180 /*! 181 * @brief Gets the PHY link speed and duplex. 182 * 183 * @param base ENET peripheral base address. 184 * @param phyAddr The PHY address. 185 * @param speed The address of PHY link speed. 186 * @param duplex The link duplex of PHY. 187 * @retval kStatus_Success PHY get link speed and duplex success 188 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 189 */ 190 status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); 191 192 /* @} */ 193 194 #if defined(__cplusplus) 195 } 196 #endif 197 198 /*! @}*/ 199 200 #endif /* _FSL_PHY_H_ */ 201
