1 /***************************************************************************//** 2 * \file cy_ephy.h 3 * \version 1.20 4 * 5 * Provides an API declaration of the Ethernet Generic PHY driver 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2020 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 /** 26 * \addtogroup group_ephy 27 * \{ 28 * The PHY chip is outside of SoC. It has 15 IEEE specified standard registers. 29 * The EPHY driver implements those standard registers. It provides an API for 30 * PHY management abstraction layer. 31 * 32 * The functions and other declarations used in this driver are in cy_ephy.h. 33 * You can include cy_pdl.h (ModusToolbox only) to get access to all functions 34 * and declarations in the PDL. 35 * 36 * \note Apart from IEEE standard registers, optionally it has some vendor 37 * specific extended registers. The EPHY driver does not implement extended 38 * registers. Any access to PHY registers can be done by using MAC driver APIs, 39 * i.e, \ref Cy_ETHIF_PhyRegRead() and \ref Cy_ETHIF_PhyRegWrite(). 40 * 41 * 42 * \section group_ephy_configuration Configuration Considerations 43 * Code snippet for Initializing DP83867IR PHY chip 44 * 45 * \snippet ethernet/snippet/main.c snippet_Cy_EPHY_DP83867IR_Init 46 * 47 * \section group_ephy_more_information More Information 48 * 49 * Refer to the technical reference manual (TRM) and the device datasheet. 50 * 51 * \section group_ephy_MISRA MISRA-C Compliance 52 * The EPHY driver does not have any specific deviation 53 * 54 * \section group_ephy_Changelog Changelog 55 * <table class="doxtable"> 56 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 57 * <tr> 58 * <td>1.20</td> 59 * <td>Changed naming conventions as per standard.</td> 60 * <td>Code Enhancement.</td> 61 * </tr> 62 * <tr> 63 * <td>1.10</td> 64 * <td>Updated \ref Cy_EPHY_Configure() function and Added new macros for BMSR register.</td> 65 * <td>Bug fixes and support enhancement for 1Gbps configuration.</td> 66 * </tr> 67 * <tr> 68 * <td>1.0</td> 69 * <td>Initial version</td> 70 * <td></td> 71 * </tr> 72 * </table> 73 * 74 * \defgroup group_ephy_macros Macros 75 * \defgroup group_ephy_functions Functions 76 * \defgroup group_ephy_enums Enumerated Types 77 * \defgroup group_ephy_data_structures Data Structures 78 */ 79 80 #if !defined (CY_EPHY_H) 81 #define CY_EPHY_H 82 83 #include "cy_device.h" 84 85 #if defined (CY_IP_MXETH) 86 87 #include <stddef.h> 88 #include "cy_syslib.h" 89 90 #if defined(__cplusplus) 91 extern "C" { 92 #endif 93 94 /** \addtogroup group_ephy_macros 95 * \{ 96 */ 97 98 /** Driver major version */ 99 #define CY_EPHY_DRV_VERSION_MAJOR 1 100 101 /** Driver minor version */ 102 #define CY_EPHY_DRV_VERSION_MINOR 20 103 104 /** EPHY driver ID */ 105 #define CY_EPHY_ID CY_PDL_DRV_ID(0x70U) 106 107 /** \} group_ephy_macros */ 108 109 /*************************************** 110 * Constants 111 ***************************************/ 112 113 /** \cond INTERNAL */ 114 115 #define MIN_PHY_ADDRESS 0 116 #define MAX_PHY_ADDRESS 31 117 118 /** Naming and numbering of basic PHY registers. */ 119 #define PHYREG_00_BMCR (0x00UL) /**< Basic Mode Control Register. */ 120 #define PHYREG_01_BMSR (0x01UL) /**< Basic Mode Status Register. */ 121 #define PHYREG_02_PHYSID1 (0x02UL) /**< PHYS ID 1 */ 122 #define PHYREG_03_PHYSID2 (0x03UL) /**< PHYS ID 2 */ 123 #define PHYREG_04_ANAR (0x04UL) /**< Advertisement control reg */ 124 #define PHYREG_05_ANLPAR (0x05UL) /**< Auto-Negotiation Link Partner Ability Register */ 125 #define PHYREG_10_MSSR (0x0AUL) /**< Master slave status register */ 126 127 /** Bit fields for 'PHYREG_00_BMCR' the 'Basic Mode Control Register'. */ 128 #define PHYBMCR_SPEED_1000_Msk (0x0040UL) /**< Set Network speed. 1:1000Mbps 0:10Mbps */ 129 #define PHYBMCR_SPEED_1000_Pos (6UL) 130 #define PHYBMCR_FULL_DUPLEX_Msk (0x0100UL) /**< Full duplex. */ 131 #define PHYBMCR_FULL_DUPLEX_Pos (8UL) 132 #define PHYBMCR_AN_RESTART_Msk (0x0200UL) /**< Auto negotiation restart. */ 133 #define PHYBMCR_AN_RESTART_Pos (9UL) 134 #define PHYBMCR_ISOLATE_Msk (0x0400UL) /**< 1 = Isolates 0 = Normal operation. */ 135 #define PHYBMCR_ISOLATE_Pos (10UL) 136 #define PHYBMCR_AN_ENABLE_Msk (0x1000UL) /**< Enable auto negotiation. */ 137 #define PHYBMCR_AN_ENABLE_Pos (12UL) 138 #define PHYBMCR_SPEED_100_Msk (0x2000UL) /**< Set Network speed. 1:100Mbps 0:10Mbps */ 139 #define PHYBMCR_SPEED_100_Pos (13UL) 140 #define PHYBMCR_RESET_Msk (0x8000UL) /**< Reset the PHY. */ 141 #define PHYBMCR_RESET_Pos (15UL) 142 143 /** Bit fields for 'BMSR', 'Basic Mode Status Register' */ 144 #define PHYBMSR_EXT_CAPABILITY_Msk (0x0001UL) /**< 1 = Extended register capable */ 145 #define PHYBMSR_EXT_CAPABILITY_Pos (0UL) 146 #define PHYBMSR_JABBER_DETECTED_Msk (0x0002UL) /**< 1 = Jabber condition detected */ 147 #define PHYBMSR_JABBER_DETECTED_Pos (1UL) 148 #define PHYBMSR_LINK_STATUS_Msk (0x0004UL) /**< Link Status. 1=Link was good since last read of this register. (10/100/1000Mbps operation) 0=Link was lost since last read of this register.*/ 149 #define PHYBMSR_LINK_STATUS_Pos (2UL) 150 #define PHYBMSR_AN_ABILITY_Msk (0x0008UL) /**< 1 = Device is able to perform Auto-Negotiation.*/ 151 #define PHYBMSR_AN_ABILITY_Pos (3UL) 152 #define PHYBMSR_REMOTE_FAULT_Msk (0x0010UL) /**< 1 = Remote Fault condition detected. 0 = No remote fault condition detected */ 153 #define PHYBMSR_REMOTE_FAULT_Pos (4UL) 154 #define PHYBMSR_AN_COMPLETE_Msk (0x0020UL) /**< 1 = Auto-Negotiation process completed. 0 = Auto-Negotiation process not complete. */ 155 #define PHYBMSR_AN_COMPLETE_Pos (5UL) 156 #define PHYBMSR_EXT_STATUS_Msk (0x0100UL) /**< 1 = Extended status present in Reg.15 0 = Extended status not present. */ 157 #define PHYBMSR_EXT_STATUS_Pos (8UL) 158 #define PHYBMSR_100BASE_T2_HD_Msk (0x0200UL) /**< 1 = PHY able to perform half duplex 100BASE-T2. 0 = PHY not able to perform half duplex 100BASE-T2. */ 159 #define PHYBMSR_100BASE_T2_HD_Pos (9UL) 160 #define PHYBMSR_100BASE_T2_FD_Msk (0x0400UL) /**< 1 = PHY able to perform full duplex 100BASE-T2. 0 = PHY not able to perform full duplex 100BASE-T2. */ 161 #define PHYBMSR_100BASE_T2_FD_Pos (10UL) 162 #define PHYBMSR_10BASE_T_HD_Msk (0x0800UL) /**< 10BASE-T Half Duplex Capable */ 163 #define PHYBMSR_10BASE_T_HD_Pos (11UL) 164 #define PHYBMSR_10BASE_T_FD_Msk (0x1000UL) /**< 10BASE-T Full Duplex Capable */ 165 #define PHYBMSR_10BASE_T_FD_Pos (12UL) 166 #define PHYBMSR_100BASE_TX_HD_Msk (0x2000UL) /**< 100BASE-TX Half Duplex Capable */ 167 #define PHYBMSR_100BASE_TX_HD_Pos (13UL) 168 #define PHYBMSR_100BASE_TX_FD_Msk (0x4000UL) /**< 100BASE-TX Full Duplex Capable */ 169 #define PHYBMSR_100BASE_TX_FD_Pos (14UL) 170 #define PHYBMSR_100BASE_T4_Msk (0x8000UL) /**< 100BASE-T4 Capable */ 171 #define PHYBMSR_100BASE_T4_Pos (15UL) /**< 100BASE-T4 Capable */ 172 173 /** PHYREG_02_PHYSID1 */ 174 #define PHYID1_OUI_Msk (0xFFFFUL) /**< OUI: 6-21st bits */ 175 #define PHYID1_OUI_Pos (0UL) 176 177 /** PHYREG_03_PHYSID2 */ 178 #define PHYID2_REV_NUM_Msk (0x000FUL) /**< Revision Number */ 179 #define PHYID2_REV_NUM_Pos (0UL) 180 #define PHYID2_MODEL_NUM_Msk (0x03F0UL) /**< Model Number */ 181 #define PHYID2_MODEL_NUM_Pos (4UL) 182 #define PHYID2_OUI_LSB_Msk (0xFC00UL) /**< OUI_LSB: Assign to 0-5th bits of OUI */ 183 #define PHYID2_OUI_LSB_Pos (10UL) 184 185 #define PHYID_ID1_Msk (0xFFFF0000UL) /**< ID1 */ 186 #define PHYID_ID1_Pos (16UL) 187 #define PHYID_ID2_Msk (0xFFFFUL) /**< ID2 */ 188 #define PHYID_ID2_Pos (0UL) 189 190 /* Auto-Negotiation Advertisement Register (ANAR), Address 0x0004 */ 191 /** Description of all capabilities that can be advertised to the peer */ 192 #define PHYANAR_PSB_Msk (0x001FUL) /**< Protocol Selection Bits. <00001> indicates that this device supports IEEE 802.3. */ 193 #define PHYANAR_PSB_Pos (0UL) 194 #define PHYANAR_10BASE_T_Msk (0x0020UL) /**< Try for 10mbps half-duplex. */ 195 #define PHYANAR_10BASE_T_Pos (5UL) 196 #define PHYANAR_10BASE_T_FD_Msk (0x0040UL) /**< Try for 10mbps full-duplex. */ 197 #define PHYANAR_10BASE_T_FD_Pos (6UL) 198 #define PHYANAR_100BASE_TX_Msk (0x0080UL) /**< Try for 100mbps half-duplex. */ 199 #define PHYANAR_100BASE_TX_Pos (7UL) 200 #define PHYANAR_100BASE_TX_FD_Msk (0x0100UL) /**< Try for 100mbps full-duplex. */ 201 #define PHYANAR_100BASE_TX_FD_Pos (8UL) 202 #define PHYANAR_ALL_Msk ( PHYANAR_10BASE_T_Msk | PHYANAR_10BASE_T_FD_Msk | PHYANAR_100BASE_TX_Msk | PHYANAR_100BASE_TX_FD_Msk ) 203 204 /* Auto-Negotiation Link Partner Ability Register (ANLPAR), Address 0x0005 */ 205 #define ANLPAR_10_Msk (0x00000020UL) /**< 10BASE-Te Support */ 206 #define ANLPAR_10_Pos (5UL) /**< 10BASE-Te bit position */ 207 #define ANLPAR_10FD_Msk (0x00000040UL) /**< 10BASE-Te Full Duplex Support */ 208 #define ANLPAR_10FD_Pos (6UL) /**< 10BASE-Te Full Duplex bit position */ 209 210 #define ANLPAR_TX_Msk (0x00000080UL) /**< 100BASE-TX Support */ 211 #define ANLPAR_TX_Pos (7UL) /**< 100BASE-TX bit position */ 212 #define ANLPAR_TXFD_Msk (0x00000100UL) /**< 100BASE-TX Full Duplex Support */ 213 #define ANLPAR_TXFD_Pos (8UL) /**< 100BASE-TX Full Duplex bit position */ 214 #define ANLPAR_T4_Msk (0x00000200UL) /**< 100BASE-T4 Support */ 215 #define ANLPAR_T4_Pos (9UL) /**< 100BASE-T4 bit position */ 216 217 /* MASTER-SLAVE status register (Register 10) */ 218 #define MSSR_1000BASE_T_HALFDUPLEX_Msk (0x00000400UL) /**< 1000BASE-T Half-Duplex Capable */ 219 #define MSSR_1000BASE_T_HALFDUPLEX_Pos (10UL) /**< 1000BASE-T Half-Duplex bit position */ 220 #define MSSR_1000BASE_T_FULLDUPLEX_Msk (0x00000800UL) /**< 1000BASE-T Full-Duplex Capable */ 221 #define MSSR_1000BASE_T_FULLDUPLEX_Pos (11UL) /**< 1000BASE-T Full-Duplex bit position */ 222 223 224 /****************************************************************************** 225 * Global Enumerations definitions 226 ******************************************************************************/ 227 228 /* PHY state machine states */ 229 typedef enum { 230 CY_EPHY_DOWN, /**< PHY device and driver are not ready for anything */ 231 CY_EPHY_READY, /** < PHY is ready to send and receive packets, but the controller is not */ 232 CY_EPHY_UP, /**< The PHY and attached device are ready to do work */ 233 CY_EPHY_AN, /**< The PHY is currently negotiating the link state. Link is therefore down for now */ 234 CY_EPHY_RUNNING, /**< PHY is currently up, running, and possibly sending and/or receiving packets */ 235 } cy_en_ephy_state_t; 236 237 /** \endcond */ 238 239 /** 240 * \addtogroup group_ephy_enums 241 * \{ 242 */ 243 244 /** EPHY Driver error codes */ 245 typedef enum 246 { 247 CY_EPHY_SUCCESS = 0x00U, /**< Returned successful */ 248 CY_EPHY_AN_NOT_SUPPORTED = 0x01U, /**< Auto Negotiation is not supported */ 249 CY_EPHY_INVALID_SPEED = 0x02U, /**< Invalid speed */ 250 CY_EPHY_INVALID_DUPLEX = 0x03U, /**< Invalid duplex */ 251 CY_EPHY_ERROR = CY_EPHY_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter or Generic Error */ 252 } cy_en_ephy_status_t; 253 254 /** PHY Duplex Mode */ 255 typedef enum 256 { 257 CY_EPHY_DUPLEX_HALF, /**< half duplex */ 258 CY_EPHY_DUPLEX_FULL, /**< full duplex */ 259 CY_EPHY_DUPLEX_AUTO /**< both half/full duplex */ 260 } cy_en_ephy_duplex_t; 261 262 /** PHY Speed */ 263 typedef enum 264 { 265 CY_EPHY_SPEED_10, /**< 10Mbps */ 266 CY_EPHY_SPEED_100, /**< 100Mbps */ 267 CY_EPHY_SPEED_1000, /**< 1000Mbps */ 268 CY_EPHY_SPEED_AUTO /**< All 10/100/1000 Mbps */ 269 } cy_en_ephy_speed_t; 270 271 /** \} group_ephy_enums */ 272 273 /****************************************************************************** 274 * Global Data Structure definitions 275 ******************************************************************************/ 276 277 /** 278 * \addtogroup group_ephy_data_structures 279 * \{ 280 */ 281 282 /** PHY read handle to application */ 283 typedef void (*cy_ephy_read_handle)(uint32_t phyAddr, uint32_t regAddress, uint32_t *value); 284 285 /** PHY write handle to application */ 286 typedef void (*cy_ephy_write_handle)(uint32_t phyAddr, uint32_t regAddress, uint32_t value); 287 288 /** This is the private data structure of EPHY. This has be instantiated by application */ 289 typedef struct cy_stc_ephy 290 { 291 cy_ephy_read_handle fnPhyRead; /**< read handle */ 292 cy_ephy_write_handle fnPhyWrite; /**< write handle */ 293 uint32_t phyId; /**< phy ID */ 294 cy_en_ephy_state_t state; /**< PHY state */ 295 uint32_t bmcr; /**< store the BMCR value while PHY configuration */ 296 uint32_t anar; /**< store the ANAR value while PHY configuration */ 297 } cy_stc_ephy_t; 298 299 /** EPHY configuration */ 300 typedef struct cy_stc_ephy_config 301 { 302 uint32_t speed; /**< speed */ 303 uint32_t duplex; /**< suplex mode */ 304 } cy_stc_ephy_config_t; 305 306 /** \} group_ephy_data_structures */ 307 308 309 /****************************************************************************** 310 * Global functions * 311 ******************************************************************************/ 312 313 /** 314 * \addtogroup group_ephy_functions 315 * \{ 316 */ 317 318 319 cy_en_ephy_status_t Cy_EPHY_Init(cy_stc_ephy_t *phy, cy_ephy_read_handle fnRead, cy_ephy_write_handle fnWrite); 320 321 cy_en_ephy_status_t Cy_EPHY_Discover(cy_stc_ephy_t *phy); 322 323 cy_en_ephy_status_t Cy_EPHY_Configure(cy_stc_ephy_t *phy, cy_stc_ephy_config_t *config); 324 325 uint32_t Cy_EPHY_GetLinkStatus(cy_stc_ephy_t *phy); 326 327 cy_en_ephy_status_t Cy_EPHY_Reset(cy_stc_ephy_t *phy); 328 329 uint32_t Cy_EPHY_GetAutoNegotiationStatus(cy_stc_ephy_t *phy); 330 331 cy_en_ephy_status_t Cy_EPHY_getLinkPartnerCapabilities(cy_stc_ephy_t *phy, cy_stc_ephy_config_t *lpConfig); 332 333 334 /** \} group_ephy_functions */ 335 336 337 338 #if defined(__cplusplus) 339 } 340 #endif 341 342 #endif /* CY_IP_MXETH */ 343 344 #endif /* CY_EPHY_H */ 345 346 /** \} group_ephy */ 347 348 /* [] END OF FILE */ 349
