1 /***************************************************************************//** 2 * \file cyip_peri.h 3 * 4 * \brief 5 * PERI IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_PERI_H_ 29 #define _CYIP_PERI_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * PERI 35 *******************************************************************************/ 36 37 #define PERI_GR_SECTION_SIZE 0x00000040UL 38 #define PERI_TR_GR_SECTION_SIZE 0x00000200UL 39 #define PERI_PPU_PR_SECTION_SIZE 0x00000040UL 40 #define PERI_PPU_GR_SECTION_SIZE 0x00000040UL 41 #define PERI_GR_PPU_SL_SECTION_SIZE 0x00000040UL 42 #define PERI_GR_PPU_RG_SECTION_SIZE 0x00000040UL 43 #define PERI_SECTION_SIZE 0x00010000UL 44 45 /** 46 * \brief Peripheral group structure (PERI_GR) 47 */ 48 typedef struct { 49 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ 50 __IM uint32_t RESERVED[7]; 51 __IOM uint32_t SL_CTL; /*!< 0x00000020 Slave control */ 52 __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000024 Timeout control */ 53 __IM uint32_t RESERVED1[6]; 54 } PERI_GR_V1_Type; /*!< Size = 64 (0x40) */ 55 56 /** 57 * \brief Trigger group (PERI_TR_GR) 58 */ 59 typedef struct { 60 __IOM uint32_t TR_OUT_CTL[128]; /*!< 0x00000000 Trigger control register */ 61 } PERI_TR_GR_V1_Type; /*!< Size = 512 (0x200) */ 62 63 /** 64 * \brief PPU structure with programmable address (PERI_PPU_PR) 65 */ 66 typedef struct { 67 __IOM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 68 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 69 __IM uint32_t RESERVED[6]; 70 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 71 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 72 __IM uint32_t RESERVED1[6]; 73 } PERI_PPU_PR_V1_Type; /*!< Size = 64 (0x40) */ 74 75 /** 76 * \brief PPU structure with fixed/constant address for a peripheral group (PERI_PPU_GR) 77 */ 78 typedef struct { 79 __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 80 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 81 __IM uint32_t RESERVED[6]; 82 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 83 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 84 __IM uint32_t RESERVED1[6]; 85 } PERI_PPU_GR_V1_Type; /*!< Size = 64 (0x40) */ 86 87 /** 88 * \brief PPU structure with fixed/constant address for a specific slave (PERI_GR_PPU_SL) 89 */ 90 typedef struct { 91 __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 92 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 93 __IM uint32_t RESERVED[6]; 94 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 95 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 96 __IM uint32_t RESERVED1[6]; 97 } PERI_GR_PPU_SL_V1_Type; /*!< Size = 64 (0x40) */ 98 99 /** 100 * \brief PPU structure with fixed/constant address for a specific region (PERI_GR_PPU_RG) 101 */ 102 typedef struct { 103 __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 104 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 105 __IM uint32_t RESERVED[6]; 106 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 107 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 108 __IM uint32_t RESERVED1[6]; 109 } PERI_GR_PPU_RG_V1_Type; /*!< Size = 64 (0x40) */ 110 111 /** 112 * \brief Peripheral interconnect (PERI) 113 */ 114 typedef struct { 115 PERI_GR_V1_Type GR[16]; /*!< 0x00000000 Peripheral group structure */ 116 __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command register */ 117 __IM uint32_t RESERVED[255]; 118 __IOM uint32_t DIV_8_CTL[64]; /*!< 0x00000800 Divider control register (for 8.0 divider) */ 119 __IOM uint32_t DIV_16_CTL[64]; /*!< 0x00000900 Divider control register (for 16.0 divider) */ 120 __IOM uint32_t DIV_16_5_CTL[64]; /*!< 0x00000A00 Divider control register (for 16.5 divider) */ 121 __IOM uint32_t DIV_24_5_CTL[63]; /*!< 0x00000B00 Divider control register (for 24.5 divider) */ 122 __IM uint32_t RESERVED1; 123 __IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */ 124 __IM uint32_t RESERVED2[128]; 125 __IOM uint32_t TR_CMD; /*!< 0x00001000 Trigger command register */ 126 __IM uint32_t RESERVED3[1023]; 127 PERI_TR_GR_V1_Type TR_GR[16]; /*!< 0x00002000 Trigger group */ 128 PERI_PPU_PR_V1_Type PPU_PR[32]; /*!< 0x00004000 PPU structure with programmable address */ 129 __IM uint32_t RESERVED4[512]; 130 PERI_PPU_GR_V1_Type PPU_GR[16]; /*!< 0x00005000 PPU structure with fixed/constant address for a peripheral 131 group */ 132 } PERI_V1_Type; /*!< Size = 21504 (0x5400) */ 133 134 135 /* PERI_GR.CLOCK_CTL */ 136 #define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL 137 #define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL 138 /* PERI_GR.SL_CTL */ 139 #define PERI_GR_SL_CTL_ENABLED_0_Pos 0UL 140 #define PERI_GR_SL_CTL_ENABLED_0_Msk 0x1UL 141 #define PERI_GR_SL_CTL_ENABLED_1_Pos 1UL 142 #define PERI_GR_SL_CTL_ENABLED_1_Msk 0x2UL 143 #define PERI_GR_SL_CTL_ENABLED_2_Pos 2UL 144 #define PERI_GR_SL_CTL_ENABLED_2_Msk 0x4UL 145 #define PERI_GR_SL_CTL_ENABLED_3_Pos 3UL 146 #define PERI_GR_SL_CTL_ENABLED_3_Msk 0x8UL 147 #define PERI_GR_SL_CTL_ENABLED_4_Pos 4UL 148 #define PERI_GR_SL_CTL_ENABLED_4_Msk 0x10UL 149 #define PERI_GR_SL_CTL_ENABLED_5_Pos 5UL 150 #define PERI_GR_SL_CTL_ENABLED_5_Msk 0x20UL 151 #define PERI_GR_SL_CTL_ENABLED_6_Pos 6UL 152 #define PERI_GR_SL_CTL_ENABLED_6_Msk 0x40UL 153 #define PERI_GR_SL_CTL_ENABLED_7_Pos 7UL 154 #define PERI_GR_SL_CTL_ENABLED_7_Msk 0x80UL 155 #define PERI_GR_SL_CTL_ENABLED_8_Pos 8UL 156 #define PERI_GR_SL_CTL_ENABLED_8_Msk 0x100UL 157 #define PERI_GR_SL_CTL_ENABLED_9_Pos 9UL 158 #define PERI_GR_SL_CTL_ENABLED_9_Msk 0x200UL 159 #define PERI_GR_SL_CTL_ENABLED_10_Pos 10UL 160 #define PERI_GR_SL_CTL_ENABLED_10_Msk 0x400UL 161 #define PERI_GR_SL_CTL_ENABLED_11_Pos 11UL 162 #define PERI_GR_SL_CTL_ENABLED_11_Msk 0x800UL 163 #define PERI_GR_SL_CTL_ENABLED_12_Pos 12UL 164 #define PERI_GR_SL_CTL_ENABLED_12_Msk 0x1000UL 165 #define PERI_GR_SL_CTL_ENABLED_13_Pos 13UL 166 #define PERI_GR_SL_CTL_ENABLED_13_Msk 0x2000UL 167 #define PERI_GR_SL_CTL_ENABLED_14_Pos 14UL 168 #define PERI_GR_SL_CTL_ENABLED_14_Msk 0x4000UL 169 #define PERI_GR_SL_CTL_ENABLED_15_Pos 15UL 170 #define PERI_GR_SL_CTL_ENABLED_15_Msk 0x8000UL 171 /* PERI_GR.TIMEOUT_CTL */ 172 #define PERI_GR_TIMEOUT_CTL_TIMEOUT_Pos 0UL 173 #define PERI_GR_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL 174 175 176 /* PERI_TR_GR.TR_OUT_CTL */ 177 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos 0UL 178 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk 0xFFUL 179 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos 8UL 180 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk 0x100UL 181 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos 9UL 182 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk 0x200UL 183 184 185 /* PERI_PPU_PR.ADDR0 */ 186 #define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Pos 0UL 187 #define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 188 #define PERI_PPU_PR_ADDR0_ADDR24_Pos 8UL 189 #define PERI_PPU_PR_ADDR0_ADDR24_Msk 0xFFFFFF00UL 190 /* PERI_PPU_PR.ATT0 */ 191 #define PERI_PPU_PR_ATT0_UR_Pos 0UL 192 #define PERI_PPU_PR_ATT0_UR_Msk 0x1UL 193 #define PERI_PPU_PR_ATT0_UW_Pos 1UL 194 #define PERI_PPU_PR_ATT0_UW_Msk 0x2UL 195 #define PERI_PPU_PR_ATT0_UX_Pos 2UL 196 #define PERI_PPU_PR_ATT0_UX_Msk 0x4UL 197 #define PERI_PPU_PR_ATT0_PR_Pos 3UL 198 #define PERI_PPU_PR_ATT0_PR_Msk 0x8UL 199 #define PERI_PPU_PR_ATT0_PW_Pos 4UL 200 #define PERI_PPU_PR_ATT0_PW_Msk 0x10UL 201 #define PERI_PPU_PR_ATT0_PX_Pos 5UL 202 #define PERI_PPU_PR_ATT0_PX_Msk 0x20UL 203 #define PERI_PPU_PR_ATT0_NS_Pos 6UL 204 #define PERI_PPU_PR_ATT0_NS_Msk 0x40UL 205 #define PERI_PPU_PR_ATT0_PC_MASK_0_Pos 8UL 206 #define PERI_PPU_PR_ATT0_PC_MASK_0_Msk 0x100UL 207 #define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Pos 9UL 208 #define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 209 #define PERI_PPU_PR_ATT0_REGION_SIZE_Pos 24UL 210 #define PERI_PPU_PR_ATT0_REGION_SIZE_Msk 0x1F000000UL 211 #define PERI_PPU_PR_ATT0_PC_MATCH_Pos 30UL 212 #define PERI_PPU_PR_ATT0_PC_MATCH_Msk 0x40000000UL 213 #define PERI_PPU_PR_ATT0_ENABLED_Pos 31UL 214 #define PERI_PPU_PR_ATT0_ENABLED_Msk 0x80000000UL 215 /* PERI_PPU_PR.ADDR1 */ 216 #define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Pos 0UL 217 #define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 218 #define PERI_PPU_PR_ADDR1_ADDR24_Pos 8UL 219 #define PERI_PPU_PR_ADDR1_ADDR24_Msk 0xFFFFFF00UL 220 /* PERI_PPU_PR.ATT1 */ 221 #define PERI_PPU_PR_ATT1_UR_Pos 0UL 222 #define PERI_PPU_PR_ATT1_UR_Msk 0x1UL 223 #define PERI_PPU_PR_ATT1_UW_Pos 1UL 224 #define PERI_PPU_PR_ATT1_UW_Msk 0x2UL 225 #define PERI_PPU_PR_ATT1_UX_Pos 2UL 226 #define PERI_PPU_PR_ATT1_UX_Msk 0x4UL 227 #define PERI_PPU_PR_ATT1_PR_Pos 3UL 228 #define PERI_PPU_PR_ATT1_PR_Msk 0x8UL 229 #define PERI_PPU_PR_ATT1_PW_Pos 4UL 230 #define PERI_PPU_PR_ATT1_PW_Msk 0x10UL 231 #define PERI_PPU_PR_ATT1_PX_Pos 5UL 232 #define PERI_PPU_PR_ATT1_PX_Msk 0x20UL 233 #define PERI_PPU_PR_ATT1_NS_Pos 6UL 234 #define PERI_PPU_PR_ATT1_NS_Msk 0x40UL 235 #define PERI_PPU_PR_ATT1_PC_MASK_0_Pos 8UL 236 #define PERI_PPU_PR_ATT1_PC_MASK_0_Msk 0x100UL 237 #define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Pos 9UL 238 #define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 239 #define PERI_PPU_PR_ATT1_REGION_SIZE_Pos 24UL 240 #define PERI_PPU_PR_ATT1_REGION_SIZE_Msk 0x1F000000UL 241 #define PERI_PPU_PR_ATT1_PC_MATCH_Pos 30UL 242 #define PERI_PPU_PR_ATT1_PC_MATCH_Msk 0x40000000UL 243 #define PERI_PPU_PR_ATT1_ENABLED_Pos 31UL 244 #define PERI_PPU_PR_ATT1_ENABLED_Msk 0x80000000UL 245 246 247 /* PERI_PPU_GR.ADDR0 */ 248 #define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Pos 0UL 249 #define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 250 #define PERI_PPU_GR_ADDR0_ADDR24_Pos 8UL 251 #define PERI_PPU_GR_ADDR0_ADDR24_Msk 0xFFFFFF00UL 252 /* PERI_PPU_GR.ATT0 */ 253 #define PERI_PPU_GR_ATT0_UR_Pos 0UL 254 #define PERI_PPU_GR_ATT0_UR_Msk 0x1UL 255 #define PERI_PPU_GR_ATT0_UW_Pos 1UL 256 #define PERI_PPU_GR_ATT0_UW_Msk 0x2UL 257 #define PERI_PPU_GR_ATT0_UX_Pos 2UL 258 #define PERI_PPU_GR_ATT0_UX_Msk 0x4UL 259 #define PERI_PPU_GR_ATT0_PR_Pos 3UL 260 #define PERI_PPU_GR_ATT0_PR_Msk 0x8UL 261 #define PERI_PPU_GR_ATT0_PW_Pos 4UL 262 #define PERI_PPU_GR_ATT0_PW_Msk 0x10UL 263 #define PERI_PPU_GR_ATT0_PX_Pos 5UL 264 #define PERI_PPU_GR_ATT0_PX_Msk 0x20UL 265 #define PERI_PPU_GR_ATT0_NS_Pos 6UL 266 #define PERI_PPU_GR_ATT0_NS_Msk 0x40UL 267 #define PERI_PPU_GR_ATT0_PC_MASK_0_Pos 8UL 268 #define PERI_PPU_GR_ATT0_PC_MASK_0_Msk 0x100UL 269 #define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Pos 9UL 270 #define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 271 #define PERI_PPU_GR_ATT0_REGION_SIZE_Pos 24UL 272 #define PERI_PPU_GR_ATT0_REGION_SIZE_Msk 0x1F000000UL 273 #define PERI_PPU_GR_ATT0_PC_MATCH_Pos 30UL 274 #define PERI_PPU_GR_ATT0_PC_MATCH_Msk 0x40000000UL 275 #define PERI_PPU_GR_ATT0_ENABLED_Pos 31UL 276 #define PERI_PPU_GR_ATT0_ENABLED_Msk 0x80000000UL 277 /* PERI_PPU_GR.ADDR1 */ 278 #define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Pos 0UL 279 #define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 280 #define PERI_PPU_GR_ADDR1_ADDR24_Pos 8UL 281 #define PERI_PPU_GR_ADDR1_ADDR24_Msk 0xFFFFFF00UL 282 /* PERI_PPU_GR.ATT1 */ 283 #define PERI_PPU_GR_ATT1_UR_Pos 0UL 284 #define PERI_PPU_GR_ATT1_UR_Msk 0x1UL 285 #define PERI_PPU_GR_ATT1_UW_Pos 1UL 286 #define PERI_PPU_GR_ATT1_UW_Msk 0x2UL 287 #define PERI_PPU_GR_ATT1_UX_Pos 2UL 288 #define PERI_PPU_GR_ATT1_UX_Msk 0x4UL 289 #define PERI_PPU_GR_ATT1_PR_Pos 3UL 290 #define PERI_PPU_GR_ATT1_PR_Msk 0x8UL 291 #define PERI_PPU_GR_ATT1_PW_Pos 4UL 292 #define PERI_PPU_GR_ATT1_PW_Msk 0x10UL 293 #define PERI_PPU_GR_ATT1_PX_Pos 5UL 294 #define PERI_PPU_GR_ATT1_PX_Msk 0x20UL 295 #define PERI_PPU_GR_ATT1_NS_Pos 6UL 296 #define PERI_PPU_GR_ATT1_NS_Msk 0x40UL 297 #define PERI_PPU_GR_ATT1_PC_MASK_0_Pos 8UL 298 #define PERI_PPU_GR_ATT1_PC_MASK_0_Msk 0x100UL 299 #define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Pos 9UL 300 #define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 301 #define PERI_PPU_GR_ATT1_REGION_SIZE_Pos 24UL 302 #define PERI_PPU_GR_ATT1_REGION_SIZE_Msk 0x1F000000UL 303 #define PERI_PPU_GR_ATT1_PC_MATCH_Pos 30UL 304 #define PERI_PPU_GR_ATT1_PC_MATCH_Msk 0x40000000UL 305 #define PERI_PPU_GR_ATT1_ENABLED_Pos 31UL 306 #define PERI_PPU_GR_ATT1_ENABLED_Msk 0x80000000UL 307 308 309 /* PERI_GR_PPU_SL.ADDR0 */ 310 #define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Pos 0UL 311 #define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 312 #define PERI_GR_PPU_SL_ADDR0_ADDR24_Pos 8UL 313 #define PERI_GR_PPU_SL_ADDR0_ADDR24_Msk 0xFFFFFF00UL 314 /* PERI_GR_PPU_SL.ATT0 */ 315 #define PERI_GR_PPU_SL_ATT0_UR_Pos 0UL 316 #define PERI_GR_PPU_SL_ATT0_UR_Msk 0x1UL 317 #define PERI_GR_PPU_SL_ATT0_UW_Pos 1UL 318 #define PERI_GR_PPU_SL_ATT0_UW_Msk 0x2UL 319 #define PERI_GR_PPU_SL_ATT0_UX_Pos 2UL 320 #define PERI_GR_PPU_SL_ATT0_UX_Msk 0x4UL 321 #define PERI_GR_PPU_SL_ATT0_PR_Pos 3UL 322 #define PERI_GR_PPU_SL_ATT0_PR_Msk 0x8UL 323 #define PERI_GR_PPU_SL_ATT0_PW_Pos 4UL 324 #define PERI_GR_PPU_SL_ATT0_PW_Msk 0x10UL 325 #define PERI_GR_PPU_SL_ATT0_PX_Pos 5UL 326 #define PERI_GR_PPU_SL_ATT0_PX_Msk 0x20UL 327 #define PERI_GR_PPU_SL_ATT0_NS_Pos 6UL 328 #define PERI_GR_PPU_SL_ATT0_NS_Msk 0x40UL 329 #define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Pos 8UL 330 #define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk 0x100UL 331 #define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Pos 9UL 332 #define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 333 #define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Pos 24UL 334 #define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk 0x1F000000UL 335 #define PERI_GR_PPU_SL_ATT0_PC_MATCH_Pos 30UL 336 #define PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk 0x40000000UL 337 #define PERI_GR_PPU_SL_ATT0_ENABLED_Pos 31UL 338 #define PERI_GR_PPU_SL_ATT0_ENABLED_Msk 0x80000000UL 339 /* PERI_GR_PPU_SL.ADDR1 */ 340 #define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Pos 0UL 341 #define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 342 #define PERI_GR_PPU_SL_ADDR1_ADDR24_Pos 8UL 343 #define PERI_GR_PPU_SL_ADDR1_ADDR24_Msk 0xFFFFFF00UL 344 /* PERI_GR_PPU_SL.ATT1 */ 345 #define PERI_GR_PPU_SL_ATT1_UR_Pos 0UL 346 #define PERI_GR_PPU_SL_ATT1_UR_Msk 0x1UL 347 #define PERI_GR_PPU_SL_ATT1_UW_Pos 1UL 348 #define PERI_GR_PPU_SL_ATT1_UW_Msk 0x2UL 349 #define PERI_GR_PPU_SL_ATT1_UX_Pos 2UL 350 #define PERI_GR_PPU_SL_ATT1_UX_Msk 0x4UL 351 #define PERI_GR_PPU_SL_ATT1_PR_Pos 3UL 352 #define PERI_GR_PPU_SL_ATT1_PR_Msk 0x8UL 353 #define PERI_GR_PPU_SL_ATT1_PW_Pos 4UL 354 #define PERI_GR_PPU_SL_ATT1_PW_Msk 0x10UL 355 #define PERI_GR_PPU_SL_ATT1_PX_Pos 5UL 356 #define PERI_GR_PPU_SL_ATT1_PX_Msk 0x20UL 357 #define PERI_GR_PPU_SL_ATT1_NS_Pos 6UL 358 #define PERI_GR_PPU_SL_ATT1_NS_Msk 0x40UL 359 #define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Pos 8UL 360 #define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk 0x100UL 361 #define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Pos 9UL 362 #define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 363 #define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Pos 24UL 364 #define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk 0x1F000000UL 365 #define PERI_GR_PPU_SL_ATT1_PC_MATCH_Pos 30UL 366 #define PERI_GR_PPU_SL_ATT1_PC_MATCH_Msk 0x40000000UL 367 #define PERI_GR_PPU_SL_ATT1_ENABLED_Pos 31UL 368 #define PERI_GR_PPU_SL_ATT1_ENABLED_Msk 0x80000000UL 369 370 371 /* PERI_GR_PPU_RG.ADDR0 */ 372 #define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Pos 0UL 373 #define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 374 #define PERI_GR_PPU_RG_ADDR0_ADDR24_Pos 8UL 375 #define PERI_GR_PPU_RG_ADDR0_ADDR24_Msk 0xFFFFFF00UL 376 /* PERI_GR_PPU_RG.ATT0 */ 377 #define PERI_GR_PPU_RG_ATT0_UR_Pos 0UL 378 #define PERI_GR_PPU_RG_ATT0_UR_Msk 0x1UL 379 #define PERI_GR_PPU_RG_ATT0_UW_Pos 1UL 380 #define PERI_GR_PPU_RG_ATT0_UW_Msk 0x2UL 381 #define PERI_GR_PPU_RG_ATT0_UX_Pos 2UL 382 #define PERI_GR_PPU_RG_ATT0_UX_Msk 0x4UL 383 #define PERI_GR_PPU_RG_ATT0_PR_Pos 3UL 384 #define PERI_GR_PPU_RG_ATT0_PR_Msk 0x8UL 385 #define PERI_GR_PPU_RG_ATT0_PW_Pos 4UL 386 #define PERI_GR_PPU_RG_ATT0_PW_Msk 0x10UL 387 #define PERI_GR_PPU_RG_ATT0_PX_Pos 5UL 388 #define PERI_GR_PPU_RG_ATT0_PX_Msk 0x20UL 389 #define PERI_GR_PPU_RG_ATT0_NS_Pos 6UL 390 #define PERI_GR_PPU_RG_ATT0_NS_Msk 0x40UL 391 #define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Pos 8UL 392 #define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk 0x100UL 393 #define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Pos 9UL 394 #define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 395 #define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Pos 24UL 396 #define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk 0x1F000000UL 397 #define PERI_GR_PPU_RG_ATT0_PC_MATCH_Pos 30UL 398 #define PERI_GR_PPU_RG_ATT0_PC_MATCH_Msk 0x40000000UL 399 #define PERI_GR_PPU_RG_ATT0_ENABLED_Pos 31UL 400 #define PERI_GR_PPU_RG_ATT0_ENABLED_Msk 0x80000000UL 401 /* PERI_GR_PPU_RG.ADDR1 */ 402 #define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Pos 0UL 403 #define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 404 #define PERI_GR_PPU_RG_ADDR1_ADDR24_Pos 8UL 405 #define PERI_GR_PPU_RG_ADDR1_ADDR24_Msk 0xFFFFFF00UL 406 /* PERI_GR_PPU_RG.ATT1 */ 407 #define PERI_GR_PPU_RG_ATT1_UR_Pos 0UL 408 #define PERI_GR_PPU_RG_ATT1_UR_Msk 0x1UL 409 #define PERI_GR_PPU_RG_ATT1_UW_Pos 1UL 410 #define PERI_GR_PPU_RG_ATT1_UW_Msk 0x2UL 411 #define PERI_GR_PPU_RG_ATT1_UX_Pos 2UL 412 #define PERI_GR_PPU_RG_ATT1_UX_Msk 0x4UL 413 #define PERI_GR_PPU_RG_ATT1_PR_Pos 3UL 414 #define PERI_GR_PPU_RG_ATT1_PR_Msk 0x8UL 415 #define PERI_GR_PPU_RG_ATT1_PW_Pos 4UL 416 #define PERI_GR_PPU_RG_ATT1_PW_Msk 0x10UL 417 #define PERI_GR_PPU_RG_ATT1_PX_Pos 5UL 418 #define PERI_GR_PPU_RG_ATT1_PX_Msk 0x20UL 419 #define PERI_GR_PPU_RG_ATT1_NS_Pos 6UL 420 #define PERI_GR_PPU_RG_ATT1_NS_Msk 0x40UL 421 #define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Pos 8UL 422 #define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk 0x100UL 423 #define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Pos 9UL 424 #define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 425 #define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Pos 24UL 426 #define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk 0x1F000000UL 427 #define PERI_GR_PPU_RG_ATT1_PC_MATCH_Pos 30UL 428 #define PERI_GR_PPU_RG_ATT1_PC_MATCH_Msk 0x40000000UL 429 #define PERI_GR_PPU_RG_ATT1_ENABLED_Pos 31UL 430 #define PERI_GR_PPU_RG_ATT1_ENABLED_Msk 0x80000000UL 431 432 433 /* PERI.DIV_CMD */ 434 #define PERI_DIV_CMD_DIV_SEL_Pos 0UL 435 #define PERI_DIV_CMD_DIV_SEL_Msk 0x3FUL 436 #define PERI_DIV_CMD_TYPE_SEL_Pos 6UL 437 #define PERI_DIV_CMD_TYPE_SEL_Msk 0xC0UL 438 #define PERI_DIV_CMD_PA_DIV_SEL_Pos 8UL 439 #define PERI_DIV_CMD_PA_DIV_SEL_Msk 0x3F00UL 440 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos 14UL 441 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk 0xC000UL 442 #define PERI_DIV_CMD_DISABLE_Pos 30UL 443 #define PERI_DIV_CMD_DISABLE_Msk 0x40000000UL 444 #define PERI_DIV_CMD_ENABLE_Pos 31UL 445 #define PERI_DIV_CMD_ENABLE_Msk 0x80000000UL 446 /* PERI.DIV_8_CTL */ 447 #define PERI_DIV_8_CTL_EN_Pos 0UL 448 #define PERI_DIV_8_CTL_EN_Msk 0x1UL 449 #define PERI_DIV_8_CTL_INT8_DIV_Pos 8UL 450 #define PERI_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL 451 /* PERI.DIV_16_CTL */ 452 #define PERI_DIV_16_CTL_EN_Pos 0UL 453 #define PERI_DIV_16_CTL_EN_Msk 0x1UL 454 #define PERI_DIV_16_CTL_INT16_DIV_Pos 8UL 455 #define PERI_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL 456 /* PERI.DIV_16_5_CTL */ 457 #define PERI_DIV_16_5_CTL_EN_Pos 0UL 458 #define PERI_DIV_16_5_CTL_EN_Msk 0x1UL 459 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL 460 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL 461 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos 8UL 462 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL 463 /* PERI.DIV_24_5_CTL */ 464 #define PERI_DIV_24_5_CTL_EN_Pos 0UL 465 #define PERI_DIV_24_5_CTL_EN_Msk 0x1UL 466 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL 467 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL 468 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos 8UL 469 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL 470 /* PERI.CLOCK_CTL */ 471 #define PERI_CLOCK_CTL_DIV_SEL_Pos 0UL 472 #define PERI_CLOCK_CTL_DIV_SEL_Msk 0x3FUL 473 #define PERI_CLOCK_CTL_TYPE_SEL_Pos 6UL 474 #define PERI_CLOCK_CTL_TYPE_SEL_Msk 0xC0UL 475 /* PERI.TR_CMD */ 476 #define PERI_TR_CMD_TR_SEL_Pos 0UL 477 #define PERI_TR_CMD_TR_SEL_Msk 0xFFUL 478 #define PERI_TR_CMD_GROUP_SEL_Pos 8UL 479 #define PERI_TR_CMD_GROUP_SEL_Msk 0xF00UL 480 #define PERI_TR_CMD_COUNT_Pos 16UL 481 #define PERI_TR_CMD_COUNT_Msk 0xFF0000UL 482 #define PERI_TR_CMD_OUT_SEL_Pos 30UL 483 #define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL 484 #define PERI_TR_CMD_ACTIVATE_Pos 31UL 485 #define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL 486 487 488 #endif /* _CYIP_PERI_H_ */ 489 490 491 /* [] END OF FILE */ 492
