1 /*
2  * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #pragma once
8 
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 typedef enum {
14     PERIPH_LEDC_MODULE = 0,
15     PERIPH_UART0_MODULE,
16     PERIPH_UART1_MODULE,
17     PERIPH_USB_DEVICE_MODULE,
18     PERIPH_I2C0_MODULE,
19     PERIPH_I2S1_MODULE,
20     PERIPH_TIMG0_MODULE,
21     PERIPH_TIMG1_MODULE,
22     PERIPH_UHCI0_MODULE,
23     PERIPH_RMT_MODULE,
24     PERIPH_PCNT_MODULE,
25     PERIPH_SPI_MODULE,  //SPI1
26     PERIPH_SPI2_MODULE, //SPI2
27     PERIPH_TWAI0_MODULE,
28     PERIPH_TWAI1_MODULE,
29     PERIPH_RNG_MODULE,
30     PERIPH_RSA_MODULE,
31     PERIPH_AES_MODULE,
32     PERIPH_SHA_MODULE,
33     PERIPH_ECC_MODULE,
34     PERIPH_HMAC_MODULE,
35     PERIPH_DS_MODULE,
36     PERIPH_SDIO_SLAVE_MODULE,
37     PERIPH_GDMA_MODULE,
38     PERIPH_MCPWM0_MODULE,
39     PERIPH_ETM_MODULE,
40     PERIPH_PARLIO_MODULE,
41     PERIPH_SYSTIMER_MODULE,
42     PERIPH_SARADC_MODULE,
43     PERIPH_TEMPSENSOR_MODULE,
44     PERIPH_REGDMA_MODULE,
45     PERIPH_LP_I2C0_MODULE,
46 /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
47     PERIPH_WIFI_MODULE,
48     PERIPH_BT_MODULE,
49     PERIPH_IEEE802154_MODULE,
50     PERIPH_COEX_MODULE,
51     PERIPH_PHY_MODULE,
52     PERIPH_ANA_I2C_MASTER_MODULE,
53     PERIPH_MODEM_ETM_MODULE,
54     PERIPH_MODEM_ADC_COMMON_FE_MODULE,
55     PERIPH_MODULE_MAX
56 /*  !!! Don't append soc modules here !!! */
57 } periph_module_t;
58 
59 #define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
60 #define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
61 #define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
62 #define IS_MODEM_MODULE(periph)  ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
63 
64 typedef enum {
65     ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
66     ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
67     ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
68     ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibartion*/
69     ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
70     ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
71     ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
72     ETS_LP_TIMER_INTR_SOURCE,
73     ETS_COEX_INTR_SOURCE,
74     ETS_BLE_TIMER_INTR_SOURCE,
75     ETS_BLE_SEC_INTR_SOURCE,
76     ETS_I2C_MASTER_SOURCE,                      /**< interrupt of I2C Master, level*/
77     ETS_ZB_MAC_SOURCE,
78     ETS_PMU_INTR_SOURCE,
79     ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
80     ETS_LP_RTC_TIMER_INTR_SOURCE,
81     ETS_LP_UART_INTR_SOURCE,
82     ETS_LP_I2C_INTR_SOURCE,
83     ETS_LP_WDT_INTR_SOURCE,
84     ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
85     ETS_LP_APM_M0_INTR_SOURCE,
86     ETS_LP_APM_M1_INTR_SOURCE,
87     ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
88     ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
89     ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/
90     ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/
91     ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
92     ETS_TRACE_INTR_SOURCE,
93     ETS_CACHE_INTR_SOURCE,
94     ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
95     ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
96     ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
97     ETS_PAU_INTR_SOURCE,
98     ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
99     ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
100     ETS_HP_APM_M0_INTR_SOURCE,
101     ETS_HP_APM_M1_INTR_SOURCE,
102     ETS_HP_APM_M2_INTR_SOURCE,
103     ETS_HP_APM_M3_INTR_SOURCE,
104     ETS_LP_APM0_INTR_SOURCE,
105     ETS_MSPI_INTR_SOURCE,
106     ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
107     ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
108     ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
109     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
110     ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
111     ETS_TWAI0_INTR_SOURCE,                      /**< interrupt of can0, level*/
112     ETS_TWAI1_INTR_SOURCE,                      /**< interrupt of can1, level*/
113     ETS_USB_SERIAL_JTAG_INTR_SOURCE,            /**< interrupt of USB, level*/
114     ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/
115     ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
116     ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level*/
117     ETS_TG0_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER1, level*/
118     ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
119     ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
120     ETS_TG1_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER1, level*/
121     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
122     ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
123     ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
124     ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
125     ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
126     ETS_MCPWM0_INTR_SOURCE,                     /**< interrupt of MCPWM0, LEVEL*/
127     ETS_PCNT_INTR_SOURCE,
128     ETS_PARL_IO_INTR_SOURCE,
129     ETS_SLC0_INTR_SOURCE,
130     ETS_SLC_INTR_SOURCE,
131     ETS_DMA_IN_CH0_INTR_SOURCE,                    /**< interrupt of general DMA IN channel 0, LEVEL*/
132     ETS_DMA_IN_CH1_INTR_SOURCE,                    /**< interrupt of general DMA IN channel 1, LEVEL*/
133     ETS_DMA_IN_CH2_INTR_SOURCE,                    /**< interrupt of general DMA IN channel 2, LEVEL*/
134     ETS_DMA_OUT_CH0_INTR_SOURCE,                   /**< interrupt of general DMA OUT channel 0, LEVEL*/
135     ETS_DMA_OUT_CH1_INTR_SOURCE,                   /**< interrupt of general DMA OUT channel 1, LEVEL*/
136     ETS_DMA_OUT_CH2_INTR_SOURCE,                   /**< interrupt of general DMA OUT channel 2, LEVEL*/
137     ETS_GSPI2_INTR_SOURCE,
138     ETS_AES_INTR_SOURCE,                        /**< interrupt of AES accelerator, level*/
139     ETS_SHA_INTR_SOURCE,                        /**< interrupt of SHA accelerator, level*/
140     ETS_RSA_INTR_SOURCE,                        /**< interrupt of RSA accelerator, level*/
141     ETS_ECC_INTR_SOURCE,                        /**< interrupt of ECC accelerator, level*/
142     ETS_MAX_INTR_SOURCE,
143 } periph_interrput_t;
144 
145 #ifdef __cplusplus
146 }
147 #endif
148