1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 typedef enum { 14 PERIPH_LEDC_MODULE = 0, 15 PERIPH_UART0_MODULE, 16 PERIPH_UART1_MODULE, 17 PERIPH_UART2_MODULE, 18 PERIPH_USB_MODULE, 19 PERIPH_I2C0_MODULE, 20 PERIPH_I2C1_MODULE, 21 PERIPH_I2S0_MODULE, 22 PERIPH_I2S1_MODULE, 23 PERIPH_LCD_CAM_MODULE, 24 PERIPH_TIMG0_MODULE, 25 PERIPH_TIMG1_MODULE, 26 PERIPH_PWM0_MODULE, 27 PERIPH_PWM1_MODULE, 28 PERIPH_PWM2_MODULE, 29 PERIPH_PWM3_MODULE, 30 PERIPH_UHCI0_MODULE, 31 PERIPH_UHCI1_MODULE, 32 PERIPH_RMT_MODULE, 33 PERIPH_PCNT_MODULE, 34 PERIPH_SPI_MODULE, 35 PERIPH_SPI2_MODULE, 36 PERIPH_SPI3_MODULE, 37 PERIPH_SDMMC_MODULE, 38 PERIPH_TWAI_MODULE, 39 PERIPH_RNG_MODULE, 40 PERIPH_WIFI_MODULE, 41 PERIPH_BT_MODULE, 42 PERIPH_WIFI_BT_COMMON_MODULE, 43 PERIPH_BT_BASEBAND_MODULE, 44 PERIPH_BT_LC_MODULE, 45 PERIPH_AES_MODULE, 46 PERIPH_SHA_MODULE, 47 PERIPH_HMAC_MODULE, 48 PERIPH_DS_MODULE, 49 PERIPH_RSA_MODULE, 50 PERIPH_SYSTIMER_MODULE, 51 PERIPH_GDMA_MODULE, 52 PERIPH_DEDIC_GPIO_MODULE, 53 PERIPH_SARADC_MODULE, 54 PERIPH_TEMPSENSOR_MODULE, 55 PERIPH_MODULE_MAX 56 } periph_module_t; 57 58 typedef enum { 59 ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ 60 ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ 61 ETS_WIFI_PWR_INTR_SOURCE, /**< */ 62 ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ 63 ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ 64 ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ 65 ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ 66 ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ 67 ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ 68 ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ 69 ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ 70 ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ 71 ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ 72 ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ 73 ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ 74 ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ 75 76 ETS_GPIO_INTR_SOURCE = 16, /**< interrupt of GPIO, level*/ 77 ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ 78 ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ 79 ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ 80 ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ 81 ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ 82 ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ 83 ETS_LCD_CAM_INTR_SOURCE = 24, /**< interrupt of LCD camera, level*/ 84 ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ 85 ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ 86 ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ 87 ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ 88 ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ 89 ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ 90 ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ 91 ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ 92 ETS_LEDC_INTR_SOURCE = 35, /**< interrupt of LED PWM, level*/ 93 ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ 94 ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ 95 ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/ 96 ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ 97 ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ 98 ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ 99 ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ 100 ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ 101 ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ 102 ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ 103 ETS_WDT_INTR_SOURCE = 47, /**< will be cancelled*/ 104 105 ETS_TIMER1_INTR_SOURCE = 48, 106 ETS_TIMER2_INTR_SOURCE, 107 ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ 108 ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ 109 ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ 110 ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ 111 ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ 112 ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ 113 ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ 114 ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ 115 ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ 116 ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ 117 ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ 118 ETS_DCACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ 119 ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ 120 ETS_DCACHE_SYNC0_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ 121 ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ 122 ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ 123 ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA RX channel 0, LEVEL*/ 124 ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA RX channel 1, LEVEL*/ 125 ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA RX channel 2, LEVEL*/ 126 ETS_DMA_IN_CH3_INTR_SOURCE, /**< interrupt of general DMA RX channel 3, LEVEL*/ 127 ETS_DMA_IN_CH4_INTR_SOURCE, /**< interrupt of general DMA RX channel 4, LEVEL*/ 128 ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA TX channel 0, LEVEL*/ 129 ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA TX channel 1, LEVEL*/ 130 ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA TX channel 2, LEVEL*/ 131 ETS_DMA_OUT_CH3_INTR_SOURCE, /**< interrupt of general DMA TX channel 3, LEVEL*/ 132 ETS_DMA_OUT_CH4_INTR_SOURCE, /**< interrupt of general DMA TX channel 4, LEVEL*/ 133 ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ 134 ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ 135 ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ 136 ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ 137 ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ 138 ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */ 139 ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */ 140 ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ 141 ETS_DMA_APBPERI_PMS_INTR_SOURCE, 142 ETS_CORE0_IRAM0_PMS_INTR_SOURCE, 143 ETS_CORE0_DRAM0_PMS_INTR_SOURCE, 144 ETS_CORE0_PIF_PMS_INTR_SOURCE, 145 ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, 146 ETS_CORE1_IRAM0_PMS_INTR_SOURCE, 147 ETS_CORE1_DRAM0_PMS_INTR_SOURCE, 148 ETS_CORE1_PIF_PMS_INTR_SOURCE, 149 ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE, 150 ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE, 151 ETS_CACHE_CORE0_ACS_INTR_SOURCE, 152 ETS_CACHE_CORE1_ACS_INTR_SOURCE, 153 ETS_USB_SERIAL_JTAG_INTR_SOURCE, 154 ETS_PREI_BACKUP_INTR_SOURCE, 155 ETS_DMA_EXTMEM_REJECT_SOURCE, 156 ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ 157 } periph_interrput_t; 158 159 #ifdef __cplusplus 160 } 161 #endif 162
