1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #include "soc/soc.h" 17 #include "soc/sensitive_reg.h" 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 //IRAM0 interrupt status bitmasks 24 #define IRAM0_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1 25 #define IRAM0_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1 26 27 #define CONF_REG_ADDRESS_SHIFT 2 28 29 //IRAM0 range 30 #define IRAM0_SRAM_BASE_ADDRESS 0x40000000 31 #define IRAM0_SRAM_ADDRESS_LOW 0x40020000 32 #define IRAM0_SRAM_ADDRESS_HIGH 0x4006FFFF 33 34 //IRAM0 unified managemnt blocks 35 #define IRAM0_SRAM_TOTAL_UNI_BLOCKS 4 36 #define IRAM0_SRAM_UNI_BLOCK_0 0 37 #define IRAM0_SRAM_UNI_BLOCK_1 1 38 #define IRAM0_SRAM_UNI_BLOCK_2 2 39 #define IRAM0_SRAM_UNI_BLOCK_3 3 40 41 //unified management addr range (blocks 0-3) 42 #define IRAM0_SRAM_UNI_BLOCK_0_LOW 0x40020000 43 #define IRAM0_SRAM_UNI_BLOCK_1_LOW 0x40022000 44 #define IRAM0_SRAM_UNI_BLOCK_2_LOW 0x40024000 45 #define IRAM0_SRAM_UNI_BLOCK_3_LOW 0x40026000 46 47 //split management addr range (blocks 4-21) 48 #define IRAM0_SRAM_SPL_BLOCK_LOW 0x40028000 //block 4 low 49 #define IRAM0_SRAM_SPL_BLOCK_HIGH 0x4006FFFF //block 21 high 50 51 #define IRAM0_INTR_ST_FAULTADDR_M 0x003FFFFC //bits 21:6 in the reg, as well as in real address 52 #define IRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x40000000 //high nonsignificant bits 31:22 of the faulting address - constant 53 54 #define IRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S) 55 56 //IRAM0 RTCFAST 57 #define IRAM0_RTCFAST_ADDRESS_LOW 0x40070000 58 #define IRAM0_RTCFAST_ADDRESS_HIGH 0x40071FFF 59 #define IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x40070000 //RTCFAST faulting address high bits (31:22, constant) 60 61 #define IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S) 62 63 //DRAM0 interrupt status bitmasks 64 #define DRAM0_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg) 65 #define DRAM0_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address) 66 #define DRAM0_INTR_ST_OP_RW_BIT BIT(4) //read: 0, write: 1 67 #define DRAM0_INTR_ST_OP_ATOMIC_BIT BIT(5) //non-atomic: 0, atomic: 1 68 69 #define DRAM0_SRAM_ADDRESS_LOW 0x3FFB0000 70 #define DRAM0_SRAM_ADDRESS_HIGH 0x3FFFFFFF 71 72 #define DRAM0_SRAM_TOTAL_UNI_BLOCKS 4 73 #define DRAM0_SRAM_UNI_BLOCK_0 0 74 #define DRAM0_SRAM_UNI_BLOCK_1 1 75 #define DRAM0_SRAM_UNI_BLOCK_2 2 76 #define DRAM0_SRAM_UNI_BLOCK_3 3 77 78 //unified management (SRAM blocks 0-3) 79 #define DRAM0_SRAM_UNI_BLOCK_0_LOW 0x3FFB0000 80 #define DRAM0_SRAM_UNI_BLOCK_1_LOW 0x3FFB2000 81 #define DRAM0_SRAM_UNI_BLOCK_2_LOW 0x3FFB4000 82 #define DRAM0_SRAM_UNI_BLOCK_3_LOW 0x3FFB6000 83 84 //split management (SRAM blocks 4-21) 85 #define DRAM0_SRAM_SPL_BLOCK_HIGH 0x3FFFFFFF //block 21 high 86 #define DRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x3FF00000 //SRAM high bits 31:22 of the faulting address - constant 87 88 #define DRAM0_SRAM_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR) << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S) 89 90 //DRAM0 RTCFAST 91 #define DRAM0_RTCFAST_ADDRESS_LOW 0x3FF9E000 92 #define DRAM0_RTCFAST_ADDRESS_HIGH 0x3FF9FFFF 93 #define DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x3FF00000 //RTCFAST high bits 31:22 of the faulting address - constant 94 #define DRAM0_RTCFAST_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR) << DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S) 95 96 //RTCSLOW 97 #define RTCSLOW_MEMORY_SIZE 0x00002000 98 99 //PeriBus1 interrupt status bitmasks 100 #define PERI1_INTR_ST_OP_TYPE_BIT BIT(4) //0: non-atomic, 1: atomic 101 #define PERI1_INTR_ST_OP_HIGH_BITS BIT(5) //0: high bits = unchanged, 1: high bits = 0x03F40000 102 #define PERI1_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg) 103 #define PERI1_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address) 104 105 #define PERI1_RTCSLOW_ADDRESS_BASE 0x3F421000 106 #define PERI1_RTCSLOW_ADDRESS_LOW PERI1_RTCSLOW_ADDRESS_BASE 107 #define PERI1_RTCSLOW_ADDRESS_HIGH PERI1_RTCSLOW_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE 108 #define PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 0x3F400000 109 110 #define PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR) << DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S) 111 112 //PeriBus2 interrupt status bitmasks 113 #define PERI2_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1 114 #define PERI2_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1 115 #define PERI2_INTR_ST_FAULTADDR_M 0xFFFFFFFC //(bits 31:2 in the reg) 116 117 #define PERI2_RTCSLOW_0_ADDRESS_BASE 0x50000000 118 #define PERI2_RTCSLOW_0_ADDRESS_LOW PERI2_RTCSLOW_0_ADDRESS_BASE 119 #define PERI2_RTCSLOW_0_ADDRESS_HIGH PERI2_RTCSLOW_0_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE 120 121 #define PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S) 122 123 #define PERI2_RTCSLOW_1_ADDRESS_BASE 0x60021000 124 #define PERI2_RTCSLOW_1_ADDRESS_LOW PERI2_RTCSLOW_1_ADDRESS_BASE 125 #define PERI2_RTCSLOW_1_ADDRESS_HIGH PERI2_RTCSLOW_1_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE 126 127 #define PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr) (((addr >> CONF_REG_ADDRESS_SHIFT) & DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR) << DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S) 128 129 #ifdef __cplusplus 130 } 131 #endif 132
