1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _NUVOTON_NPCX_REG_DEF_H
8 #define _NUVOTON_NPCX_REG_DEF_H
9
10 #include <stdint.h>
11
12 #include <zephyr/devicetree.h>
13 #include <zephyr/sys/__assert.h>
14 #include <zephyr/sys/util_macro.h>
15 #include <zephyr/toolchain.h>
16
17 /*
18 * NPCX register structure size/offset checking macro function to mitigate
19 * the risk of unexpected compiling results. All addresses of NPCX registers
20 * must meet the alignment requirement of cortex-m4.
21 * DO NOT use 'packed' attribute if module contains different length ie.
22 * 8/16/32 bits registers.
23 */
24 #define NPCX_REG_SIZE_CHECK(reg_def, size) \
25 BUILD_ASSERT(sizeof(struct reg_def) == size, \
26 "Failed in size check of register structure!")
27 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
28 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
29 "Failed in offset check of register structure member!")
30
31 /*
32 * NPCX register access checking via structure macro function to mitigate the
33 * risk of unexpected compiling results if module contains different length
34 * registers. For example, a word register access might break into two byte
35 * register accesses by adding 'packed' attribute.
36 *
37 * For example, add this macro for word register 'PRSC' of PWM module in its
38 * device init function for checking violation. Once it occurred, core will be
39 * stalled forever and easy to find out what happens.
40 */
41 #define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
42 uint16_t placeholder = reg; \
43 reg = val; \
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
45 reg = placeholder; \
46 }
47 #define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
48 uint32_t placeholder = reg; \
49 reg = val; \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
51 reg = placeholder; \
52 }
53 /*
54 * Core Domain Clock Generator (CDCG) device registers
55 */
56 struct cdcg_reg {
57 /* High Frequency Clock Generator (HFCG) registers */
58 /* 0x000: HFCG Control */
59 volatile uint8_t HFCGCTRL;
60 volatile uint8_t reserved1;
61 /* 0x002: HFCG M Low Byte Value */
62 volatile uint8_t HFCGML;
63 volatile uint8_t reserved2;
64 /* 0x004: HFCG M High Byte Value */
65 volatile uint8_t HFCGMH;
66 volatile uint8_t reserved3;
67 /* 0x006: HFCG N Value */
68 volatile uint8_t HFCGN;
69 volatile uint8_t reserved4;
70 /* 0x008: HFCG Prescaler */
71 volatile uint8_t HFCGP;
72 volatile uint8_t reserved5[7];
73 /* 0x010: HFCG Bus Clock Dividers */
74 volatile uint8_t HFCBCD;
75 volatile uint8_t reserved6;
76 /* 0x012: HFCG Bus Clock Dividers */
77 volatile uint8_t HFCBCD1;
78 volatile uint8_t reserved7;
79 /* 0x014: HFCG Bus Clock Dividers */
80 volatile uint8_t HFCBCD2;
81 volatile uint8_t reserved12[8];
82 /* 0x01d: HFCG Bus Clock Dividers */
83 volatile uint8_t HFCBCD3;
84 volatile uint8_t reserved8[226];
85
86 /* Low Frequency Clock Generator (LFCG) registers */
87 /* 0x100: LFCG Control */
88 volatile uint8_t LFCGCTL;
89 volatile uint8_t reserved9;
90 /* 0x102: High-Frequency Reference Divisor I */
91 volatile uint16_t HFRDI;
92 /* 0x104: High-Frequency Reference Divisor F */
93 volatile uint16_t HFRDF;
94 /* 0x106: FRCLK Clock Divisor */
95 volatile uint16_t FRCDIV;
96 /* 0x108: Divisor Correction Value 1 */
97 volatile uint16_t DIVCOR1;
98 /* 0x10A: Divisor Correction Value 2 */
99 volatile uint16_t DIVCOR2;
100 volatile uint8_t reserved10[8];
101 /* 0x114: LFCG Control 2 */
102 volatile uint8_t LFCGCTL2;
103 volatile uint8_t reserved11;
104 };
105
106 /* CDCG register fields */
107 #define NPCX_HFCGCTRL_LOAD 0
108 #define NPCX_HFCGCTRL_LOCK 2
109 #define NPCX_HFCGCTRL_CLK_CHNG 7
110
111 #define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
112
113 /*
114 * Power Management Controller (PMC) device registers
115 */
116 struct pmc_reg {
117 /* 0x000: Power Management Controller */
118 volatile uint8_t PMCSR;
119 volatile uint8_t reserved1[2];
120 /* 0x003: Enable in Sleep Control */
121 volatile uint8_t ENIDL_CTL;
122 /* 0x004: Disable in Idle Control */
123 volatile uint8_t DISIDL_CTL;
124 /* 0x005: Disable in Idle Control 1 */
125 volatile uint8_t DISIDL_CTL1;
126 volatile uint8_t reserved2[2];
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
128 volatile uint8_t PWDWN_CTL1[6];
129 volatile uint8_t reserved3[18];
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
131 volatile uint8_t RAM_PD[2];
132 volatile uint8_t reserved4[2];
133 /* 0x024: Power-Down Control 7 */
134 volatile uint8_t PWDWN_CTL7[1];
135 };
136
137 /* PMC internal inline functions for multi-registers */
npcx_pwdwn_ctl_offset(uint32_t ctl_no)138 static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
139 {
140 if (ctl_no < 6) {
141 return 0x008 + ctl_no;
142 } else {
143 return 0x024 + ctl_no - 6;
144 }
145 }
146
147 /* Macro functions for PMC multi-registers */
148 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
149 npcx_pwdwn_ctl_offset(n)))
150
151 /* PMC register fields */
152 #define NPCX_PMCSR_DI_INSTW 0
153 #define NPCX_PMCSR_DHF 1
154 #define NPCX_PMCSR_IDLE 2
155 #define NPCX_PMCSR_NWBI 3
156 #define NPCX_PMCSR_OHFC 6
157 #define NPCX_PMCSR_OLFC 7
158 #define NPCX_DISIDL_CTL_RAM_DID 5
159 #define NPCX_ENIDL_CTL_ADC_LFSL 7
160 #define NPCX_ENIDL_CTL_LP_WK_CTL 6
161 #define NPCX_ENIDL_CTL_PECI_ENI 2
162 #define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
163
164 /* Macro functions for Development and Debugger Interface (DDI) registers */
165 #define NPCX_DBGCTRL(base) (*(volatile uint8_t *)(base + 0x004))
166 #define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006))
167 #define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007))
168 #define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008))
169 #define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009))
170
171 /* DDI register fields */
172 #define NPCX_DBGCTRL_CCDEV_SEL FIELD(6, 2)
173 #define NPCX_DBGCTRL_CCDEV_DIR 5
174 #define NPCX_DBGCTRL_SEQ_WK_EN 4
175 #define NPCX_DBGCTRL_FRCLK_SEL_DIS 3
176 #define NPCX_DBGFRZEN1_SPIFEN 7
177 #define NPCX_DBGFRZEN1_HIFEN 6
178 #define NPCX_DBGFRZEN1_ESPISEN 5
179 #define NPCX_DBGFRZEN1_UART1FEN 4
180 #define NPCX_DBGFRZEN1_SMB3FEN 3
181 #define NPCX_DBGFRZEN1_SMB2FEN 2
182 #define NPCX_DBGFRZEN1_MFT2FEN 1
183 #define NPCX_DBGFRZEN1_MFT1FEN 0
184 #define NPCX_DBGFRZEN2_ITIM6FEN 7
185 #define NPCX_DBGFRZEN2_ITIM5FEN 6
186 #define NPCX_DBGFRZEN2_ITIM4FEN 5
187 #define NPCX_DBGFRZEN2_ITIM64FEN 3
188 #define NPCX_DBGFRZEN2_SMB1FEN 2
189 #define NPCX_DBGFRZEN2_SMB0FEN 1
190 #define NPCX_DBGFRZEN2_MFT3FEN 0
191 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
192 #define NPCX_DBGFRZEN3_ITIM3FEN 6
193 #define NPCX_DBGFRZEN3_ITIM2FEN 5
194 #define NPCX_DBGFRZEN3_ITIM1FEN 4
195 #define NPCX_DBGFRZEN3_I3CFEN 2
196 #define NPCX_DBGFRZEN3_SMB4FEN 1
197 #define NPCX_DBGFRZEN3_SHMFEN 0
198 #define NPCX_DBGFRZEN4_UART2FEN 6
199 #define NPCX_DBGFRZEN4_UART3FEN 5
200 #define NPCX_DBGFRZEN4_UART4FEN 4
201 #define NPCX_DBGFRZEN4_LCTFEN 3
202 #define NPCX_DBGFRZEN4_SMB7FEN 2
203 #define NPCX_DBGFRZEN4_SMB6FEN 1
204 #define NPCX_DBGFRZEN4_SMB5FEN 0
205
206 /*
207 * System Configuration (SCFG) device registers
208 */
209 struct scfg_reg {
210 /* 0x000: Device Control */
211 volatile uint8_t DEVCNT;
212 /* 0x001: Straps Status */
213 volatile uint8_t STRPST;
214 /* 0x002: Reset Control and Status */
215 volatile uint8_t RSTCTL;
216 volatile uint8_t reserved1;
217 /* 0x004: Device Control 3*/
218 volatile uint8_t DEV_CTL3;
219 volatile uint8_t reserved2;
220 /* 0x006: Device Control 4 */
221 volatile uint8_t DEV_CTL4;
222 volatile uint8_t reserved3[9];
223 /* 0x010 - 1F: Device Alternate Function 0 - F */
224 volatile uint8_t DEVALT0[16];
225 volatile uint8_t reserved4[6];
226 /* 0x026: Low-Voltage GPIO Pins Control 5 */
227 volatile uint8_t LV_GPIO_CTL5[1];
228 volatile uint8_t reserved5;
229 /* 0x028: Pull-Up/Pull-Down Enable 0 */
230 volatile uint8_t PUPD_EN0;
231 /* 0x029: Pull-Up/Pull-Down Enable 1 */
232 volatile uint8_t PUPD_EN1;
233 /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
234 volatile uint8_t LV_GPIO_CTL0[5];
235 };
236
237 /* Macro functions for SCFG multi-registers */
238 #define NPCX_DEV_CTL(base, n) \
239 (*(volatile uint8_t *)(base + n))
240 #define NPCX_DEVALT(base, n) \
241 (*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
242 #define NPCX_DEVALT_LK(base, n) \
243 (*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
244 #define NPCX_PUPD_EN(base, n) \
245 (*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
246 #define NPCX_LV_GPIO_CTL(base, n) \
247 (*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
248
249 #define NPCX_JEN_CTL1_OFFSET 0x120
250 #define NPCX_JEN_CTL1(base) (*(volatile uint8_t *)(base + (NPCX_JEN_CTL1_OFFSET)))
251
252 #define NPCX_JEN_CTL1_JEN_EN FIELD(0, 4)
253 #define NPCX_JEN_CTL1_JEN_HEN FIELD(4, 4)
254 #define NPCX_JEN_CTL1_JEN_ENABLE 0x9
255 #define NPCX_JEN_CTL1_JEN_DISABLE 0x6
256
257 /* SCFG register fields */
258 #define NPCX_DEVCNT_F_SPI_TRIS 6
259 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
260 #define NPCX_DEVCNT_JEN1_HEN 5
261 #define NPCX_DEVCNT_JEN0_HEN 4
262 #define NPCX_STRPST_TRIST 1
263 #define NPCX_STRPST_TEST 2
264 #define NPCX_STRPST_JEN1 4
265 #define NPCX_STRPST_JEN0 5
266 #define NPCX_STRPST_SPI_COMP 7
267 #define NPCX_RSTCTL_VCC1_RST_STS 0
268 #define NPCX_RSTCTL_DBGRST_STS 1
269 #define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
270 #define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
271 #define NPCX_RSTCTL_HIPRST_MODE 6
272 #define NPCX_DEV_CTL3_RNGINT_MD 1
273 #define NPCX_DEV_CTL3_FVCC1_PURST_EN 2
274 #define NPCX_DEV_CTL3_I3C1_MS 3
275 #define NPCX_DEV_CTL3_I3C2_MS 4
276 #define NPCX_DEV_CTL3_I3C3_MS 5
277 #define NPCX_DEV_CTL3_SIO_CLK_SEL FIELD(6, 2)
278 #define NPCX_DEV_CTL4_F_SPI_SLLK 2
279 #define NPCX_DEV_CTL4_SPI_SP_SEL 4
280 #define NPCX_DEV_CTL4_WP_IF 5
281 #define NPCX_DEV_CTL4_VCC1_RST_LK 6
282 #define NPCX_DEVPU0_I2C0_0_PUE 0
283 #define NPCX_DEVPU0_I2C0_1_PUE 1
284 #define NPCX_DEVPU0_I2C1_0_PUE 2
285 #define NPCX_DEVPU0_I2C2_0_PUE 4
286 #define NPCX_DEVPU0_I2C3_0_PUE 6
287 #define NPCX_DEVPU1_F_SPI_PUD_EN 7
288
289 #if defined(CONFIG_SOC_SERIES_NPCX4)
290 /* I3C module controller, target mode for the MDMA module operation */
291 #define NPCX_DEV_CTL3_I3C_MODE_BIT(inst_id) BIT(inst_id + 3)
292 #endif /* End of CONFIG_SOC_SERIES_NPCX4 */
293
294 /* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
295 enum npcx_hif_type {
296 NPCX_HIF_TYPE_NONE,
297 NPCX_HIF_TYPE_LPC,
298 NPCX_HIF_TYPE_ESPI_SHI,
299 };
300
301 /* Supported VOSCCLK frequency for SIO_CLK_SEL FILED in DEV_CTL3 register. */
302 enum npcx_voscclk_type {
303 NPCX_VOSCCLK_96MHz,
304 NPCX_VOSCCLK_100MHz,
305 NPCX_VOSCCLK_120MHz,
306 NPCX_VOSCCLK_90MHz,
307 };
308
309 /*
310 * System Glue (GLUE) device registers
311 */
312 struct glue_reg {
313 volatile uint8_t reserved1[2];
314 /* 0x002: SMBus Start Bit Detection */
315 volatile uint8_t SMB_SBD;
316 /* 0x003: SMBus Event Enable */
317 volatile uint8_t SMB_EEN;
318 volatile uint8_t reserved2[12];
319 /* 0x010: Simple Debug Port Data 0 */
320 volatile uint8_t SDPD0;
321 volatile uint8_t reserved3;
322 /* 0x012: Simple Debug Port Data 1 */
323 volatile uint8_t SDPD1;
324 volatile uint8_t reserved4;
325 /* 0x014: Simple Debug Port Control and Status */
326 volatile uint8_t SDP_CTS;
327 volatile uint8_t reserved5[12];
328 /* 0x021: SMBus Bus Select */
329 volatile uint8_t SMB_SEL;
330 volatile uint8_t reserved6[5];
331 /* 0x027: PSL Control and Status */
332 volatile uint8_t PSL_CTS;
333 };
334
335 /* GLUE register fields */
336 /* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
337 #define NPCX_PSL_CTS_MODE_BIT(bit) BIT(bit + 4)
338 /* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
339 #define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
340
341 /*
342 * Universal Asynchronous Receiver-Transmitter (UART) device registers
343 */
344 struct uart_reg {
345 /* 0x000: Transmit Data Buffer */
346 volatile uint8_t UTBUF;
347 volatile uint8_t reserved1;
348 /* 0x002: Receive Data Buffer */
349 volatile uint8_t URBUF;
350 volatile uint8_t reserved2;
351 /* 0x004: Interrupt Control */
352 volatile uint8_t UICTRL;
353 volatile uint8_t reserved3;
354 /* 0x006: Status */
355 volatile uint8_t USTAT;
356 volatile uint8_t reserved4;
357 /* 0x008: Frame Select */
358 volatile uint8_t UFRS;
359 volatile uint8_t reserved5;
360 /* 0x00A: Mode Select */
361 volatile uint8_t UMDSL;
362 volatile uint8_t reserved6;
363 /* 0x00C: Baud Rate Divisor */
364 volatile uint8_t UBAUD;
365 volatile uint8_t reserved7;
366 /* 0x00E: Baud Rate Prescaler */
367 volatile uint8_t UPSR;
368 volatile uint8_t reserved8[17];
369 /* 0x020: FIFO Mode Transmit Status */
370 volatile uint8_t UFTSTS;
371 volatile uint8_t reserved9;
372 /* 0x022: FIFO Mode Receive Status */
373 volatile uint8_t UFRSTS;
374 volatile uint8_t reserved10;
375 /* 0x024: FIFO Mode Transmit Control */
376 volatile uint8_t UFTCTL;
377 volatile uint8_t reserved11;
378 /* 0x026: FIFO Mode Receive Control */
379 volatile uint8_t UFRCTL;
380 };
381
382 /* UART register fields */
383 #define NPCX_UICTRL_TBE 0
384 #define NPCX_UICTRL_RBF 1
385 #define NPCX_UICTRL_ETI 5
386 #define NPCX_UICTRL_ERI 6
387 #define NPCX_UICTRL_EEI 7
388 #define NPCX_USTAT_PE 0
389 #define NPCX_USTAT_FE 1
390 #define NPCX_USTAT_DOE 2
391 #define NPCX_USTAT_ERR 3
392 #define NPCX_USTAT_BKD 4
393 #define NPCX_USTAT_RB9 5
394 #define NPCX_USTAT_XMIP 6
395 #define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
396 #define NPCX_UFRS_STP 2
397 #define NPCX_UFRS_XB9 3
398 #define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
399 #define NPCX_UFRS_PEN 6
400 #define NPCX_UMDSL_FIFO_MD 0
401 #define NPCX_UMDSL_ETD 4
402 #define NPCX_UMDSL_ERD 5
403
404 #define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
405 #define NPCX_UFTSTS_TEMPTY_LVL_STS 5
406 #define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
407 #define NPCX_UFTSTS_NXMIP 7
408 #define NPCX_UFRSTS_RFULL_LVL_STS 5
409 #define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
410 #define NPCX_UFRSTS_ERR 7
411 #define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
412 #define NPCX_UFTCTL_TEMPTY_LVL_EN 5
413 #define NPCX_UFTCTL_TEMPTY_EN 6
414 #define NPCX_UFTCTL_NXMIP_EN 7
415 #define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
416 #define NPCX_UFRCTL_RFULL_LVL_EN 5
417 #define NPCX_UFRCTL_RNEMPTY_EN 6
418 #define NPCX_UFRCTL_ERR_EN 7
419
420 /* Macro functions for MIWU multi-registers */
421 #define NPCX_WKEDG(base, group) \
422 (*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
423 #define NPCX_WKAEDG(base, group) \
424 (*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
425 #define NPCX_WKPND(base, group) \
426 (*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
427 #define NPCX_WKPCL(base, group) \
428 (*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
429 #define NPCX_WKEN(base, group) \
430 (*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
431 #define NPCX_WKINEN(base, group) \
432 (*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
433 #define NPCX_WKMOD(base, group) \
434 (*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
435 #define NPCX_WKST(base, group) \
436 (*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group)))
437
438 /*
439 * General-Purpose I/O (GPIO) device registers
440 */
441 struct gpio_reg {
442 /* 0x000: Port GPIOx Data Out */
443 volatile uint8_t PDOUT;
444 /* 0x001: Port GPIOx Data In */
445 volatile uint8_t PDIN;
446 /* 0x002: Port GPIOx Direction */
447 volatile uint8_t PDIR;
448 /* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
449 volatile uint8_t PPULL;
450 /* 0x004: Port GPIOx Pull-Up/Down Selection */
451 volatile uint8_t PPUD;
452 /* 0x005: Port GPIOx Drive Enable by VDD Present */
453 volatile uint8_t PENVDD;
454 /* 0x006: Port GPIOx Output Type */
455 volatile uint8_t PTYPE;
456 /* 0x007: Port GPIOx Lock Control */
457 volatile uint8_t PLOCK_CTL;
458 };
459
460 /*
461 * Pulse Width Modulator (PWM) device registers
462 */
463 struct pwm_reg {
464 /* 0x000: Clock Prescaler */
465 volatile uint16_t PRSC;
466 /* 0x002: Cycle Time */
467 volatile uint16_t CTR;
468 /* 0x004: PWM Control */
469 volatile uint8_t PWMCTL;
470 volatile uint8_t reserved1;
471 /* 0x006: Duty Cycle */
472 volatile uint16_t DCR;
473 volatile uint8_t reserved2[4];
474 /* 0x00C: PWM Control Extended */
475 volatile uint8_t PWMCTLEX;
476 volatile uint8_t reserved3;
477 };
478
479 /* PWM register fields */
480 #define NPCX_PWMCTL_INVP 0
481 #define NPCX_PWMCTL_CKSEL 1
482 #define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
483 #define NPCX_PWMCTL_PWR 7
484 #define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
485 #define NPCX_PWMCTLEX_OD_OUT 7
486
487 /*
488 * Analog-To-Digital Converter (ADC) device registers
489 */
490 struct adc_reg {
491 /* 0x000: ADC Status */
492 volatile uint16_t ADCSTS;
493 /* 0x002: ADC Configuration */
494 volatile uint16_t ADCCNF;
495 /* 0x004: ADC Timing Control */
496 volatile uint16_t ATCTL;
497 /* 0x006: ADC Single Channel Address */
498 volatile uint16_t ASCADD;
499 /* 0x008: ADC Scan Channels Select */
500 volatile uint16_t ADCCS;
501 /* 0x00A: ADC Scan Channels Select 2 */
502 volatile uint16_t ADCCS2;
503 volatile uint8_t reserved1[14];
504 /* 0x01A: Threshold Status */
505 volatile uint16_t THRCTS;
506 volatile uint8_t reserved2[4];
507 /* 0x020: Internal register 1 for ADC Speed */
508 volatile uint16_t ADCCNF2;
509 /* 0x022: Internal register 2 for ADC Speed */
510 volatile uint16_t GENDLY;
511 volatile uint8_t reserved3[2];
512 /* 0x026: Internal register 3 for ADC Speed */
513 volatile uint16_t MEAST;
514 };
515
516 /* ADC internal inline functions for multi-registers */
517 #define CHNDAT(base, ch) \
518 (*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
519 #define THRCTL(base, ctrl) \
520 (*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
521
522 /* ADC register fields */
523 #define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
524 #define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
525 #define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
526 #define NPCX_ADCSTS_EOCEV 0
527 #define NPCX_ADCSTS_EOCCEV 1
528 #define NPCX_ADCCNF_ADCEN 0
529 #define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
530 #define NPCX_ADCCNF_ADCRPTC 3
531 #define NPCX_ADCCNF_START 4
532 #define NPCX_ADCCNF_ADCTTE 5
533 #define NPCX_ADCCNF_INTECEN 6
534 #define NPCX_ADCCNF_INTECCEN 7
535 #define NPCX_ADCCNF_INTETCEN 8
536 #define NPCX_ADCCNF_INTOVFEN 9
537 #define NPCX_ADCCNF_STOP 11
538 #define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
539 #define NPCX_CHNDAT_NEW 15
540 #define NPCX_THRCTS_ADC_WKEN 15
541 #define NPCX_THRCTS_THR3_IEN 10
542 #define NPCX_THRCTS_THR2_IEN 9
543 #define NPCX_THRCTS_THR1_IEN 8
544 #define NPCX_THRCTS_ADC_EVENT 7
545 #define NPCX_THRCTS_THR3_STS 2
546 #define NPCX_THRCTS_THR2_STS 1
547 #define NPCX_THRCTS_THR1_STS 0
548 #define NPCX_THR_DCTL_THRD_EN 15
549 #define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
550
551 /*
552 * Timer Watchdog (TWD) device registers
553 */
554 struct twd_reg {
555 /* 0x000: Timer and Watchdog Configuration */
556 volatile uint8_t TWCFG;
557 volatile uint8_t reserved1;
558 /* 0x002: Timer and Watchdog Clock Prescaler */
559 volatile uint8_t TWCP;
560 volatile uint8_t reserved2;
561 /* 0x004: TWD Timer 0 */
562 volatile uint16_t TWDT0;
563 /* 0x006: TWDT0 Control and Status */
564 volatile uint8_t T0CSR;
565 volatile uint8_t reserved3;
566 /* 0x008: Watchdog Count */
567 volatile uint8_t WDCNT;
568 volatile uint8_t reserved4;
569 /* 0x00A: Watchdog Service Data Match */
570 volatile uint8_t WDSDM;
571 volatile uint8_t reserved5;
572 /* 0x00C: TWD Timer 0 Counter */
573 volatile uint16_t TWMT0;
574 /* 0x00E: Watchdog Counter */
575 volatile uint8_t TWMWD;
576 volatile uint8_t reserved6;
577 /* 0x010: Watchdog Clock Prescaler */
578 volatile uint8_t WDCP;
579 volatile uint8_t reserved7;
580 };
581
582 /* TWD register fields */
583 #define NPCX_TWCFG_LTWCFG 0
584 #define NPCX_TWCFG_LTWCP 1
585 #define NPCX_TWCFG_LTWDT0 2
586 #define NPCX_TWCFG_LWDCNT 3
587 #define NPCX_TWCFG_WDCT0I 4
588 #define NPCX_TWCFG_WDSDME 5
589 #define NPCX_T0CSR_RST 0
590 #define NPCX_T0CSR_TC 1
591 #define NPCX_T0CSR_WDLTD 3
592 #define NPCX_T0CSR_WDRST_STS 4
593 #define NPCX_T0CSR_WD_RUN 5
594 #define NPCX_T0CSR_TESDIS 7
595
596 /*
597 * Enhanced Serial Peripheral Interface (eSPI) device registers
598 */
599 struct espi_reg {
600 /* 0x000: eSPI Identification */
601 volatile uint32_t ESPIID;
602 /* 0x004: eSPI Configuration */
603 volatile uint32_t ESPICFG;
604 /* 0x008: eSPI Status */
605 volatile uint32_t ESPISTS;
606 /* 0x00C: eSPI Interrupt Enable */
607 volatile uint32_t ESPIIE;
608 /* 0x010: eSPI Wake-Up Enable */
609 volatile uint32_t ESPIWE;
610 /* 0x014: Virtual Wire Register Index */
611 volatile uint32_t VWREGIDX;
612 /* 0x018: Virtual Wire Register Data */
613 volatile uint32_t VWREGDATA;
614 /* 0x01C: OOB Receive Buffer Read Head */
615 volatile uint32_t OOBRXRDHEAD;
616 /* 0x020: OOB Transmit Buffer Write Head */
617 volatile uint32_t OOBTXWRHEAD;
618 /* 0x024: OOB Channel Control */
619 volatile uint32_t OOBCTL;
620 /* 0x028: Flash Receive Buffer Read Head */
621 volatile uint32_t FLASHRXRDHEAD;
622 /* 0x02C: Flash Transmit Buffer Write Head */
623 volatile uint32_t FLASHTXWRHEAD;
624 volatile uint32_t reserved1;
625 /* 0x034: Flash Channel Configuration */
626 volatile uint32_t FLASHCFG;
627 /* 0x038: Flash Channel Control */
628 volatile uint32_t FLASHCTL;
629 /* 0x03C: eSPI Error Status */
630 volatile uint32_t ESPIERR;
631 /* 0x040: Peripheral Bus Master Receive Buffer Read Head */
632 volatile uint32_t PBMRXRDHEAD;
633 /* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
634 volatile uint32_t PBMTXWRHEAD;
635 /* 0x048: Peripheral Channel Configuration */
636 volatile uint32_t PERCFG;
637 /* 0x04C: Peripheral Channel Control */
638 volatile uint32_t PERCTL;
639 /* 0x050: Status Image Register */
640 volatile uint16_t STATUS_IMG;
641 volatile uint16_t reserved2[79];
642 /* 0x0F0: NPCX specific eSPI Register1 */
643 volatile uint8_t NPCX_ONLY_ESPI_REG1;
644 /* 0x0F1: NPCX specific eSPI Register2 */
645 volatile uint8_t NPCX_ONLY_ESPI_REG2;
646 volatile uint16_t reserved3[7];
647 /* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
648 volatile uint32_t VWEVSM[10];
649 volatile uint32_t reserved4[6];
650 /* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
651 volatile uint32_t VWEVMS[12];
652 volatile uint32_t reserved5[4];
653 /* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
654 volatile uint32_t VWGPSM[16];
655 volatile uint32_t reserved6[79];
656 /* 0x2FC: Virtual Wire Channel Control */
657 volatile uint32_t VWCTL;
658 /* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
659 volatile uint32_t OOBRXBUF[20];
660 volatile uint32_t reserved7[12];
661 /* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
662 volatile uint32_t OOBTXBUF[20];
663 volatile uint32_t reserved8[11];
664 /* 0x3FC: OOB Channel Control used in 'direct' mode */
665 volatile uint32_t OOBCTL_DIRECT;
666 /* 0x400 - 443: Flash Receive Buffer 0-17 */
667 volatile uint32_t FLASHRXBUF[18];
668 volatile uint32_t reserved9[14];
669 /* 0x480 - 497: Flash Transmit Buffer 0-16 */
670 volatile uint32_t FLASHTXBUF[17];
671 volatile uint32_t reserved10[14];
672 /* 0x4FC: Flash Channel Control used in 'direct' mode */
673 volatile uint32_t FLASHCTL_DIRECT;
674 volatile uint32_t reserved12[64];
675 /* 0x600 - 63F */
676 volatile uint32_t FLASH_PRTR_BADDR[16];
677 /* 0x640 - 67F */
678 volatile uint32_t FLASH_PRTR_HADDR[16];
679 /* 0x680 - 6BF */
680 volatile uint32_t FLASH_RGN_TAG_OVR[16];
681 volatile uint32_t reserved13[80];
682 /* 0x800 */
683 volatile uint32_t FLASH_RPMC_CFG_1;
684 /* 0x804 */
685 volatile uint32_t FLASH_RPMC_CFG_2;
686 /* 0x808 */
687 volatile uint32_t RMAP_FLASH_OFFS;
688 /* 0x80C */
689 volatile uint32_t RMAP_DST_BASE;
690 /* 0x810 */
691 volatile uint32_t RMAP_WIN_SIZE;
692 /* 0x814 */
693 volatile uint32_t FLASHBASE;
694 volatile uint32_t reserved14[58];
695 };
696
697 /* eSPI register fields */
698 #define NPCX_ESPICFG_PCHANEN 0
699 #define NPCX_ESPICFG_VWCHANEN 1
700 #define NPCX_ESPICFG_OOBCHANEN 2
701 #define NPCX_ESPICFG_FLASHCHANEN 3
702 #define NPCX_ESPICFG_HPCHANEN 4
703 #define NPCX_ESPICFG_HVWCHANEN 5
704 #define NPCX_ESPICFG_HOOBCHANEN 6
705 #define NPCX_ESPICFG_HFLASHCHANEN 7
706 #define NPCX_ESPICFG_CHANS_FIELD FIELD(0, 4)
707 #define NPCX_ESPICFG_HCHANS_FIELD FIELD(4, 4)
708 #define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
709 #define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
710 #define NPCX_ESPICFG_FLCHANMODE 16
711 #define NPCX_ESPICFG_PCCHN_SUPP 24
712 #define NPCX_ESPICFG_VWCHN_SUPP 25
713 #define NPCX_ESPICFG_OOBCHN_SUPP 26
714 #define NPCX_ESPICFG_FLASHCHN_SUPP 27
715 #define NPCX_ESPIIE_IBRSTIE 0
716 #define NPCX_ESPIIE_CFGUPDIE 1
717 #define NPCX_ESPIIE_BERRIE 2
718 #define NPCX_ESPIIE_OOBRXIE 3
719 #define NPCX_ESPIIE_FLASHRXIE 4
720 #define NPCX_ESPIIE_FLNACSIE 5
721 #define NPCX_ESPIIE_PERACCIE 6
722 #define NPCX_ESPIIE_DFRDIE 7
723 #define NPCX_ESPIIE_VWUPDIE 8
724 #define NPCX_ESPIIE_ESPIRSTIE 9
725 #define NPCX_ESPIIE_PLTRSTIE 10
726 #define NPCX_ESPIIE_AMERRIE 15
727 #define NPCX_ESPIIE_AMDONEIE 16
728 #define NPCX_ESPIIE_BMTXDONEIE 19
729 #define NPCX_ESPIIE_PBMRXIE 20
730 #define NPCX_ESPIIE_PMSGRXIE 21
731 #define NPCX_ESPIIE_BMBURSTERRIE 22
732 #define NPCX_ESPIIE_BMBURSTDONEIE 23
733 #define NPCX_ESPIWE_IBRSTWE 0
734 #define NPCX_ESPIWE_CFGUPDWE 1
735 #define NPCX_ESPIWE_BERRWE 2
736 #define NPCX_ESPIWE_OOBRXWE 3
737 #define NPCX_ESPIWE_FLASHRXWE 4
738 #define NPCX_ESPIWE_FLNACSWE 5
739 #define NPCX_ESPIWE_PERACCWE 6
740 #define NPCX_ESPIWE_DFRDWE 7
741 #define NPCX_ESPIWE_VWUPDWE 8
742 #define NPCX_ESPIWE_ESPIRSTWE 9
743 #define NPCX_ESPIWE_PBMRXWE 20
744 #define NPCX_ESPIWE_PMSGRXWE 21
745 #define NPCX_ESPISTS_IBRST 0
746 #define NPCX_ESPISTS_CFGUPD 1
747 #define NPCX_ESPISTS_BERR 2
748 #define NPCX_ESPISTS_OOBRX 3
749 #define NPCX_ESPISTS_FLASHRX 4
750 #define NPCX_ESPISTS_FLNACS 5
751 #define NPCX_ESPISTS_PERACC 6
752 #define NPCX_ESPISTS_DFRD 7
753 #define NPCX_ESPISTS_VWUPD 8
754 #define NPCX_ESPISTS_ESPIRST 9
755 #define NPCX_ESPISTS_PLTRST 10
756 #define NPCX_ESPISTS_AMERR 15
757 #define NPCX_ESPISTS_AMDONE 16
758 #define NPCX_ESPISTS_VWUPDW 17
759 #define NPCX_ESPISTS_BMTXDONE 19
760 #define NPCX_ESPISTS_PBMRX 20
761 #define NPCX_ESPISTS_PMSGRX 21
762 #define NPCX_ESPISTS_BMBURSTERR 22
763 #define NPCX_ESPISTS_BMBURSTDONE 23
764 #define NPCX_ESPISTS_ESPIRST_LVL 24
765 #define NPCX_VWSWIRQ_IRQ_NUM FIELD(0, 7)
766 #define NPCX_VWSWIRQ_IRQ_LVL 7
767 #define NPCX_VWSWIRQ_INDEX FIELD(8, 7)
768 #define NPCX_VWSWIRQ_INDEX_EN 15
769 #define NPCX_VWSWIRQ_DIRTY 16
770 #define NPCX_VWSWIRQ_ENPLTRST 17
771 #define NPCX_VWSWIRQ_ENCDRST 19
772 #define NPCX_VWSWIRQ_EDGE_IRQ 28
773 #define NPCX_VWEVMS_WIRE FIELD(0, 4)
774 #define NPCX_VWEVMS_VALID FIELD(4, 4)
775 #define NPCX_VWEVMS_INDEX FIELD(8, 7)
776 #define NPCX_VWEVMS_INDEX_EN 15
777 #define NPCX_VWEVMS_IE 18
778 #define NPCX_VWEVMS_WE 20
779 #define NPCX_VWEVSM_WIRE FIELD(0, 4)
780 #define NPCX_VWEVSM_VALID FIELD(4, 4)
781 #define NPCX_VWEVSM_INDEX FIELD(8, 7)
782 #define NPCX_VWEVSM_INDEX_EN 15
783 #define NPCX_VWEVSM_BIT_VALID(n) (4+n)
784 #define NPCX_VWEVSM_HW_WIRE FIELD(24, 4)
785 #define NPCX_VWGPSM_INDEX_EN 15
786 #define NPCX_OOBCTL_OOB_FREE 0
787 #define NPCX_OOBCTL_OOB_AVAIL 1
788 #define NPCX_OOBCTL_RSTBUFHEADS 2
789 #define NPCX_OOBCTL_OOBPLSIZE FIELD(10, 3)
790 #define NPCX_FLASHCFG_FLASHBLERSSIZE FIELD(7, 3)
791 #define NPCX_FLASHCFG_FLASHPLSIZE FIELD(10, 3)
792 #define NPCX_FLASHCFG_FLASHREQSIZE FIELD(13, 3)
793 #define NPCX_FLASHCFG_FLCAPA FIELD(24, 2)
794 #define NPCX_FLASHCFG_TRGFLEBLKSIZE FIELD(16, 8)
795 #define NPCX_FLASHCFG_FLREQSUP FIELD(0, 3)
796 #define NPCX_FLASHCTL_FLASH_NP_FREE 0
797 #define NPCX_FLASHCTL_FLASH_TX_AVAIL 1
798 #define NPCX_FLASHCTL_STRPHDR 2
799 #define NPCX_FLASHCTL_DMATHRESH FIELD(3, 2)
800 #define NPCX_FLASHCTL_AMTSIZE FIELD(5, 8)
801 #define NPCX_FLASHCTL_RSTBUFHEADS 13
802 #define NPCX_FLASHCTL_CRCEN 14
803 #define NPCX_FLASHCTL_CHKSUMSEL 15
804 #define NPCX_FLASHCTL_AMTEN 16
805 #define NPCX_FLASHCTL_SAF_AUTO_READ 18
806 #define NPCX_FLASHCTL_AUTO_RD_DIS_CTL 19
807 #define NPCX_FLASHCTL_BLK_FLASH_NP_FREE 20
808 #define NPCX_FLASHBASE_FLBASE_ADDR FIELD(12, 15)
809 #define NPCX_FLASH_PRTR_BADDR FIELD(12, 15)
810 #define NPCX_FRGN_WPR 29
811 #define SAF_PROT_LCK 31
812 #define NPCX_FRGN_RPR 30
813 #define NPCX_FLASH_PRTR_HADDR FIELD(12, 15)
814 #define NPCX_FLASH_TAG_OVR_RPR FIELD(16, 16)
815 #define NPCX_FLASH_TAG_OVR_WPR FIELD(0, 16)
816 #define NPCX_FLASH_RPMC_CFG1_CNTR FIELD(0, 4)
817 #define NPCX_FLASH_RPMC_CFG1_OP1 FIELD(4, 8)
818 #define NPCX_FLASH_RPMC_CFG1_TRGRPMCSUP FIELD(26, 6)
819 #define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
820 #define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
821 #define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
822
823 /*
824 * Mobile System Wake-Up Control (MSWC) device registers
825 */
826 struct mswc_reg {
827 /* 0x000: MSWC Control Status 1 */
828 volatile uint8_t MSWCTL1;
829 volatile uint8_t reserved1;
830 /* 0x002: MSWC Control Status 2 */
831 volatile uint8_t MSWCTL2;
832 volatile uint8_t reserved2[5];
833 /* 0x008: Host Configuration Base Address Low */
834 volatile uint8_t HCBAL;
835 volatile uint8_t reserved3;
836 /* 0x00A: Host Configuration Base Address High */
837 volatile uint8_t HCBAH;
838 volatile uint8_t reserved4;
839 /* 0X00C: MSWC INTERRUPT ENABLE 2 */
840 volatile uint8_t MSIEN2;
841 volatile uint8_t reserved5;
842 /* 0x00E: MSWC Host Event Status 0 */
843 volatile uint8_t MSHES0;
844 volatile uint8_t reserved6;
845 /* 0x010: MSWC Host Event Interrupt Enable */
846 volatile uint8_t MSHEIE0;
847 volatile uint8_t reserved7;
848 /* 0x012: Host Control */
849 volatile uint8_t HOST_CTL;
850 volatile uint8_t reserved8;
851 /* 0x014: SMI Pulse Length */
852 volatile uint8_t SMIP_LEN;
853 volatile uint8_t reserved9;
854 /* 0x016: SCI Pulse Length */
855 volatile uint8_t SCIP_LEN;
856 volatile uint8_t reserved10[5];
857 /* 0x01C: SRID Core Access */
858 volatile uint8_t SRID_CR;
859 volatile uint8_t reserved11[3];
860 /* 0x020: SID Core Access */
861 volatile uint8_t SID_CR;
862 volatile uint8_t reserved12;
863 /* 0x022: DEVICE_ID Core Access */
864 volatile uint8_t DEVICE_ID_CR;
865 volatile uint8_t reserved13[5];
866 /* 0x028: Chip Revision Core Access */
867 volatile uint8_t CHPREV_CR;
868 volatile uint8_t reserved14[5];
869 /* 0x02E: Virtual Wire Sleep States */
870 volatile uint8_t VW_SLPST1;
871 volatile uint8_t reserved15;
872 };
873
874 /* MSWC register fields */
875 #define NPCX_MSWCTL1_HRSTOB 0
876 #define NPCS_MSWCTL1_HWPRON 1
877 #define NPCX_MSWCTL1_PLTRST_ACT 2
878 #define NPCX_MSWCTL1_VHCFGA 3
879 #define NPCX_MSWCTL1_HCFGLK 4
880 #define NPCX_MSWCTL1_PWROFFB 6
881 #define NPCX_MSWCTL1_A20MB 7
882
883 /*
884 * Shared Memory (SHM) device registers
885 */
886 struct shm_reg {
887 /* 0x000: Shared Memory Core Status */
888 volatile uint8_t SMC_STS;
889 /* 0x001: Shared Memory Core Control */
890 volatile uint8_t SMC_CTL;
891 /* 0x002: Shared Memory Host Control */
892 volatile uint8_t SHM_CTL;
893 volatile uint8_t reserved1[2];
894 /* 0x005: Indirect Memory Access Window Size */
895 volatile uint8_t IMA_WIN_SIZE;
896 volatile uint8_t reserved2;
897 /* 0x007: Shared Access Windows Size */
898 volatile uint8_t WIN_SIZE;
899 /* 0x008: Shared Access Window 1, Semaphore */
900 volatile uint8_t SHAW1_SEM;
901 /* 0x009: Shared Access Window 2, Semaphore */
902 volatile uint8_t SHAW2_SEM;
903 volatile uint8_t reserved3;
904 /* 0x00B: Indirect Memory Access, Semaphore */
905 volatile uint8_t IMA_SEM;
906 volatile uint8_t reserved4[2];
907 /* 0x00E: Shared Memory Configuration */
908 volatile uint16_t SHCFG;
909 /* 0x010: Shared Access Window 1 Write Protect */
910 volatile uint8_t WIN1_WR_PROT;
911 /* 0x011: Shared Access Window 1 Read Protect */
912 volatile uint8_t WIN1_RD_PROT;
913 /* 0x012: Shared Access Window 2 Write Protect */
914 volatile uint8_t WIN2_WR_PROT;
915 /* 0x013: Shared Access Window 2 Read Protect */
916 volatile uint8_t WIN2_RD_PROT;
917 volatile uint8_t reserved5[2];
918 /* 0x016: Indirect Memory Access Write Protect */
919 volatile uint8_t IMA_WR_PROT;
920 /* 0x017: Indirect Memory Access Read Protect */
921 volatile uint8_t IMA_RD_PROT;
922 volatile uint8_t reserved6[8];
923 /* 0x020: Shared Access Window 1 Base */
924 volatile uint32_t WIN_BASE1;
925 /* 0x024: Shared Access Window 2 Base */
926 volatile uint32_t WIN_BASE2;
927 volatile uint32_t reserved7;
928 /* 0x02C: Indirect Memory Access Base */
929 volatile uint32_t IMA_BASE;
930 volatile uint8_t reserved8[10];
931 /* 0x03A: Reset Configuration */
932 volatile uint8_t RST_CFG;
933 volatile uint8_t reserved9[5];
934 /* 0x040: Debug Port 80 Buffered Data */
935 volatile uint16_t DP80BUF;
936 /* 0x042: Debug Port 80 Status */
937 volatile uint8_t DP80STS;
938 volatile uint8_t reserved10;
939 /* 0x044: Debug Port 80 Control */
940 volatile uint8_t DP80CTL;
941 volatile uint8_t reserved11[3];
942 /* 0x048: Host_Offset in Windows 1, 2 Status */
943 volatile uint8_t HOFS_STS;
944 /* 0x049: Host_Offset in Windows 1, 2 Control */
945 volatile uint8_t HOFS_CTL;
946 /* 0x04A: Core_Offset in Window 2 Address */
947 volatile uint16_t COFS2;
948 /* 0x04C: Core_Offset in Window 1 Address */
949 volatile uint16_t COFS1;
950 volatile uint16_t reserved12;
951 };
952
953 /* SHM register fields */
954 #define NPCX_SMC_STS_HRERR 0
955 #define NPCX_SMC_STS_HWERR 1
956 #define NPCX_SMC_STS_HSEM1W 4
957 #define NPCX_SMC_STS_HSEM2W 5
958 #define NPCX_SMC_STS_SHM_ACC 6
959 #define NPCX_SMC_CTL_HERR_IE 2
960 #define NPCX_SMC_CTL_HSEM1_IE 3
961 #define NPCX_SMC_CTL_HSEM2_IE 4
962 #define NPCX_SMC_CTL_ACC_IE 5
963 #define NPCX_SMC_CTL_PREF_EN 6
964 #define NPCX_SMC_CTL_HOSTWAIT 7
965 #define NPCX_FLASH_SIZE_STALL_HOST 6
966 #define NPCX_FLASH_SIZE_RD_BURST 7
967 #define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD FIELD(0, 4)
968 #define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD FIELD(4, 4)
969 #define NPCX_WIN_PROT_RW1L_RP 0
970 #define NPCX_WIN_PROT_RW1L_WP 1
971 #define NPCX_WIN_PROT_RW1H_RP 2
972 #define NPCX_WIN_PROT_RW1H_WP 3
973 #define NPCX_WIN_PROT_RW2L_RP 4
974 #define NPCX_WIN_PROT_RW2L_WP 5
975 #define NPCX_WIN_PROT_RW2H_RP 6
976 #define NPCX_WIN_PROT_RW2H_WP 7
977 #define NPCX_PWIN_SIZEI_RPROT 13
978 #define NPCX_PWIN_SIZEI_WPROT 14
979 #define NPCX_CSEM2 6
980 #define NPCX_CSEM3 7
981 #define NPCX_DP80STS_FWR 5
982 #define NPCX_DP80STS_FNE 6
983 #define NPCX_DP80STS_FOR 7
984 #define NPCX_DP80CTL_DP80EN 0
985 #define NPCX_DP80CTL_SYNCEN 1
986 #define NPCX_DP80CTL_ADV 2
987 #define NPCX_DP80CTL_RAA 3
988 #define NPCX_DP80CTL_RFIFO 4
989 #define NPCX_DP80CTL_CIEN 5
990 #define NPCX_DP80CTL_DP80_HF_CFG 7
991 #define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
992
993 /*
994 * Keyboard and Mouse Controller (KBC) device registers
995 */
996 struct kbc_reg {
997 /* 0x000h: Host Interface Control */
998 volatile uint8_t HICTRL;
999 volatile uint8_t reserved1;
1000 /* 0x002h: Host Interface IRQ Control */
1001 volatile uint8_t HIIRQC;
1002 volatile uint8_t reserved2;
1003 /* 0x004h: Host Interface Keyboard/Mouse Status */
1004 volatile uint8_t HIKMST;
1005 volatile uint8_t reserved3;
1006 /* 0x006h: Host Interface Keyboard Data Out Buffer */
1007 volatile uint8_t HIKDO;
1008 volatile uint8_t reserved4;
1009 /* 0x008h: Host Interface Mouse Data Out Buffer */
1010 volatile uint8_t HIMDO;
1011 volatile uint8_t reserved5;
1012 /* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
1013 volatile uint8_t HIKMDI;
1014 /* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
1015 volatile uint8_t SHIKMDI;
1016 };
1017
1018 /* KBC register field */
1019 #define NPCX_HICTRL_OBFKIE 0
1020 #define NPCX_HICTRL_OBFMIE 1
1021 #define NPCX_HICTRL_OBECIE 2
1022 #define NPCX_HICTRL_IBFCIE 3
1023 #define NPCX_HICTRL_PMIHIE 4
1024 #define NPCX_HICTRL_PMIOCIE 5
1025 #define NPCX_HICTRL_PMICIE 6
1026 #define NPCX_HICTRL_FW_OBF 7
1027 #define NPCX_HIKMST_OBF 0
1028 #define NPCX_HIKMST_IBF 1
1029 #define NPCX_HIKMST_F0 2
1030 #define NPCX_HIKMST_A2 3
1031 #define NPCX_HIKMST_ST0 4
1032 #define NPCX_HIKMST_ST1 5
1033 #define NPCX_HIKMST_ST2 6
1034 #define NPCX_HIKMST_ST3 7
1035
1036 /*
1037 * Power Management Channel (PMCH) device registers
1038 */
1039
1040 struct pmch_reg {
1041 /* 0x000: Host Interface PM Status */
1042 volatile uint8_t HIPMST;
1043 volatile uint8_t reserved1;
1044 /* 0x002: Host Interface PM Data Out Buffer */
1045 volatile uint8_t HIPMDO;
1046 volatile uint8_t reserved2;
1047 /* 0x004: Host Interface PM Data In Buffer */
1048 volatile uint8_t HIPMDI;
1049 /* 0x005: Host Interface PM Shadow Data In Buffer */
1050 volatile uint8_t SHIPMDI;
1051 /* 0x006: Host Interface PM Data Out Buffer with SCI */
1052 volatile uint8_t HIPMDOC;
1053 volatile uint8_t reserved3;
1054 /* 0x008: Host Interface PM Data Out Buffer with SMI */
1055 volatile uint8_t HIPMDOM;
1056 volatile uint8_t reserved4;
1057 /* 0x00A: Host Interface PM Data In Buffer with SCI */
1058 volatile uint8_t HIPMDIC;
1059 volatile uint8_t reserved5;
1060 /* 0x00C: Host Interface PM Control */
1061 volatile uint8_t HIPMCTL;
1062 /* 0x00D: Host Interface PM Control 2 */
1063 volatile uint8_t HIPMCTL2;
1064 /* 0x00E: Host Interface PM Interrupt Control */
1065 volatile uint8_t HIPMIC;
1066 volatile uint8_t reserved6;
1067 /* 0x010: Host Interface PM Interrupt Enable */
1068 volatile uint8_t HIPMIE;
1069 volatile uint8_t reserved7;
1070 };
1071
1072 /* PMCH register field */
1073 #define NPCX_HIPMIE_SCIE 1
1074 #define NPCX_HIPMIE_SMIE 2
1075 #define NPCX_HIPMCTL_IBFIE 0
1076 #define NPCX_HIPMCTL_OBEIE 1
1077 #define NPCX_HIPMCTL_SCIPOL 6
1078 #define NPCX_HIPMST_OBF 0
1079 #define NPCX_HIPMST_IBF 1
1080 #define NPCX_HIPMST_F0 2
1081 #define NPCX_HIPMST_CMD 3
1082 #define NPCX_HIPMST_ST0 4
1083 #define NPCX_HIPMST_ST1 5
1084 #define NPCX_HIPMST_ST2 6
1085 #define NPCX_HIPMIC_SMIB 1
1086 #define NPCX_HIPMIC_SCIB 2
1087 #define NPCX_HIPMIC_SMIPOL 6
1088
1089 /*
1090 * Core Access to Host (C2H) device registers
1091 */
1092 struct c2h_reg {
1093 /* 0x000: Indirect Host I/O Address */
1094 volatile uint16_t IHIOA;
1095 /* 0x002: Indirect Host Data */
1096 volatile uint8_t IHD;
1097 volatile uint8_t reserved1;
1098 /* 0x004: Lock Host Access */
1099 volatile uint16_t LKSIOHA;
1100 /* 0x006: Access Lock Violation */
1101 volatile uint16_t SIOLV;
1102 /* 0x008: Core-to-Host Modules Access Enable */
1103 volatile uint16_t CRSMAE;
1104 /* 0x00A: Module Control */
1105 volatile uint8_t SIBCTRL;
1106 volatile uint8_t reserved3;
1107 };
1108
1109 /* C2H register fields */
1110 #define NPCX_LKSIOHA_LKCFG 0
1111 #define NPCX_LKSIOHA_LKSPHA 2
1112 #define NPCX_LKSIOHA_LKHIKBD 11
1113 #define NPCX_CRSMAE_CFGAE 0
1114 #define NPCX_CRSMAE_HIKBDAE 11
1115 #define NPCX_SIOLV_SPLV 2
1116 #define NPCX_SIBCTRL_CSAE 0
1117 #define NPCX_SIBCTRL_CSRD 1
1118 #define NPCX_SIBCTRL_CSWR 2
1119
1120 /*
1121 * SMBUS (SMB) device registers
1122 */
1123 struct smb_reg {
1124 /* 0x000: SMB Serial Data */
1125 volatile uint8_t SMBSDA;
1126 volatile uint8_t reserved1;
1127 /* 0x002: SMB Status */
1128 volatile uint8_t SMBST;
1129 volatile uint8_t reserved2;
1130 /* 0x004: SMB Control Status */
1131 volatile uint8_t SMBCST;
1132 volatile uint8_t reserved3;
1133 /* 0x006: SMB Control 1 */
1134 volatile uint8_t SMBCTL1;
1135 volatile uint8_t reserved4;
1136 /* 0x008: SMB Own Address */
1137 volatile uint8_t SMBADDR1;
1138 volatile uint8_t reserved5;
1139 /* 0x00A: SMB Control 2 */
1140 volatile uint8_t SMBCTL2;
1141 volatile uint8_t reserved6;
1142 /* 0x00C: SMB Own Address */
1143 volatile uint8_t SMBADDR2;
1144 volatile uint8_t reserved7;
1145 /* 0x00E: SMB Control 3 */
1146 volatile uint8_t SMBCTL3;
1147 /* 0x00F: SMB Bus Timeout */
1148 volatile uint8_t SMBT_OUT;
1149 union {
1150 /* Bank 0 */
1151 struct {
1152 /* 0x010: SMB Own Address 3 */
1153 volatile uint8_t SMBADDR3;
1154 /* 0x011: SMB Own Address 7 */
1155 volatile uint8_t SMBADDR7;
1156 /* 0x012: SMB Own Address 4 */
1157 volatile uint8_t SMBADDR4;
1158 /* 0x013: SMB Own Address 8 */
1159 volatile uint8_t SMBADDR8;
1160 /* 0x014: SMB Own Address 5 */
1161 volatile uint8_t SMBADDR5;
1162 volatile uint8_t reserved8;
1163 /* 0x016: SMB Own Address 6 */
1164 volatile uint8_t SMBADDR6;
1165 volatile uint8_t reserved9;
1166 /* 0x018: SMB Control Status 2 */
1167 volatile uint8_t SMBCST2;
1168 /* 0x019: SMB Control Status 3 */
1169 volatile uint8_t SMBCST3;
1170 /* 0x01A: SMB Control 4 */
1171 volatile uint8_t SMBCTL4;
1172 volatile uint8_t reserved10;
1173 /* 0x01C: SMB SCL Low Time */
1174 volatile uint8_t SMBSCLLT;
1175 /* 0x01D: SMB FIFO Control */
1176 volatile uint8_t SMBFIF_CTL;
1177 /* 0x01E: SMB SCL High Time */
1178 volatile uint8_t SMBSCLHT;
1179 volatile uint8_t reserved11;
1180 };
1181 /* Bank 1 */
1182 struct {
1183 /* 0x010: SMB FIFO Control */
1184 volatile uint8_t SMBFIF_CTS;
1185 volatile uint8_t reserved12;
1186 /* 0x012: SMB Tx-FIFO Control */
1187 volatile uint8_t SMBTXF_CTL;
1188 volatile uint8_t reserved13;
1189 /* 0x014: SMB Bus Timeout */
1190 volatile uint8_t SMB_T_OUT;
1191 volatile uint8_t reserved14[3];
1192 /* 0x018: SMB Control Status 2 (FIFO) */
1193 volatile uint8_t SMBCST2_FIFO;
1194 /* 0x019: SMB Control Status 3 (FIFO) */
1195 volatile uint8_t SMBCST3_FIFO;
1196 /* 0x01A: SMB Tx-FIFO Status */
1197 volatile uint8_t SMBTXF_STS;
1198 volatile uint8_t reserved15;
1199 /* 0x01C: SMB Rx-FIFO Status */
1200 volatile uint8_t SMBRXF_STS;
1201 volatile uint8_t reserved16;
1202 /* 0x01E: SMB Rx-FIFO Control */
1203 volatile uint8_t SMBRXF_CTL;
1204 volatile uint8_t reserved17[1];
1205 };
1206 };
1207 };
1208
1209 /* SMB register fields */
1210 #define NPCX_SMBST_XMIT 0
1211 #define NPCX_SMBST_MASTER 1
1212 #define NPCX_SMBST_NMATCH 2
1213 #define NPCX_SMBST_STASTR 3
1214 #define NPCX_SMBST_NEGACK 4
1215 #define NPCX_SMBST_BER 5
1216 #define NPCX_SMBST_SDAST 6
1217 #define NPCX_SMBST_SLVSTP 7
1218 #define NPCX_SMBCST_BUSY 0
1219 #define NPCX_SMBCST_BB 1
1220 #define NPCX_SMBCST_MATCH 2
1221 #define NPCX_SMBCST_GCMATCH 3
1222 #define NPCX_SMBCST_TSDA 4
1223 #define NPCX_SMBCST_TGSCL 5
1224 #define NPCX_SMBCST_MATCHAF 6
1225 #define NPCX_SMBCST_ARPMATCH 7
1226 #define NPCX_SMBCST2_MATCHA1F 0
1227 #define NPCX_SMBCST2_MATCHA2F 1
1228 #define NPCX_SMBCST2_MATCHA3F 2
1229 #define NPCX_SMBCST2_MATCHA4F 3
1230 #define NPCX_SMBCST2_MATCHA5F 4
1231 #define NPCX_SMBCST2_MATCHA6F 5
1232 #define NPCX_SMBCST2_MATCHA7F 6
1233 #define NPCX_SMBCST2_INTSTS 7
1234 #define NPCX_SMBCST3_MATCHA8F 0
1235 #define NPCX_SMBCST3_MATCHA9F 1
1236 #define NPCX_SMBCST3_MATCHA10F 2
1237 #define NPCX_SMBCTL1_START 0
1238 #define NPCX_SMBCTL1_STOP 1
1239 #define NPCX_SMBCTL1_INTEN 2
1240 #define NPCX_SMBCTL1_ACK 4
1241 #define NPCX_SMBCTL1_GCMEN 5
1242 #define NPCX_SMBCTL1_NMINTE 6
1243 #define NPCX_SMBCTL1_STASTRE 7
1244 #define NPCX_SMBCTL2_ENABLE 0
1245 #define NPCX_SMBCTL2_SCLFRQ0_6_FIELD FIELD(1, 7)
1246 #define NPCX_SMBCTL3_ARPMEN 2
1247 #define NPCX_SMBCTL3_SCLFRQ7_8_FIELD FIELD(0, 2)
1248 #define NPCX_SMBCTL3_IDL_START 3
1249 #define NPCX_SMBCTL3_400K 4
1250 #define NPCX_SMBCTL3_BNK_SEL 5
1251 #define NPCX_SMBCTL3_SDA_LVL 6
1252 #define NPCX_SMBCTL3_SCL_LVL 7
1253 #define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
1254 #define NPCX_SMBCTL4_LVL_WE 7
1255 #define NPCX_SMBADDR1_SAEN 7
1256 #define NPCX_SMBADDR2_SAEN 7
1257 #define NPCX_SMBADDR3_SAEN 7
1258 #define NPCX_SMBADDR4_SAEN 7
1259 #define NPCX_SMBADDR5_SAEN 7
1260 #define NPCX_SMBADDR6_SAEN 7
1261 #define NPCX_SMBADDR7_SAEN 7
1262 #define NPCX_SMBADDR8_SAEN 7
1263 #define NPCX_SMBSEL_SMB4SEL 4
1264 #define NPCX_SMBSEL_SMB5SEL 5
1265 #define NPCX_SMBSEL_SMB6SEL 6
1266 #define NPCX_SMBFIF_CTS_RXF_TXE 1
1267 #define NPCX_SMBFIF_CTS_CLR_FIFO 6
1268 #define NPCX_SMBFIF_CTL_FIFO_EN 4
1269 #define NPCX_SMBRXF_STS_RX_THST 6
1270
1271 /* RX FIFO threshold */
1272 #define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
1273 #define NPCX_SMBRXF_CTL_LAST 7
1274
1275 /*
1276 * Internal 32-bit Timer (ITIM32) device registers
1277 */
1278 struct itim32_reg {
1279 volatile uint8_t reserved1;
1280 /* 0x001: Internal 32-bit Timer Prescaler */
1281 volatile uint8_t ITPRE32;
1282 volatile uint8_t reserved2[2];
1283 /* 0x004: Internal 32-bit Timer Control and Status */
1284 volatile uint8_t ITCTS32;
1285 volatile uint8_t reserved3[3];
1286 /* 0x008: Internal 32-Bit Timer Counter */
1287 volatile uint32_t ITCNT32;
1288 };
1289
1290 /*
1291 * Internal 64-bit Timer (ITIM54) device registers
1292 */
1293 struct itim64_reg {
1294 volatile uint8_t reserved1;
1295 /* 0x001: Internal 64-bit Timer Prescaler */
1296 volatile uint8_t ITPRE64;
1297 volatile uint8_t reserved2[2];
1298 /* 0x004: Internal 64-bit Timer Control and Status */
1299 volatile uint8_t ITCTS64;
1300 volatile uint8_t reserved3[3];
1301 /* 0x008: Internal 32-Bit Timer Counter */
1302 volatile uint32_t ITCNT64L;
1303 /* 0x00C: Internal 32-Bit Timer Counter */
1304 volatile uint32_t ITCNT64H;
1305 };
1306
1307 /* ITIM register fields */
1308 #define NPCX_ITCTSXX_TO_STS 0
1309 #define NPCX_ITCTSXX_TO_IE 2
1310 #define NPCX_ITCTSXX_TO_WUE 3
1311 #define NPCX_ITCTSXX_CKSEL 4
1312 #define NPCX_ITCTSXX_ITEN 7
1313
1314 /*
1315 * Tachometer (TACH) Sensor device registers
1316 */
1317 struct tach_reg {
1318 /* 0x000: Timer/Counter 1 */
1319 volatile uint16_t TCNT1;
1320 /* 0x002: Reload/Capture A */
1321 volatile uint16_t TCRA;
1322 /* 0x004: Reload/Capture B */
1323 volatile uint16_t TCRB;
1324 /* 0x006: Timer/Counter 2 */
1325 volatile uint16_t TCNT2;
1326 /* 0x008: Clock Prescaler */
1327 volatile uint8_t TPRSC;
1328 volatile uint8_t reserved1;
1329 /* 0x00A: Clock Unit Control */
1330 volatile uint8_t TCKC;
1331 volatile uint8_t reserved2;
1332 /* 0x00C: Timer Mode Control */
1333 volatile uint8_t TMCTRL;
1334 volatile uint8_t reserved3;
1335 /* 0x00E: Timer Event Control */
1336 volatile uint8_t TECTRL;
1337 volatile uint8_t reserved4;
1338 /* 0x010: Timer Event Clear */
1339 volatile uint8_t TECLR;
1340 volatile uint8_t reserved5;
1341 /* 0x012: Timer Interrupt Enable */
1342 volatile uint8_t TIEN;
1343 volatile uint8_t reserved6;
1344 /* 0x014: Compare A */
1345 volatile uint16_t TCPA;
1346 /* 0x016: Compare B */
1347 volatile uint16_t TCPB;
1348 /* 0x018: Compare Configuration */
1349 volatile uint8_t TCPCFG;
1350 volatile uint8_t reserved7;
1351 /* 0x01A: Timer Wake-Up Enable */
1352 volatile uint8_t TWUEN;
1353 volatile uint8_t reserved8;
1354 /* 0x01C: Timer Configuration */
1355 volatile uint8_t TCFG;
1356 volatile uint8_t reserved9;
1357 };
1358
1359 /* TACH register fields */
1360 #define NPCX_TCKC_LOW_PWR 7
1361 #define NPCX_TCKC_PLS_ACC_CLK 6
1362 #define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
1363 #define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
1364 #define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
1365 #define NPCX_TMCTRL_TAEN 5
1366 #define NPCX_TMCTRL_TBEN 6
1367 #define NPCX_TMCTRL_TAEDG 3
1368 #define NPCX_TMCTRL_TBEDG 4
1369 #define NPCX_TCFG_TADBEN 6
1370 #define NPCX_TCFG_TBDBEN 7
1371 #define NPCX_TECTRL_TAPND 0
1372 #define NPCX_TECTRL_TBPND 1
1373 #define NPCX_TECTRL_TCPND 2
1374 #define NPCX_TECTRL_TDPND 3
1375 #define NPCX_TECLR_TACLR 0
1376 #define NPCX_TECLR_TBCLR 1
1377 #define NPCX_TECLR_TCCLR 2
1378 #define NPCX_TECLR_TDCLR 3
1379 #define NPCX_TIEN_TAIEN 0
1380 #define NPCX_TIEN_TBIEN 1
1381 #define NPCX_TIEN_TCIEN 2
1382 #define NPCX_TIEN_TDIEN 3
1383 #define NPCX_TWUEN_TAWEN 0
1384 #define NPCX_TWUEN_TBWEN 1
1385 #define NPCX_TWUEN_TCWEN 2
1386 #define NPCX_TWUEN_TDWEN 3
1387
1388 /* Debug Interface registers */
1389 struct dbg_reg {
1390 /* 0x000: Debug Control */
1391 volatile uint8_t DBGCTRL;
1392 volatile uint8_t reserved1;
1393 /* 0x002: Debug Freeze Enable 1 */
1394 volatile uint8_t DBGFRZEN1;
1395 /* 0x003: Debug Freeze Enable 2 */
1396 volatile uint8_t DBGFRZEN2;
1397 /* 0x004: Debug Freeze Enable 3 */
1398 volatile uint8_t DBGFRZEN3;
1399 /* 0x005: Debug Freeze Enable 4 */
1400 volatile uint8_t DBGFRZEN4;
1401 };
1402 /* Debug Interface registers fields */
1403 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
1404
1405 /* PS/2 Interface registers */
1406 struct ps2_reg {
1407 /* 0x000: PS/2 Data */
1408 volatile uint8_t PSDAT;
1409 volatile uint8_t reserved1;
1410 /* 0x002: PS/2 Status */
1411 volatile uint8_t PSTAT;
1412 volatile uint8_t reserved2;
1413 /* 0x004: PS/2 Control */
1414 volatile uint8_t PSCON;
1415 volatile uint8_t reserved3;
1416 /* 0x006: PS/2 Output Signal */
1417 volatile uint8_t PSOSIG;
1418 volatile uint8_t reserved4;
1419 /* 0x008: PS/2 Input Signal */
1420 volatile uint8_t PSISIG;
1421 volatile uint8_t reserved5;
1422 /* 0x00A: PS/2 Interrupt Enable */
1423 volatile uint8_t PSIEN;
1424 volatile uint8_t reserved6;
1425 };
1426
1427 /* PS/2 Interface registers fields */
1428 #define NPCX_PSTAT_SOT 0
1429 #define NPCX_PSTAT_EOT 1
1430 #define NPCX_PSTAT_PERR 2
1431 #define NPCX_PSTAT_ACH FIELD(3, 3)
1432 #define NPCX_PSTAT_RFERR 6
1433
1434 #define NPCX_PSCON_EN 0
1435 #define NPCX_PSCON_XMT 1
1436 #define NPCX_PSCON_HDRV FIELD(2, 2)
1437 #define NPCX_PSCON_IDB FIELD(4, 3)
1438 #define NPCX_PSCON_WPUED 7
1439
1440 #define NPCX_PSOSIG_WDAT0 0
1441 #define NPCX_PSOSIG_WDAT1 1
1442 #define NPCX_PSOSIG_WDAT2 2
1443 #define NPCX_PSOSIG_CLK0 3
1444 #define NPCX_PSOSIG_CLK1 4
1445 #define NPCX_PSOSIG_CLK2 5
1446 #define NPCX_PSOSIG_WDAT3 6
1447 #define NPCX_PSOSIG_CLK3 7
1448 #define NPCX_PSOSIG_CLK(n) (((n) < 3) ? ((n) + 3) : 7)
1449 #define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
1450 #define NPCX_PSOSIG_CLK_MASK_ALL \
1451 (BIT(NPCX_PSOSIG_CLK0) | \
1452 BIT(NPCX_PSOSIG_CLK1) | \
1453 BIT(NPCX_PSOSIG_CLK2) | \
1454 BIT(NPCX_PSOSIG_CLK3))
1455
1456 #define NPCX_PSIEN_SOTIE 0
1457 #define NPCX_PSIEN_EOTIE 1
1458 #define NPCX_PSIEN_PS2_WUE 4
1459 #define NPCX_PSIEN_PS2_CLK_SEL 7
1460
1461 /* Flash Interface Unit (FIU) device registers */
1462 struct fiu_reg {
1463 volatile uint8_t reserved1;
1464 /* 0x001: Burst Configuration */
1465 volatile uint8_t BURST_CFG;
1466 /* 0x002: FIU Response Configuration */
1467 volatile uint8_t RESP_CFG;
1468 volatile uint8_t reserved2[17];
1469 /* 0x014: SPI Flash Configuration */
1470 volatile uint8_t SPI_FL_CFG;
1471 volatile uint8_t reserved3;
1472 /* 0x016: UMA Code Byte */
1473 volatile uint8_t UMA_CODE;
1474 /* 0x017: UMA Address Byte 0 */
1475 volatile uint8_t UMA_AB0;
1476 /* 0x018: UMA Address Byte 1 */
1477 volatile uint8_t UMA_AB1;
1478 /* 0x019: UMA Address Byte 2 */
1479 volatile uint8_t UMA_AB2;
1480 /* 0x01A: UMA Data Byte 0 */
1481 volatile uint8_t UMA_DB0;
1482 /* 0x01B: UMA Data Byte 1 */
1483 volatile uint8_t UMA_DB1;
1484 /* 0x01C: UMA Data Byte 2 */
1485 volatile uint8_t UMA_DB2;
1486 /* 0x01D: UMA Data Byte 3 */
1487 volatile uint8_t UMA_DB3;
1488 /* 0x01E: UMA Control and Status */
1489 volatile uint8_t UMA_CTS;
1490 /* 0x01F: UMA Extended Control and Status */
1491 volatile uint8_t UMA_ECTS;
1492 /* 0x020: UMA Data Bytes 0-3 */
1493 volatile uint32_t UMA_DB0_3;
1494 volatile uint8_t reserved4[2];
1495 /* 0x026: CRC Control Register */
1496 volatile uint8_t CRCCON;
1497 /* 0x027: CRC Entry Register */
1498 volatile uint8_t CRCENT;
1499 /* 0x028: CRC Initialization and Result Register */
1500 volatile uint32_t CRCRSLT;
1501 volatile uint8_t reserved5[4];
1502 /* 0x030: FIU Read Command */
1503 volatile uint8_t FIU_RD_CMD;
1504 volatile uint8_t reserved6;
1505 /* 0x032: FIU Dummy Cycles */
1506 volatile uint8_t FIU_DMM_CYC;
1507 /* 0x033: FIU Extended Configuration */
1508 volatile uint8_t FIU_EXT_CFG;
1509 #if defined(CONFIG_SOC_SERIES_NPCX9)
1510 /* 0x034: UMA address byte 0-3 */
1511 volatile uint32_t UMA_AB0_3;
1512 /* 0x038-0x3C */
1513 volatile uint8_t reserved8[5];
1514 /* 0x03D: SPI Device */
1515 volatile uint8_t SPI1_DEV;
1516 /* 0x03E-0x3F */
1517 volatile uint8_t reserved9[2];
1518 #elif defined(CONFIG_SOC_SERIES_NPCX4)
1519 /* 0x034: UMA address byte 0-3 */
1520 volatile uint32_t UMA_AB0_3;
1521 /* 0x038-0x3B */
1522 volatile uint8_t reserved8[4];
1523 /* 0x03C: SPI Device */
1524 volatile uint8_t SPI_DEV;
1525 /* 0x03D */
1526 volatile uint8_t reserved9;
1527 /* 0x03E */
1528 volatile uint8_t SPI_DEV_SIZE;
1529 /* 0x03F */
1530 volatile uint8_t reserved10;
1531 #endif
1532 };
1533
1534 /* FIU register fields */
1535 #define NPCX_BURST_CFG_SPI_DEV_SEL FIELD(4, 2)
1536 #define NPCX_RESP_CFG_IAD_EN 0
1537 #define NPCX_RESP_CFG_DEV_SIZE_EX 2
1538 #define NPCX_RESP_CFG_QUAD_EN 3
1539 #define NPCX_SPI_FL_CFG_RD_MODE FIELD(6, 2)
1540 #define NPCX_UMA_CTS_A_SIZE 3
1541 #define NPCX_UMA_CTS_C_SIZE 4
1542 #define NPCX_UMA_CTS_RD_WR 5
1543 #define NPCX_UMA_CTS_DEV_NUM 6
1544 #define NPCX_UMA_CTS_EXEC_DONE 7
1545 #define NPCX_UMA_ECTS_SW_CS0 0
1546 #define NPCX_UMA_ECTS_SW_CS1 1
1547 #define NPCX_UMA_ECTS_SEC_CS 2
1548 #define NPCX_UMA_ECTS_UMA_LOCK 3
1549 #define NPCX_UMA_ECTS_UMA_ADDR_SIZE FIELD(4, 3)
1550 #define NPCX_SPI1_DEV_FOUR_BADDR_CS10 6
1551 #define NPCX_SPI1_DEV_FOUR_BADDR_CS11 7
1552 #define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
1553 #define NPCX_FIU_EXT_CFG_SET_DMM_EN 2
1554 #define NPCX_FIU_EXT_CFG_SET_CMD_EN 1
1555 #define NPCX_SPI_DEV_NADDRB FIELD(5, 3)
1556
1557 #define NPCX_MSR_IE_CFG_UMA_BLOCK 3
1558
1559 /* UMA fields selections */
1560 #define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
1561 #define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE) /* No 1-Byte CMD field */
1562 #define UMA_FLD_WRITE BIT(NPCX_UMA_CTS_RD_WR) /* Write transaction */
1563 #define UMA_FLD_SHD_SL BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
1564 #define UMA_FLD_EXEC BIT(NPCX_UMA_CTS_EXEC_DONE)
1565
1566 #define UMA_FIELD_DATA_1 0x01
1567 #define UMA_FIELD_DATA_2 0x02
1568 #define UMA_FIELD_DATA_3 0x03
1569 #define UMA_FIELD_DATA_4 0x04
1570
1571 /* UMA code for transaction */
1572 #define UMA_CODE_CMD_ONLY (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
1573 #define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | \
1574 UMA_FLD_SHD_SL)
1575 #define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
1576 UMA_FLD_SHD_SL)
1577 #define UMA_CODE_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
1578 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1579 #define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1580 UMA_FLD_SHD_SL)
1581 #define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1582 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1583 #define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
1584 UMA_FLD_SHD_SL)
1585
1586 #define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1587 UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
1588 UMA_FLD_SHD_SL)
1589
1590 /* Platform Environment Control Interface (PECI) device registers */
1591 struct peci_reg {
1592 /* 0x000: PECI Control Status */
1593 volatile uint8_t PECI_CTL_STS;
1594 /* 0x001: PECI Read Length */
1595 volatile uint8_t PECI_RD_LENGTH;
1596 /* 0x002: PECI Address */
1597 volatile uint8_t PECI_ADDR;
1598 /* 0x003: PECI Command */
1599 volatile uint8_t PECI_CMD;
1600 /* 0x004: PECI Control 2 */
1601 volatile uint8_t PECI_CTL2;
1602 /* 0x005: PECI Index */
1603 volatile uint8_t PECI_INDEX;
1604 /* 0x006: PECI Index Data */
1605 volatile uint8_t PECI_IDATA;
1606 /* 0x007: PECI Write Length */
1607 volatile uint8_t PECI_WR_LENGTH;
1608 volatile uint8_t reserved1[3];
1609 /* 0x00B: PECI Write FCS */
1610 volatile uint8_t PECI_WR_FCS;
1611 /* 0x00C: PECI Read FCS */
1612 volatile uint8_t PECI_RD_FCS;
1613 /* 0x00D: PECI Assured Write FCS */
1614 volatile uint8_t PECI_AW_FCS;
1615 volatile uint8_t reserved2;
1616 /* 0x00F: PECI Transfer Rate */
1617 volatile uint8_t PECI_RATE;
1618 /* 0x010 - 0x04F: PECI Data In/Out */
1619 union {
1620 volatile uint8_t PECI_DATA_IN[64];
1621 volatile uint8_t PECI_DATA_OUT[64];
1622 };
1623 };
1624
1625 /* PECI register fields */
1626 #define NPCX_PECI_CTL_STS_START_BUSY 0
1627 #define NPCX_PECI_CTL_STS_DONE 1
1628 #define NPCX_PECI_CTL_STS_CRC_ERR 3
1629 #define NPCX_PECI_CTL_STS_ABRT_ERR 4
1630 #define NPCX_PECI_CTL_STS_AWFCS_EB 5
1631 #define NPCX_PECI_CTL_STS_DONE_EN 6
1632 #define NPCX_PECI_RATE_MAX_BIT_RATE FIELD(0, 5)
1633 #define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
1634 /* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
1635 #define PECI_MAX_BIT_RATE_VALID_MIN 0x05
1636 #define PECI_HIGH_SPEED_MIN_VAL 0x07
1637
1638 #define NPCX_PECI_RATE_EHSP 6
1639
1640 /* KBS (Keyboard Scan) device registers */
1641 struct kbs_reg {
1642 volatile uint8_t reserved1[4];
1643 /* 0x004: Keyboard Scan In */
1644 volatile uint8_t KBSIN;
1645 /* 0x005: Keyboard Scan In Pull-Up Enable */
1646 volatile uint8_t KBSINPU;
1647 /* 0x006: Keyboard Scan Out 0 */
1648 volatile uint16_t KBSOUT0;
1649 /* 0x008: Keyboard Scan Out 1 */
1650 volatile uint16_t KBSOUT1;
1651 /* 0x00A: Keyboard Scan Buffer Index */
1652 volatile uint8_t KBS_BUF_INDX;
1653 /* 0x00B: Keyboard Scan Buffer Data */
1654 volatile uint8_t KBS_BUF_DATA;
1655 /* 0x00C: Keyboard Scan Event */
1656 volatile uint8_t KBSEVT;
1657 /* 0x00D: Keyboard Scan Control */
1658 volatile uint8_t KBSCTL;
1659 /* 0x00E: Keyboard Scan Configuration Index */
1660 volatile uint8_t KBS_CFG_INDX;
1661 /* 0x00F: Keyboard Scan Configuration Data */
1662 volatile uint8_t KBS_CFG_DATA;
1663 };
1664
1665 /* KBS register fields */
1666 #define NPCX_KBSBUFINDX 0
1667 #define NPCX_KBSEVT_KBSDONE 0
1668 #define NPCX_KBSEVT_KBSERR 1
1669 #define NPCX_KBSCTL_START 0
1670 #define NPCX_KBSCTL_KBSMODE 1
1671 #define NPCX_KBSCTL_KBSIEN 2
1672 #define NPCX_KBSCTL_KBSINC 3
1673 #define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
1674 #define NPCX_KBSCFGINDX 0
1675 /* Index of 'Automatic Scan' configuration register */
1676 #define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */
1677 #define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */
1678 #define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */
1679 #define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */
1680 #define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */
1681
1682 /* SHI (Serial Host Interface) registers */
1683 struct shi_reg {
1684 volatile uint8_t reserved1;
1685 /* 0x001: SHI Configuration 1 */
1686 volatile uint8_t SHICFG1;
1687 /* 0x002: SHI Configuration 2 */
1688 volatile uint8_t SHICFG2;
1689 volatile uint8_t reserved2[2];
1690 /* 0x005: Event Enable */
1691 volatile uint8_t EVENABLE;
1692 /* 0x006: Event Status */
1693 volatile uint8_t EVSTAT;
1694 /* 0x007: SHI Capabilities */
1695 volatile uint8_t CAPABILITY;
1696 /* 0x008: Status */
1697 volatile uint8_t STATUS;
1698 volatile uint8_t reserved3;
1699 /* 0x00A: Input Buffer Status */
1700 volatile uint8_t IBUFSTAT;
1701 /* 0x00B: Output Buffer Status */
1702 volatile uint8_t OBUFSTAT;
1703 /* 0x00C: SHI Configuration 3 */
1704 volatile uint8_t SHICFG3;
1705 /* 0x00D: SHI Configuration 4 */
1706 volatile uint8_t SHICFG4;
1707 /* 0x00E: SHI Configuration 5 */
1708 volatile uint8_t SHICFG5;
1709 /* 0x00F: Event Status 2 */
1710 volatile uint8_t EVSTAT2;
1711 /* 0x010: Event Enable 2 */
1712 volatile uint8_t EVENABLE2;
1713 /* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
1714 volatile uint8_t SHICFG6;
1715 /* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */
1716 volatile uint8_t SBOBUF;
1717 volatile uint8_t reserved4[13];
1718 /* 0x20~0x9F: Output Buffer */
1719 volatile uint8_t OBUF[128];
1720 /* 0xA0~0x11F: Input Buffer */
1721 volatile uint8_t IBUF[128];
1722 };
1723
1724 /* SHI register fields */
1725 #define NPCX_SHICFG1_EN 0
1726 #define NPCX_SHICFG1_MODE 1
1727 #define NPCX_SHICFG1_WEN 2
1728 #define NPCX_SHICFG1_AUTIBF 3
1729 #define NPCX_SHICFG1_AUTOBE 4
1730 #define NPCX_SHICFG1_DAS 5
1731 #define NPCX_SHICFG1_CPOL 6
1732 #define NPCX_SHICFG1_IWRAP 7
1733 #define NPCX_SHICFG2_SIMUL 0
1734 #define NPCX_SHICFG2_BUSY 1
1735 #define NPCX_SHICFG2_ONESHOT 2
1736 #define NPCX_SHICFG2_SLWU 3
1737 #define NPCX_SHICFG2_REEN 4
1738 #define NPCX_SHICFG2_RESTART 5
1739 #define NPCX_SHICFG2_REEVEN 6
1740 #define NPCX_EVENABLE_OBEEN 0
1741 #define NPCX_EVENABLE_OBHEEN 1
1742 #define NPCX_EVENABLE_IBFEN 2
1743 #define NPCX_EVENABLE_IBHFEN 3
1744 #define NPCX_EVENABLE_EOREN 4
1745 #define NPCX_EVENABLE_EOWEN 5
1746 #define NPCX_EVENABLE_STSREN 6
1747 #define NPCX_EVENABLE_IBOREN 7
1748 #define NPCX_EVSTAT_OBE 0
1749 #define NPCX_EVSTAT_OBHE 1
1750 #define NPCX_EVSTAT_IBF 2
1751 #define NPCX_EVSTAT_IBHF 3
1752 #define NPCX_EVSTAT_EOR 4
1753 #define NPCX_EVSTAT_EOW 5
1754 #define NPCX_EVSTAT_STSR 6
1755 #define NPCX_EVSTAT_IBOR 7
1756 #define NPCX_STATUS_OBES 6
1757 #define NPCX_STATUS_IBFS 7
1758 #define NPCX_SHICFG3_OBUFLVLDIS 7
1759 #define NPCX_SHICFG4_IBUFLVLDIS 7
1760 #define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
1761 #define NPCX_SHICFG5_IBUFLVL2DIS 7
1762 #define NPCX_EVSTAT2_IBHF2 0
1763 #define NPCX_EVSTAT2_CSNRE 1
1764 #define NPCX_EVSTAT2_CSNFE 2
1765 #define NPCX_EVENABLE2_IBHF2EN 0
1766 #define NPCX_EVENABLE2_CSNREEN 1
1767 #define NPCX_EVENABLE2_CSNFEEN 2
1768 #define NPCX_SHICFG6_EBUFMD 0
1769 #define NPCX_SHICFG6_OBUF_SL 1
1770
1771 #define IBF_IBHF_EN_MASK (BIT(NPCX_EVENABLE_IBFEN) | BIT(NPCX_EVENABLE_IBHFEN))
1772
1773 /* SPIP (SPI Peripheral Interface) registers */
1774 struct spip_reg {
1775 /* 0x000: SPIP Data In/Out */
1776 volatile uint16_t SPIP_DATA;
1777 /* 0x002: SPIP Control 1 */
1778 volatile uint16_t SPIP_CTL1;
1779 /* 0x004: SPIP Status */
1780 volatile uint8_t SPIP_STAT;
1781 volatile uint8_t reserved1;
1782 };
1783
1784 #define NPCX_SPIP_CTL1_SPIEN 0
1785 #define NPCX_SPIP_CTL1_MOD 2
1786 #define NPCX_SPIP_CTL1_EIR 5
1787 #define NPCX_SPIP_CTL1_EIW 6
1788 #define NPCX_SPIP_CTL1_SCM 7
1789 #define NPCX_SPIP_CTL1_SCIDL 8
1790 #define NPCX_SPIP_CTL1_SCDV FIELD(9, 7)
1791 #define NPCX_SPIP_STAT_BSY 0
1792 #define NPCX_SPIP_STAT_RBF 1
1793
1794 /* Software-triggered Pheripheral Reset Controller Register */
1795 struct swrst_reg {
1796 /* 0x000: Software Reset Trigger */
1797 volatile uint16_t SWRST_TRG;
1798 volatile uint8_t reserved1[2];
1799 volatile uint32_t SWRST_CTL[4];
1800 };
1801
1802 /* Improved Inter Integrated Circuit (I3C) device registers */
1803 struct i3c_reg {
1804 /* 0x000: Controller Configuration */
1805 volatile uint32_t MCONFIG;
1806 /* 0x004: Target Configuration */
1807 volatile uint32_t CONFIG;
1808 /* 0x008: Target Status */
1809 volatile uint32_t STATUS;
1810 /* 0x00C: Target Control */
1811 volatile uint32_t CTRL;
1812 /* 0x010: Target Interrupt Enable Set */
1813 volatile uint32_t INTSET;
1814 /* 0x014: Target Interrupt Enable Clear */
1815 volatile uint32_t INTCLR;
1816 /* 0x018: Target Interrupt Masked */
1817 volatile uint32_t INTMASKED;
1818 /* 0x01C: Target Error and Warning */
1819 volatile uint32_t ERRWARN;
1820 /* 0x020: Target DMA Control */
1821 volatile uint32_t DMACTRL;
1822 /* 0x024-0x02B: reserved */
1823 volatile uint32_t reserved0[2];
1824 /* 0x02C: Target Data Control */
1825 volatile uint32_t DATACTRL;
1826 /* 0x030: Target Write Byte Data */
1827 volatile uint32_t WDATAB;
1828 /* 0x034: Target Write Byte Data as End */
1829 volatile uint32_t WDATABE;
1830 /* 0x038: Target Write Half-Word Data */
1831 volatile uint32_t WDATAH;
1832 /* 0x03C: Target Write Half-Word Data as End */
1833 volatile uint32_t WDATAHE;
1834 /* 0x040: Target Read Byte Data */
1835 volatile uint32_t RDATAB;
1836 /* 0x044: reserved */
1837 volatile uint32_t reserved1;
1838 /* 0x048: Target Read Half-Word Data */
1839 volatile uint32_t RDATAH;
1840 /* 0x04C-0x05B: reserved */
1841 volatile uint32_t reserved2[4];
1842 /* 0x05C: Target Capabilities 2 */
1843 volatile uint32_t CCAPABILITIES2;
1844 /* 0x060: Target Capabilities */
1845 volatile uint32_t CCAPABILITIES;
1846 /* 0x064: Target Dynamic Address */
1847 volatile uint32_t DYNADDR;
1848 /* 0x068: Target Maximum Limits */
1849 volatile uint32_t MAXLIMITS;
1850 /* 0x06C: Target Part Number */
1851 volatile uint32_t PARTNO;
1852 /* 0x070: Target ID Extension */
1853 volatile uint32_t IDEXT;
1854 /* 0x074: Target Vendor ID */
1855 volatile uint32_t VENDORID;
1856 /* 0x078: Target Timing Control Clock */
1857 volatile uint32_t TCCLOCK;
1858 /* 0x07C: Target Matching Address Index */
1859 volatile uint32_t MSGLAST;
1860 /* 0x080: reserved */
1861 volatile uint32_t reserved3;
1862 /* 0x084: Controller Control */
1863 volatile uint32_t MCTRL;
1864 /* 0x088: Controller Status */
1865 volatile uint32_t MSTATUS;
1866 /* 0x08C: IBI Registry and Rules */
1867 volatile uint32_t IBIRULES;
1868 /* 0x090: Controller Interrupt Enable Set */
1869 volatile uint32_t MINTSET;
1870 /* 0x094: Controller Interrupt Enable Clear */
1871 volatile uint32_t MINTCLR;
1872 /* 0x098: Controller Interrupt Masked */
1873 volatile uint32_t MINTMASKED;
1874 /* 0x09C: Controller Error and Warning */
1875 volatile uint32_t MERRWARN;
1876 /* 0x0A0: Controller DMA Control */
1877 volatile uint32_t MDMACTRL;
1878 /* 0x0A0-0x0AB: reserved */
1879 volatile uint32_t reserved4[2];
1880 /* 0x0AC: Controller Data Control */
1881 volatile uint32_t MDATACTRL;
1882 /* 0x0B0: Controller Write Byte Data */
1883 volatile uint32_t MWDATAB;
1884 /* 0x0B4: Controller Write Byte Data as End */
1885 volatile uint32_t MWDATABE;
1886 /* 0x0B8: Controller Write Half-Word Data */
1887 volatile uint32_t MWDATAH;
1888 /* 0x0BC: Controller Write Half-Word Data as End */
1889 volatile uint32_t MWDATAHE;
1890 /* 0x0C0: Controller Read Byte Data */
1891 volatile uint32_t MRDATAB;
1892 /* 0x0C4: reserved */
1893 volatile uint32_t reserved5;
1894 /* 0x0C8: Controller Read Half-Word Data */
1895 volatile uint32_t MRDATAH;
1896 /* 0x0CC-0x0D7: reserved */
1897 volatile uint32_t reserved6[3];
1898 /* 0x0D8: Start or Continue DDR Message */
1899 volatile uint32_t MWMSG_DDR;
1900 /* 0x0DC: Read DDR Message Data */
1901 volatile uint32_t MRMSG_DDR;
1902 /* 0x0E0: reserved */
1903 volatile uint32_t reserved7;
1904 /* 0x0E4: Controller Dynamic Address */
1905 volatile uint32_t MDYNADDR;
1906 /* 0x0E8-0x0FF reserved */
1907 volatile uint32_t reserved8[6];
1908 /* 0x100: Target Reset Recovery Time */
1909 volatile uint32_t RSTACTTIME;
1910 /* 0x104: reserved */
1911 volatile uint32_t reserved9;
1912 /* 0x108: Target HDR Command Byte */
1913 volatile uint32_t HDRCMD;
1914 /* 0x10C-0x113: reserved */
1915 volatile uint32_t reserved10[2];
1916 /* 0x114: Target Group Definition */
1917 volatile uint32_t GROUPDEF;
1918 /* 0x118: reserved */
1919 volatile uint32_t reserved11;
1920 /* 0x11C: Target Map Control 0 */
1921 volatile uint32_t MAPCTRL0;
1922 /* 0x120: Target Map Control 1 */
1923 volatile uint32_t MAPCTRL1;
1924 /* 0x124: Target Map Control 2 */
1925 volatile uint32_t MAPCTRL2;
1926 /* 0x128: Target Map Control 3 */
1927 volatile uint32_t MAPCTRL3;
1928 /* 0x12C: Target Map Control 4 */
1929 volatile uint32_t MAPCTRL4;
1930 /* 0x130: Target Map Control 5 */
1931 volatile uint32_t MAPCTRL5;
1932 /* 0x134: Target Map Control 6 */
1933 volatile uint32_t MAPCTRL6;
1934 /* 0x138: Target Map Control 7 */
1935 volatile uint32_t MAPCTRL7;
1936 /* 0x13C: Target Map Control 8 */
1937 volatile uint32_t MAPCTRL8;
1938 /* 0x140: Target Extended IBI Data 1 */
1939 volatile uint32_t IBIEXT1;
1940 /* 0x144: Target Extended IBI Data 2 */
1941 volatile uint32_t IBIEXT2;
1942 };
1943
1944 /* I3C controller register fields */
1945 #define NPCX_I3C_MCONFIG_CTRENA FIELD(0, 2)
1946 #define NPCX_I3C_MCONFIG_DISTO 3
1947 #define NPCX_I3C_MCONFIG_HKEEP FIELD(4, 2) /* Must be '11' */
1948 #define NPCX_I3C_MCONFIG_ODSTOP 6
1949 #define NPCX_I3C_MCONFIG_PPBAUD FIELD(8, 4)
1950 #define NPCX_I3C_MCONFIG_PPLOW FIELD(12, 4)
1951 #define NPCX_I3C_MCONFIG_ODBAUD FIELD(16, 8)
1952 #define NPCX_I3C_MCONFIG_ODHPP 24
1953 #define NPCX_I3C_MCONFIG_SKEW FIELD(25, 3)
1954 #define NPCX_I3C_MCONFIG_I2CBAUD FIELD(28, 4)
1955 #define NPCX_I3C_MCTRL_REQUEST FIELD(0, 3)
1956 #define NPCX_I3C_MCTRL_TYPE FIELD(4, 2)
1957 #define NPCX_I3C_MCTRL_IBIRESP FIELD(6, 2)
1958 #define NPCX_I3C_MCTRL_DIR 8
1959 #define NPCX_I3C_MCTRL_ADDR FIELD(9, 7)
1960 #define NPCX_I3C_MCTRL_RDTERM FIELD(16, 8)
1961 #define NPCX_I3C_MSTATUS_STATE FIELD(0, 3)
1962 #define NPCX_I3C_MSTATUS_BETWEEN 4
1963 #define NPCX_I3C_MSTATUS_NACKED 5
1964 #define NPCX_I3C_MSTATUS_IBITYPE FIELD(6, 2)
1965 #define NPCX_I3C_MSTATUS_TGTSTART 8
1966 #define NPCX_I3C_MSTATUS_MCTRLDONE 9
1967 #define NPCX_I3C_MSTATUS_COMPLETE 10
1968 #define NPCX_I3C_MSTATUS_RXPEND 11
1969 #define NPCX_I3C_MSTATUS_TXNOTFULL 12
1970 #define NPCX_I3C_MSTATUS_IBIWON 13
1971 #define NPCX_I3C_MSTATUS_ERRWARN 15
1972 #define NPCX_I3C_MSTATUS_NOWCNTLR 19
1973 #define NPCX_I3C_MSTATUS_IBIADDR FIELD(24, 7)
1974 #define NPCX_I3C_IBIRULES_MSB0 30
1975 #define NPCX_I3C_IBIRULES_NOBYTE 31
1976 #define NPCX_I3C_MINTSET_TGTSTART 8
1977 #define NPCX_I3C_MINTSET_MCTRLDONE 9
1978 #define NPCX_I3C_MINTSET_COMPLETE 10
1979 #define NPCX_I3C_MINTSET_RXPEND 11
1980 #define NPCX_I3C_MINTSET_TXNOTFULL 12
1981 #define NPCX_I3C_MINTSET_IBIWON 13
1982 #define NPCX_I3C_MINTSET_ERRWARN 15
1983 #define NPCX_I3C_MINTSET_NOWCNTLR 19
1984 #define NPCX_I3C_MINTCLR_TGTSTART 8
1985 #define NPCX_I3C_MINTCLR_MCTRLDONE 9
1986 #define NPCX_I3C_MINTCLR_COMPLETE 10
1987 #define NPCX_I3C_MINTCLR_RXPEND 11
1988 #define NPCX_I3C_MINTCLR_TXNOTFULL 12
1989 #define NPCX_I3C_MINTCLR_IBIWON 13
1990 #define NPCX_I3C_MINTCLR_ERRWARN 15
1991 #define NPCX_I3C_MINTCLR_NOWCNTLR 19
1992 #define NPCX_I3C_MINTMASKED_NOWCNTLR 19
1993 #define NPCX_I3C_MDATACTRL_FLUSHTB 0
1994 #define NPCX_I3C_MDATACTRL_FLUSHFB 1
1995 #define NPCX_I3C_MDATACTRL_UNLOCK 3
1996 #define NPCX_I3C_MDATACTRL_TXTRIG FIELD(4, 2)
1997 #define NPCX_I3C_MDATACTRL_RXTRIG FIELD(6, 2)
1998 #define NPCX_I3C_MDATACTRL_TXCOUNT FIELD(16, 5)
1999 #define NPCX_I3C_MDATACTRL_RXCOUNT FIELD(24, 5)
2000 #define NPCX_I3C_MDATACTRL_TXFULL 30
2001 #define NPCX_I3C_MDATACTRL_RXEMPTY 31
2002 #define NPCX_I3C_MERRWARN_NACK 2
2003 #define NPCX_I3C_MERRWARN_WRABT 3
2004 #define NPCX_I3C_MERRWARN_TERM 4
2005 #define NPCX_I3C_MERRWARN_HPAR 9
2006 #define NPCX_I3C_MERRWARN_HCRC 10
2007 #define NPCX_I3C_MERRWARN_OREAD 16
2008 #define NPCX_I3C_MERRWARN_OWRITE 17
2009 #define NPCX_I3C_MERRWARN_MSGERR 18
2010 #define NPCX_I3C_MERRWARN_INVERQ 19
2011 #define NPCX_I3C_MERRWARN_TIMEOUT 20
2012 #define NPCX_I3C_MDMACTRL_DMAFB FIELD(0, 2)
2013 #define NPCX_I3C_MDMACTRL_DMATB FIELD(2, 2)
2014
2015 /* I3C target register fields */
2016 #define NPCX_I3C_CONFIG_TGTENA 0
2017 #define NPCX_I3C_CONFIG_MATCHSS 2
2018 #define NPCX_I3C_CONFIG_S0IGNORE 3
2019 #define NPCX_I3C_CONFIG_IDRAND 8
2020 #define NPCX_I3C_CONFIG_OFFLINE 9
2021 #define NPCX_I3C_CONFIG_HDRCMD FIELD(10, 2)
2022 #define NPCX_I3C_CONFIG_BAMATCH FIELD(16, 7)
2023 #define NPCX_I3C_CONFIG_SADDR FIELD(25, 7)
2024 #define NPCX_I3C_STATUS_STNOTSTOP 0
2025 #define NPCX_I3C_STATUS_STMSG 1
2026 #define NPCX_I3C_STATUS_STCCCH 2
2027 #define NPCX_I3C_STATUS_STREQRD 3
2028 #define NPCX_I3C_STATUS_STREQWR 4
2029 #define NPCX_I3C_STATUS_STDAA 5
2030 #define NPCX_I3C_STATUS_STHDR 6
2031 #define NPCX_I3C_STATUS_START 8
2032 #define NPCX_I3C_STATUS_MATCHED 9
2033 #define NPCX_I3C_STATUS_STOP 10
2034 #define NPCX_I3C_STATUS_RXPEND 11
2035 #define NPCX_I3C_STATUS_TXNOTFULL 12
2036 #define NPCX_I3C_STATUS_DACHG 13
2037 #define NPCX_I3C_STATUS_CCC 14
2038 #define NPCX_I3C_STATUS_ERRWARN 15
2039 #define NPCX_I3C_STATUS_HDRMATCH 16
2040 #define NPCX_I3C_STATUS_CHANDLED 17
2041 #define NPCX_I3C_STATUS_EVENT 18
2042 #define NPCX_I3C_STATUS_TGTRST 19
2043 #define NPCX_I3C_STATUS_EVDET FIELD(20, 2)
2044 #define NPCX_I3C_STATUS_IBIDIS 24
2045 #define NPCX_I3C_STATUS_MRDIS 25
2046 #define NPCX_I3C_STATUS_HJDIS 27
2047 #define NPCX_I3C_STATUS_ACTSTATE FIELD(28, 2)
2048 #define NPCX_I3C_STATUS_TIMECTRL FIELD(30, 2)
2049 #define NPCX_I3C_CTRL_EVENT FIELD(0, 2)
2050 #define NPCX_I3C_CTRL_EXTDATA 3
2051 #define NPCX_I3C_CTRL_MAPIDX FIELD(4, 4)
2052 #define NPCX_I3C_CTRL_IBIDATA FIELD(8, 8)
2053 #define NPCX_I3C_CTRL_PENDINT FIELD(16, 4)
2054 #define NPCX_I3C_CTRL_ACTSTATE FIELD(20, 2)
2055 #define NPCX_I3C_CTRL_VENDINFO FIELD(24, 8)
2056 #define NPCX_I3C_INTSET_START 8
2057 #define NPCX_I3C_INTSET_MATCHED 9
2058 #define NPCX_I3C_INTSET_STOP 10
2059 #define NPCX_I3C_INTSET_RXPEND 11
2060 #define NPCX_I3C_INTSET_TXNOTFULL 12
2061 #define NPCX_I3C_INTSET_DACHG 13
2062 #define NPCX_I3C_INTSET_CCC 14
2063 #define NPCX_I3C_INTSET_ERRWARN 15
2064 #define NPCX_I3C_INTSET_HDRMATCH 16
2065 #define NPCX_I3C_INTSET_CHANDLED 17
2066 #define NPCX_I3C_INTSET_EVENT 18
2067 #define NPCX_I3C_INTSET_TGTRST 19
2068 #define NPCX_I3C_INTCLR_START 8
2069 #define NPCX_I3C_INTCLR_MATCHED 9
2070 #define NPCX_I3C_INTCLR_STOP 10
2071 #define NPCX_I3C_INTCLR_RXPEND 11
2072 #define NPCX_I3C_INTCLR_TXNOTFULL 12
2073 #define NPCX_I3C_INTCLR_DACHG 13
2074 #define NPCX_I3C_INTCLR_CCC 14
2075 #define NPCX_I3C_INTCLR_ERRWARN 15
2076 #define NPCX_I3C_INTCLR_HDRMATCH 16
2077 #define NPCX_I3C_INTCLR_CHANDLED 17
2078 #define NPCX_I3C_INTCLR_EVENT 18
2079 #define NPCX_I3C_INTCLR_TGTRST 19
2080 #define NPCX_I3C_INTMASKED_START 8
2081 #define NPCX_I3C_INTMASKED_MATCHED 9
2082 #define NPCX_I3C_INTMASKED_STOP 10
2083 #define NPCX_I3C_INTMASKED_RXPEND 11
2084 #define NPCX_I3C_INTMASKED_TXNOTFULL 12
2085 #define NPCX_I3C_INTMASKED_DACHG 13
2086 #define NPCX_I3C_INTMASKED_CCC 14
2087 #define NPCX_I3C_INTMASKED_ERRWARN 15
2088 #define NPCX_I3C_INTMASKED_HDRMATCH 16
2089 #define NPCX_I3C_INTMASKED_CHANDLED 17
2090 #define NPCX_I3C_INTMASKED_EVENT 18
2091 #define NPCX_I3C_INTMASKED_TGTRST 19
2092 #define NPCX_I3C_ERRWARN_ORUN 0
2093 #define NPCX_I3C_ERRWARN_URUN 1
2094 #define NPCX_I3C_ERRWARN_URUNNACK 2
2095 #define NPCX_I3C_ERRWARN_TERM 3
2096 #define NPCX_I3C_ERRWARN_INVSTART 4
2097 #define NPCX_I3C_ERRWARN_SPAR 8
2098 #define NPCX_I3C_ERRWARN_HPAR 9
2099 #define NPCX_I3C_ERRWARN_HCRC 10
2100 #define NPCX_I3C_ERRWARN_S0S1 11
2101 #define NPCX_I3C_ERRWARN_OREAD 16
2102 #define NPCX_I3C_ERRWARN_OWRITE 17
2103 #define NPCX_I3C_DMACTRL_DMAFB FIELD(0, 2)
2104 #define NPCX_I3C_DMACTRL_DMATB FIELD(2, 2)
2105 #define NPCX_I3C_DATACTRL_FLUSHTB 0
2106 #define NPCX_I3C_DATACTRL_FLUSHFB 1
2107 #define NPCX_I3C_DATACTRL_UNLOCK 3
2108 #define NPCX_I3C_DATACTRL_TXTRIG FIELD(4, 2)
2109 #define NPCX_I3C_DATACTRL_RXTRIG FIELD(6, 2)
2110 #define NPCX_I3C_DATACTRL_TXCOUNT FIELD(16, 6)
2111 #define NPCX_I3C_DATACTRL_RXCOUNT FIELD(24, 6)
2112 #define NPCX_I3C_DATACTRL_TXFULL 30
2113 #define NPCX_I3C_DATACTRL_RXEMPTY 31
2114 #define NPCX_I3C_WDATAB_DATA FIELD(0, 8)
2115 #define NPCX_I3C_WDATAB_END_B 8
2116 #define NPCX_I3C_WDATAB_END_A 16
2117 #define NPCX_I3C_WDATABE_DATA FIELD(0, 8)
2118 #define NPCX_I3C_WDATAH_DATA0 FIELD(0, 8)
2119 #define NPCX_I3C_WDATAH_DATA1 FIELD(8, 8)
2120 #define NPCX_I3C_WDATAH_END 16
2121 #define NPCX_I3C_WDATAHE_DATA0 FIELD(0, 8)
2122 #define NPCX_I3C_WDATAHE_DATA1 FIELD(8, 8)
2123 #define NPCX_I3C_RDATAB_DATA FIELD(0, 8)
2124 #define NPCX_I3C_RDATAH_DATA0 FIELD(0, 8)
2125 #define NPCX_I3C_RDATAH_DATA1 FIELD(8, 8)
2126 #define NPCX_I3C_CAPABILITIES2_MAPCNT FIELD(0, 4)
2127 #define NPCX_I3C_CAPABILITIES2_I2C10B 4
2128 #define NPCX_I3C_CAPABILITIES2_I2CRST 5
2129 #define NPCX_I3C_CAPABILITIES2_I2CDEVID 6
2130 #define NPCX_I3C_CAPABILITIES2_DATA32 7
2131 #define NPCX_I3C_CAPABILITIES2_IBIEXT 8
2132 #define NPCX_I3C_CAPABILITIES2_IBIXREG 9
2133 #define NPCX_I3C_CAPABILITIES2_SMLANE FIELD(12, 2)
2134 #define NPCX_I3C_CAPABILITIES2_V1_1 16
2135 #define NPCX_I3C_CAPABILITIES2_TGTRST 17
2136 #define NPCX_I3C_CAPABILITIES2_GROUP FIELD(18, 2)
2137 #define NPCX_I3C_CAPABILITIES2_AASA 21
2138 #define NPCX_I3C_CAPABILITIES2_SSTSUB 22
2139 #define NPCX_I3C_CAPABILITIES2_SSTWR 23
2140 #define NPCX_I3C_CAPABILITIES_IDENA FIELD(0, 2)
2141 #define NPCX_I3C_CAPABILITIES_IDREG FIELD(2, 4)
2142 #define NPCX_I3C_CAPABILITIES_HDRSUPP FIELD(6, 3)
2143 #define NPCX_I3C_CAPABILITIES_CNTLR 9
2144 #define NPCX_I3C_CAPABILITIES_SADDR FIELD(10, 2)
2145 #define NPCX_I3C_CAPABILITIES_CCCHANDLE FIELD(12, 4)
2146 #define NPCX_I3C_CAPABILITIES_IBI_MR_HJ FIELD(16, 5)
2147 #define NPCX_I3C_CAPABILITIES_TIMECTRL 21
2148 #define NPCX_I3C_CAPABILITIES_EXTFIFO FIELD(23, 3)
2149 #define NPCX_I3C_CAPABILITIES_FIFOTX FIELD(26, 2)
2150 #define NPCX_I3C_CAPABILITIES_FIFORX FIELD(28, 2)
2151 #define NPCX_I3C_CAPABILITIES_INT 30
2152 #define NPCX_I3C_CAPABILITIES_DMA 31
2153 #define NPCX_I3C_DYNADDR_DAVALID 0
2154 #define NPCX_I3C_DYNADDR_DADDR FIELD(1, 7)
2155 #define NPCX_I3C_DYNADDR_CAUSE FIELD(8, 3)
2156 #define NPCX_I3C_MAXLIMITS_MAXRD FIELD(0, 12)
2157 #define NPCX_I3C_MAXLIMITS_MAXWR FIELD(16, 12)
2158 #define NPCX_I3C_IDEXT_DCR FIELD(8, 8)
2159 #define NPCX_I3C_IDEXT_BCR FIELD(16, 8)
2160 #define NPCX_I3C_VENDORID_VID FIELD(0, 15)
2161 #define NPCX_I3C_TCCLOCK_ACCURACY FIELD(0, 8)
2162 #define NPCX_I3C_TCCLOCK_FREQ FIELD(8, 8)
2163 #define NPCX_I3C_MSGLAST_MAPLAST FIELD(0, 4)
2164 #define NPCX_I3C_MSGLAST_LASTSTATIC 4
2165 #define NPCX_I3C_MSGLAST_LASTGROUP 5
2166 #define NPCX_I3C_MSGLAST_LASTMODE FIELD(6, 2)
2167 #define NPCX_I3C_MSGLAST_MAPLASTM1 FIELD(8, 4)
2168 #define NPCX_I3C_MSGLAST_LASTGROUPM1 13
2169 #define NPCX_I3C_MSGLAST_LASTMODE1 FIELD(14, 2)
2170 #define NPCX_I3C_MSGLAST_MAPLASTM2 FIELD(16, 4)
2171 #define NPCX_I3C_MSGLAST_LASTGROUPM2 21
2172 #define NPCX_I3C_MSGLAST_LASTMODE2 FIELD(22, 2)
2173 #define NPCX_I3C_RSTACTTIME_PERRSTTIM FIELD(0, 8)
2174 #define NPCX_I3C_RSTACTTIME_SYSRSTTIM FIELD(8, 8)
2175 #define NPCX_I3C_HDRCMD_CMD0 FIELD(0, 8)
2176 #define NPCX_I3C_HDRCMD_OVFL 30
2177 #define NPCX_I3C_HDRCMD_NEWCMD 31
2178 #define NPCX_I3C_GROUPDEF_GRP0ENA 0
2179 #define NPCX_I3C_GROUPDEF_GRP0DA FIELD(1, 7)
2180 #define NPCX_I3C_GROUPDEF_GRP1ENA 8
2181 #define NPCX_I3C_GROUPDEF_GRP1DA FIELD(9, 7)
2182 #define NPCX_I3C_GROUPDEF_GRP2ENA 16
2183 #define NPCX_I3C_GROUPDEF_GRP2DA FIELD(17, 7)
2184 #define NPCX_I3C_MAPCTRL0_ENA 0
2185 #define NPCX_I3C_MAPCTRL0_DA FIELD(1, 7)
2186 #define NPCX_I3C_MAPCTRL0_CAUSE FIELD(8, 3)
2187 #define NPCX_I3C_MAPCTRLn_ENA 0
2188 #define NPCX_I3C_MAPCTRLn_ADDR FIELD(1, 7)
2189 #define NPCX_I3C_MAPCTRLn_MAPSA 8
2190 #define NPCX_I3C_MAPCTRLn_NACK 12
2191 #define NPCX_I3C_MAPCTRLn_AUTO 13
2192 #define NPCX_I3C_MAPCTRLn_SLOT_PID FIELD(14, 5)
2193 #define NPCX_I3C_IBIEXT1_CNT FIELD(0, 3)
2194 #define NPCX_I3C_IBIEXT1_EXT1 FIELD(8, 8)
2195 #define NPCX_I3C_IBIEXT1_EXT2 FIELD(16, 8)
2196 #define NPCX_I3C_IBIEXT1_EXT3 FIELD(24, 8)
2197 #define NPCX_I3C_IBIEXT2_EXT4 FIELD(0, 8)
2198 #define NPCX_I3C_IBIEXT2_EXT5 FIELD(8, 8)
2199 #define NPCX_I3C_IBIEXT2_EXT6 FIELD(16, 8)
2200 #define NPCX_I3C_IBIEXT2_EXT7 FIELD(24, 8)
2201
2202 /* MDMA Controller registers */
2203 struct mdma_reg {
2204 /* Channel 0 */
2205 /* 0x000: Channel 0 Control */
2206 volatile uint32_t MDMA_CTL0;
2207 /* 0x004: Channel 0 Source Base Address */
2208 volatile uint32_t MDMA_SRCB0;
2209 /* 0x008: Channel 0 Destination Base Address */
2210 volatile uint32_t MDMA_DSTB0;
2211 /* 0x00C: Channel 0 Transfer Count */
2212 volatile uint32_t MDMA_TCNT0;
2213 /* 0x010: reserved1 */
2214 volatile uint32_t reserved1;
2215 /* 0x014: Channel 0 Current Destination */
2216 volatile uint32_t MDMA_CDST0;
2217 /* 0x018: Channel 0 Current Transfer Count */
2218 volatile uint32_t MDMA_CTCNT0;
2219 /* 0x01C: reserved2 */
2220 volatile uint32_t reserved2;
2221
2222 /* Channel 1 */
2223 /* 0x020: Channel 1 Control */
2224 volatile uint32_t MDMA_CTL1;
2225 /* 0x024: Channel 1 Source Base Address */
2226 volatile uint32_t MDMA_SRCB1;
2227 /* 0x028: Channel 1 Destination Base Address */
2228 volatile uint32_t MDMA_DSTB1;
2229 /* 0x02C: Channel 1 Transfer Count */
2230 volatile uint32_t MDMA_TCNT1;
2231 /* 0x030: Channel 1 Current Source */
2232 volatile uint32_t MDMA_CSRC1;
2233 /* 0x034: reserved3 */
2234 volatile uint32_t reserved3;
2235 /* 0x038: Channel 1 Current Transfer Count */
2236 volatile uint32_t MDMA_CTCNT1;
2237 };
2238
2239 /* MDMA register fields */
2240 #define NPCX_MDMA_CTL_MDMAEN 0
2241 #define NPCX_MDMA_CTL_MPD 1
2242 #define NPCX_MDMA_CTL_SIEN 8
2243 #define NPCX_MDMA_CTL_MPS 14
2244 #define NPCX_MDMA_CTL_TC 18
2245
2246 /* Channel 0/1 Transfer Count Register (MDMA_TCNT0/MDMA_TCNT1) */
2247 #define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 13)
2248
2249 /* Channel 0/1 Current Transfer Count Register (MDMA_CTCNT0/MDMA_CTCNT1) */
2250 #define NPCX_MDMA_CTCNT_CURRENT_TFR_CNT FIELD(0, 13)
2251
2252 #endif /* _NUVOTON_NPCX_REG_DEF_H */
2253
