1 /**************************************************************************//** 2 * @file pdma_reg.h 3 * @version V1.00 4 * @brief PDMA register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_REG_H__ 10 #define __PDMA_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/ 24 /** 25 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) 26 Memory Mapped Structure for PDMA Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var DSCT_T::CTL 35 * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[1:0] |OPMODE |PDMA Operation Mode Selection 40 * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. 41 * | | |01 = Basic mode: The descriptor table only has one task 42 * | | |When this task is finished, PDMA_INTSTS[1] will be asserted. 43 * | | |10 = Scatter-gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCTn_NEXT register; PDMA controller will ignore this task, then load the next task to execute. 44 * | | |11 = Reserved. 45 * | | |Note: Before filling new transfer task in the Descriptor Table, user must check PDMA_INTSTS[1] to make sure the current task is complete. 46 * |[2] |TXTYPE |Transfer Type 47 * | | |0 = Burst transfer type. 48 * | | |1 = Single transfer type. 49 * |[6:4] |BURSIZE |Burst Size 50 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. 51 * | | |000 = 128 Transfers. 52 * | | |001 = 64 Transfers. 53 * | | |010 = 32 Transfers. 54 * | | |011 = 16 Transfers. 55 * | | |100 = 8 Transfers. 56 * | | |101 = 4 Transfers. 57 * | | |110 = 2 Transfers. 58 * | | |111 = 1 Transfers. 59 * | | |Note: This field is only useful in burst transfer type. 60 * |[7] |TBINTDIS |Table Interrupt Disable Bit 61 * | | |This field can be used to decide whether to enable table interrupt or not 62 * | | |If the TBINTDIS bit is 1 it will not generates TDIFn(PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task. 63 * | | |0 = Table interrupt Enabled. 64 * | | |1 = Table interrupt Disabled. 65 * | | |Note: This function only for Scatter-gather mode. 66 * |[9:8] |SAINC |Source Address Increment 67 * | | |This field is used to set the source address increment size. 68 * | | |11 = No increment (fixed address). 69 * | | |Others = Increment and size is depended on TXWIDTH selection. 70 * | | |Note: The fixed address function does not support in memory to memory transfer type. 71 * |[11:10] |DAINC |Destination Address Increment 72 * | | |This field is used to set the destination address increment size. 73 * | | |11 = No increment (fixed address). 74 * | | |Others = Increment and size is depended on TXWIDTH selection. 75 * | | |Note: The fixed address function does not support in memory to memory transfer type. 76 * |[13:12] |TXWIDTH |Transfer Width Selection 77 * | | |This field is used for transfer width. 78 * | | |00 = One byte (8 bit) is transferred for every operation. 79 * | | |01= One half-word (16 bit) is transferred for every operation. 80 * | | |10 = One word (32-bit) is transferred for every operation. 81 * | | |11 = Reserved. 82 * | | |Note: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection 83 * |[31:16] |TXCNT |Transfer Count 84 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. 85 * | | |Note: When PDMA finishes each transfer data, this field will be decreased immediately. 86 * @var DSCT_T::SA 87 * Offset: 0x04 Source Address Register of PDMA Channel n 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[31:0] |SA |PDMA Transfer Source Address 92 * | | |This field indicates a 32-bit source address of PDMA controller. 93 * @var DSCT_T::DA 94 * Offset: 0x08 Destination Address Register of PDMA Channel n 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[31:0] |DA |PDMA Transfer Destination Address 99 * | | |This field indicates a 32-bit destination address of PDMA controller. 100 * @var DSCT_T::NEXT 101 * Offset: 0x0C Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[15:0] |NEXT |PDMA Next Descriptor Table Offset 106 * | | |This field indicates the offset of the next descriptor table address in system memory. 107 * | | |Write Operation: 108 * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. 109 * | | |Read Operation: 110 * | | |When operating in Scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. 111 * | | |Note 1: The descriptor table address must be word boundary. 112 * | | |Note 2: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete. 113 * |[31:16] |EXENEXT |PDMA Execution Next Descriptor Table Offset 114 * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. 115 * | | |Note: Write operation is useless in this field. 116 */ 117 __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n */ 118 __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ 119 __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ 120 __IO uint32_t NEXT; /*!< [0x000c] Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n */ 121 122 } DSCT_T; 123 124 typedef struct 125 { 126 127 128 /** 129 * @var PDMA_T::CURSCAT 130 * Offset: 0x100 Current Scatter-gather Descriptor Table Address of PDMA Channel n 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[31:0] |CURADDR |PDMA Current Description Address (Read Only) 135 * | | |This field indicates a 32-bit current external description address of PDMA controller. 136 * | | |Note: This field is read only and used for Scatter-gather mode only to indicate the current external description address. 137 * @var PDMA_T::CHCTL 138 * Offset: 0x400 PDMA Channel Control Register 139 * --------------------------------------------------------------------------------------------------- 140 * |Bits |Field |Descriptions 141 * | :----: | :----: | :---- | 142 * |[15:0] |CHENn |PDMA Channel Enable Bits 143 * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. 144 * | | |0 = PDMA channel [n] Disabled. 145 * | | |1 = PDMA channel [n] Enabled. 146 * | | |Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 147 * @var PDMA_T::PAUSE 148 * Offset: 0x404 PDMA Transfer Pause Control Register 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[15:0] |PAUSEn |PDMA Channel n Transfer Pause Control (Write Only) 153 * | | |User can set PAUSEn bit field to pause PDMA transfer 154 * | | |When user sets PAUSEn bit, PDMA will pause the on-going transfer, then clear channel enable bit CHENn(PDMA_CHCTL [n], n=0,1..15) and clear request active flag(PDMA_TRGSTS[n:0], n=0,1..15) 155 * | | |If the paused channel is re-enabled again, the remaining transfers will be processed. 156 * | | |0 = No effect. 157 * | | |1 = Pause PDMA channel n transfer. 158 * @var PDMA_T::SWREQ 159 * Offset: 0x408 PDMA Software Request Register 160 * --------------------------------------------------------------------------------------------------- 161 * |Bits |Field |Descriptions 162 * | :----: | :----: | :---- | 163 * |[15:0] |SWREQn |PDMA Software Request (Write Only) 164 * | | |Set this bit to 1 to generate a software request to PDMA [n]. 165 * | | |0 = No effect. 166 * | | |1 = Generate a software request. 167 * | | |Note 1: User can read PDMA_TRGSTS register to know which channel is on active 168 * | | |Active flag may be triggered by software request or peripheral request. 169 * | | |Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored. 170 * @var PDMA_T::TRGSTS 171 * Offset: 0x40C PDMA Channel Request Status Register 172 * --------------------------------------------------------------------------------------------------- 173 * |Bits |Field |Descriptions 174 * | :----: | :----: | :---- | 175 * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) 176 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral 177 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. 178 * | | |0 = PDMA Channel n has no request. 179 * | | |1 = PDMA Channel n has a request. 180 * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 181 * @var PDMA_T::PRISET 182 * Offset: 0x410 PDMA Fixed Priority Setting Register 183 * --------------------------------------------------------------------------------------------------- 184 * |Bits |Field |Descriptions 185 * | :----: | :----: | :---- | 186 * |[15:0] |FPRISETn |PDMA Fixed Priority Setting 187 * | | |Set this bit to 1 to enable fixed priority level. 188 * | | |Write Operation: 189 * | | |0 = No effect. 190 * | | |1 = Set PDMA channel [n] to fixed priority channel. 191 * | | |Read Operation: 192 * | | |0 = Corresponding PDMA channel is round-robin priority. 193 * | | |1 = Corresponding PDMA channel is fixed priority. 194 * | | |Note: This field is only set to fixed priority. To clear fixed priority, use PDMA_PRICLR register. 195 * @var PDMA_T::PRICLR 196 * Offset: 0x414 PDMA Fixed Priority Clear Register 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Bits (Write Only) 201 * | | |Set this bit to 1 to clear fixed priority level. 202 * | | |0 = No effect. 203 * | | |1 = Clear PDMA channel [n] fixed priority setting. 204 * | | |Note: User can read PDMA_PRISET register to know the channel priority. 205 * @var PDMA_T::INTEN 206 * Offset: 0x418 PDMA Interrupt Enable Register 207 * --------------------------------------------------------------------------------------------------- 208 * |Bits |Field |Descriptions 209 * | :----: | :----: | :---- | 210 * |[15:0] |INTENn |PDMA Interrupt Enable Bits 211 * | | |This field is used to enable PDMA channel[n] interrupt. 212 * | | |0 = PDMA channel n interrupt Disabled. 213 * | | |1 = PDMA channel n interrupt Enabled. 214 * | | |Note: The interrupt flag is time-out, abort, transfer done and align. 215 * @var PDMA_T::INTSTS 216 * Offset: 0x41C PDMA Interrupt Status Register 217 * --------------------------------------------------------------------------------------------------- 218 * |Bits |Field |Descriptions 219 * | :----: | :----: | :---- | 220 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only) 221 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. 222 * | | |0 = No AHB bus ERROR response received. 223 * | | |1 = AHB bus ERROR response received. 224 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) 225 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. 226 * | | |0 = Not finished yet. 227 * | | |1 = PDMA channel has finished transmission. 228 * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) 229 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 230 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 231 * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 232 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC0(PDMA_TOC0_1[15:0]. 233 * | | |0 = No request time-out. 234 * | | |1 = Peripheral request time-out. 235 * | | |Note 1: Please disable time-out function before clearing this bit. 236 * | | |Note 2: User can write 1 to clear this bit. 237 * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 238 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC1(PDMA_TOC0_1[31:16]). 239 * | | |0 = No request time-out. 240 * | | |1 = Peripheral request time-out. 241 * | | |Note 1: Please disable time-out function before clearing this bit. 242 * | | |Note 2: User can write 1 to clear this bit. 243 * @var PDMA_T::ABTSTS 244 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register 245 * --------------------------------------------------------------------------------------------------- 246 * |Bits |Field |Descriptions 247 * | :----: | :----: | :---- | 248 * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag 249 * | | |This bit indicates which PDMA controller has target abort error. 250 * | | |0 = No AHB bus ERROR response received when channel n transfer. 251 * | | |1 = AHB bus ERROR response received when channel n transfer. 252 * | | |Note 1: If channel n target abort, REQSRCn should set0 to disable peripheral request. 253 * | | |Note 2: User can write 1 to clear this bit. 254 * @var PDMA_T::TDSTS 255 * Offset: 0x424 PDMA Channel Transfer Done Flag Register 256 * --------------------------------------------------------------------------------------------------- 257 * |Bits |Field |Descriptions 258 * | :----: | :----: | :---- | 259 * |[15:0] |TDIFn |Transfer Done Flag 260 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not. 261 * | | |0 = PDMA channel transfer has not finished. 262 * | | |1 = PDMA channel has finished transmission. 263 * | | |Note: User can write 1 to clear these bits. 264 * @var PDMA_T::ALIGN 265 * Offset: 0x428 PDMA Transfer Alignment Status Register 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[15:0] |ALIGNn |Transfer Alignment Flag 270 * | | |This bit indicates whether source and destination address both follow transfer width setting. 271 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 272 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 273 * | | |Note: User can write 1 to clear these bits. 274 * @var PDMA_T::TACTSTS 275 * Offset: 0x42C PDMA Transfer Active Flag Register 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[15:0] |TXACTFn |Transfer on Active Flag (Read Only) 280 * | | |This bit indicates which PDMA channel is in active. 281 * | | |0 = PDMA channel is finished. 282 * | | |1 = PDMA channel is active. 283 * @var PDMA_T::TOUTPSC 284 * Offset: 0x430 PDMA Time-out Prescaler Register(CH0 to CH1) 285 * --------------------------------------------------------------------------------------------------- 286 * |Bits |Field |Descriptions 287 * | :----: | :----: | :---- | 288 * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits 289 * | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8. 290 * | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9. 291 * | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10. 292 * | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11. 293 * | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12. 294 * | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13. 295 * | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14. 296 * | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15. 297 * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits 298 * | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8. 299 * | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9. 300 * | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10. 301 * | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11. 302 * | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12. 303 * | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13. 304 * | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14. 305 * | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15. 306 * @var PDMA_T::TOUTEN 307 * Offset: 0x434 PDMA Time-out Enable Register 308 * --------------------------------------------------------------------------------------------------- 309 * |Bits |Field |Descriptions 310 * | :----: | :----: | :---- | 311 * |[1:0] |TOUTENn |PDMA Time-out Enable Bits 312 * | | |0 = PDMA Channel n time-out function Disabled. 313 * | | |1 = PDMA Channel n time-out function Enabled. 314 * @var PDMA_T::TOUTIEN 315 * Offset: 0x438 PDMA Time-out Interrupt Enable Register 316 * --------------------------------------------------------------------------------------------------- 317 * |Bits |Field |Descriptions 318 * | :----: | :----: | :---- | 319 * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits 320 * | | |0 = PDMA Channel n time-out interrupt Disabled. 321 * | | |1 = PDMA Channel n time-out interrupt Enabled. 322 * @var PDMA_T::SCATBA 323 * Offset: 0x43C PDMA Scatter-gather Descriptor Table Base Address Register 324 * --------------------------------------------------------------------------------------------------- 325 * |Bits |Field |Descriptions 326 * | :----: | :----: | :---- | 327 * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address 328 * | | |In Scatter-gather mode, this is the base address for calculating the next link - list address 329 * | | |The next link address equation is 330 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCTn_NEXT. 331 * | | |Note: Only useful in Scatter-gather mode. 332 * @var PDMA_T::TOC 333 * Offset: 0x440 PDMA Time-out Counter Ch0 and Ch1 Register 334 * --------------------------------------------------------------------------------------------------- 335 * |Bits |Field |Descriptions 336 * | :----: | :----: | :---- | 337 * |[15:0] |TOC0 |Time-out Counter for Channel 0 338 * | | |This controls the period of time-out function for channel 0 339 * | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. 340 * | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n=0,1. 341 * |[31:16] |TOC1 |Time-out Counter for Channel 1 342 * | | |This controls the period of time-out function for channel 1 343 * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock 344 * | | |The example of time-out period can refer TOC0 bit description. 345 * @var PDMA_T::CHRST 346 * Offset: 0x460 PDMA Channel Reset Register 347 * --------------------------------------------------------------------------------------------------- 348 * |Bits |Field |Descriptions 349 * | :----: | :----: | :---- | 350 * |[15:0] |CHnRST |Channel n Reset 351 * | | |0 = Corresponding channel n is not reset. 352 * | | |1 = Corresponding channel n is reset. 353 * @var PDMA_T::REQSEL0_3 354 * Offset: 0x480 PDMA Request Source Select Register 0 355 * --------------------------------------------------------------------------------------------------- 356 * |Bits |Field |Descriptions 357 * | :----: | :----: | :---- | 358 * |[6:0] |REQSRC0 |Channel 0 Request Source Selection 359 * | | |This filed defines which peripheral is connected to PDMA channel 0 360 * | | |User can configure the peripheral by setting REQSRC0. 361 * | | |0 = Disable PDMA peripheral request. 362 * | | |1 = Reserved. 363 * | | |2 = Channel connects to USB_TX. 364 * | | |3 = Channel connects to USB_RX. 365 * | | |4 = Channel connects to UART0_TX. 366 * | | |5 = Channel connects to UART0_RX. 367 * | | |6 = Channel connects to UART1_TX. 368 * | | |7 = Channel connects to UART1_RX. 369 * | | |8 = Channel connects to UART2_TX. 370 * | | |9 = Channel connects to UART2_RX. 371 * | | |10 = Channel connects to UART3_TX. 372 * | | |11 = Channel connects to UART3_RX. 373 * | | |12 = Channel connects to UART4_TX. 374 * | | |13 = Channel connects to UART4_RX. 375 * | | |14 = Channel connects to UART5_TX. 376 * | | |15 = Channel connects to UART5_RX. 377 * | | |16 = Channel connects to USCI0_TX. 378 * | | |17 = Channel connects to USCI0_RX. 379 * | | |18 = Channel connects to USCI1_TX. 380 * | | |19 = Channel connects to USCI1_RX . 381 * | | |20 = Channel connects to QSPI0_TX. 382 * | | |21 = Channel connects to QSPI0_RX. 383 * | | |22 = Channel connects to SPI0_TX. 384 * | | |23 = Channel connects to SPI0_RX. 385 * | | |24 = Channel connects to SPI1_TX. 386 * | | |25 = Channel connects to SPI1_RX. 387 * | | |26 = Channel connects to SPI2_TX. 388 * | | |27 = Channel connects to SPI2_RX. 389 * | | |28 = Channel connects to SPI3_TX. 390 * | | |29 = Channel connects to SPI3_RX. 391 * | | |30 = Channel connects to ACMP0. 392 * | | |31 = Channel connects to ACMP1. 393 * | | |32 = Channel connects to EPWM0_P1_RX. 394 * | | |33 = Channel connects to EPWM0_P2_RX. 395 * | | |34 = Channel connects to EPWM0_P3_RX. 396 * | | |35 = Channel connects to EPWM1_P1_RX. 397 * | | |36 = Channel connects to EPWM1_P2_RX. 398 * | | |37 = Channel connects to EPWM1_P3_RX. 399 * | | |38 = Channel connects to I2C0_TX. 400 * | | |39 = Channel connects to I2C0_RX. 401 * | | |40 = Channel connects to I2C1_TX. 402 * | | |41 = Channel connects to I2C1_RX. 403 * | | |42 = Channel connects to I2C2_TX. 404 * | | |43 = Channel connects to I2C2_RX. 405 * | | |44 = Channel connects to I2C3_TX. 406 * | | |45 = Channel connects to I2C3_RX. 407 * | | |46 = Channel connects to TMR0. 408 * | | |47 = Channel connects to TMR1. 409 * | | |48 = Channel connects to TMR2. 410 * | | |49 = Channel connects to TMR3. 411 * | | |50 = Channel connects to DAC0_TX. 412 * | | |51 = Channel connects to DAC1_TX. 413 * | | |52 = Channel connects to EPWM0_CH0_TX. 414 * | | |53 = Channel connects to EPWM0_CH1_TX. 415 * | | |54 = Channel connects to EPWM0_CH2_TX. 416 * | | |55 = Channel connects to EPWM0_CH3_TX. 417 * | | |56 = Channel connects to EPWM0_CH4_TX. 418 * | | |57 = Channel connects to EPWM0_CH5_TX. 419 * | | |58 = Channel connects to EPWM1_CH0_TX. 420 * | | |59 = Channel connects to EPWM1_CH1_TX. 421 * | | |60 = Channel connects to EPWM1_CH2_TX. 422 * | | |61 = Channel connects to EPWM1_CH3_TX. 423 * | | |62 = Channel connects to EPWM1_CH4_TX. 424 * | | |63 = Channel connects to EPWM1_CH5_TX. 425 * | | |64 = Channel connects to EADC0_RX. 426 * | | |65 = Channel connects to EADC1_RX. 427 * | | |66 = Channel connects to UART6_TX. 428 * | | |67 = Channel connects to UART6_RX. 429 * | | |68 = Channel connects to UART7_TX. 430 * | | |69 = Channel connects to UART7_RX. 431 * | | |70 = Channel connects to PWM0_P1_RX. 432 * | | |71 = Channel connects to PWM0_P2_RX. 433 * | | |72 = Channel connects to PWM0_P3_RX. 434 * | | |73 = Channel connects to PWM1_P1_RX. 435 * | | |74 = Channel connects to PWM1_P2_RX. 436 * | | |75 = Channel connects to PWM1_P3_RX. 437 * | | |76 = Channel connects to PWM0_CH0_TX. 438 * | | |77 = Channel connects to PWM0_CH2_TX. 439 * | | |78 = Channel connects to PWM0_CH4_TX. 440 * | | |79 = Channel connects to PWM1_CH0_TX. 441 * | | |80 = Channel connects to PWM1_CH2_TX. 442 * | | |81 = Channel connects to PWM1_CH4_TX. 443 * | | |82 = Channel connects to EINT0. 444 * | | |83 = Channel connects to EINT1. 445 * | | |84 = Channel connects to EINT2. 446 * | | |85 = Channel connects to EINT3. 447 * | | |86 = Channel connects to EINT4. 448 * | | |87 = Channel connects to EINT5. 449 * | | |88 = Channel connects to EINT6. 450 * | | |89 = Channel connects to EINT7. 451 * | | |90 = Channel connects to ACMP2. 452 * | | |Others = Reserved. 453 * | | |Note 1: A peripheral cannot be assigned to two channels at the same time. 454 * | | |Note 2: This field is useless when transfer between memory and memory. 455 * |[14:8] |REQSRC1 |Channel 1 Request Source Selection 456 * | | |This filed defines which peripheral is connected to PDMA channel 1 457 * | | |User can configure the peripheral setting by REQSRC1. 458 * | | |Note: The channel configuration is the same as REQSRC0 field 459 * | | |Please refer to the explanation of REQSRC0. 460 * |[22:16] |REQSRC2 |Channel 2 Request Source Selection 461 * | | |This filed defines which peripheral is connected to PDMA channel 2 462 * | | |User can configure the peripheral setting by REQSRC2. 463 * | | |Note: The channel configuration is the same as REQSRC0 field 464 * | | |Please refer to the explanation of REQSRC0. 465 * |[30:24] |REQSRC3 |Channel 3 Request Source Selection 466 * | | |This filed defines which peripheral is connected to PDMA channel 3 467 * | | |User can configure the peripheral setting by REQSRC3. 468 * | | |Note: The channel configuration is the same as REQSRC0 field 469 * | | |Please refer to the explanation of REQSRC0. 470 * @var PDMA_T::REQSEL4_7 471 * Offset: 0x484 PDMA Request Source Select Register 1 472 * --------------------------------------------------------------------------------------------------- 473 * |Bits |Field |Descriptions 474 * | :----: | :----: | :---- | 475 * |[6:0] |REQSRC4 |Channel 4 Request Source Selection 476 * | | |This filed defines which peripheral is connected to PDMA channel 4 477 * | | |User can configure the peripheral setting by REQSRC4. 478 * | | |Note: The channel configuration is the same as REQSRC0 field 479 * | | |Please refer to the explanation of REQSRC0. 480 * |[14:8] |REQSRC5 |Channel 5 Request Source Selection 481 * | | |This filed defines which peripheral is connected to PDMA channel 5 482 * | | |User can configure the peripheral setting by REQSRC5. 483 * | | |Note: The channel configuration is the same as REQSRC0 field 484 * | | |Please refer to the explanation of REQSRC0. 485 * |[22:16] |REQSRC6 |Channel 6 Request Source Selection 486 * | | |This filed defines which peripheral is connected to PDMA channel 6 487 * | | |User can configure the peripheral setting by REQSRC6. 488 * | | |Note: The channel configuration is the same as REQSRC0 field 489 * | | |Please refer to the explanation of REQSRC0. 490 * |[30:24] |REQSRC7 |Channel 7 Request Source Selection 491 * | | |This filed defines which peripheral is connected to PDMA channel 7 492 * | | |User can configure the peripheral setting by REQSRC7. 493 * | | |Note: The channel configuration is the same as REQSRC0 field 494 * | | |Please refer to the explanation of REQSRC0. 495 * @var PDMA_T::REQSEL8_11 496 * Offset: 0x488 PDMA Request Source Select Register 2 497 * --------------------------------------------------------------------------------------------------- 498 * |Bits |Field |Descriptions 499 * | :----: | :----: | :---- | 500 * |[6:0] |REQSRC8 |Channel 8 Request Source Selection 501 * | | |This filed defines which peripheral is connected to PDMA channel 8 502 * | | |User can configure the peripheral setting by REQSRC8. 503 * | | |Note: The channel configuration is the same as REQSRC0 field 504 * | | |Please refer to the explanation of REQSRC0. 505 * |[14:8] |REQSRC9 |Channel 9 Request Source Selection 506 * | | |This filed defines which peripheral is connected to PDMA channel 9 507 * | | |User can configure the peripheral setting by REQSRC9. 508 * | | |Note: The channel configuration is the same as REQSRC0 field 509 * | | |Please refer to the explanation of REQSRC0. 510 * |[22:16] |REQSRC10 |Channel 10 Request Source Selection 511 * | | |This filed defines which peripheral is connected to PDMA channel 10 512 * | | |User can configure the peripheral setting by REQSRC10. 513 * | | |Note: The channel configuration is the same as REQSRC0 field 514 * | | |Please refer to the explanation of REQSRC0. 515 * |[30:24] |REQSRC11 |Channel 11 Request Source Selection 516 * | | |This filed defines which peripheral is connected to PDMA channel 11 517 * | | |User can configure the peripheral setting by REQSRC11. 518 * | | |Note: The channel configuration is the same as REQSRC0 field 519 * | | |Please refer to the explanation of REQSRC0. 520 * @var PDMA_T::REQSEL12_15 521 * Offset: 0x48C PDMA Request Source Select Register 3 522 * --------------------------------------------------------------------------------------------------- 523 * |Bits |Field |Descriptions 524 * | :----: | :----: | :---- | 525 * |[6:0] |REQSRC12 |Channel 12 Request Source Selection 526 * | | |This filed defines which peripheral is connected to PDMA channel 12 527 * | | |User can configure the peripheral setting by REQSRC12. 528 * | | |Note: The channel configuration is the same as REQSRC0 field 529 * | | |Please refer to the explanation of REQSRC0. 530 * |[14:8] |REQSRC13 |Channel 13 Request Source Selection 531 * | | |This filed defines which peripheral is connected to PDMA channel 13 532 * | | |User can configure the peripheral setting by REQSRC13. 533 * | | |Note: The channel configuration is the same as REQSRC0 field 534 * | | |Please refer to the explanation of REQSRC0. 535 * |[22:16] |REQSRC14 |Channel 14 Request Source Selection 536 * | | |This filed defines which peripheral is connected to PDMA channel 14 537 * | | |User can configure the peripheral setting by REQSRC14. 538 * | | |Note: The channel configuration is the same as REQSRC0 field 539 * | | |Please refer to the explanation of REQSRC0. 540 * |[30:24] |REQSRC15 |Channel 15 Request Source Selection 541 * | | |This filed defines which peripheral is connected to PDMA channel 15 542 * | | |User can configure the peripheral setting by REQSRC15. 543 * | | |Note: The channel configuration is the same as REQSRC0 field 544 * | | |Please refer to the explanation of REQSRC0. 545 */ 546 DSCT_T DSCT[16]; /*!< [0x0000 ~ 0x015C] Control Register of PDMA Channel 0 ~ 15 */ 547 __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-gather Descriptor Table Address of PDMA Channel n */ 548 __I uint32_t RESERVE0[176]; 549 __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ 550 __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ 551 __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ 552 __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ 553 __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ 554 __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ 555 __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ 556 __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ 557 __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ 558 __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ 559 __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ 560 __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ 561 __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register(CH0 to CH1) */ 562 __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ 563 __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ 564 __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-gather Descriptor Table Base Address Register */ 565 __IO uint32_t TOC; /*!< [0x0440] PDMA Time-out Counter Ch0 and Ch1 Register */ 566 __I uint32_t RESERVE1[7]; 567 __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ 568 __I uint32_t RESERVE2[7]; 569 __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ 570 __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ 571 __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ 572 __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ 573 574 } PDMA_T; 575 576 /** 577 @addtogroup PDMA_CONST PDMA Bit Field Definition 578 Constant Definitions for PDMA Controller 579 @{ */ 580 581 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */ 582 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */ 583 584 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */ 585 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */ 586 587 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */ 588 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */ 589 590 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */ 591 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */ 592 593 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */ 594 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */ 595 596 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */ 597 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */ 598 599 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */ 600 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */ 601 602 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */ 603 #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */ 604 605 #define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */ 606 #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */ 607 608 #define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */ 609 #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */ 610 611 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */ 612 #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */ 613 614 #define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< DSCT_T::NEXT: EXENEXT Position */ 615 #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< DSCT_T::NEXT: EXENEXT Mask */ 616 617 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ 618 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ 619 620 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ 621 #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ 622 623 #define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ 624 #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ 625 626 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ 627 #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ 628 629 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ 630 #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ 631 632 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ 633 #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ 634 635 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ 636 #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ 637 638 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ 639 #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ 640 641 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ 642 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ 643 644 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ 645 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ 646 647 #define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ 648 #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ 649 650 #define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ 651 #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ 652 653 #define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ 654 #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ 655 656 #define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ 657 #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ 658 659 #define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ 660 #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ 661 662 #define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ 663 #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ 664 665 #define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ 666 #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ 667 668 #define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ 669 #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ 670 671 #define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ 672 #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ 673 674 #define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ 675 #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ 676 677 #define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ 678 #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ 679 680 #define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ 681 #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ 682 683 #define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ 684 #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ 685 686 #define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ 687 #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ 688 689 #define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ 690 #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ 691 692 #define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ 693 #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ 694 695 #define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ 696 #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ 697 698 #define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ 699 #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ 700 701 #define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ 702 #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ 703 704 #define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ 705 #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ 706 707 #define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ 708 #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ 709 710 #define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ 711 #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ 712 713 #define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ 714 #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ 715 716 #define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ 717 #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ 718 719 #define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ 720 #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ 721 722 #define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ 723 #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ 724 725 #define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ 726 #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ 727 728 #define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ 729 #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ 730 731 #define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ 732 #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ 733 734 #define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ 735 #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ 736 737 #define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ 738 #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ 739 740 #define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ 741 #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ 742 743 #define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ 744 #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ 745 746 #define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ 747 #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ 748 749 #define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ 750 #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ 751 752 #define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ 753 #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ 754 755 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ 756 #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ 757 758 #define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ 759 #define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ 760 761 #define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ 762 #define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ 763 764 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ 765 #define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ 766 767 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ 768 #define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ 769 770 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ 771 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ 772 773 #define PDMA_TOC_TOC0_Pos (0) /*!< PDMA_T::TOC: TOC0 Position */ 774 #define PDMA_TOC_TOC0_Msk (0xfffful << PDMA_TOC_TOC0_Pos) /*!< PDMA_T::TOC: TOC0 Mask */ 775 776 #define PDMA_TOC_TOC1_Pos (16) /*!< PDMA_T::TOC: TOC1 Position */ 777 #define PDMA_TOC_TOC1_Msk (0xfffful << PDMA_TOC_TOC1_Pos) /*!< PDMA_T::TOC: TOC1 Mask */ 778 779 #define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ 780 #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ 781 782 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ 783 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ 784 785 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ 786 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ 787 788 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ 789 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ 790 791 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ 792 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ 793 794 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ 795 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ 796 797 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ 798 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ 799 800 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ 801 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ 802 803 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ 804 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ 805 806 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ 807 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ 808 809 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ 810 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ 811 812 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ 813 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ 814 815 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ 816 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ 817 818 #define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ 819 #define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ 820 821 #define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ 822 #define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ 823 824 #define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ 825 #define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ 826 827 #define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ 828 #define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ 829 830 /**@}*/ /* PDMA_CONST */ 831 /**@}*/ /* end of PDMA register group */ 832 /**@}*/ /* end of REGISTER group */ 833 834 #if defined ( __CC_ARM ) 835 #pragma no_anon_unions 836 #endif 837 838 #endif /* __PDMA_REG_H__ */
