1 /**************************************************************************//** 2 * @file pdma_reg.h 3 * @version V1.00 4 * @brief PDMA register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_REG_H__ 10 #define __PDMA_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup PDMA Peripheral Direct Memory Access Controller (PDMA) 23 Memory Mapped Structure for PDMA Controller 24 @{ */ 25 26 27 typedef struct 28 { 29 30 /** 31 * @var DSCT_T::CTL 32 * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n. 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[1:0] |OPMODE |PDMA Operation Mode Selection 37 * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. 38 * | | |01 = Basic mode: The descriptor table only has one task 39 * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. 40 * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. 41 * | | |11 = Reserved. 42 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. 43 * |[2] |TXTYPE |Transfer Type 44 * | | |0 = Burst transfer type. 45 * | | |1 = Single transfer type. 46 * |[6:4] |BURSIZE |Burst Size 47 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. 48 * | | |000 = 128 Transfers. 49 * | | |001 = 64 Transfers. 50 * | | |010 = 32 Transfers. 51 * | | |011 = 16 Transfers. 52 * | | |100 = 8 Transfers. 53 * | | |101 = 4 Transfers. 54 * | | |110 = 2 Transfers. 55 * | | |111 = 1 Transfers. 56 * | | |Note: This field is only useful in burst transfer type. 57 * |[7] |TBINTDIS |Table Interrupt Disable Bit 58 * | | |This field can be used to decide whether to enable table interrupt or not 59 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. 60 * | | |0 = Table interrupt Enabled. 61 * | | |1 = Table interrupt Disabled. 62 * |[9:8] |SAINC |Source Address Increment 63 * | | |This field is used to set the source address increment size. 64 * | | |11 = No increment (fixed address). 65 * | | |Others = Increment and size is depended on TXWIDTH selection. 66 * |[11:10] |DAINC |Destination Address Increment 67 * | | |This field is used to set the destination address increment size. 68 * | | |11 = No increment (fixed address). 69 * | | |Others = Increment and size is depended on TXWIDTH selection. 70 * |[13:12] |TXWIDTH |Transfer Width Selection 71 * | | |This field is used for transfer width. 72 * | | |00 = One byte (8 bit) is transferred for every operation. 73 * | | |01= One half-word (16 bit) is transferred for every operation. 74 * | | |10 = One word (32-bit) is transferred for every operation. 75 * | | |11 = Reserved. 76 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 77 * |[14] |TXACK |Transfer Acknowledge Selection 78 * | | |0 = transfer ack when transfer done. 79 * | | |1 = transfer ack when PDMA get transfer data. 80 * |[15] |STRIDEEN |Stride Mode Enable Bit 81 * | | |0 = Stride transfer mode Disabled. 82 * | | |1 = Stride transfer mode Enabled. 83 * |[31:16] |TXCNT |Transfer Count 84 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 32768, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. 85 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. 86 * @var DSCT_T::SA 87 * Offset: 0x04 Source Address Register of PDMA Channel n 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[31:0] |SA |PDMA Transfer Source Address Register 92 * | | |This field indicates a 32-bit source address of PDMA controller. 93 * @var DSCT_T::DA 94 * Offset: 0x08 Destination Address Register of PDMA Channel n 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[31:0] |DA |PDMA Transfer Destination Address Register 99 * | | |This field indicates a 32-bit destination address of PDMA controller. 100 * @var DSCT_T::NEXT 101 * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset 106 * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. 107 * | | |Note: write operation is useless in this field. 108 * |[31:16] |NEXT |PDMA Next Descriptor Table Offset. 109 * | | |This field indicates the offset of the next descriptor table address in system memory. 110 * | | |Write Operation: 111 * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. 112 * | | |Read Operation: 113 * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. 114 * | | |Note1: The descriptor table address must be word boundary. 115 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 116 */ 117 __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ 118 __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ 119 __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ 120 __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ 121 } DSCT_T; 122 123 124 typedef struct 125 { 126 /** 127 * @var STRIDE_T::STCR 128 * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n 129 * --------------------------------------------------------------------------------------------------- 130 * |Bits |Field |Descriptions 131 * | :----: | :----: | :---- | 132 * |[15:0] |STC |PDMA Stride Transfer Count 133 * | | |The 16-bit register defines the stride transfer count of each row. 134 * @var STRIDE_T::ASOCR 135 * Offset: 0x504 Address Stride Offset Register of PDMA Channel n 136 * --------------------------------------------------------------------------------------------------- 137 * |Bits |Field |Descriptions 138 * | :----: | :----: | :---- | 139 * |[15:0] |SASOL |VDMA Source Address Stride Offset Length 140 * | | |The 16-bit register defines the source address stride transfer offset count of each row. 141 * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length 142 * | | |The 16-bit register defines the destination address stride transfer offset count of each row. 143 */ 144 __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ 145 __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ 146 } STRIDE_T; 147 148 typedef struct 149 { 150 /** 151 * @var REPEAT_T::AICTL 152 * Offset: 0x600 Address Interval Control Register of PDMA Channel n 153 * --------------------------------------------------------------------------------------------------- 154 * |Bits |Field |Descriptions 155 * | :----: | :----: | :---- | 156 * |[15:0] |SAICNT |PDMA Source Address Interval Count 157 * | | |The 16-bit register defines the source address interval count of each row. 158 * |[31:16] |DAICNT |PDMA Destination Address Interval Count 159 * | | |The 16-bit register defines the destination address interval count of each row. 160 * @var REPEAT_T::RCNT 161 * Offset: 0x604 Repeat Count Register of PDMA Channe n 162 * --------------------------------------------------------------------------------------------------- 163 * |Bits |Field |Descriptions 164 * | :----: | :----: | :---- | 165 * |[15:0] |RCNT |PDMA Repeat Count 166 * | | |The 16-bit register defines the repeat times of block transfer. 167 */ 168 __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ 169 __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ 170 } REPEAT_T; 171 172 typedef struct 173 { 174 175 176 /** 177 * @var PDMA_T::CURSCAT 178 * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n 179 * --------------------------------------------------------------------------------------------------- 180 * |Bits |Field |Descriptions 181 * | :----: | :----: | :---- | 182 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) 183 * | | |This field indicates a 32-bit current external description address of PDMA controller. 184 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. 185 * @var PDMA_T::CHCTL 186 * Offset: 0x400 PDMA Channel Control Register 187 * --------------------------------------------------------------------------------------------------- 188 * |Bits |Field |Descriptions 189 * | :----: | :----: | :---- | 190 * |[15:0] |CHENn |PDMA Channel Enable Bit 191 * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. 192 * | | |0 = PDMA channel [n] Disabled. 193 * | | |1 = PDMA channel [n] Enabled. 194 * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 195 * @var PDMA_T::PAUSE 196 * Offset: 0x404 PDMA Transfer Stop Control Register 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) 201 * | | |User can set PAUSEn bit field to pause the PDMA transfer 202 * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag 203 * | | |If re-enable the paused channel again, the remaining transfers will be processed. 204 * | | |0 = No effect. 205 * | | |1 = Pause PDMA channel n transfer. 206 * @var PDMA_T::SWREQ 207 * Offset: 0x408 PDMA Software Request Register 208 * --------------------------------------------------------------------------------------------------- 209 * |Bits |Field |Descriptions 210 * | :----: | :----: | :---- | 211 * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) 212 * | | |Set this bit to 1 to generate a software request to PDMA [n]. 213 * | | |0 = No effect. 214 * | | |1 = Generate a software request. 215 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active 216 * | | |Active flag may be triggered by software request or peripheral request. 217 * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. 218 * @var PDMA_T::TRGSTS 219 * Offset: 0x40C PDMA Channel Request Status Register 220 * --------------------------------------------------------------------------------------------------- 221 * |Bits |Field |Descriptions 222 * | :----: | :----: | :---- | 223 * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) 224 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral 225 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. 226 * | | |0 = PDMA Channel n has no request. 227 * | | |1 = PDMA Channel n has a request. 228 * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. 229 * @var PDMA_T::PRISET 230 * Offset: 0x410 PDMA Fixed Priority Setting Register 231 * --------------------------------------------------------------------------------------------------- 232 * |Bits |Field |Descriptions 233 * | :----: | :----: | :---- | 234 * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register 235 * | | |Set this bit to 1 to enable fixed priority level. 236 * | | |Write Operation: 237 * | | |0 = No effect. 238 * | | |1 = Set PDMA channel [n] to fixed priority channel. 239 * | | |Read Operation: 240 * | | |0 = Corresponding PDMA channel is round-robin priority. 241 * | | |1 = Corresponding PDMA channel is fixed priority. 242 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 243 * @var PDMA_T::PRICLR 244 * Offset: 0x414 PDMA Fixed Priority Clear Register 245 * --------------------------------------------------------------------------------------------------- 246 * |Bits |Field |Descriptions 247 * | :----: | :----: | :---- | 248 * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) 249 * | | |Set this bit to 1 to clear fixed priority level. 250 * | | |0 = No effect. 251 * | | |1 = Clear PDMA channel [n] fixed priority setting. 252 * | | |Note: User can read PDMA_PRISET register to know the channel priority. 253 * @var PDMA_T::INTEN 254 * Offset: 0x418 PDMA Interrupt Enable Register 255 * --------------------------------------------------------------------------------------------------- 256 * |Bits |Field |Descriptions 257 * | :----: | :----: | :---- | 258 * |[15:0] |INTENn |PDMA Interrupt Enable Register 259 * | | |This field is used for enabling PDMA channel[n] interrupt. 260 * | | |0 = PDMA channel n interrupt Disabled. 261 * | | |1 = PDMA channel n interrupt Enabled. 262 * @var PDMA_T::INTSTS 263 * Offset: 0x41C PDMA Interrupt Status Register 264 * --------------------------------------------------------------------------------------------------- 265 * |Bits |Field |Descriptions 266 * | :----: | :----: | :---- | 267 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only) 268 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. 269 * | | |0 = No AHB bus ERROR response received. 270 * | | |1 = AHB bus ERROR response received. 271 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) 272 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. 273 * | | |0 = Not finished yet. 274 * | | |1 = PDMA channel has finished transmission. 275 * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) 276 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 277 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 278 * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 279 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC0(PDMA_TOC0_1[15:0], user can write 1 to clear these bits. 280 * | | |0 = No request time-out. 281 * | | |1 = Peripheral request time-out. 282 * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 283 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC1(PDMA_TOC0_1[31:16]), user can write 1 to clear these bits. 284 * | | |0 = No request time-out. 285 * | | |1 = Peripheral request time-out. 286 * |[10] |REQTOF2 |Request Time-out Flag for Channel 2 287 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC2(PDMA_TOC2_3[15:0]), user can write 1 to clear these bits. 288 * | | |0 = No request time-out. 289 * | | |1 = Peripheral request time-out. 290 * |[11] |REQTOF3 |Request Time-out Flag for Channel 3 291 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC3(PDMA_TOC2_3[31:16]), user can write 1 to clear these bits. 292 * | | |0 = No request time-out. 293 * | | |1 = Peripheral request time-out. 294 * |[12] |REQTOF4 |Request Time-out Flag for Channel 4 295 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC4(PDMA_TOC4_5[15:0]), user can write 1 to clear these bits. 296 * | | |0 = No request time-out. 297 * | | |1 = Peripheral request time-out. 298 * |[13] |REQTOF5 |Request Time-out Flag for Channel 5 299 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC5(PDMA_TOC4_5[31:16]), user can write 1 to clear these bits. 300 * | | |0 = No request time-out. 301 * | | |1 = Peripheral request time-out. 302 * |[14] |REQTOF6 |Request Time-out Flag for Channel 6 303 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC6(PDMA_TOC6_7[15:0]), user can write 1 to clear these bits. 304 * | | |0 = No request time-out. 305 * | | |1 = Peripheral request time-out. 306 * |[15] |REQTOF7 |Request Time-out Flag for Channel 7 307 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC7(PDMA_TOC6_7[31:16]), user can write 1 to clear these bits. 308 * | | |0 = No request time-out. 309 * | | |1 = Peripheral request time-out. 310 * |[16] |REQTOF8 |Request Time-out Flag for Channel 8 311 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC8(PDMA_TOC8_9[15:0]), user can write 1 to clear these bits. 312 * | | |0 = No request time-out. 313 * | | |1 = Peripheral request time-out. 314 * |[17] |REQTOF9 |Request Time-out Flag for Channel 9 315 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC9(PDMA_TOC8_9[31:16]), user can write 1 to clear these bits. 316 * | | |0 = No request time-out. 317 * | | |1 = Peripheral request time-out. 318 * |[18] |REQTOF10 |Request Time-out Flag for Channel 10 319 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC10(PDMA_TOC10_11[15:0]), user can write 1 to clear these bits. 320 * | | |0 = No request time-out. 321 * | | |1 = Peripheral request time-out. 322 * |[19] |REQTOF11 |Request Time-out Flag for Channel 11 323 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC11(PDMA_TOC10_11[31:16]), user can write 1 to clear these bits. 324 * | | |0 = No request time-out. 325 * | | |1 = Peripheral request time-out. 326 * |[20] |REQTOF12 |Request Time-out Flag for Channel 12 327 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC12(PDMA_TOC13_12[15:0]), user can write 1 to clear these bits. 328 * | | |0 = No request time-out. 329 * | | |1 = Peripheral request time-out. 330 * |[21] |REQTOF13 |Request Time-out Flag for Channel 13 331 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC13(PDMA_TOC13_12[31:16]), user can write 1 to clear these bits. 332 * | | |0 = No request time-out. 333 * | | |1 = Peripheral request time-out. 334 * |[22] |REQTOF14 |Request Time-out Flag for Channel 14 335 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC14(PDMA_TOC15_14[15:0]), user can write 1 to clear these bits. 336 * | | |0 = No request time-out. 337 * | | |1 = Peripheral request time-out. 338 * |[23] |REQTOF15 |Request Time-out Flag for Channel 15 339 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC15(PDMA_TOC15_14[31:16]), user can write 1 to clear these bits. 340 * | | |0 = No request time-out. 341 * | | |1 = Peripheral request time-out. 342 * @var PDMA_T::ABTSTS 343 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register 344 * --------------------------------------------------------------------------------------------------- 345 * |Bits |Field |Descriptions 346 * | :----: | :----: | :---- | 347 * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag 348 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. 349 * | | |0 = No AHB bus ERROR response received when channel n transfer. 350 * | | |1 = AHB bus ERROR response received when channel n transfer. 351 * @var PDMA_T::TDSTS 352 * Offset: 0x424 PDMA Channel Transfer Done Flag Register 353 * --------------------------------------------------------------------------------------------------- 354 * |Bits |Field |Descriptions 355 * | :----: | :----: | :---- | 356 * |[15:0] |TDIFn |Transfer Done Flag Register 357 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 358 * | | |0 = PDMA channel transfer has not finished. 359 * | | |1 = PDMA channel has finished transmission. 360 * @var PDMA_T::ALIGN 361 * Offset: 0x428 PDMA Transfer Alignment Status Register 362 * --------------------------------------------------------------------------------------------------- 363 * |Bits |Field |Descriptions 364 * | :----: | :----: | :---- | 365 * |[15:0] |ALIGNn |Transfer Alignment Flag Register 366 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 367 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 368 * @var PDMA_T::TACTSTS 369 * Offset: 0x42C PDMA Transfer Active Flag Register 370 * --------------------------------------------------------------------------------------------------- 371 * |Bits |Field |Descriptions 372 * | :----: | :----: | :---- | 373 * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) 374 * | | |This bit indicates which PDMA channel is in active. 375 * | | |0 = PDMA channel is not finished. 376 * | | |1 = PDMA channel is active. 377 * @var PDMA_T::TOUTPSC0_7 378 * Offset: 0x430 PDMA Time-out Prescaler Register(CH0 to CH7) 379 * --------------------------------------------------------------------------------------------------- 380 * |Bits |Field |Descriptions 381 * | :----: | :----: | :---- | 382 * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits 383 * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. 384 * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. 385 * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. 386 * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. 387 * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. 388 * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. 389 * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. 390 * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. 391 * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits 392 * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. 393 * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. 394 * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. 395 * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. 396 * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. 397 * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. 398 * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. 399 * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. 400 * |[10:8] |TOUTPSC2 |PDMA Channel 2 Time-out Clock Source Prescaler Bits 401 * | | |000 = PDMA channel 2 time-out clock source is HCLK/28. 402 * | | |001 = PDMA channel 2 time-out clock source is HCLK/29. 403 * | | |010 = PDMA channel 2 time-out clock source is HCLK/210. 404 * | | |011 = PDMA channel 2 time-out clock source is HCLK/211. 405 * | | |100 = PDMA channel 2 time-out clock source is HCLK/212. 406 * | | |101 = PDMA channel 2 time-out clock source is HCLK/213. 407 * | | |110 = PDMA channel 2 time-out clock source is HCLK/214. 408 * | | |111 = PDMA channel 2 time-out clock source is HCLK/215. 409 * |[14:12] |TOUTPSC3 |PDMA Channel 3 Time-out Clock Source Prescaler Bits 410 * | | |000 = PDMA channel 3 time-out clock source is HCLK/28. 411 * | | |001 = PDMA channel 3 time-out clock source is HCLK/29. 412 * | | |010 = PDMA channel 3 time-out clock source is HCLK/210. 413 * | | |011 = PDMA channel 3 time-out clock source is HCLK/211. 414 * | | |100 = PDMA channel 3 time-out clock source is HCLK/212. 415 * | | |101 = PDMA channel 3 time-out clock source is HCLK/213. 416 * | | |110 = PDMA channel 3 time-out clock source is HCLK/214. 417 * | | |111 = PDMA channel 3 time-out clock source is HCLK/215. 418 * |[18:16] |TOUTPSC4 |PDMA Channel 4 Time-out Clock Source Prescaler Bits 419 * | | |000 = PDMA channel 4 time-out clock source is HCLK/28. 420 * | | |001 = PDMA channel 4 time-out clock source is HCLK/29. 421 * | | |010 = PDMA channel 4 time-out clock source is HCLK/210. 422 * | | |011 = PDMA channel 4 time-out clock source is HCLK/211. 423 * | | |100 = PDMA channel 4 time-out clock source is HCLK/212. 424 * | | |101 = PDMA channel 4 time-out clock source is HCLK/213. 425 * | | |110 = PDMA channel 4 time-out clock source is HCLK/214. 426 * | | |111 = PDMA channel 4 time-out clock source is HCLK/215. 427 * |[22:20] |TOUTPSC5 |PDMA Channel 5 Time-out Clock Source Prescaler Bits 428 * | | |000 = PDMA channel 5 time-out clock source is HCLK/28. 429 * | | |001 = PDMA channel 5 time-out clock source is HCLK/29. 430 * | | |010 = PDMA channel 5 time-out clock source is HCLK/210. 431 * | | |011 = PDMA channel 5 time-out clock source is HCLK/211. 432 * | | |100 = PDMA channel 5 time-out clock source is HCLK/212. 433 * | | |101 = PDMA channel 5 time-out clock source is HCLK/213. 434 * | | |110 = PDMA channel 5 time-out clock source is HCLK/214. 435 * | | |111 = PDMA channel 5 time-out clock source is HCLK/215. 436 * |[26:24] |TOUTPSC6 |PDMA Channel 6 Time-out Clock Source Prescaler Bits 437 * | | |000 = PDMA channel 6 time-out clock source is HCLK/28. 438 * | | |001 = PDMA channel 6 time-out clock source is HCLK/29. 439 * | | |010 = PDMA channel 6 time-out clock source is HCLK/210. 440 * | | |011 = PDMA channel 6 time-out clock source is HCLK/211. 441 * | | |100 = PDMA channel 6 time-out clock source is HCLK/212. 442 * | | |101 = PDMA channel 6 time-out clock source is HCLK/213. 443 * | | |110 = PDMA channel 6 time-out clock source is HCLK/214. 444 * | | |111 = PDMA channel 6 time-out clock source is HCLK/215. 445 * |[30:28] |TOUTPSC7 |PDMA Channel 7 Time-out Clock Source Prescaler Bits 446 * | | |000 = PDMA channel 7 time-out clock source is HCLK/28. 447 * | | |001 = PDMA channel 7 time-out clock source is HCLK/29. 448 * | | |010 = PDMA channel 7 time-out clock source is HCLK/210. 449 * | | |011 = PDMA channel 7 time-out clock source is HCLK/211. 450 * | | |100 = PDMA channel 7 time-out clock source is HCLK/212. 451 * | | |101 = PDMA channel 7 time-out clock source is HCLK/213. 452 * | | |110 = PDMA channel 7 time-out clock source is HCLK/214. 453 * | | |111 = PDMA channel 7 time-out clock source is HCLK/215. 454 * @var PDMA_T::TOUTEN 455 * Offset: 0x434 PDMA Time-out Enable Register 456 * --------------------------------------------------------------------------------------------------- 457 * |Bits |Field |Descriptions 458 * | :----: | :----: | :---- | 459 * |[15:0] |TOUTENn |PDMA Time-out Enable Bits 460 * | | |0 = PDMA Channel n time-out function Disable. 461 * | | |1 = PDMA Channel n time-out function Enable. 462 * @var PDMA_T::TOUTIEN 463 * Offset: 0x438 PDMA Time-out Interrupt Enable Register 464 * --------------------------------------------------------------------------------------------------- 465 * |Bits |Field |Descriptions 466 * | :----: | :----: | :---- | 467 * |[15:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits 468 * | | |0 = PDMA Channel n time-out interrupt Disable. 469 * | | |1 = PDMA Channel n time-out interrupt Enable. 470 * @var PDMA_T::SCATBA 471 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register 472 * --------------------------------------------------------------------------------------------------- 473 * |Bits |Field |Descriptions 474 * | :----: | :----: | :---- | 475 * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register 476 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address 477 * | | |The next link address equation is 478 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. 479 * | | |Note: Only useful in Scatter-Gather mode. 480 * @var PDMA_T::TOC0_1 481 * Offset: 0x440 PDMA Time-out Counter Ch0 and Ch1 Register 482 * --------------------------------------------------------------------------------------------------- 483 * |Bits |Field |Descriptions 484 * | :----: | :----: | :---- | 485 * |[15:0] |TOC0 |Time-out Counter for Channel 0 486 * | | |This controls the period of time-out function for channel 0 487 * | | |The calculation unit is based on 10 kHz clock. 488 * |[31:16] |TOC1 |Time-out Counter for Channel 1 489 * | | |This controls the period of time-out function for channel 1 490 * | | |The calculation unit is based on 10 kHz clock. 491 * @var PDMA_T::TOC2_3 492 * Offset: 0x444 PDMA Time-out Counter Ch2 and Ch3 Register 493 * --------------------------------------------------------------------------------------------------- 494 * |Bits |Field |Descriptions 495 * | :----: | :----: | :---- | 496 * |[15:0] |TOC2 |Time-out Counter for Channel 2 497 * | | |This controls the period of time-out function for channel 2 498 * | | |The calculation unit is based on 10 kHz clock. 499 * |[31:16] |TOC3 |Time-out Counter for Channel 3 500 * | | |This controls the period of time-out function for channel 3 501 * | | |The calculation unit is based on 10 kHz clock. 502 * @var PDMA_T::TOC4_5 503 * Offset: 0x448 PDMA Time-out Counter Ch4 and Ch5 Register 504 * --------------------------------------------------------------------------------------------------- 505 * |Bits |Field |Descriptions 506 * | :----: | :----: | :---- | 507 * |[15:0] |TOC4 |Time-out Counter for Channel 4 508 * | | |This controls the period of time-out function for channel 4 509 * | | |The calculation unit is based on 10 kHz clock. 510 * |[31:16] |TOC5 |Time-out Counter for Channel 5 511 * | | |This controls the period of time-out function for channel 5 512 * | | |The calculation unit is based on 10 kHz clock. 513 * @var PDMA_T::TOC6_7 514 * Offset: 0x44C PDMA Time-out Counter Ch6 and Ch7 Register 515 * --------------------------------------------------------------------------------------------------- 516 * |Bits |Field |Descriptions 517 * | :----: | :----: | :---- | 518 * |[15:0] |TOC6 |Time-out Counter for Channel 6 519 * | | |This controls the period of time-out function for channel 6 520 * | | |The calculation unit is based on 10 kHz clock. 521 * |[31:16] |TOC7 |Time-out Counter for Channel 7 522 * | | |This controls the period of time-out function for channel 7 523 * | | |The calculation unit is based on 10 kHz clock. 524 * @var PDMA_T::TOC8_9 525 * Offset: 0x450 PDMA Time-out Counter Ch8 and Ch9 Register 526 * --------------------------------------------------------------------------------------------------- 527 * |Bits |Field |Descriptions 528 * | :----: | :----: | :---- | 529 * |[15:0] |TOC8 |Time-out Counter for Channel 8 530 * | | |This controls the period of time-out function for channel 8 531 * | | |The calculation unit is based on 10 kHz clock. 532 * |[31:16] |TOC9 |Time-out Counter for Channel 9 533 * | | |This controls the period of time-out function for channel 9 534 * | | |The calculation unit is based on 10 kHz clock. 535 * @var PDMA_T::TOC10_11 536 * Offset: 0x454 PDMA Time-out Counter Ch10 and Ch11 Register 537 * --------------------------------------------------------------------------------------------------- 538 * |Bits |Field |Descriptions 539 * | :----: | :----: | :---- | 540 * |[15:0] |TOC10 |Time-out Counter for Channel 10 541 * | | |This controls the period of time-out function for channel 10 542 * | | |The calculation unit is based on 10 kHz clock. 543 * |[31:16] |TOC11 |Time-out Counter for Channel 11 544 * | | |This controls the period of time-out function for channel 11 545 * | | |The calculation unit is based on 10 kHz clock. 546 * @var PDMA_T::TOC12_13 547 * Offset: 0x458 PDMA Time-out Counter Ch12 and Ch13 Register 548 * --------------------------------------------------------------------------------------------------- 549 * |Bits |Field |Descriptions 550 * | :----: | :----: | :---- | 551 * |[15:0] |TOC12 |Time-out Counter for Channel 12 552 * | | |This controls the period of time-out function for channel 12 553 * | | |The calculation unit is based on 10 kHz clock. 554 * |[31:16] |TOC13 |Time-out Counter for Channel 13 555 * | | |This controls the period of time-out function for channel 13 556 * | | |The calculation unit is based on 10 kHz clock. 557 * @var PDMA_T::TOC14_15 558 * Offset: 0x45C PDMA Time-out Counter Ch14 and Ch15 Register 559 * --------------------------------------------------------------------------------------------------- 560 * |Bits |Field |Descriptions 561 * | :----: | :----: | :---- | 562 * |[15:0] |TOC14 |Time-out Counter for Channel 14 563 * | | |This controls the period of time-out function for channel 14 564 * | | |The calculation unit is based on 10 kHz clock. 565 * |[31:16] |TOC15 |Time-out Counter for Channel 15 566 * | | |This controls the period of time-out function for channel 15 567 * | | |The calculation unit is based on 10 kHz clock. 568 * @var PDMA_T::CHRST 569 * Offset: 0x460 PDMA Channel Reset Register 570 * --------------------------------------------------------------------------------------------------- 571 * |Bits |Field |Descriptions 572 * | :----: | :----: | :---- | 573 * |[15:0] |CHnRST |Channel N Reset 574 * | | |0 = corresponding channel n not reset. 575 * | | |1 = corresponding channel n is reset. 576 * @var PDMA_T::TOUTPSC8_15 577 * Offset: 0x468 PDMA Time-out Prescaler Register(CH8 to CH15) 578 * --------------------------------------------------------------------------------------------------- 579 * |Bits |Field |Descriptions 580 * | :----: | :----: | :---- | 581 * |[2:0] |TOUTPSC8 |PDMA Channel 8 Time-out Clock Source Prescaler Bits 582 * | | |000 = PDMA channel 8 time-out clock source is HCLK/28. 583 * | | |001 = PDMA channel 8 time-out clock source is HCLK/29. 584 * | | |010 = PDMA channel 8 time-out clock source is HCLK/210. 585 * | | |011 = PDMA channel 8 time-out clock source is HCLK/211. 586 * | | |100 = PDMA channel 8 time-out clock source is HCLK/212. 587 * | | |101 = PDMA channel 8 time-out clock source is HCLK/213. 588 * | | |110 = PDMA channel 8 time-out clock source is HCLK/214. 589 * | | |111 = PDMA channel 8 time-out clock source is HCLK/215. 590 * |[6:4] |TOUTPSC9 |PDMA Channel 9 Time-out Clock Source Prescaler Bits 591 * | | |000 = PDMA channel 9 time-out clock source is HCLK/28. 592 * | | |001 = PDMA channel 9 time-out clock source is HCLK/29. 593 * | | |010 = PDMA channel 9 time-out clock source is HCLK/210. 594 * | | |011 = PDMA channel 9 time-out clock source is HCLK/211. 595 * | | |100 = PDMA channel 9 time-out clock source is HCLK/212. 596 * | | |101 = PDMA channel 9 time-out clock source is HCLK/213. 597 * | | |110 = PDMA channel 9 time-out clock source is HCLK/214. 598 * | | |111 = PDMA channel 9 time-out clock source is HCLK/215. 599 * |[10:8] |TOUTPSC10 |PDMA Channel 10 Time-out Clock Source Prescaler Bits 600 * | | |000 = PDMA channel 10 time-out clock source is HCLK/28. 601 * | | |001 = PDMA channel 10 time-out clock source is HCLK/29. 602 * | | |010 = PDMA channel 10 time-out clock source is HCLK/210. 603 * | | |011 = PDMA channel 10 time-out clock source is HCLK/211. 604 * | | |100 = PDMA channel 10 time-out clock source is HCLK/212. 605 * | | |101 = PDMA channel 10 time-out clock source is HCLK/213. 606 * | | |110 = PDMA channel 10 time-out clock source is HCLK/214. 607 * | | |111 = PDMA channel 10 time-out clock source is HCLK/215. 608 * |[14:12] |TOUTPSC11 |PDMA Channel 11 Time-out Clock Source Prescaler Bits 609 * | | |000 = PDMA channel 11 time-out clock source is HCLK/28. 610 * | | |001 = PDMA channel 11 time-out clock source is HCLK/29. 611 * | | |010 = PDMA channel 11 time-out clock source is HCLK/210. 612 * | | |011 = PDMA channel 11 time-out clock source is HCLK/211. 613 * | | |100 = PDMA channel 11 time-out clock source is HCLK/212. 614 * | | |101 = PDMA channel 11 time-out clock source is HCLK/213. 615 * | | |110 = PDMA channel 11 time-out clock source is HCLK/214. 616 * | | |111 = PDMA channel 11 time-out clock source is HCLK/215. 617 * |[18:16] |TOUTPSC12 |PDMA Channel 12 Time-out Clock Source Prescaler Bits 618 * | | |000 = PDMA channel 12 time-out clock source is HCLK/28. 619 * | | |001 = PDMA channel 12 time-out clock source is HCLK/29. 620 * | | |010 = PDMA channel 12 time-out clock source is HCLK/210. 621 * | | |011 = PDMA channel 12 time-out clock source is HCLK/211. 622 * | | |100 = PDMA channel 12 time-out clock source is HCLK/212. 623 * | | |101 = PDMA channel 12 time-out clock source is HCLK/213. 624 * | | |110 = PDMA channel 12 time-out clock source is HCLK/214. 625 * | | |111 = PDMA channel 12 time-out clock source is HCLK/215. 626 * |[22:20] |TOUTPSC13 |PDMA Channel 13 Time-out Clock Source Prescaler Bits 627 * | | |000 = PDMA channel 13 time-out clock source is HCLK/28. 628 * | | |001 = PDMA channel 13 time-out clock source is HCLK/29. 629 * | | |010 = PDMA channel 13 time-out clock source is HCLK/210. 630 * | | |011 = PDMA channel 13 time-out clock source is HCLK/211. 631 * | | |100 = PDMA channel 13 time-out clock source is HCLK/212. 632 * | | |101 = PDMA channel 13 time-out clock source is HCLK/213. 633 * | | |110 = PDMA channel 13 time-out clock source is HCLK/214. 634 * | | |111 = PDMA channel 13 time-out clock source is HCLK/215. 635 * |[26:24] |TOUTPSC14 |PDMA Channel 14 Time-out Clock Source Prescaler Bits 636 * | | |000 = PDMA channel 14 time-out clock source is HCLK/28. 637 * | | |001 = PDMA channel 14 time-out clock source is HCLK/29. 638 * | | |010 = PDMA channel 14 time-out clock source is HCLK/210. 639 * | | |011 = PDMA channel 14 time-out clock source is HCLK/211. 640 * | | |100 = PDMA channel 14 time-out clock source is HCLK/212. 641 * | | |101 = PDMA channel 14 time-out clock source is HCLK/213. 642 * | | |110 = PDMA channel 14 time-out clock source is HCLK/214. 643 * | | |111 = PDMA channel 14 time-out clock source is HCLK/215. 644 * |[30:28] |TOUTPSC15 |PDMA Channel 15 Time-out Clock Source Prescaler Bits 645 * | | |000 = PDMA channel 15 time-out clock source is HCLK/28. 646 * | | |001 = PDMA channel 15 time-out clock source is HCLK/29. 647 * | | |010 = PDMA channel 15 time-out clock source is HCLK/210. 648 * | | |011 = PDMA channel 15 time-out clock source is HCLK/211. 649 * | | |100 = PDMA channel 15 time-out clock source is HCLK/212. 650 * | | |101 = PDMA channel 15 time-out clock source is HCLK/213. 651 * | | |110 = PDMA channel 15 time-out clock source is HCLK/214. 652 * | | |111 = PDMA channel 15 time-out clock source is HCLK/215. 653 * @var PDMA_T::REQSEL0_3 654 * Offset: 0x480 PDMA Request Source Select Register 0 655 * --------------------------------------------------------------------------------------------------- 656 * |Bits |Field |Descriptions 657 * | :----: | :----: | :---- | 658 * |[6:0] |REQSRC0 |Channel 0 Request Source Selection 659 * | | |This filed defines which peripheral is connected to PDMA channel 0 660 * | | |User can configure the peripheral by setting REQSRC0. 661 * | | |0 = Disable PDMA peripheral request. 662 * | | |1 = Reserved. 663 * | | |2 = Channel connects to USB_TX. 664 * | | |3 = Channel connects to USB_RX. 665 * | | |4 = Channel connects to UART0_TX. 666 * | | |5 = Channel connects to UART0_RX. 667 * | | |6 = Channel connects to UART1_TX. 668 * | | |7 = Channel connects to UART1_RX. 669 * | | |8 = Channel connects to UART2_TX. 670 * | | |9 = Channel connects to UART2_RX. 671 * | | |10=Channel connects to UART3_TX. 672 * | | |11 = Channel connects to UART3_RX. 673 * | | |12 = Channel connects to UART4_TX. 674 * | | |13 = Channel connects to UART4_RX. 675 * | | |14 = Channel connects to UART5_TX. 676 * | | |15 = Channel connects to UART5_RX. 677 * | | |16 = Channel connects to USCI0_TX. 678 * | | |17 = Channel connects to USCI0_RX. 679 * | | |18 = Reserved. 680 * | | |19 = Reserved. 681 * | | |20 = Channel connects to QSPI0_TX. 682 * | | |21 = Channel connects to QSPI0_RX. 683 * | | |22 = Channel connects to SPI0_TX. 684 * | | |23 = Channel connects to SPI0_RX. 685 * | | |24 = Channel connects to SPI1_TX. 686 * | | |25 = Channel connects to SPI1_RX. 687 * | | |26 = Channel connects to SPI2_TX. 688 * | | |27 = Channel connects to SPI2_RX. 689 * | | |28 = Channel connects to SPI3_TX. 690 * | | |29 = Channel connects to SPI3_RX. 691 * | | |30 = Channel connects to QSPI1_TX 692 * | | |31 = Channel connects to QSPI1_RX. 693 * | | |32 = Channel connects to EPWM0_P1_RX. 694 * | | |33 = Channel connects to EPWM0_P2_RX. 695 * | | |34 = Channel connects to EPWM0_P3_RX. 696 * | | |35 = Channel connects to EPWM1_P1_RX. 697 * | | |36 = Channel connects to EPWM1_P2_RX. 698 * | | |37 = Channel connects to EPWM1_P3_RX. 699 * | | |38 = Channel connects to I2C0_TX. 700 * | | |39 = Channel connects to I2C0_RX. 701 * | | |40 = Channel connects to I2C1_TX. 702 * | | |41 = Channel connects to I2C1_RX. 703 * | | |42 = Channel connects to I2C2_TX. 704 * | | |43 = Channel connects to I2C2_RX. 705 * | | |44 = Channel connects to I2S0_TX. 706 * | | |45 = Channel connects to I2S0_RX. 707 * | | |46 = Channel connects to TMR0. 708 * | | |47 = Channel connects to TMR1. 709 * | | |48 = Channel connects to TMR2. 710 * | | |49 = Channel connects to TMR3. 711 * | | |50 = Channel connects to ADC0_RX. 712 * | | |51 = Channel connects to DAC0_TX. 713 * | | |52 = Channel connects to DAC1_TX. 714 * | | |53 = Channel connects to EPWM0_CH0_TX. 715 * | | |54 = Channel connects to EPWM0_CH1_TX. 716 * | | |55 = Channel connects to EPWM0_CH2_TX. 717 * | | |56 = Channel connects to EPWM0_CH3_TX. 718 * | | |57 = Channel connects to EPWM0_CH4_TX. 719 * | | |58 = Channel connects to EPWM0_CH5_TX. 720 * | | |59 = Channel connects to EPWM1_CH0_TX. 721 * | | |60 = Channel connects to EPWM1_CH1_TX. 722 * | | |61 = Channel connects to EPWM1_CH2_TX. 723 * | | |62 = Channel connects to EPWM1_CH3_TX. 724 * | | |63 = Channel connects to EPWM1_CH4_TX. 725 * | | |64 = Channel connects to EPWM1_CH5_TX. 726 * | | |65 = Reserved. 727 * | | |66 = Channel connects to UART6_TX. 728 * | | |67 = Channel connects to UART6_RX. 729 * | | |68 = Channel connects to UART7_TX. 730 * | | |69 = Channel connects to UART7_RX. 731 * | | |70 = Channel connects to ADC1_RX. 732 * | | |71 = Channel connects to ACMP0. 733 * | | |72 = Channel connects to ACMP1. 734 * | | |73 = Channel connects to PSIO_TX. 735 * | | |74 = Channel connects to PSIO_RX. 736 * | | |75 = Channel connects to I2C3_TX. 737 * | | |76 = Channel connects to I2C3_RX. 738 * | | |77 = Channel connects to I2C4_TX. 739 * | | |78 = Channel connects to I2C4_RX. 740 * | | |79 = Channel connects to I2S1_TX. 741 * | | |80 = Channel connects to I2S1_RX. 742 * | | |81 = Channel connects to EINT0. 743 * | | |82 = Channel connects to EINT1. 744 * | | |83 = Channel connects to EINT2. 745 * | | |84 = Channel connects to EINT3. 746 * | | |85 = Channel connects to EINT4. 747 * | | |86 = Channel connects to EINT5. 748 * | | |87 = Channel connects to EINT6. 749 * | | |88 = Channel connects to EINT7. 750 * | | |89 = Channel connects to UART8_TX. 751 * | | |90 = Channel connects to UART8_RX. 752 * | | |91 = Channel connects to UART9_TX. 753 * | | |92 = Channel connects to UART9_RX. 754 * | | |93 = Channel connects to ADC2_RX. 755 * | | |94 = Channel connects to ACMP2. 756 * | | |95 = Channel connects to ACMP3. 757 * | | |Others = Reserved. 758 * | | |Note 1: A peripheral can't assign to two channels at the same time. 759 * | | |Note 2: This field is useless when transfer between memory and memory. 760 * |[14:8] |REQSRC1 |Channel 1 Request Source Selection 761 * | | |This filed defines which peripheral is connected to PDMA channel 1 762 * | | |User can configure the peripheral setting by REQSRC1. 763 * | | |Note: The channel configuration is the same as REQSRC0 field 764 * | | |Please refer to the explanation of REQSRC0. 765 * |[22:16] |REQSRC2 |Channel 2 Request Source Selection 766 * | | |This filed defines which peripheral is connected to PDMA channel 2 767 * | | |User can configure the peripheral setting by REQSRC2. 768 * | | |Note: The channel configuration is the same as REQSRC0 field 769 * | | |Please refer to the explanation of REQSRC0. 770 * |[30:24] |REQSRC3 |Channel 3 Request Source Selection 771 * | | |This filed defines which peripheral is connected to PDMA channel 3 772 * | | |User can configure the peripheral setting by REQSRC3. 773 * | | |Note: The channel configuration is the same as REQSRC0 field 774 * | | |Please refer to the explanation of REQSRC0. 775 * @var PDMA_T::REQSEL4_7 776 * Offset: 0x484 PDMA Request Source Select Register 1 777 * --------------------------------------------------------------------------------------------------- 778 * |Bits |Field |Descriptions 779 * | :----: | :----: | :---- | 780 * |[6:0] |REQSRC4 |Channel 4 Request Source Selection 781 * | | |This filed defines which peripheral is connected to PDMA channel 4 782 * | | |User can configure the peripheral setting by REQSRC4. 783 * | | |Note: The channel configuration is the same as REQSRC0 field 784 * | | |Please refer to the explanation of REQSRC0. 785 * |[14:8] |REQSRC5 |Channel 5 Request Source Selection 786 * | | |This filed defines which peripheral is connected to PDMA channel 5 787 * | | |User can configure the peripheral setting by REQSRC5. 788 * | | |Note: The channel configuration is the same as REQSRC0 field 789 * | | |Please refer to the explanation of REQSRC0. 790 * |[22:16] |REQSRC6 |Channel 6 Request Source Selection 791 * | | |This filed defines which peripheral is connected to PDMA channel 6 792 * | | |User can configure the peripheral setting by REQSRC6. 793 * | | |Note: The channel configuration is the same as REQSRC0 field 794 * | | |Please refer to the explanation of REQSRC0. 795 * |[30:24] |REQSRC7 |Channel 7 Request Source Selection 796 * | | |This filed defines which peripheral is connected to PDMA channel 7 797 * | | |User can configure the peripheral setting by REQSRC7. 798 * | | |Note: The channel configuration is the same as REQSRC0 field 799 * | | |Please refer to the explanation of REQSRC0. 800 * @var PDMA_T::REQSEL8_11 801 * Offset: 0x488 PDMA Request Source Select Register 2 802 * --------------------------------------------------------------------------------------------------- 803 * |Bits |Field |Descriptions 804 * | :----: | :----: | :---- | 805 * |[6:0] |REQSRC8 |Channel 8 Request Source Selection 806 * | | |This filed defines which peripheral is connected to PDMA channel 8 807 * | | |User can configure the peripheral setting by REQSRC8. 808 * | | |Note: The channel configuration is the same as REQSRC0 field 809 * | | |Please refer to the explanation of REQSRC0. 810 * |[14:8] |REQSRC9 |Channel 9 Request Source Selection 811 * | | |This filed defines which peripheral is connected to PDMA channel 9 812 * | | |User can configure the peripheral setting by REQSRC9. 813 * | | |Note: The channel configuration is the same as REQSRC0 field 814 * | | |Please refer to the explanation of REQSRC0. 815 * |[22:16] |REQSRC10 |Channel 10 Request Source Selection 816 * | | |This filed defines which peripheral is connected to PDMA channel 10 817 * | | |User can configure the peripheral setting by REQSRC10. 818 * | | |Note: The channel configuration is the same as REQSRC0 field 819 * | | |Please refer to the explanation of REQSRC0. 820 * |[30:24] |REQSRC11 |Channel 11 Request Source Selection 821 * | | |This filed defines which peripheral is connected to PDMA channel 11 822 * | | |User can configure the peripheral setting by REQSRC11. 823 * | | |Note: The channel configuration is the same as REQSRC0 field 824 * | | |Please refer to the explanation of REQSRC0. 825 * @var PDMA_T::REQSEL12_15 826 * Offset: 0x48C PDMA Request Source Select Register 3 827 * --------------------------------------------------------------------------------------------------- 828 * |Bits |Field |Descriptions 829 * | :----: | :----: | :---- | 830 * |[6:0] |REQSRC12 |Channel 12 Request Source Selection 831 * | | |This filed defines which peripheral is connected to PDMA channel 12 832 * | | |User can configure the peripheral setting by REQSRC12. 833 * | | |Note: The channel configuration is the same as REQSRC0 field 834 * | | |Please refer to the explanation of REQSRC0. 835 * |[14:8] |REQSRC13 |Channel 13 Request Source Selection 836 * | | |This filed defines which peripheral is connected to PDMA channel 13 837 * | | |User can configure the peripheral setting by REQSRC13. 838 * | | |Note: The channel configuration is the same as REQSRC0 field 839 * | | |Please refer to the explanation of REQSRC0. 840 * |[22:16] |REQSRC14 |Channel 14 Request Source Selection 841 * | | |This filed defines which peripheral is connected to PDMA channel 14 842 * | | |User can configure the peripheral setting by REQSRC14. 843 * | | |Note: The channel configuration is the same as REQSRC0 field 844 * | | |Please refer to the explanation of REQSRC0. 845 * |[30:24] |REQSRC15 |Channel 15 Request Source Selection 846 * | | |This filed defines which peripheral is connected to PDMA channel 15 847 * | | |User can configure the peripheral setting by REQSRC15. 848 * | | |Note: The channel configuration is the same as REQSRC0 field 849 * | | |Please refer to the explanation of REQSRC0. 850 */ 851 DSCT_T DSCT[16]; 852 __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */ 853 /// @cond HIDDEN_SYMBOLS 854 __I uint32_t RESERVE1[176]; 855 /// @endcond //HIDDEN_SYMBOLS 856 __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ 857 __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ 858 __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ 859 __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ 860 __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ 861 __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ 862 __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ 863 __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ 864 __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ 865 __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ 866 __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ 867 __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ 868 __IO uint32_t TOUTPSC0_7; /*!< [0x0430] PDMA Time-out Prescaler Register(CH0 to CH7) */ 869 __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ 870 __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ 871 __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ 872 __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch0 and Ch1 Register */ 873 __IO uint32_t TOC2_3; /*!< [0x0444] PDMA Time-out Counter Ch2 and Ch3 Register */ 874 __IO uint32_t TOC4_5; /*!< [0x0448] PDMA Time-out Counter Ch4 and Ch5 Register */ 875 __IO uint32_t TOC6_7; /*!< [0x044C] PDMA Time-out Counter Ch6 and Ch7 Register */ 876 __IO uint32_t TOC8_9; /*!< [0x0450] PDMA Time-out Counter Ch8 and Ch9 Register */ 877 __IO uint32_t TOC10_11; /*!< [0x0454] PDMA Time-out Counter Ch10 and Ch11 Register */ 878 __IO uint32_t TOC12_13; /*!< [0x0458] PDMA Time-out Counter Ch12 and Ch13 Register */ 879 __IO uint32_t TOC14_15; /*!< [0x045C] PDMA Time-out Counter Ch14 and Ch15 Register */ 880 __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ 881 /// @cond HIDDEN_SYMBOLS 882 __I uint32_t RESERVE2[1]; 883 /// @endcond //HIDDEN_SYMBOLS 884 __IO uint32_t TOUTPSC8_15; /*!< [0x0468] PDMA Time-out Prescaler Register(CH8 to CH15) */ 885 /// @cond HIDDEN_SYMBOLS 886 __I uint32_t RESERVE3[5]; 887 /// @endcond //HIDDEN_SYMBOLS 888 __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ 889 __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ 890 __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ 891 __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ 892 /// @cond HIDDEN_SYMBOLS 893 __I uint32_t RESERVE4[28]; 894 /// @endcond //HIDDEN_SYMBOLS 895 STRIDE_T STRIDE[6]; 896 /// @cond HIDDEN_SYMBOLS 897 __IO uint32_t RESERVE5[52]; 898 /// @endcond //HIDDEN_SYMBOLS 899 REPEAT_T REPEAT[2]; 900 } PDMA_T; 901 902 /** 903 @addtogroup PDMA_CONST PDMA Bit Field Definition 904 Constant Definitions for PDMA Controller 905 @{ */ 906 907 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ 908 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ 909 910 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ 911 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ 912 913 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ 914 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ 915 916 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ 917 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ 918 919 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ 920 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ 921 922 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ 923 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ 924 925 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ 926 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ 927 928 #define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ 929 #define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ 930 931 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ 932 #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ 933 934 #define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ 935 #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ 936 937 #define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ 938 #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ 939 940 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ 941 #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ 942 943 #define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ 944 #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ 945 946 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ 947 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ 948 949 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ 950 #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ 951 952 #define PDMA_CHCTL_CHEN0_Pos (0) /*!< PDMA_T::CHCTL: CHEN0 Position */ 953 #define PDMA_CHCTL_CHEN0_Msk (0x1ul << PDMA_CHCTL_CHEN0_Pos) /*!< PDMA_T::CHCTL: CHEN0 Mask */ 954 955 #define PDMA_CHCTL_CHEN1_Pos (1) /*!< PDMA_T::CHCTL: CHEN1 Position */ 956 #define PDMA_CHCTL_CHEN1_Msk (0x1ul << PDMA_CHCTL_CHEN1_Pos) /*!< PDMA_T::CHCTL: CHEN1 Mask */ 957 958 #define PDMA_CHCTL_CHEN2_Pos (2) /*!< PDMA_T::CHCTL: CHEN2 Position */ 959 #define PDMA_CHCTL_CHEN2_Msk (0x1ul << PDMA_CHCTL_CHEN2_Pos) /*!< PDMA_T::CHCTL: CHEN2 Mask */ 960 961 #define PDMA_CHCTL_CHEN3_Pos (3) /*!< PDMA_T::CHCTL: CHEN3 Position */ 962 #define PDMA_CHCTL_CHEN3_Msk (0x1ul << PDMA_CHCTL_CHEN3_Pos) /*!< PDMA_T::CHCTL: CHEN3 Mask */ 963 964 #define PDMA_CHCTL_CHEN4_Pos (4) /*!< PDMA_T::CHCTL: CHEN4 Position */ 965 #define PDMA_CHCTL_CHEN4_Msk (0x1ul << PDMA_CHCTL_CHEN4_Pos) /*!< PDMA_T::CHCTL: CHEN4 Mask */ 966 967 #define PDMA_CHCTL_CHEN5_Pos (5) /*!< PDMA_T::CHCTL: CHEN5 Position */ 968 #define PDMA_CHCTL_CHEN5_Msk (0x1ul << PDMA_CHCTL_CHEN5_Pos) /*!< PDMA_T::CHCTL: CHEN5 Mask */ 969 970 #define PDMA_CHCTL_CHEN6_Pos (6) /*!< PDMA_T::CHCTL: CHEN6 Position */ 971 #define PDMA_CHCTL_CHEN6_Msk (0x1ul << PDMA_CHCTL_CHEN6_Pos) /*!< PDMA_T::CHCTL: CHEN6 Mask */ 972 973 #define PDMA_CHCTL_CHEN7_Pos (7) /*!< PDMA_T::CHCTL: CHEN7 Position */ 974 #define PDMA_CHCTL_CHEN7_Msk (0x1ul << PDMA_CHCTL_CHEN7_Pos) /*!< PDMA_T::CHCTL: CHEN7 Mask */ 975 976 #define PDMA_CHCTL_CHEN8_Pos (8) /*!< PDMA_T::CHCTL: CHEN8 Position */ 977 #define PDMA_CHCTL_CHEN8_Msk (0x1ul << PDMA_CHCTL_CHEN8_Pos) /*!< PDMA_T::CHCTL: CHEN8 Mask */ 978 979 #define PDMA_CHCTL_CHEN9_Pos (9) /*!< PDMA_T::CHCTL: CHEN9 Position */ 980 #define PDMA_CHCTL_CHEN9_Msk (0x1ul << PDMA_CHCTL_CHEN9_Pos) /*!< PDMA_T::CHCTL: CHEN9 Mask */ 981 982 #define PDMA_CHCTL_CHEN10_Pos (10) /*!< PDMA_T::CHCTL: CHEN10 Position */ 983 #define PDMA_CHCTL_CHEN10_Msk (0x1ul << PDMA_CHCTL_CHEN10_Pos) /*!< PDMA_T::CHCTL: CHEN10 Mask */ 984 985 #define PDMA_CHCTL_CHEN11_Pos (11) /*!< PDMA_T::CHCTL: CHEN11 Position */ 986 #define PDMA_CHCTL_CHEN11_Msk (0x1ul << PDMA_CHCTL_CHEN11_Pos) /*!< PDMA_T::CHCTL: CHEN11 Mask */ 987 988 #define PDMA_CHCTL_CHEN12_Pos (12) /*!< PDMA_T::CHCTL: CHEN12 Position */ 989 #define PDMA_CHCTL_CHEN12_Msk (0x1ul << PDMA_CHCTL_CHEN12_Pos) /*!< PDMA_T::CHCTL: CHEN12 Mask */ 990 991 #define PDMA_CHCTL_CHEN13_Pos (13) /*!< PDMA_T::CHCTL: CHEN13 Position */ 992 #define PDMA_CHCTL_CHEN13_Msk (0x1ul << PDMA_CHCTL_CHEN13_Pos) /*!< PDMA_T::CHCTL: CHEN13 Mask */ 993 994 #define PDMA_CHCTL_CHEN14_Pos (14) /*!< PDMA_T::CHCTL: CHEN14 Position */ 995 #define PDMA_CHCTL_CHEN14_Msk (0x1ul << PDMA_CHCTL_CHEN14_Pos) /*!< PDMA_T::CHCTL: CHEN14 Mask */ 996 997 #define PDMA_CHCTL_CHEN15_Pos (15) /*!< PDMA_T::CHCTL: CHEN15 Position */ 998 #define PDMA_CHCTL_CHEN15_Msk (0x1ul << PDMA_CHCTL_CHEN15_Pos) /*!< PDMA_T::CHCTL: CHEN15 Mask */ 999 1000 #define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ 1001 #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ 1002 1003 #define PDMA_PAUSE_PAUSE0_Pos (0) /*!< PDMA_T::PAUSE: PAUSE0 Position */ 1004 #define PDMA_PAUSE_PAUSE0_Msk (0x1ul << PDMA_PAUSE_PAUSE0_Pos) /*!< PDMA_T::PAUSE: PAUSE0 Mask */ 1005 1006 #define PDMA_PAUSE_PAUSE1_Pos (1) /*!< PDMA_T::PAUSE: PAUSE1 Position */ 1007 #define PDMA_PAUSE_PAUSE1_Msk (0x1ul << PDMA_PAUSE_PAUSE1_Pos) /*!< PDMA_T::PAUSE: PAUSE1 Mask */ 1008 1009 #define PDMA_PAUSE_PAUSE2_Pos (2) /*!< PDMA_T::PAUSE: PAUSE2 Position */ 1010 #define PDMA_PAUSE_PAUSE2_Msk (0x1ul << PDMA_PAUSE_PAUSE2_Pos) /*!< PDMA_T::PAUSE: PAUSE2 Mask */ 1011 1012 #define PDMA_PAUSE_PAUSE3_Pos (3) /*!< PDMA_T::PAUSE: PAUSE3 Position */ 1013 #define PDMA_PAUSE_PAUSE3_Msk (0x1ul << PDMA_PAUSE_PAUSE3_Pos) /*!< PDMA_T::PAUSE: PAUSE3 Mask */ 1014 1015 #define PDMA_PAUSE_PAUSE4_Pos (4) /*!< PDMA_T::PAUSE: PAUSE4 Position */ 1016 #define PDMA_PAUSE_PAUSE4_Msk (0x1ul << PDMA_PAUSE_PAUSE4_Pos) /*!< PDMA_T::PAUSE: PAUSE4 Mask */ 1017 1018 #define PDMA_PAUSE_PAUSE5_Pos (5) /*!< PDMA_T::PAUSE: PAUSE5 Position */ 1019 #define PDMA_PAUSE_PAUSE5_Msk (0x1ul << PDMA_PAUSE_PAUSE5_Pos) /*!< PDMA_T::PAUSE: PAUSE5 Mask */ 1020 1021 #define PDMA_PAUSE_PAUSE6_Pos (6) /*!< PDMA_T::PAUSE: PAUSE6 Position */ 1022 #define PDMA_PAUSE_PAUSE6_Msk (0x1ul << PDMA_PAUSE_PAUSE6_Pos) /*!< PDMA_T::PAUSE: PAUSE6 Mask */ 1023 1024 #define PDMA_PAUSE_PAUSE7_Pos (7) /*!< PDMA_T::PAUSE: PAUSE7 Position */ 1025 #define PDMA_PAUSE_PAUSE7_Msk (0x1ul << PDMA_PAUSE_PAUSE7_Pos) /*!< PDMA_T::PAUSE: PAUSE7 Mask */ 1026 1027 #define PDMA_PAUSE_PAUSE8_Pos (8) /*!< PDMA_T::PAUSE: PAUSE8 Position */ 1028 #define PDMA_PAUSE_PAUSE8_Msk (0x1ul << PDMA_PAUSE_PAUSE8_Pos) /*!< PDMA_T::PAUSE: PAUSE8 Mask */ 1029 1030 #define PDMA_PAUSE_PAUSE9_Pos (9) /*!< PDMA_T::PAUSE: PAUSE9 Position */ 1031 #define PDMA_PAUSE_PAUSE9_Msk (0x1ul << PDMA_PAUSE_PAUSE9_Pos) /*!< PDMA_T::PAUSE: PAUSE9 Mask */ 1032 1033 #define PDMA_PAUSE_PAUSE10_Pos (10) /*!< PDMA_T::PAUSE: PAUSE10 Position */ 1034 #define PDMA_PAUSE_PAUSE10_Msk (0x1ul << PDMA_PAUSE_PAUSE10_Pos) /*!< PDMA_T::PAUSE: PAUSE10 Mask */ 1035 1036 #define PDMA_PAUSE_PAUSE11_Pos (11) /*!< PDMA_T::PAUSE: PAUSE11 Position */ 1037 #define PDMA_PAUSE_PAUSE11_Msk (0x1ul << PDMA_PAUSE_PAUSE11_Pos) /*!< PDMA_T::PAUSE: PAUSE11 Mask */ 1038 1039 #define PDMA_PAUSE_PAUSE12_Pos (12) /*!< PDMA_T::PAUSE: PAUSE12 Position */ 1040 #define PDMA_PAUSE_PAUSE12_Msk (0x1ul << PDMA_PAUSE_PAUSE12_Pos) /*!< PDMA_T::PAUSE: PAUSE12 Mask */ 1041 1042 #define PDMA_PAUSE_PAUSE13_Pos (13) /*!< PDMA_T::PAUSE: PAUSE13 Position */ 1043 #define PDMA_PAUSE_PAUSE13_Msk (0x1ul << PDMA_PAUSE_PAUSE13_Pos) /*!< PDMA_T::PAUSE: PAUSE13 Mask */ 1044 1045 #define PDMA_PAUSE_PAUSE14_Pos (14) /*!< PDMA_T::PAUSE: PAUSE14 Position */ 1046 #define PDMA_PAUSE_PAUSE14_Msk (0x1ul << PDMA_PAUSE_PAUSE14_Pos) /*!< PDMA_T::PAUSE: PAUSE14 Mask */ 1047 1048 #define PDMA_PAUSE_PAUSE15_Pos (15) /*!< PDMA_T::PAUSE: PAUSE15 Position */ 1049 #define PDMA_PAUSE_PAUSE15_Msk (0x1ul << PDMA_PAUSE_PAUSE15_Pos) /*!< PDMA_T::PAUSE: PAUSE15 Mask */ 1050 1051 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ 1052 #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ 1053 1054 #define PDMA_SWREQ_SWREQ0_Pos (0) /*!< PDMA_T::SWREQ: SWREQ0 Position */ 1055 #define PDMA_SWREQ_SWREQ0_Msk (0x1ul << PDMA_SWREQ_SWREQ0_Pos) /*!< PDMA_T::SWREQ: SWREQ0 Mask */ 1056 1057 #define PDMA_SWREQ_SWREQ1_Pos (1) /*!< PDMA_T::SWREQ: SWREQ1 Position */ 1058 #define PDMA_SWREQ_SWREQ1_Msk (0x1ul << PDMA_SWREQ_SWREQ1_Pos) /*!< PDMA_T::SWREQ: SWREQ1 Mask */ 1059 1060 #define PDMA_SWREQ_SWREQ2_Pos (2) /*!< PDMA_T::SWREQ: SWREQ2 Position */ 1061 #define PDMA_SWREQ_SWREQ2_Msk (0x1ul << PDMA_SWREQ_SWREQ2_Pos) /*!< PDMA_T::SWREQ: SWREQ2 Mask */ 1062 1063 #define PDMA_SWREQ_SWREQ3_Pos (3) /*!< PDMA_T::SWREQ: SWREQ3 Position */ 1064 #define PDMA_SWREQ_SWREQ3_Msk (0x1ul << PDMA_SWREQ_SWREQ3_Pos) /*!< PDMA_T::SWREQ: SWREQ3 Mask */ 1065 1066 #define PDMA_SWREQ_SWREQ4_Pos (4) /*!< PDMA_T::SWREQ: SWREQ4 Position */ 1067 #define PDMA_SWREQ_SWREQ4_Msk (0x1ul << PDMA_SWREQ_SWREQ4_Pos) /*!< PDMA_T::SWREQ: SWREQ4 Mask */ 1068 1069 #define PDMA_SWREQ_SWREQ5_Pos (5) /*!< PDMA_T::SWREQ: SWREQ5 Position */ 1070 #define PDMA_SWREQ_SWREQ5_Msk (0x1ul << PDMA_SWREQ_SWREQ5_Pos) /*!< PDMA_T::SWREQ: SWREQ5 Mask */ 1071 1072 #define PDMA_SWREQ_SWREQ6_Pos (6) /*!< PDMA_T::SWREQ: SWREQ6 Position */ 1073 #define PDMA_SWREQ_SWREQ6_Msk (0x1ul << PDMA_SWREQ_SWREQ6_Pos) /*!< PDMA_T::SWREQ: SWREQ6 Mask */ 1074 1075 #define PDMA_SWREQ_SWREQ7_Pos (7) /*!< PDMA_T::SWREQ: SWREQ7 Position */ 1076 #define PDMA_SWREQ_SWREQ7_Msk (0x1ul << PDMA_SWREQ_SWREQ7_Pos) /*!< PDMA_T::SWREQ: SWREQ7 Mask */ 1077 1078 #define PDMA_SWREQ_SWREQ8_Pos (8) /*!< PDMA_T::SWREQ: SWREQ8 Position */ 1079 #define PDMA_SWREQ_SWREQ8_Msk (0x1ul << PDMA_SWREQ_SWREQ8_Pos) /*!< PDMA_T::SWREQ: SWREQ8 Mask */ 1080 1081 #define PDMA_SWREQ_SWREQ9_Pos (9) /*!< PDMA_T::SWREQ: SWREQ9 Position */ 1082 #define PDMA_SWREQ_SWREQ9_Msk (0x1ul << PDMA_SWREQ_SWREQ9_Pos) /*!< PDMA_T::SWREQ: SWREQ9 Mask */ 1083 1084 #define PDMA_SWREQ_SWREQ10_Pos (10) /*!< PDMA_T::SWREQ: SWREQ10 Position */ 1085 #define PDMA_SWREQ_SWREQ10_Msk (0x1ul << PDMA_SWREQ_SWREQ10_Pos) /*!< PDMA_T::SWREQ: SWREQ10 Mask */ 1086 1087 #define PDMA_SWREQ_SWREQ11_Pos (11) /*!< PDMA_T::SWREQ: SWREQ11 Position */ 1088 #define PDMA_SWREQ_SWREQ11_Msk (0x1ul << PDMA_SWREQ_SWREQ11_Pos) /*!< PDMA_T::SWREQ: SWREQ11 Mask */ 1089 1090 #define PDMA_SWREQ_SWREQ12_Pos (12) /*!< PDMA_T::SWREQ: SWREQ12 Position */ 1091 #define PDMA_SWREQ_SWREQ12_Msk (0x1ul << PDMA_SWREQ_SWREQ12_Pos) /*!< PDMA_T::SWREQ: SWREQ12 Mask */ 1092 1093 #define PDMA_SWREQ_SWREQ13_Pos (13) /*!< PDMA_T::SWREQ: SWREQ13 Position */ 1094 #define PDMA_SWREQ_SWREQ13_Msk (0x1ul << PDMA_SWREQ_SWREQ13_Pos) /*!< PDMA_T::SWREQ: SWREQ13 Mask */ 1095 1096 #define PDMA_SWREQ_SWREQ14_Pos (14) /*!< PDMA_T::SWREQ: SWREQ14 Position */ 1097 #define PDMA_SWREQ_SWREQ14_Msk (0x1ul << PDMA_SWREQ_SWREQ14_Pos) /*!< PDMA_T::SWREQ: SWREQ14 Mask */ 1098 1099 #define PDMA_SWREQ_SWREQ15_Pos (15) /*!< PDMA_T::SWREQ: SWREQ15 Position */ 1100 #define PDMA_SWREQ_SWREQ15_Msk (0x1ul << PDMA_SWREQ_SWREQ15_Pos) /*!< PDMA_T::SWREQ: SWREQ15 Mask */ 1101 1102 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ 1103 #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ 1104 1105 #define PDMA_TRGSTS_REQSTS0_Pos (0) /*!< PDMA_T::TRGSTS: REQSTS0 Position */ 1106 #define PDMA_TRGSTS_REQSTS0_Msk (0x1ul << PDMA_TRGSTS_REQSTS0_Pos) /*!< PDMA_T::TRGSTS: REQSTS0 Mask */ 1107 1108 #define PDMA_TRGSTS_REQSTS1_Pos (1) /*!< PDMA_T::TRGSTS: REQSTS1 Position */ 1109 #define PDMA_TRGSTS_REQSTS1_Msk (0x1ul << PDMA_TRGSTS_REQSTS1_Pos) /*!< PDMA_T::TRGSTS: REQSTS1 Mask */ 1110 1111 #define PDMA_TRGSTS_REQSTS2_Pos (2) /*!< PDMA_T::TRGSTS: REQSTS2 Position */ 1112 #define PDMA_TRGSTS_REQSTS2_Msk (0x1ul << PDMA_TRGSTS_REQSTS2_Pos) /*!< PDMA_T::TRGSTS: REQSTS2 Mask */ 1113 1114 #define PDMA_TRGSTS_REQSTS3_Pos (3) /*!< PDMA_T::TRGSTS: REQSTS3 Position */ 1115 #define PDMA_TRGSTS_REQSTS3_Msk (0x1ul << PDMA_TRGSTS_REQSTS3_Pos) /*!< PDMA_T::TRGSTS: REQSTS3 Mask */ 1116 1117 #define PDMA_TRGSTS_REQSTS4_Pos (4) /*!< PDMA_T::TRGSTS: REQSTS4 Position */ 1118 #define PDMA_TRGSTS_REQSTS4_Msk (0x1ul << PDMA_TRGSTS_REQSTS4_Pos) /*!< PDMA_T::TRGSTS: REQSTS4 Mask */ 1119 1120 #define PDMA_TRGSTS_REQSTS5_Pos (5) /*!< PDMA_T::TRGSTS: REQSTS5 Position */ 1121 #define PDMA_TRGSTS_REQSTS5_Msk (0x1ul << PDMA_TRGSTS_REQSTS5_Pos) /*!< PDMA_T::TRGSTS: REQSTS5 Mask */ 1122 1123 #define PDMA_TRGSTS_REQSTS6_Pos (6) /*!< PDMA_T::TRGSTS: REQSTS6 Position */ 1124 #define PDMA_TRGSTS_REQSTS6_Msk (0x1ul << PDMA_TRGSTS_REQSTS6_Pos) /*!< PDMA_T::TRGSTS: REQSTS6 Mask */ 1125 1126 #define PDMA_TRGSTS_REQSTS7_Pos (7) /*!< PDMA_T::TRGSTS: REQSTS7 Position */ 1127 #define PDMA_TRGSTS_REQSTS7_Msk (0x1ul << PDMA_TRGSTS_REQSTS7_Pos) /*!< PDMA_T::TRGSTS: REQSTS7 Mask */ 1128 1129 #define PDMA_TRGSTS_REQSTS8_Pos (8) /*!< PDMA_T::TRGSTS: REQSTS8 Position */ 1130 #define PDMA_TRGSTS_REQSTS8_Msk (0x1ul << PDMA_TRGSTS_REQSTS8_Pos) /*!< PDMA_T::TRGSTS: REQSTS8 Mask */ 1131 1132 #define PDMA_TRGSTS_REQSTS9_Pos (9) /*!< PDMA_T::TRGSTS: REQSTS9 Position */ 1133 #define PDMA_TRGSTS_REQSTS9_Msk (0x1ul << PDMA_TRGSTS_REQSTS9_Pos) /*!< PDMA_T::TRGSTS: REQSTS9 Mask */ 1134 1135 #define PDMA_TRGSTS_REQSTS10_Pos (10) /*!< PDMA_T::TRGSTS: REQSTS10 Position */ 1136 #define PDMA_TRGSTS_REQSTS10_Msk (0x1ul << PDMA_TRGSTS_REQSTS10_Pos) /*!< PDMA_T::TRGSTS: REQSTS10 Mask */ 1137 1138 #define PDMA_TRGSTS_REQSTS11_Pos (11) /*!< PDMA_T::TRGSTS: REQSTS11 Position */ 1139 #define PDMA_TRGSTS_REQSTS11_Msk (0x1ul << PDMA_TRGSTS_REQSTS11_Pos) /*!< PDMA_T::TRGSTS: REQSTS11 Mask */ 1140 1141 #define PDMA_TRGSTS_REQSTS12_Pos (12) /*!< PDMA_T::TRGSTS: REQSTS12 Position */ 1142 #define PDMA_TRGSTS_REQSTS12_Msk (0x1ul << PDMA_TRGSTS_REQSTS12_Pos) /*!< PDMA_T::TRGSTS: REQSTS12 Mask */ 1143 1144 #define PDMA_TRGSTS_REQSTS13_Pos (13) /*!< PDMA_T::TRGSTS: REQSTS13 Position */ 1145 #define PDMA_TRGSTS_REQSTS13_Msk (0x1ul << PDMA_TRGSTS_REQSTS13_Pos) /*!< PDMA_T::TRGSTS: REQSTS13 Mask */ 1146 1147 #define PDMA_TRGSTS_REQSTS14_Pos (14) /*!< PDMA_T::TRGSTS: REQSTS14 Position */ 1148 #define PDMA_TRGSTS_REQSTS14_Msk (0x1ul << PDMA_TRGSTS_REQSTS14_Pos) /*!< PDMA_T::TRGSTS: REQSTS14 Mask */ 1149 1150 #define PDMA_TRGSTS_REQSTS15_Pos (15) /*!< PDMA_T::TRGSTS: REQSTS15 Position */ 1151 #define PDMA_TRGSTS_REQSTS15_Msk (0x1ul << PDMA_TRGSTS_REQSTS15_Pos) /*!< PDMA_T::TRGSTS: REQSTS15 Mask */ 1152 1153 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ 1154 #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ 1155 1156 #define PDMA_PRISET_FPRISET0_Pos (0) /*!< PDMA_T::PRISET: FPRISET0 Position */ 1157 #define PDMA_PRISET_FPRISET0_Msk (0x1ul << PDMA_PRISET_FPRISET0_Pos) /*!< PDMA_T::PRISET: FPRISET0 Mask */ 1158 1159 #define PDMA_PRISET_FPRISET1_Pos (1) /*!< PDMA_T::PRISET: FPRISET1 Position */ 1160 #define PDMA_PRISET_FPRISET1_Msk (0x1ul << PDMA_PRISET_FPRISET1_Pos) /*!< PDMA_T::PRISET: FPRISET1 Mask */ 1161 1162 #define PDMA_PRISET_FPRISET2_Pos (2) /*!< PDMA_T::PRISET: FPRISET2 Position */ 1163 #define PDMA_PRISET_FPRISET2_Msk (0x1ul << PDMA_PRISET_FPRISET2_Pos) /*!< PDMA_T::PRISET: FPRISET2 Mask */ 1164 1165 #define PDMA_PRISET_FPRISET3_Pos (3) /*!< PDMA_T::PRISET: FPRISET3 Position */ 1166 #define PDMA_PRISET_FPRISET3_Msk (0x1ul << PDMA_PRISET_FPRISET3_Pos) /*!< PDMA_T::PRISET: FPRISET3 Mask */ 1167 1168 #define PDMA_PRISET_FPRISET4_Pos (4) /*!< PDMA_T::PRISET: FPRISET4 Position */ 1169 #define PDMA_PRISET_FPRISET4_Msk (0x1ul << PDMA_PRISET_FPRISET4_Pos) /*!< PDMA_T::PRISET: FPRISET4 Mask */ 1170 1171 #define PDMA_PRISET_FPRISET5_Pos (5) /*!< PDMA_T::PRISET: FPRISET5 Position */ 1172 #define PDMA_PRISET_FPRISET5_Msk (0x1ul << PDMA_PRISET_FPRISET5_Pos) /*!< PDMA_T::PRISET: FPRISET5 Mask */ 1173 1174 #define PDMA_PRISET_FPRISET6_Pos (6) /*!< PDMA_T::PRISET: FPRISET6 Position */ 1175 #define PDMA_PRISET_FPRISET6_Msk (0x1ul << PDMA_PRISET_FPRISET6_Pos) /*!< PDMA_T::PRISET: FPRISET6 Mask */ 1176 1177 #define PDMA_PRISET_FPRISET7_Pos (7) /*!< PDMA_T::PRISET: FPRISET7 Position */ 1178 #define PDMA_PRISET_FPRISET7_Msk (0x1ul << PDMA_PRISET_FPRISET7_Pos) /*!< PDMA_T::PRISET: FPRISET7 Mask */ 1179 1180 #define PDMA_PRISET_FPRISET8_Pos (8) /*!< PDMA_T::PRISET: FPRISET8 Position */ 1181 #define PDMA_PRISET_FPRISET8_Msk (0x1ul << PDMA_PRISET_FPRISET8_Pos) /*!< PDMA_T::PRISET: FPRISET8 Mask */ 1182 1183 #define PDMA_PRISET_FPRISET9_Pos (9) /*!< PDMA_T::PRISET: FPRISET9 Position */ 1184 #define PDMA_PRISET_FPRISET9_Msk (0x1ul << PDMA_PRISET_FPRISET9_Pos) /*!< PDMA_T::PRISET: FPRISET9 Mask */ 1185 1186 #define PDMA_PRISET_FPRISET10_Pos (10) /*!< PDMA_T::PRISET: FPRISET10 Position */ 1187 #define PDMA_PRISET_FPRISET10_Msk (0x1ul << PDMA_PRISET_FPRISET10_Pos) /*!< PDMA_T::PRISET: FPRISET10 Mask */ 1188 1189 #define PDMA_PRISET_FPRISET11_Pos (11) /*!< PDMA_T::PRISET: FPRISET11 Position */ 1190 #define PDMA_PRISET_FPRISET11_Msk (0x1ul << PDMA_PRISET_FPRISET11_Pos) /*!< PDMA_T::PRISET: FPRISET11 Mask */ 1191 1192 #define PDMA_PRISET_FPRISET12_Pos (12) /*!< PDMA_T::PRISET: FPRISET12 Position */ 1193 #define PDMA_PRISET_FPRISET12_Msk (0x1ul << PDMA_PRISET_FPRISET12_Pos) /*!< PDMA_T::PRISET: FPRISET12 Mask */ 1194 1195 #define PDMA_PRISET_FPRISET13_Pos (13) /*!< PDMA_T::PRISET: FPRISET13 Position */ 1196 #define PDMA_PRISET_FPRISET13_Msk (0x1ul << PDMA_PRISET_FPRISET13_Pos) /*!< PDMA_T::PRISET: FPRISET13 Mask */ 1197 1198 #define PDMA_PRISET_FPRISET14_Pos (14) /*!< PDMA_T::PRISET: FPRISET14 Position */ 1199 #define PDMA_PRISET_FPRISET14_Msk (0x1ul << PDMA_PRISET_FPRISET14_Pos) /*!< PDMA_T::PRISET: FPRISET14 Mask */ 1200 1201 #define PDMA_PRISET_FPRISET15_Pos (15) /*!< PDMA_T::PRISET: FPRISET15 Position */ 1202 #define PDMA_PRISET_FPRISET15_Msk (0x1ul << PDMA_PRISET_FPRISET15_Pos) /*!< PDMA_T::PRISET: FPRISET15 Mask */ 1203 1204 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ 1205 #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ 1206 1207 #define PDMA_PRICLR_FPRICLR0_Pos (0) /*!< PDMA_T::PRICLR: FPRICLR0 Position */ 1208 #define PDMA_PRICLR_FPRICLR0_Msk (0x1ul << PDMA_PRICLR_FPRICLR0_Pos) /*!< PDMA_T::PRICLR: FPRICLR0 Mask */ 1209 1210 #define PDMA_PRICLR_FPRICLR1_Pos (1) /*!< PDMA_T::PRICLR: FPRICLR1 Position */ 1211 #define PDMA_PRICLR_FPRICLR1_Msk (0x1ul << PDMA_PRICLR_FPRICLR1_Pos) /*!< PDMA_T::PRICLR: FPRICLR1 Mask */ 1212 1213 #define PDMA_PRICLR_FPRICLR2_Pos (2) /*!< PDMA_T::PRICLR: FPRICLR2 Position */ 1214 #define PDMA_PRICLR_FPRICLR2_Msk (0x1ul << PDMA_PRICLR_FPRICLR2_Pos) /*!< PDMA_T::PRICLR: FPRICLR2 Mask */ 1215 1216 #define PDMA_PRICLR_FPRICLR3_Pos (3) /*!< PDMA_T::PRICLR: FPRICLR3 Position */ 1217 #define PDMA_PRICLR_FPRICLR3_Msk (0x1ul << PDMA_PRICLR_FPRICLR3_Pos) /*!< PDMA_T::PRICLR: FPRICLR3 Mask */ 1218 1219 #define PDMA_PRICLR_FPRICLR4_Pos (4) /*!< PDMA_T::PRICLR: FPRICLR4 Position */ 1220 #define PDMA_PRICLR_FPRICLR4_Msk (0x1ul << PDMA_PRICLR_FPRICLR4_Pos) /*!< PDMA_T::PRICLR: FPRICLR4 Mask */ 1221 1222 #define PDMA_PRICLR_FPRICLR5_Pos (5) /*!< PDMA_T::PRICLR: FPRICLR5 Position */ 1223 #define PDMA_PRICLR_FPRICLR5_Msk (0x1ul << PDMA_PRICLR_FPRICLR5_Pos) /*!< PDMA_T::PRICLR: FPRICLR5 Mask */ 1224 1225 #define PDMA_PRICLR_FPRICLR6_Pos (6) /*!< PDMA_T::PRICLR: FPRICLR6 Position */ 1226 #define PDMA_PRICLR_FPRICLR6_Msk (0x1ul << PDMA_PRICLR_FPRICLR6_Pos) /*!< PDMA_T::PRICLR: FPRICLR6 Mask */ 1227 1228 #define PDMA_PRICLR_FPRICLR7_Pos (7) /*!< PDMA_T::PRICLR: FPRICLR7 Position */ 1229 #define PDMA_PRICLR_FPRICLR7_Msk (0x1ul << PDMA_PRICLR_FPRICLR7_Pos) /*!< PDMA_T::PRICLR: FPRICLR7 Mask */ 1230 1231 #define PDMA_PRICLR_FPRICLR8_Pos (8) /*!< PDMA_T::PRICLR: FPRICLR8 Position */ 1232 #define PDMA_PRICLR_FPRICLR8_Msk (0x1ul << PDMA_PRICLR_FPRICLR8_Pos) /*!< PDMA_T::PRICLR: FPRICLR8 Mask */ 1233 1234 #define PDMA_PRICLR_FPRICLR9_Pos (9) /*!< PDMA_T::PRICLR: FPRICLR9 Position */ 1235 #define PDMA_PRICLR_FPRICLR9_Msk (0x1ul << PDMA_PRICLR_FPRICLR9_Pos) /*!< PDMA_T::PRICLR: FPRICLR9 Mask */ 1236 1237 #define PDMA_PRICLR_FPRICLR10_Pos (10) /*!< PDMA_T::PRICLR: FPRICLR10 Position */ 1238 #define PDMA_PRICLR_FPRICLR10_Msk (0x1ul << PDMA_PRICLR_FPRICLR10_Pos) /*!< PDMA_T::PRICLR: FPRICLR10 Mask */ 1239 1240 #define PDMA_PRICLR_FPRICLR11_Pos (11) /*!< PDMA_T::PRICLR: FPRICLR11 Position */ 1241 #define PDMA_PRICLR_FPRICLR11_Msk (0x1ul << PDMA_PRICLR_FPRICLR11_Pos) /*!< PDMA_T::PRICLR: FPRICLR11 Mask */ 1242 1243 #define PDMA_PRICLR_FPRICLR12_Pos (12) /*!< PDMA_T::PRICLR: FPRICLR12 Position */ 1244 #define PDMA_PRICLR_FPRICLR12_Msk (0x1ul << PDMA_PRICLR_FPRICLR12_Pos) /*!< PDMA_T::PRICLR: FPRICLR12 Mask */ 1245 1246 #define PDMA_PRICLR_FPRICLR13_Pos (13) /*!< PDMA_T::PRICLR: FPRICLR13 Position */ 1247 #define PDMA_PRICLR_FPRICLR13_Msk (0x1ul << PDMA_PRICLR_FPRICLR13_Pos) /*!< PDMA_T::PRICLR: FPRICLR13 Mask */ 1248 1249 #define PDMA_PRICLR_FPRICLR14_Pos (14) /*!< PDMA_T::PRICLR: FPRICLR14 Position */ 1250 #define PDMA_PRICLR_FPRICLR14_Msk (0x1ul << PDMA_PRICLR_FPRICLR14_Pos) /*!< PDMA_T::PRICLR: FPRICLR14 Mask */ 1251 1252 #define PDMA_PRICLR_FPRICLR15_Pos (15) /*!< PDMA_T::PRICLR: FPRICLR15 Position */ 1253 #define PDMA_PRICLR_FPRICLR15_Msk (0x1ul << PDMA_PRICLR_FPRICLR15_Pos) /*!< PDMA_T::PRICLR: FPRICLR15 Mask */ 1254 1255 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ 1256 #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ 1257 1258 #define PDMA_INTEN_INTEN0_Pos (0) /*!< PDMA_T::INTEN: INTEN0 Position */ 1259 #define PDMA_INTEN_INTEN0_Msk (0x1ul << PDMA_INTEN_INTEN0_Pos) /*!< PDMA_T::INTEN: INTEN0 Mask */ 1260 1261 #define PDMA_INTEN_INTEN1_Pos (1) /*!< PDMA_T::INTEN: INTEN1 Position */ 1262 #define PDMA_INTEN_INTEN1_Msk (0x1ul << PDMA_INTEN_INTEN1_Pos) /*!< PDMA_T::INTEN: INTEN1 Mask */ 1263 1264 #define PDMA_INTEN_INTEN2_Pos (2) /*!< PDMA_T::INTEN: INTEN2 Position */ 1265 #define PDMA_INTEN_INTEN2_Msk (0x1ul << PDMA_INTEN_INTEN2_Pos) /*!< PDMA_T::INTEN: INTEN2 Mask */ 1266 1267 #define PDMA_INTEN_INTEN3_Pos (3) /*!< PDMA_T::INTEN: INTEN3 Position */ 1268 #define PDMA_INTEN_INTEN3_Msk (0x1ul << PDMA_INTEN_INTEN3_Pos) /*!< PDMA_T::INTEN: INTEN3 Mask */ 1269 1270 #define PDMA_INTEN_INTEN4_Pos (4) /*!< PDMA_T::INTEN: INTEN4 Position */ 1271 #define PDMA_INTEN_INTEN4_Msk (0x1ul << PDMA_INTEN_INTEN4_Pos) /*!< PDMA_T::INTEN: INTEN4 Mask */ 1272 1273 #define PDMA_INTEN_INTEN5_Pos (5) /*!< PDMA_T::INTEN: INTEN5 Position */ 1274 #define PDMA_INTEN_INTEN5_Msk (0x1ul << PDMA_INTEN_INTEN5_Pos) /*!< PDMA_T::INTEN: INTEN5 Mask */ 1275 1276 #define PDMA_INTEN_INTEN6_Pos (6) /*!< PDMA_T::INTEN: INTEN6 Position */ 1277 #define PDMA_INTEN_INTEN6_Msk (0x1ul << PDMA_INTEN_INTEN6_Pos) /*!< PDMA_T::INTEN: INTEN6 Mask */ 1278 1279 #define PDMA_INTEN_INTEN7_Pos (7) /*!< PDMA_T::INTEN: INTEN7 Position */ 1280 #define PDMA_INTEN_INTEN7_Msk (0x1ul << PDMA_INTEN_INTEN7_Pos) /*!< PDMA_T::INTEN: INTEN7 Mask */ 1281 1282 #define PDMA_INTEN_INTEN8_Pos (8) /*!< PDMA_T::INTEN: INTEN8 Position */ 1283 #define PDMA_INTEN_INTEN8_Msk (0x1ul << PDMA_INTEN_INTEN8_Pos) /*!< PDMA_T::INTEN: INTEN8 Mask */ 1284 1285 #define PDMA_INTEN_INTEN9_Pos (9) /*!< PDMA_T::INTEN: INTEN9 Position */ 1286 #define PDMA_INTEN_INTEN9_Msk (0x1ul << PDMA_INTEN_INTEN9_Pos) /*!< PDMA_T::INTEN: INTEN9 Mask */ 1287 1288 #define PDMA_INTEN_INTEN10_Pos (10) /*!< PDMA_T::INTEN: INTEN10 Position */ 1289 #define PDMA_INTEN_INTEN10_Msk (0x1ul << PDMA_INTEN_INTEN10_Pos) /*!< PDMA_T::INTEN: INTEN10 Mask */ 1290 1291 #define PDMA_INTEN_INTEN11_Pos (11) /*!< PDMA_T::INTEN: INTEN11 Position */ 1292 #define PDMA_INTEN_INTEN11_Msk (0x1ul << PDMA_INTEN_INTEN11_Pos) /*!< PDMA_T::INTEN: INTEN11 Mask */ 1293 1294 #define PDMA_INTEN_INTEN12_Pos (12) /*!< PDMA_T::INTEN: INTEN12 Position */ 1295 #define PDMA_INTEN_INTEN12_Msk (0x1ul << PDMA_INTEN_INTEN12_Pos) /*!< PDMA_T::INTEN: INTEN12 Mask */ 1296 1297 #define PDMA_INTEN_INTEN13_Pos (13) /*!< PDMA_T::INTEN: INTEN13 Position */ 1298 #define PDMA_INTEN_INTEN13_Msk (0x1ul << PDMA_INTEN_INTEN13_Pos) /*!< PDMA_T::INTEN: INTEN13 Mask */ 1299 1300 #define PDMA_INTEN_INTEN14_Pos (14) /*!< PDMA_T::INTEN: INTEN14 Position */ 1301 #define PDMA_INTEN_INTEN14_Msk (0x1ul << PDMA_INTEN_INTEN14_Pos) /*!< PDMA_T::INTEN: INTEN14 Mask */ 1302 1303 #define PDMA_INTEN_INTEN15_Pos (15) /*!< PDMA_T::INTEN: INTEN15 Position */ 1304 #define PDMA_INTEN_INTEN15_Msk (0x1ul << PDMA_INTEN_INTEN15_Pos) /*!< PDMA_T::INTEN: INTEN15 Mask */ 1305 1306 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ 1307 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ 1308 1309 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ 1310 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ 1311 1312 #define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ 1313 #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ 1314 1315 #define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ 1316 #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ 1317 1318 #define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ 1319 #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ 1320 1321 #define PDMA_INTSTS_REQTOF2_Pos (10) /*!< PDMA_T::INTSTS: REQTOF2 Position */ 1322 #define PDMA_INTSTS_REQTOF2_Msk (0x1ul << PDMA_INTSTS_REQTOF2_Pos) /*!< PDMA_T::INTSTS: REQTOF2 Mask */ 1323 1324 #define PDMA_INTSTS_REQTOF3_Pos (11) /*!< PDMA_T::INTSTS: REQTOF3 Position */ 1325 #define PDMA_INTSTS_REQTOF3_Msk (0x1ul << PDMA_INTSTS_REQTOF3_Pos) /*!< PDMA_T::INTSTS: REQTOF3 Mask */ 1326 1327 #define PDMA_INTSTS_REQTOF4_Pos (12) /*!< PDMA_T::INTSTS: REQTOF4 Position */ 1328 #define PDMA_INTSTS_REQTOF4_Msk (0x1ul << PDMA_INTSTS_REQTOF4_Pos) /*!< PDMA_T::INTSTS: REQTOF4 Mask */ 1329 1330 #define PDMA_INTSTS_REQTOF5_Pos (13) /*!< PDMA_T::INTSTS: REQTOF5 Position */ 1331 #define PDMA_INTSTS_REQTOF5_Msk (0x1ul << PDMA_INTSTS_REQTOF5_Pos) /*!< PDMA_T::INTSTS: REQTOF5 Mask */ 1332 1333 #define PDMA_INTSTS_REQTOF6_Pos (14) /*!< PDMA_T::INTSTS: REQTOF6 Position */ 1334 #define PDMA_INTSTS_REQTOF6_Msk (0x1ul << PDMA_INTSTS_REQTOF6_Pos) /*!< PDMA_T::INTSTS: REQTOF6 Mask */ 1335 1336 #define PDMA_INTSTS_REQTOF7_Pos (15) /*!< PDMA_T::INTSTS: REQTOF7 Position */ 1337 #define PDMA_INTSTS_REQTOF7_Msk (0x1ul << PDMA_INTSTS_REQTOF7_Pos) /*!< PDMA_T::INTSTS: REQTOF7 Mask */ 1338 1339 #define PDMA_INTSTS_REQTOF8_Pos (16) /*!< PDMA_T::INTSTS: REQTOF8 Position */ 1340 #define PDMA_INTSTS_REQTOF8_Msk (0x1ul << PDMA_INTSTS_REQTOF8_Pos) /*!< PDMA_T::INTSTS: REQTOF8 Mask */ 1341 1342 #define PDMA_INTSTS_REQTOF9_Pos (17) /*!< PDMA_T::INTSTS: REQTOF9 Position */ 1343 #define PDMA_INTSTS_REQTOF9_Msk (0x1ul << PDMA_INTSTS_REQTOF9_Pos) /*!< PDMA_T::INTSTS: REQTOF9 Mask */ 1344 1345 #define PDMA_INTSTS_REQTOF10_Pos (18) /*!< PDMA_T::INTSTS: REQTOF10 Position */ 1346 #define PDMA_INTSTS_REQTOF10_Msk (0x1ul << PDMA_INTSTS_REQTOF10_Pos) /*!< PDMA_T::INTSTS: REQTOF10 Mask */ 1347 1348 #define PDMA_INTSTS_REQTOF11_Pos (19) /*!< PDMA_T::INTSTS: REQTOF11 Position */ 1349 #define PDMA_INTSTS_REQTOF11_Msk (0x1ul << PDMA_INTSTS_REQTOF11_Pos) /*!< PDMA_T::INTSTS: REQTOF11 Mask */ 1350 1351 #define PDMA_INTSTS_REQTOF12_Pos (20) /*!< PDMA_T::INTSTS: REQTOF12 Position */ 1352 #define PDMA_INTSTS_REQTOF12_Msk (0x1ul << PDMA_INTSTS_REQTOF12_Pos) /*!< PDMA_T::INTSTS: REQTOF12 Mask */ 1353 1354 #define PDMA_INTSTS_REQTOF13_Pos (21) /*!< PDMA_T::INTSTS: REQTOF13 Position */ 1355 #define PDMA_INTSTS_REQTOF13_Msk (0x1ul << PDMA_INTSTS_REQTOF13_Pos) /*!< PDMA_T::INTSTS: REQTOF13 Mask */ 1356 1357 #define PDMA_INTSTS_REQTOF14_Pos (22) /*!< PDMA_T::INTSTS: REQTOF14 Position */ 1358 #define PDMA_INTSTS_REQTOF14_Msk (0x1ul << PDMA_INTSTS_REQTOF14_Pos) /*!< PDMA_T::INTSTS: REQTOF14 Mask */ 1359 1360 #define PDMA_INTSTS_REQTOF15_Pos (23) /*!< PDMA_T::INTSTS: REQTOF15 Position */ 1361 #define PDMA_INTSTS_REQTOF15_Msk (0x1ul << PDMA_INTSTS_REQTOF15_Pos) /*!< PDMA_T::INTSTS: REQTOF15 Mask */ 1362 1363 #define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ 1364 #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ 1365 1366 #define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ 1367 #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ 1368 1369 #define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ 1370 #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ 1371 1372 #define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ 1373 #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ 1374 1375 #define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ 1376 #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ 1377 1378 #define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ 1379 #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ 1380 1381 #define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ 1382 #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ 1383 1384 #define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ 1385 #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ 1386 1387 #define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ 1388 #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ 1389 1390 #define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ 1391 #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ 1392 1393 #define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ 1394 #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ 1395 1396 #define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ 1397 #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ 1398 1399 #define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ 1400 #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ 1401 1402 #define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ 1403 #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ 1404 1405 #define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ 1406 #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ 1407 1408 #define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ 1409 #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ 1410 1411 #define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ 1412 #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ 1413 1414 #define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ 1415 #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ 1416 1417 #define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ 1418 #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ 1419 1420 #define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ 1421 #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ 1422 1423 #define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ 1424 #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ 1425 1426 #define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ 1427 #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ 1428 1429 #define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ 1430 #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ 1431 1432 #define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ 1433 #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ 1434 1435 #define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ 1436 #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ 1437 1438 #define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ 1439 #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ 1440 1441 #define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ 1442 #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ 1443 1444 #define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ 1445 #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ 1446 1447 #define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ 1448 #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ 1449 1450 #define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ 1451 #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ 1452 1453 #define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ 1454 #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ 1455 1456 #define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ 1457 #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ 1458 1459 #define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ 1460 #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ 1461 1462 #define PDMA_ALIGN_ALIGN0_Pos (0) /*!< PDMA_T::ALIGN: ALIGN0 Position */ 1463 #define PDMA_ALIGN_ALIGN0_Msk (0x1ul << PDMA_ALIGN_ALIGN0_Pos) /*!< PDMA_T::ALIGN: ALIGN0 Mask */ 1464 1465 #define PDMA_ALIGN_ALIGN1_Pos (1) /*!< PDMA_T::ALIGN: ALIGN1 Position */ 1466 #define PDMA_ALIGN_ALIGN1_Msk (0x1ul << PDMA_ALIGN_ALIGN1_Pos) /*!< PDMA_T::ALIGN: ALIGN1 Mask */ 1467 1468 #define PDMA_ALIGN_ALIGN2_Pos (2) /*!< PDMA_T::ALIGN: ALIGN2 Position */ 1469 #define PDMA_ALIGN_ALIGN2_Msk (0x1ul << PDMA_ALIGN_ALIGN2_Pos) /*!< PDMA_T::ALIGN: ALIGN2 Mask */ 1470 1471 #define PDMA_ALIGN_ALIGN3_Pos (3) /*!< PDMA_T::ALIGN: ALIGN3 Position */ 1472 #define PDMA_ALIGN_ALIGN3_Msk (0x1ul << PDMA_ALIGN_ALIGN3_Pos) /*!< PDMA_T::ALIGN: ALIGN3 Mask */ 1473 1474 #define PDMA_ALIGN_ALIGN4_Pos (4) /*!< PDMA_T::ALIGN: ALIGN4 Position */ 1475 #define PDMA_ALIGN_ALIGN4_Msk (0x1ul << PDMA_ALIGN_ALIGN4_Pos) /*!< PDMA_T::ALIGN: ALIGN4 Mask */ 1476 1477 #define PDMA_ALIGN_ALIGN5_Pos (5) /*!< PDMA_T::ALIGN: ALIGN5 Position */ 1478 #define PDMA_ALIGN_ALIGN5_Msk (0x1ul << PDMA_ALIGN_ALIGN5_Pos) /*!< PDMA_T::ALIGN: ALIGN5 Mask */ 1479 1480 #define PDMA_ALIGN_ALIGN6_Pos (6) /*!< PDMA_T::ALIGN: ALIGN6 Position */ 1481 #define PDMA_ALIGN_ALIGN6_Msk (0x1ul << PDMA_ALIGN_ALIGN6_Pos) /*!< PDMA_T::ALIGN: ALIGN6 Mask */ 1482 1483 #define PDMA_ALIGN_ALIGN7_Pos (7) /*!< PDMA_T::ALIGN: ALIGN7 Position */ 1484 #define PDMA_ALIGN_ALIGN7_Msk (0x1ul << PDMA_ALIGN_ALIGN7_Pos) /*!< PDMA_T::ALIGN: ALIGN7 Mask */ 1485 1486 #define PDMA_ALIGN_ALIGN8_Pos (8) /*!< PDMA_T::ALIGN: ALIGN8 Position */ 1487 #define PDMA_ALIGN_ALIGN8_Msk (0x1ul << PDMA_ALIGN_ALIGN8_Pos) /*!< PDMA_T::ALIGN: ALIGN8 Mask */ 1488 1489 #define PDMA_ALIGN_ALIGN9_Pos (9) /*!< PDMA_T::ALIGN: ALIGN9 Position */ 1490 #define PDMA_ALIGN_ALIGN9_Msk (0x1ul << PDMA_ALIGN_ALIGN9_Pos) /*!< PDMA_T::ALIGN: ALIGN9 Mask */ 1491 1492 #define PDMA_ALIGN_ALIGN10_Pos (10) /*!< PDMA_T::ALIGN: ALIGN10 Position */ 1493 #define PDMA_ALIGN_ALIGN10_Msk (0x1ul << PDMA_ALIGN_ALIGN10_Pos) /*!< PDMA_T::ALIGN: ALIGN10 Mask */ 1494 1495 #define PDMA_ALIGN_ALIGN11_Pos (11) /*!< PDMA_T::ALIGN: ALIGN11 Position */ 1496 #define PDMA_ALIGN_ALIGN11_Msk (0x1ul << PDMA_ALIGN_ALIGN11_Pos) /*!< PDMA_T::ALIGN: ALIGN11 Mask */ 1497 1498 #define PDMA_ALIGN_ALIGN12_Pos (12) /*!< PDMA_T::ALIGN: ALIGN12 Position */ 1499 #define PDMA_ALIGN_ALIGN12_Msk (0x1ul << PDMA_ALIGN_ALIGN12_Pos) /*!< PDMA_T::ALIGN: ALIGN12 Mask */ 1500 1501 #define PDMA_ALIGN_ALIGN13_Pos (13) /*!< PDMA_T::ALIGN: ALIGN13 Position */ 1502 #define PDMA_ALIGN_ALIGN13_Msk (0x1ul << PDMA_ALIGN_ALIGN13_Pos) /*!< PDMA_T::ALIGN: ALIGN13 Mask */ 1503 1504 #define PDMA_ALIGN_ALIGN14_Pos (14) /*!< PDMA_T::ALIGN: ALIGN14 Position */ 1505 #define PDMA_ALIGN_ALIGN14_Msk (0x1ul << PDMA_ALIGN_ALIGN14_Pos) /*!< PDMA_T::ALIGN: ALIGN14 Mask */ 1506 1507 #define PDMA_ALIGN_ALIGN15_Pos (15) /*!< PDMA_T::ALIGN: ALIGN15 Position */ 1508 #define PDMA_ALIGN_ALIGN15_Msk (0x1ul << PDMA_ALIGN_ALIGN15_Pos) /*!< PDMA_T::ALIGN: ALIGN15 Mask */ 1509 1510 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ 1511 #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ 1512 1513 #define PDMA_TACTSTS_TXACTF0_Pos (0) /*!< PDMA_T::TACTSTS: TXACTF0 Position */ 1514 #define PDMA_TACTSTS_TXACTF0_Msk (0x1ul << PDMA_TACTSTS_TXACTF0_Pos) /*!< PDMA_T::TACTSTS: TXACTF0 Mask */ 1515 1516 #define PDMA_TACTSTS_TXACTF1_Pos (1) /*!< PDMA_T::TACTSTS: TXACTF1 Position */ 1517 #define PDMA_TACTSTS_TXACTF1_Msk (0x1ul << PDMA_TACTSTS_TXACTF1_Pos) /*!< PDMA_T::TACTSTS: TXACTF1 Mask */ 1518 1519 #define PDMA_TACTSTS_TXACTF2_Pos (2) /*!< PDMA_T::TACTSTS: TXACTF2 Position */ 1520 #define PDMA_TACTSTS_TXACTF2_Msk (0x1ul << PDMA_TACTSTS_TXACTF2_Pos) /*!< PDMA_T::TACTSTS: TXACTF2 Mask */ 1521 1522 #define PDMA_TACTSTS_TXACTF3_Pos (3) /*!< PDMA_T::TACTSTS: TXACTF3 Position */ 1523 #define PDMA_TACTSTS_TXACTF3_Msk (0x1ul << PDMA_TACTSTS_TXACTF3_Pos) /*!< PDMA_T::TACTSTS: TXACTF3 Mask */ 1524 1525 #define PDMA_TACTSTS_TXACTF4_Pos (4) /*!< PDMA_T::TACTSTS: TXACTF4 Position */ 1526 #define PDMA_TACTSTS_TXACTF4_Msk (0x1ul << PDMA_TACTSTS_TXACTF4_Pos) /*!< PDMA_T::TACTSTS: TXACTF4 Mask */ 1527 1528 #define PDMA_TACTSTS_TXACTF5_Pos (5) /*!< PDMA_T::TACTSTS: TXACTF5 Position */ 1529 #define PDMA_TACTSTS_TXACTF5_Msk (0x1ul << PDMA_TACTSTS_TXACTF5_Pos) /*!< PDMA_T::TACTSTS: TXACTF5 Mask */ 1530 1531 #define PDMA_TACTSTS_TXACTF6_Pos (6) /*!< PDMA_T::TACTSTS: TXACTF6 Position */ 1532 #define PDMA_TACTSTS_TXACTF6_Msk (0x1ul << PDMA_TACTSTS_TXACTF6_Pos) /*!< PDMA_T::TACTSTS: TXACTF6 Mask */ 1533 1534 #define PDMA_TACTSTS_TXACTF7_Pos (7) /*!< PDMA_T::TACTSTS: TXACTF7 Position */ 1535 #define PDMA_TACTSTS_TXACTF7_Msk (0x1ul << PDMA_TACTSTS_TXACTF7_Pos) /*!< PDMA_T::TACTSTS: TXACTF7 Mask */ 1536 1537 #define PDMA_TACTSTS_TXACTF8_Pos (8) /*!< PDMA_T::TACTSTS: TXACTF8 Position */ 1538 #define PDMA_TACTSTS_TXACTF8_Msk (0x1ul << PDMA_TACTSTS_TXACTF8_Pos) /*!< PDMA_T::TACTSTS: TXACTF8 Mask */ 1539 1540 #define PDMA_TACTSTS_TXACTF9_Pos (9) /*!< PDMA_T::TACTSTS: TXACTF9 Position */ 1541 #define PDMA_TACTSTS_TXACTF9_Msk (0x1ul << PDMA_TACTSTS_TXACTF9_Pos) /*!< PDMA_T::TACTSTS: TXACTF9 Mask */ 1542 1543 #define PDMA_TACTSTS_TXACTF10_Pos (10) /*!< PDMA_T::TACTSTS: TXACTF10 Position */ 1544 #define PDMA_TACTSTS_TXACTF10_Msk (0x1ul << PDMA_TACTSTS_TXACTF10_Pos) /*!< PDMA_T::TACTSTS: TXACTF10 Mask */ 1545 1546 #define PDMA_TACTSTS_TXACTF11_Pos (11) /*!< PDMA_T::TACTSTS: TXACTF11 Position */ 1547 #define PDMA_TACTSTS_TXACTF11_Msk (0x1ul << PDMA_TACTSTS_TXACTF11_Pos) /*!< PDMA_T::TACTSTS: TXACTF11 Mask */ 1548 1549 #define PDMA_TACTSTS_TXACTF12_Pos (12) /*!< PDMA_T::TACTSTS: TXACTF12 Position */ 1550 #define PDMA_TACTSTS_TXACTF12_Msk (0x1ul << PDMA_TACTSTS_TXACTF12_Pos) /*!< PDMA_T::TACTSTS: TXACTF12 Mask */ 1551 1552 #define PDMA_TACTSTS_TXACTF13_Pos (13) /*!< PDMA_T::TACTSTS: TXACTF13 Position */ 1553 #define PDMA_TACTSTS_TXACTF13_Msk (0x1ul << PDMA_TACTSTS_TXACTF13_Pos) /*!< PDMA_T::TACTSTS: TXACTF13 Mask */ 1554 1555 #define PDMA_TACTSTS_TXACTF14_Pos (14) /*!< PDMA_T::TACTSTS: TXACTF14 Position */ 1556 #define PDMA_TACTSTS_TXACTF14_Msk (0x1ul << PDMA_TACTSTS_TXACTF14_Pos) /*!< PDMA_T::TACTSTS: TXACTF14 Mask */ 1557 1558 #define PDMA_TACTSTS_TXACTF15_Pos (15) /*!< PDMA_T::TACTSTS: TXACTF15 Position */ 1559 #define PDMA_TACTSTS_TXACTF15_Msk (0x1ul << PDMA_TACTSTS_TXACTF15_Pos) /*!< PDMA_T::TACTSTS: TXACTF15 Mask */ 1560 1561 #define PDMA_TOUTPSC0_7_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC0 Position */ 1562 #define PDMA_TOUTPSC0_7_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC0 Mask */ 1563 1564 #define PDMA_TOUTPSC0_7_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC1 Position */ 1565 #define PDMA_TOUTPSC0_7_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC1 Mask */ 1566 1567 #define PDMA_TOUTPSC0_7_TOUTPSC2_Pos (8) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC2 Position */ 1568 #define PDMA_TOUTPSC0_7_TOUTPSC2_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC2_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC2 Mask */ 1569 1570 #define PDMA_TOUTPSC0_7_TOUTPSC3_Pos (12) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC3 Position */ 1571 #define PDMA_TOUTPSC0_7_TOUTPSC3_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC3_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC3 Mask */ 1572 1573 #define PDMA_TOUTPSC0_7_TOUTPSC4_Pos (16) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC4 Position */ 1574 #define PDMA_TOUTPSC0_7_TOUTPSC4_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC4_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC4 Mask */ 1575 1576 #define PDMA_TOUTPSC0_7_TOUTPSC5_Pos (20) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC5 Position */ 1577 #define PDMA_TOUTPSC0_7_TOUTPSC5_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC5_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC5 Mask */ 1578 1579 #define PDMA_TOUTPSC0_7_TOUTPSC6_Pos (24) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC6 Position */ 1580 #define PDMA_TOUTPSC0_7_TOUTPSC6_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC6_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC6 Mask */ 1581 1582 #define PDMA_TOUTPSC0_7_TOUTPSC7_Pos (28) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC7 Position */ 1583 #define PDMA_TOUTPSC0_7_TOUTPSC7_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC7_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC7 Mask */ 1584 1585 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ 1586 #define PDMA_TOUTEN_TOUTENn_Msk (0xfffful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ 1587 1588 #define PDMA_TOUTEN_TOUTEN0_Pos (0) /*!< PDMA_T::TOUTEN: TOUTEN0 Position */ 1589 #define PDMA_TOUTEN_TOUTEN0_Msk (0x1ul << PDMA_TOUTEN_TOUTEN0_Pos) /*!< PDMA_T::TOUTEN: TOUTEN0 Mask */ 1590 1591 #define PDMA_TOUTEN_TOUTEN1_Pos (1) /*!< PDMA_T::TOUTEN: TOUTEN1 Position */ 1592 #define PDMA_TOUTEN_TOUTEN1_Msk (0x1ul << PDMA_TOUTEN_TOUTEN1_Pos) /*!< PDMA_T::TOUTEN: TOUTEN1 Mask */ 1593 1594 #define PDMA_TOUTEN_TOUTEN2_Pos (2) /*!< PDMA_T::TOUTEN: TOUTEN2 Position */ 1595 #define PDMA_TOUTEN_TOUTEN2_Msk (0x1ul << PDMA_TOUTEN_TOUTEN2_Pos) /*!< PDMA_T::TOUTEN: TOUTEN2 Mask */ 1596 1597 #define PDMA_TOUTEN_TOUTEN3_Pos (3) /*!< PDMA_T::TOUTEN: TOUTEN3 Position */ 1598 #define PDMA_TOUTEN_TOUTEN3_Msk (0x1ul << PDMA_TOUTEN_TOUTEN3_Pos) /*!< PDMA_T::TOUTEN: TOUTEN3 Mask */ 1599 1600 #define PDMA_TOUTEN_TOUTEN4_Pos (4) /*!< PDMA_T::TOUTEN: TOUTEN4 Position */ 1601 #define PDMA_TOUTEN_TOUTEN4_Msk (0x1ul << PDMA_TOUTEN_TOUTEN4_Pos) /*!< PDMA_T::TOUTEN: TOUTEN4 Mask */ 1602 1603 #define PDMA_TOUTEN_TOUTEN5_Pos (5) /*!< PDMA_T::TOUTEN: TOUTEN5 Position */ 1604 #define PDMA_TOUTEN_TOUTEN5_Msk (0x1ul << PDMA_TOUTEN_TOUTEN5_Pos) /*!< PDMA_T::TOUTEN: TOUTEN5 Mask */ 1605 1606 #define PDMA_TOUTEN_TOUTEN6_Pos (6) /*!< PDMA_T::TOUTEN: TOUTEN6 Position */ 1607 #define PDMA_TOUTEN_TOUTEN6_Msk (0x1ul << PDMA_TOUTEN_TOUTEN6_Pos) /*!< PDMA_T::TOUTEN: TOUTEN6 Mask */ 1608 1609 #define PDMA_TOUTEN_TOUTEN7_Pos (7) /*!< PDMA_T::TOUTEN: TOUTEN7 Position */ 1610 #define PDMA_TOUTEN_TOUTEN7_Msk (0x1ul << PDMA_TOUTEN_TOUTEN7_Pos) /*!< PDMA_T::TOUTEN: TOUTEN7 Mask */ 1611 1612 #define PDMA_TOUTEN_TOUTEN8_Pos (8) /*!< PDMA_T::TOUTEN: TOUTEN8 Position */ 1613 #define PDMA_TOUTEN_TOUTEN8_Msk (0x1ul << PDMA_TOUTEN_TOUTEN8_Pos) /*!< PDMA_T::TOUTEN: TOUTEN8 Mask */ 1614 1615 #define PDMA_TOUTEN_TOUTEN9_Pos (9) /*!< PDMA_T::TOUTEN: TOUTEN9 Position */ 1616 #define PDMA_TOUTEN_TOUTEN9_Msk (0x1ul << PDMA_TOUTEN_TOUTEN9_Pos) /*!< PDMA_T::TOUTEN: TOUTEN9 Mask */ 1617 1618 #define PDMA_TOUTEN_TOUTEN10_Pos (10) /*!< PDMA_T::TOUTEN: TOUTEN10 Position */ 1619 #define PDMA_TOUTEN_TOUTEN10_Msk (0x1ul << PDMA_TOUTEN_TOUTEN10_Pos) /*!< PDMA_T::TOUTEN: TOUTEN10 Mask */ 1620 1621 #define PDMA_TOUTEN_TOUTEN11_Pos (11) /*!< PDMA_T::TOUTEN: TOUTEN11 Position */ 1622 #define PDMA_TOUTEN_TOUTEN11_Msk (0x1ul << PDMA_TOUTEN_TOUTEN11_Pos) /*!< PDMA_T::TOUTEN: TOUTEN11 Mask */ 1623 1624 #define PDMA_TOUTEN_TOUTEN12_Pos (12) /*!< PDMA_T::TOUTEN: TOUTEN12 Position */ 1625 #define PDMA_TOUTEN_TOUTEN12_Msk (0x1ul << PDMA_TOUTEN_TOUTEN12_Pos) /*!< PDMA_T::TOUTEN: TOUTEN12 Mask */ 1626 1627 #define PDMA_TOUTEN_TOUTEN13_Pos (13) /*!< PDMA_T::TOUTEN: TOUTEN13 Position */ 1628 #define PDMA_TOUTEN_TOUTEN13_Msk (0x1ul << PDMA_TOUTEN_TOUTEN13_Pos) /*!< PDMA_T::TOUTEN: TOUTEN13 Mask */ 1629 1630 #define PDMA_TOUTEN_TOUTEN14_Pos (14) /*!< PDMA_T::TOUTEN: TOUTEN14 Position */ 1631 #define PDMA_TOUTEN_TOUTEN14_Msk (0x1ul << PDMA_TOUTEN_TOUTEN14_Pos) /*!< PDMA_T::TOUTEN: TOUTEN14 Mask */ 1632 1633 #define PDMA_TOUTEN_TOUTEN15_Pos (15) /*!< PDMA_T::TOUTEN: TOUTEN15 Position */ 1634 #define PDMA_TOUTEN_TOUTEN15_Msk (0x1ul << PDMA_TOUTEN_TOUTEN15_Pos) /*!< PDMA_T::TOUTEN: TOUTEN15 Mask */ 1635 1636 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ 1637 #define PDMA_TOUTIEN_TOUTIENn_Msk (0xfffful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ 1638 1639 #define PDMA_TOUTIEN_TOUTIEN0_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIEN0 Position */ 1640 #define PDMA_TOUTIEN_TOUTIEN0_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN0_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN0 Mask */ 1641 1642 #define PDMA_TOUTIEN_TOUTIEN1_Pos (1) /*!< PDMA_T::TOUTIEN: TOUTIEN1 Position */ 1643 #define PDMA_TOUTIEN_TOUTIEN1_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN1_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN1 Mask */ 1644 1645 #define PDMA_TOUTIEN_TOUTIEN2_Pos (2) /*!< PDMA_T::TOUTIEN: TOUTIEN2 Position */ 1646 #define PDMA_TOUTIEN_TOUTIEN2_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN2_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN2 Mask */ 1647 1648 #define PDMA_TOUTIEN_TOUTIEN3_Pos (3) /*!< PDMA_T::TOUTIEN: TOUTIEN3 Position */ 1649 #define PDMA_TOUTIEN_TOUTIEN3_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN3_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN3 Mask */ 1650 1651 #define PDMA_TOUTIEN_TOUTIEN4_Pos (4) /*!< PDMA_T::TOUTIEN: TOUTIEN4 Position */ 1652 #define PDMA_TOUTIEN_TOUTIEN4_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN4_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN4 Mask */ 1653 1654 #define PDMA_TOUTIEN_TOUTIEN5_Pos (5) /*!< PDMA_T::TOUTIEN: TOUTIEN5 Position */ 1655 #define PDMA_TOUTIEN_TOUTIEN5_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN5_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN5 Mask */ 1656 1657 #define PDMA_TOUTIEN_TOUTIEN6_Pos (6) /*!< PDMA_T::TOUTIEN: TOUTIEN6 Position */ 1658 #define PDMA_TOUTIEN_TOUTIEN6_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN6_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN6 Mask */ 1659 1660 #define PDMA_TOUTIEN_TOUTIEN7_Pos (7) /*!< PDMA_T::TOUTIEN: TOUTIEN7 Position */ 1661 #define PDMA_TOUTIEN_TOUTIEN7_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN7_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN7 Mask */ 1662 1663 #define PDMA_TOUTIEN_TOUTIEN8_Pos (8) /*!< PDMA_T::TOUTIEN: TOUTIEN8 Position */ 1664 #define PDMA_TOUTIEN_TOUTIEN8_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN8_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN8 Mask */ 1665 1666 #define PDMA_TOUTIEN_TOUTIEN9_Pos (9) /*!< PDMA_T::TOUTIEN: TOUTIEN9 Position */ 1667 #define PDMA_TOUTIEN_TOUTIEN9_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN9_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN9 Mask */ 1668 1669 #define PDMA_TOUTIEN_TOUTIEN10_Pos (10) /*!< PDMA_T::TOUTIEN: TOUTIEN10 Position */ 1670 #define PDMA_TOUTIEN_TOUTIEN10_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN10_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN10 Mask */ 1671 1672 #define PDMA_TOUTIEN_TOUTIEN11_Pos (11) /*!< PDMA_T::TOUTIEN: TOUTIEN11 Position */ 1673 #define PDMA_TOUTIEN_TOUTIEN11_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN11_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN11 Mask */ 1674 1675 #define PDMA_TOUTIEN_TOUTIEN12_Pos (12) /*!< PDMA_T::TOUTIEN: TOUTIEN12 Position */ 1676 #define PDMA_TOUTIEN_TOUTIEN12_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN12_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN12 Mask */ 1677 1678 #define PDMA_TOUTIEN_TOUTIEN13_Pos (13) /*!< PDMA_T::TOUTIEN: TOUTIEN13 Position */ 1679 #define PDMA_TOUTIEN_TOUTIEN13_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN13_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN13 Mask */ 1680 1681 #define PDMA_TOUTIEN_TOUTIEN14_Pos (14) /*!< PDMA_T::TOUTIEN: TOUTIEN14 Position */ 1682 #define PDMA_TOUTIEN_TOUTIEN14_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN14_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN14 Mask */ 1683 1684 #define PDMA_TOUTIEN_TOUTIEN15_Pos (15) /*!< PDMA_T::TOUTIEN: TOUTIEN15 Position */ 1685 #define PDMA_TOUTIEN_TOUTIEN15_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN15_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN15 Mask */ 1686 1687 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ 1688 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ 1689 1690 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ 1691 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ 1692 1693 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ 1694 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ 1695 1696 #define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */ 1697 #define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */ 1698 1699 #define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */ 1700 #define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */ 1701 1702 #define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */ 1703 #define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */ 1704 1705 #define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */ 1706 #define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */ 1707 1708 #define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */ 1709 #define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */ 1710 1711 #define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */ 1712 #define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */ 1713 1714 #define PDMA_TOC8_9_TOC8_Pos (0) /*!< PDMA_T::TOC8_9: TOC8 Position */ 1715 #define PDMA_TOC8_9_TOC8_Msk (0xfffful << PDMA_TOC8_9_TOC8_Pos) /*!< PDMA_T::TOC8_9: TOC8 Mask */ 1716 1717 #define PDMA_TOC8_9_TOC9_Pos (16) /*!< PDMA_T::TOC8_9: TOC9 Position */ 1718 #define PDMA_TOC8_9_TOC9_Msk (0xfffful << PDMA_TOC8_9_TOC9_Pos) /*!< PDMA_T::TOC8_9: TOC9 Mask */ 1719 1720 #define PDMA_TOC10_11_TOC10_Pos (0) /*!< PDMA_T::TOC10_11: TOC10 Position */ 1721 #define PDMA_TOC10_11_TOC10_Msk (0xfffful << PDMA_TOC10_11_TOC10_Pos) /*!< PDMA_T::TOC10_11: TOC10 Mask */ 1722 1723 #define PDMA_TOC10_11_TOC11_Pos (16) /*!< PDMA_T::TOC10_11: TOC11 Position */ 1724 #define PDMA_TOC10_11_TOC11_Msk (0xfffful << PDMA_TOC10_11_TOC11_Pos) /*!< PDMA_T::TOC10_11: TOC11 Mask */ 1725 1726 #define PDMA_TOC12_13_TOC12_Pos (0) /*!< PDMA_T::TOC12_13: TOC12 Position */ 1727 #define PDMA_TOC12_13_TOC12_Msk (0xfffful << PDMA_TOC12_13_TOC12_Pos) /*!< PDMA_T::TOC12_13: TOC12 Mask */ 1728 1729 #define PDMA_TOC12_13_TOC13_Pos (16) /*!< PDMA_T::TOC12_13: TOC13 Position */ 1730 #define PDMA_TOC12_13_TOC13_Msk (0xfffful << PDMA_TOC12_13_TOC13_Pos) /*!< PDMA_T::TOC12_13: TOC13 Mask */ 1731 1732 #define PDMA_TOC14_15_TOC14_Pos (0) /*!< PDMA_T::TOC14_15: TOC14 Position */ 1733 #define PDMA_TOC14_15_TOC14_Msk (0xfffful << PDMA_TOC14_15_TOC14_Pos) /*!< PDMA_T::TOC14_15: TOC14 Mask */ 1734 1735 #define PDMA_TOC14_15_TOC15_Pos (16) /*!< PDMA_T::TOC14_15: TOC15 Position */ 1736 #define PDMA_TOC14_15_TOC15_Msk (0xfffful << PDMA_TOC14_15_TOC15_Pos) /*!< PDMA_T::TOC14_15: TOC15 Mask */ 1737 1738 #define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ 1739 #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ 1740 1741 #define PDMA_CHRST_CH0RST_Pos (0) /*!< PDMA_T::CHRST: CH0RST Position */ 1742 #define PDMA_CHRST_CH0RST_Msk (0x1ul << PDMA_CHRST_CH0RST_Pos) /*!< PDMA_T::CHRST: CH0RST Mask */ 1743 1744 #define PDMA_CHRST_CH1RST_Pos (1) /*!< PDMA_T::CHRST: CH1RST Position */ 1745 #define PDMA_CHRST_CH1RST_Msk (0x1ul << PDMA_CHRST_CH1RST_Pos) /*!< PDMA_T::CHRST: CH1RST Mask */ 1746 1747 #define PDMA_CHRST_CH2RST_Pos (2) /*!< PDMA_T::CHRST: CH2RST Position */ 1748 #define PDMA_CHRST_CH2RST_Msk (0x1ul << PDMA_CHRST_CH2RST_Pos) /*!< PDMA_T::CHRST: CH2RST Mask */ 1749 1750 #define PDMA_CHRST_CH3RST_Pos (3) /*!< PDMA_T::CHRST: CH3RST Position */ 1751 #define PDMA_CHRST_CH3RST_Msk (0x1ul << PDMA_CHRST_CH3RST_Pos) /*!< PDMA_T::CHRST: CH3RST Mask */ 1752 1753 #define PDMA_CHRST_CH4RST_Pos (4) /*!< PDMA_T::CHRST: CH4RST Position */ 1754 #define PDMA_CHRST_CH4RST_Msk (0x1ul << PDMA_CHRST_CH4RST_Pos) /*!< PDMA_T::CHRST: CH4RST Mask */ 1755 1756 #define PDMA_CHRST_CH5RST_Pos (5) /*!< PDMA_T::CHRST: CH5RST Position */ 1757 #define PDMA_CHRST_CH5RST_Msk (0x1ul << PDMA_CHRST_CH5RST_Pos) /*!< PDMA_T::CHRST: CH5RST Mask */ 1758 1759 #define PDMA_CHRST_CH6RST_Pos (6) /*!< PDMA_T::CHRST: CH6RST Position */ 1760 #define PDMA_CHRST_CH6RST_Msk (0x1ul << PDMA_CHRST_CH6RST_Pos) /*!< PDMA_T::CHRST: CH6RST Mask */ 1761 1762 #define PDMA_CHRST_CH7RST_Pos (7) /*!< PDMA_T::CHRST: CH7RST Position */ 1763 #define PDMA_CHRST_CH7RST_Msk (0x1ul << PDMA_CHRST_CH7RST_Pos) /*!< PDMA_T::CHRST: CH7RST Mask */ 1764 1765 #define PDMA_CHRST_CH8RST_Pos (8) /*!< PDMA_T::CHRST: CH8RST Position */ 1766 #define PDMA_CHRST_CH8RST_Msk (0x1ul << PDMA_CHRST_CH8RST_Pos) /*!< PDMA_T::CHRST: CH8RST Mask */ 1767 1768 #define PDMA_CHRST_CH9RST_Pos (9) /*!< PDMA_T::CHRST: CH9RST Position */ 1769 #define PDMA_CHRST_CH9RST_Msk (0x1ul << PDMA_CHRST_CH9RST_Pos) /*!< PDMA_T::CHRST: CH9RST Mask */ 1770 1771 #define PDMA_CHRST_CH10RST_Pos (10) /*!< PDMA_T::CHRST: CH10RST Position */ 1772 #define PDMA_CHRST_CH10RST_Msk (0x1ul << PDMA_CHRST_CH10RST_Pos) /*!< PDMA_T::CHRST: CH10RST Mask */ 1773 1774 #define PDMA_CHRST_CH11RST_Pos (11) /*!< PDMA_T::CHRST: CH11RST Position */ 1775 #define PDMA_CHRST_CH11RST_Msk (0x1ul << PDMA_CHRST_CH11RST_Pos) /*!< PDMA_T::CHRST: CH11RST Mask */ 1776 1777 #define PDMA_CHRST_CH12RST_Pos (12) /*!< PDMA_T::CHRST: CH12RST Position */ 1778 #define PDMA_CHRST_CH12RST_Msk (0x1ul << PDMA_CHRST_CH12RST_Pos) /*!< PDMA_T::CHRST: CH12RST Mask */ 1779 1780 #define PDMA_CHRST_CH13RST_Pos (13) /*!< PDMA_T::CHRST: CH13RST Position */ 1781 #define PDMA_CHRST_CH13RST_Msk (0x1ul << PDMA_CHRST_CH13RST_Pos) /*!< PDMA_T::CHRST: CH13RST Mask */ 1782 1783 #define PDMA_CHRST_CH14RST_Pos (14) /*!< PDMA_T::CHRST: CH14RST Position */ 1784 #define PDMA_CHRST_CH14RST_Msk (0x1ul << PDMA_CHRST_CH14RST_Pos) /*!< PDMA_T::CHRST: CH14RST Mask */ 1785 1786 #define PDMA_CHRST_CH15RST_Pos (15) /*!< PDMA_T::CHRST: CH15RST Position */ 1787 #define PDMA_CHRST_CH15RST_Msk (0x1ul << PDMA_CHRST_CH15RST_Pos) /*!< PDMA_T::CHRST: CH15RST Mask */ 1788 1789 #define PDMA_TOUTPSC8_15_TOUTPSC8_Pos (0) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC8 Position */ 1790 #define PDMA_TOUTPSC8_15_TOUTPSC8_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC8_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC8 Mask */ 1791 1792 #define PDMA_TOUTPSC8_15_TOUTPSC9_Pos (4) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC9 Position */ 1793 #define PDMA_TOUTPSC8_15_TOUTPSC9_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC9_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC9 Mask */ 1794 1795 #define PDMA_TOUTPSC8_15_TOUTPSC10_Pos (8) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC10 Position */ 1796 #define PDMA_TOUTPSC8_15_TOUTPSC10_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC10_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC10 Mask */ 1797 1798 #define PDMA_TOUTPSC8_15_TOUTPSC11_Pos (12) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC11 Position */ 1799 #define PDMA_TOUTPSC8_15_TOUTPSC11_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC11_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC11 Mask */ 1800 1801 #define PDMA_TOUTPSC8_15_TOUTPSC12_Pos (16) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC12 Position */ 1802 #define PDMA_TOUTPSC8_15_TOUTPSC12_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC12_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC12 Mask */ 1803 1804 #define PDMA_TOUTPSC8_15_TOUTPSC13_Pos (20) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC13 Position */ 1805 #define PDMA_TOUTPSC8_15_TOUTPSC13_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC13_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC13 Mask */ 1806 1807 #define PDMA_TOUTPSC8_15_TOUTPSC14_Pos (24) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC14 Position */ 1808 #define PDMA_TOUTPSC8_15_TOUTPSC14_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC14_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC14 Mask */ 1809 1810 #define PDMA_TOUTPSC8_15_TOUTPSC15_Pos (28) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC15 Position */ 1811 #define PDMA_TOUTPSC8_15_TOUTPSC15_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC15_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC15 Mask */ 1812 1813 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ 1814 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ 1815 1816 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ 1817 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ 1818 1819 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ 1820 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ 1821 1822 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ 1823 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ 1824 1825 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ 1826 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ 1827 1828 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ 1829 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ 1830 1831 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ 1832 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ 1833 1834 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ 1835 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ 1836 1837 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ 1838 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ 1839 1840 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ 1841 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ 1842 1843 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ 1844 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ 1845 1846 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ 1847 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ 1848 1849 #define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ 1850 #define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ 1851 1852 #define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ 1853 #define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ 1854 1855 #define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ 1856 #define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ 1857 1858 #define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ 1859 #define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ 1860 1861 #define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ 1862 #define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ 1863 1864 #define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ 1865 #define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ 1866 1867 #define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ 1868 #define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ 1869 1870 #define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ 1871 #define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ 1872 1873 #define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ 1874 #define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ 1875 1876 #define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ 1877 #define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ 1878 1879 /**@}*/ /* PDMA_CONST */ 1880 /**@}*/ /* end of PDMA register group */ 1881 /**@}*/ /* end of REGISTER group */ 1882 1883 #if defined ( __CC_ARM ) 1884 #pragma no_anon_unions 1885 #endif 1886 1887 #endif /* __PDMA_REG_H__ */ 1888
