1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** PCR_UART0_CONF_REG register 15 * UART0 configuration register 16 */ 17 #define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) 18 /** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; 19 * Set 1 to enable uart0 apb clock 20 */ 21 #define PCR_UART0_CLK_EN (BIT(0)) 22 #define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) 23 #define PCR_UART0_CLK_EN_V 0x00000001U 24 #define PCR_UART0_CLK_EN_S 0 25 /** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; 26 * Set 0 to reset uart0 module 27 */ 28 #define PCR_UART0_RST_EN (BIT(1)) 29 #define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) 30 #define PCR_UART0_RST_EN_V 0x00000001U 31 #define PCR_UART0_RST_EN_S 1 32 33 /** PCR_UART0_SCLK_CONF_REG register 34 * UART0_SCLK configuration register 35 */ 36 #define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) 37 /** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; 38 * The denominator of the frequency divider factor of the uart0 function clock. 39 */ 40 #define PCR_UART0_SCLK_DIV_A 0x0000003FU 41 #define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) 42 #define PCR_UART0_SCLK_DIV_A_V 0x0000003FU 43 #define PCR_UART0_SCLK_DIV_A_S 0 44 /** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; 45 * The numerator of the frequency divider factor of the uart0 function clock. 46 */ 47 #define PCR_UART0_SCLK_DIV_B 0x0000003FU 48 #define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) 49 #define PCR_UART0_SCLK_DIV_B_V 0x0000003FU 50 #define PCR_UART0_SCLK_DIV_B_S 6 51 /** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; 52 * The integral part of the frequency divider factor of the uart0 function clock. 53 */ 54 #define PCR_UART0_SCLK_DIV_NUM 0x000000FFU 55 #define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) 56 #define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU 57 #define PCR_UART0_SCLK_DIV_NUM_S 12 58 /** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; 59 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 60 * FOSC, 3(default): XTAL. 61 */ 62 #define PCR_UART0_SCLK_SEL 0x00000003U 63 #define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) 64 #define PCR_UART0_SCLK_SEL_V 0x00000003U 65 #define PCR_UART0_SCLK_SEL_S 20 66 /** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; 67 * Set 1 to enable uart0 function clock 68 */ 69 #define PCR_UART0_SCLK_EN (BIT(22)) 70 #define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) 71 #define PCR_UART0_SCLK_EN_V 0x00000001U 72 #define PCR_UART0_SCLK_EN_S 22 73 74 /** PCR_UART0_PD_CTRL_REG register 75 * UART0 power control register 76 */ 77 #define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) 78 /** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; 79 * Set this bit to force power down UART0 memory. 80 */ 81 #define PCR_UART0_MEM_FORCE_PU (BIT(1)) 82 #define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) 83 #define PCR_UART0_MEM_FORCE_PU_V 0x00000001U 84 #define PCR_UART0_MEM_FORCE_PU_S 1 85 /** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; 86 * Set this bit to force power up UART0 memory. 87 */ 88 #define PCR_UART0_MEM_FORCE_PD (BIT(2)) 89 #define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) 90 #define PCR_UART0_MEM_FORCE_PD_V 0x00000001U 91 #define PCR_UART0_MEM_FORCE_PD_S 2 92 93 /** PCR_UART1_CONF_REG register 94 * UART1 configuration register 95 */ 96 #define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) 97 /** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; 98 * Set 1 to enable uart1 apb clock 99 */ 100 #define PCR_UART1_CLK_EN (BIT(0)) 101 #define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) 102 #define PCR_UART1_CLK_EN_V 0x00000001U 103 #define PCR_UART1_CLK_EN_S 0 104 /** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; 105 * Set 0 to reset uart1 module 106 */ 107 #define PCR_UART1_RST_EN (BIT(1)) 108 #define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) 109 #define PCR_UART1_RST_EN_V 0x00000001U 110 #define PCR_UART1_RST_EN_S 1 111 112 /** PCR_UART1_SCLK_CONF_REG register 113 * UART1_SCLK configuration register 114 */ 115 #define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) 116 /** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; 117 * The denominator of the frequency divider factor of the uart1 function clock. 118 */ 119 #define PCR_UART1_SCLK_DIV_A 0x0000003FU 120 #define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) 121 #define PCR_UART1_SCLK_DIV_A_V 0x0000003FU 122 #define PCR_UART1_SCLK_DIV_A_S 0 123 /** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; 124 * The numerator of the frequency divider factor of the uart1 function clock. 125 */ 126 #define PCR_UART1_SCLK_DIV_B 0x0000003FU 127 #define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) 128 #define PCR_UART1_SCLK_DIV_B_V 0x0000003FU 129 #define PCR_UART1_SCLK_DIV_B_S 6 130 /** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; 131 * The integral part of the frequency divider factor of the uart1 function clock. 132 */ 133 #define PCR_UART1_SCLK_DIV_NUM 0x000000FFU 134 #define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) 135 #define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU 136 #define PCR_UART1_SCLK_DIV_NUM_S 12 137 /** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; 138 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 139 * FOSC, 3(default): XTAL. 140 */ 141 #define PCR_UART1_SCLK_SEL 0x00000003U 142 #define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) 143 #define PCR_UART1_SCLK_SEL_V 0x00000003U 144 #define PCR_UART1_SCLK_SEL_S 20 145 /** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; 146 * Set 1 to enable uart0 function clock 147 */ 148 #define PCR_UART1_SCLK_EN (BIT(22)) 149 #define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) 150 #define PCR_UART1_SCLK_EN_V 0x00000001U 151 #define PCR_UART1_SCLK_EN_S 22 152 153 /** PCR_UART1_PD_CTRL_REG register 154 * UART1 power control register 155 */ 156 #define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) 157 /** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; 158 * Set this bit to force power down UART1 memory. 159 */ 160 #define PCR_UART1_MEM_FORCE_PU (BIT(1)) 161 #define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) 162 #define PCR_UART1_MEM_FORCE_PU_V 0x00000001U 163 #define PCR_UART1_MEM_FORCE_PU_S 1 164 /** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; 165 * Set this bit to force power up UART1 memory. 166 */ 167 #define PCR_UART1_MEM_FORCE_PD (BIT(2)) 168 #define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) 169 #define PCR_UART1_MEM_FORCE_PD_V 0x00000001U 170 #define PCR_UART1_MEM_FORCE_PD_S 2 171 172 /** PCR_MSPI_CONF_REG register 173 * MSPI configuration register 174 */ 175 #define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) 176 /** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; 177 * Set 1 to enable mspi clock, include mspi pll clock 178 */ 179 #define PCR_MSPI_CLK_EN (BIT(0)) 180 #define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) 181 #define PCR_MSPI_CLK_EN_V 0x00000001U 182 #define PCR_MSPI_CLK_EN_S 0 183 /** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; 184 * Set 0 to reset mspi module 185 */ 186 #define PCR_MSPI_RST_EN (BIT(1)) 187 #define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) 188 #define PCR_MSPI_RST_EN_V 0x00000001U 189 #define PCR_MSPI_RST_EN_S 1 190 /** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; 191 * Set 1 to enable mspi pll clock 192 */ 193 #define PCR_MSPI_PLL_CLK_EN (BIT(2)) 194 #define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) 195 #define PCR_MSPI_PLL_CLK_EN_V 0x00000001U 196 #define PCR_MSPI_PLL_CLK_EN_S 2 197 198 /** PCR_MSPI_CLK_CONF_REG register 199 * MSPI_CLK configuration register 200 */ 201 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) 202 /** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; 203 * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed 204 * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a 205 * low-speed clock-source such as XTAL/FOSC. 206 */ 207 #define PCR_MSPI_FAST_LS_DIV_NUM 0x000000FFU 208 #define PCR_MSPI_FAST_LS_DIV_NUM_M (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S) 209 #define PCR_MSPI_FAST_LS_DIV_NUM_V 0x000000FFU 210 #define PCR_MSPI_FAST_LS_DIV_NUM_S 0 211 /** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; 212 * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed 213 * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a 214 * high-speed clock-source such as SPLL. 215 */ 216 #define PCR_MSPI_FAST_HS_DIV_NUM 0x000000FFU 217 #define PCR_MSPI_FAST_HS_DIV_NUM_M (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S) 218 #define PCR_MSPI_FAST_HS_DIV_NUM_V 0x000000FFU 219 #define PCR_MSPI_FAST_HS_DIV_NUM_S 8 220 221 /** PCR_I2C_CONF_REG register 222 * I2C configuration register 223 */ 224 #define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) 225 /** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; 226 * Set 1 to enable i2c apb clock 227 */ 228 #define PCR_I2C_CLK_EN (BIT(0)) 229 #define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) 230 #define PCR_I2C_CLK_EN_V 0x00000001U 231 #define PCR_I2C_CLK_EN_S 0 232 /** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; 233 * Set 0 to reset i2c module 234 */ 235 #define PCR_I2C_RST_EN (BIT(1)) 236 #define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) 237 #define PCR_I2C_RST_EN_V 0x00000001U 238 #define PCR_I2C_RST_EN_S 1 239 240 /** PCR_I2C_SCLK_CONF_REG register 241 * I2C_SCLK configuration register 242 */ 243 #define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) 244 /** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; 245 * The denominator of the frequency divider factor of the i2c function clock. 246 */ 247 #define PCR_I2C_SCLK_DIV_A 0x0000003FU 248 #define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) 249 #define PCR_I2C_SCLK_DIV_A_V 0x0000003FU 250 #define PCR_I2C_SCLK_DIV_A_S 0 251 /** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; 252 * The numerator of the frequency divider factor of the i2c function clock. 253 */ 254 #define PCR_I2C_SCLK_DIV_B 0x0000003FU 255 #define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) 256 #define PCR_I2C_SCLK_DIV_B_V 0x0000003FU 257 #define PCR_I2C_SCLK_DIV_B_S 6 258 /** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; 259 * The integral part of the frequency divider factor of the i2c function clock. 260 */ 261 #define PCR_I2C_SCLK_DIV_NUM 0x000000FFU 262 #define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) 263 #define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU 264 #define PCR_I2C_SCLK_DIV_NUM_S 12 265 /** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; 266 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 267 */ 268 #define PCR_I2C_SCLK_SEL (BIT(20)) 269 #define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) 270 #define PCR_I2C_SCLK_SEL_V 0x00000001U 271 #define PCR_I2C_SCLK_SEL_S 20 272 /** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; 273 * Set 1 to enable i2c function clock 274 */ 275 #define PCR_I2C_SCLK_EN (BIT(22)) 276 #define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) 277 #define PCR_I2C_SCLK_EN_V 0x00000001U 278 #define PCR_I2C_SCLK_EN_S 22 279 280 /** PCR_UHCI_CONF_REG register 281 * UHCI configuration register 282 */ 283 #define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28) 284 /** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; 285 * Set 1 to enable uhci clock 286 */ 287 #define PCR_UHCI_CLK_EN (BIT(0)) 288 #define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) 289 #define PCR_UHCI_CLK_EN_V 0x00000001U 290 #define PCR_UHCI_CLK_EN_S 0 291 /** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; 292 * Set 0 to reset uhci module 293 */ 294 #define PCR_UHCI_RST_EN (BIT(1)) 295 #define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) 296 #define PCR_UHCI_RST_EN_V 0x00000001U 297 #define PCR_UHCI_RST_EN_S 1 298 299 /** PCR_RMT_CONF_REG register 300 * RMT configuration register 301 */ 302 #define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c) 303 /** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; 304 * Set 1 to enable rmt apb clock 305 */ 306 #define PCR_RMT_CLK_EN (BIT(0)) 307 #define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) 308 #define PCR_RMT_CLK_EN_V 0x00000001U 309 #define PCR_RMT_CLK_EN_S 0 310 /** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; 311 * Set 0 to reset rmt module 312 */ 313 #define PCR_RMT_RST_EN (BIT(1)) 314 #define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) 315 #define PCR_RMT_RST_EN_V 0x00000001U 316 #define PCR_RMT_RST_EN_S 1 317 318 /** PCR_RMT_SCLK_CONF_REG register 319 * RMT_SCLK configuration register 320 */ 321 #define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) 322 /** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; 323 * The denominator of the frequency divider factor of the rmt function clock. 324 */ 325 #define PCR_RMT_SCLK_DIV_A 0x0000003FU 326 #define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) 327 #define PCR_RMT_SCLK_DIV_A_V 0x0000003FU 328 #define PCR_RMT_SCLK_DIV_A_S 0 329 /** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; 330 * The numerator of the frequency divider factor of the rmt function clock. 331 */ 332 #define PCR_RMT_SCLK_DIV_B 0x0000003FU 333 #define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) 334 #define PCR_RMT_SCLK_DIV_B_V 0x0000003FU 335 #define PCR_RMT_SCLK_DIV_B_S 6 336 /** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; 337 * The integral part of the frequency divider factor of the rmt function clock. 338 */ 339 #define PCR_RMT_SCLK_DIV_NUM 0x000000FFU 340 #define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) 341 #define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU 342 #define PCR_RMT_SCLK_DIV_NUM_S 12 343 /** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; 344 * set this field to select clock-source. 0: do not select anyone clock, 1(default): 345 * 80MHz, 2: FOSC, 3: XTAL. 346 */ 347 #define PCR_RMT_SCLK_SEL 0x00000003U 348 #define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) 349 #define PCR_RMT_SCLK_SEL_V 0x00000003U 350 #define PCR_RMT_SCLK_SEL_S 20 351 /** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; 352 * Set 1 to enable rmt function clock 353 */ 354 #define PCR_RMT_SCLK_EN (BIT(22)) 355 #define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) 356 #define PCR_RMT_SCLK_EN_V 0x00000001U 357 #define PCR_RMT_SCLK_EN_S 22 358 359 /** PCR_LEDC_CONF_REG register 360 * LEDC configuration register 361 */ 362 #define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) 363 /** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; 364 * Set 1 to enable ledc apb clock 365 */ 366 #define PCR_LEDC_CLK_EN (BIT(0)) 367 #define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) 368 #define PCR_LEDC_CLK_EN_V 0x00000001U 369 #define PCR_LEDC_CLK_EN_S 0 370 /** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; 371 * Set 0 to reset ledc module 372 */ 373 #define PCR_LEDC_RST_EN (BIT(1)) 374 #define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) 375 #define PCR_LEDC_RST_EN_V 0x00000001U 376 #define PCR_LEDC_RST_EN_S 1 377 378 /** PCR_LEDC_SCLK_CONF_REG register 379 * LEDC_SCLK configuration register 380 */ 381 #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) 382 /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; 383 * set this field to select clock-source. 0(default): do not select anyone clock, 1: 384 * 80MHz, 2: FOSC, 3: XTAL. 385 */ 386 #define PCR_LEDC_SCLK_SEL 0x00000003U 387 #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) 388 #define PCR_LEDC_SCLK_SEL_V 0x00000003U 389 #define PCR_LEDC_SCLK_SEL_S 20 390 /** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; 391 * Set 1 to enable ledc function clock 392 */ 393 #define PCR_LEDC_SCLK_EN (BIT(22)) 394 #define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) 395 #define PCR_LEDC_SCLK_EN_V 0x00000001U 396 #define PCR_LEDC_SCLK_EN_S 22 397 398 /** PCR_TIMERGROUP0_CONF_REG register 399 * TIMERGROUP0 configuration register 400 */ 401 #define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c) 402 /** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; 403 * Set 1 to enable timer_group0 apb clock 404 */ 405 #define PCR_TG0_CLK_EN (BIT(0)) 406 #define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) 407 #define PCR_TG0_CLK_EN_V 0x00000001U 408 #define PCR_TG0_CLK_EN_S 0 409 /** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; 410 * Set 0 to reset timer_group0 module 411 */ 412 #define PCR_TG0_RST_EN (BIT(1)) 413 #define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) 414 #define PCR_TG0_RST_EN_V 0x00000001U 415 #define PCR_TG0_RST_EN_S 1 416 417 /** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register 418 * TIMERGROUP0_TIMER_CLK configuration register 419 */ 420 #define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40) 421 /** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; 422 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 423 * reserved. 424 */ 425 #define PCR_TG0_TIMER_CLK_SEL 0x00000003U 426 #define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) 427 #define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U 428 #define PCR_TG0_TIMER_CLK_SEL_S 20 429 /** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; 430 * Set 1 to enable timer_group0 timer clock 431 */ 432 #define PCR_TG0_TIMER_CLK_EN (BIT(22)) 433 #define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) 434 #define PCR_TG0_TIMER_CLK_EN_V 0x00000001U 435 #define PCR_TG0_TIMER_CLK_EN_S 22 436 437 /** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register 438 * TIMERGROUP0_WDT_CLK configuration register 439 */ 440 #define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) 441 /** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; 442 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 443 * reserved. 444 */ 445 #define PCR_TG0_WDT_CLK_SEL 0x00000003U 446 #define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) 447 #define PCR_TG0_WDT_CLK_SEL_V 0x00000003U 448 #define PCR_TG0_WDT_CLK_SEL_S 20 449 /** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; 450 * Set 1 to enable timer_group0 wdt clock 451 */ 452 #define PCR_TG0_WDT_CLK_EN (BIT(22)) 453 #define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) 454 #define PCR_TG0_WDT_CLK_EN_V 0x00000001U 455 #define PCR_TG0_WDT_CLK_EN_S 22 456 457 /** PCR_TIMERGROUP1_CONF_REG register 458 * TIMERGROUP1 configuration register 459 */ 460 #define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48) 461 /** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; 462 * Set 1 to enable timer_group1 apb clock 463 */ 464 #define PCR_TG1_CLK_EN (BIT(0)) 465 #define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) 466 #define PCR_TG1_CLK_EN_V 0x00000001U 467 #define PCR_TG1_CLK_EN_S 0 468 /** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; 469 * Set 0 to reset timer_group1 module 470 */ 471 #define PCR_TG1_RST_EN (BIT(1)) 472 #define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) 473 #define PCR_TG1_RST_EN_V 0x00000001U 474 #define PCR_TG1_RST_EN_S 1 475 476 /** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register 477 * TIMERGROUP1_TIMER_CLK configuration register 478 */ 479 #define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) 480 /** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; 481 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 482 * reserved. 483 */ 484 #define PCR_TG1_TIMER_CLK_SEL 0x00000003U 485 #define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) 486 #define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U 487 #define PCR_TG1_TIMER_CLK_SEL_S 20 488 /** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; 489 * Set 1 to enable timer_group1 timer clock 490 */ 491 #define PCR_TG1_TIMER_CLK_EN (BIT(22)) 492 #define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) 493 #define PCR_TG1_TIMER_CLK_EN_V 0x00000001U 494 #define PCR_TG1_TIMER_CLK_EN_S 22 495 496 /** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register 497 * TIMERGROUP1_WDT_CLK configuration register 498 */ 499 #define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) 500 /** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; 501 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 502 * reserved. 503 */ 504 #define PCR_TG1_WDT_CLK_SEL 0x00000003U 505 #define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) 506 #define PCR_TG1_WDT_CLK_SEL_V 0x00000003U 507 #define PCR_TG1_WDT_CLK_SEL_S 20 508 /** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; 509 * Set 1 to enable timer_group0 wdt clock 510 */ 511 #define PCR_TG1_WDT_CLK_EN (BIT(22)) 512 #define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) 513 #define PCR_TG1_WDT_CLK_EN_V 0x00000001U 514 #define PCR_TG1_WDT_CLK_EN_S 22 515 516 /** PCR_SYSTIMER_CONF_REG register 517 * SYSTIMER configuration register 518 */ 519 #define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54) 520 /** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; 521 * Set 1 to enable systimer apb clock 522 */ 523 #define PCR_SYSTIMER_CLK_EN (BIT(0)) 524 #define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) 525 #define PCR_SYSTIMER_CLK_EN_V 0x00000001U 526 #define PCR_SYSTIMER_CLK_EN_S 0 527 /** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; 528 * Set 0 to reset systimer module 529 */ 530 #define PCR_SYSTIMER_RST_EN (BIT(1)) 531 #define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) 532 #define PCR_SYSTIMER_RST_EN_V 0x00000001U 533 #define PCR_SYSTIMER_RST_EN_S 1 534 535 /** PCR_SYSTIMER_FUNC_CLK_CONF_REG register 536 * SYSTIMER_FUNC_CLK configuration register 537 */ 538 #define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) 539 /** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; 540 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 541 */ 542 #define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) 543 #define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) 544 #define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U 545 #define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 546 /** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; 547 * Set 1 to enable systimer function clock 548 */ 549 #define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) 550 #define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) 551 #define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U 552 #define PCR_SYSTIMER_FUNC_CLK_EN_S 22 553 554 /** PCR_TWAI0_CONF_REG register 555 * TWAI0 configuration register 556 */ 557 #define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c) 558 /** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; 559 * Set 1 to enable twai0 apb clock 560 */ 561 #define PCR_TWAI0_CLK_EN (BIT(0)) 562 #define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) 563 #define PCR_TWAI0_CLK_EN_V 0x00000001U 564 #define PCR_TWAI0_CLK_EN_S 0 565 /** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; 566 * Set 0 to reset twai0 module 567 */ 568 #define PCR_TWAI0_RST_EN (BIT(1)) 569 #define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) 570 #define PCR_TWAI0_RST_EN_V 0x00000001U 571 #define PCR_TWAI0_RST_EN_S 1 572 573 /** PCR_TWAI0_FUNC_CLK_CONF_REG register 574 * TWAI0_FUNC_CLK configuration register 575 */ 576 #define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) 577 /** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; 578 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 579 */ 580 #define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) 581 #define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) 582 #define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U 583 #define PCR_TWAI0_FUNC_CLK_SEL_S 20 584 /** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; 585 * Set 1 to enable twai0 function clock 586 */ 587 #define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) 588 #define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) 589 #define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U 590 #define PCR_TWAI0_FUNC_CLK_EN_S 22 591 592 /** PCR_TWAI1_CONF_REG register 593 * TWAI1 configuration register 594 */ 595 #define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64) 596 /** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; 597 * Set 1 to enable twai1 apb clock 598 */ 599 #define PCR_TWAI1_CLK_EN (BIT(0)) 600 #define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) 601 #define PCR_TWAI1_CLK_EN_V 0x00000001U 602 #define PCR_TWAI1_CLK_EN_S 0 603 /** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; 604 * Set 0 to reset twai1 module 605 */ 606 #define PCR_TWAI1_RST_EN (BIT(1)) 607 #define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) 608 #define PCR_TWAI1_RST_EN_V 0x00000001U 609 #define PCR_TWAI1_RST_EN_S 1 610 611 /** PCR_TWAI1_FUNC_CLK_CONF_REG register 612 * TWAI1_FUNC_CLK configuration register 613 */ 614 #define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) 615 /** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; 616 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 617 */ 618 #define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) 619 #define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) 620 #define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U 621 #define PCR_TWAI1_FUNC_CLK_SEL_S 20 622 /** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; 623 * Set 1 to enable twai1 function clock 624 */ 625 #define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) 626 #define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) 627 #define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U 628 #define PCR_TWAI1_FUNC_CLK_EN_S 22 629 630 /** PCR_I2S_CONF_REG register 631 * I2S configuration register 632 */ 633 #define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) 634 /** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; 635 * Set 1 to enable i2s apb clock 636 */ 637 #define PCR_I2S_CLK_EN (BIT(0)) 638 #define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) 639 #define PCR_I2S_CLK_EN_V 0x00000001U 640 #define PCR_I2S_CLK_EN_S 0 641 /** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; 642 * Set 0 to reset i2s module 643 */ 644 #define PCR_I2S_RST_EN (BIT(1)) 645 #define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) 646 #define PCR_I2S_RST_EN_V 0x00000001U 647 #define PCR_I2S_RST_EN_S 1 648 649 /** PCR_I2S_TX_CLKM_CONF_REG register 650 * I2S_TX_CLKM configuration register 651 */ 652 #define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) 653 /** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; 654 * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be 655 * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= 656 * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * 657 * (n+1)-div] + y * (n+1)-div. 658 */ 659 #define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU 660 #define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) 661 #define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU 662 #define PCR_I2S_TX_CLKM_DIV_NUM_S 12 663 /** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; 664 * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: 665 * I2S_MCLK_in. 666 */ 667 #define PCR_I2S_TX_CLKM_SEL 0x00000003U 668 #define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) 669 #define PCR_I2S_TX_CLKM_SEL_V 0x00000003U 670 #define PCR_I2S_TX_CLKM_SEL_S 20 671 /** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; 672 * Set 1 to enable i2s_tx function clock 673 */ 674 #define PCR_I2S_TX_CLKM_EN (BIT(22)) 675 #define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) 676 #define PCR_I2S_TX_CLKM_EN_V 0x00000001U 677 #define PCR_I2S_TX_CLKM_EN_S 22 678 679 /** PCR_I2S_TX_CLKM_DIV_CONF_REG register 680 * I2S_TX_CLKM_DIV configuration register 681 */ 682 #define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) 683 /** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; 684 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of 685 * I2S_TX_CLKM_DIV_Z is (a-b). 686 */ 687 #define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU 688 #define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) 689 #define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU 690 #define PCR_I2S_TX_CLKM_DIV_Z_S 0 691 /** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; 692 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 693 * I2S_TX_CLKM_DIV_Y is (a%(a-b)). 694 */ 695 #define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU 696 #define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) 697 #define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU 698 #define PCR_I2S_TX_CLKM_DIV_Y_S 9 699 /** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; 700 * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 701 * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 702 */ 703 #define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU 704 #define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) 705 #define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU 706 #define PCR_I2S_TX_CLKM_DIV_X_S 18 707 /** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; 708 * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 709 * I2S_TX_CLKM_DIV_YN1 is 1. 710 */ 711 #define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) 712 #define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) 713 #define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U 714 #define PCR_I2S_TX_CLKM_DIV_YN1_S 27 715 716 /** PCR_I2S_RX_CLKM_CONF_REG register 717 * I2S_RX_CLKM configuration register 718 */ 719 #define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) 720 /** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; 721 * Integral I2S clock divider value 722 */ 723 #define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU 724 #define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) 725 #define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU 726 #define PCR_I2S_RX_CLKM_DIV_NUM_S 12 727 /** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; 728 * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 729 */ 730 #define PCR_I2S_RX_CLKM_SEL 0x00000003U 731 #define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) 732 #define PCR_I2S_RX_CLKM_SEL_V 0x00000003U 733 #define PCR_I2S_RX_CLKM_SEL_S 20 734 /** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; 735 * Set 1 to enable i2s_rx function clock 736 */ 737 #define PCR_I2S_RX_CLKM_EN (BIT(22)) 738 #define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) 739 #define PCR_I2S_RX_CLKM_EN_V 0x00000001U 740 #define PCR_I2S_RX_CLKM_EN_S 22 741 /** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; 742 * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx 743 */ 744 #define PCR_I2S_MCLK_SEL (BIT(23)) 745 #define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) 746 #define PCR_I2S_MCLK_SEL_V 0x00000001U 747 #define PCR_I2S_MCLK_SEL_S 23 748 749 /** PCR_I2S_RX_CLKM_DIV_CONF_REG register 750 * I2S_RX_CLKM_DIV configuration register 751 */ 752 #define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) 753 /** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; 754 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of 755 * I2S_RX_CLKM_DIV_Z is (a-b). 756 */ 757 #define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU 758 #define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) 759 #define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU 760 #define PCR_I2S_RX_CLKM_DIV_Z_S 0 761 /** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; 762 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 763 * I2S_RX_CLKM_DIV_Y is (a%(a-b)). 764 */ 765 #define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU 766 #define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) 767 #define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU 768 #define PCR_I2S_RX_CLKM_DIV_Y_S 9 769 /** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; 770 * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 771 * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 772 */ 773 #define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU 774 #define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) 775 #define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU 776 #define PCR_I2S_RX_CLKM_DIV_X_S 18 777 /** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; 778 * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 779 * I2S_RX_CLKM_DIV_YN1 is 1. 780 */ 781 #define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) 782 #define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) 783 #define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U 784 #define PCR_I2S_RX_CLKM_DIV_YN1_S 27 785 786 /** PCR_SARADC_CONF_REG register 787 * SARADC configuration register 788 */ 789 #define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) 790 /** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; 791 * no use 792 */ 793 #define PCR_SARADC_CLK_EN (BIT(0)) 794 #define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) 795 #define PCR_SARADC_CLK_EN_V 0x00000001U 796 #define PCR_SARADC_CLK_EN_S 0 797 /** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; 798 * Set 0 to reset function_register of saradc module 799 */ 800 #define PCR_SARADC_RST_EN (BIT(1)) 801 #define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) 802 #define PCR_SARADC_RST_EN_V 0x00000001U 803 #define PCR_SARADC_RST_EN_S 1 804 /** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; 805 * Set 1 to enable saradc apb clock 806 */ 807 #define PCR_SARADC_REG_CLK_EN (BIT(2)) 808 #define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) 809 #define PCR_SARADC_REG_CLK_EN_V 0x00000001U 810 #define PCR_SARADC_REG_CLK_EN_S 2 811 /** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; 812 * Set 0 to reset apb_register of saradc module 813 */ 814 #define PCR_SARADC_REG_RST_EN (BIT(3)) 815 #define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) 816 #define PCR_SARADC_REG_RST_EN_V 0x00000001U 817 #define PCR_SARADC_REG_RST_EN_S 3 818 819 /** PCR_SARADC_CLKM_CONF_REG register 820 * SARADC_CLKM configuration register 821 */ 822 #define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) 823 /** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; 824 * The denominator of the frequency divider factor of the saradc function clock. 825 */ 826 #define PCR_SARADC_CLKM_DIV_A 0x0000003FU 827 #define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) 828 #define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU 829 #define PCR_SARADC_CLKM_DIV_A_S 0 830 /** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; 831 * The numerator of the frequency divider factor of the saradc function clock. 832 */ 833 #define PCR_SARADC_CLKM_DIV_B 0x0000003FU 834 #define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) 835 #define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU 836 #define PCR_SARADC_CLKM_DIV_B_S 6 837 /** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; 838 * The integral part of the frequency divider factor of the saradc function clock. 839 */ 840 #define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU 841 #define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) 842 #define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU 843 #define PCR_SARADC_CLKM_DIV_NUM_S 12 844 /** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; 845 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 846 * reserved. 847 */ 848 #define PCR_SARADC_CLKM_SEL 0x00000003U 849 #define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) 850 #define PCR_SARADC_CLKM_SEL_V 0x00000003U 851 #define PCR_SARADC_CLKM_SEL_S 20 852 /** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; 853 * Set 1 to enable saradc function clock 854 */ 855 #define PCR_SARADC_CLKM_EN (BIT(22)) 856 #define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) 857 #define PCR_SARADC_CLKM_EN_V 0x00000001U 858 #define PCR_SARADC_CLKM_EN_S 22 859 860 /** PCR_TSENS_CLK_CONF_REG register 861 * TSENS_CLK configuration register 862 */ 863 #define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) 864 /** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; 865 * set this field to select clock-source. 0(default): FOSC, 1: XTAL. 866 */ 867 #define PCR_TSENS_CLK_SEL (BIT(20)) 868 #define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) 869 #define PCR_TSENS_CLK_SEL_V 0x00000001U 870 #define PCR_TSENS_CLK_SEL_S 20 871 /** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; 872 * Set 1 to enable tsens clock 873 */ 874 #define PCR_TSENS_CLK_EN (BIT(22)) 875 #define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) 876 #define PCR_TSENS_CLK_EN_V 0x00000001U 877 #define PCR_TSENS_CLK_EN_S 22 878 /** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; 879 * Set 0 to reset tsens module 880 */ 881 #define PCR_TSENS_RST_EN (BIT(23)) 882 #define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) 883 #define PCR_TSENS_RST_EN_V 0x00000001U 884 #define PCR_TSENS_RST_EN_S 23 885 886 /** PCR_USB_DEVICE_CONF_REG register 887 * USB_DEVICE configuration register 888 */ 889 #define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) 890 /** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; 891 * Set 1 to enable usb_device clock 892 */ 893 #define PCR_USB_DEVICE_CLK_EN (BIT(0)) 894 #define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) 895 #define PCR_USB_DEVICE_CLK_EN_V 0x00000001U 896 #define PCR_USB_DEVICE_CLK_EN_S 0 897 /** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; 898 * Set 0 to reset usb_device module 899 */ 900 #define PCR_USB_DEVICE_RST_EN (BIT(1)) 901 #define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) 902 #define PCR_USB_DEVICE_RST_EN_V 0x00000001U 903 #define PCR_USB_DEVICE_RST_EN_S 1 904 905 /** PCR_INTMTX_CONF_REG register 906 * INTMTX configuration register 907 */ 908 #define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) 909 /** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; 910 * Set 1 to enable intmtx clock 911 */ 912 #define PCR_INTMTX_CLK_EN (BIT(0)) 913 #define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) 914 #define PCR_INTMTX_CLK_EN_V 0x00000001U 915 #define PCR_INTMTX_CLK_EN_S 0 916 /** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; 917 * Set 0 to reset intmtx module 918 */ 919 #define PCR_INTMTX_RST_EN (BIT(1)) 920 #define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) 921 #define PCR_INTMTX_RST_EN_V 0x00000001U 922 #define PCR_INTMTX_RST_EN_S 1 923 924 /** PCR_PCNT_CONF_REG register 925 * PCNT configuration register 926 */ 927 #define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) 928 /** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; 929 * Set 1 to enable pcnt clock 930 */ 931 #define PCR_PCNT_CLK_EN (BIT(0)) 932 #define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) 933 #define PCR_PCNT_CLK_EN_V 0x00000001U 934 #define PCR_PCNT_CLK_EN_S 0 935 /** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; 936 * Set 0 to reset pcnt module 937 */ 938 #define PCR_PCNT_RST_EN (BIT(1)) 939 #define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) 940 #define PCR_PCNT_RST_EN_V 0x00000001U 941 #define PCR_PCNT_RST_EN_S 1 942 943 /** PCR_ETM_CONF_REG register 944 * ETM configuration register 945 */ 946 #define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) 947 /** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; 948 * Set 1 to enable etm clock 949 */ 950 #define PCR_ETM_CLK_EN (BIT(0)) 951 #define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) 952 #define PCR_ETM_CLK_EN_V 0x00000001U 953 #define PCR_ETM_CLK_EN_S 0 954 /** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; 955 * Set 0 to reset etm module 956 */ 957 #define PCR_ETM_RST_EN (BIT(1)) 958 #define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) 959 #define PCR_ETM_RST_EN_V 0x00000001U 960 #define PCR_ETM_RST_EN_S 1 961 962 /** PCR_PWM_CONF_REG register 963 * PWM configuration register 964 */ 965 #define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) 966 /** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; 967 * Set 1 to enable pwm clock 968 */ 969 #define PCR_PWM_CLK_EN (BIT(0)) 970 #define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) 971 #define PCR_PWM_CLK_EN_V 0x00000001U 972 #define PCR_PWM_CLK_EN_S 0 973 /** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; 974 * Set 0 to reset pwm module 975 */ 976 #define PCR_PWM_RST_EN (BIT(1)) 977 #define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) 978 #define PCR_PWM_RST_EN_V 0x00000001U 979 #define PCR_PWM_RST_EN_S 1 980 981 /** PCR_PWM_CLK_CONF_REG register 982 * PWM_CLK configuration register 983 */ 984 #define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) 985 /** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; 986 * The integral part of the frequency divider factor of the pwm function clock. 987 */ 988 #define PCR_PWM_DIV_NUM 0x000000FFU 989 #define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) 990 #define PCR_PWM_DIV_NUM_V 0x000000FFU 991 #define PCR_PWM_DIV_NUM_S 12 992 /** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; 993 * set this field to select clock-source. 0(default): do not select anyone clock, 1: 994 * 160MHz, 2: XTAL, 3: FOSC. 995 */ 996 #define PCR_PWM_CLKM_SEL 0x00000003U 997 #define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) 998 #define PCR_PWM_CLKM_SEL_V 0x00000003U 999 #define PCR_PWM_CLKM_SEL_S 20 1000 /** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; 1001 * set this field as 1 to activate pwm clkm. 1002 */ 1003 #define PCR_PWM_CLKM_EN (BIT(22)) 1004 #define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) 1005 #define PCR_PWM_CLKM_EN_V 0x00000001U 1006 #define PCR_PWM_CLKM_EN_S 22 1007 1008 /** PCR_PARL_IO_CONF_REG register 1009 * PARL_IO configuration register 1010 */ 1011 #define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) 1012 /** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; 1013 * Set 1 to enable parl apb clock 1014 */ 1015 #define PCR_PARL_CLK_EN (BIT(0)) 1016 #define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) 1017 #define PCR_PARL_CLK_EN_V 0x00000001U 1018 #define PCR_PARL_CLK_EN_S 0 1019 /** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; 1020 * Set 0 to reset parl apb reg 1021 */ 1022 #define PCR_PARL_RST_EN (BIT(1)) 1023 #define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) 1024 #define PCR_PARL_RST_EN_V 0x00000001U 1025 #define PCR_PARL_RST_EN_S 1 1026 1027 /** PCR_PARL_CLK_RX_CONF_REG register 1028 * PARL_CLK_RX configuration register 1029 */ 1030 #define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) 1031 /** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; 1032 * The integral part of the frequency divider factor of the parl rx clock. 1033 */ 1034 #define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU 1035 #define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) 1036 #define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU 1037 #define PCR_PARL_CLK_RX_DIV_NUM_S 0 1038 /** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; 1039 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 1040 * user clock from pad. 1041 */ 1042 #define PCR_PARL_CLK_RX_SEL 0x00000003U 1043 #define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) 1044 #define PCR_PARL_CLK_RX_SEL_V 0x00000003U 1045 #define PCR_PARL_CLK_RX_SEL_S 16 1046 /** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; 1047 * Set 1 to enable parl rx clock 1048 */ 1049 #define PCR_PARL_CLK_RX_EN (BIT(18)) 1050 #define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) 1051 #define PCR_PARL_CLK_RX_EN_V 0x00000001U 1052 #define PCR_PARL_CLK_RX_EN_S 18 1053 /** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; 1054 * Set 0 to reset parl rx module 1055 */ 1056 #define PCR_PARL_RX_RST_EN (BIT(19)) 1057 #define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) 1058 #define PCR_PARL_RX_RST_EN_V 0x00000001U 1059 #define PCR_PARL_RX_RST_EN_S 19 1060 1061 /** PCR_PARL_CLK_TX_CONF_REG register 1062 * PARL_CLK_TX configuration register 1063 */ 1064 #define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) 1065 /** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; 1066 * The integral part of the frequency divider factor of the parl tx clock. 1067 */ 1068 #define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU 1069 #define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) 1070 #define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU 1071 #define PCR_PARL_CLK_TX_DIV_NUM_S 0 1072 /** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; 1073 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 1074 * user clock from pad. 1075 */ 1076 #define PCR_PARL_CLK_TX_SEL 0x00000003U 1077 #define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) 1078 #define PCR_PARL_CLK_TX_SEL_V 0x00000003U 1079 #define PCR_PARL_CLK_TX_SEL_S 16 1080 /** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; 1081 * Set 1 to enable parl tx clock 1082 */ 1083 #define PCR_PARL_CLK_TX_EN (BIT(18)) 1084 #define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) 1085 #define PCR_PARL_CLK_TX_EN_V 0x00000001U 1086 #define PCR_PARL_CLK_TX_EN_S 18 1087 /** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; 1088 * Set 0 to reset parl tx module 1089 */ 1090 #define PCR_PARL_TX_RST_EN (BIT(19)) 1091 #define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) 1092 #define PCR_PARL_TX_RST_EN_V 0x00000001U 1093 #define PCR_PARL_TX_RST_EN_S 19 1094 1095 /** PCR_SDIO_SLAVE_CONF_REG register 1096 * SDIO_SLAVE configuration register 1097 */ 1098 #define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0) 1099 /** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; 1100 * Set 1 to enable sdio_slave clock 1101 */ 1102 #define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) 1103 #define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) 1104 #define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U 1105 #define PCR_SDIO_SLAVE_CLK_EN_S 0 1106 /** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; 1107 * Set 0 to reset sdio_slave module 1108 */ 1109 #define PCR_SDIO_SLAVE_RST_EN (BIT(1)) 1110 #define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) 1111 #define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U 1112 #define PCR_SDIO_SLAVE_RST_EN_S 1 1113 1114 /** PCR_PVT_MONITOR_CONF_REG register 1115 * PVT_MONITOR configuration register 1116 */ 1117 #define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4) 1118 /** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; 1119 * Set 1 to enable apb clock of pvt module 1120 */ 1121 #define PCR_PVT_MONITOR_CLK_EN (BIT(0)) 1122 #define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) 1123 #define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U 1124 #define PCR_PVT_MONITOR_CLK_EN_S 0 1125 /** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; 1126 * Set 0 to reset all pvt monitor module 1127 */ 1128 #define PCR_PVT_MONITOR_RST_EN (BIT(1)) 1129 #define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) 1130 #define PCR_PVT_MONITOR_RST_EN_V 0x00000001U 1131 #define PCR_PVT_MONITOR_RST_EN_S 1 1132 /** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; 1133 * Set 1 to enable function clock of modem pvt module 1134 */ 1135 #define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) 1136 #define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) 1137 #define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U 1138 #define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 1139 /** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; 1140 * Set 1 to enable function clock of cpu pvt module 1141 */ 1142 #define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) 1143 #define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) 1144 #define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U 1145 #define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 1146 /** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; 1147 * Set 1 to enable function clock of hp_peri pvt module 1148 */ 1149 #define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) 1150 #define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) 1151 #define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U 1152 #define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 1153 1154 /** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register 1155 * PVT_MONITOR function clock configuration register 1156 */ 1157 #define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8) 1158 /** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; 1159 * The integral part of the frequency divider factor of the pvt_monitor function clock. 1160 */ 1161 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU 1162 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) 1163 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU 1164 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 1165 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; 1166 * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL 1167 * divided by 3. 1168 */ 1169 #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) 1170 #define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) 1171 #define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U 1172 #define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 1173 /** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; 1174 * Set 1 to enable source clock of pvt sitex 1175 */ 1176 #define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) 1177 #define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) 1178 #define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U 1179 #define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 1180 1181 /** PCR_GDMA_CONF_REG register 1182 * GDMA configuration register 1183 */ 1184 #define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc) 1185 /** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; 1186 * Set 1 to enable gdma clock 1187 */ 1188 #define PCR_GDMA_CLK_EN (BIT(0)) 1189 #define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) 1190 #define PCR_GDMA_CLK_EN_V 0x00000001U 1191 #define PCR_GDMA_CLK_EN_S 0 1192 /** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; 1193 * Set 0 to reset gdma module 1194 */ 1195 #define PCR_GDMA_RST_EN (BIT(1)) 1196 #define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) 1197 #define PCR_GDMA_RST_EN_V 0x00000001U 1198 #define PCR_GDMA_RST_EN_S 1 1199 1200 /** PCR_SPI2_CONF_REG register 1201 * SPI2 configuration register 1202 */ 1203 #define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0) 1204 /** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; 1205 * Set 1 to enable spi2 apb clock 1206 */ 1207 #define PCR_SPI2_CLK_EN (BIT(0)) 1208 #define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) 1209 #define PCR_SPI2_CLK_EN_V 0x00000001U 1210 #define PCR_SPI2_CLK_EN_S 0 1211 /** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; 1212 * Set 0 to reset spi2 module 1213 */ 1214 #define PCR_SPI2_RST_EN (BIT(1)) 1215 #define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) 1216 #define PCR_SPI2_RST_EN_V 0x00000001U 1217 #define PCR_SPI2_RST_EN_S 1 1218 1219 /** PCR_SPI2_CLKM_CONF_REG register 1220 * SPI2_CLKM configuration register 1221 */ 1222 #define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4) 1223 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; 1224 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 1225 * reserved. 1226 */ 1227 #define PCR_SPI2_CLKM_SEL 0x00000003U 1228 #define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) 1229 #define PCR_SPI2_CLKM_SEL_V 0x00000003U 1230 #define PCR_SPI2_CLKM_SEL_S 20 1231 /** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; 1232 * Set 1 to enable spi2 function clock 1233 */ 1234 #define PCR_SPI2_CLKM_EN (BIT(22)) 1235 #define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) 1236 #define PCR_SPI2_CLKM_EN_V 0x00000001U 1237 #define PCR_SPI2_CLKM_EN_S 22 1238 1239 /** PCR_AES_CONF_REG register 1240 * AES configuration register 1241 */ 1242 #define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8) 1243 /** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; 1244 * Set 1 to enable aes clock 1245 */ 1246 #define PCR_AES_CLK_EN (BIT(0)) 1247 #define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) 1248 #define PCR_AES_CLK_EN_V 0x00000001U 1249 #define PCR_AES_CLK_EN_S 0 1250 /** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; 1251 * Set 0 to reset aes module 1252 */ 1253 #define PCR_AES_RST_EN (BIT(1)) 1254 #define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) 1255 #define PCR_AES_RST_EN_V 0x00000001U 1256 #define PCR_AES_RST_EN_S 1 1257 1258 /** PCR_SHA_CONF_REG register 1259 * SHA configuration register 1260 */ 1261 #define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc) 1262 /** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; 1263 * Set 1 to enable sha clock 1264 */ 1265 #define PCR_SHA_CLK_EN (BIT(0)) 1266 #define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) 1267 #define PCR_SHA_CLK_EN_V 0x00000001U 1268 #define PCR_SHA_CLK_EN_S 0 1269 /** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; 1270 * Set 0 to reset sha module 1271 */ 1272 #define PCR_SHA_RST_EN (BIT(1)) 1273 #define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) 1274 #define PCR_SHA_RST_EN_V 0x00000001U 1275 #define PCR_SHA_RST_EN_S 1 1276 1277 /** PCR_RSA_CONF_REG register 1278 * RSA configuration register 1279 */ 1280 #define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0) 1281 /** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; 1282 * Set 1 to enable rsa clock 1283 */ 1284 #define PCR_RSA_CLK_EN (BIT(0)) 1285 #define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) 1286 #define PCR_RSA_CLK_EN_V 0x00000001U 1287 #define PCR_RSA_CLK_EN_S 0 1288 /** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; 1289 * Set 0 to reset rsa module 1290 */ 1291 #define PCR_RSA_RST_EN (BIT(1)) 1292 #define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) 1293 #define PCR_RSA_RST_EN_V 0x00000001U 1294 #define PCR_RSA_RST_EN_S 1 1295 1296 /** PCR_RSA_PD_CTRL_REG register 1297 * RSA power control register 1298 */ 1299 #define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4) 1300 /** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; 1301 * Set this bit to power down rsa internal memory. 1302 */ 1303 #define PCR_RSA_MEM_PD (BIT(0)) 1304 #define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) 1305 #define PCR_RSA_MEM_PD_V 0x00000001U 1306 #define PCR_RSA_MEM_PD_S 0 1307 /** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; 1308 * Set this bit to force power up rsa internal memory 1309 */ 1310 #define PCR_RSA_MEM_FORCE_PU (BIT(1)) 1311 #define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) 1312 #define PCR_RSA_MEM_FORCE_PU_V 0x00000001U 1313 #define PCR_RSA_MEM_FORCE_PU_S 1 1314 /** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; 1315 * Set this bit to force power down rsa internal memory. 1316 */ 1317 #define PCR_RSA_MEM_FORCE_PD (BIT(2)) 1318 #define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) 1319 #define PCR_RSA_MEM_FORCE_PD_V 0x00000001U 1320 #define PCR_RSA_MEM_FORCE_PD_S 2 1321 1322 /** PCR_ECC_CONF_REG register 1323 * ECC configuration register 1324 */ 1325 #define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8) 1326 /** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; 1327 * Set 1 to enable ecc clock 1328 */ 1329 #define PCR_ECC_CLK_EN (BIT(0)) 1330 #define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) 1331 #define PCR_ECC_CLK_EN_V 0x00000001U 1332 #define PCR_ECC_CLK_EN_S 0 1333 /** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; 1334 * Set 0 to reset ecc module 1335 */ 1336 #define PCR_ECC_RST_EN (BIT(1)) 1337 #define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) 1338 #define PCR_ECC_RST_EN_V 0x00000001U 1339 #define PCR_ECC_RST_EN_S 1 1340 1341 /** PCR_ECC_PD_CTRL_REG register 1342 * ECC power control register 1343 */ 1344 #define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) 1345 /** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; 1346 * Set this bit to power down ecc internal memory. 1347 */ 1348 #define PCR_ECC_MEM_PD (BIT(0)) 1349 #define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) 1350 #define PCR_ECC_MEM_PD_V 0x00000001U 1351 #define PCR_ECC_MEM_PD_S 0 1352 /** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; 1353 * Set this bit to force power up ecc internal memory 1354 */ 1355 #define PCR_ECC_MEM_FORCE_PU (BIT(1)) 1356 #define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) 1357 #define PCR_ECC_MEM_FORCE_PU_V 0x00000001U 1358 #define PCR_ECC_MEM_FORCE_PU_S 1 1359 /** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; 1360 * Set this bit to force power down ecc internal memory. 1361 */ 1362 #define PCR_ECC_MEM_FORCE_PD (BIT(2)) 1363 #define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) 1364 #define PCR_ECC_MEM_FORCE_PD_V 0x00000001U 1365 #define PCR_ECC_MEM_FORCE_PD_S 2 1366 1367 /** PCR_DS_CONF_REG register 1368 * DS configuration register 1369 */ 1370 #define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0) 1371 /** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; 1372 * Set 1 to enable ds clock 1373 */ 1374 #define PCR_DS_CLK_EN (BIT(0)) 1375 #define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) 1376 #define PCR_DS_CLK_EN_V 0x00000001U 1377 #define PCR_DS_CLK_EN_S 0 1378 /** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; 1379 * Set 0 to reset ds module 1380 */ 1381 #define PCR_DS_RST_EN (BIT(1)) 1382 #define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) 1383 #define PCR_DS_RST_EN_V 0x00000001U 1384 #define PCR_DS_RST_EN_S 1 1385 1386 /** PCR_HMAC_CONF_REG register 1387 * HMAC configuration register 1388 */ 1389 #define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4) 1390 /** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; 1391 * Set 1 to enable hmac clock 1392 */ 1393 #define PCR_HMAC_CLK_EN (BIT(0)) 1394 #define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) 1395 #define PCR_HMAC_CLK_EN_V 0x00000001U 1396 #define PCR_HMAC_CLK_EN_S 0 1397 /** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; 1398 * Set 0 to reset hmac module 1399 */ 1400 #define PCR_HMAC_RST_EN (BIT(1)) 1401 #define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) 1402 #define PCR_HMAC_RST_EN_V 0x00000001U 1403 #define PCR_HMAC_RST_EN_S 1 1404 1405 /** PCR_IOMUX_CONF_REG register 1406 * IOMUX configuration register 1407 */ 1408 #define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) 1409 /** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; 1410 * Set 1 to enable iomux apb clock 1411 */ 1412 #define PCR_IOMUX_CLK_EN (BIT(0)) 1413 #define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) 1414 #define PCR_IOMUX_CLK_EN_V 0x00000001U 1415 #define PCR_IOMUX_CLK_EN_S 0 1416 /** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; 1417 * Set 0 to reset iomux module 1418 */ 1419 #define PCR_IOMUX_RST_EN (BIT(1)) 1420 #define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) 1421 #define PCR_IOMUX_RST_EN_V 0x00000001U 1422 #define PCR_IOMUX_RST_EN_S 1 1423 1424 /** PCR_IOMUX_CLK_CONF_REG register 1425 * IOMUX_CLK configuration register 1426 */ 1427 #define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) 1428 /** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3; 1429 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 1430 * FOSC, 3(default): XTAL. 1431 */ 1432 #define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U 1433 #define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) 1434 #define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U 1435 #define PCR_IOMUX_FUNC_CLK_SEL_S 20 1436 /** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; 1437 * Set 1 to enable iomux function clock 1438 */ 1439 #define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) 1440 #define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) 1441 #define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U 1442 #define PCR_IOMUX_FUNC_CLK_EN_S 22 1443 1444 /** PCR_MEM_MONITOR_CONF_REG register 1445 * MEM_MONITOR configuration register 1446 */ 1447 #define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) 1448 /** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; 1449 * Set 1 to enable mem_monitor clock 1450 */ 1451 #define PCR_MEM_MONITOR_CLK_EN (BIT(0)) 1452 #define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) 1453 #define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U 1454 #define PCR_MEM_MONITOR_CLK_EN_S 0 1455 /** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; 1456 * Set 0 to reset mem_monitor module 1457 */ 1458 #define PCR_MEM_MONITOR_RST_EN (BIT(1)) 1459 #define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) 1460 #define PCR_MEM_MONITOR_RST_EN_V 0x00000001U 1461 #define PCR_MEM_MONITOR_RST_EN_S 1 1462 1463 /** PCR_REGDMA_CONF_REG register 1464 * REGDMA configuration register 1465 */ 1466 #define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) 1467 /** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; 1468 * Set 1 to enable regdma clock 1469 */ 1470 #define PCR_REGDMA_CLK_EN (BIT(0)) 1471 #define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) 1472 #define PCR_REGDMA_CLK_EN_V 0x00000001U 1473 #define PCR_REGDMA_CLK_EN_S 0 1474 /** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; 1475 * Set 0 to reset regdma module 1476 */ 1477 #define PCR_REGDMA_RST_EN (BIT(1)) 1478 #define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) 1479 #define PCR_REGDMA_RST_EN_V 0x00000001U 1480 #define PCR_REGDMA_RST_EN_S 1 1481 1482 /** PCR_RETENTION_CONF_REG register 1483 * retention configuration register 1484 */ 1485 #define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8) 1486 /** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0; 1487 * Set 1 to enable retention clock 1488 */ 1489 #define PCR_RETENTION_CLK_EN (BIT(0)) 1490 #define PCR_RETENTION_CLK_EN_M (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S) 1491 #define PCR_RETENTION_CLK_EN_V 0x00000001U 1492 #define PCR_RETENTION_CLK_EN_S 0 1493 /** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0; 1494 * Set 0 to reset retention module 1495 */ 1496 #define PCR_RETENTION_RST_EN (BIT(1)) 1497 #define PCR_RETENTION_RST_EN_M (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S) 1498 #define PCR_RETENTION_RST_EN_V 0x00000001U 1499 #define PCR_RETENTION_RST_EN_S 1 1500 1501 /** PCR_TRACE_CONF_REG register 1502 * TRACE configuration register 1503 */ 1504 #define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) 1505 /** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; 1506 * Set 1 to enable trace clock 1507 */ 1508 #define PCR_TRACE_CLK_EN (BIT(0)) 1509 #define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) 1510 #define PCR_TRACE_CLK_EN_V 0x00000001U 1511 #define PCR_TRACE_CLK_EN_S 0 1512 /** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; 1513 * Set 0 to reset trace module 1514 */ 1515 #define PCR_TRACE_RST_EN (BIT(1)) 1516 #define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) 1517 #define PCR_TRACE_RST_EN_V 0x00000001U 1518 #define PCR_TRACE_RST_EN_S 1 1519 1520 /** PCR_ASSIST_CONF_REG register 1521 * ASSIST configuration register 1522 */ 1523 #define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) 1524 /** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; 1525 * Set 1 to enable assist clock 1526 */ 1527 #define PCR_ASSIST_CLK_EN (BIT(0)) 1528 #define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) 1529 #define PCR_ASSIST_CLK_EN_V 0x00000001U 1530 #define PCR_ASSIST_CLK_EN_S 0 1531 /** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; 1532 * Set 0 to reset assist module 1533 */ 1534 #define PCR_ASSIST_RST_EN (BIT(1)) 1535 #define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) 1536 #define PCR_ASSIST_RST_EN_V 0x00000001U 1537 #define PCR_ASSIST_RST_EN_S 1 1538 1539 /** PCR_CACHE_CONF_REG register 1540 * CACHE configuration register 1541 */ 1542 #define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) 1543 /** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; 1544 * Set 1 to enable cache clock 1545 */ 1546 #define PCR_CACHE_CLK_EN (BIT(0)) 1547 #define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) 1548 #define PCR_CACHE_CLK_EN_V 0x00000001U 1549 #define PCR_CACHE_CLK_EN_S 0 1550 /** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; 1551 * Set 0 to reset cache module 1552 */ 1553 #define PCR_CACHE_RST_EN (BIT(1)) 1554 #define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) 1555 #define PCR_CACHE_RST_EN_V 0x00000001U 1556 #define PCR_CACHE_RST_EN_S 1 1557 1558 /** PCR_MODEM_APB_CONF_REG register 1559 * MODEM_APB configuration register 1560 */ 1561 #define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108) 1562 /** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; 1563 * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). 1564 */ 1565 #define PCR_MODEM_APB_CLK_EN (BIT(0)) 1566 #define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) 1567 #define PCR_MODEM_APB_CLK_EN_V 0x00000001U 1568 #define PCR_MODEM_APB_CLK_EN_S 0 1569 /** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; 1570 * Set this file as 1 to reset modem-subsystem. 1571 */ 1572 #define PCR_MODEM_RST_EN (BIT(1)) 1573 #define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) 1574 #define PCR_MODEM_RST_EN_V 0x00000001U 1575 #define PCR_MODEM_RST_EN_S 1 1576 1577 /** PCR_TIMEOUT_CONF_REG register 1578 * TIMEOUT configuration register 1579 */ 1580 #define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) 1581 /** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; 1582 * Set 0 to reset cpu_peri timeout module 1583 */ 1584 #define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) 1585 #define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) 1586 #define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U 1587 #define PCR_CPU_TIMEOUT_RST_EN_S 1 1588 /** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; 1589 * Set 0 to reset hp_peri timeout module and hp_modem timeout module 1590 */ 1591 #define PCR_HP_TIMEOUT_RST_EN (BIT(2)) 1592 #define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) 1593 #define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U 1594 #define PCR_HP_TIMEOUT_RST_EN_S 2 1595 1596 /** PCR_SYSCLK_CONF_REG register 1597 * SYSCLK configuration register 1598 */ 1599 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) 1600 /** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; 1601 * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed 1602 * clock-source such as XTAL/FOSC. 1603 */ 1604 #define PCR_LS_DIV_NUM 0x000000FFU 1605 #define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) 1606 #define PCR_LS_DIV_NUM_V 0x000000FFU 1607 #define PCR_LS_DIV_NUM_S 0 1608 /** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; 1609 * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. 1610 */ 1611 #define PCR_HS_DIV_NUM 0x000000FFU 1612 #define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) 1613 #define PCR_HS_DIV_NUM_V 0x000000FFU 1614 #define PCR_HS_DIV_NUM_S 8 1615 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; 1616 * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. 1617 */ 1618 #define PCR_SOC_CLK_SEL 0x00000003U 1619 #define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) 1620 #define PCR_SOC_CLK_SEL_V 0x00000003U 1621 #define PCR_SOC_CLK_SEL_S 16 1622 /** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; 1623 * This field indicates the frequency(MHz) of XTAL. 1624 */ 1625 #define PCR_CLK_XTAL_FREQ 0x0000007FU 1626 #define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) 1627 #define PCR_CLK_XTAL_FREQ_V 0x0000007FU 1628 #define PCR_CLK_XTAL_FREQ_S 24 1629 1630 /** PCR_CPU_WAITI_CONF_REG register 1631 * CPU_WAITI configuration register 1632 */ 1633 #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) 1634 /** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; 1635 * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM 1636 */ 1637 #define PCR_CPUPERIOD_SEL 0x00000003U 1638 #define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) 1639 #define PCR_CPUPERIOD_SEL_V 0x00000003U 1640 #define PCR_CPUPERIOD_SEL_S 0 1641 /** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; 1642 * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM 1643 */ 1644 #define PCR_PLL_FREQ_SEL (BIT(2)) 1645 #define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) 1646 #define PCR_PLL_FREQ_SEL_V 0x00000001U 1647 #define PCR_PLL_FREQ_SEL_S 2 1648 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; 1649 * Set 1 to force cpu_waiti_clk enable. 1650 */ 1651 #define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) 1652 #define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) 1653 #define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U 1654 #define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 1655 /** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; 1656 * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk 1657 * will close 1658 */ 1659 #define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU 1660 #define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) 1661 #define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU 1662 #define PCR_CPU_WAITI_DELAY_NUM_S 4 1663 1664 /** PCR_CPU_FREQ_CONF_REG register 1665 * CPU_FREQ configuration register 1666 */ 1667 #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) 1668 /** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; 1669 * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is 1670 * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed 1671 * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. 1672 */ 1673 #define PCR_CPU_LS_DIV_NUM 0x000000FFU 1674 #define PCR_CPU_LS_DIV_NUM_M (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S) 1675 #define PCR_CPU_LS_DIV_NUM_V 0x000000FFU 1676 #define PCR_CPU_LS_DIV_NUM_S 0 1677 /** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0; 1678 * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is 1679 * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed 1680 * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. 1681 */ 1682 #define PCR_CPU_HS_DIV_NUM 0x000000FFU 1683 #define PCR_CPU_HS_DIV_NUM_M (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S) 1684 #define PCR_CPU_HS_DIV_NUM_V 0x000000FFU 1685 #define PCR_CPU_HS_DIV_NUM_S 8 1686 /** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0; 1687 * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. 1688 * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. 1689 */ 1690 #define PCR_CPU_HS_120M_FORCE (BIT(16)) 1691 #define PCR_CPU_HS_120M_FORCE_M (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S) 1692 #define PCR_CPU_HS_120M_FORCE_V 0x00000001U 1693 #define PCR_CPU_HS_120M_FORCE_S 16 1694 1695 /** PCR_AHB_FREQ_CONF_REG register 1696 * AHB_FREQ configuration register 1697 */ 1698 #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) 1699 /** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; 1700 * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb 1701 * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for 1702 * low-speed clock-source such as XTAL/FOSC, and should be used together with 1703 * PCR_CPU_LS_DIV_NUM. 1704 */ 1705 #define PCR_AHB_LS_DIV_NUM 0x000000FFU 1706 #define PCR_AHB_LS_DIV_NUM_M (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S) 1707 #define PCR_AHB_LS_DIV_NUM_V 0x000000FFU 1708 #define PCR_AHB_LS_DIV_NUM_S 0 1709 /** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; 1710 * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is 1711 * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed 1712 * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. 1713 */ 1714 #define PCR_AHB_HS_DIV_NUM 0x000000FFU 1715 #define PCR_AHB_HS_DIV_NUM_M (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S) 1716 #define PCR_AHB_HS_DIV_NUM_V 0x000000FFU 1717 #define PCR_AHB_HS_DIV_NUM_S 8 1718 1719 /** PCR_APB_FREQ_CONF_REG register 1720 * APB_FREQ configuration register 1721 */ 1722 #define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) 1723 /** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; 1724 * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be 1725 * automatically down to clk_apb_decrease only when no access is on apb-bus, and will 1726 * recover to the previous frequency when a new access appears on apb-bus. Set as one 1727 * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note 1728 * that enable this function will reduce performance. Users can set this field as zero 1729 * to disable the auto-decrease-apb-freq function. By default, this function is 1730 * disable. 1731 */ 1732 #define PCR_APB_DECREASE_DIV_NUM 0x000000FFU 1733 #define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) 1734 #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU 1735 #define PCR_APB_DECREASE_DIV_NUM_S 0 1736 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; 1737 * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is 1738 * div1(default)/div2/div4 of clk_ahb. 1739 */ 1740 #define PCR_APB_DIV_NUM 0x000000FFU 1741 #define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) 1742 #define PCR_APB_DIV_NUM_V 0x000000FFU 1743 #define PCR_APB_DIV_NUM_S 8 1744 1745 /** PCR_SYSCLK_FREQ_QUERY_0_REG register 1746 * SYSCLK frequency query 0 register 1747 */ 1748 #define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124) 1749 /** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20; 1750 * This field indicates the frequency(MHz) of FOSC. 1751 */ 1752 #define PCR_FOSC_FREQ 0x000000FFU 1753 #define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) 1754 #define PCR_FOSC_FREQ_V 0x000000FFU 1755 #define PCR_FOSC_FREQ_S 0 1756 /** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480; 1757 * This field indicates the frequency(MHz) of SPLL. 1758 */ 1759 #define PCR_PLL_FREQ 0x000003FFU 1760 #define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) 1761 #define PCR_PLL_FREQ_V 0x000003FFU 1762 #define PCR_PLL_FREQ_S 8 1763 1764 /** PCR_PLL_DIV_CLK_EN_REG register 1765 * SPLL DIV clock-gating configuration register 1766 */ 1767 #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) 1768 /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; 1769 * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1770 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1771 */ 1772 #define PCR_PLL_240M_CLK_EN (BIT(0)) 1773 #define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) 1774 #define PCR_PLL_240M_CLK_EN_V 0x00000001U 1775 #define PCR_PLL_240M_CLK_EN_S 0 1776 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; 1777 * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1778 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1779 */ 1780 #define PCR_PLL_160M_CLK_EN (BIT(1)) 1781 #define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) 1782 #define PCR_PLL_160M_CLK_EN_V 0x00000001U 1783 #define PCR_PLL_160M_CLK_EN_S 1 1784 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; 1785 * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1786 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1787 */ 1788 #define PCR_PLL_120M_CLK_EN (BIT(2)) 1789 #define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) 1790 #define PCR_PLL_120M_CLK_EN_V 0x00000001U 1791 #define PCR_PLL_120M_CLK_EN_S 2 1792 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; 1793 * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1794 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1795 */ 1796 #define PCR_PLL_80M_CLK_EN (BIT(3)) 1797 #define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) 1798 #define PCR_PLL_80M_CLK_EN_V 0x00000001U 1799 #define PCR_PLL_80M_CLK_EN_S 3 1800 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; 1801 * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1802 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1803 */ 1804 #define PCR_PLL_48M_CLK_EN (BIT(4)) 1805 #define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) 1806 #define PCR_PLL_48M_CLK_EN_V 0x00000001U 1807 #define PCR_PLL_48M_CLK_EN_S 4 1808 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; 1809 * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1810 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1811 */ 1812 #define PCR_PLL_40M_CLK_EN (BIT(5)) 1813 #define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) 1814 #define PCR_PLL_40M_CLK_EN_V 0x00000001U 1815 #define PCR_PLL_40M_CLK_EN_S 5 1816 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1; 1817 * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1818 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1819 */ 1820 #define PCR_PLL_20M_CLK_EN (BIT(6)) 1821 #define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) 1822 #define PCR_PLL_20M_CLK_EN_V 0x00000001U 1823 #define PCR_PLL_20M_CLK_EN_S 6 1824 1825 /** PCR_CTRL_CLK_OUT_EN_REG register 1826 * CLK_OUT_EN configuration register 1827 */ 1828 #define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c) 1829 /** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; 1830 * Set 1 to enable 20m clock 1831 */ 1832 #define PCR_CLK20_OEN (BIT(0)) 1833 #define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) 1834 #define PCR_CLK20_OEN_V 0x00000001U 1835 #define PCR_CLK20_OEN_S 0 1836 /** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; 1837 * Set 1 to enable 22m clock 1838 */ 1839 #define PCR_CLK22_OEN (BIT(1)) 1840 #define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) 1841 #define PCR_CLK22_OEN_V 0x00000001U 1842 #define PCR_CLK22_OEN_S 1 1843 /** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; 1844 * Set 1 to enable 44m clock 1845 */ 1846 #define PCR_CLK44_OEN (BIT(2)) 1847 #define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) 1848 #define PCR_CLK44_OEN_V 0x00000001U 1849 #define PCR_CLK44_OEN_S 2 1850 /** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; 1851 * Set 1 to enable bb clock 1852 */ 1853 #define PCR_CLK_BB_OEN (BIT(3)) 1854 #define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) 1855 #define PCR_CLK_BB_OEN_V 0x00000001U 1856 #define PCR_CLK_BB_OEN_S 3 1857 /** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; 1858 * Set 1 to enable 80m clock 1859 */ 1860 #define PCR_CLK80_OEN (BIT(4)) 1861 #define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) 1862 #define PCR_CLK80_OEN_V 0x00000001U 1863 #define PCR_CLK80_OEN_S 4 1864 /** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; 1865 * Set 1 to enable 160m clock 1866 */ 1867 #define PCR_CLK160_OEN (BIT(5)) 1868 #define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) 1869 #define PCR_CLK160_OEN_V 0x00000001U 1870 #define PCR_CLK160_OEN_S 5 1871 /** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; 1872 * Set 1 to enable 320m clock 1873 */ 1874 #define PCR_CLK_320M_OEN (BIT(6)) 1875 #define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) 1876 #define PCR_CLK_320M_OEN_V 0x00000001U 1877 #define PCR_CLK_320M_OEN_S 6 1878 /** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; 1879 * Reserved 1880 */ 1881 #define PCR_CLK_ADC_INF_OEN (BIT(7)) 1882 #define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) 1883 #define PCR_CLK_ADC_INF_OEN_V 0x00000001U 1884 #define PCR_CLK_ADC_INF_OEN_S 7 1885 /** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; 1886 * Reserved 1887 */ 1888 #define PCR_CLK_DAC_CPU_OEN (BIT(8)) 1889 #define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) 1890 #define PCR_CLK_DAC_CPU_OEN_V 0x00000001U 1891 #define PCR_CLK_DAC_CPU_OEN_S 8 1892 /** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; 1893 * Set 1 to enable 40x_bb clock 1894 */ 1895 #define PCR_CLK40X_BB_OEN (BIT(9)) 1896 #define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) 1897 #define PCR_CLK40X_BB_OEN_V 0x00000001U 1898 #define PCR_CLK40X_BB_OEN_S 9 1899 /** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; 1900 * Set 1 to enable xtal clock 1901 */ 1902 #define PCR_CLK_XTAL_OEN (BIT(10)) 1903 #define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) 1904 #define PCR_CLK_XTAL_OEN_V 0x00000001U 1905 #define PCR_CLK_XTAL_OEN_S 10 1906 1907 /** PCR_CTRL_TICK_CONF_REG register 1908 * TICK configuration register 1909 */ 1910 #define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130) 1911 /** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; 1912 * ******* Description *********** 1913 */ 1914 #define PCR_XTAL_TICK_NUM 0x000000FFU 1915 #define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) 1916 #define PCR_XTAL_TICK_NUM_V 0x000000FFU 1917 #define PCR_XTAL_TICK_NUM_S 0 1918 /** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; 1919 * ******* Description *********** 1920 */ 1921 #define PCR_FOSC_TICK_NUM 0x000000FFU 1922 #define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) 1923 #define PCR_FOSC_TICK_NUM_V 0x000000FFU 1924 #define PCR_FOSC_TICK_NUM_S 8 1925 /** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; 1926 * ******* Description *********** 1927 */ 1928 #define PCR_TICK_ENABLE (BIT(16)) 1929 #define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) 1930 #define PCR_TICK_ENABLE_V 0x00000001U 1931 #define PCR_TICK_ENABLE_S 16 1932 /** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; 1933 * ******* Description *********** 1934 */ 1935 #define PCR_RST_TICK_CNT (BIT(17)) 1936 #define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) 1937 #define PCR_RST_TICK_CNT_V 0x00000001U 1938 #define PCR_RST_TICK_CNT_S 17 1939 1940 /** PCR_CTRL_32K_CONF_REG register 1941 * 32KHz clock configuration register 1942 */ 1943 #define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134) 1944 /** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; 1945 * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and 1946 * timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. 1947 */ 1948 #define PCR_32K_SEL 0x00000003U 1949 #define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) 1950 #define PCR_32K_SEL_V 0x00000003U 1951 #define PCR_32K_SEL_S 0 1952 1953 /** PCR_SRAM_POWER_CONF_REG register 1954 * HP SRAM/ROM configuration register 1955 */ 1956 #define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138) 1957 /** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; 1958 * Set this bit to force power up SRAM 1959 */ 1960 #define PCR_SRAM_FORCE_PU 0x0000000FU 1961 #define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) 1962 #define PCR_SRAM_FORCE_PU_V 0x0000000FU 1963 #define PCR_SRAM_FORCE_PU_S 0 1964 /** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0; 1965 * Set this bit to force power down SRAM. 1966 */ 1967 #define PCR_SRAM_FORCE_PD 0x0000000FU 1968 #define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) 1969 #define PCR_SRAM_FORCE_PD_V 0x0000000FU 1970 #define PCR_SRAM_FORCE_PD_S 4 1971 /** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0; 1972 * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A 1973 * gate-clock will be used when accessing the SRAM. 1974 */ 1975 #define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU 1976 #define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) 1977 #define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU 1978 #define PCR_SRAM_CLKGATE_FORCE_ON_S 8 1979 /** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7; 1980 * Set this bit to force power up ROM 1981 */ 1982 #define PCR_ROM_FORCE_PU 0x00000007U 1983 #define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) 1984 #define PCR_ROM_FORCE_PU_V 0x00000007U 1985 #define PCR_ROM_FORCE_PU_S 12 1986 /** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0; 1987 * Set this bit to force power down ROM. 1988 */ 1989 #define PCR_ROM_FORCE_PD 0x00000007U 1990 #define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) 1991 #define PCR_ROM_FORCE_PD_V 0x00000007U 1992 #define PCR_ROM_FORCE_PD_S 15 1993 /** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0; 1994 * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A 1995 * gate-clock will be used when accessing the ROM. 1996 */ 1997 #define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U 1998 #define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) 1999 #define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U 2000 #define PCR_ROM_CLKGATE_FORCE_ON_S 18 2001 2002 /** PCR_RESET_EVENT_BYPASS_REG register 2003 * reset event bypass backdoor configuration register 2004 */ 2005 #define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) 2006 /** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; 2007 * This field is used to control reset event relationship for 2008 * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset 2009 * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg 2010 * will not only be reset by power-reset, but also some reset event. 2011 */ 2012 #define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) 2013 #define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) 2014 #define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U 2015 #define PCR_RESET_EVENT_BYPASS_APM_S 0 2016 /** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; 2017 * This field is used to control reset event relationship for system-bus. 1: system 2018 * bus (including arbiter/router) will only be reset by power-reset. some reset event 2019 * will be bypass. 0: system bus (including arbiter/router) will not only be reset by 2020 * power-reset, but also some reset event. 2021 */ 2022 #define PCR_RESET_EVENT_BYPASS (BIT(1)) 2023 #define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) 2024 #define PCR_RESET_EVENT_BYPASS_V 0x00000001U 2025 #define PCR_RESET_EVENT_BYPASS_S 1 2026 2027 /** PCR_FPGA_DEBUG_REG register 2028 * fpga debug register 2029 */ 2030 #define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) 2031 /** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; 2032 * Only used in fpga debug. 2033 */ 2034 #define PCR_FPGA_DEBUG 0xFFFFFFFFU 2035 #define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) 2036 #define PCR_FPGA_DEBUG_V 0xFFFFFFFFU 2037 #define PCR_FPGA_DEBUG_S 0 2038 2039 /** PCR_CLOCK_GATE_REG register 2040 * PCR clock gating configure register 2041 */ 2042 #define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) 2043 /** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; 2044 * Set this bit as 1 to force on clock gating. 2045 */ 2046 #define PCR_CLK_EN (BIT(0)) 2047 #define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) 2048 #define PCR_CLK_EN_V 0x00000001U 2049 #define PCR_CLK_EN_S 0 2050 2051 /** PCR_DATE_REG register 2052 * Date register. 2053 */ 2054 #define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) 2055 /** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496; 2056 * PCR version information. 2057 */ 2058 #define PCR_DATE 0x0FFFFFFFU 2059 #define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) 2060 #define PCR_DATE_V 0x0FFFFFFFU 2061 #define PCR_DATE_S 0 2062 2063 #ifdef __cplusplus 2064 } 2065 #endif 2066
