1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_NET_DEF_H 10 #define VERSAL_NET_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2 16 /* This part is taken from U-Boot project under GPL that's why dual license above */ 17 #define __bf_shf(x) (__builtin_ffsll(x) - 1U) 18 #define FIELD_GET(_mask, _reg) \ 19 ({ \ 20 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ 21 }) 22 23 /* List all consoles */ 24 #define VERSAL_NET_CONSOLE_ID_pl011 U(1) 25 #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) 26 #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) 27 #define VERSAL_NET_CONSOLE_ID_dcc U(3) 28 29 #define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) 30 31 /* List all platforms */ 32 #define VERSAL_NET_SILICON U(0) 33 #define VERSAL_NET_SPP U(1) 34 #define VERSAL_NET_EMU U(2) 35 #define VERSAL_NET_QEMU U(3) 36 #define VERSAL_NET_QEMU_COSIM U(7) 37 38 /* For platform detection */ 39 #define PMC_TAP U(0xF11A0000) 40 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 41 # define PLATFORM_MASK GENMASK(27U, 24U) 42 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 43 44 /* Global timer reset */ 45 #define PSX_CRF U(0xEC200000) 46 #define ACPU0_CLK_CTRL U(0x10C) 47 #define ACPU_CLK_CTRL_CLKACT BIT(25) 48 49 #define RST_APU0_OFFSET U(0x300) 50 #define RST_APU_COLD_RESET BIT(0) 51 #define RST_APU_WARN_RESET BIT(4) 52 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 53 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 54 55 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 56 57 #define APU_PCLI (0xECB10000ULL) 58 #define APU_PCLI_CPU_STEP (0x30ULL) 59 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 60 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 61 #define APU_PCLI_CLUSTER_STEP U(0x1000) 62 #define PCLI_PREQ_OFFSET U(0x4) 63 #define PREQ_CHANGE_REQUEST BIT(0) 64 #define PCLI_PSTATE_OFFSET U(0x8) 65 #define PCLI_PSTATE_VAL_SET U(0x48) 66 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 67 68 /* Firmware Image Package */ 69 #define VERSAL_NET_PRIMARY_CPU U(0) 70 71 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 72 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 73 (APU_PCLI_CPU_STEP * (cpu_id)))) 74 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 75 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 76 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 77 (APU_PCLI_CPU_STEP * (cpu_id)))) 78 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 79 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 80 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 81 (APU_PCLI_CPU_STEP * (cpu_id)))) 82 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 83 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 84 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 85 (APU_PCLI_CPU_STEP * (cpu_id)))) 86 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 87 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 88 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 89 (APU_PCLI_CPU_STEP * (cpu_id)))) 90 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 91 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 92 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 93 (APU_PCLI_CPU_STEP * (cpu_id)))) 94 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 95 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 96 97 /******************************************************************************* 98 * memory map related constants 99 ******************************************************************************/ 100 /* IPP 1.2/SPP 0.9 mapping */ 101 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 102 #define DEVICE0_SIZE U(0x08000000) 103 #define DEVICE1_BASE U(0xE2000000) /* gic */ 104 #define DEVICE1_SIZE U(0x00800000) 105 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 106 #define DEVICE2_SIZE U(0x01000000) 107 #define CRF_BASE U(0xFD1A0000) 108 #define CRF_SIZE U(0x00600000) 109 #define IPI_BASE U(0xEB300000) 110 #define IPI_SIZE U(0x00100000) 111 112 /* CRL */ 113 #define VERSAL_NET_CRL U(0xEB5E0000) 114 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 115 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) 116 117 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 118 119 /* IOU SCNTRS */ 120 #define VERSAL_NET_IOU_SCNTRS U(0xEC920000) 121 #define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 122 #define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 123 124 #define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1) 125 126 #define APU_CLUSTER0 U(0xECC00000) 127 #define APU_RVBAR_L_0 U(0x40) 128 #define APU_RVBAR_H_0 U(0x44) 129 #define APU_CLUSTER_STEP U(0x100000) 130 131 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 132 133 /******************************************************************************* 134 * IRQ constants 135 ******************************************************************************/ 136 #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) 137 138 /******************************************************************************* 139 * UART related constants 140 ******************************************************************************/ 141 #define VERSAL_NET_UART0_BASE U(0xF1920000) 142 #define VERSAL_NET_UART1_BASE U(0xF1930000) 143 144 #define VERSAL_NET_UART_BAUDRATE 115200 145 146 #if VERSAL_NET_CONSOLE_IS(pl011_1) 147 #define VERSAL_NET_UART_BASE VERSAL_NET_UART1_BASE 148 #else 149 /* Default console is UART0 */ 150 #define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE 151 #endif 152 153 #define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE 154 #define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK 155 #define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE 156 157 /******************************************************************************* 158 * IPI registers and bitfields 159 ******************************************************************************/ 160 #define IPI0_REG_BASE (0xEB330000U) 161 #define IPI0_TRIG_BIT (1 << 2) 162 #define PMC_IPI_TRIG_BIT (1 << 1) 163 #define IPI1_REG_BASE (0xEB340000U) 164 #define IPI1_TRIG_BIT (1 << 3) 165 #define IPI2_REG_BASE (0xEB350000U) 166 #define IPI2_TRIG_BIT (1 << 4) 167 #define IPI3_REG_BASE (0xEB360000U) 168 #define IPI3_TRIG_BIT (1 << 5) 169 #define IPI4_REG_BASE (0xEB370000U) 170 #define IPI4_TRIG_BIT (1 << 6) 171 #define IPI5_REG_BASE (0xEB380000U) 172 #define IPI5_TRIG_BIT (1 << 7) 173 174 /* Processor core device IDs */ 175 #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) 176 #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) 177 #define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) 178 #define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) 179 180 #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) 181 #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) 182 #define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) 183 #define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) 184 185 #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) 186 #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) 187 #define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) 188 #define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) 189 190 #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) 191 #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) 192 #define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) 193 #define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) 194 195 #endif /* VERSAL_NET_DEF_H */ 196
