1 /***************************************************************************//** 2 * \file cyip_ms_ctl_1_2.h 3 * 4 * \brief 5 * MS_CTL_1_2 IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_MS_CTL_1_2_H_ 28 #define _CYIP_MS_CTL_1_2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * MS_CTL_1_2 34 *******************************************************************************/ 35 36 #define MS_SECTION_SIZE 0x00000010UL 37 #define MS_PC_SECTION_SIZE 0x00000010UL 38 #define MS_CTL_1_2_SECTION_SIZE 0x00004000UL 39 40 /** 41 * \brief Master protection context control (MS) 42 */ 43 typedef struct { 44 __IOM uint32_t CTL; /*!< 0x00000000 Master 'x' protection context control */ 45 __IM uint32_t RESERVED[3]; 46 } MS_Type; /*!< Size = 16 (0x10) */ 47 48 /** 49 * \brief Master protection context value (MS_PC) 50 */ 51 typedef struct { 52 __IOM uint32_t PC; /*!< 0x00000000 Master 'x' protection context value */ 53 __IM uint32_t PC_READ_MIR; /*!< 0x00000004 Master 'x' protection context value read mirror register */ 54 __IM uint32_t RESERVED[2]; 55 } MS_PC_Type; /*!< Size = 16 (0x10) */ 56 57 /** 58 * \brief Master control registers (MS_CTL_1_2) 59 */ 60 typedef struct { 61 MS_Type MS[32]; /*!< 0x00000000 Master protection context control */ 62 __IM uint32_t RESERVED[896]; 63 MS_PC_Type MS_PC[32]; /*!< 0x00001000 Master protection context value */ 64 __IM uint32_t RESERVED1[896]; 65 __IOM uint32_t CODE_MS0_MSC_ACG_CTL; /*!< 0x00002000 CODE_MS0 master security Controller & ACG configuration */ 66 __IM uint32_t RESERVED2[3]; 67 __IOM uint32_t SYS_MS0_MSC_ACG_CTL; /*!< 0x00002010 SYS_MS0 master security Controller & ACG configuration */ 68 __IOM uint32_t SYS_MS1_MSC_ACG_CTL; /*!< 0x00002014 SYS_MS1 master security Controller & ACG configuration */ 69 __IM uint32_t RESERVED3[2]; 70 __IOM uint32_t EXP_MS_MSC_ACG_CTL; /*!< 0x00002020 EXP_MS master security Controller & ACG configuration */ 71 __IM uint32_t RESERVED4[3]; 72 __IOM uint32_t DMAC0_MSC_ACG_CTL; /*!< 0x00002030 DMAC-0 master security Controller & ACG configuration */ 73 __IM uint32_t RESERVED5[3]; 74 __IOM uint32_t DMAC1_MSC_ACG_CTL; /*!< 0x00002040 DMAC-1 master security Controller & ACG configuration */ 75 } MS_CTL_1_2_Type; /*!< Size = 8260 (0x2044) */ 76 77 78 /* MS.CTL */ 79 #define MS_CTL_P_Pos 0UL 80 #define MS_CTL_P_Msk 0x1UL 81 #define MS_CTL_NS_Pos 1UL 82 #define MS_CTL_NS_Msk 0x2UL 83 #define MS_CTL_PC_MASK_Pos 16UL 84 #define MS_CTL_PC_MASK_Msk 0xFFFF0000UL 85 86 87 /* MS_PC.PC */ 88 #define MS_PC_PC_PC_Pos 0UL 89 #define MS_PC_PC_PC_Msk 0xFUL 90 #define MS_PC_PC_PC_SAVED_Pos 16UL 91 #define MS_PC_PC_PC_SAVED_Msk 0xF0000UL 92 /* MS_PC.PC_READ_MIR */ 93 #define MS_PC_PC_READ_MIR_PC_Pos 0UL 94 #define MS_PC_PC_READ_MIR_PC_Msk 0xFUL 95 #define MS_PC_PC_READ_MIR_PC_SAVED_Pos 16UL 96 #define MS_PC_PC_READ_MIR_PC_SAVED_Msk 0xF0000UL 97 98 99 /* MS_CTL_1_2.CODE_MS0_MSC_ACG_CTL */ 100 #define MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos 0UL 101 #define MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk 0x1UL 102 #define MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Pos 1UL 103 #define MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Msk 0x2UL 104 /* MS_CTL_1_2.SYS_MS0_MSC_ACG_CTL */ 105 #define MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos 0UL 106 #define MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk 0x1UL 107 #define MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Pos 1UL 108 #define MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Msk 0x2UL 109 /* MS_CTL_1_2.SYS_MS1_MSC_ACG_CTL */ 110 #define MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Pos 0UL 111 #define MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Msk 0x1UL 112 #define MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Pos 1UL 113 #define MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Msk 0x2UL 114 /* MS_CTL_1_2.EXP_MS_MSC_ACG_CTL */ 115 #define MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Pos 0UL 116 #define MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Msk 0x1UL 117 #define MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_SEC_RESP_Pos 1UL 118 #define MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_SEC_RESP_Msk 0x2UL 119 /* MS_CTL_1_2.DMAC0_MSC_ACG_CTL */ 120 #define MS_CTL_1_2_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Pos 0UL 121 #define MS_CTL_1_2_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Msk 0x1UL 122 #define MS_CTL_1_2_DMAC0_MSC_ACG_CTL_SEC_RESP_Pos 1UL 123 #define MS_CTL_1_2_DMAC0_MSC_ACG_CTL_SEC_RESP_Msk 0x2UL 124 /* MS_CTL_1_2.DMAC1_MSC_ACG_CTL */ 125 #define MS_CTL_1_2_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Pos 0UL 126 #define MS_CTL_1_2_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Msk 0x1UL 127 #define MS_CTL_1_2_DMAC1_MSC_ACG_CTL_SEC_RESP_Pos 1UL 128 #define MS_CTL_1_2_DMAC1_MSC_ACG_CTL_SEC_RESP_Msk 0x2UL 129 130 131 #endif /* _CYIP_MS_CTL_1_2_H_ */ 132 133 134 /* [] END OF FILE */ 135
