1 // =========================================================================== 2 // This file is autogenerated, please DO NOT modify! 3 // 4 // Generated on 2024-05-23 12:09:01 5 // by user: developer 6 // on machine: swtools 7 // CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic 8 // Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt 9 // C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt 10 // 11 // Relevant file version(s): 12 // 13 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl 14 // rcs-info: (file not managed or unknown revision control system) 15 // git-hash: 68a752a8737845355f7bdb320d25a59eac685840 16 // 17 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt 18 // rcs-info: (file not managed or unknown revision control system) 19 // git-hash: e341d2d047097f8c7281906c9724785f4a71526a 20 // 21 // =========================================================================== 22 23 24 #ifndef __PBE_GENERIC_RAM_REGS_H 25 #define __PBE_GENERIC_RAM_REGS_H 26 27 //****************************************************************************** 28 // REGISTER OFFSETS 29 //****************************************************************************** 30 // 31 #define PBE_GENERIC_RAM_O_PHY 0x00000020U 32 33 // 34 #define PBE_GENERIC_RAM_O_SYNTHCALTIMEOUT 0x00000022U 35 36 // Packet configuration (common between TX and RX) 37 #define PBE_GENERIC_RAM_O_PKTCFG 0x00000024U 38 39 // 40 #define PBE_GENERIC_RAM_O_NUMCRCBITS 0x00000026U 41 42 // Configure FIFO usage 43 #define PBE_GENERIC_RAM_O_FIFOCFG 0x00000028U 44 45 // 46 #define PBE_GENERIC_RAM_O_EXTRABYTES 0x0000002AU 47 48 // Initialization for the whitener, if 0 the whitener is not used 49 #define PBE_GENERIC_RAM_O_WHITEINIT 0x0000002CU 50 51 // CRC initialization value 52 #define PBE_GENERIC_RAM_O_CRCINITL 0x00000030U 53 54 // CRC initialization value 55 #define PBE_GENERIC_RAM_O_CRCINITH 0x00000032U 56 57 // Length field configuration 58 #define PBE_GENERIC_RAM_O_LENCFG 0x00000034U 59 60 // 61 #define PBE_GENERIC_RAM_O_LENOFFSET 0x00000036U 62 63 // 64 #define PBE_GENERIC_RAM_O_FIRSTRXTIMEOUT 0x00000038U 65 66 // How long to search for sync before giving up 67 #define PBE_GENERIC_RAM_O_RXTIMEOUT 0x0000003AU 68 69 // 70 #define PBE_GENERIC_RAM_O_RFINTERVAL 0x0000003CU 71 72 // 73 #define PBE_GENERIC_RAM_O_PRETXIFS 0x0000003EU 74 75 // 76 #define PBE_GENERIC_RAM_O_PRERXIFS 0x00000040U 77 78 // combined tx/rx/fs configuration 79 #define PBE_GENERIC_RAM_O_OPCFG 0x00000042U 80 81 // Maximum allowed packet length in RX 82 #define PBE_GENERIC_RAM_O_MAXLEN 0x00000044U 83 84 // 85 #define PBE_GENERIC_RAM_O_PATTERN 0x00000046U 86 87 // Address filtering config 88 #define PBE_GENERIC_RAM_O_ADDRCFG 0x00000048U 89 90 // Address filtering config 91 #define PBE_GENERIC_RAM_O_ADDRSW 0x0000004AU 92 93 // 94 #define PBE_GENERIC_RAM_O_TESTCFG 0x0000004CU 95 96 // 97 #define PBE_GENERIC_RAM_O_TESTAPI 0x0000004EU 98 99 // 100 #define PBE_GENERIC_RAM_O_TESTTIMEOUT 0x00000050U 101 102 // 103 #define PBE_GENERIC_RAM_O_ADD0 0x00000054U 104 105 // 106 #define PBE_GENERIC_RAM_O_ADD1 0x00000056U 107 108 // 109 #define PBE_GENERIC_RAM_O_ADD2 0x00000058U 110 111 // 112 #define PBE_GENERIC_RAM_O_ADD3 0x0000005AU 113 114 // 115 #define PBE_GENERIC_RAM_O_ADD4 0x0000005CU 116 117 // 118 #define PBE_GENERIC_RAM_O_ADD5 0x0000005EU 119 120 // 121 #define PBE_GENERIC_RAM_O_ADD6 0x00000060U 122 123 // 124 #define PBE_GENERIC_RAM_O_ADD7 0x00000062U 125 126 // 127 #define PBE_GENERIC_RAM_O_ADD8 0x00000064U 128 129 // 130 #define PBE_GENERIC_RAM_O_ADD9 0x00000066U 131 132 // 133 #define PBE_GENERIC_RAM_O_ADD10 0x00000068U 134 135 // 136 #define PBE_GENERIC_RAM_O_ADD11 0x0000006AU 137 138 // 139 #define PBE_GENERIC_RAM_O_ADD12 0x0000006CU 140 141 // 142 #define PBE_GENERIC_RAM_O_ADD13 0x0000006EU 143 144 // 145 #define PBE_GENERIC_RAM_O_ADD15 0x00000070U 146 147 // 148 #define PBE_GENERIC_RAM_O_NRXNOK 0x00000072U 149 150 // 151 #define PBE_GENERIC_RAM_O_NRXIGNORED 0x00000074U 152 153 // 154 #define PBE_GENERIC_RAM_O_NRXEMPTY 0x00000076U 155 156 // 157 #define PBE_GENERIC_RAM_O_NRXFIFOFULL 0x00000078U 158 159 // 160 #define PBE_GENERIC_RAM_O_NRXOK 0x0000007AU 161 162 // 163 #define PBE_GENERIC_RAM_O_NTX 0x0000007CU 164 165 // 166 #define PBE_GENERIC_RAM_O_NRXTIMEOUT 0x0000007EU 167 168 // 169 #define PBE_GENERIC_RAM_O_LASTRSSI 0x00000080U 170 171 // 172 #define PBE_GENERIC_RAM_O_LASTFREQOFF 0x00000082U 173 174 // 175 #define PBE_GENERIC_RAM_O_LASTLQI 0x00000084U 176 177 // 178 #define PBE_GENERIC_RAM_O_LASTTIMESTAMPL 0x00000088U 179 180 // 181 #define PBE_GENERIC_RAM_O_LASTTIMESTAMPH 0x0000008AU 182 183 // 184 #define PBE_GENERIC_RAM_O_PEERADRINFO 0x0000008CU 185 186 // Peer address list for syncwordA (MDMSYNCA*) 187 #define PBE_GENERIC_RAM_O_PEERADR1AL 0x0000008EU 188 189 // Peer address list for syncwordA (MDMSYNCA*) 190 #define PBE_GENERIC_RAM_O_PEERADR1AH 0x00000090U 191 192 // Peer address list for syncwordA (MDMSYNCA*) 193 #define PBE_GENERIC_RAM_O_PEERADR0AL 0x00000092U 194 195 // Peer address list for syncwordA (MDMSYNCA*) 196 #define PBE_GENERIC_RAM_O_PEERADR0AH 0x00000094U 197 198 // Peer address list for syncwordB (MDMSYNCB*) 199 #define PBE_GENERIC_RAM_O_PEERADR1BL 0x00000096U 200 201 // Peer address list for syncwordB (MDMSYNCB*) 202 #define PBE_GENERIC_RAM_O_PEERADR1BH 0x00000098U 203 204 // Peer address list for syncwordB (MDMSYNCB*) 205 #define PBE_GENERIC_RAM_O_PEERADR0BL 0x0000009AU 206 207 // Peer address list for syncwordB (MDMSYNCB*) 208 #define PBE_GENERIC_RAM_O_PEERADR0BH 0x0000009CU 209 210 // Nordic Enhanced Shock Burst configuration shared for both PTX and PRX devices. 211 #define PBE_GENERIC_RAM_O_NESB 0x0000009EU 212 213 // NESB feature. CRC value (last two bytes if more than 2 CRC bytes) of last successfully received packet with syncWord0. 214 #define PBE_GENERIC_RAM_O_CRCVAL0 0x000000A0U 215 216 // Sequencing or Pkt ID status 217 #define PBE_GENERIC_RAM_O_SEQSTAT0 0x000000A2U 218 219 // NESB feature. CRC value (first two bytes if more than 2 CRC bytes) of first successfully received packet with syncWord1. 220 #define PBE_GENERIC_RAM_O_CRCVAL1 0x000000A4U 221 222 // Sequencing or Pkt ID status 223 #define PBE_GENERIC_RAM_O_SEQSTAT1 0x000000A6U 224 225 // Status for the received packet, appended in the RX FIFO depending on FIFOCFG. 226 #define PBE_GENERIC_RAM_O_STATUSBYTE 0x000000A8U 227 228 // Temporary register for storing header byte 229 #define PBE_GENERIC_RAM_O_TMPBYTE1 0x000000AAU 230 231 // Temporary register for storing header byte 232 #define PBE_GENERIC_RAM_O_TMPBYTE2 0x000000ACU 233 234 // Temporary register for storing header byte 235 #define PBE_GENERIC_RAM_O_TMPBYTE3 0x000000AEU 236 237 // Temporary register for storing header byte 238 #define PBE_GENERIC_RAM_O_TMPBYTE4 0x000000B0U 239 240 // Temporary register for storing RSSI 241 #define PBE_GENERIC_RAM_O_TMPRSSI 0x000000B2U 242 243 // Temporary address register 244 #define PBE_GENERIC_RAM_O_TMPADR1 0x000000B4U 245 246 // Temporary address register 247 #define PBE_GENERIC_RAM_O_TMPADR2 0x000000B6U 248 249 // Temporary address register 250 #define PBE_GENERIC_RAM_O_TMPADR3 0x000000B8U 251 252 // Temporary address register 253 #define PBE_GENERIC_RAM_O_TMPADR4 0x000000BAU 254 255 //****************************************************************************** 256 // Register: PHY 257 //****************************************************************************** 258 // Field: [5:3] rfesel 259 // 260 // Used to pass on the value of the Coding Indicator to the RFE. 261 #define PBE_GENERIC_RAM_PHY_RFESEL_W 3U 262 #define PBE_GENERIC_RAM_PHY_RFESEL_M 0x0038U 263 #define PBE_GENERIC_RAM_PHY_RFESEL_S 3U 264 #define PBE_GENERIC_RAM_PHY_RFESEL_1M 0x0000U 265 #define PBE_GENERIC_RAM_PHY_RFESEL_2M 0x0008U 266 #define PBE_GENERIC_RAM_PHY_RFESEL_CODED_125K 0x0010U 267 #define PBE_GENERIC_RAM_PHY_RFESEL_CODED_500K 0x0018U 268 269 // Field: [2:0] mcesel 270 // 271 // Used to pass on the value of the Coding Indicator to the MCE. 272 #define PBE_GENERIC_RAM_PHY_MCESEL_W 3U 273 #define PBE_GENERIC_RAM_PHY_MCESEL_M 0x0007U 274 #define PBE_GENERIC_RAM_PHY_MCESEL_S 0U 275 #define PBE_GENERIC_RAM_PHY_MCESEL_1M 0x0000U 276 #define PBE_GENERIC_RAM_PHY_MCESEL_2M 0x0001U 277 #define PBE_GENERIC_RAM_PHY_MCESEL_CODED_125K 0x0002U 278 #define PBE_GENERIC_RAM_PHY_MCESEL_CODED_500K 0x0003U 279 280 //****************************************************************************** 281 // Register: SYNTHCALTIMEOUT 282 //****************************************************************************** 283 // Field: [15:0] val 284 // 285 // SynthCal timeout in 0.25 us unit. 0 means infinite (no timeout) 286 #define PBE_GENERIC_RAM_SYNTHCALTIMEOUT_VAL_W 16U 287 #define PBE_GENERIC_RAM_SYNTHCALTIMEOUT_VAL_M 0xFFFFU 288 #define PBE_GENERIC_RAM_SYNTHCALTIMEOUT_VAL_S 0U 289 290 //****************************************************************************** 291 // Register: PKTCFG 292 //****************************************************************************** 293 // Field: [11:11] whiteorder 294 // 295 // For NextGen CC2500 compatibility 296 #define PBE_GENERIC_RAM_PKTCFG_WHITEORDER 0x0800U 297 #define PBE_GENERIC_RAM_PKTCFG_WHITEORDER_M 0x0800U 298 #define PBE_GENERIC_RAM_PKTCFG_WHITEORDER_S 11U 299 300 // Field: [10:10] crcorder 301 // 302 // Bit ordering of the CRC 303 #define PBE_GENERIC_RAM_PKTCFG_CRCORDER 0x0400U 304 #define PBE_GENERIC_RAM_PKTCFG_CRCORDER_M 0x0400U 305 #define PBE_GENERIC_RAM_PKTCFG_CRCORDER_S 10U 306 307 // Field: [9:9] bitorder 308 // 309 // Bit ordering of the payload 310 #define PBE_GENERIC_RAM_PKTCFG_BITORDER 0x0200U 311 #define PBE_GENERIC_RAM_PKTCFG_BITORDER_M 0x0200U 312 #define PBE_GENERIC_RAM_PKTCFG_BITORDER_S 9U 313 314 // Field: [8:8] hdrorder 315 // 316 // Bit ordering of the header 317 #define PBE_GENERIC_RAM_PKTCFG_HDRORDER 0x0100U 318 #define PBE_GENERIC_RAM_PKTCFG_HDRORDER_M 0x0100U 319 #define PBE_GENERIC_RAM_PKTCFG_HDRORDER_S 8U 320 321 // Field: [7:7] crcinchdr 322 // 323 // CRC HDR rule 324 #define PBE_GENERIC_RAM_PKTCFG_CRCINCHDR 0x0080U 325 #define PBE_GENERIC_RAM_PKTCFG_CRCINCHDR_M 0x0080U 326 #define PBE_GENERIC_RAM_PKTCFG_CRCINCHDR_S 7U 327 328 // Field: [6:6] crcincsw 329 // 330 // CRC SW rule 331 #define PBE_GENERIC_RAM_PKTCFG_CRCINCSW 0x0040U 332 #define PBE_GENERIC_RAM_PKTCFG_CRCINCSW_M 0x0040U 333 #define PBE_GENERIC_RAM_PKTCFG_CRCINCSW_S 6U 334 335 // Field: [5:0] numhdrbits 336 // 337 // Number of bits in the header 0-32 338 #define PBE_GENERIC_RAM_PKTCFG_NUMHDRBITS_W 6U 339 #define PBE_GENERIC_RAM_PKTCFG_NUMHDRBITS_M 0x003FU 340 #define PBE_GENERIC_RAM_PKTCFG_NUMHDRBITS_S 0U 341 342 //****************************************************************************** 343 // Register: NUMCRCBITS 344 //****************************************************************************** 345 // Field: [5:0] val 346 // 347 // Length of CRC checksum in bits 348 #define PBE_GENERIC_RAM_NUMCRCBITS_VAL_W 6U 349 #define PBE_GENERIC_RAM_NUMCRCBITS_VAL_M 0x003FU 350 #define PBE_GENERIC_RAM_NUMCRCBITS_VAL_S 0U 351 352 //****************************************************************************** 353 // Register: FIFOCFG 354 //****************************************************************************** 355 // Field: [15:15] appendtimestamp 356 // 357 // 358 #define PBE_GENERIC_RAM_FIFOCFG_APPENDTIMESTAMP 0x8000U 359 #define PBE_GENERIC_RAM_FIFOCFG_APPENDTIMESTAMP_M 0x8000U 360 #define PBE_GENERIC_RAM_FIFOCFG_APPENDTIMESTAMP_S 15U 361 362 // Field: [14:14] appendrssi 363 // 364 // 365 #define PBE_GENERIC_RAM_FIFOCFG_APPENDRSSI 0x4000U 366 #define PBE_GENERIC_RAM_FIFOCFG_APPENDRSSI_M 0x4000U 367 #define PBE_GENERIC_RAM_FIFOCFG_APPENDRSSI_S 14U 368 369 // Field: [13:13] appendfreqest 370 // 371 // 372 #define PBE_GENERIC_RAM_FIFOCFG_APPENDFREQEST 0x2000U 373 #define PBE_GENERIC_RAM_FIFOCFG_APPENDFREQEST_M 0x2000U 374 #define PBE_GENERIC_RAM_FIFOCFG_APPENDFREQEST_S 13U 375 376 // Field: [12:12] appendlqi 377 // 378 // 379 #define PBE_GENERIC_RAM_FIFOCFG_APPENDLQI 0x1000U 380 #define PBE_GENERIC_RAM_FIFOCFG_APPENDLQI_M 0x1000U 381 #define PBE_GENERIC_RAM_FIFOCFG_APPENDLQI_S 12U 382 383 // Field: [11:11] appendstatus 384 // 385 // CRCOK, Ignore, Code rate 386 #define PBE_GENERIC_RAM_FIFOCFG_APPENDSTATUS 0x0800U 387 #define PBE_GENERIC_RAM_FIFOCFG_APPENDSTATUS_M 0x0800U 388 #define PBE_GENERIC_RAM_FIFOCFG_APPENDSTATUS_S 11U 389 390 // Field: [10:10] appendcrc 391 // 392 // Append all received crc bits 393 #define PBE_GENERIC_RAM_FIFOCFG_APPENDCRC 0x0400U 394 #define PBE_GENERIC_RAM_FIFOCFG_APPENDCRC_M 0x0400U 395 #define PBE_GENERIC_RAM_FIFOCFG_APPENDCRC_S 10U 396 397 // Field: [9:9] autoflushempty 398 // 399 // 400 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY 0x0200U 401 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_M 0x0200U 402 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_S 9U 403 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_KEEP 0x0000U 404 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_FLUSH 0x0200U 405 406 // Field: [8:8] autoflushign 407 // 408 // 409 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN 0x0100U 410 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_M 0x0100U 411 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_S 8U 412 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_KEEP 0x0000U 413 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_FLUSH 0x0100U 414 415 // Field: [7:7] autoflushcrc 416 // 417 // 418 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC 0x0080U 419 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_M 0x0080U 420 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_S 7U 421 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_KEEP 0x0000U 422 #define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_FLUSH 0x0080U 423 424 // Field: [6:4] lenoptpad 425 // 426 // Length of optional padding, required by the PBE during RX operations 427 #define PBE_GENERIC_RAM_FIFOCFG_LENOPTPAD_W 3U 428 #define PBE_GENERIC_RAM_FIFOCFG_LENOPTPAD_M 0x0070U 429 #define PBE_GENERIC_RAM_FIFOCFG_LENOPTPAD_S 4U 430 431 //****************************************************************************** 432 // Register: EXTRABYTES 433 //****************************************************************************** 434 // Field: [15:0] val 435 // 436 // Indicates how many bytes that are required after the PDU to hold the statuses configured in FIFOCFG. It has to be equal or greater. If FIFOCFG_APPENDRSSI is high, EXTRABYTES shall increment by 2 etc. 437 #define PBE_GENERIC_RAM_EXTRABYTES_VAL_W 16U 438 #define PBE_GENERIC_RAM_EXTRABYTES_VAL_M 0xFFFFU 439 #define PBE_GENERIC_RAM_EXTRABYTES_VAL_S 0U 440 441 //****************************************************************************** 442 // Register: WHITEINIT 443 //****************************************************************************** 444 // Field: [15:0] val 445 // 446 // Whitener initialization value 447 #define PBE_GENERIC_RAM_WHITEINIT_VAL_W 16U 448 #define PBE_GENERIC_RAM_WHITEINIT_VAL_M 0xFFFFU 449 #define PBE_GENERIC_RAM_WHITEINIT_VAL_S 0U 450 451 //****************************************************************************** 452 // Register: CRCINITL 453 //****************************************************************************** 454 // Field: [15:0] vallsb 455 // 456 // 457 #define PBE_GENERIC_RAM_CRCINITL_VALLSB_W 16U 458 #define PBE_GENERIC_RAM_CRCINITL_VALLSB_M 0xFFFFU 459 #define PBE_GENERIC_RAM_CRCINITL_VALLSB_S 0U 460 461 //****************************************************************************** 462 // Register: CRCINITH 463 //****************************************************************************** 464 // Field: [15:0] valmsb 465 // 466 // 467 #define PBE_GENERIC_RAM_CRCINITH_VALMSB_W 16U 468 #define PBE_GENERIC_RAM_CRCINITH_VALMSB_M 0xFFFFU 469 #define PBE_GENERIC_RAM_CRCINITH_VALMSB_S 0U 470 471 //****************************************************************************** 472 // Register: LENCFG 473 //****************************************************************************** 474 // Field: [15:10] reserved 475 // 476 // Reserved values 477 #define PBE_GENERIC_RAM_LENCFG_RESERVED_W 6U 478 #define PBE_GENERIC_RAM_LENCFG_RESERVED_M 0xFC00U 479 #define PBE_GENERIC_RAM_LENCFG_RESERVED_S 10U 480 481 // Field: [9:5] numlenbits 482 // 483 // Number of bits in length field 0-16. 484 #define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_W 5U 485 #define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_M 0x03E0U 486 #define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_S 5U 487 #define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_FIXED 0x0000U 488 489 // Field: [4:0] lenpos 490 // 491 // Position of length field in header 0-31 492 #define PBE_GENERIC_RAM_LENCFG_LENPOS_W 5U 493 #define PBE_GENERIC_RAM_LENCFG_LENPOS_M 0x001FU 494 #define PBE_GENERIC_RAM_LENCFG_LENPOS_S 0U 495 496 //****************************************************************************** 497 // Register: LENOFFSET 498 //****************************************************************************** 499 // Field: [15:0] val 500 // 501 // Signed value to add to length field 502 #define PBE_GENERIC_RAM_LENOFFSET_VAL_W 16U 503 #define PBE_GENERIC_RAM_LENOFFSET_VAL_M 0xFFFFU 504 #define PBE_GENERIC_RAM_LENOFFSET_VAL_S 0U 505 506 //****************************************************************************** 507 // Register: FIRSTRXTIMEOUT 508 //****************************************************************************** 509 // Field: [15:0] val 510 // 511 // For NESB tasks, the timeout in µs from SYSTCMP0 event to giving up listening for the first packet. Must be at least 128 µs if non-zero, may be up to 32000 µs. 512 #define PBE_GENERIC_RAM_FIRSTRXTIMEOUT_VAL_W 16U 513 #define PBE_GENERIC_RAM_FIRSTRXTIMEOUT_VAL_M 0xFFFFU 514 #define PBE_GENERIC_RAM_FIRSTRXTIMEOUT_VAL_S 0U 515 516 //****************************************************************************** 517 // Register: RXTIMEOUT 518 //****************************************************************************** 519 // Field: [15:0] val 520 // 521 // RX timeout in 0.25 us unit. 0 means infinite (no timeout) 522 #define PBE_GENERIC_RAM_RXTIMEOUT_VAL_W 16U 523 #define PBE_GENERIC_RAM_RXTIMEOUT_VAL_M 0xFFFFU 524 #define PBE_GENERIC_RAM_RXTIMEOUT_VAL_S 0U 525 526 //****************************************************************************** 527 // Register: RFINTERVAL 528 //****************************************************************************** 529 // Field: [15:0] val 530 // 531 // RF interval in units of 1 µs 532 #define PBE_GENERIC_RAM_RFINTERVAL_VAL_W 16U 533 #define PBE_GENERIC_RAM_RFINTERVAL_VAL_M 0xFFFFU 534 #define PBE_GENERIC_RAM_RFINTERVAL_VAL_S 0U 535 536 //****************************************************************************** 537 // Register: PRETXIFS 538 //****************************************************************************** 539 // Field: [15:0] val 540 // 541 // Base value used to set timer0 for when to start Transmission. 542 #define PBE_GENERIC_RAM_PRETXIFS_VAL_W 16U 543 #define PBE_GENERIC_RAM_PRETXIFS_VAL_M 0xFFFFU 544 #define PBE_GENERIC_RAM_PRETXIFS_VAL_S 0U 545 546 //****************************************************************************** 547 // Register: PRERXIFS 548 //****************************************************************************** 549 // Field: [15:0] val 550 // 551 // Base value used to set timer0 for when to start Reception. 552 #define PBE_GENERIC_RAM_PRERXIFS_VAL_W 16U 553 #define PBE_GENERIC_RAM_PRERXIFS_VAL_M 0xFFFFU 554 #define PBE_GENERIC_RAM_PRERXIFS_VAL_S 0U 555 556 //****************************************************************************** 557 // Register: OPCFG 558 //****************************************************************************** 559 // Field: [14:14] rxfilterop 560 // 561 // Address filtering option 562 #define PBE_GENERIC_RAM_OPCFG_RXFILTEROP 0x4000U 563 #define PBE_GENERIC_RAM_OPCFG_RXFILTEROP_M 0x4000U 564 #define PBE_GENERIC_RAM_OPCFG_RXFILTEROP_S 14U 565 566 // Field: [13:13] rxincludehdr 567 // 568 // Rule for HDR inclusion in FIFO 569 #define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR 0x2000U 570 #define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_M 0x2000U 571 #define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_S 13U 572 #define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_NO 0x0000U 573 #define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_YES 0x2000U 574 575 // Field: [12:12] rxrepeatok 576 // 577 // Rule for what to do after packets with correct CRC 578 #define PBE_GENERIC_RAM_OPCFG_RXREPEATOK 0x1000U 579 #define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_M 0x1000U 580 #define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_S 12U 581 #define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_YES 0x0000U 582 #define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_NO 0x1000U 583 584 // Field: [11:11] rxrepeatnok 585 // 586 // Rule for what to do after packets with CRC error or address mismatch. 587 #define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK 0x0800U 588 #define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_M 0x0800U 589 #define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_S 11U 590 #define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_NO 0x0000U 591 #define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_YES 0x0800U 592 593 // Field: [10:10] txinfinite 594 // 595 // Infinite TX control 596 #define PBE_GENERIC_RAM_OPCFG_TXINFINITE 0x0400U 597 #define PBE_GENERIC_RAM_OPCFG_TXINFINITE_M 0x0400U 598 #define PBE_GENERIC_RAM_OPCFG_TXINFINITE_S 10U 599 #define PBE_GENERIC_RAM_OPCFG_TXINFINITE_NO 0x0000U 600 #define PBE_GENERIC_RAM_OPCFG_TXINFINITE_YES 0x0400U 601 602 // Field: [9:9] txpattern 603 // 604 // Send fixed pattern 605 #define PBE_GENERIC_RAM_OPCFG_TXPATTERN 0x0200U 606 #define PBE_GENERIC_RAM_OPCFG_TXPATTERN_M 0x0200U 607 #define PBE_GENERIC_RAM_OPCFG_TXPATTERN_S 9U 608 #define PBE_GENERIC_RAM_OPCFG_TXPATTERN_NO 0x0000U 609 #define PBE_GENERIC_RAM_OPCFG_TXPATTERN_YES 0x0200U 610 611 // Field: [8:7] txfcmd 612 // 613 // Rule for FCMD after TX_DONE 614 #define PBE_GENERIC_RAM_OPCFG_TXFCMD_W 2U 615 #define PBE_GENERIC_RAM_OPCFG_TXFCMD_M 0x0180U 616 #define PBE_GENERIC_RAM_OPCFG_TXFCMD_S 7U 617 #define PBE_GENERIC_RAM_OPCFG_TXFCMD_NONE 0x0000U 618 #define PBE_GENERIC_RAM_OPCFG_TXFCMD_RETRY 0x0080U 619 #define PBE_GENERIC_RAM_OPCFG_TXFCMD_DEALLOC 0x0100U 620 621 // Field: [6:6] start 622 // 623 // Rule for start of operation. 624 #define PBE_GENERIC_RAM_OPCFG_START 0x0040U 625 #define PBE_GENERIC_RAM_OPCFG_START_M 0x0040U 626 #define PBE_GENERIC_RAM_OPCFG_START_S 6U 627 628 // Field: [5:5] fs_nocal 629 // 630 // Rule for frequency synthesizer(FS) calibration 631 #define PBE_GENERIC_RAM_OPCFG_FS_NOCAL 0x0020U 632 #define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M 0x0020U 633 #define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_S 5U 634 #define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_CAL 0x0000U 635 #define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_NOCAL 0x0020U 636 637 // Field: [4:4] fs_keepon 638 // 639 // Rule for frequency synthesizer(FS) power down 640 #define PBE_GENERIC_RAM_OPCFG_FS_KEEPON 0x0010U 641 #define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M 0x0010U 642 #define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_S 4U 643 #define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_NO 0x0000U 644 #define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_YES 0x0010U 645 646 // Field: [3:3] nextop 647 // 648 // Enable automatic RX/TX switching, does nothing if OPCFG_SINGLE is selected. 649 #define PBE_GENERIC_RAM_OPCFG_NEXTOP 0x0008U 650 #define PBE_GENERIC_RAM_OPCFG_NEXTOP_M 0x0008U 651 #define PBE_GENERIC_RAM_OPCFG_NEXTOP_S 3U 652 #define PBE_GENERIC_RAM_OPCFG_NEXTOP_SWITCH 0x0000U 653 #define PBE_GENERIC_RAM_OPCFG_NEXTOP_SAME 0x0008U 654 655 // Field: [2:2] single 656 // 657 // Only one shall be high of SINGLE, IFSPERIOD or RFINTERVAL. 658 #define PBE_GENERIC_RAM_OPCFG_SINGLE 0x0004U 659 #define PBE_GENERIC_RAM_OPCFG_SINGLE_M 0x0004U 660 #define PBE_GENERIC_RAM_OPCFG_SINGLE_S 2U 661 #define PBE_GENERIC_RAM_OPCFG_SINGLE_DIS 0x0000U 662 #define PBE_GENERIC_RAM_OPCFG_SINGLE_EN 0x0004U 663 664 // Field: [1:1] ifsperiod 665 // 666 // Only one shall be high of SINGLE, IFSPERIOD or RFINTERVAL. 667 #define PBE_GENERIC_RAM_OPCFG_IFSPERIOD 0x0002U 668 #define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_M 0x0002U 669 #define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_S 1U 670 #define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_DIS 0x0000U 671 #define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_EN 0x0002U 672 673 // Field: [0:0] rfinterval 674 // 675 // Only one shall be high of SINGLE, IFSPERIOD or RFINTERVAL. 676 #define PBE_GENERIC_RAM_OPCFG_RFINTERVAL 0x0001U 677 #define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_M 0x0001U 678 #define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_S 0U 679 #define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_DIS 0x0000U 680 #define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_EN 0x0001U 681 682 //****************************************************************************** 683 // Register: MAXLEN 684 //****************************************************************************** 685 // Field: [15:0] val 686 // 687 // Indicates maximum expected packet length during RX. If NUMLENBITS is 0 then MAXLEN indicates the length of the payload. The length is fixed. If it's 0, RX restarts sync search. 688 #define PBE_GENERIC_RAM_MAXLEN_VAL_W 16U 689 #define PBE_GENERIC_RAM_MAXLEN_VAL_M 0xFFFFU 690 #define PBE_GENERIC_RAM_MAXLEN_VAL_S 0U 691 692 //****************************************************************************** 693 // Register: PATTERN 694 //****************************************************************************** 695 // Field: [15:0] val 696 // 697 // Data to send if OPCFG.TXPATTERN is 1 698 #define PBE_GENERIC_RAM_PATTERN_VAL_W 16U 699 #define PBE_GENERIC_RAM_PATTERN_VAL_M 0xFFFFU 700 #define PBE_GENERIC_RAM_PATTERN_VAL_S 0U 701 702 //****************************************************************************** 703 // Register: ADDRCFG 704 //****************************************************************************** 705 // Field: [15:11] numaddr 706 // 707 // Number of addresses in use in the address table 708 #define PBE_GENERIC_RAM_ADDRCFG_NUMADDR_W 5U 709 #define PBE_GENERIC_RAM_ADDRCFG_NUMADDR_M 0xF800U 710 #define PBE_GENERIC_RAM_ADDRCFG_NUMADDR_S 11U 711 712 // Field: [10:6] addrpos 713 // 714 // If ADDRTYPE=1, bit position of address in header. If ADDRTYPE=1, set to non-zero to extend address with sync word identifier. 715 #define PBE_GENERIC_RAM_ADDRCFG_ADDRPOS_W 5U 716 #define PBE_GENERIC_RAM_ADDRCFG_ADDRPOS_M 0x07C0U 717 #define PBE_GENERIC_RAM_ADDRCFG_ADDRPOS_S 6U 718 719 // Field: [5:1] addrsz 720 // 721 // Address size. If ADDRTYPE=0 it is in bytes, if ADDRTYPE=1 it is in bits 722 #define PBE_GENERIC_RAM_ADDRCFG_ADDRSZ_W 5U 723 #define PBE_GENERIC_RAM_ADDRCFG_ADDRSZ_M 0x003EU 724 #define PBE_GENERIC_RAM_ADDRCFG_ADDRSZ_S 1U 725 726 // Field: [0:0] addrtype 727 // 728 // Address type 729 #define PBE_GENERIC_RAM_ADDRCFG_ADDRTYPE 0x0001U 730 #define PBE_GENERIC_RAM_ADDRCFG_ADDRTYPE_M 0x0001U 731 #define PBE_GENERIC_RAM_ADDRCFG_ADDRTYPE_S 0U 732 733 //****************************************************************************** 734 // Register: ADDRSW 735 //****************************************************************************** 736 // Field: [15:15] add15sw 737 // 738 // Control what SW add15 is expected to belong to 739 #define PBE_GENERIC_RAM_ADDRSW_ADD15SW 0x8000U 740 #define PBE_GENERIC_RAM_ADDRSW_ADD15SW_M 0x8000U 741 #define PBE_GENERIC_RAM_ADDRSW_ADD15SW_S 15U 742 #define PBE_GENERIC_RAM_ADDRSW_ADD15SW_A 0x0000U 743 #define PBE_GENERIC_RAM_ADDRSW_ADD15SW_B 0x8000U 744 745 // Field: [14:14] add14sw 746 // 747 // Control what SW add14 is expected to belong to 748 #define PBE_GENERIC_RAM_ADDRSW_ADD14SW 0x4000U 749 #define PBE_GENERIC_RAM_ADDRSW_ADD14SW_M 0x4000U 750 #define PBE_GENERIC_RAM_ADDRSW_ADD14SW_S 14U 751 #define PBE_GENERIC_RAM_ADDRSW_ADD14SW_A 0x0000U 752 #define PBE_GENERIC_RAM_ADDRSW_ADD14SW_B 0x4000U 753 754 // Field: [13:13] add13sw 755 // 756 // Control what SW add13 is expected to belong to 757 #define PBE_GENERIC_RAM_ADDRSW_ADD13SW 0x2000U 758 #define PBE_GENERIC_RAM_ADDRSW_ADD13SW_M 0x2000U 759 #define PBE_GENERIC_RAM_ADDRSW_ADD13SW_S 13U 760 #define PBE_GENERIC_RAM_ADDRSW_ADD13SW_A 0x0000U 761 #define PBE_GENERIC_RAM_ADDRSW_ADD13SW_B 0x2000U 762 763 // Field: [12:12] add12sw 764 // 765 // Control what SW add12 is expected to belong to 766 #define PBE_GENERIC_RAM_ADDRSW_ADD12SW 0x1000U 767 #define PBE_GENERIC_RAM_ADDRSW_ADD12SW_M 0x1000U 768 #define PBE_GENERIC_RAM_ADDRSW_ADD12SW_S 12U 769 #define PBE_GENERIC_RAM_ADDRSW_ADD12SW_A 0x0000U 770 #define PBE_GENERIC_RAM_ADDRSW_ADD12SW_B 0x1000U 771 772 // Field: [11:11] add11sw 773 // 774 // Control what SW add11 is expected to belong to 775 #define PBE_GENERIC_RAM_ADDRSW_ADD11SW 0x0800U 776 #define PBE_GENERIC_RAM_ADDRSW_ADD11SW_M 0x0800U 777 #define PBE_GENERIC_RAM_ADDRSW_ADD11SW_S 11U 778 #define PBE_GENERIC_RAM_ADDRSW_ADD11SW_A 0x0000U 779 #define PBE_GENERIC_RAM_ADDRSW_ADD11SW_B 0x0800U 780 781 // Field: [10:10] add10sw 782 // 783 // Control what SW add10 is expected to belong to 784 #define PBE_GENERIC_RAM_ADDRSW_ADD10SW 0x0400U 785 #define PBE_GENERIC_RAM_ADDRSW_ADD10SW_M 0x0400U 786 #define PBE_GENERIC_RAM_ADDRSW_ADD10SW_S 10U 787 #define PBE_GENERIC_RAM_ADDRSW_ADD10SW_A 0x0000U 788 #define PBE_GENERIC_RAM_ADDRSW_ADD10SW_B 0x0400U 789 790 // Field: [9:9] add9sw 791 // 792 // Control what SW add9 is expected to belong to 793 #define PBE_GENERIC_RAM_ADDRSW_ADD9SW 0x0200U 794 #define PBE_GENERIC_RAM_ADDRSW_ADD9SW_M 0x0200U 795 #define PBE_GENERIC_RAM_ADDRSW_ADD9SW_S 9U 796 #define PBE_GENERIC_RAM_ADDRSW_ADD9SW_A 0x0000U 797 #define PBE_GENERIC_RAM_ADDRSW_ADD9SW_B 0x0200U 798 799 // Field: [8:8] add8sw 800 // 801 // Control what SW add8 is expected to belong to 802 #define PBE_GENERIC_RAM_ADDRSW_ADD8SW 0x0100U 803 #define PBE_GENERIC_RAM_ADDRSW_ADD8SW_M 0x0100U 804 #define PBE_GENERIC_RAM_ADDRSW_ADD8SW_S 8U 805 #define PBE_GENERIC_RAM_ADDRSW_ADD8SW_A 0x0000U 806 #define PBE_GENERIC_RAM_ADDRSW_ADD8SW_B 0x0100U 807 808 // Field: [7:7] add7sw 809 // 810 // Control what SW add7 is expected to belong to 811 #define PBE_GENERIC_RAM_ADDRSW_ADD7SW 0x0080U 812 #define PBE_GENERIC_RAM_ADDRSW_ADD7SW_M 0x0080U 813 #define PBE_GENERIC_RAM_ADDRSW_ADD7SW_S 7U 814 #define PBE_GENERIC_RAM_ADDRSW_ADD7SW_A 0x0000U 815 #define PBE_GENERIC_RAM_ADDRSW_ADD7SW_B 0x0080U 816 817 // Field: [6:6] add6sw 818 // 819 // Control what SW add6 is expected to belong to 820 #define PBE_GENERIC_RAM_ADDRSW_ADD6SW 0x0040U 821 #define PBE_GENERIC_RAM_ADDRSW_ADD6SW_M 0x0040U 822 #define PBE_GENERIC_RAM_ADDRSW_ADD6SW_S 6U 823 #define PBE_GENERIC_RAM_ADDRSW_ADD6SW_A 0x0000U 824 #define PBE_GENERIC_RAM_ADDRSW_ADD6SW_B 0x0040U 825 826 // Field: [5:5] add5sw 827 // 828 // Control what SW add5 is expected to belong to 829 #define PBE_GENERIC_RAM_ADDRSW_ADD5SW 0x0020U 830 #define PBE_GENERIC_RAM_ADDRSW_ADD5SW_M 0x0020U 831 #define PBE_GENERIC_RAM_ADDRSW_ADD5SW_S 5U 832 #define PBE_GENERIC_RAM_ADDRSW_ADD5SW_A 0x0000U 833 #define PBE_GENERIC_RAM_ADDRSW_ADD5SW_B 0x0020U 834 835 // Field: [4:4] add4sw 836 // 837 // Control what SW add4 is expected to belong to 838 #define PBE_GENERIC_RAM_ADDRSW_ADD4SW 0x0010U 839 #define PBE_GENERIC_RAM_ADDRSW_ADD4SW_M 0x0010U 840 #define PBE_GENERIC_RAM_ADDRSW_ADD4SW_S 4U 841 #define PBE_GENERIC_RAM_ADDRSW_ADD4SW_A 0x0000U 842 #define PBE_GENERIC_RAM_ADDRSW_ADD4SW_B 0x0010U 843 844 // Field: [3:3] add3sw 845 // 846 // Control what SW add3 is expected to belong to 847 #define PBE_GENERIC_RAM_ADDRSW_ADD3SW 0x0008U 848 #define PBE_GENERIC_RAM_ADDRSW_ADD3SW_M 0x0008U 849 #define PBE_GENERIC_RAM_ADDRSW_ADD3SW_S 3U 850 #define PBE_GENERIC_RAM_ADDRSW_ADD3SW_A 0x0000U 851 #define PBE_GENERIC_RAM_ADDRSW_ADD3SW_B 0x0008U 852 853 // Field: [2:2] add2sw 854 // 855 // Control what SW add2 is expected to belong to 856 #define PBE_GENERIC_RAM_ADDRSW_ADD2SW 0x0004U 857 #define PBE_GENERIC_RAM_ADDRSW_ADD2SW_M 0x0004U 858 #define PBE_GENERIC_RAM_ADDRSW_ADD2SW_S 2U 859 #define PBE_GENERIC_RAM_ADDRSW_ADD2SW_A 0x0000U 860 #define PBE_GENERIC_RAM_ADDRSW_ADD2SW_B 0x0004U 861 862 // Field: [1:1] add1sw 863 // 864 // Control what SW add1 is expected to belong to 865 #define PBE_GENERIC_RAM_ADDRSW_ADD1SW 0x0002U 866 #define PBE_GENERIC_RAM_ADDRSW_ADD1SW_M 0x0002U 867 #define PBE_GENERIC_RAM_ADDRSW_ADD1SW_S 1U 868 #define PBE_GENERIC_RAM_ADDRSW_ADD1SW_A 0x0000U 869 #define PBE_GENERIC_RAM_ADDRSW_ADD1SW_B 0x0002U 870 871 // Field: [0:0] add0sw 872 // 873 // Control what SW add0 is expected to belong to 874 #define PBE_GENERIC_RAM_ADDRSW_ADD0SW 0x0001U 875 #define PBE_GENERIC_RAM_ADDRSW_ADD0SW_M 0x0001U 876 #define PBE_GENERIC_RAM_ADDRSW_ADD0SW_S 0U 877 #define PBE_GENERIC_RAM_ADDRSW_ADD0SW_A 0x0000U 878 #define PBE_GENERIC_RAM_ADDRSW_ADD0SW_B 0x0001U 879 880 //****************************************************************************** 881 // Register: TESTCFG 882 //****************************************************************************** 883 // Field: [9:8] endcond 884 // 885 // Condition to end the command 886 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_W 2U 887 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_M 0x0300U 888 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_S 8U 889 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_NEVER 0x0000U 890 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_MDMRFE 0x0100U 891 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_TIMEOUT 0x0200U 892 #define PBE_GENERIC_RAM_TESTCFG_ENDCOND_TIMEOUT_DONE 0x0300U 893 894 // Field: [7:1] reserved1 895 // 896 // Reserved 897 #define PBE_GENERIC_RAM_TESTCFG_RESERVED1_W 7U 898 #define PBE_GENERIC_RAM_TESTCFG_RESERVED1_M 0x00FEU 899 #define PBE_GENERIC_RAM_TESTCFG_RESERVED1_S 1U 900 901 // Field: [0:0] start 902 // 903 // Condition to tigger the test command 904 #define PBE_GENERIC_RAM_TESTCFG_START 0x0001U 905 #define PBE_GENERIC_RAM_TESTCFG_START_M 0x0001U 906 #define PBE_GENERIC_RAM_TESTCFG_START_S 0U 907 #define PBE_GENERIC_RAM_TESTCFG_START_SYNC 0x0000U 908 #define PBE_GENERIC_RAM_TESTCFG_START_ASYNC 0x0001U 909 910 //****************************************************************************** 911 // Register: TESTAPI 912 //****************************************************************************** 913 // Field: [15:8] mdmapi 914 // 915 // Command to be sent to modem 916 #define PBE_GENERIC_RAM_TESTAPI_MDMAPI_W 8U 917 #define PBE_GENERIC_RAM_TESTAPI_MDMAPI_M 0xFF00U 918 #define PBE_GENERIC_RAM_TESTAPI_MDMAPI_S 8U 919 920 // Field: [7:0] rfeapi 921 // 922 // Command to be sent to RFE 923 #define PBE_GENERIC_RAM_TESTAPI_RFEAPI_W 8U 924 #define PBE_GENERIC_RAM_TESTAPI_RFEAPI_M 0x00FFU 925 #define PBE_GENERIC_RAM_TESTAPI_RFEAPI_S 0U 926 927 //****************************************************************************** 928 // Register: TESTTIMEOUT 929 //****************************************************************************** 930 // Field: [15:0] val 931 // 932 // Optional timeout value for test command, unit 0.25 us 933 #define PBE_GENERIC_RAM_TESTTIMEOUT_VAL_W 16U 934 #define PBE_GENERIC_RAM_TESTTIMEOUT_VAL_M 0xFFFFU 935 #define PBE_GENERIC_RAM_TESTTIMEOUT_VAL_S 0U 936 937 //****************************************************************************** 938 // Register: ADD0 939 //****************************************************************************** 940 // Field: [15:0] val 941 // 942 // address bits 943 #define PBE_GENERIC_RAM_ADD0_VAL_W 16U 944 #define PBE_GENERIC_RAM_ADD0_VAL_M 0xFFFFU 945 #define PBE_GENERIC_RAM_ADD0_VAL_S 0U 946 947 //****************************************************************************** 948 // Register: ADD1 949 //****************************************************************************** 950 // Field: [15:0] val 951 // 952 // address bits 953 #define PBE_GENERIC_RAM_ADD1_VAL_W 16U 954 #define PBE_GENERIC_RAM_ADD1_VAL_M 0xFFFFU 955 #define PBE_GENERIC_RAM_ADD1_VAL_S 0U 956 957 //****************************************************************************** 958 // Register: ADD2 959 //****************************************************************************** 960 // Field: [15:0] val 961 // 962 // address bits 963 #define PBE_GENERIC_RAM_ADD2_VAL_W 16U 964 #define PBE_GENERIC_RAM_ADD2_VAL_M 0xFFFFU 965 #define PBE_GENERIC_RAM_ADD2_VAL_S 0U 966 967 //****************************************************************************** 968 // Register: ADD3 969 //****************************************************************************** 970 // Field: [15:0] val 971 // 972 // address bits 973 #define PBE_GENERIC_RAM_ADD3_VAL_W 16U 974 #define PBE_GENERIC_RAM_ADD3_VAL_M 0xFFFFU 975 #define PBE_GENERIC_RAM_ADD3_VAL_S 0U 976 977 //****************************************************************************** 978 // Register: ADD4 979 //****************************************************************************** 980 // Field: [15:0] val 981 // 982 // address bits 983 #define PBE_GENERIC_RAM_ADD4_VAL_W 16U 984 #define PBE_GENERIC_RAM_ADD4_VAL_M 0xFFFFU 985 #define PBE_GENERIC_RAM_ADD4_VAL_S 0U 986 987 //****************************************************************************** 988 // Register: ADD5 989 //****************************************************************************** 990 // Field: [15:0] val 991 // 992 // address bits 993 #define PBE_GENERIC_RAM_ADD5_VAL_W 16U 994 #define PBE_GENERIC_RAM_ADD5_VAL_M 0xFFFFU 995 #define PBE_GENERIC_RAM_ADD5_VAL_S 0U 996 997 //****************************************************************************** 998 // Register: ADD6 999 //****************************************************************************** 1000 // Field: [15:0] val 1001 // 1002 // address bits 1003 #define PBE_GENERIC_RAM_ADD6_VAL_W 16U 1004 #define PBE_GENERIC_RAM_ADD6_VAL_M 0xFFFFU 1005 #define PBE_GENERIC_RAM_ADD6_VAL_S 0U 1006 1007 //****************************************************************************** 1008 // Register: ADD7 1009 //****************************************************************************** 1010 // Field: [15:0] val 1011 // 1012 // address bits 1013 #define PBE_GENERIC_RAM_ADD7_VAL_W 16U 1014 #define PBE_GENERIC_RAM_ADD7_VAL_M 0xFFFFU 1015 #define PBE_GENERIC_RAM_ADD7_VAL_S 0U 1016 1017 //****************************************************************************** 1018 // Register: ADD8 1019 //****************************************************************************** 1020 // Field: [15:0] val 1021 // 1022 // address bits 1023 #define PBE_GENERIC_RAM_ADD8_VAL_W 16U 1024 #define PBE_GENERIC_RAM_ADD8_VAL_M 0xFFFFU 1025 #define PBE_GENERIC_RAM_ADD8_VAL_S 0U 1026 1027 //****************************************************************************** 1028 // Register: ADD9 1029 //****************************************************************************** 1030 // Field: [15:0] val 1031 // 1032 // address bits 1033 #define PBE_GENERIC_RAM_ADD9_VAL_W 16U 1034 #define PBE_GENERIC_RAM_ADD9_VAL_M 0xFFFFU 1035 #define PBE_GENERIC_RAM_ADD9_VAL_S 0U 1036 1037 //****************************************************************************** 1038 // Register: ADD10 1039 //****************************************************************************** 1040 // Field: [15:0] val 1041 // 1042 // address bits 1043 #define PBE_GENERIC_RAM_ADD10_VAL_W 16U 1044 #define PBE_GENERIC_RAM_ADD10_VAL_M 0xFFFFU 1045 #define PBE_GENERIC_RAM_ADD10_VAL_S 0U 1046 1047 //****************************************************************************** 1048 // Register: ADD11 1049 //****************************************************************************** 1050 // Field: [15:0] val 1051 // 1052 // address bits 1053 #define PBE_GENERIC_RAM_ADD11_VAL_W 16U 1054 #define PBE_GENERIC_RAM_ADD11_VAL_M 0xFFFFU 1055 #define PBE_GENERIC_RAM_ADD11_VAL_S 0U 1056 1057 //****************************************************************************** 1058 // Register: ADD12 1059 //****************************************************************************** 1060 // Field: [15:0] val 1061 // 1062 // address bits 1063 #define PBE_GENERIC_RAM_ADD12_VAL_W 16U 1064 #define PBE_GENERIC_RAM_ADD12_VAL_M 0xFFFFU 1065 #define PBE_GENERIC_RAM_ADD12_VAL_S 0U 1066 1067 //****************************************************************************** 1068 // Register: ADD13 1069 //****************************************************************************** 1070 // Field: [15:0] val 1071 // 1072 // address bits 1073 #define PBE_GENERIC_RAM_ADD13_VAL_W 16U 1074 #define PBE_GENERIC_RAM_ADD13_VAL_M 0xFFFFU 1075 #define PBE_GENERIC_RAM_ADD13_VAL_S 0U 1076 1077 //****************************************************************************** 1078 // Register: ADD15 1079 //****************************************************************************** 1080 // Field: [15:0] val 1081 // 1082 // address bits 1083 #define PBE_GENERIC_RAM_ADD15_VAL_W 16U 1084 #define PBE_GENERIC_RAM_ADD15_VAL_M 0xFFFFU 1085 #define PBE_GENERIC_RAM_ADD15_VAL_S 0U 1086 1087 //****************************************************************************** 1088 // Register: NRXNOK 1089 //****************************************************************************** 1090 // Field: [15:0] val 1091 // 1092 // Number of packets received with CRC error 1093 #define PBE_GENERIC_RAM_NRXNOK_VAL_W 16U 1094 #define PBE_GENERIC_RAM_NRXNOK_VAL_M 0xFFFFU 1095 #define PBE_GENERIC_RAM_NRXNOK_VAL_S 0U 1096 1097 //****************************************************************************** 1098 // Register: NRXIGNORED 1099 //****************************************************************************** 1100 // Field: [15:0] val 1101 // 1102 // Number of packets received with CRC OK, but to be ignored by the MCU 1103 #define PBE_GENERIC_RAM_NRXIGNORED_VAL_W 16U 1104 #define PBE_GENERIC_RAM_NRXIGNORED_VAL_M 0xFFFFU 1105 #define PBE_GENERIC_RAM_NRXIGNORED_VAL_S 0U 1106 1107 //****************************************************************************** 1108 // Register: NRXEMPTY 1109 //****************************************************************************** 1110 // Field: [15:0] val 1111 // 1112 // Number of packets received with CRC OK and length zero 1113 #define PBE_GENERIC_RAM_NRXEMPTY_VAL_W 16U 1114 #define PBE_GENERIC_RAM_NRXEMPTY_VAL_M 0xFFFFU 1115 #define PBE_GENERIC_RAM_NRXEMPTY_VAL_S 0U 1116 1117 //****************************************************************************** 1118 // Register: NRXFIFOFULL 1119 //****************************************************************************** 1120 // Field: [15:0] val 1121 // 1122 // Number of received packets discarded because the Rx FIFO was full 1123 #define PBE_GENERIC_RAM_NRXFIFOFULL_VAL_W 16U 1124 #define PBE_GENERIC_RAM_NRXFIFOFULL_VAL_M 0xFFFFU 1125 #define PBE_GENERIC_RAM_NRXFIFOFULL_VAL_S 0U 1126 1127 //****************************************************************************** 1128 // Register: NRXOK 1129 //****************************************************************************** 1130 // Field: [15:0] val 1131 // 1132 // Number of non-empty packets received with CRC OK and not to be ignored by the MCU 1133 #define PBE_GENERIC_RAM_NRXOK_VAL_W 16U 1134 #define PBE_GENERIC_RAM_NRXOK_VAL_M 0xFFFFU 1135 #define PBE_GENERIC_RAM_NRXOK_VAL_S 0U 1136 1137 //****************************************************************************** 1138 // Register: NTX 1139 //****************************************************************************** 1140 // Field: [15:0] val 1141 // 1142 // Number of transmitted packets,incremented for every transmitted packet 1143 #define PBE_GENERIC_RAM_NTX_VAL_W 16U 1144 #define PBE_GENERIC_RAM_NTX_VAL_M 0xFFFFU 1145 #define PBE_GENERIC_RAM_NTX_VAL_S 0U 1146 1147 //****************************************************************************** 1148 // Register: NRXTIMEOUT 1149 //****************************************************************************** 1150 // Field: [15:0] val 1151 // 1152 // Number of RX timeout 1153 #define PBE_GENERIC_RAM_NRXTIMEOUT_VAL_W 16U 1154 #define PBE_GENERIC_RAM_NRXTIMEOUT_VAL_M 0xFFFFU 1155 #define PBE_GENERIC_RAM_NRXTIMEOUT_VAL_S 0U 1156 1157 //****************************************************************************** 1158 // Register: LASTRSSI 1159 //****************************************************************************** 1160 // Field: [15:0] val 1161 // 1162 // RSSI of last received packet with crc OK 1163 #define PBE_GENERIC_RAM_LASTRSSI_VAL_W 16U 1164 #define PBE_GENERIC_RAM_LASTRSSI_VAL_M 0xFFFFU 1165 #define PBE_GENERIC_RAM_LASTRSSI_VAL_S 0U 1166 1167 //****************************************************************************** 1168 // Register: LASTFREQOFF 1169 //****************************************************************************** 1170 // Field: [15:0] val 1171 // 1172 // FREQOFF of last received packet with crc OK 1173 #define PBE_GENERIC_RAM_LASTFREQOFF_VAL_W 16U 1174 #define PBE_GENERIC_RAM_LASTFREQOFF_VAL_M 0xFFFFU 1175 #define PBE_GENERIC_RAM_LASTFREQOFF_VAL_S 0U 1176 1177 //****************************************************************************** 1178 // Register: LASTLQI 1179 //****************************************************************************** 1180 // Field: [15:0] val 1181 // 1182 // LQI of last received packet with crc OK 1183 #define PBE_GENERIC_RAM_LASTLQI_VAL_W 16U 1184 #define PBE_GENERIC_RAM_LASTLQI_VAL_M 0xFFFFU 1185 #define PBE_GENERIC_RAM_LASTLQI_VAL_S 0U 1186 1187 //****************************************************************************** 1188 // Register: LASTTIMESTAMPL 1189 //****************************************************************************** 1190 // Field: [15:0] val 1191 // 1192 // Lower part of timestamp. 1193 #define PBE_GENERIC_RAM_LASTTIMESTAMPL_VAL_W 16U 1194 #define PBE_GENERIC_RAM_LASTTIMESTAMPL_VAL_M 0xFFFFU 1195 #define PBE_GENERIC_RAM_LASTTIMESTAMPL_VAL_S 0U 1196 1197 //****************************************************************************** 1198 // Register: LASTTIMESTAMPH 1199 //****************************************************************************** 1200 // Field: [15:0] val 1201 // 1202 // Upper part of timestamp. 1203 #define PBE_GENERIC_RAM_LASTTIMESTAMPH_VAL_W 16U 1204 #define PBE_GENERIC_RAM_LASTTIMESTAMPH_VAL_M 0xFFFFU 1205 #define PBE_GENERIC_RAM_LASTTIMESTAMPH_VAL_S 0U 1206 1207 //****************************************************************************** 1208 // Register: PEERADRINFO 1209 //****************************************************************************** 1210 // Field: [15:0] val 1211 // 1212 // Indicates which peer address that matched the received address. 1213 #define PBE_GENERIC_RAM_PEERADRINFO_VAL_W 16U 1214 #define PBE_GENERIC_RAM_PEERADRINFO_VAL_M 0xFFFFU 1215 #define PBE_GENERIC_RAM_PEERADRINFO_VAL_S 0U 1216 1217 //****************************************************************************** 1218 // Register: PEERADR1AL 1219 //****************************************************************************** 1220 // Field: [15:0] val 1221 // 1222 // bits 15:0 of address 1223 #define PBE_GENERIC_RAM_PEERADR1AL_VAL_W 16U 1224 #define PBE_GENERIC_RAM_PEERADR1AL_VAL_M 0xFFFFU 1225 #define PBE_GENERIC_RAM_PEERADR1AL_VAL_S 0U 1226 1227 //****************************************************************************** 1228 // Register: PEERADR1AH 1229 //****************************************************************************** 1230 // Field: [15:0] val 1231 // 1232 // bits 31:16 of address 1233 #define PBE_GENERIC_RAM_PEERADR1AH_VAL_W 16U 1234 #define PBE_GENERIC_RAM_PEERADR1AH_VAL_M 0xFFFFU 1235 #define PBE_GENERIC_RAM_PEERADR1AH_VAL_S 0U 1236 1237 //****************************************************************************** 1238 // Register: PEERADR0AL 1239 //****************************************************************************** 1240 // Field: [15:0] val 1241 // 1242 // bits 15:0 of address 1243 #define PBE_GENERIC_RAM_PEERADR0AL_VAL_W 16U 1244 #define PBE_GENERIC_RAM_PEERADR0AL_VAL_M 0xFFFFU 1245 #define PBE_GENERIC_RAM_PEERADR0AL_VAL_S 0U 1246 1247 //****************************************************************************** 1248 // Register: PEERADR0AH 1249 //****************************************************************************** 1250 // Field: [15:0] val 1251 // 1252 // bits 31:16 of address 1253 #define PBE_GENERIC_RAM_PEERADR0AH_VAL_W 16U 1254 #define PBE_GENERIC_RAM_PEERADR0AH_VAL_M 0xFFFFU 1255 #define PBE_GENERIC_RAM_PEERADR0AH_VAL_S 0U 1256 1257 //****************************************************************************** 1258 // Register: PEERADR1BL 1259 //****************************************************************************** 1260 // Field: [15:0] val 1261 // 1262 // bits 15:0 of address 1263 #define PBE_GENERIC_RAM_PEERADR1BL_VAL_W 16U 1264 #define PBE_GENERIC_RAM_PEERADR1BL_VAL_M 0xFFFFU 1265 #define PBE_GENERIC_RAM_PEERADR1BL_VAL_S 0U 1266 1267 //****************************************************************************** 1268 // Register: PEERADR1BH 1269 //****************************************************************************** 1270 // Field: [15:0] val 1271 // 1272 // bits 31:16 of address 1273 #define PBE_GENERIC_RAM_PEERADR1BH_VAL_W 16U 1274 #define PBE_GENERIC_RAM_PEERADR1BH_VAL_M 0xFFFFU 1275 #define PBE_GENERIC_RAM_PEERADR1BH_VAL_S 0U 1276 1277 //****************************************************************************** 1278 // Register: PEERADR0BL 1279 //****************************************************************************** 1280 // Field: [15:0] val 1281 // 1282 // bits 15:0 of address 1283 #define PBE_GENERIC_RAM_PEERADR0BL_VAL_W 16U 1284 #define PBE_GENERIC_RAM_PEERADR0BL_VAL_M 0xFFFFU 1285 #define PBE_GENERIC_RAM_PEERADR0BL_VAL_S 0U 1286 1287 //****************************************************************************** 1288 // Register: PEERADR0BH 1289 //****************************************************************************** 1290 // Field: [15:0] val 1291 // 1292 // bits 31:16 of address 1293 #define PBE_GENERIC_RAM_PEERADR0BH_VAL_W 16U 1294 #define PBE_GENERIC_RAM_PEERADR0BH_VAL_M 0xFFFFU 1295 #define PBE_GENERIC_RAM_PEERADR0BH_VAL_S 0U 1296 1297 //****************************************************************************** 1298 // Register: NESB 1299 //****************************************************************************** 1300 // Field: [15:6] reserved 1301 // 1302 // reserved 1303 #define PBE_GENERIC_RAM_NESB_RESERVED_W 10U 1304 #define PBE_GENERIC_RAM_NESB_RESERVED_M 0xFFC0U 1305 #define PBE_GENERIC_RAM_NESB_RESERVED_S 6U 1306 1307 // Field: [5:3] peeradrlen 1308 // 1309 // Length of address after header (0-4 bytes) at the start of the "Payload" 1310 #define PBE_GENERIC_RAM_NESB_PEERADRLEN_W 3U 1311 #define PBE_GENERIC_RAM_NESB_PEERADRLEN_M 0x0038U 1312 #define PBE_GENERIC_RAM_NESB_PEERADRLEN_S 3U 1313 1314 // Field: [2:2] nesbmode 1315 // 1316 // The default mode is ble5 without many features, aka generic ble5. 1317 #define PBE_GENERIC_RAM_NESB_NESBMODE 0x0004U 1318 #define PBE_GENERIC_RAM_NESB_NESBMODE_M 0x0004U 1319 #define PBE_GENERIC_RAM_NESB_NESBMODE_S 2U 1320 #define PBE_GENERIC_RAM_NESB_NESBMODE_OFF 0x0000U 1321 #define PBE_GENERIC_RAM_NESB_NESBMODE_ON 0x0004U 1322 1323 //****************************************************************************** 1324 // Register: CRCVAL0 1325 //****************************************************************************** 1326 // Field: [15:0] val 1327 // 1328 // 1329 #define PBE_GENERIC_RAM_CRCVAL0_VAL_W 16U 1330 #define PBE_GENERIC_RAM_CRCVAL0_VAL_M 0xFFFFU 1331 #define PBE_GENERIC_RAM_CRCVAL0_VAL_S 0U 1332 1333 //****************************************************************************** 1334 // Register: SEQSTAT0 1335 //****************************************************************************** 1336 // Field: [15:5] reserved 1337 // 1338 // reserved 1339 #define PBE_GENERIC_RAM_SEQSTAT0_RESERVED_W 11U 1340 #define PBE_GENERIC_RAM_SEQSTAT0_RESERVED_M 0xFFE0U 1341 #define PBE_GENERIC_RAM_SEQSTAT0_RESERVED_S 5U 1342 1343 // Field: [4:3] stopauto 1344 // 1345 // PTX may attempt to receive an Ack packet and then execute automatic retransmission if the reception failed due to sync timeout or wrong CRC or full RX fifo. PRX may execute automatic acknowledgement transmission and then return to sync search. 1346 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_W 2U 1347 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_M 0x0018U 1348 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_S 3U 1349 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_ALWAYS 0x0000U 1350 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_POSNOA 0x0008U 1351 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_NEGNOA 0x0010U 1352 #define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_NEVER 0x0018U 1353 1354 // Field: [2:1] pid 1355 // 1356 // NESB Sequence Number or packet ID. 1357 #define PBE_GENERIC_RAM_SEQSTAT0_PID_W 2U 1358 #define PBE_GENERIC_RAM_SEQSTAT0_PID_M 0x0006U 1359 #define PBE_GENERIC_RAM_SEQSTAT0_PID_S 1U 1360 1361 // Field: [0:0] valid 1362 // 1363 // 1364 #define PBE_GENERIC_RAM_SEQSTAT0_VALID 0x0001U 1365 #define PBE_GENERIC_RAM_SEQSTAT0_VALID_M 0x0001U 1366 #define PBE_GENERIC_RAM_SEQSTAT0_VALID_S 0U 1367 #define PBE_GENERIC_RAM_SEQSTAT0_VALID_NO 0x0000U 1368 #define PBE_GENERIC_RAM_SEQSTAT0_VALID_YES 0x0001U 1369 1370 //****************************************************************************** 1371 // Register: CRCVAL1 1372 //****************************************************************************** 1373 // Field: [15:0] val 1374 // 1375 // 1376 #define PBE_GENERIC_RAM_CRCVAL1_VAL_W 16U 1377 #define PBE_GENERIC_RAM_CRCVAL1_VAL_M 0xFFFFU 1378 #define PBE_GENERIC_RAM_CRCVAL1_VAL_S 0U 1379 1380 //****************************************************************************** 1381 // Register: SEQSTAT1 1382 //****************************************************************************** 1383 // Field: [15:5] reserved 1384 // 1385 // reserved 1386 #define PBE_GENERIC_RAM_SEQSTAT1_RESERVED_W 11U 1387 #define PBE_GENERIC_RAM_SEQSTAT1_RESERVED_M 0xFFE0U 1388 #define PBE_GENERIC_RAM_SEQSTAT1_RESERVED_S 5U 1389 1390 // Field: [4:3] stopauto 1391 // 1392 // PTX may attempt to receive an Ack packet and then execute automatic retransmission if the reception failed due to sync timeout or wrong CRC or full RX fifo. PRX may execute automatic acknowledgement transmission and then return to sync search. 1393 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_W 2U 1394 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_M 0x0018U 1395 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_S 3U 1396 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_ALWAYS 0x0000U 1397 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_POSNOA 0x0008U 1398 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_NEGNOA 0x0010U 1399 #define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_NEVER 0x0018U 1400 1401 // Field: [2:1] pid 1402 // 1403 // NESB Sequence Number or packet ID. 1404 #define PBE_GENERIC_RAM_SEQSTAT1_PID_W 2U 1405 #define PBE_GENERIC_RAM_SEQSTAT1_PID_M 0x0006U 1406 #define PBE_GENERIC_RAM_SEQSTAT1_PID_S 1U 1407 1408 // Field: [0:0] valid 1409 // 1410 // 1411 #define PBE_GENERIC_RAM_SEQSTAT1_VALID 0x0001U 1412 #define PBE_GENERIC_RAM_SEQSTAT1_VALID_M 0x0001U 1413 #define PBE_GENERIC_RAM_SEQSTAT1_VALID_S 0U 1414 #define PBE_GENERIC_RAM_SEQSTAT1_VALID_NO 0x0000U 1415 #define PBE_GENERIC_RAM_SEQSTAT1_VALID_YES 0x0001U 1416 1417 //****************************************************************************** 1418 // Register: STATUSBYTE 1419 //****************************************************************************** 1420 // Field: [15:5] reserved 1421 // 1422 // Flags 1423 #define PBE_GENERIC_RAM_STATUSBYTE_RESERVED_W 11U 1424 #define PBE_GENERIC_RAM_STATUSBYTE_RESERVED_M 0xFFE0U 1425 #define PBE_GENERIC_RAM_STATUSBYTE_RESERVED_S 5U 1426 1427 // Field: [4:4] swsel 1428 // 1429 // Indicates which syncword that was used. 0: SyncwordA, 1: SyncwordB. 1430 #define PBE_GENERIC_RAM_STATUSBYTE_SWSEL 0x0010U 1431 #define PBE_GENERIC_RAM_STATUSBYTE_SWSEL_M 0x0010U 1432 #define PBE_GENERIC_RAM_STATUSBYTE_SWSEL_S 4U 1433 1434 // Field: [3:3] ignored 1435 // 1436 // Ignored due to PID or address. 1437 #define PBE_GENERIC_RAM_STATUSBYTE_IGNORED 0x0008U 1438 #define PBE_GENERIC_RAM_STATUSBYTE_IGNORED_M 0x0008U 1439 #define PBE_GENERIC_RAM_STATUSBYTE_IGNORED_S 3U 1440 1441 // Field: [2:2] crcerror 1442 // 1443 // CRC check with PHA failed. 1444 #define PBE_GENERIC_RAM_STATUSBYTE_CRCERROR 0x0004U 1445 #define PBE_GENERIC_RAM_STATUSBYTE_CRCERROR_M 0x0004U 1446 #define PBE_GENERIC_RAM_STATUSBYTE_CRCERROR_S 2U 1447 1448 // Field: [1:0] phy 1449 // 1450 // aka Rate Indicator. 1451 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_W 2U 1452 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_M 0x0003U 1453 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_S 0U 1454 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_1M 0x0000U 1455 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_2M 0x0001U 1456 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_CODED_125K 0x0002U 1457 #define PBE_GENERIC_RAM_STATUSBYTE_PHY_CODED_500K 0x0003U 1458 1459 //****************************************************************************** 1460 // Register: TMPBYTE1 1461 //****************************************************************************** 1462 // Field: [15:0] val 1463 // 1464 // Flags 1465 #define PBE_GENERIC_RAM_TMPBYTE1_VAL_W 16U 1466 #define PBE_GENERIC_RAM_TMPBYTE1_VAL_M 0xFFFFU 1467 #define PBE_GENERIC_RAM_TMPBYTE1_VAL_S 0U 1468 1469 //****************************************************************************** 1470 // Register: TMPBYTE2 1471 //****************************************************************************** 1472 // Field: [15:0] val 1473 // 1474 // Flags 1475 #define PBE_GENERIC_RAM_TMPBYTE2_VAL_W 16U 1476 #define PBE_GENERIC_RAM_TMPBYTE2_VAL_M 0xFFFFU 1477 #define PBE_GENERIC_RAM_TMPBYTE2_VAL_S 0U 1478 1479 //****************************************************************************** 1480 // Register: TMPBYTE3 1481 //****************************************************************************** 1482 // Field: [15:0] val 1483 // 1484 // Flags 1485 #define PBE_GENERIC_RAM_TMPBYTE3_VAL_W 16U 1486 #define PBE_GENERIC_RAM_TMPBYTE3_VAL_M 0xFFFFU 1487 #define PBE_GENERIC_RAM_TMPBYTE3_VAL_S 0U 1488 1489 //****************************************************************************** 1490 // Register: TMPBYTE4 1491 //****************************************************************************** 1492 // Field: [15:0] val 1493 // 1494 // Flags 1495 #define PBE_GENERIC_RAM_TMPBYTE4_VAL_W 16U 1496 #define PBE_GENERIC_RAM_TMPBYTE4_VAL_M 0xFFFFU 1497 #define PBE_GENERIC_RAM_TMPBYTE4_VAL_S 0U 1498 1499 //****************************************************************************** 1500 // Register: TMPRSSI 1501 //****************************************************************************** 1502 // Field: [15:0] val 1503 // 1504 // RSSI 1505 #define PBE_GENERIC_RAM_TMPRSSI_VAL_W 16U 1506 #define PBE_GENERIC_RAM_TMPRSSI_VAL_M 0xFFFFU 1507 #define PBE_GENERIC_RAM_TMPRSSI_VAL_S 0U 1508 1509 //****************************************************************************** 1510 // Register: TMPADR1 1511 //****************************************************************************** 1512 // Field: [15:0] val 1513 // 1514 // Flags 1515 #define PBE_GENERIC_RAM_TMPADR1_VAL_W 16U 1516 #define PBE_GENERIC_RAM_TMPADR1_VAL_M 0xFFFFU 1517 #define PBE_GENERIC_RAM_TMPADR1_VAL_S 0U 1518 1519 //****************************************************************************** 1520 // Register: TMPADR2 1521 //****************************************************************************** 1522 // Field: [15:0] val 1523 // 1524 // Flags 1525 #define PBE_GENERIC_RAM_TMPADR2_VAL_W 16U 1526 #define PBE_GENERIC_RAM_TMPADR2_VAL_M 0xFFFFU 1527 #define PBE_GENERIC_RAM_TMPADR2_VAL_S 0U 1528 1529 //****************************************************************************** 1530 // Register: TMPADR3 1531 //****************************************************************************** 1532 // Field: [15:0] val 1533 // 1534 // Flags 1535 #define PBE_GENERIC_RAM_TMPADR3_VAL_W 16U 1536 #define PBE_GENERIC_RAM_TMPADR3_VAL_M 0xFFFFU 1537 #define PBE_GENERIC_RAM_TMPADR3_VAL_S 0U 1538 1539 //****************************************************************************** 1540 // Register: TMPADR4 1541 //****************************************************************************** 1542 // Field: [15:0] val 1543 // 1544 // Flags 1545 #define PBE_GENERIC_RAM_TMPADR4_VAL_W 16U 1546 #define PBE_GENERIC_RAM_TMPADR4_VAL_M 0xFFFFU 1547 #define PBE_GENERIC_RAM_TMPADR4_VAL_S 0U 1548 1549 1550 #endif // __PBE_GENERIC_RAM_REGS_H 1551
