1 // ===========================================================================
2 // This file is autogenerated, please DO NOT modify!
3 //
4 // Generated on  2024-05-23 12:09:01
5 // by user:      developer
6 // on machine:   swtools
7 // CWD:          /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs
8 // Commandline:  /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt
9 // C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt
10 //
11 // Relevant file version(s):
12 //
13 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl
14 //   rcs-info: (file not managed or unknown revision control system)
15 //   git-hash: 68a752a8737845355f7bdb320d25a59eac685840
16 //
17 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt
18 //   rcs-info: (file not managed or unknown revision control system)
19 //   git-hash: 8bfaeeaefba74967a4e950e027534072ffcb9647
20 //
21 // ===========================================================================
22 
23 
24 #ifndef __PBE_BLE_CS_RAM_REGS_H
25 #define __PBE_BLE_CS_RAM_REGS_H
26 
27 //******************************************************************************
28 // REGISTER OFFSETS
29 //******************************************************************************
30 //
31 #define PBE_BLE_CS_RAM_O_MODE                                        0x00000020U
32 
33 //
34 #define PBE_BLE_CS_RAM_O_ANTMSK                                      0x00000022U
35 
36 //
37 #define PBE_BLE_CS_RAM_O_ANT0                                        0x00000024U
38 
39 //
40 #define PBE_BLE_CS_RAM_O_ANT1                                        0x00000026U
41 
42 //
43 #define PBE_BLE_CS_RAM_O_ANT2                                        0x00000028U
44 
45 //
46 #define PBE_BLE_CS_RAM_O_ANT3                                        0x0000002AU
47 
48 //
49 #define PBE_BLE_CS_RAM_O_ANTN                                        0x0000002CU
50 
51 //
52 #define PBE_BLE_CS_RAM_O_TFCS                                        0x0000002EU
53 
54 //
55 #define PBE_BLE_CS_RAM_O_TFM                                         0x00000030U
56 
57 //
58 #define PBE_BLE_CS_RAM_O_TPM                                         0x00000032U
59 
60 //
61 #define PBE_BLE_CS_RAM_O_TIP1                                        0x00000034U
62 
63 //
64 #define PBE_BLE_CS_RAM_O_TIP2                                        0x00000036U
65 
66 //
67 #define PBE_BLE_CS_RAM_O_TRXTIMEOUTR013                              0x00000038U
68 
69 //
70 #define PBE_BLE_CS_RAM_O_TRXTIMEOUTI0                                0x0000003AU
71 
72 //
73 #define PBE_BLE_CS_RAM_O_TRXTIMEOUTI3                                0x0000003CU
74 
75 //
76 #define PBE_BLE_CS_RAM_O_TPILOTADJ                                   0x0000003EU
77 
78 //
79 #define PBE_BLE_CS_RAM_O_TSW                                         0x00000040U
80 
81 //
82 #define PBE_BLE_CS_RAM_O_DEMMISC3                                    0x00000042U
83 
84 //
85 #define PBE_BLE_CS_RAM_O_TRXWIDENINGR0                               0x00000044U
86 
87 //
88 #define PBE_BLE_CS_RAM_O_TSTEPREMAININGR0                            0x00000046U
89 
90 //
91 #define PBE_BLE_CS_RAM_O_TSWADJA                                     0x00000048U
92 
93 //
94 #define PBE_BLE_CS_RAM_O_TSWADJB                                     0x0000004AU
95 
96 //
97 #define PBE_BLE_CS_RAM_O_S2ROUTIDX                                   0x0000004CU
98 
99 //
100 #define PBE_BLE_CS_RAM_O_S2ROUTCHIDX                                 0x0000004EU
101 
102 //
103 #define PBE_BLE_CS_RAM_O_S2ROUTWORDSIZE                              0x00000050U
104 
105 //
106 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOADLEN                            0x00000052U
107 
108 //
109 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD0L                             0x00000054U
110 
111 //
112 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD0H                             0x00000056U
113 
114 //
115 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD1L                             0x00000058U
116 
117 //
118 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD1H                             0x0000005AU
119 
120 //
121 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD2L                             0x0000005CU
122 
123 //
124 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD2H                             0x0000005EU
125 
126 //
127 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD3L                             0x00000060U
128 
129 //
130 #define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD3H                             0x00000062U
131 
132 //
133 #define PBE_BLE_CS_RAM_O_FOFFSUM                                     0x00000064U
134 
135 //
136 #define PBE_BLE_CS_RAM_O_FOFFNUM                                     0x00000066U
137 
138 //
139 #define PBE_BLE_CS_RAM_O_FOFFLAST                                    0x00000068U
140 
141 //
142 #define PBE_BLE_CS_RAM_O_FOFFCOMP                                    0x0000006AU
143 
144 //
145 #define PBE_BLE_CS_RAM_O_RSSILAST                                    0x0000006CU
146 
147 //
148 #define PBE_BLE_CS_RAM_O_RSSISUM0                                    0x0000006EU
149 
150 //
151 #define PBE_BLE_CS_RAM_O_RSSINUM0                                    0x00000070U
152 
153 //
154 #define PBE_BLE_CS_RAM_O_NSTEPSDONE                                  0x00000072U
155 
156 //
157 #define PBE_BLE_CS_RAM_O_TSTEPACCL                                   0x00000074U
158 
159 //
160 #define PBE_BLE_CS_RAM_O_TSTEPACCH                                   0x00000076U
161 
162 //
163 #define PBE_BLE_CS_RAM_O_TSTEPACCTHRL                                0x00000078U
164 
165 //
166 #define PBE_BLE_CS_RAM_O_TSTEPACCTHRH                                0x0000007AU
167 
168 //
169 #define PBE_BLE_CS_RAM_O_TSTEPCOMP                                   0x0000007CU
170 
171 //
172 #define PBE_BLE_CS_RAM_O_TPOSTPROCESSDIV1                            0x0000007EU
173 
174 //
175 #define PBE_BLE_CS_RAM_O_TPOSTPROCESSDIV12                           0x00000080U
176 
177 //******************************************************************************
178 // Register: MODE
179 //******************************************************************************
180 // Field: [15:8] num_steps
181 //
182 //
183 #define PBE_BLE_CS_RAM_MODE_NUM_STEPS_W                                       8U
184 #define PBE_BLE_CS_RAM_MODE_NUM_STEPS_M                                  0xFF00U
185 #define PBE_BLE_CS_RAM_MODE_NUM_STEPS_S                                       8U
186 
187 // Field: [7:3] num_s2r
188 //
189 //
190 #define PBE_BLE_CS_RAM_MODE_NUM_S2R_W                                         5U
191 #define PBE_BLE_CS_RAM_MODE_NUM_S2R_M                                    0x00F8U
192 #define PBE_BLE_CS_RAM_MODE_NUM_S2R_S                                         3U
193 
194 // Field: [2:2] infinit
195 //
196 //
197 #define PBE_BLE_CS_RAM_MODE_INFINIT                                      0x0004U
198 #define PBE_BLE_CS_RAM_MODE_INFINIT_M                                    0x0004U
199 #define PBE_BLE_CS_RAM_MODE_INFINIT_S                                         2U
200 
201 // Field: [1:1] phy
202 //
203 //
204 #define PBE_BLE_CS_RAM_MODE_PHY                                          0x0002U
205 #define PBE_BLE_CS_RAM_MODE_PHY_M                                        0x0002U
206 #define PBE_BLE_CS_RAM_MODE_PHY_S                                             1U
207 
208 // Field: [0:0] role
209 //
210 //
211 #define PBE_BLE_CS_RAM_MODE_ROLE                                         0x0001U
212 #define PBE_BLE_CS_RAM_MODE_ROLE_M                                       0x0001U
213 #define PBE_BLE_CS_RAM_MODE_ROLE_S                                            0U
214 
215 //******************************************************************************
216 // Register: ANTMSK
217 //******************************************************************************
218 // Field: [7:0] val
219 //
220 //
221 #define PBE_BLE_CS_RAM_ANTMSK_VAL_W                                           8U
222 #define PBE_BLE_CS_RAM_ANTMSK_VAL_M                                      0x00FFU
223 #define PBE_BLE_CS_RAM_ANTMSK_VAL_S                                           0U
224 
225 //******************************************************************************
226 // Register: ANT0
227 //******************************************************************************
228 // Field: [7:0] val
229 //
230 //
231 #define PBE_BLE_CS_RAM_ANT0_VAL_W                                             8U
232 #define PBE_BLE_CS_RAM_ANT0_VAL_M                                        0x00FFU
233 #define PBE_BLE_CS_RAM_ANT0_VAL_S                                             0U
234 
235 //******************************************************************************
236 // Register: ANT1
237 //******************************************************************************
238 // Field: [7:0] val
239 //
240 //
241 #define PBE_BLE_CS_RAM_ANT1_VAL_W                                             8U
242 #define PBE_BLE_CS_RAM_ANT1_VAL_M                                        0x00FFU
243 #define PBE_BLE_CS_RAM_ANT1_VAL_S                                             0U
244 
245 //******************************************************************************
246 // Register: ANT2
247 //******************************************************************************
248 // Field: [7:0] val
249 //
250 //
251 #define PBE_BLE_CS_RAM_ANT2_VAL_W                                             8U
252 #define PBE_BLE_CS_RAM_ANT2_VAL_M                                        0x00FFU
253 #define PBE_BLE_CS_RAM_ANT2_VAL_S                                             0U
254 
255 //******************************************************************************
256 // Register: ANT3
257 //******************************************************************************
258 // Field: [7:0] val
259 //
260 //
261 #define PBE_BLE_CS_RAM_ANT3_VAL_W                                             8U
262 #define PBE_BLE_CS_RAM_ANT3_VAL_M                                        0x00FFU
263 #define PBE_BLE_CS_RAM_ANT3_VAL_S                                             0U
264 
265 //******************************************************************************
266 // Register: ANTN
267 //******************************************************************************
268 // Field: [7:0] val
269 //
270 //
271 #define PBE_BLE_CS_RAM_ANTN_VAL_W                                             8U
272 #define PBE_BLE_CS_RAM_ANTN_VAL_M                                        0x00FFU
273 #define PBE_BLE_CS_RAM_ANTN_VAL_S                                             0U
274 
275 //******************************************************************************
276 // Register: TFCS
277 //******************************************************************************
278 // Field: [15:0] val
279 //
280 //
281 #define PBE_BLE_CS_RAM_TFCS_VAL_W                                            16U
282 #define PBE_BLE_CS_RAM_TFCS_VAL_M                                        0xFFFFU
283 #define PBE_BLE_CS_RAM_TFCS_VAL_S                                             0U
284 
285 //******************************************************************************
286 // Register: TFM
287 //******************************************************************************
288 // Field: [15:0] val
289 //
290 //
291 #define PBE_BLE_CS_RAM_TFM_VAL_W                                             16U
292 #define PBE_BLE_CS_RAM_TFM_VAL_M                                         0xFFFFU
293 #define PBE_BLE_CS_RAM_TFM_VAL_S                                              0U
294 
295 //******************************************************************************
296 // Register: TPM
297 //******************************************************************************
298 // Field: [15:0] val
299 //
300 //
301 #define PBE_BLE_CS_RAM_TPM_VAL_W                                             16U
302 #define PBE_BLE_CS_RAM_TPM_VAL_M                                         0xFFFFU
303 #define PBE_BLE_CS_RAM_TPM_VAL_S                                              0U
304 
305 //******************************************************************************
306 // Register: TIP1
307 //******************************************************************************
308 // Field: [15:0] val
309 //
310 //
311 #define PBE_BLE_CS_RAM_TIP1_VAL_W                                            16U
312 #define PBE_BLE_CS_RAM_TIP1_VAL_M                                        0xFFFFU
313 #define PBE_BLE_CS_RAM_TIP1_VAL_S                                             0U
314 
315 //******************************************************************************
316 // Register: TIP2
317 //******************************************************************************
318 // Field: [15:0] val
319 //
320 //
321 #define PBE_BLE_CS_RAM_TIP2_VAL_W                                            16U
322 #define PBE_BLE_CS_RAM_TIP2_VAL_M                                        0xFFFFU
323 #define PBE_BLE_CS_RAM_TIP2_VAL_S                                             0U
324 
325 //******************************************************************************
326 // Register: TRXTIMEOUTR013
327 //******************************************************************************
328 // Field: [15:0] val
329 //
330 //
331 #define PBE_BLE_CS_RAM_TRXTIMEOUTR013_VAL_W                                  16U
332 #define PBE_BLE_CS_RAM_TRXTIMEOUTR013_VAL_M                              0xFFFFU
333 #define PBE_BLE_CS_RAM_TRXTIMEOUTR013_VAL_S                                   0U
334 
335 //******************************************************************************
336 // Register: TRXTIMEOUTI0
337 //******************************************************************************
338 // Field: [15:0] val
339 //
340 //
341 #define PBE_BLE_CS_RAM_TRXTIMEOUTI0_VAL_W                                    16U
342 #define PBE_BLE_CS_RAM_TRXTIMEOUTI0_VAL_M                                0xFFFFU
343 #define PBE_BLE_CS_RAM_TRXTIMEOUTI0_VAL_S                                     0U
344 
345 //******************************************************************************
346 // Register: TRXTIMEOUTI3
347 //******************************************************************************
348 // Field: [15:0] val
349 //
350 //
351 #define PBE_BLE_CS_RAM_TRXTIMEOUTI3_VAL_W                                    16U
352 #define PBE_BLE_CS_RAM_TRXTIMEOUTI3_VAL_M                                0xFFFFU
353 #define PBE_BLE_CS_RAM_TRXTIMEOUTI3_VAL_S                                     0U
354 
355 //******************************************************************************
356 // Register: TPILOTADJ
357 //******************************************************************************
358 // Field: [15:0] val
359 //
360 //
361 #define PBE_BLE_CS_RAM_TPILOTADJ_VAL_W                                       16U
362 #define PBE_BLE_CS_RAM_TPILOTADJ_VAL_M                                   0xFFFFU
363 #define PBE_BLE_CS_RAM_TPILOTADJ_VAL_S                                        0U
364 
365 //******************************************************************************
366 // Register: TSW
367 //******************************************************************************
368 // Field: [15:0] val
369 //
370 //
371 #define PBE_BLE_CS_RAM_TSW_VAL_W                                             16U
372 #define PBE_BLE_CS_RAM_TSW_VAL_M                                         0xFFFFU
373 #define PBE_BLE_CS_RAM_TSW_VAL_S                                              0U
374 
375 //******************************************************************************
376 // Register: DEMMISC3
377 //******************************************************************************
378 // Field: [15:0] val
379 //
380 //
381 #define PBE_BLE_CS_RAM_DEMMISC3_VAL_W                                        16U
382 #define PBE_BLE_CS_RAM_DEMMISC3_VAL_M                                    0xFFFFU
383 #define PBE_BLE_CS_RAM_DEMMISC3_VAL_S                                         0U
384 
385 //******************************************************************************
386 // Register: TRXWIDENINGR0
387 //******************************************************************************
388 // Field: [15:0] val
389 //
390 //
391 #define PBE_BLE_CS_RAM_TRXWIDENINGR0_VAL_W                                   16U
392 #define PBE_BLE_CS_RAM_TRXWIDENINGR0_VAL_M                               0xFFFFU
393 #define PBE_BLE_CS_RAM_TRXWIDENINGR0_VAL_S                                    0U
394 
395 //******************************************************************************
396 // Register: TSTEPREMAININGR0
397 //******************************************************************************
398 // Field: [15:0] val
399 //
400 //
401 #define PBE_BLE_CS_RAM_TSTEPREMAININGR0_VAL_W                                16U
402 #define PBE_BLE_CS_RAM_TSTEPREMAININGR0_VAL_M                            0xFFFFU
403 #define PBE_BLE_CS_RAM_TSTEPREMAININGR0_VAL_S                                 0U
404 
405 //******************************************************************************
406 // Register: TSWADJA
407 //******************************************************************************
408 // Field: [15:0] val
409 //
410 //
411 #define PBE_BLE_CS_RAM_TSWADJA_VAL_W                                         16U
412 #define PBE_BLE_CS_RAM_TSWADJA_VAL_M                                     0xFFFFU
413 #define PBE_BLE_CS_RAM_TSWADJA_VAL_S                                          0U
414 
415 //******************************************************************************
416 // Register: TSWADJB
417 //******************************************************************************
418 // Field: [15:0] val
419 //
420 //
421 #define PBE_BLE_CS_RAM_TSWADJB_VAL_W                                         16U
422 #define PBE_BLE_CS_RAM_TSWADJB_VAL_M                                     0xFFFFU
423 #define PBE_BLE_CS_RAM_TSWADJB_VAL_S                                          0U
424 
425 //******************************************************************************
426 // Register: S2ROUTIDX
427 //******************************************************************************
428 // Field: [15:0] val
429 //
430 //
431 #define PBE_BLE_CS_RAM_S2ROUTIDX_VAL_W                                       16U
432 #define PBE_BLE_CS_RAM_S2ROUTIDX_VAL_M                                   0xFFFFU
433 #define PBE_BLE_CS_RAM_S2ROUTIDX_VAL_S                                        0U
434 
435 //******************************************************************************
436 // Register: S2ROUTCHIDX
437 //******************************************************************************
438 // Field: [15:0] val
439 //
440 //
441 #define PBE_BLE_CS_RAM_S2ROUTCHIDX_VAL_W                                     16U
442 #define PBE_BLE_CS_RAM_S2ROUTCHIDX_VAL_M                                 0xFFFFU
443 #define PBE_BLE_CS_RAM_S2ROUTCHIDX_VAL_S                                      0U
444 
445 //******************************************************************************
446 // Register: S2ROUTWORDSIZE
447 //******************************************************************************
448 // Field: [15:0] val
449 //
450 //
451 #define PBE_BLE_CS_RAM_S2ROUTWORDSIZE_VAL_W                                  16U
452 #define PBE_BLE_CS_RAM_S2ROUTWORDSIZE_VAL_M                              0xFFFFU
453 #define PBE_BLE_CS_RAM_S2ROUTWORDSIZE_VAL_S                                   0U
454 
455 //******************************************************************************
456 // Register: S2ROUTPAYLOADLEN
457 //******************************************************************************
458 // Field: [15:0] val
459 //
460 //
461 #define PBE_BLE_CS_RAM_S2ROUTPAYLOADLEN_VAL_W                                16U
462 #define PBE_BLE_CS_RAM_S2ROUTPAYLOADLEN_VAL_M                            0xFFFFU
463 #define PBE_BLE_CS_RAM_S2ROUTPAYLOADLEN_VAL_S                                 0U
464 
465 //******************************************************************************
466 // Register: S2ROUTPAYLOAD0L
467 //******************************************************************************
468 // Field: [15:0] val
469 //
470 //
471 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0L_VAL_W                                 16U
472 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0L_VAL_M                             0xFFFFU
473 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0L_VAL_S                                  0U
474 
475 //******************************************************************************
476 // Register: S2ROUTPAYLOAD0H
477 //******************************************************************************
478 // Field: [15:0] val
479 //
480 //
481 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0H_VAL_W                                 16U
482 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0H_VAL_M                             0xFFFFU
483 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0H_VAL_S                                  0U
484 
485 //******************************************************************************
486 // Register: S2ROUTPAYLOAD1L
487 //******************************************************************************
488 // Field: [15:0] val
489 //
490 //
491 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1L_VAL_W                                 16U
492 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1L_VAL_M                             0xFFFFU
493 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1L_VAL_S                                  0U
494 
495 //******************************************************************************
496 // Register: S2ROUTPAYLOAD1H
497 //******************************************************************************
498 // Field: [15:0] val
499 //
500 //
501 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1H_VAL_W                                 16U
502 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1H_VAL_M                             0xFFFFU
503 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1H_VAL_S                                  0U
504 
505 //******************************************************************************
506 // Register: S2ROUTPAYLOAD2L
507 //******************************************************************************
508 // Field: [15:0] val
509 //
510 //
511 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2L_VAL_W                                 16U
512 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2L_VAL_M                             0xFFFFU
513 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2L_VAL_S                                  0U
514 
515 //******************************************************************************
516 // Register: S2ROUTPAYLOAD2H
517 //******************************************************************************
518 // Field: [15:0] val
519 //
520 //
521 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2H_VAL_W                                 16U
522 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2H_VAL_M                             0xFFFFU
523 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2H_VAL_S                                  0U
524 
525 //******************************************************************************
526 // Register: S2ROUTPAYLOAD3L
527 //******************************************************************************
528 // Field: [15:0] val
529 //
530 //
531 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3L_VAL_W                                 16U
532 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3L_VAL_M                             0xFFFFU
533 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3L_VAL_S                                  0U
534 
535 //******************************************************************************
536 // Register: S2ROUTPAYLOAD3H
537 //******************************************************************************
538 // Field: [15:0] val
539 //
540 //
541 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3H_VAL_W                                 16U
542 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3H_VAL_M                             0xFFFFU
543 #define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3H_VAL_S                                  0U
544 
545 //******************************************************************************
546 // Register: FOFFSUM
547 //******************************************************************************
548 // Field: [15:0] val
549 //
550 //
551 #define PBE_BLE_CS_RAM_FOFFSUM_VAL_W                                         16U
552 #define PBE_BLE_CS_RAM_FOFFSUM_VAL_M                                     0xFFFFU
553 #define PBE_BLE_CS_RAM_FOFFSUM_VAL_S                                          0U
554 
555 //******************************************************************************
556 // Register: FOFFNUM
557 //******************************************************************************
558 // Field: [15:0] val
559 //
560 //
561 #define PBE_BLE_CS_RAM_FOFFNUM_VAL_W                                         16U
562 #define PBE_BLE_CS_RAM_FOFFNUM_VAL_M                                     0xFFFFU
563 #define PBE_BLE_CS_RAM_FOFFNUM_VAL_S                                          0U
564 
565 //******************************************************************************
566 // Register: FOFFLAST
567 //******************************************************************************
568 // Field: [15:0] val
569 //
570 //
571 #define PBE_BLE_CS_RAM_FOFFLAST_VAL_W                                        16U
572 #define PBE_BLE_CS_RAM_FOFFLAST_VAL_M                                    0xFFFFU
573 #define PBE_BLE_CS_RAM_FOFFLAST_VAL_S                                         0U
574 
575 //******************************************************************************
576 // Register: FOFFCOMP
577 //******************************************************************************
578 // Field: [15:0] val
579 //
580 //
581 #define PBE_BLE_CS_RAM_FOFFCOMP_VAL_W                                        16U
582 #define PBE_BLE_CS_RAM_FOFFCOMP_VAL_M                                    0xFFFFU
583 #define PBE_BLE_CS_RAM_FOFFCOMP_VAL_S                                         0U
584 
585 //******************************************************************************
586 // Register: RSSILAST
587 //******************************************************************************
588 // Field: [15:0] val
589 //
590 //
591 #define PBE_BLE_CS_RAM_RSSILAST_VAL_W                                        16U
592 #define PBE_BLE_CS_RAM_RSSILAST_VAL_M                                    0xFFFFU
593 #define PBE_BLE_CS_RAM_RSSILAST_VAL_S                                         0U
594 
595 //******************************************************************************
596 // Register: RSSISUM0
597 //******************************************************************************
598 // Field: [15:0] val
599 //
600 //
601 #define PBE_BLE_CS_RAM_RSSISUM0_VAL_W                                        16U
602 #define PBE_BLE_CS_RAM_RSSISUM0_VAL_M                                    0xFFFFU
603 #define PBE_BLE_CS_RAM_RSSISUM0_VAL_S                                         0U
604 
605 //******************************************************************************
606 // Register: RSSINUM0
607 //******************************************************************************
608 // Field: [15:0] val
609 //
610 //
611 #define PBE_BLE_CS_RAM_RSSINUM0_VAL_W                                        16U
612 #define PBE_BLE_CS_RAM_RSSINUM0_VAL_M                                    0xFFFFU
613 #define PBE_BLE_CS_RAM_RSSINUM0_VAL_S                                         0U
614 
615 //******************************************************************************
616 // Register: NSTEPSDONE
617 //******************************************************************************
618 // Field: [15:0] val
619 //
620 //
621 #define PBE_BLE_CS_RAM_NSTEPSDONE_VAL_W                                      16U
622 #define PBE_BLE_CS_RAM_NSTEPSDONE_VAL_M                                  0xFFFFU
623 #define PBE_BLE_CS_RAM_NSTEPSDONE_VAL_S                                       0U
624 
625 //******************************************************************************
626 // Register: TSTEPACCL
627 //******************************************************************************
628 // Field: [15:0] val
629 //
630 //
631 #define PBE_BLE_CS_RAM_TSTEPACCL_VAL_W                                       16U
632 #define PBE_BLE_CS_RAM_TSTEPACCL_VAL_M                                   0xFFFFU
633 #define PBE_BLE_CS_RAM_TSTEPACCL_VAL_S                                        0U
634 
635 //******************************************************************************
636 // Register: TSTEPACCH
637 //******************************************************************************
638 // Field: [15:0] val
639 //
640 //
641 #define PBE_BLE_CS_RAM_TSTEPACCH_VAL_W                                       16U
642 #define PBE_BLE_CS_RAM_TSTEPACCH_VAL_M                                   0xFFFFU
643 #define PBE_BLE_CS_RAM_TSTEPACCH_VAL_S                                        0U
644 
645 //******************************************************************************
646 // Register: TSTEPACCTHRL
647 //******************************************************************************
648 // Field: [15:0] val
649 //
650 //
651 #define PBE_BLE_CS_RAM_TSTEPACCTHRL_VAL_W                                    16U
652 #define PBE_BLE_CS_RAM_TSTEPACCTHRL_VAL_M                                0xFFFFU
653 #define PBE_BLE_CS_RAM_TSTEPACCTHRL_VAL_S                                     0U
654 
655 //******************************************************************************
656 // Register: TSTEPACCTHRH
657 //******************************************************************************
658 // Field: [15:0] val
659 //
660 //
661 #define PBE_BLE_CS_RAM_TSTEPACCTHRH_VAL_W                                    16U
662 #define PBE_BLE_CS_RAM_TSTEPACCTHRH_VAL_M                                0xFFFFU
663 #define PBE_BLE_CS_RAM_TSTEPACCTHRH_VAL_S                                     0U
664 
665 //******************************************************************************
666 // Register: TSTEPCOMP
667 //******************************************************************************
668 // Field: [15:0] val
669 //
670 //
671 #define PBE_BLE_CS_RAM_TSTEPCOMP_VAL_W                                       16U
672 #define PBE_BLE_CS_RAM_TSTEPCOMP_VAL_M                                   0xFFFFU
673 #define PBE_BLE_CS_RAM_TSTEPCOMP_VAL_S                                        0U
674 
675 //******************************************************************************
676 // Register: TPOSTPROCESSDIV1
677 //******************************************************************************
678 // Field: [15:0] val
679 //
680 //
681 #define PBE_BLE_CS_RAM_TPOSTPROCESSDIV1_VAL_W                                16U
682 #define PBE_BLE_CS_RAM_TPOSTPROCESSDIV1_VAL_M                            0xFFFFU
683 #define PBE_BLE_CS_RAM_TPOSTPROCESSDIV1_VAL_S                                 0U
684 
685 //******************************************************************************
686 // Register: TPOSTPROCESSDIV12
687 //******************************************************************************
688 // Field: [15:0] val
689 //
690 //
691 #define PBE_BLE_CS_RAM_TPOSTPROCESSDIV12_VAL_W                               16U
692 #define PBE_BLE_CS_RAM_TPOSTPROCESSDIV12_VAL_M                           0xFFFFU
693 #define PBE_BLE_CS_RAM_TPOSTPROCESSDIV12_VAL_S                                0U
694 
695 
696 #endif // __PBE_BLE_CS_RAM_REGS_H
697