1 // =========================================================================== 2 // This file is autogenerated, please DO NOT modify! 3 // 4 // Generated on 2024-05-23 12:08:59 5 // by user: developer 6 // on machine: swtools 7 // CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5 8 // Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt 9 // C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt 10 // 11 // Relevant file version(s): 12 // 13 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl 14 // rcs-info: (file not managed or unknown revision control system) 15 // git-hash: 68a752a8737845355f7bdb320d25a59eac685840 16 // 17 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt 18 // rcs-info: (file not managed or unknown revision control system) 19 // git-hash: 0b79d4d13cc055db992ad8a96ee84cae10ff93ac 20 // 21 // =========================================================================== 22 23 24 #ifndef __PBE_BLE5_RAM_REGS_H 25 #define __PBE_BLE5_RAM_REGS_H 26 27 //****************************************************************************** 28 // REGISTER OFFSETS 29 //****************************************************************************** 30 // 31 #define PBE_BLE5_RAM_O_PHY 0x00000020U 32 33 // 34 #define PBE_BLE5_RAM_O_PRETXIFS500K 0x00000022U 35 36 // 37 #define PBE_BLE5_RAM_O_PRETXIFS 0x00000024U 38 39 // 40 #define PBE_BLE5_RAM_O_PRERXIFS 0x00000026U 41 42 // 43 #define PBE_BLE5_RAM_O_RXTIMEOUT 0x00000028U 44 45 // 46 #define PBE_BLE5_RAM_O_SYNTHCALTIMEOUT 0x0000002AU 47 48 // 49 #define PBE_BLE5_RAM_O_RECALTIMEOUT 0x0000002CU 50 51 // Scanner and Intor use both. Advertiser uses only RPAMODE_PEERADR, it shall be unaffected by RPAMODE_OWNADR. 52 #define PBE_BLE5_RAM_O_RPAMODE 0x0000002EU 53 54 // Configure Advertiser ENDCAUSE status. 55 #define PBE_BLE5_RAM_O_RPACONNECT 0x00000030U 56 57 // Configure FIFO usage 58 #define PBE_BLE5_RAM_O_FIFOCFG 0x00000032U 59 60 // Status for the received packet, appended in the RX FIFO depending on FIFOCFG. 61 #define PBE_BLE5_RAM_O_STATUSBYTE 0x00000034U 62 63 // 64 #define PBE_BLE5_RAM_O_NAKHUB 0x00000036U 65 66 // Initialization for the whitener, if 0 the whitener is not used 67 #define PBE_BLE5_RAM_O_WHITEINIT 0x00000038U 68 69 // Indicates how many bytes that are required after the PDU to hold the statuses configured in FIFOCFG. It has to be equal or greater. 70 #define PBE_BLE5_RAM_O_EXTRABYTES 0x0000003AU 71 72 // CRC initialization value Random by Link Layer for Data PDU, 0x555555 for Adv PDU. 73 #define PBE_BLE5_RAM_O_CRCINITL 0x0000003CU 74 75 // CRC initialization value Random by Link Layer for Data PDU, 0x555555 for Adv PDU. 76 #define PBE_BLE5_RAM_O_CRCINITH 0x0000003EU 77 78 // Sequencing status 79 #define PBE_BLE5_RAM_O_SEQSTAT 0x00000040U 80 81 // Back off count 82 #define PBE_BLE5_RAM_O_BACKOFFCNT 0x00000042U 83 84 // Configure scanner 85 #define PBE_BLE5_RAM_O_SCANCFG 0x00000044U 86 87 // Extended advertising configuration 88 #define PBE_BLE5_RAM_O_AECFG 0x00000046U 89 90 // Temporary storage for AE flags 91 #define PBE_BLE5_RAM_O_AETMP 0x00000048U 92 93 // Temporary storage for RT7_EXT_LENGTH 94 #define PBE_BLE5_RAM_O_EXTLENTMP 0x0000004AU 95 96 // WinOffset parameter to divide by 4 and write in CONNECT_IND message. This value will be decremented at each systimer event x until transmission of a CONNECT_REQ has started. If the value is decremented from 4, it is set to WINMOD. 97 #define PBE_BLE5_RAM_O_WINOFFSET 0x0000004CU 98 99 // 100 #define PBE_BLE5_RAM_O_WINMOD 0x0000004EU 101 102 // Maximum number of payload bytes in a packet. Checked in OP_BLE_TX_RAW and OP_BLE_RX_RAW. PDU TYPE specific lengths are confirmed in addition. 103 #define PBE_BLE5_RAM_O_MAXLEN 0x00000050U 104 105 // Filter policies 106 #define PBE_BLE5_RAM_O_FILTPOLICY 0x00000052U 107 108 // Address modes 109 #define PBE_BLE5_RAM_O_OWNADRTYPE 0x00000054U 110 111 // Address modes 112 #define PBE_BLE5_RAM_O_PEERADRTYPE 0x00000056U 113 114 // Low part of own address, 16 bits 115 #define PBE_BLE5_RAM_O_OWNADRL 0x00000058U 116 117 // Middle part of own address, 16 bits 118 #define PBE_BLE5_RAM_O_OWNADRM 0x0000005AU 119 120 // High part of own address, 16 bits 121 #define PBE_BLE5_RAM_O_OWNADRH 0x0000005CU 122 123 // 124 #define PBE_BLE5_RAM_O_TMPADRL 0x0000005EU 125 126 // 127 #define PBE_BLE5_RAM_O_TMPADRM 0x00000060U 128 129 // 130 #define PBE_BLE5_RAM_O_TMPADRH 0x00000062U 131 132 // Low part of peer address 133 #define PBE_BLE5_RAM_O_PEERADRL 0x00000064U 134 135 // Middle part of peer address 136 #define PBE_BLE5_RAM_O_PEERADRM 0x00000066U 137 138 // High part of peer address 139 #define PBE_BLE5_RAM_O_PEERADRH 0x00000068U 140 141 // 142 #define PBE_BLE5_RAM_O_NTXDONE 0x0000006AU 143 144 // 145 #define PBE_BLE5_RAM_O_NTXACK 0x0000006CU 146 147 // 148 #define PBE_BLE5_RAM_O_NTXCTLACK 0x0000006EU 149 150 // 151 #define PBE_BLE5_RAM_O_NTXCTL 0x00000070U 152 153 // 154 #define PBE_BLE5_RAM_O_NTXRETRANS 0x00000072U 155 156 // 157 #define PBE_BLE5_RAM_O_NRXNOK 0x00000074U 158 159 // 160 #define PBE_BLE5_RAM_O_NRXIGNORED 0x00000076U 161 162 // 163 #define PBE_BLE5_RAM_O_NRXEMPTY 0x00000078U 164 165 // 166 #define PBE_BLE5_RAM_O_NRXFIFOFULL 0x0000007AU 167 168 // 169 #define PBE_BLE5_RAM_O_NRXOK 0x0000007CU 170 171 // 172 #define PBE_BLE5_RAM_O_NTX 0x0000007EU 173 174 // 175 #define PBE_BLE5_RAM_O_NRXCTL 0x00000080U 176 177 // 178 #define PBE_BLE5_RAM_O_NRXCTLACK 0x00000082U 179 180 // 181 #define PBE_BLE5_RAM_O_LASTRSSI 0x00000084U 182 183 // 184 #define PBE_BLE5_RAM_O_FIRSTRXTIMEOUT 0x00000086U 185 186 // 187 #define PBE_BLE5_RAM_O_LASTTIMESTAMPL 0x00000088U 188 189 // 190 #define PBE_BLE5_RAM_O_LASTTIMESTAMPH 0x0000008AU 191 192 // 193 #define PBE_BLE5_RAM_O_MDCFG 0x0000008CU 194 195 // Configure Advertiser Task Behavior. This configuration determines the control flow of the advertiser command(OP_BLE_ADV) on the PBE_API. More than one bit may be high at the same time. 196 #define PBE_BLE5_RAM_O_ADVCFG 0x0000008EU 197 198 // Temporary register for storing RSSI 199 #define PBE_BLE5_RAM_O_TMPRSSI 0x00000090U 200 201 // 202 #define PBE_BLE5_RAM_O_FIRSTTIMESTAMPL 0x00000094U 203 204 // 205 #define PBE_BLE5_RAM_O_FIRSTTIMESTAMPH 0x00000096U 206 207 // 208 #define PBE_BLE5_RAM_O_FL1RESULT 0x00000098U 209 210 // 211 #define PBE_BLE5_RAM_O_FL1MASK 0x0000009AU 212 213 // 214 #define PBE_BLE5_RAM_O_FL2RESULT 0x0000009CU 215 216 // 217 #define PBE_BLE5_RAM_O_FL2MASK 0x0000009EU 218 219 // 220 #define PBE_BLE5_RAM_O_FLSTAT 0x000000A0U 221 222 // 223 #define PBE_BLE5_RAM_O_TMPATYPE 0x000000A2U 224 225 // 226 #define PBE_BLE5_RAM_O_PATTERN 0x000000A4U 227 228 // 229 #define PBE_BLE5_RAM_O_RFINTERVAL 0x000000A6U 230 231 // 232 #define PBE_BLE5_RAM_O_NTXTARGET 0x000000A8U 233 234 // combined tx/rx/fs configuration 235 #define PBE_BLE5_RAM_O_OPCFG 0x000000AAU 236 237 // 238 #define PBE_BLE5_RAM_O_FL1INFO0 0x000000ACU 239 240 // 241 #define PBE_BLE5_RAM_O_FL1ADRL0 0x000000AEU 242 243 // 244 #define PBE_BLE5_RAM_O_FL1ADRM0 0x000000B0U 245 246 // 247 #define PBE_BLE5_RAM_O_FL1ADRH0 0x000000B2U 248 249 // 250 #define PBE_BLE5_RAM_O_FL1INFO1 0x000000B4U 251 252 // 253 #define PBE_BLE5_RAM_O_FL1ADRL1 0x000000B6U 254 255 // 256 #define PBE_BLE5_RAM_O_FL1ADRM1 0x000000B8U 257 258 // 259 #define PBE_BLE5_RAM_O_FL1ADRH1 0x000000BAU 260 261 // 262 #define PBE_BLE5_RAM_O_FL1INFO2 0x000000BCU 263 264 // 265 #define PBE_BLE5_RAM_O_FL1ADRL2 0x000000BEU 266 267 // 268 #define PBE_BLE5_RAM_O_FL1ADRM2 0x000000C0U 269 270 // 271 #define PBE_BLE5_RAM_O_FL1ADRH2 0x000000C2U 272 273 // 274 #define PBE_BLE5_RAM_O_FL1INFO3 0x000000C4U 275 276 // 277 #define PBE_BLE5_RAM_O_FL1ADRL3 0x000000C6U 278 279 // 280 #define PBE_BLE5_RAM_O_FL1ADRM3 0x000000C8U 281 282 // 283 #define PBE_BLE5_RAM_O_FL1ADRH3 0x000000CAU 284 285 // 286 #define PBE_BLE5_RAM_O_FL1INFO4 0x000000CCU 287 288 // 289 #define PBE_BLE5_RAM_O_FL1ADRL4 0x000000CEU 290 291 // 292 #define PBE_BLE5_RAM_O_FL1ADRM4 0x000000D0U 293 294 // 295 #define PBE_BLE5_RAM_O_FL1ADRH4 0x000000D2U 296 297 // 298 #define PBE_BLE5_RAM_O_FL1INFO5 0x000000D4U 299 300 // 301 #define PBE_BLE5_RAM_O_FL1ADRL5 0x000000D6U 302 303 // 304 #define PBE_BLE5_RAM_O_FL1ADRM5 0x000000D8U 305 306 // 307 #define PBE_BLE5_RAM_O_FL1ADRH5 0x000000DAU 308 309 // 310 #define PBE_BLE5_RAM_O_FL1INFO6 0x000000DCU 311 312 // 313 #define PBE_BLE5_RAM_O_FL1ADRL6 0x000000DEU 314 315 // 316 #define PBE_BLE5_RAM_O_FL1ADRM6 0x000000E0U 317 318 // 319 #define PBE_BLE5_RAM_O_FL1ADRH6 0x000000E2U 320 321 // 322 #define PBE_BLE5_RAM_O_FL1INFO7 0x000000E4U 323 324 // 325 #define PBE_BLE5_RAM_O_FL1ADRL7 0x000000E6U 326 327 // 328 #define PBE_BLE5_RAM_O_FL1ADRM7 0x000000E8U 329 330 // 331 #define PBE_BLE5_RAM_O_FL1ADRH7 0x000000EAU 332 333 // 334 #define PBE_BLE5_RAM_O_FL1INFO8 0x000000ECU 335 336 // 337 #define PBE_BLE5_RAM_O_FL1ADRL8 0x000000EEU 338 339 // 340 #define PBE_BLE5_RAM_O_FL1ADRM8 0x000000F0U 341 342 // 343 #define PBE_BLE5_RAM_O_FL1ADRH8 0x000000F2U 344 345 // 346 #define PBE_BLE5_RAM_O_FL1INFO9 0x000000F4U 347 348 // 349 #define PBE_BLE5_RAM_O_FL1ADRL9 0x000000F6U 350 351 // 352 #define PBE_BLE5_RAM_O_FL1ADRM9 0x000000F8U 353 354 // 355 #define PBE_BLE5_RAM_O_FL1ADRH9 0x000000FAU 356 357 // 358 #define PBE_BLE5_RAM_O_FL1INFO10 0x000000FCU 359 360 // 361 #define PBE_BLE5_RAM_O_FL1ADRL10 0x000000FEU 362 363 // 364 #define PBE_BLE5_RAM_O_FL1ADRM10 0x00000100U 365 366 // 367 #define PBE_BLE5_RAM_O_FL1ADRH10 0x00000102U 368 369 // 370 #define PBE_BLE5_RAM_O_FL1INFO11 0x00000104U 371 372 // 373 #define PBE_BLE5_RAM_O_FL1ADRL11 0x00000106U 374 375 // 376 #define PBE_BLE5_RAM_O_FL1ADRM11 0x00000108U 377 378 // 379 #define PBE_BLE5_RAM_O_FL1ADRH11 0x0000010AU 380 381 // 382 #define PBE_BLE5_RAM_O_FL1INFO12 0x0000010CU 383 384 // 385 #define PBE_BLE5_RAM_O_FL1ADRL12 0x0000010EU 386 387 // 388 #define PBE_BLE5_RAM_O_FL1ADRM12 0x00000110U 389 390 // 391 #define PBE_BLE5_RAM_O_FL1ADRH12 0x00000112U 392 393 // 394 #define PBE_BLE5_RAM_O_FL1INFO13 0x00000114U 395 396 // 397 #define PBE_BLE5_RAM_O_FL1ADRL13 0x00000116U 398 399 // 400 #define PBE_BLE5_RAM_O_FL1ADRM13 0x00000118U 401 402 // 403 #define PBE_BLE5_RAM_O_FL1ADRH13 0x0000011AU 404 405 // 406 #define PBE_BLE5_RAM_O_FL1INFO14 0x0000011CU 407 408 // 409 #define PBE_BLE5_RAM_O_FL1ADRL14 0x0000011EU 410 411 // 412 #define PBE_BLE5_RAM_O_FL1ADRM14 0x00000120U 413 414 // 415 #define PBE_BLE5_RAM_O_FL1ADRH14 0x00000122U 416 417 // 418 #define PBE_BLE5_RAM_O_FL1INFO15 0x00000124U 419 420 // 421 #define PBE_BLE5_RAM_O_FL1ADRL15 0x00000126U 422 423 // 424 #define PBE_BLE5_RAM_O_FL1ADRM15 0x00000128U 425 426 // 427 #define PBE_BLE5_RAM_O_FL1ADRH15 0x0000012AU 428 429 // 430 #define PBE_BLE5_RAM_O_FL2INFO0 0x0000012CU 431 432 // 433 #define PBE_BLE5_RAM_O_FL2ADRL0 0x0000012EU 434 435 // 436 #define PBE_BLE5_RAM_O_FL2ADRM0 0x00000130U 437 438 // 439 #define PBE_BLE5_RAM_O_FL2ADRH0 0x00000132U 440 441 // 442 #define PBE_BLE5_RAM_O_FL2INFO1 0x00000134U 443 444 // 445 #define PBE_BLE5_RAM_O_FL2ADRL1 0x00000136U 446 447 // 448 #define PBE_BLE5_RAM_O_FL2ADRM1 0x00000138U 449 450 // 451 #define PBE_BLE5_RAM_O_FL2ADRH1 0x0000013AU 452 453 // 454 #define PBE_BLE5_RAM_O_FL2INFO2 0x0000013CU 455 456 // 457 #define PBE_BLE5_RAM_O_FL2ADRL2 0x0000013EU 458 459 // 460 #define PBE_BLE5_RAM_O_FL2ADRM2 0x00000140U 461 462 // 463 #define PBE_BLE5_RAM_O_FL2ADRH2 0x00000142U 464 465 // 466 #define PBE_BLE5_RAM_O_FL2INFO3 0x00000144U 467 468 // 469 #define PBE_BLE5_RAM_O_FL2ADRL3 0x00000146U 470 471 // 472 #define PBE_BLE5_RAM_O_FL2ADRM3 0x00000148U 473 474 // 475 #define PBE_BLE5_RAM_O_FL2ADRH3 0x0000014AU 476 477 // 478 #define PBE_BLE5_RAM_O_FL2INFO4 0x0000014CU 479 480 // 481 #define PBE_BLE5_RAM_O_FL2ADRL4 0x0000014EU 482 483 // 484 #define PBE_BLE5_RAM_O_FL2ADRM4 0x00000150U 485 486 // 487 #define PBE_BLE5_RAM_O_FL2ADRH4 0x00000152U 488 489 // 490 #define PBE_BLE5_RAM_O_FL2INFO5 0x00000154U 491 492 // 493 #define PBE_BLE5_RAM_O_FL2ADRL5 0x00000156U 494 495 // 496 #define PBE_BLE5_RAM_O_FL2ADRM5 0x00000158U 497 498 // 499 #define PBE_BLE5_RAM_O_FL2ADRH5 0x0000015AU 500 501 // 502 #define PBE_BLE5_RAM_O_FL2INFO6 0x0000015CU 503 504 // 505 #define PBE_BLE5_RAM_O_FL2ADRL6 0x0000015EU 506 507 // 508 #define PBE_BLE5_RAM_O_FL2ADRM6 0x00000160U 509 510 // 511 #define PBE_BLE5_RAM_O_FL2ADRH6 0x00000162U 512 513 // 514 #define PBE_BLE5_RAM_O_FL2INFO7 0x00000164U 515 516 // 517 #define PBE_BLE5_RAM_O_FL2ADRL7 0x00000166U 518 519 // 520 #define PBE_BLE5_RAM_O_FL2ADRM7 0x00000168U 521 522 // 523 #define PBE_BLE5_RAM_O_FL2ADRH7 0x0000016AU 524 525 // 526 #define PBE_BLE5_RAM_O_FL2INFO8 0x0000016CU 527 528 // 529 #define PBE_BLE5_RAM_O_FL2ADRL8 0x0000016EU 530 531 // 532 #define PBE_BLE5_RAM_O_FL2ADRM8 0x00000170U 533 534 // 535 #define PBE_BLE5_RAM_O_FL2ADRH8 0x00000172U 536 537 // 538 #define PBE_BLE5_RAM_O_FL2INFO9 0x00000174U 539 540 // 541 #define PBE_BLE5_RAM_O_FL2ADRL9 0x00000176U 542 543 // 544 #define PBE_BLE5_RAM_O_FL2ADRM9 0x00000178U 545 546 // 547 #define PBE_BLE5_RAM_O_FL2ADRH9 0x0000017AU 548 549 // 550 #define PBE_BLE5_RAM_O_FL2INFO10 0x0000017CU 551 552 // 553 #define PBE_BLE5_RAM_O_FL2ADRL10 0x0000017EU 554 555 // 556 #define PBE_BLE5_RAM_O_FL2ADRM10 0x00000180U 557 558 // 559 #define PBE_BLE5_RAM_O_FL2ADRH10 0x00000182U 560 561 // 562 #define PBE_BLE5_RAM_O_FL2INFO11 0x00000184U 563 564 // 565 #define PBE_BLE5_RAM_O_FL2ADRL11 0x00000186U 566 567 // 568 #define PBE_BLE5_RAM_O_FL2ADRM11 0x00000188U 569 570 // 571 #define PBE_BLE5_RAM_O_FL2ADRH11 0x0000018AU 572 573 // 574 #define PBE_BLE5_RAM_O_FL2INFO12 0x0000018CU 575 576 // 577 #define PBE_BLE5_RAM_O_FL2ADRL12 0x0000018EU 578 579 // 580 #define PBE_BLE5_RAM_O_FL2ADRM12 0x00000190U 581 582 // 583 #define PBE_BLE5_RAM_O_FL2ADRH12 0x00000192U 584 585 // 586 #define PBE_BLE5_RAM_O_FL2INFO13 0x00000194U 587 588 // 589 #define PBE_BLE5_RAM_O_FL2ADRL13 0x00000196U 590 591 // 592 #define PBE_BLE5_RAM_O_FL2ADRM13 0x00000198U 593 594 // 595 #define PBE_BLE5_RAM_O_FL2ADRH13 0x0000019AU 596 597 // 598 #define PBE_BLE5_RAM_O_FL2INFO14 0x0000019CU 599 600 // 601 #define PBE_BLE5_RAM_O_FL2ADRL14 0x0000019EU 602 603 // 604 #define PBE_BLE5_RAM_O_FL2ADRM14 0x000001A0U 605 606 // 607 #define PBE_BLE5_RAM_O_FL2ADRH14 0x000001A2U 608 609 // 610 #define PBE_BLE5_RAM_O_FL2INFO15 0x000001A4U 611 612 // 613 #define PBE_BLE5_RAM_O_FL2ADRL15 0x000001A6U 614 615 // 616 #define PBE_BLE5_RAM_O_FL2ADRM15 0x000001A8U 617 618 // 619 #define PBE_BLE5_RAM_O_FL2ADRH15 0x000001AAU 620 621 //****************************************************************************** 622 // Register: PHY 623 //****************************************************************************** 624 // Field: [1:0] sel 625 // 626 // Used to pass on the value of the Coding Indicator, 627 #define PBE_BLE5_RAM_PHY_SEL_W 2U 628 #define PBE_BLE5_RAM_PHY_SEL_M 0x0003U 629 #define PBE_BLE5_RAM_PHY_SEL_S 0U 630 #define PBE_BLE5_RAM_PHY_SEL_1M 0x0000U 631 #define PBE_BLE5_RAM_PHY_SEL_2M 0x0001U 632 #define PBE_BLE5_RAM_PHY_SEL_CODED_125K 0x0002U 633 #define PBE_BLE5_RAM_PHY_SEL_CODED_500K 0x0003U 634 635 //****************************************************************************** 636 // Register: PRETXIFS500K 637 //****************************************************************************** 638 // Field: [15:0] val 639 // 640 // For bluetooth long range (BLR) and the 500k data rate only. Base value used after RX to set timer0 for when to start Transmission. 641 #define PBE_BLE5_RAM_PRETXIFS500K_VAL_W 16U 642 #define PBE_BLE5_RAM_PRETXIFS500K_VAL_M 0xFFFFU 643 #define PBE_BLE5_RAM_PRETXIFS500K_VAL_S 0U 644 645 //****************************************************************************** 646 // Register: PRETXIFS 647 //****************************************************************************** 648 // Field: [15:0] val 649 // 650 // Base value used after RX to set timer0 for when to start Transmission. 651 #define PBE_BLE5_RAM_PRETXIFS_VAL_W 16U 652 #define PBE_BLE5_RAM_PRETXIFS_VAL_M 0xFFFFU 653 #define PBE_BLE5_RAM_PRETXIFS_VAL_S 0U 654 655 //****************************************************************************** 656 // Register: PRERXIFS 657 //****************************************************************************** 658 // Field: [15:0] val 659 // 660 // Base value used after TX to set timer0 for when to start Receiving. 661 #define PBE_BLE5_RAM_PRERXIFS_VAL_W 16U 662 #define PBE_BLE5_RAM_PRERXIFS_VAL_M 0xFFFFU 663 #define PBE_BLE5_RAM_PRERXIFS_VAL_S 0U 664 665 //****************************************************************************** 666 // Register: RXTIMEOUT 667 //****************************************************************************** 668 // Field: [15:0] val 669 // 670 // Time to stay in RX before giving up sync search. Only used in T_IFS scenarios. If VAL = 0 then the PBE waits forever or until the CM0 manually interrupts. 671 #define PBE_BLE5_RAM_RXTIMEOUT_VAL_W 16U 672 #define PBE_BLE5_RAM_RXTIMEOUT_VAL_M 0xFFFFU 673 #define PBE_BLE5_RAM_RXTIMEOUT_VAL_S 0U 674 675 //****************************************************************************** 676 // Register: SYNTHCALTIMEOUT 677 //****************************************************************************** 678 // Field: [15:0] val 679 // 680 // How many µs the PBE shall set its local timer to wait for the RFE synth calibration. 681 #define PBE_BLE5_RAM_SYNTHCALTIMEOUT_VAL_W 16U 682 #define PBE_BLE5_RAM_SYNTHCALTIMEOUT_VAL_M 0xFFFFU 683 #define PBE_BLE5_RAM_SYNTHCALTIMEOUT_VAL_S 0U 684 685 //****************************************************************************** 686 // Register: RECALTIMEOUT 687 //****************************************************************************** 688 // Field: [15:0] val 689 // 690 // How many µs the PBE shall set its local timer to wait for the RFE synth re-calibration. 691 #define PBE_BLE5_RAM_RECALTIMEOUT_VAL_W 16U 692 #define PBE_BLE5_RAM_RECALTIMEOUT_VAL_M 0xFFFFU 693 #define PBE_BLE5_RAM_RECALTIMEOUT_VAL_S 0U 694 695 //****************************************************************************** 696 // Register: RPAMODE 697 //****************************************************************************** 698 // Field: [3:3] ownadr 699 // 700 // Filtering of own (receiver) address 701 #define PBE_BLE5_RAM_RPAMODE_OWNADR 0x0008U 702 #define PBE_BLE5_RAM_RPAMODE_OWNADR_M 0x0008U 703 #define PBE_BLE5_RAM_RPAMODE_OWNADR_S 3U 704 705 // Field: [2:2] peeradr 706 // 707 // Filtering of peer (transmitter) address, may use the Filter Accept List 708 #define PBE_BLE5_RAM_RPAMODE_PEERADR 0x0004U 709 #define PBE_BLE5_RAM_RPAMODE_PEERADR_M 0x0004U 710 #define PBE_BLE5_RAM_RPAMODE_PEERADR_S 2U 711 712 //****************************************************************************** 713 // Register: RPACONNECT 714 //****************************************************************************** 715 // Field: [0:0] endadv 716 // 717 // 718 #define PBE_BLE5_RAM_RPACONNECT_ENDADV 0x0001U 719 #define PBE_BLE5_RAM_RPACONNECT_ENDADV_M 0x0001U 720 #define PBE_BLE5_RAM_RPACONNECT_ENDADV_S 0U 721 722 //****************************************************************************** 723 // Register: FIFOCFG 724 //****************************************************************************** 725 // Field: [8:8] appendtimestamp 726 // 727 // 728 #define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP 0x0100U 729 #define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_M 0x0100U 730 #define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_S 8U 731 #define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_DIS 0x0000U 732 #define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_ENA 0x0100U 733 734 // Field: [7:7] appendrssi 735 // 736 // 737 #define PBE_BLE5_RAM_FIFOCFG_APPENDRSSI 0x0080U 738 #define PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M 0x0080U 739 #define PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_S 7U 740 741 // Field: [6:6] appendfreqest 742 // 743 // 744 #define PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST 0x0040U 745 #define PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_M 0x0040U 746 #define PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_S 6U 747 748 // Field: [5:5] appendlqi 749 // 750 // 751 #define PBE_BLE5_RAM_FIFOCFG_APPENDLQI 0x0020U 752 #define PBE_BLE5_RAM_FIFOCFG_APPENDLQI_M 0x0020U 753 #define PBE_BLE5_RAM_FIFOCFG_APPENDLQI_S 5U 754 755 // Field: [4:4] appendstatus 756 // 757 // CRCOK, Ignore, Code rate 758 #define PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS 0x0010U 759 #define PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M 0x0010U 760 #define PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_S 4U 761 762 // Field: [3:3] appendcrc 763 // 764 // Append all received crc bits 765 #define PBE_BLE5_RAM_FIFOCFG_APPENDCRC 0x0008U 766 #define PBE_BLE5_RAM_FIFOCFG_APPENDCRC_M 0x0008U 767 #define PBE_BLE5_RAM_FIFOCFG_APPENDCRC_S 3U 768 769 // Field: [2:2] autoflushempty 770 // 771 // 772 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY 0x0004U 773 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_M 0x0004U 774 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_S 2U 775 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_KEEP 0x0000U 776 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_FLUSH 0x0004U 777 778 // Field: [1:1] autoflushign 779 // 780 // 781 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN 0x0002U 782 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_M 0x0002U 783 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_S 1U 784 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_KEEP 0x0000U 785 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_FLUSH 0x0002U 786 787 // Field: [0:0] autoflushcrc 788 // 789 // 790 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC 0x0001U 791 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_M 0x0001U 792 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_S 0U 793 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_KEEP 0x0000U 794 #define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_FLUSH 0x0001U 795 796 //****************************************************************************** 797 // Register: STATUSBYTE 798 //****************************************************************************** 799 // Field: [15:5] reserved 800 // 801 // Flags 802 #define PBE_BLE5_RAM_STATUSBYTE_RESERVED_W 11U 803 #define PBE_BLE5_RAM_STATUSBYTE_RESERVED_M 0xFFE0U 804 #define PBE_BLE5_RAM_STATUSBYTE_RESERVED_S 5U 805 806 // Field: [4:4] rpaignored 807 // 808 // Ignored due to RPA. 809 #define PBE_BLE5_RAM_STATUSBYTE_RPAIGNORED 0x0010U 810 #define PBE_BLE5_RAM_STATUSBYTE_RPAIGNORED_M 0x0010U 811 #define PBE_BLE5_RAM_STATUSBYTE_RPAIGNORED_S 4U 812 813 // Field: [3:3] ignored 814 // 815 // Ignored due to PID or address. 816 #define PBE_BLE5_RAM_STATUSBYTE_IGNORED 0x0008U 817 #define PBE_BLE5_RAM_STATUSBYTE_IGNORED_M 0x0008U 818 #define PBE_BLE5_RAM_STATUSBYTE_IGNORED_S 3U 819 820 // Field: [2:2] crcerror 821 // 822 // CRC check with PHA failed. 823 #define PBE_BLE5_RAM_STATUSBYTE_CRCERROR 0x0004U 824 #define PBE_BLE5_RAM_STATUSBYTE_CRCERROR_M 0x0004U 825 #define PBE_BLE5_RAM_STATUSBYTE_CRCERROR_S 2U 826 827 // Field: [1:0] phy 828 // 829 // aka Rate Indicator. 830 #define PBE_BLE5_RAM_STATUSBYTE_PHY_W 2U 831 #define PBE_BLE5_RAM_STATUSBYTE_PHY_M 0x0003U 832 #define PBE_BLE5_RAM_STATUSBYTE_PHY_S 0U 833 #define PBE_BLE5_RAM_STATUSBYTE_PHY_1M 0x0000U 834 #define PBE_BLE5_RAM_STATUSBYTE_PHY_2M 0x0001U 835 #define PBE_BLE5_RAM_STATUSBYTE_PHY_CODED_125K 0x0002U 836 #define PBE_BLE5_RAM_STATUSBYTE_PHY_CODED_500K 0x0003U 837 838 //****************************************************************************** 839 // Register: NAKHUB 840 //****************************************************************************** 841 // Field: [5:3] nrnaks 842 // 843 // How many consecutive NAKS has been received 844 #define PBE_BLE5_RAM_NAKHUB_NRNAKS_W 3U 845 #define PBE_BLE5_RAM_NAKHUB_NRNAKS_M 0x0038U 846 #define PBE_BLE5_RAM_NAKHUB_NRNAKS_S 3U 847 848 // Field: [2:0] maxnak 849 // 850 // Maximum number of packets received without a new value of NESN in the same task before the task ends. If both devices find themselves with full RX FIFO or no RX buffer available, they will request the peer to retransmit by transmitting a NAK. This is a sort of livelock loop. If it's 0, do not end the task based on this. 851 #define PBE_BLE5_RAM_NAKHUB_MAXNAK_W 3U 852 #define PBE_BLE5_RAM_NAKHUB_MAXNAK_M 0x0007U 853 #define PBE_BLE5_RAM_NAKHUB_MAXNAK_S 0U 854 855 //****************************************************************************** 856 // Register: WHITEINIT 857 //****************************************************************************** 858 // Field: [15:0] val 859 // 860 // Whitener initialization value 861 #define PBE_BLE5_RAM_WHITEINIT_VAL_W 16U 862 #define PBE_BLE5_RAM_WHITEINIT_VAL_M 0xFFFFU 863 #define PBE_BLE5_RAM_WHITEINIT_VAL_S 0U 864 865 //****************************************************************************** 866 // Register: EXTRABYTES 867 //****************************************************************************** 868 // Field: [15:0] val 869 // 870 // The number of bytes required. 871 #define PBE_BLE5_RAM_EXTRABYTES_VAL_W 16U 872 #define PBE_BLE5_RAM_EXTRABYTES_VAL_M 0xFFFFU 873 #define PBE_BLE5_RAM_EXTRABYTES_VAL_S 0U 874 875 //****************************************************************************** 876 // Register: CRCINITL 877 //****************************************************************************** 878 // Field: [15:0] vallsb 879 // 880 // 881 #define PBE_BLE5_RAM_CRCINITL_VALLSB_W 16U 882 #define PBE_BLE5_RAM_CRCINITL_VALLSB_M 0xFFFFU 883 #define PBE_BLE5_RAM_CRCINITL_VALLSB_S 0U 884 885 //****************************************************************************** 886 // Register: CRCINITH 887 //****************************************************************************** 888 // Field: [15:0] valmsb 889 // 890 // 891 #define PBE_BLE5_RAM_CRCINITH_VALMSB_W 16U 892 #define PBE_BLE5_RAM_CRCINITH_VALMSB_M 0xFFFFU 893 #define PBE_BLE5_RAM_CRCINITH_VALMSB_S 0U 894 895 //****************************************************************************** 896 // Register: SEQSTAT 897 //****************************************************************************** 898 // Field: [7:7] ctlackpend 899 // 900 // The last successfully received packet was an LL control packet which has not yet been ACK'ed 901 #define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND 0x0080U 902 #define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_M 0x0080U 903 #define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_S 7U 904 #define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_NO 0x0000U 905 #define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_YES 0x0080U 906 907 // Field: [6:6] ctlack 908 // 909 // The last received packet was the ACK of an LL control packet 910 #define PBE_BLE5_RAM_SEQSTAT_CTLACK 0x0040U 911 #define PBE_BLE5_RAM_SEQSTAT_CTLACK_M 0x0040U 912 #define PBE_BLE5_RAM_SEQSTAT_CTLACK_S 6U 913 #define PBE_BLE5_RAM_SEQSTAT_CTLACK_NO 0x0000U 914 #define PBE_BLE5_RAM_SEQSTAT_CTLACK_YES 0x0040U 915 916 // Field: [5:5] ctltx 917 // 918 // The last transmitted packet was an LL control packet (LLID = 11) 919 #define PBE_BLE5_RAM_SEQSTAT_CTLTX 0x0020U 920 #define PBE_BLE5_RAM_SEQSTAT_CTLTX_M 0x0020U 921 #define PBE_BLE5_RAM_SEQSTAT_CTLTX_S 5U 922 #define PBE_BLE5_RAM_SEQSTAT_CTLTX_NO 0x0000U 923 #define PBE_BLE5_RAM_SEQSTAT_CTLTX_YES 0x0020U 924 925 // Field: [4:4] empty 926 // 927 // The last transmitted packet was an auto-empty packet. 928 #define PBE_BLE5_RAM_SEQSTAT_EMPTY 0x0010U 929 #define PBE_BLE5_RAM_SEQSTAT_EMPTY_M 0x0010U 930 #define PBE_BLE5_RAM_SEQSTAT_EMPTY_S 4U 931 932 // Field: [3:3] firstpkt 933 // 934 // Has there been any packets transmitted on this connection 935 #define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT 0x0008U 936 #define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_M 0x0008U 937 #define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_S 3U 938 #define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_NOT_FIRST 0x0000U 939 #define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_FIRST 0x0008U 940 941 // Field: [2:2] nexttxsn 942 // 943 // SN in the next message to transmit. 944 #define PBE_BLE5_RAM_SEQSTAT_NEXTTXSN 0x0004U 945 #define PBE_BLE5_RAM_SEQSTAT_NEXTTXSN_M 0x0004U 946 #define PBE_BLE5_RAM_SEQSTAT_NEXTTXSN_S 2U 947 948 // Field: [1:1] lasttxsn 949 // 950 // SN in the last message transmitted. 951 #define PBE_BLE5_RAM_SEQSTAT_LASTTXSN 0x0002U 952 #define PBE_BLE5_RAM_SEQSTAT_LASTTXSN_M 0x0002U 953 #define PBE_BLE5_RAM_SEQSTAT_LASTTXSN_S 1U 954 955 // Field: [0:0] lastrxsn 956 // 957 // SN in the last message received with CRC OK. 958 #define PBE_BLE5_RAM_SEQSTAT_LASTRXSN 0x0001U 959 #define PBE_BLE5_RAM_SEQSTAT_LASTRXSN_M 0x0001U 960 #define PBE_BLE5_RAM_SEQSTAT_LASTRXSN_S 0U 961 962 //****************************************************************************** 963 // Register: BACKOFFCNT 964 //****************************************************************************** 965 // Field: [15:0] val 966 // 967 // MCU writes new value of back-off count for first scanner task after transmission of SCAN_REQ and subsequent reception or attempted reception of SCAN_RSP, or returned value from last scanner task. PBE decrements the back-off count on every correctly received advertising packet that will generate a SCAN_RSP and writes it back at the end of the task. Allowed values: write from MCU: 1–256. Read from MCU: 0–256. 968 #define PBE_BLE5_RAM_BACKOFFCNT_VAL_W 16U 969 #define PBE_BLE5_RAM_BACKOFFCNT_VAL_M 0xFFFFU 970 #define PBE_BLE5_RAM_BACKOFFCNT_VAL_S 0U 971 972 //****************************************************************************** 973 // Register: SCANCFG 974 //****************************************************************************** 975 // Field: [0:0] actpass 976 // 977 // Configure scan type 978 #define PBE_BLE5_RAM_SCANCFG_ACTPASS 0x0001U 979 #define PBE_BLE5_RAM_SCANCFG_ACTPASS_M 0x0001U 980 #define PBE_BLE5_RAM_SCANCFG_ACTPASS_S 0U 981 #define PBE_BLE5_RAM_SCANCFG_ACTPASS_PASS 0x0000U 982 #define PBE_BLE5_RAM_SCANCFG_ACTPASS_ACT 0x0001U 983 984 //****************************************************************************** 985 // Register: AECFG 986 //****************************************************************************** 987 // Field: [5:5] advmode2 988 // 989 // Accept extended advertising packets with ADV_MODE=2 990 #define PBE_BLE5_RAM_AECFG_ADVMODE2 0x0020U 991 #define PBE_BLE5_RAM_AECFG_ADVMODE2_M 0x0020U 992 #define PBE_BLE5_RAM_AECFG_ADVMODE2_S 5U 993 #define PBE_BLE5_RAM_AECFG_ADVMODE2_REJECT 0x0000U 994 #define PBE_BLE5_RAM_AECFG_ADVMODE2_ACCEPT 0x0020U 995 996 // Field: [4:4] advmode1 997 // 998 // Accept extended advertising packets with ADV_MODE=1 999 #define PBE_BLE5_RAM_AECFG_ADVMODE1 0x0010U 1000 #define PBE_BLE5_RAM_AECFG_ADVMODE1_M 0x0010U 1001 #define PBE_BLE5_RAM_AECFG_ADVMODE1_S 4U 1002 #define PBE_BLE5_RAM_AECFG_ADVMODE1_REJECT 0x0000U 1003 #define PBE_BLE5_RAM_AECFG_ADVMODE1_ACCEPT 0x0010U 1004 1005 // Field: [3:3] advmode0 1006 // 1007 // Accept extended advertising packets with ADV_MODE=0 1008 #define PBE_BLE5_RAM_AECFG_ADVMODE0 0x0008U 1009 #define PBE_BLE5_RAM_AECFG_ADVMODE0_M 0x0008U 1010 #define PBE_BLE5_RAM_AECFG_ADVMODE0_S 3U 1011 #define PBE_BLE5_RAM_AECFG_ADVMODE0_REJECT 0x0000U 1012 #define PBE_BLE5_RAM_AECFG_ADVMODE0_ACCEPT 0x0008U 1013 1014 // Field: [2:2] chnl 1015 // 1016 // Current channel type 1017 #define PBE_BLE5_RAM_AECFG_CHNL 0x0004U 1018 #define PBE_BLE5_RAM_AECFG_CHNL_M 0x0004U 1019 #define PBE_BLE5_RAM_AECFG_CHNL_S 2U 1020 #define PBE_BLE5_RAM_AECFG_CHNL_PRIMARY 0x0000U 1021 #define PBE_BLE5_RAM_AECFG_CHNL_SECONDARY 0x0004U 1022 1023 // Field: [1:1] extended 1024 // 1025 // Extended advertisement enabled 1026 #define PBE_BLE5_RAM_AECFG_EXTENDED 0x0002U 1027 #define PBE_BLE5_RAM_AECFG_EXTENDED_M 0x0002U 1028 #define PBE_BLE5_RAM_AECFG_EXTENDED_S 1U 1029 #define PBE_BLE5_RAM_AECFG_EXTENDED_DIS 0x0000U 1030 #define PBE_BLE5_RAM_AECFG_EXTENDED_EN 0x0002U 1031 1032 // Field: [0:0] legacy 1033 // 1034 // Legacy advertisement enabled 1035 #define PBE_BLE5_RAM_AECFG_LEGACY 0x0001U 1036 #define PBE_BLE5_RAM_AECFG_LEGACY_M 0x0001U 1037 #define PBE_BLE5_RAM_AECFG_LEGACY_S 0U 1038 #define PBE_BLE5_RAM_AECFG_LEGACY_DIS 0x0000U 1039 #define PBE_BLE5_RAM_AECFG_LEGACY_EN 0x0001U 1040 1041 //****************************************************************************** 1042 // Register: AETMP 1043 //****************************************************************************** 1044 // Field: [9:9] scannable 1045 // 1046 // 1047 #define PBE_BLE5_RAM_AETMP_SCANNABLE 0x0200U 1048 #define PBE_BLE5_RAM_AETMP_SCANNABLE_M 0x0200U 1049 #define PBE_BLE5_RAM_AETMP_SCANNABLE_S 9U 1050 1051 // Field: [8:8] connectable 1052 // 1053 // 1054 #define PBE_BLE5_RAM_AETMP_CONNECTABLE 0x0100U 1055 #define PBE_BLE5_RAM_AETMP_CONNECTABLE_M 0x0100U 1056 #define PBE_BLE5_RAM_AETMP_CONNECTABLE_S 8U 1057 1058 // Field: [7:7] res 1059 // 1060 // 1061 #define PBE_BLE5_RAM_AETMP_RES 0x0080U 1062 #define PBE_BLE5_RAM_AETMP_RES_M 0x0080U 1063 #define PBE_BLE5_RAM_AETMP_RES_S 7U 1064 1065 // Field: [6:6] txpower 1066 // 1067 // 1068 #define PBE_BLE5_RAM_AETMP_TXPOWER 0x0040U 1069 #define PBE_BLE5_RAM_AETMP_TXPOWER_M 0x0040U 1070 #define PBE_BLE5_RAM_AETMP_TXPOWER_S 6U 1071 1072 // Field: [5:5] syncinfo 1073 // 1074 // 1075 #define PBE_BLE5_RAM_AETMP_SYNCINFO 0x0020U 1076 #define PBE_BLE5_RAM_AETMP_SYNCINFO_M 0x0020U 1077 #define PBE_BLE5_RAM_AETMP_SYNCINFO_S 5U 1078 1079 // Field: [4:4] auxptr 1080 // 1081 // 1082 #define PBE_BLE5_RAM_AETMP_AUXPTR 0x0010U 1083 #define PBE_BLE5_RAM_AETMP_AUXPTR_M 0x0010U 1084 #define PBE_BLE5_RAM_AETMP_AUXPTR_S 4U 1085 1086 // Field: [3:3] adi 1087 // 1088 // 1089 #define PBE_BLE5_RAM_AETMP_ADI 0x0008U 1090 #define PBE_BLE5_RAM_AETMP_ADI_M 0x0008U 1091 #define PBE_BLE5_RAM_AETMP_ADI_S 3U 1092 1093 // Field: [2:2] cteinfo 1094 // 1095 // 1096 #define PBE_BLE5_RAM_AETMP_CTEINFO 0x0004U 1097 #define PBE_BLE5_RAM_AETMP_CTEINFO_M 0x0004U 1098 #define PBE_BLE5_RAM_AETMP_CTEINFO_S 2U 1099 1100 // Field: [1:1] targeta 1101 // 1102 // 1103 #define PBE_BLE5_RAM_AETMP_TARGETA 0x0002U 1104 #define PBE_BLE5_RAM_AETMP_TARGETA_M 0x0002U 1105 #define PBE_BLE5_RAM_AETMP_TARGETA_S 1U 1106 1107 // Field: [0:0] adva 1108 // 1109 // 1110 #define PBE_BLE5_RAM_AETMP_ADVA 0x0001U 1111 #define PBE_BLE5_RAM_AETMP_ADVA_M 0x0001U 1112 #define PBE_BLE5_RAM_AETMP_ADVA_S 0U 1113 1114 //****************************************************************************** 1115 // Register: EXTLENTMP 1116 //****************************************************************************** 1117 // Field: [15:0] val 1118 // 1119 // 1120 #define PBE_BLE5_RAM_EXTLENTMP_VAL_W 16U 1121 #define PBE_BLE5_RAM_EXTLENTMP_VAL_M 0xFFFFU 1122 #define PBE_BLE5_RAM_EXTLENTMP_VAL_S 0U 1123 1124 //****************************************************************************** 1125 // Register: WINOFFSET 1126 //****************************************************************************** 1127 // Field: [15:0] val 1128 // 1129 // The RCL intializes this to the range 4-WINMOD at the start of the intiator operation. 1130 #define PBE_BLE5_RAM_WINOFFSET_VAL_W 16U 1131 #define PBE_BLE5_RAM_WINOFFSET_VAL_M 0xFFFFU 1132 #define PBE_BLE5_RAM_WINOFFSET_VAL_S 0U 1133 1134 //****************************************************************************** 1135 // Register: WINMOD 1136 //****************************************************************************** 1137 // Field: [15:0] val 1138 // 1139 // The amount of 312.5 us periods in the connection interval (four times the number given by the BLE LL). A value of 0 means that dynamic window offset is disabled. 1140 #define PBE_BLE5_RAM_WINMOD_VAL_W 16U 1141 #define PBE_BLE5_RAM_WINMOD_VAL_M 0xFFFFU 1142 #define PBE_BLE5_RAM_WINMOD_VAL_S 0U 1143 1144 //****************************************************************************** 1145 // Register: MAXLEN 1146 //****************************************************************************** 1147 // Field: [15:0] val 1148 // 1149 // 1150 #define PBE_BLE5_RAM_MAXLEN_VAL_W 16U 1151 #define PBE_BLE5_RAM_MAXLEN_VAL_M 0xFFFFU 1152 #define PBE_BLE5_RAM_MAXLEN_VAL_S 0U 1153 1154 //****************************************************************************** 1155 // Register: FILTPOLICY 1156 //****************************************************************************** 1157 // Field: [4:4] intor 1158 // 1159 // Initiator's filter policy 1160 #define PBE_BLE5_RAM_FILTPOLICY_INTOR 0x0010U 1161 #define PBE_BLE5_RAM_FILTPOLICY_INTOR_M 0x0010U 1162 #define PBE_BLE5_RAM_FILTPOLICY_INTOR_S 4U 1163 #define PBE_BLE5_RAM_FILTPOLICY_INTOR_PEERADR 0x0000U 1164 #define PBE_BLE5_RAM_FILTPOLICY_INTOR_FL2 0x0010U 1165 1166 // Field: [3:3] extscanner 1167 // 1168 // Extended scanner filter policy. 1169 #define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER 0x0008U 1170 #define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_M 0x0008U 1171 #define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_S 3U 1172 #define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_NORPA 0x0000U 1173 #define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_ANYRPA 0x0008U 1174 1175 // Field: [2:2] scanner 1176 // 1177 // Scanner's filter policy 1178 #define PBE_BLE5_RAM_FILTPOLICY_SCANNER 0x0004U 1179 #define PBE_BLE5_RAM_FILTPOLICY_SCANNER_M 0x0004U 1180 #define PBE_BLE5_RAM_FILTPOLICY_SCANNER_S 2U 1181 #define PBE_BLE5_RAM_FILTPOLICY_SCANNER_REJFL1 0x0000U 1182 #define PBE_BLE5_RAM_FILTPOLICY_SCANNER_FL1 0x0004U 1183 1184 // Field: [1:0] adv 1185 // 1186 // Advertiser's filter policy. Note: The Advertiser's filter policy is ignored during all directed advertiser events, all combinations. 1187 #define PBE_BLE5_RAM_FILTPOLICY_ADV_W 2U 1188 #define PBE_BLE5_RAM_FILTPOLICY_ADV_M 0x0003U 1189 #define PBE_BLE5_RAM_FILTPOLICY_ADV_S 0U 1190 #define PBE_BLE5_RAM_FILTPOLICY_ADV_REJFL1_REJFL2 0x0000U 1191 #define PBE_BLE5_RAM_FILTPOLICY_ADV_FL1_REJFL2 0x0001U 1192 #define PBE_BLE5_RAM_FILTPOLICY_ADV_REJFL1_FL2 0x0002U 1193 #define PBE_BLE5_RAM_FILTPOLICY_ADV_FL1_FL2 0x0003U 1194 1195 //****************************************************************************** 1196 // Register: OWNADRTYPE 1197 //****************************************************************************** 1198 // Field: [0:0] type 1199 // 1200 // Address in OWNADR 1201 #define PBE_BLE5_RAM_OWNADRTYPE_TYPE 0x0001U 1202 #define PBE_BLE5_RAM_OWNADRTYPE_TYPE_M 0x0001U 1203 #define PBE_BLE5_RAM_OWNADRTYPE_TYPE_S 0U 1204 #define PBE_BLE5_RAM_OWNADRTYPE_TYPE_PUBLIC 0x0000U 1205 #define PBE_BLE5_RAM_OWNADRTYPE_TYPE_RANDOM 0x0001U 1206 1207 //****************************************************************************** 1208 // Register: PEERADRTYPE 1209 //****************************************************************************** 1210 // Field: [0:0] type 1211 // 1212 // Address in PEERADR 1213 #define PBE_BLE5_RAM_PEERADRTYPE_TYPE 0x0001U 1214 #define PBE_BLE5_RAM_PEERADRTYPE_TYPE_M 0x0001U 1215 #define PBE_BLE5_RAM_PEERADRTYPE_TYPE_S 0U 1216 #define PBE_BLE5_RAM_PEERADRTYPE_TYPE_PUBLIC 0x0000U 1217 #define PBE_BLE5_RAM_PEERADRTYPE_TYPE_RANDOM 0x0001U 1218 1219 //****************************************************************************** 1220 // Register: OWNADRL 1221 //****************************************************************************** 1222 // Field: [15:0] vallsb 1223 // 1224 // 1225 #define PBE_BLE5_RAM_OWNADRL_VALLSB_W 16U 1226 #define PBE_BLE5_RAM_OWNADRL_VALLSB_M 0xFFFFU 1227 #define PBE_BLE5_RAM_OWNADRL_VALLSB_S 0U 1228 1229 //****************************************************************************** 1230 // Register: OWNADRM 1231 //****************************************************************************** 1232 // Field: [15:0] vallsb 1233 // 1234 // 1235 #define PBE_BLE5_RAM_OWNADRM_VALLSB_W 16U 1236 #define PBE_BLE5_RAM_OWNADRM_VALLSB_M 0xFFFFU 1237 #define PBE_BLE5_RAM_OWNADRM_VALLSB_S 0U 1238 1239 //****************************************************************************** 1240 // Register: OWNADRH 1241 //****************************************************************************** 1242 // Field: [15:0] valmsb 1243 // 1244 // 1245 #define PBE_BLE5_RAM_OWNADRH_VALMSB_W 16U 1246 #define PBE_BLE5_RAM_OWNADRH_VALMSB_M 0xFFFFU 1247 #define PBE_BLE5_RAM_OWNADRH_VALMSB_S 0U 1248 1249 //****************************************************************************** 1250 // Register: TMPADRL 1251 //****************************************************************************** 1252 // Field: [15:0] val 1253 // 1254 // bits 15:0 of temporary address 1255 #define PBE_BLE5_RAM_TMPADRL_VAL_W 16U 1256 #define PBE_BLE5_RAM_TMPADRL_VAL_M 0xFFFFU 1257 #define PBE_BLE5_RAM_TMPADRL_VAL_S 0U 1258 1259 //****************************************************************************** 1260 // Register: TMPADRM 1261 //****************************************************************************** 1262 // Field: [15:0] val 1263 // 1264 // bits 31:16 of temporary address 1265 #define PBE_BLE5_RAM_TMPADRM_VAL_W 16U 1266 #define PBE_BLE5_RAM_TMPADRM_VAL_M 0xFFFFU 1267 #define PBE_BLE5_RAM_TMPADRM_VAL_S 0U 1268 1269 //****************************************************************************** 1270 // Register: TMPADRH 1271 //****************************************************************************** 1272 // Field: [15:0] val 1273 // 1274 // bits 47:32 of temporary address 1275 #define PBE_BLE5_RAM_TMPADRH_VAL_W 16U 1276 #define PBE_BLE5_RAM_TMPADRH_VAL_M 0xFFFFU 1277 #define PBE_BLE5_RAM_TMPADRH_VAL_S 0U 1278 1279 //****************************************************************************** 1280 // Register: PEERADRL 1281 //****************************************************************************** 1282 // Field: [15:0] vallsb 1283 // 1284 // 1285 #define PBE_BLE5_RAM_PEERADRL_VALLSB_W 16U 1286 #define PBE_BLE5_RAM_PEERADRL_VALLSB_M 0xFFFFU 1287 #define PBE_BLE5_RAM_PEERADRL_VALLSB_S 0U 1288 1289 //****************************************************************************** 1290 // Register: PEERADRM 1291 //****************************************************************************** 1292 // Field: [15:0] vallsb 1293 // 1294 // 1295 #define PBE_BLE5_RAM_PEERADRM_VALLSB_W 16U 1296 #define PBE_BLE5_RAM_PEERADRM_VALLSB_M 0xFFFFU 1297 #define PBE_BLE5_RAM_PEERADRM_VALLSB_S 0U 1298 1299 //****************************************************************************** 1300 // Register: PEERADRH 1301 //****************************************************************************** 1302 // Field: [15:0] valmsb 1303 // 1304 // 1305 #define PBE_BLE5_RAM_PEERADRH_VALMSB_W 16U 1306 #define PBE_BLE5_RAM_PEERADRH_VALMSB_M 0xFFFFU 1307 #define PBE_BLE5_RAM_PEERADRH_VALMSB_S 0U 1308 1309 //****************************************************************************** 1310 // Register: NTXDONE 1311 //****************************************************************************** 1312 // Field: [15:0] val 1313 // 1314 // Number of acknowledgements received on packets from the Tx FIFO 1315 #define PBE_BLE5_RAM_NTXDONE_VAL_W 16U 1316 #define PBE_BLE5_RAM_NTXDONE_VAL_M 0xFFFFU 1317 #define PBE_BLE5_RAM_NTXDONE_VAL_S 0U 1318 1319 //****************************************************************************** 1320 // Register: NTXACK 1321 //****************************************************************************** 1322 // Field: [15:0] val 1323 // 1324 // Total number of acknowledgement received on transmitted packets 1325 #define PBE_BLE5_RAM_NTXACK_VAL_W 16U 1326 #define PBE_BLE5_RAM_NTXACK_VAL_M 0xFFFFU 1327 #define PBE_BLE5_RAM_NTXACK_VAL_S 0U 1328 1329 //****************************************************************************** 1330 // Register: NTXCTLACK 1331 //****************************************************************************** 1332 // Field: [15:0] val 1333 // 1334 // Number of acknowledgements received on transmitted LL control packets 1335 #define PBE_BLE5_RAM_NTXCTLACK_VAL_W 16U 1336 #define PBE_BLE5_RAM_NTXCTLACK_VAL_M 0xFFFFU 1337 #define PBE_BLE5_RAM_NTXCTLACK_VAL_S 0U 1338 1339 //****************************************************************************** 1340 // Register: NTXCTL 1341 //****************************************************************************** 1342 // Field: [15:0] val 1343 // 1344 // Number of unique LL control packets transmitted 1345 #define PBE_BLE5_RAM_NTXCTL_VAL_W 16U 1346 #define PBE_BLE5_RAM_NTXCTL_VAL_M 0xFFFFU 1347 #define PBE_BLE5_RAM_NTXCTL_VAL_S 0U 1348 1349 //****************************************************************************** 1350 // Register: NTXRETRANS 1351 //****************************************************************************** 1352 // Field: [15:0] val 1353 // 1354 // Number of packets transmitted being the same as the previously transmitted packet. 1355 #define PBE_BLE5_RAM_NTXRETRANS_VAL_W 16U 1356 #define PBE_BLE5_RAM_NTXRETRANS_VAL_M 0xFFFFU 1357 #define PBE_BLE5_RAM_NTXRETRANS_VAL_S 0U 1358 1359 //****************************************************************************** 1360 // Register: NRXNOK 1361 //****************************************************************************** 1362 // Field: [15:0] val 1363 // 1364 // Number of packets received with CRC error 1365 #define PBE_BLE5_RAM_NRXNOK_VAL_W 16U 1366 #define PBE_BLE5_RAM_NRXNOK_VAL_M 0xFFFFU 1367 #define PBE_BLE5_RAM_NRXNOK_VAL_S 0U 1368 1369 //****************************************************************************** 1370 // Register: NRXIGNORED 1371 //****************************************************************************** 1372 // Field: [15:0] val 1373 // 1374 // Number of packets received with CRC OK, but to be ignored by the MCU 1375 #define PBE_BLE5_RAM_NRXIGNORED_VAL_W 16U 1376 #define PBE_BLE5_RAM_NRXIGNORED_VAL_M 0xFFFFU 1377 #define PBE_BLE5_RAM_NRXIGNORED_VAL_S 0U 1378 1379 //****************************************************************************** 1380 // Register: NRXEMPTY 1381 //****************************************************************************** 1382 // Field: [15:0] val 1383 // 1384 // Number of packets received with CRC OK and length zero 1385 #define PBE_BLE5_RAM_NRXEMPTY_VAL_W 16U 1386 #define PBE_BLE5_RAM_NRXEMPTY_VAL_M 0xFFFFU 1387 #define PBE_BLE5_RAM_NRXEMPTY_VAL_S 0U 1388 1389 //****************************************************************************** 1390 // Register: NRXFIFOFULL 1391 //****************************************************************************** 1392 // Field: [15:0] val 1393 // 1394 // Number of received packets discarded because the Rx FIFO was full 1395 #define PBE_BLE5_RAM_NRXFIFOFULL_VAL_W 16U 1396 #define PBE_BLE5_RAM_NRXFIFOFULL_VAL_M 0xFFFFU 1397 #define PBE_BLE5_RAM_NRXFIFOFULL_VAL_S 0U 1398 1399 //****************************************************************************** 1400 // Register: NRXOK 1401 //****************************************************************************** 1402 // Field: [15:0] val 1403 // 1404 // Number of non-empty packets received with CRC OK and not to be ignored by the MCU 1405 #define PBE_BLE5_RAM_NRXOK_VAL_W 16U 1406 #define PBE_BLE5_RAM_NRXOK_VAL_M 0xFFFFU 1407 #define PBE_BLE5_RAM_NRXOK_VAL_S 0U 1408 1409 //****************************************************************************** 1410 // Register: NTX 1411 //****************************************************************************** 1412 // Field: [15:0] val 1413 // 1414 // Total number of packets transmitted in the task 1415 #define PBE_BLE5_RAM_NTX_VAL_W 16U 1416 #define PBE_BLE5_RAM_NTX_VAL_M 0xFFFFU 1417 #define PBE_BLE5_RAM_NTX_VAL_S 0U 1418 1419 //****************************************************************************** 1420 // Register: NRXCTL 1421 //****************************************************************************** 1422 // Field: [15:0] val 1423 // 1424 // Number of LL control packets correctly received (also included in NRXOK) 1425 #define PBE_BLE5_RAM_NRXCTL_VAL_W 16U 1426 #define PBE_BLE5_RAM_NRXCTL_VAL_M 0xFFFFU 1427 #define PBE_BLE5_RAM_NRXCTL_VAL_S 0U 1428 1429 //****************************************************************************** 1430 // Register: NRXCTLACK 1431 //****************************************************************************** 1432 // Field: [15:0] val 1433 // 1434 // Total number of acknowledgement transmitted on received LL control packets. 1435 #define PBE_BLE5_RAM_NRXCTLACK_VAL_W 16U 1436 #define PBE_BLE5_RAM_NRXCTLACK_VAL_M 0xFFFFU 1437 #define PBE_BLE5_RAM_NRXCTLACK_VAL_S 0U 1438 1439 //****************************************************************************** 1440 // Register: LASTRSSI 1441 //****************************************************************************** 1442 // Field: [15:0] val 1443 // 1444 // RSSI of last packet received in task 1445 #define PBE_BLE5_RAM_LASTRSSI_VAL_W 16U 1446 #define PBE_BLE5_RAM_LASTRSSI_VAL_M 0xFFFFU 1447 #define PBE_BLE5_RAM_LASTRSSI_VAL_S 0U 1448 1449 //****************************************************************************** 1450 // Register: FIRSTRXTIMEOUT 1451 //****************************************************************************** 1452 // Field: [15:0] val 1453 // 1454 // For peripheral tasks, the timeout in µs from SYSTCMP0 event to giving up listening for the first packet. Must be at least 128 µs if non-zero. Can be up to 32000 µs based on supervision timeout, window widening. 1455 #define PBE_BLE5_RAM_FIRSTRXTIMEOUT_VAL_W 16U 1456 #define PBE_BLE5_RAM_FIRSTRXTIMEOUT_VAL_M 0xFFFFU 1457 #define PBE_BLE5_RAM_FIRSTRXTIMEOUT_VAL_S 0U 1458 1459 //****************************************************************************** 1460 // Register: LASTTIMESTAMPL 1461 //****************************************************************************** 1462 // Field: [15:0] val 1463 // 1464 // Lower part of timestamp. 1465 #define PBE_BLE5_RAM_LASTTIMESTAMPL_VAL_W 16U 1466 #define PBE_BLE5_RAM_LASTTIMESTAMPL_VAL_M 0xFFFFU 1467 #define PBE_BLE5_RAM_LASTTIMESTAMPL_VAL_S 0U 1468 1469 //****************************************************************************** 1470 // Register: LASTTIMESTAMPH 1471 //****************************************************************************** 1472 // Field: [15:0] val 1473 // 1474 // Upper part of timestamp. 1475 #define PBE_BLE5_RAM_LASTTIMESTAMPH_VAL_W 16U 1476 #define PBE_BLE5_RAM_LASTTIMESTAMPH_VAL_M 0xFFFFU 1477 #define PBE_BLE5_RAM_LASTTIMESTAMPH_VAL_S 0U 1478 1479 //****************************************************************************** 1480 // Register: MDCFG 1481 //****************************************************************************** 1482 // Field: [1:0] force 1483 // 1484 // 1485 #define PBE_BLE5_RAM_MDCFG_FORCE_W 2U 1486 #define PBE_BLE5_RAM_MDCFG_FORCE_M 0x0003U 1487 #define PBE_BLE5_RAM_MDCFG_FORCE_S 0U 1488 #define PBE_BLE5_RAM_MDCFG_FORCE_MD0 0x0001U 1489 #define PBE_BLE5_RAM_MDCFG_FORCE_MD1 0x0002U 1490 1491 //****************************************************************************** 1492 // Register: ADVCFG 1493 //****************************************************************************** 1494 // Field: [3:3] extended 1495 // 1496 // 1497 #define PBE_BLE5_RAM_ADVCFG_EXTENDED 0x0008U 1498 #define PBE_BLE5_RAM_ADVCFG_EXTENDED_M 0x0008U 1499 #define PBE_BLE5_RAM_ADVCFG_EXTENDED_S 3U 1500 1501 // Field: [2:2] directed 1502 // 1503 // 1504 #define PBE_BLE5_RAM_ADVCFG_DIRECTED 0x0004U 1505 #define PBE_BLE5_RAM_ADVCFG_DIRECTED_M 0x0004U 1506 #define PBE_BLE5_RAM_ADVCFG_DIRECTED_S 2U 1507 1508 // Field: [1:1] scannable 1509 // 1510 // 1511 #define PBE_BLE5_RAM_ADVCFG_SCANNABLE 0x0002U 1512 #define PBE_BLE5_RAM_ADVCFG_SCANNABLE_M 0x0002U 1513 #define PBE_BLE5_RAM_ADVCFG_SCANNABLE_S 1U 1514 1515 // Field: [0:0] connectable 1516 // 1517 // 1518 #define PBE_BLE5_RAM_ADVCFG_CONNECTABLE 0x0001U 1519 #define PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M 0x0001U 1520 #define PBE_BLE5_RAM_ADVCFG_CONNECTABLE_S 0U 1521 1522 //****************************************************************************** 1523 // Register: TMPRSSI 1524 //****************************************************************************** 1525 // Field: [15:0] val 1526 // 1527 // RSSI 1528 #define PBE_BLE5_RAM_TMPRSSI_VAL_W 16U 1529 #define PBE_BLE5_RAM_TMPRSSI_VAL_M 0xFFFFU 1530 #define PBE_BLE5_RAM_TMPRSSI_VAL_S 0U 1531 1532 //****************************************************************************** 1533 // Register: FIRSTTIMESTAMPL 1534 //****************************************************************************** 1535 // Field: [15:0] val 1536 // 1537 // Peripheral only. 1538 #define PBE_BLE5_RAM_FIRSTTIMESTAMPL_VAL_W 16U 1539 #define PBE_BLE5_RAM_FIRSTTIMESTAMPL_VAL_M 0xFFFFU 1540 #define PBE_BLE5_RAM_FIRSTTIMESTAMPL_VAL_S 0U 1541 1542 //****************************************************************************** 1543 // Register: FIRSTTIMESTAMPH 1544 //****************************************************************************** 1545 // Field: [15:0] val 1546 // 1547 // Peripheral only. 1548 #define PBE_BLE5_RAM_FIRSTTIMESTAMPH_VAL_W 16U 1549 #define PBE_BLE5_RAM_FIRSTTIMESTAMPH_VAL_M 0xFFFFU 1550 #define PBE_BLE5_RAM_FIRSTTIMESTAMPH_VAL_S 0U 1551 1552 //****************************************************************************** 1553 // Register: FL1RESULT 1554 //****************************************************************************** 1555 // Field: [3:0] index 1556 // 1557 // Which entry in the address table matched 1558 #define PBE_BLE5_RAM_FL1RESULT_INDEX_W 4U 1559 #define PBE_BLE5_RAM_FL1RESULT_INDEX_M 0x000FU 1560 #define PBE_BLE5_RAM_FL1RESULT_INDEX_S 0U 1561 1562 //****************************************************************************** 1563 // Register: FL1MASK 1564 //****************************************************************************** 1565 // Field: [15:15] match 1566 // 1567 // 1568 #define PBE_BLE5_RAM_FL1MASK_MATCH 0x8000U 1569 #define PBE_BLE5_RAM_FL1MASK_MATCH_M 0x8000U 1570 #define PBE_BLE5_RAM_FL1MASK_MATCH_S 15U 1571 #define PBE_BLE5_RAM_FL1MASK_MATCH_DIS 0x0000U 1572 #define PBE_BLE5_RAM_FL1MASK_MATCH_EN 0x8000U 1573 1574 // Field: [14:4] rfuign 1575 // 1576 // These bits works the same was as PRIVIGN and FALIGN. 1577 #define PBE_BLE5_RAM_FL1MASK_RFUIGN_W 11U 1578 #define PBE_BLE5_RAM_FL1MASK_RFUIGN_M 0x7FF0U 1579 #define PBE_BLE5_RAM_FL1MASK_RFUIGN_S 4U 1580 1581 // Field: [3:3] privign 1582 // 1583 // 1584 #define PBE_BLE5_RAM_FL1MASK_PRIVIGN 0x0008U 1585 #define PBE_BLE5_RAM_FL1MASK_PRIVIGN_M 0x0008U 1586 #define PBE_BLE5_RAM_FL1MASK_PRIVIGN_S 3U 1587 #define PBE_BLE5_RAM_FL1MASK_PRIVIGN_NIGN 0x0000U 1588 #define PBE_BLE5_RAM_FL1MASK_PRIVIGN_IGN 0x0008U 1589 1590 // Field: [2:2] duplicateign 1591 // 1592 // 1593 #define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN 0x0004U 1594 #define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M 0x0004U 1595 #define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_S 2U 1596 #define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_NIGN 0x0000U 1597 #define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_IGN 0x0004U 1598 1599 // Field: [1:1] type 1600 // 1601 // Address type 1602 #define PBE_BLE5_RAM_FL1MASK_TYPE 0x0002U 1603 #define PBE_BLE5_RAM_FL1MASK_TYPE_M 0x0002U 1604 #define PBE_BLE5_RAM_FL1MASK_TYPE_S 1U 1605 #define PBE_BLE5_RAM_FL1MASK_TYPE_DIS 0x0000U 1606 #define PBE_BLE5_RAM_FL1MASK_TYPE_EN 0x0002U 1607 1608 // Field: [0:0] en 1609 // 1610 // Enable 1611 #define PBE_BLE5_RAM_FL1MASK_EN 0x0001U 1612 #define PBE_BLE5_RAM_FL1MASK_EN_M 0x0001U 1613 #define PBE_BLE5_RAM_FL1MASK_EN_S 0U 1614 #define PBE_BLE5_RAM_FL1MASK_EN_DIS 0x0000U 1615 #define PBE_BLE5_RAM_FL1MASK_EN_EN 0x0001U 1616 1617 //****************************************************************************** 1618 // Register: FL2RESULT 1619 //****************************************************************************** 1620 // Field: [3:0] index 1621 // 1622 // Which entry in the address table matched 1623 #define PBE_BLE5_RAM_FL2RESULT_INDEX_W 4U 1624 #define PBE_BLE5_RAM_FL2RESULT_INDEX_M 0x000FU 1625 #define PBE_BLE5_RAM_FL2RESULT_INDEX_S 0U 1626 1627 //****************************************************************************** 1628 // Register: FL2MASK 1629 //****************************************************************************** 1630 // Field: [15:15] match 1631 // 1632 // 1633 #define PBE_BLE5_RAM_FL2MASK_MATCH 0x8000U 1634 #define PBE_BLE5_RAM_FL2MASK_MATCH_M 0x8000U 1635 #define PBE_BLE5_RAM_FL2MASK_MATCH_S 15U 1636 #define PBE_BLE5_RAM_FL2MASK_MATCH_DIS 0x0000U 1637 #define PBE_BLE5_RAM_FL2MASK_MATCH_EN 0x8000U 1638 1639 // Field: [14:4] rfuign 1640 // 1641 // These bits works the same was as PRIVIGN and FALIGN. 1642 #define PBE_BLE5_RAM_FL2MASK_RFUIGN_W 11U 1643 #define PBE_BLE5_RAM_FL2MASK_RFUIGN_M 0x7FF0U 1644 #define PBE_BLE5_RAM_FL2MASK_RFUIGN_S 4U 1645 1646 // Field: [3:3] privign 1647 // 1648 // 1649 #define PBE_BLE5_RAM_FL2MASK_PRIVIGN 0x0008U 1650 #define PBE_BLE5_RAM_FL2MASK_PRIVIGN_M 0x0008U 1651 #define PBE_BLE5_RAM_FL2MASK_PRIVIGN_S 3U 1652 #define PBE_BLE5_RAM_FL2MASK_PRIVIGN_NIGN 0x0000U 1653 #define PBE_BLE5_RAM_FL2MASK_PRIVIGN_IGN 0x0008U 1654 1655 // Field: [2:2] duplicateign 1656 // 1657 // 1658 #define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN 0x0004U 1659 #define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_M 0x0004U 1660 #define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_S 2U 1661 #define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_NIGN 0x0000U 1662 #define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_IGN 0x0004U 1663 1664 // Field: [1:1] type 1665 // 1666 // Address type 1667 #define PBE_BLE5_RAM_FL2MASK_TYPE 0x0002U 1668 #define PBE_BLE5_RAM_FL2MASK_TYPE_M 0x0002U 1669 #define PBE_BLE5_RAM_FL2MASK_TYPE_S 1U 1670 #define PBE_BLE5_RAM_FL2MASK_TYPE_DIS 0x0000U 1671 #define PBE_BLE5_RAM_FL2MASK_TYPE_EN 0x0002U 1672 1673 // Field: [0:0] en 1674 // 1675 // Enable 1676 #define PBE_BLE5_RAM_FL2MASK_EN 0x0001U 1677 #define PBE_BLE5_RAM_FL2MASK_EN_M 0x0001U 1678 #define PBE_BLE5_RAM_FL2MASK_EN_S 0U 1679 #define PBE_BLE5_RAM_FL2MASK_EN_DIS 0x0000U 1680 #define PBE_BLE5_RAM_FL2MASK_EN_EN 0x0001U 1681 1682 //****************************************************************************** 1683 // Register: FLSTAT 1684 //****************************************************************************** 1685 // Field: [1:1] fl2running 1686 // 1687 // Status; is FL2 running address filtering 1688 #define PBE_BLE5_RAM_FLSTAT_FL2RUNNING 0x0002U 1689 #define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_M 0x0002U 1690 #define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_S 1U 1691 #define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_IDLE 0x0000U 1692 #define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_RUNNING 0x0002U 1693 1694 // Field: [0:0] fl1running 1695 // 1696 // Status; is FL1 running address filtering 1697 #define PBE_BLE5_RAM_FLSTAT_FL1RUNNING 0x0001U 1698 #define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_M 0x0001U 1699 #define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_S 0U 1700 #define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_IDLE 0x0000U 1701 #define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_RUNNING 0x0001U 1702 1703 //****************************************************************************** 1704 // Register: TMPATYPE 1705 //****************************************************************************** 1706 // Field: [0:0] val 1707 // 1708 // temporary address type storage 1709 #define PBE_BLE5_RAM_TMPATYPE_VAL 0x0001U 1710 #define PBE_BLE5_RAM_TMPATYPE_VAL_M 0x0001U 1711 #define PBE_BLE5_RAM_TMPATYPE_VAL_S 0U 1712 1713 //****************************************************************************** 1714 // Register: PATTERN 1715 //****************************************************************************** 1716 // Field: [15:0] val 1717 // 1718 // Data to send if OPCFG.TXPATTERN is 1 1719 #define PBE_BLE5_RAM_PATTERN_VAL_W 16U 1720 #define PBE_BLE5_RAM_PATTERN_VAL_M 0xFFFFU 1721 #define PBE_BLE5_RAM_PATTERN_VAL_S 0U 1722 1723 //****************************************************************************** 1724 // Register: RFINTERVAL 1725 //****************************************************************************** 1726 // Field: [15:0] val 1727 // 1728 // RF interval, measured from start-to-start of TX_RAW. The actual time depends on configuration of timer1. 1729 #define PBE_BLE5_RAM_RFINTERVAL_VAL_W 16U 1730 #define PBE_BLE5_RAM_RFINTERVAL_VAL_M 0xFFFFU 1731 #define PBE_BLE5_RAM_RFINTERVAL_VAL_S 0U 1732 1733 //****************************************************************************** 1734 // Register: NTXTARGET 1735 //****************************************************************************** 1736 // Field: [15:0] val 1737 // 1738 // Used in TX_RAW; Total number of packets to transfer. 1739 #define PBE_BLE5_RAM_NTXTARGET_VAL_W 16U 1740 #define PBE_BLE5_RAM_NTXTARGET_VAL_M 0xFFFFU 1741 #define PBE_BLE5_RAM_NTXTARGET_VAL_S 0U 1742 1743 //****************************************************************************** 1744 // Register: OPCFG 1745 //****************************************************************************** 1746 // Field: [4:4] repeat 1747 // 1748 // Rule for what to do after operation completes. 1749 #define PBE_BLE5_RAM_OPCFG_REPEAT 0x0010U 1750 #define PBE_BLE5_RAM_OPCFG_REPEAT_M 0x0010U 1751 #define PBE_BLE5_RAM_OPCFG_REPEAT_S 4U 1752 #define PBE_BLE5_RAM_OPCFG_REPEAT_NO 0x0000U 1753 #define PBE_BLE5_RAM_OPCFG_REPEAT_YES 0x0010U 1754 1755 // Field: [3:3] txpattern 1756 // 1757 // Send fixed pattern 1758 #define PBE_BLE5_RAM_OPCFG_TXPATTERN 0x0008U 1759 #define PBE_BLE5_RAM_OPCFG_TXPATTERN_M 0x0008U 1760 #define PBE_BLE5_RAM_OPCFG_TXPATTERN_S 3U 1761 #define PBE_BLE5_RAM_OPCFG_TXPATTERN_NO 0x0000U 1762 #define PBE_BLE5_RAM_OPCFG_TXPATTERN_YES 0x0008U 1763 1764 // Field: [2:1] txfcmd 1765 // 1766 // Rule for FCMD after TX_DONE 1767 #define PBE_BLE5_RAM_OPCFG_TXFCMD_W 2U 1768 #define PBE_BLE5_RAM_OPCFG_TXFCMD_M 0x0006U 1769 #define PBE_BLE5_RAM_OPCFG_TXFCMD_S 1U 1770 #define PBE_BLE5_RAM_OPCFG_TXFCMD_NONE 0x0000U 1771 #define PBE_BLE5_RAM_OPCFG_TXFCMD_RETRY 0x0002U 1772 #define PBE_BLE5_RAM_OPCFG_TXFCMD_DEALLOC 0x0004U 1773 1774 // Field: [0:0] rfinterval 1775 // 1776 // Requires REPEAT to make sense. 1777 #define PBE_BLE5_RAM_OPCFG_RFINTERVAL 0x0001U 1778 #define PBE_BLE5_RAM_OPCFG_RFINTERVAL_M 0x0001U 1779 #define PBE_BLE5_RAM_OPCFG_RFINTERVAL_S 0U 1780 #define PBE_BLE5_RAM_OPCFG_RFINTERVAL_DIS 0x0000U 1781 #define PBE_BLE5_RAM_OPCFG_RFINTERVAL_EN 0x0001U 1782 1783 //****************************************************************************** 1784 // Register: FL1INFO0 1785 //****************************************************************************** 1786 // Field: [15:15] matchtmp 1787 // 1788 // Temporary variable used in matching, ignore from CM0 1789 #define PBE_BLE5_RAM_FL1INFO0_MATCHTMP 0x8000U 1790 #define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_M 0x8000U 1791 #define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_S 15U 1792 #define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_NOMATCH 0x0000U 1793 #define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_MATCH 0x8000U 1794 1795 // Field: [14:4] reserved 1796 // 1797 // Reserved for future use 1798 #define PBE_BLE5_RAM_FL1INFO0_RESERVED_W 11U 1799 #define PBE_BLE5_RAM_FL1INFO0_RESERVED_M 0x7FF0U 1800 #define PBE_BLE5_RAM_FL1INFO0_RESERVED_S 4U 1801 1802 // Field: [3:3] privign 1803 // 1804 // Ignore control for privacy 1805 #define PBE_BLE5_RAM_FL1INFO0_PRIVIGN 0x0008U 1806 #define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_M 0x0008U 1807 #define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_S 3U 1808 #define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_NIGN 0x0000U 1809 #define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_IGN 0x0008U 1810 1811 // Field: [2:2] falign 1812 // 1813 // Ignore in accept list context 1814 #define PBE_BLE5_RAM_FL1INFO0_FALIGN 0x0004U 1815 #define PBE_BLE5_RAM_FL1INFO0_FALIGN_M 0x0004U 1816 #define PBE_BLE5_RAM_FL1INFO0_FALIGN_S 2U 1817 #define PBE_BLE5_RAM_FL1INFO0_FALIGN_NIGN 0x0000U 1818 #define PBE_BLE5_RAM_FL1INFO0_FALIGN_IGN 0x0004U 1819 1820 // Field: [1:1] type 1821 // 1822 // Address type 1823 #define PBE_BLE5_RAM_FL1INFO0_TYPE 0x0002U 1824 #define PBE_BLE5_RAM_FL1INFO0_TYPE_M 0x0002U 1825 #define PBE_BLE5_RAM_FL1INFO0_TYPE_S 1U 1826 #define PBE_BLE5_RAM_FL1INFO0_TYPE_PUBLIC 0x0000U 1827 #define PBE_BLE5_RAM_FL1INFO0_TYPE_RANDOM 0x0002U 1828 1829 // Field: [0:0] en 1830 // 1831 // Enable 1832 #define PBE_BLE5_RAM_FL1INFO0_EN 0x0001U 1833 #define PBE_BLE5_RAM_FL1INFO0_EN_M 0x0001U 1834 #define PBE_BLE5_RAM_FL1INFO0_EN_S 0U 1835 #define PBE_BLE5_RAM_FL1INFO0_EN_DIS 0x0000U 1836 #define PBE_BLE5_RAM_FL1INFO0_EN_EN 0x0001U 1837 1838 //****************************************************************************** 1839 // Register: FL1ADRL0 1840 //****************************************************************************** 1841 // Field: [15:0] val 1842 // 1843 // bits 15:0 of address 1844 #define PBE_BLE5_RAM_FL1ADRL0_VAL_W 16U 1845 #define PBE_BLE5_RAM_FL1ADRL0_VAL_M 0xFFFFU 1846 #define PBE_BLE5_RAM_FL1ADRL0_VAL_S 0U 1847 1848 //****************************************************************************** 1849 // Register: FL1ADRM0 1850 //****************************************************************************** 1851 // Field: [15:0] val 1852 // 1853 // bits 31:16 of address 1854 #define PBE_BLE5_RAM_FL1ADRM0_VAL_W 16U 1855 #define PBE_BLE5_RAM_FL1ADRM0_VAL_M 0xFFFFU 1856 #define PBE_BLE5_RAM_FL1ADRM0_VAL_S 0U 1857 1858 //****************************************************************************** 1859 // Register: FL1ADRH0 1860 //****************************************************************************** 1861 // Field: [15:0] val 1862 // 1863 // bits 47:32 of address 1864 #define PBE_BLE5_RAM_FL1ADRH0_VAL_W 16U 1865 #define PBE_BLE5_RAM_FL1ADRH0_VAL_M 0xFFFFU 1866 #define PBE_BLE5_RAM_FL1ADRH0_VAL_S 0U 1867 1868 //****************************************************************************** 1869 // Register: FL1INFO1 1870 //****************************************************************************** 1871 // Field: [15:15] matchtmp 1872 // 1873 // Temporary variable used in matching, ignore from CM0 1874 #define PBE_BLE5_RAM_FL1INFO1_MATCHTMP 0x8000U 1875 #define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_M 0x8000U 1876 #define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_S 15U 1877 #define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_NOMATCH 0x0000U 1878 #define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_MATCH 0x8000U 1879 1880 // Field: [14:4] reserved 1881 // 1882 // Reserved for future use 1883 #define PBE_BLE5_RAM_FL1INFO1_RESERVED_W 11U 1884 #define PBE_BLE5_RAM_FL1INFO1_RESERVED_M 0x7FF0U 1885 #define PBE_BLE5_RAM_FL1INFO1_RESERVED_S 4U 1886 1887 // Field: [3:3] privign 1888 // 1889 // Ignore control for privacy 1890 #define PBE_BLE5_RAM_FL1INFO1_PRIVIGN 0x0008U 1891 #define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_M 0x0008U 1892 #define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_S 3U 1893 #define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_NIGN 0x0000U 1894 #define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_IGN 0x0008U 1895 1896 // Field: [2:2] falign 1897 // 1898 // Ignore in accept list context 1899 #define PBE_BLE5_RAM_FL1INFO1_FALIGN 0x0004U 1900 #define PBE_BLE5_RAM_FL1INFO1_FALIGN_M 0x0004U 1901 #define PBE_BLE5_RAM_FL1INFO1_FALIGN_S 2U 1902 #define PBE_BLE5_RAM_FL1INFO1_FALIGN_NIGN 0x0000U 1903 #define PBE_BLE5_RAM_FL1INFO1_FALIGN_IGN 0x0004U 1904 1905 // Field: [1:1] type 1906 // 1907 // Address type 1908 #define PBE_BLE5_RAM_FL1INFO1_TYPE 0x0002U 1909 #define PBE_BLE5_RAM_FL1INFO1_TYPE_M 0x0002U 1910 #define PBE_BLE5_RAM_FL1INFO1_TYPE_S 1U 1911 #define PBE_BLE5_RAM_FL1INFO1_TYPE_PUBLIC 0x0000U 1912 #define PBE_BLE5_RAM_FL1INFO1_TYPE_RANDOM 0x0002U 1913 1914 // Field: [0:0] en 1915 // 1916 // Enable 1917 #define PBE_BLE5_RAM_FL1INFO1_EN 0x0001U 1918 #define PBE_BLE5_RAM_FL1INFO1_EN_M 0x0001U 1919 #define PBE_BLE5_RAM_FL1INFO1_EN_S 0U 1920 #define PBE_BLE5_RAM_FL1INFO1_EN_DIS 0x0000U 1921 #define PBE_BLE5_RAM_FL1INFO1_EN_EN 0x0001U 1922 1923 //****************************************************************************** 1924 // Register: FL1ADRL1 1925 //****************************************************************************** 1926 // Field: [15:0] val 1927 // 1928 // bits 15:0 of address 1929 #define PBE_BLE5_RAM_FL1ADRL1_VAL_W 16U 1930 #define PBE_BLE5_RAM_FL1ADRL1_VAL_M 0xFFFFU 1931 #define PBE_BLE5_RAM_FL1ADRL1_VAL_S 0U 1932 1933 //****************************************************************************** 1934 // Register: FL1ADRM1 1935 //****************************************************************************** 1936 // Field: [15:0] val 1937 // 1938 // bits 31:16 of address 1939 #define PBE_BLE5_RAM_FL1ADRM1_VAL_W 16U 1940 #define PBE_BLE5_RAM_FL1ADRM1_VAL_M 0xFFFFU 1941 #define PBE_BLE5_RAM_FL1ADRM1_VAL_S 0U 1942 1943 //****************************************************************************** 1944 // Register: FL1ADRH1 1945 //****************************************************************************** 1946 // Field: [15:0] val 1947 // 1948 // bits 47:32 of address 1949 #define PBE_BLE5_RAM_FL1ADRH1_VAL_W 16U 1950 #define PBE_BLE5_RAM_FL1ADRH1_VAL_M 0xFFFFU 1951 #define PBE_BLE5_RAM_FL1ADRH1_VAL_S 0U 1952 1953 //****************************************************************************** 1954 // Register: FL1INFO2 1955 //****************************************************************************** 1956 // Field: [15:15] matchtmp 1957 // 1958 // Temporary variable used in matching, ignore from CM0 1959 #define PBE_BLE5_RAM_FL1INFO2_MATCHTMP 0x8000U 1960 #define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_M 0x8000U 1961 #define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_S 15U 1962 #define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_NOMATCH 0x0000U 1963 #define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_MATCH 0x8000U 1964 1965 // Field: [14:4] reserved 1966 // 1967 // Reserved for future use 1968 #define PBE_BLE5_RAM_FL1INFO2_RESERVED_W 11U 1969 #define PBE_BLE5_RAM_FL1INFO2_RESERVED_M 0x7FF0U 1970 #define PBE_BLE5_RAM_FL1INFO2_RESERVED_S 4U 1971 1972 // Field: [3:3] privign 1973 // 1974 // Ignore control for privacy 1975 #define PBE_BLE5_RAM_FL1INFO2_PRIVIGN 0x0008U 1976 #define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_M 0x0008U 1977 #define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_S 3U 1978 #define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_NIGN 0x0000U 1979 #define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_IGN 0x0008U 1980 1981 // Field: [2:2] falign 1982 // 1983 // Ignore in accept list context 1984 #define PBE_BLE5_RAM_FL1INFO2_FALIGN 0x0004U 1985 #define PBE_BLE5_RAM_FL1INFO2_FALIGN_M 0x0004U 1986 #define PBE_BLE5_RAM_FL1INFO2_FALIGN_S 2U 1987 #define PBE_BLE5_RAM_FL1INFO2_FALIGN_NIGN 0x0000U 1988 #define PBE_BLE5_RAM_FL1INFO2_FALIGN_IGN 0x0004U 1989 1990 // Field: [1:1] type 1991 // 1992 // Address type 1993 #define PBE_BLE5_RAM_FL1INFO2_TYPE 0x0002U 1994 #define PBE_BLE5_RAM_FL1INFO2_TYPE_M 0x0002U 1995 #define PBE_BLE5_RAM_FL1INFO2_TYPE_S 1U 1996 #define PBE_BLE5_RAM_FL1INFO2_TYPE_PUBLIC 0x0000U 1997 #define PBE_BLE5_RAM_FL1INFO2_TYPE_RANDOM 0x0002U 1998 1999 // Field: [0:0] en 2000 // 2001 // Enable 2002 #define PBE_BLE5_RAM_FL1INFO2_EN 0x0001U 2003 #define PBE_BLE5_RAM_FL1INFO2_EN_M 0x0001U 2004 #define PBE_BLE5_RAM_FL1INFO2_EN_S 0U 2005 #define PBE_BLE5_RAM_FL1INFO2_EN_DIS 0x0000U 2006 #define PBE_BLE5_RAM_FL1INFO2_EN_EN 0x0001U 2007 2008 //****************************************************************************** 2009 // Register: FL1ADRL2 2010 //****************************************************************************** 2011 // Field: [15:0] val 2012 // 2013 // bits 15:0 of address 2014 #define PBE_BLE5_RAM_FL1ADRL2_VAL_W 16U 2015 #define PBE_BLE5_RAM_FL1ADRL2_VAL_M 0xFFFFU 2016 #define PBE_BLE5_RAM_FL1ADRL2_VAL_S 0U 2017 2018 //****************************************************************************** 2019 // Register: FL1ADRM2 2020 //****************************************************************************** 2021 // Field: [15:0] val 2022 // 2023 // bits 31:16 of address 2024 #define PBE_BLE5_RAM_FL1ADRM2_VAL_W 16U 2025 #define PBE_BLE5_RAM_FL1ADRM2_VAL_M 0xFFFFU 2026 #define PBE_BLE5_RAM_FL1ADRM2_VAL_S 0U 2027 2028 //****************************************************************************** 2029 // Register: FL1ADRH2 2030 //****************************************************************************** 2031 // Field: [15:0] val 2032 // 2033 // bits 47:32 of address 2034 #define PBE_BLE5_RAM_FL1ADRH2_VAL_W 16U 2035 #define PBE_BLE5_RAM_FL1ADRH2_VAL_M 0xFFFFU 2036 #define PBE_BLE5_RAM_FL1ADRH2_VAL_S 0U 2037 2038 //****************************************************************************** 2039 // Register: FL1INFO3 2040 //****************************************************************************** 2041 // Field: [15:15] matchtmp 2042 // 2043 // Temporary variable used in matching, ignore from CM0 2044 #define PBE_BLE5_RAM_FL1INFO3_MATCHTMP 0x8000U 2045 #define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_M 0x8000U 2046 #define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_S 15U 2047 #define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_NOMATCH 0x0000U 2048 #define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_MATCH 0x8000U 2049 2050 // Field: [14:4] reserved 2051 // 2052 // Reserved for future use 2053 #define PBE_BLE5_RAM_FL1INFO3_RESERVED_W 11U 2054 #define PBE_BLE5_RAM_FL1INFO3_RESERVED_M 0x7FF0U 2055 #define PBE_BLE5_RAM_FL1INFO3_RESERVED_S 4U 2056 2057 // Field: [3:3] privign 2058 // 2059 // Ignore control for privacy 2060 #define PBE_BLE5_RAM_FL1INFO3_PRIVIGN 0x0008U 2061 #define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_M 0x0008U 2062 #define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_S 3U 2063 #define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_NIGN 0x0000U 2064 #define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_IGN 0x0008U 2065 2066 // Field: [2:2] falign 2067 // 2068 // Ignore in accept list context 2069 #define PBE_BLE5_RAM_FL1INFO3_FALIGN 0x0004U 2070 #define PBE_BLE5_RAM_FL1INFO3_FALIGN_M 0x0004U 2071 #define PBE_BLE5_RAM_FL1INFO3_FALIGN_S 2U 2072 #define PBE_BLE5_RAM_FL1INFO3_FALIGN_NIGN 0x0000U 2073 #define PBE_BLE5_RAM_FL1INFO3_FALIGN_IGN 0x0004U 2074 2075 // Field: [1:1] type 2076 // 2077 // Address type 2078 #define PBE_BLE5_RAM_FL1INFO3_TYPE 0x0002U 2079 #define PBE_BLE5_RAM_FL1INFO3_TYPE_M 0x0002U 2080 #define PBE_BLE5_RAM_FL1INFO3_TYPE_S 1U 2081 #define PBE_BLE5_RAM_FL1INFO3_TYPE_PUBLIC 0x0000U 2082 #define PBE_BLE5_RAM_FL1INFO3_TYPE_RANDOM 0x0002U 2083 2084 // Field: [0:0] en 2085 // 2086 // Enable 2087 #define PBE_BLE5_RAM_FL1INFO3_EN 0x0001U 2088 #define PBE_BLE5_RAM_FL1INFO3_EN_M 0x0001U 2089 #define PBE_BLE5_RAM_FL1INFO3_EN_S 0U 2090 #define PBE_BLE5_RAM_FL1INFO3_EN_DIS 0x0000U 2091 #define PBE_BLE5_RAM_FL1INFO3_EN_EN 0x0001U 2092 2093 //****************************************************************************** 2094 // Register: FL1ADRL3 2095 //****************************************************************************** 2096 // Field: [15:0] val 2097 // 2098 // bits 15:0 of address 2099 #define PBE_BLE5_RAM_FL1ADRL3_VAL_W 16U 2100 #define PBE_BLE5_RAM_FL1ADRL3_VAL_M 0xFFFFU 2101 #define PBE_BLE5_RAM_FL1ADRL3_VAL_S 0U 2102 2103 //****************************************************************************** 2104 // Register: FL1ADRM3 2105 //****************************************************************************** 2106 // Field: [15:0] val 2107 // 2108 // bits 31:16 of address 2109 #define PBE_BLE5_RAM_FL1ADRM3_VAL_W 16U 2110 #define PBE_BLE5_RAM_FL1ADRM3_VAL_M 0xFFFFU 2111 #define PBE_BLE5_RAM_FL1ADRM3_VAL_S 0U 2112 2113 //****************************************************************************** 2114 // Register: FL1ADRH3 2115 //****************************************************************************** 2116 // Field: [15:0] val 2117 // 2118 // bits 47:32 of address 2119 #define PBE_BLE5_RAM_FL1ADRH3_VAL_W 16U 2120 #define PBE_BLE5_RAM_FL1ADRH3_VAL_M 0xFFFFU 2121 #define PBE_BLE5_RAM_FL1ADRH3_VAL_S 0U 2122 2123 //****************************************************************************** 2124 // Register: FL1INFO4 2125 //****************************************************************************** 2126 // Field: [15:15] matchtmp 2127 // 2128 // Temporary variable used in matching, ignore from CM0 2129 #define PBE_BLE5_RAM_FL1INFO4_MATCHTMP 0x8000U 2130 #define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_M 0x8000U 2131 #define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_S 15U 2132 #define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_NOMATCH 0x0000U 2133 #define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_MATCH 0x8000U 2134 2135 // Field: [14:4] reserved 2136 // 2137 // Reserved for future use 2138 #define PBE_BLE5_RAM_FL1INFO4_RESERVED_W 11U 2139 #define PBE_BLE5_RAM_FL1INFO4_RESERVED_M 0x7FF0U 2140 #define PBE_BLE5_RAM_FL1INFO4_RESERVED_S 4U 2141 2142 // Field: [3:3] privign 2143 // 2144 // Ignore control for privacy 2145 #define PBE_BLE5_RAM_FL1INFO4_PRIVIGN 0x0008U 2146 #define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_M 0x0008U 2147 #define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_S 3U 2148 #define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_NIGN 0x0000U 2149 #define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_IGN 0x0008U 2150 2151 // Field: [2:2] falign 2152 // 2153 // Ignore in accept list context 2154 #define PBE_BLE5_RAM_FL1INFO4_FALIGN 0x0004U 2155 #define PBE_BLE5_RAM_FL1INFO4_FALIGN_M 0x0004U 2156 #define PBE_BLE5_RAM_FL1INFO4_FALIGN_S 2U 2157 #define PBE_BLE5_RAM_FL1INFO4_FALIGN_NIGN 0x0000U 2158 #define PBE_BLE5_RAM_FL1INFO4_FALIGN_IGN 0x0004U 2159 2160 // Field: [1:1] type 2161 // 2162 // Address type 2163 #define PBE_BLE5_RAM_FL1INFO4_TYPE 0x0002U 2164 #define PBE_BLE5_RAM_FL1INFO4_TYPE_M 0x0002U 2165 #define PBE_BLE5_RAM_FL1INFO4_TYPE_S 1U 2166 #define PBE_BLE5_RAM_FL1INFO4_TYPE_PUBLIC 0x0000U 2167 #define PBE_BLE5_RAM_FL1INFO4_TYPE_RANDOM 0x0002U 2168 2169 // Field: [0:0] en 2170 // 2171 // Enable 2172 #define PBE_BLE5_RAM_FL1INFO4_EN 0x0001U 2173 #define PBE_BLE5_RAM_FL1INFO4_EN_M 0x0001U 2174 #define PBE_BLE5_RAM_FL1INFO4_EN_S 0U 2175 #define PBE_BLE5_RAM_FL1INFO4_EN_DIS 0x0000U 2176 #define PBE_BLE5_RAM_FL1INFO4_EN_EN 0x0001U 2177 2178 //****************************************************************************** 2179 // Register: FL1ADRL4 2180 //****************************************************************************** 2181 // Field: [15:0] val 2182 // 2183 // bits 15:0 of address 2184 #define PBE_BLE5_RAM_FL1ADRL4_VAL_W 16U 2185 #define PBE_BLE5_RAM_FL1ADRL4_VAL_M 0xFFFFU 2186 #define PBE_BLE5_RAM_FL1ADRL4_VAL_S 0U 2187 2188 //****************************************************************************** 2189 // Register: FL1ADRM4 2190 //****************************************************************************** 2191 // Field: [15:0] val 2192 // 2193 // bits 31:16 of address 2194 #define PBE_BLE5_RAM_FL1ADRM4_VAL_W 16U 2195 #define PBE_BLE5_RAM_FL1ADRM4_VAL_M 0xFFFFU 2196 #define PBE_BLE5_RAM_FL1ADRM4_VAL_S 0U 2197 2198 //****************************************************************************** 2199 // Register: FL1ADRH4 2200 //****************************************************************************** 2201 // Field: [15:0] val 2202 // 2203 // bits 47:32 of address 2204 #define PBE_BLE5_RAM_FL1ADRH4_VAL_W 16U 2205 #define PBE_BLE5_RAM_FL1ADRH4_VAL_M 0xFFFFU 2206 #define PBE_BLE5_RAM_FL1ADRH4_VAL_S 0U 2207 2208 //****************************************************************************** 2209 // Register: FL1INFO5 2210 //****************************************************************************** 2211 // Field: [15:15] matchtmp 2212 // 2213 // Temporary variable used in matching, ignore from CM0 2214 #define PBE_BLE5_RAM_FL1INFO5_MATCHTMP 0x8000U 2215 #define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_M 0x8000U 2216 #define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_S 15U 2217 #define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_NOMATCH 0x0000U 2218 #define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_MATCH 0x8000U 2219 2220 // Field: [14:4] reserved 2221 // 2222 // Reserved for future use 2223 #define PBE_BLE5_RAM_FL1INFO5_RESERVED_W 11U 2224 #define PBE_BLE5_RAM_FL1INFO5_RESERVED_M 0x7FF0U 2225 #define PBE_BLE5_RAM_FL1INFO5_RESERVED_S 4U 2226 2227 // Field: [3:3] privign 2228 // 2229 // Ignore control for privacy 2230 #define PBE_BLE5_RAM_FL1INFO5_PRIVIGN 0x0008U 2231 #define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_M 0x0008U 2232 #define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_S 3U 2233 #define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_NIGN 0x0000U 2234 #define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_IGN 0x0008U 2235 2236 // Field: [2:2] falign 2237 // 2238 // Ignore in accept list context 2239 #define PBE_BLE5_RAM_FL1INFO5_FALIGN 0x0004U 2240 #define PBE_BLE5_RAM_FL1INFO5_FALIGN_M 0x0004U 2241 #define PBE_BLE5_RAM_FL1INFO5_FALIGN_S 2U 2242 #define PBE_BLE5_RAM_FL1INFO5_FALIGN_NIGN 0x0000U 2243 #define PBE_BLE5_RAM_FL1INFO5_FALIGN_IGN 0x0004U 2244 2245 // Field: [1:1] type 2246 // 2247 // Address type 2248 #define PBE_BLE5_RAM_FL1INFO5_TYPE 0x0002U 2249 #define PBE_BLE5_RAM_FL1INFO5_TYPE_M 0x0002U 2250 #define PBE_BLE5_RAM_FL1INFO5_TYPE_S 1U 2251 #define PBE_BLE5_RAM_FL1INFO5_TYPE_PUBLIC 0x0000U 2252 #define PBE_BLE5_RAM_FL1INFO5_TYPE_RANDOM 0x0002U 2253 2254 // Field: [0:0] en 2255 // 2256 // Enable 2257 #define PBE_BLE5_RAM_FL1INFO5_EN 0x0001U 2258 #define PBE_BLE5_RAM_FL1INFO5_EN_M 0x0001U 2259 #define PBE_BLE5_RAM_FL1INFO5_EN_S 0U 2260 #define PBE_BLE5_RAM_FL1INFO5_EN_DIS 0x0000U 2261 #define PBE_BLE5_RAM_FL1INFO5_EN_EN 0x0001U 2262 2263 //****************************************************************************** 2264 // Register: FL1ADRL5 2265 //****************************************************************************** 2266 // Field: [15:0] val 2267 // 2268 // bits 15:0 of address 2269 #define PBE_BLE5_RAM_FL1ADRL5_VAL_W 16U 2270 #define PBE_BLE5_RAM_FL1ADRL5_VAL_M 0xFFFFU 2271 #define PBE_BLE5_RAM_FL1ADRL5_VAL_S 0U 2272 2273 //****************************************************************************** 2274 // Register: FL1ADRM5 2275 //****************************************************************************** 2276 // Field: [15:0] val 2277 // 2278 // bits 31:16 of address 2279 #define PBE_BLE5_RAM_FL1ADRM5_VAL_W 16U 2280 #define PBE_BLE5_RAM_FL1ADRM5_VAL_M 0xFFFFU 2281 #define PBE_BLE5_RAM_FL1ADRM5_VAL_S 0U 2282 2283 //****************************************************************************** 2284 // Register: FL1ADRH5 2285 //****************************************************************************** 2286 // Field: [15:0] val 2287 // 2288 // bits 47:32 of address 2289 #define PBE_BLE5_RAM_FL1ADRH5_VAL_W 16U 2290 #define PBE_BLE5_RAM_FL1ADRH5_VAL_M 0xFFFFU 2291 #define PBE_BLE5_RAM_FL1ADRH5_VAL_S 0U 2292 2293 //****************************************************************************** 2294 // Register: FL1INFO6 2295 //****************************************************************************** 2296 // Field: [15:15] matchtmp 2297 // 2298 // Temporary variable used in matching, ignore from CM0 2299 #define PBE_BLE5_RAM_FL1INFO6_MATCHTMP 0x8000U 2300 #define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_M 0x8000U 2301 #define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_S 15U 2302 #define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_NOMATCH 0x0000U 2303 #define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_MATCH 0x8000U 2304 2305 // Field: [14:4] reserved 2306 // 2307 // Reserved for future use 2308 #define PBE_BLE5_RAM_FL1INFO6_RESERVED_W 11U 2309 #define PBE_BLE5_RAM_FL1INFO6_RESERVED_M 0x7FF0U 2310 #define PBE_BLE5_RAM_FL1INFO6_RESERVED_S 4U 2311 2312 // Field: [3:3] privign 2313 // 2314 // Ignore control for privacy 2315 #define PBE_BLE5_RAM_FL1INFO6_PRIVIGN 0x0008U 2316 #define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_M 0x0008U 2317 #define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_S 3U 2318 #define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_NIGN 0x0000U 2319 #define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_IGN 0x0008U 2320 2321 // Field: [2:2] falign 2322 // 2323 // Ignore in accept list context 2324 #define PBE_BLE5_RAM_FL1INFO6_FALIGN 0x0004U 2325 #define PBE_BLE5_RAM_FL1INFO6_FALIGN_M 0x0004U 2326 #define PBE_BLE5_RAM_FL1INFO6_FALIGN_S 2U 2327 #define PBE_BLE5_RAM_FL1INFO6_FALIGN_NIGN 0x0000U 2328 #define PBE_BLE5_RAM_FL1INFO6_FALIGN_IGN 0x0004U 2329 2330 // Field: [1:1] type 2331 // 2332 // Address type 2333 #define PBE_BLE5_RAM_FL1INFO6_TYPE 0x0002U 2334 #define PBE_BLE5_RAM_FL1INFO6_TYPE_M 0x0002U 2335 #define PBE_BLE5_RAM_FL1INFO6_TYPE_S 1U 2336 #define PBE_BLE5_RAM_FL1INFO6_TYPE_PUBLIC 0x0000U 2337 #define PBE_BLE5_RAM_FL1INFO6_TYPE_RANDOM 0x0002U 2338 2339 // Field: [0:0] en 2340 // 2341 // Enable 2342 #define PBE_BLE5_RAM_FL1INFO6_EN 0x0001U 2343 #define PBE_BLE5_RAM_FL1INFO6_EN_M 0x0001U 2344 #define PBE_BLE5_RAM_FL1INFO6_EN_S 0U 2345 #define PBE_BLE5_RAM_FL1INFO6_EN_DIS 0x0000U 2346 #define PBE_BLE5_RAM_FL1INFO6_EN_EN 0x0001U 2347 2348 //****************************************************************************** 2349 // Register: FL1ADRL6 2350 //****************************************************************************** 2351 // Field: [15:0] val 2352 // 2353 // bits 15:0 of address 2354 #define PBE_BLE5_RAM_FL1ADRL6_VAL_W 16U 2355 #define PBE_BLE5_RAM_FL1ADRL6_VAL_M 0xFFFFU 2356 #define PBE_BLE5_RAM_FL1ADRL6_VAL_S 0U 2357 2358 //****************************************************************************** 2359 // Register: FL1ADRM6 2360 //****************************************************************************** 2361 // Field: [15:0] val 2362 // 2363 // bits 31:16 of address 2364 #define PBE_BLE5_RAM_FL1ADRM6_VAL_W 16U 2365 #define PBE_BLE5_RAM_FL1ADRM6_VAL_M 0xFFFFU 2366 #define PBE_BLE5_RAM_FL1ADRM6_VAL_S 0U 2367 2368 //****************************************************************************** 2369 // Register: FL1ADRH6 2370 //****************************************************************************** 2371 // Field: [15:0] val 2372 // 2373 // bits 47:32 of address 2374 #define PBE_BLE5_RAM_FL1ADRH6_VAL_W 16U 2375 #define PBE_BLE5_RAM_FL1ADRH6_VAL_M 0xFFFFU 2376 #define PBE_BLE5_RAM_FL1ADRH6_VAL_S 0U 2377 2378 //****************************************************************************** 2379 // Register: FL1INFO7 2380 //****************************************************************************** 2381 // Field: [15:15] matchtmp 2382 // 2383 // Temporary variable used in matching, ignore from CM0 2384 #define PBE_BLE5_RAM_FL1INFO7_MATCHTMP 0x8000U 2385 #define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_M 0x8000U 2386 #define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_S 15U 2387 #define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_NOMATCH 0x0000U 2388 #define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_MATCH 0x8000U 2389 2390 // Field: [14:4] reserved 2391 // 2392 // Reserved for future use 2393 #define PBE_BLE5_RAM_FL1INFO7_RESERVED_W 11U 2394 #define PBE_BLE5_RAM_FL1INFO7_RESERVED_M 0x7FF0U 2395 #define PBE_BLE5_RAM_FL1INFO7_RESERVED_S 4U 2396 2397 // Field: [3:3] privign 2398 // 2399 // Ignore control for privacy 2400 #define PBE_BLE5_RAM_FL1INFO7_PRIVIGN 0x0008U 2401 #define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_M 0x0008U 2402 #define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_S 3U 2403 #define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_NIGN 0x0000U 2404 #define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_IGN 0x0008U 2405 2406 // Field: [2:2] falign 2407 // 2408 // Ignore in accept list context 2409 #define PBE_BLE5_RAM_FL1INFO7_FALIGN 0x0004U 2410 #define PBE_BLE5_RAM_FL1INFO7_FALIGN_M 0x0004U 2411 #define PBE_BLE5_RAM_FL1INFO7_FALIGN_S 2U 2412 #define PBE_BLE5_RAM_FL1INFO7_FALIGN_NIGN 0x0000U 2413 #define PBE_BLE5_RAM_FL1INFO7_FALIGN_IGN 0x0004U 2414 2415 // Field: [1:1] type 2416 // 2417 // Address type 2418 #define PBE_BLE5_RAM_FL1INFO7_TYPE 0x0002U 2419 #define PBE_BLE5_RAM_FL1INFO7_TYPE_M 0x0002U 2420 #define PBE_BLE5_RAM_FL1INFO7_TYPE_S 1U 2421 #define PBE_BLE5_RAM_FL1INFO7_TYPE_PUBLIC 0x0000U 2422 #define PBE_BLE5_RAM_FL1INFO7_TYPE_RANDOM 0x0002U 2423 2424 // Field: [0:0] en 2425 // 2426 // Enable 2427 #define PBE_BLE5_RAM_FL1INFO7_EN 0x0001U 2428 #define PBE_BLE5_RAM_FL1INFO7_EN_M 0x0001U 2429 #define PBE_BLE5_RAM_FL1INFO7_EN_S 0U 2430 #define PBE_BLE5_RAM_FL1INFO7_EN_DIS 0x0000U 2431 #define PBE_BLE5_RAM_FL1INFO7_EN_EN 0x0001U 2432 2433 //****************************************************************************** 2434 // Register: FL1ADRL7 2435 //****************************************************************************** 2436 // Field: [15:0] val 2437 // 2438 // bits 15:0 of address 2439 #define PBE_BLE5_RAM_FL1ADRL7_VAL_W 16U 2440 #define PBE_BLE5_RAM_FL1ADRL7_VAL_M 0xFFFFU 2441 #define PBE_BLE5_RAM_FL1ADRL7_VAL_S 0U 2442 2443 //****************************************************************************** 2444 // Register: FL1ADRM7 2445 //****************************************************************************** 2446 // Field: [15:0] val 2447 // 2448 // bits 31:16 of address 2449 #define PBE_BLE5_RAM_FL1ADRM7_VAL_W 16U 2450 #define PBE_BLE5_RAM_FL1ADRM7_VAL_M 0xFFFFU 2451 #define PBE_BLE5_RAM_FL1ADRM7_VAL_S 0U 2452 2453 //****************************************************************************** 2454 // Register: FL1ADRH7 2455 //****************************************************************************** 2456 // Field: [15:0] val 2457 // 2458 // bits 47:32 of address 2459 #define PBE_BLE5_RAM_FL1ADRH7_VAL_W 16U 2460 #define PBE_BLE5_RAM_FL1ADRH7_VAL_M 0xFFFFU 2461 #define PBE_BLE5_RAM_FL1ADRH7_VAL_S 0U 2462 2463 //****************************************************************************** 2464 // Register: FL1INFO8 2465 //****************************************************************************** 2466 // Field: [15:15] matchtmp 2467 // 2468 // Temporary variable used in matching, ignore from CM0 2469 #define PBE_BLE5_RAM_FL1INFO8_MATCHTMP 0x8000U 2470 #define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_M 0x8000U 2471 #define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_S 15U 2472 #define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_NOMATCH 0x0000U 2473 #define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_MATCH 0x8000U 2474 2475 // Field: [14:4] reserved 2476 // 2477 // Reserved for future use 2478 #define PBE_BLE5_RAM_FL1INFO8_RESERVED_W 11U 2479 #define PBE_BLE5_RAM_FL1INFO8_RESERVED_M 0x7FF0U 2480 #define PBE_BLE5_RAM_FL1INFO8_RESERVED_S 4U 2481 2482 // Field: [3:3] privign 2483 // 2484 // Ignore control for privacy 2485 #define PBE_BLE5_RAM_FL1INFO8_PRIVIGN 0x0008U 2486 #define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_M 0x0008U 2487 #define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_S 3U 2488 #define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_NIGN 0x0000U 2489 #define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_IGN 0x0008U 2490 2491 // Field: [2:2] falign 2492 // 2493 // Ignore in accept list context 2494 #define PBE_BLE5_RAM_FL1INFO8_FALIGN 0x0004U 2495 #define PBE_BLE5_RAM_FL1INFO8_FALIGN_M 0x0004U 2496 #define PBE_BLE5_RAM_FL1INFO8_FALIGN_S 2U 2497 #define PBE_BLE5_RAM_FL1INFO8_FALIGN_NIGN 0x0000U 2498 #define PBE_BLE5_RAM_FL1INFO8_FALIGN_IGN 0x0004U 2499 2500 // Field: [1:1] type 2501 // 2502 // Address type 2503 #define PBE_BLE5_RAM_FL1INFO8_TYPE 0x0002U 2504 #define PBE_BLE5_RAM_FL1INFO8_TYPE_M 0x0002U 2505 #define PBE_BLE5_RAM_FL1INFO8_TYPE_S 1U 2506 #define PBE_BLE5_RAM_FL1INFO8_TYPE_PUBLIC 0x0000U 2507 #define PBE_BLE5_RAM_FL1INFO8_TYPE_RANDOM 0x0002U 2508 2509 // Field: [0:0] en 2510 // 2511 // Enable 2512 #define PBE_BLE5_RAM_FL1INFO8_EN 0x0001U 2513 #define PBE_BLE5_RAM_FL1INFO8_EN_M 0x0001U 2514 #define PBE_BLE5_RAM_FL1INFO8_EN_S 0U 2515 #define PBE_BLE5_RAM_FL1INFO8_EN_DIS 0x0000U 2516 #define PBE_BLE5_RAM_FL1INFO8_EN_EN 0x0001U 2517 2518 //****************************************************************************** 2519 // Register: FL1ADRL8 2520 //****************************************************************************** 2521 // Field: [15:0] val 2522 // 2523 // bits 15:0 of address 2524 #define PBE_BLE5_RAM_FL1ADRL8_VAL_W 16U 2525 #define PBE_BLE5_RAM_FL1ADRL8_VAL_M 0xFFFFU 2526 #define PBE_BLE5_RAM_FL1ADRL8_VAL_S 0U 2527 2528 //****************************************************************************** 2529 // Register: FL1ADRM8 2530 //****************************************************************************** 2531 // Field: [15:0] val 2532 // 2533 // bits 31:16 of address 2534 #define PBE_BLE5_RAM_FL1ADRM8_VAL_W 16U 2535 #define PBE_BLE5_RAM_FL1ADRM8_VAL_M 0xFFFFU 2536 #define PBE_BLE5_RAM_FL1ADRM8_VAL_S 0U 2537 2538 //****************************************************************************** 2539 // Register: FL1ADRH8 2540 //****************************************************************************** 2541 // Field: [15:0] val 2542 // 2543 // bits 47:32 of address 2544 #define PBE_BLE5_RAM_FL1ADRH8_VAL_W 16U 2545 #define PBE_BLE5_RAM_FL1ADRH8_VAL_M 0xFFFFU 2546 #define PBE_BLE5_RAM_FL1ADRH8_VAL_S 0U 2547 2548 //****************************************************************************** 2549 // Register: FL1INFO9 2550 //****************************************************************************** 2551 // Field: [15:15] matchtmp 2552 // 2553 // Temporary variable used in matching, ignore from CM0 2554 #define PBE_BLE5_RAM_FL1INFO9_MATCHTMP 0x8000U 2555 #define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_M 0x8000U 2556 #define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_S 15U 2557 #define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_NOMATCH 0x0000U 2558 #define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_MATCH 0x8000U 2559 2560 // Field: [14:4] reserved 2561 // 2562 // Reserved for future use 2563 #define PBE_BLE5_RAM_FL1INFO9_RESERVED_W 11U 2564 #define PBE_BLE5_RAM_FL1INFO9_RESERVED_M 0x7FF0U 2565 #define PBE_BLE5_RAM_FL1INFO9_RESERVED_S 4U 2566 2567 // Field: [3:3] privign 2568 // 2569 // Ignore control for privacy 2570 #define PBE_BLE5_RAM_FL1INFO9_PRIVIGN 0x0008U 2571 #define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_M 0x0008U 2572 #define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_S 3U 2573 #define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_NIGN 0x0000U 2574 #define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_IGN 0x0008U 2575 2576 // Field: [2:2] falign 2577 // 2578 // Ignore in accept list context 2579 #define PBE_BLE5_RAM_FL1INFO9_FALIGN 0x0004U 2580 #define PBE_BLE5_RAM_FL1INFO9_FALIGN_M 0x0004U 2581 #define PBE_BLE5_RAM_FL1INFO9_FALIGN_S 2U 2582 #define PBE_BLE5_RAM_FL1INFO9_FALIGN_NIGN 0x0000U 2583 #define PBE_BLE5_RAM_FL1INFO9_FALIGN_IGN 0x0004U 2584 2585 // Field: [1:1] type 2586 // 2587 // Address type 2588 #define PBE_BLE5_RAM_FL1INFO9_TYPE 0x0002U 2589 #define PBE_BLE5_RAM_FL1INFO9_TYPE_M 0x0002U 2590 #define PBE_BLE5_RAM_FL1INFO9_TYPE_S 1U 2591 #define PBE_BLE5_RAM_FL1INFO9_TYPE_PUBLIC 0x0000U 2592 #define PBE_BLE5_RAM_FL1INFO9_TYPE_RANDOM 0x0002U 2593 2594 // Field: [0:0] en 2595 // 2596 // Enable 2597 #define PBE_BLE5_RAM_FL1INFO9_EN 0x0001U 2598 #define PBE_BLE5_RAM_FL1INFO9_EN_M 0x0001U 2599 #define PBE_BLE5_RAM_FL1INFO9_EN_S 0U 2600 #define PBE_BLE5_RAM_FL1INFO9_EN_DIS 0x0000U 2601 #define PBE_BLE5_RAM_FL1INFO9_EN_EN 0x0001U 2602 2603 //****************************************************************************** 2604 // Register: FL1ADRL9 2605 //****************************************************************************** 2606 // Field: [15:0] val 2607 // 2608 // bits 15:0 of address 2609 #define PBE_BLE5_RAM_FL1ADRL9_VAL_W 16U 2610 #define PBE_BLE5_RAM_FL1ADRL9_VAL_M 0xFFFFU 2611 #define PBE_BLE5_RAM_FL1ADRL9_VAL_S 0U 2612 2613 //****************************************************************************** 2614 // Register: FL1ADRM9 2615 //****************************************************************************** 2616 // Field: [15:0] val 2617 // 2618 // bits 31:16 of address 2619 #define PBE_BLE5_RAM_FL1ADRM9_VAL_W 16U 2620 #define PBE_BLE5_RAM_FL1ADRM9_VAL_M 0xFFFFU 2621 #define PBE_BLE5_RAM_FL1ADRM9_VAL_S 0U 2622 2623 //****************************************************************************** 2624 // Register: FL1ADRH9 2625 //****************************************************************************** 2626 // Field: [15:0] val 2627 // 2628 // bits 47:32 of address 2629 #define PBE_BLE5_RAM_FL1ADRH9_VAL_W 16U 2630 #define PBE_BLE5_RAM_FL1ADRH9_VAL_M 0xFFFFU 2631 #define PBE_BLE5_RAM_FL1ADRH9_VAL_S 0U 2632 2633 //****************************************************************************** 2634 // Register: FL1INFO10 2635 //****************************************************************************** 2636 // Field: [15:15] matchtmp 2637 // 2638 // Temporary variable used in matching, ignore from CM0 2639 #define PBE_BLE5_RAM_FL1INFO10_MATCHTMP 0x8000U 2640 #define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_M 0x8000U 2641 #define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_S 15U 2642 #define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_NOMATCH 0x0000U 2643 #define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_MATCH 0x8000U 2644 2645 // Field: [14:4] reserved 2646 // 2647 // Reserved for future use 2648 #define PBE_BLE5_RAM_FL1INFO10_RESERVED_W 11U 2649 #define PBE_BLE5_RAM_FL1INFO10_RESERVED_M 0x7FF0U 2650 #define PBE_BLE5_RAM_FL1INFO10_RESERVED_S 4U 2651 2652 // Field: [3:3] privign 2653 // 2654 // Ignore control for privacy 2655 #define PBE_BLE5_RAM_FL1INFO10_PRIVIGN 0x0008U 2656 #define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_M 0x0008U 2657 #define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_S 3U 2658 #define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_NIGN 0x0000U 2659 #define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_IGN 0x0008U 2660 2661 // Field: [2:2] falign 2662 // 2663 // Ignore in accept list context 2664 #define PBE_BLE5_RAM_FL1INFO10_FALIGN 0x0004U 2665 #define PBE_BLE5_RAM_FL1INFO10_FALIGN_M 0x0004U 2666 #define PBE_BLE5_RAM_FL1INFO10_FALIGN_S 2U 2667 #define PBE_BLE5_RAM_FL1INFO10_FALIGN_NIGN 0x0000U 2668 #define PBE_BLE5_RAM_FL1INFO10_FALIGN_IGN 0x0004U 2669 2670 // Field: [1:1] type 2671 // 2672 // Address type 2673 #define PBE_BLE5_RAM_FL1INFO10_TYPE 0x0002U 2674 #define PBE_BLE5_RAM_FL1INFO10_TYPE_M 0x0002U 2675 #define PBE_BLE5_RAM_FL1INFO10_TYPE_S 1U 2676 #define PBE_BLE5_RAM_FL1INFO10_TYPE_PUBLIC 0x0000U 2677 #define PBE_BLE5_RAM_FL1INFO10_TYPE_RANDOM 0x0002U 2678 2679 // Field: [0:0] en 2680 // 2681 // Enable 2682 #define PBE_BLE5_RAM_FL1INFO10_EN 0x0001U 2683 #define PBE_BLE5_RAM_FL1INFO10_EN_M 0x0001U 2684 #define PBE_BLE5_RAM_FL1INFO10_EN_S 0U 2685 #define PBE_BLE5_RAM_FL1INFO10_EN_DIS 0x0000U 2686 #define PBE_BLE5_RAM_FL1INFO10_EN_EN 0x0001U 2687 2688 //****************************************************************************** 2689 // Register: FL1ADRL10 2690 //****************************************************************************** 2691 // Field: [15:0] val 2692 // 2693 // bits 15:0 of address 2694 #define PBE_BLE5_RAM_FL1ADRL10_VAL_W 16U 2695 #define PBE_BLE5_RAM_FL1ADRL10_VAL_M 0xFFFFU 2696 #define PBE_BLE5_RAM_FL1ADRL10_VAL_S 0U 2697 2698 //****************************************************************************** 2699 // Register: FL1ADRM10 2700 //****************************************************************************** 2701 // Field: [15:0] val 2702 // 2703 // bits 31:16 of address 2704 #define PBE_BLE5_RAM_FL1ADRM10_VAL_W 16U 2705 #define PBE_BLE5_RAM_FL1ADRM10_VAL_M 0xFFFFU 2706 #define PBE_BLE5_RAM_FL1ADRM10_VAL_S 0U 2707 2708 //****************************************************************************** 2709 // Register: FL1ADRH10 2710 //****************************************************************************** 2711 // Field: [15:0] val 2712 // 2713 // bits 47:32 of address 2714 #define PBE_BLE5_RAM_FL1ADRH10_VAL_W 16U 2715 #define PBE_BLE5_RAM_FL1ADRH10_VAL_M 0xFFFFU 2716 #define PBE_BLE5_RAM_FL1ADRH10_VAL_S 0U 2717 2718 //****************************************************************************** 2719 // Register: FL1INFO11 2720 //****************************************************************************** 2721 // Field: [15:15] matchtmp 2722 // 2723 // Temporary variable used in matching, ignore from CM0 2724 #define PBE_BLE5_RAM_FL1INFO11_MATCHTMP 0x8000U 2725 #define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_M 0x8000U 2726 #define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_S 15U 2727 #define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_NOMATCH 0x0000U 2728 #define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_MATCH 0x8000U 2729 2730 // Field: [14:4] reserved 2731 // 2732 // Reserved for future use 2733 #define PBE_BLE5_RAM_FL1INFO11_RESERVED_W 11U 2734 #define PBE_BLE5_RAM_FL1INFO11_RESERVED_M 0x7FF0U 2735 #define PBE_BLE5_RAM_FL1INFO11_RESERVED_S 4U 2736 2737 // Field: [3:3] privign 2738 // 2739 // Ignore control for privacy 2740 #define PBE_BLE5_RAM_FL1INFO11_PRIVIGN 0x0008U 2741 #define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_M 0x0008U 2742 #define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_S 3U 2743 #define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_NIGN 0x0000U 2744 #define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_IGN 0x0008U 2745 2746 // Field: [2:2] falign 2747 // 2748 // Ignore in accept list context 2749 #define PBE_BLE5_RAM_FL1INFO11_FALIGN 0x0004U 2750 #define PBE_BLE5_RAM_FL1INFO11_FALIGN_M 0x0004U 2751 #define PBE_BLE5_RAM_FL1INFO11_FALIGN_S 2U 2752 #define PBE_BLE5_RAM_FL1INFO11_FALIGN_NIGN 0x0000U 2753 #define PBE_BLE5_RAM_FL1INFO11_FALIGN_IGN 0x0004U 2754 2755 // Field: [1:1] type 2756 // 2757 // Address type 2758 #define PBE_BLE5_RAM_FL1INFO11_TYPE 0x0002U 2759 #define PBE_BLE5_RAM_FL1INFO11_TYPE_M 0x0002U 2760 #define PBE_BLE5_RAM_FL1INFO11_TYPE_S 1U 2761 #define PBE_BLE5_RAM_FL1INFO11_TYPE_PUBLIC 0x0000U 2762 #define PBE_BLE5_RAM_FL1INFO11_TYPE_RANDOM 0x0002U 2763 2764 // Field: [0:0] en 2765 // 2766 // Enable 2767 #define PBE_BLE5_RAM_FL1INFO11_EN 0x0001U 2768 #define PBE_BLE5_RAM_FL1INFO11_EN_M 0x0001U 2769 #define PBE_BLE5_RAM_FL1INFO11_EN_S 0U 2770 #define PBE_BLE5_RAM_FL1INFO11_EN_DIS 0x0000U 2771 #define PBE_BLE5_RAM_FL1INFO11_EN_EN 0x0001U 2772 2773 //****************************************************************************** 2774 // Register: FL1ADRL11 2775 //****************************************************************************** 2776 // Field: [15:0] val 2777 // 2778 // bits 15:0 of address 2779 #define PBE_BLE5_RAM_FL1ADRL11_VAL_W 16U 2780 #define PBE_BLE5_RAM_FL1ADRL11_VAL_M 0xFFFFU 2781 #define PBE_BLE5_RAM_FL1ADRL11_VAL_S 0U 2782 2783 //****************************************************************************** 2784 // Register: FL1ADRM11 2785 //****************************************************************************** 2786 // Field: [15:0] val 2787 // 2788 // bits 31:16 of address 2789 #define PBE_BLE5_RAM_FL1ADRM11_VAL_W 16U 2790 #define PBE_BLE5_RAM_FL1ADRM11_VAL_M 0xFFFFU 2791 #define PBE_BLE5_RAM_FL1ADRM11_VAL_S 0U 2792 2793 //****************************************************************************** 2794 // Register: FL1ADRH11 2795 //****************************************************************************** 2796 // Field: [15:0] val 2797 // 2798 // bits 47:32 of address 2799 #define PBE_BLE5_RAM_FL1ADRH11_VAL_W 16U 2800 #define PBE_BLE5_RAM_FL1ADRH11_VAL_M 0xFFFFU 2801 #define PBE_BLE5_RAM_FL1ADRH11_VAL_S 0U 2802 2803 //****************************************************************************** 2804 // Register: FL1INFO12 2805 //****************************************************************************** 2806 // Field: [15:15] matchtmp 2807 // 2808 // Temporary variable used in matching, ignore from CM0 2809 #define PBE_BLE5_RAM_FL1INFO12_MATCHTMP 0x8000U 2810 #define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_M 0x8000U 2811 #define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_S 15U 2812 #define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_NOMATCH 0x0000U 2813 #define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_MATCH 0x8000U 2814 2815 // Field: [14:4] reserved 2816 // 2817 // Reserved for future use 2818 #define PBE_BLE5_RAM_FL1INFO12_RESERVED_W 11U 2819 #define PBE_BLE5_RAM_FL1INFO12_RESERVED_M 0x7FF0U 2820 #define PBE_BLE5_RAM_FL1INFO12_RESERVED_S 4U 2821 2822 // Field: [3:3] privign 2823 // 2824 // Ignore control for privacy 2825 #define PBE_BLE5_RAM_FL1INFO12_PRIVIGN 0x0008U 2826 #define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_M 0x0008U 2827 #define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_S 3U 2828 #define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_NIGN 0x0000U 2829 #define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_IGN 0x0008U 2830 2831 // Field: [2:2] falign 2832 // 2833 // Ignore in accept list context 2834 #define PBE_BLE5_RAM_FL1INFO12_FALIGN 0x0004U 2835 #define PBE_BLE5_RAM_FL1INFO12_FALIGN_M 0x0004U 2836 #define PBE_BLE5_RAM_FL1INFO12_FALIGN_S 2U 2837 #define PBE_BLE5_RAM_FL1INFO12_FALIGN_NIGN 0x0000U 2838 #define PBE_BLE5_RAM_FL1INFO12_FALIGN_IGN 0x0004U 2839 2840 // Field: [1:1] type 2841 // 2842 // Address type 2843 #define PBE_BLE5_RAM_FL1INFO12_TYPE 0x0002U 2844 #define PBE_BLE5_RAM_FL1INFO12_TYPE_M 0x0002U 2845 #define PBE_BLE5_RAM_FL1INFO12_TYPE_S 1U 2846 #define PBE_BLE5_RAM_FL1INFO12_TYPE_PUBLIC 0x0000U 2847 #define PBE_BLE5_RAM_FL1INFO12_TYPE_RANDOM 0x0002U 2848 2849 // Field: [0:0] en 2850 // 2851 // Enable 2852 #define PBE_BLE5_RAM_FL1INFO12_EN 0x0001U 2853 #define PBE_BLE5_RAM_FL1INFO12_EN_M 0x0001U 2854 #define PBE_BLE5_RAM_FL1INFO12_EN_S 0U 2855 #define PBE_BLE5_RAM_FL1INFO12_EN_DIS 0x0000U 2856 #define PBE_BLE5_RAM_FL1INFO12_EN_EN 0x0001U 2857 2858 //****************************************************************************** 2859 // Register: FL1ADRL12 2860 //****************************************************************************** 2861 // Field: [15:0] val 2862 // 2863 // bits 15:0 of address 2864 #define PBE_BLE5_RAM_FL1ADRL12_VAL_W 16U 2865 #define PBE_BLE5_RAM_FL1ADRL12_VAL_M 0xFFFFU 2866 #define PBE_BLE5_RAM_FL1ADRL12_VAL_S 0U 2867 2868 //****************************************************************************** 2869 // Register: FL1ADRM12 2870 //****************************************************************************** 2871 // Field: [15:0] val 2872 // 2873 // bits 31:16 of address 2874 #define PBE_BLE5_RAM_FL1ADRM12_VAL_W 16U 2875 #define PBE_BLE5_RAM_FL1ADRM12_VAL_M 0xFFFFU 2876 #define PBE_BLE5_RAM_FL1ADRM12_VAL_S 0U 2877 2878 //****************************************************************************** 2879 // Register: FL1ADRH12 2880 //****************************************************************************** 2881 // Field: [15:0] val 2882 // 2883 // bits 47:32 of address 2884 #define PBE_BLE5_RAM_FL1ADRH12_VAL_W 16U 2885 #define PBE_BLE5_RAM_FL1ADRH12_VAL_M 0xFFFFU 2886 #define PBE_BLE5_RAM_FL1ADRH12_VAL_S 0U 2887 2888 //****************************************************************************** 2889 // Register: FL1INFO13 2890 //****************************************************************************** 2891 // Field: [15:15] matchtmp 2892 // 2893 // Temporary variable used in matching, ignore from CM0 2894 #define PBE_BLE5_RAM_FL1INFO13_MATCHTMP 0x8000U 2895 #define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_M 0x8000U 2896 #define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_S 15U 2897 #define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_NOMATCH 0x0000U 2898 #define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_MATCH 0x8000U 2899 2900 // Field: [14:4] reserved 2901 // 2902 // Reserved for future use 2903 #define PBE_BLE5_RAM_FL1INFO13_RESERVED_W 11U 2904 #define PBE_BLE5_RAM_FL1INFO13_RESERVED_M 0x7FF0U 2905 #define PBE_BLE5_RAM_FL1INFO13_RESERVED_S 4U 2906 2907 // Field: [3:3] privign 2908 // 2909 // Ignore control for privacy 2910 #define PBE_BLE5_RAM_FL1INFO13_PRIVIGN 0x0008U 2911 #define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_M 0x0008U 2912 #define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_S 3U 2913 #define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_NIGN 0x0000U 2914 #define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_IGN 0x0008U 2915 2916 // Field: [2:2] falign 2917 // 2918 // Ignore in accept list context 2919 #define PBE_BLE5_RAM_FL1INFO13_FALIGN 0x0004U 2920 #define PBE_BLE5_RAM_FL1INFO13_FALIGN_M 0x0004U 2921 #define PBE_BLE5_RAM_FL1INFO13_FALIGN_S 2U 2922 #define PBE_BLE5_RAM_FL1INFO13_FALIGN_NIGN 0x0000U 2923 #define PBE_BLE5_RAM_FL1INFO13_FALIGN_IGN 0x0004U 2924 2925 // Field: [1:1] type 2926 // 2927 // Address type 2928 #define PBE_BLE5_RAM_FL1INFO13_TYPE 0x0002U 2929 #define PBE_BLE5_RAM_FL1INFO13_TYPE_M 0x0002U 2930 #define PBE_BLE5_RAM_FL1INFO13_TYPE_S 1U 2931 #define PBE_BLE5_RAM_FL1INFO13_TYPE_PUBLIC 0x0000U 2932 #define PBE_BLE5_RAM_FL1INFO13_TYPE_RANDOM 0x0002U 2933 2934 // Field: [0:0] en 2935 // 2936 // Enable 2937 #define PBE_BLE5_RAM_FL1INFO13_EN 0x0001U 2938 #define PBE_BLE5_RAM_FL1INFO13_EN_M 0x0001U 2939 #define PBE_BLE5_RAM_FL1INFO13_EN_S 0U 2940 #define PBE_BLE5_RAM_FL1INFO13_EN_DIS 0x0000U 2941 #define PBE_BLE5_RAM_FL1INFO13_EN_EN 0x0001U 2942 2943 //****************************************************************************** 2944 // Register: FL1ADRL13 2945 //****************************************************************************** 2946 // Field: [15:0] val 2947 // 2948 // bits 15:0 of address 2949 #define PBE_BLE5_RAM_FL1ADRL13_VAL_W 16U 2950 #define PBE_BLE5_RAM_FL1ADRL13_VAL_M 0xFFFFU 2951 #define PBE_BLE5_RAM_FL1ADRL13_VAL_S 0U 2952 2953 //****************************************************************************** 2954 // Register: FL1ADRM13 2955 //****************************************************************************** 2956 // Field: [15:0] val 2957 // 2958 // bits 31:16 of address 2959 #define PBE_BLE5_RAM_FL1ADRM13_VAL_W 16U 2960 #define PBE_BLE5_RAM_FL1ADRM13_VAL_M 0xFFFFU 2961 #define PBE_BLE5_RAM_FL1ADRM13_VAL_S 0U 2962 2963 //****************************************************************************** 2964 // Register: FL1ADRH13 2965 //****************************************************************************** 2966 // Field: [15:0] val 2967 // 2968 // bits 47:32 of address 2969 #define PBE_BLE5_RAM_FL1ADRH13_VAL_W 16U 2970 #define PBE_BLE5_RAM_FL1ADRH13_VAL_M 0xFFFFU 2971 #define PBE_BLE5_RAM_FL1ADRH13_VAL_S 0U 2972 2973 //****************************************************************************** 2974 // Register: FL1INFO14 2975 //****************************************************************************** 2976 // Field: [15:15] matchtmp 2977 // 2978 // Temporary variable used in matching, ignore from CM0 2979 #define PBE_BLE5_RAM_FL1INFO14_MATCHTMP 0x8000U 2980 #define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_M 0x8000U 2981 #define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_S 15U 2982 #define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_NOMATCH 0x0000U 2983 #define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_MATCH 0x8000U 2984 2985 // Field: [14:4] reserved 2986 // 2987 // Reserved for future use 2988 #define PBE_BLE5_RAM_FL1INFO14_RESERVED_W 11U 2989 #define PBE_BLE5_RAM_FL1INFO14_RESERVED_M 0x7FF0U 2990 #define PBE_BLE5_RAM_FL1INFO14_RESERVED_S 4U 2991 2992 // Field: [3:3] privign 2993 // 2994 // Ignore control for privacy 2995 #define PBE_BLE5_RAM_FL1INFO14_PRIVIGN 0x0008U 2996 #define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_M 0x0008U 2997 #define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_S 3U 2998 #define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_NIGN 0x0000U 2999 #define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_IGN 0x0008U 3000 3001 // Field: [2:2] falign 3002 // 3003 // Ignore in accept list context 3004 #define PBE_BLE5_RAM_FL1INFO14_FALIGN 0x0004U 3005 #define PBE_BLE5_RAM_FL1INFO14_FALIGN_M 0x0004U 3006 #define PBE_BLE5_RAM_FL1INFO14_FALIGN_S 2U 3007 #define PBE_BLE5_RAM_FL1INFO14_FALIGN_NIGN 0x0000U 3008 #define PBE_BLE5_RAM_FL1INFO14_FALIGN_IGN 0x0004U 3009 3010 // Field: [1:1] type 3011 // 3012 // Address type 3013 #define PBE_BLE5_RAM_FL1INFO14_TYPE 0x0002U 3014 #define PBE_BLE5_RAM_FL1INFO14_TYPE_M 0x0002U 3015 #define PBE_BLE5_RAM_FL1INFO14_TYPE_S 1U 3016 #define PBE_BLE5_RAM_FL1INFO14_TYPE_PUBLIC 0x0000U 3017 #define PBE_BLE5_RAM_FL1INFO14_TYPE_RANDOM 0x0002U 3018 3019 // Field: [0:0] en 3020 // 3021 // Enable 3022 #define PBE_BLE5_RAM_FL1INFO14_EN 0x0001U 3023 #define PBE_BLE5_RAM_FL1INFO14_EN_M 0x0001U 3024 #define PBE_BLE5_RAM_FL1INFO14_EN_S 0U 3025 #define PBE_BLE5_RAM_FL1INFO14_EN_DIS 0x0000U 3026 #define PBE_BLE5_RAM_FL1INFO14_EN_EN 0x0001U 3027 3028 //****************************************************************************** 3029 // Register: FL1ADRL14 3030 //****************************************************************************** 3031 // Field: [15:0] val 3032 // 3033 // bits 15:0 of address 3034 #define PBE_BLE5_RAM_FL1ADRL14_VAL_W 16U 3035 #define PBE_BLE5_RAM_FL1ADRL14_VAL_M 0xFFFFU 3036 #define PBE_BLE5_RAM_FL1ADRL14_VAL_S 0U 3037 3038 //****************************************************************************** 3039 // Register: FL1ADRM14 3040 //****************************************************************************** 3041 // Field: [15:0] val 3042 // 3043 // bits 31:16 of address 3044 #define PBE_BLE5_RAM_FL1ADRM14_VAL_W 16U 3045 #define PBE_BLE5_RAM_FL1ADRM14_VAL_M 0xFFFFU 3046 #define PBE_BLE5_RAM_FL1ADRM14_VAL_S 0U 3047 3048 //****************************************************************************** 3049 // Register: FL1ADRH14 3050 //****************************************************************************** 3051 // Field: [15:0] val 3052 // 3053 // bits 47:32 of address 3054 #define PBE_BLE5_RAM_FL1ADRH14_VAL_W 16U 3055 #define PBE_BLE5_RAM_FL1ADRH14_VAL_M 0xFFFFU 3056 #define PBE_BLE5_RAM_FL1ADRH14_VAL_S 0U 3057 3058 //****************************************************************************** 3059 // Register: FL1INFO15 3060 //****************************************************************************** 3061 // Field: [15:15] matchtmp 3062 // 3063 // Temporary variable used in matching, ignore from CM0 3064 #define PBE_BLE5_RAM_FL1INFO15_MATCHTMP 0x8000U 3065 #define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_M 0x8000U 3066 #define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_S 15U 3067 #define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_NOMATCH 0x0000U 3068 #define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_MATCH 0x8000U 3069 3070 // Field: [14:4] reserved 3071 // 3072 // Reserved for future use 3073 #define PBE_BLE5_RAM_FL1INFO15_RESERVED_W 11U 3074 #define PBE_BLE5_RAM_FL1INFO15_RESERVED_M 0x7FF0U 3075 #define PBE_BLE5_RAM_FL1INFO15_RESERVED_S 4U 3076 3077 // Field: [3:3] privign 3078 // 3079 // Ignore control for privacy 3080 #define PBE_BLE5_RAM_FL1INFO15_PRIVIGN 0x0008U 3081 #define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_M 0x0008U 3082 #define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_S 3U 3083 #define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_NIGN 0x0000U 3084 #define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_IGN 0x0008U 3085 3086 // Field: [2:2] falign 3087 // 3088 // Ignore in accept list context 3089 #define PBE_BLE5_RAM_FL1INFO15_FALIGN 0x0004U 3090 #define PBE_BLE5_RAM_FL1INFO15_FALIGN_M 0x0004U 3091 #define PBE_BLE5_RAM_FL1INFO15_FALIGN_S 2U 3092 #define PBE_BLE5_RAM_FL1INFO15_FALIGN_NIGN 0x0000U 3093 #define PBE_BLE5_RAM_FL1INFO15_FALIGN_IGN 0x0004U 3094 3095 // Field: [1:1] type 3096 // 3097 // Address type 3098 #define PBE_BLE5_RAM_FL1INFO15_TYPE 0x0002U 3099 #define PBE_BLE5_RAM_FL1INFO15_TYPE_M 0x0002U 3100 #define PBE_BLE5_RAM_FL1INFO15_TYPE_S 1U 3101 #define PBE_BLE5_RAM_FL1INFO15_TYPE_PUBLIC 0x0000U 3102 #define PBE_BLE5_RAM_FL1INFO15_TYPE_RANDOM 0x0002U 3103 3104 // Field: [0:0] en 3105 // 3106 // Enable 3107 #define PBE_BLE5_RAM_FL1INFO15_EN 0x0001U 3108 #define PBE_BLE5_RAM_FL1INFO15_EN_M 0x0001U 3109 #define PBE_BLE5_RAM_FL1INFO15_EN_S 0U 3110 #define PBE_BLE5_RAM_FL1INFO15_EN_DIS 0x0000U 3111 #define PBE_BLE5_RAM_FL1INFO15_EN_EN 0x0001U 3112 3113 //****************************************************************************** 3114 // Register: FL1ADRL15 3115 //****************************************************************************** 3116 // Field: [15:0] val 3117 // 3118 // bits 15:0 of address 3119 #define PBE_BLE5_RAM_FL1ADRL15_VAL_W 16U 3120 #define PBE_BLE5_RAM_FL1ADRL15_VAL_M 0xFFFFU 3121 #define PBE_BLE5_RAM_FL1ADRL15_VAL_S 0U 3122 3123 //****************************************************************************** 3124 // Register: FL1ADRM15 3125 //****************************************************************************** 3126 // Field: [15:0] val 3127 // 3128 // bits 31:16 of address 3129 #define PBE_BLE5_RAM_FL1ADRM15_VAL_W 16U 3130 #define PBE_BLE5_RAM_FL1ADRM15_VAL_M 0xFFFFU 3131 #define PBE_BLE5_RAM_FL1ADRM15_VAL_S 0U 3132 3133 //****************************************************************************** 3134 // Register: FL1ADRH15 3135 //****************************************************************************** 3136 // Field: [15:0] val 3137 // 3138 // bits 47:32 of address 3139 #define PBE_BLE5_RAM_FL1ADRH15_VAL_W 16U 3140 #define PBE_BLE5_RAM_FL1ADRH15_VAL_M 0xFFFFU 3141 #define PBE_BLE5_RAM_FL1ADRH15_VAL_S 0U 3142 3143 //****************************************************************************** 3144 // Register: FL2INFO0 3145 //****************************************************************************** 3146 // Field: [15:15] matchtmp 3147 // 3148 // Temporary variable used in matching, ignore from CM0 3149 #define PBE_BLE5_RAM_FL2INFO0_MATCHTMP 0x8000U 3150 #define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_M 0x8000U 3151 #define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_S 15U 3152 #define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_NOMATCH 0x0000U 3153 #define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_MATCH 0x8000U 3154 3155 // Field: [14:4] reserved 3156 // 3157 // Reserved for future use 3158 #define PBE_BLE5_RAM_FL2INFO0_RESERVED_W 11U 3159 #define PBE_BLE5_RAM_FL2INFO0_RESERVED_M 0x7FF0U 3160 #define PBE_BLE5_RAM_FL2INFO0_RESERVED_S 4U 3161 3162 // Field: [3:3] privign 3163 // 3164 // Ignore control for privacy 3165 #define PBE_BLE5_RAM_FL2INFO0_PRIVIGN 0x0008U 3166 #define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_M 0x0008U 3167 #define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_S 3U 3168 #define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_NIGN 0x0000U 3169 #define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_IGN 0x0008U 3170 3171 // Field: [2:2] falign 3172 // 3173 // Ignore in accept list context 3174 #define PBE_BLE5_RAM_FL2INFO0_FALIGN 0x0004U 3175 #define PBE_BLE5_RAM_FL2INFO0_FALIGN_M 0x0004U 3176 #define PBE_BLE5_RAM_FL2INFO0_FALIGN_S 2U 3177 #define PBE_BLE5_RAM_FL2INFO0_FALIGN_NIGN 0x0000U 3178 #define PBE_BLE5_RAM_FL2INFO0_FALIGN_IGN 0x0004U 3179 3180 // Field: [1:1] type 3181 // 3182 // Address type 3183 #define PBE_BLE5_RAM_FL2INFO0_TYPE 0x0002U 3184 #define PBE_BLE5_RAM_FL2INFO0_TYPE_M 0x0002U 3185 #define PBE_BLE5_RAM_FL2INFO0_TYPE_S 1U 3186 #define PBE_BLE5_RAM_FL2INFO0_TYPE_PUBLIC 0x0000U 3187 #define PBE_BLE5_RAM_FL2INFO0_TYPE_RANDOM 0x0002U 3188 3189 // Field: [0:0] en 3190 // 3191 // Enable 3192 #define PBE_BLE5_RAM_FL2INFO0_EN 0x0001U 3193 #define PBE_BLE5_RAM_FL2INFO0_EN_M 0x0001U 3194 #define PBE_BLE5_RAM_FL2INFO0_EN_S 0U 3195 #define PBE_BLE5_RAM_FL2INFO0_EN_DIS 0x0000U 3196 #define PBE_BLE5_RAM_FL2INFO0_EN_EN 0x0001U 3197 3198 //****************************************************************************** 3199 // Register: FL2ADRL0 3200 //****************************************************************************** 3201 // Field: [15:0] val 3202 // 3203 // bits 15:0 of address 3204 #define PBE_BLE5_RAM_FL2ADRL0_VAL_W 16U 3205 #define PBE_BLE5_RAM_FL2ADRL0_VAL_M 0xFFFFU 3206 #define PBE_BLE5_RAM_FL2ADRL0_VAL_S 0U 3207 3208 //****************************************************************************** 3209 // Register: FL2ADRM0 3210 //****************************************************************************** 3211 // Field: [15:0] val 3212 // 3213 // bits 31:16 of address 3214 #define PBE_BLE5_RAM_FL2ADRM0_VAL_W 16U 3215 #define PBE_BLE5_RAM_FL2ADRM0_VAL_M 0xFFFFU 3216 #define PBE_BLE5_RAM_FL2ADRM0_VAL_S 0U 3217 3218 //****************************************************************************** 3219 // Register: FL2ADRH0 3220 //****************************************************************************** 3221 // Field: [15:0] val 3222 // 3223 // bits 47:32 of address 3224 #define PBE_BLE5_RAM_FL2ADRH0_VAL_W 16U 3225 #define PBE_BLE5_RAM_FL2ADRH0_VAL_M 0xFFFFU 3226 #define PBE_BLE5_RAM_FL2ADRH0_VAL_S 0U 3227 3228 //****************************************************************************** 3229 // Register: FL2INFO1 3230 //****************************************************************************** 3231 // Field: [15:15] matchtmp 3232 // 3233 // Temporary variable used in matching, ignore from CM0 3234 #define PBE_BLE5_RAM_FL2INFO1_MATCHTMP 0x8000U 3235 #define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_M 0x8000U 3236 #define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_S 15U 3237 #define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_NOMATCH 0x0000U 3238 #define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_MATCH 0x8000U 3239 3240 // Field: [14:4] reserved 3241 // 3242 // Reserved for future use 3243 #define PBE_BLE5_RAM_FL2INFO1_RESERVED_W 11U 3244 #define PBE_BLE5_RAM_FL2INFO1_RESERVED_M 0x7FF0U 3245 #define PBE_BLE5_RAM_FL2INFO1_RESERVED_S 4U 3246 3247 // Field: [3:3] privign 3248 // 3249 // Ignore control for privacy 3250 #define PBE_BLE5_RAM_FL2INFO1_PRIVIGN 0x0008U 3251 #define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_M 0x0008U 3252 #define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_S 3U 3253 #define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_NIGN 0x0000U 3254 #define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_IGN 0x0008U 3255 3256 // Field: [2:2] falign 3257 // 3258 // Ignore in accept list context 3259 #define PBE_BLE5_RAM_FL2INFO1_FALIGN 0x0004U 3260 #define PBE_BLE5_RAM_FL2INFO1_FALIGN_M 0x0004U 3261 #define PBE_BLE5_RAM_FL2INFO1_FALIGN_S 2U 3262 #define PBE_BLE5_RAM_FL2INFO1_FALIGN_NIGN 0x0000U 3263 #define PBE_BLE5_RAM_FL2INFO1_FALIGN_IGN 0x0004U 3264 3265 // Field: [1:1] type 3266 // 3267 // Address type 3268 #define PBE_BLE5_RAM_FL2INFO1_TYPE 0x0002U 3269 #define PBE_BLE5_RAM_FL2INFO1_TYPE_M 0x0002U 3270 #define PBE_BLE5_RAM_FL2INFO1_TYPE_S 1U 3271 #define PBE_BLE5_RAM_FL2INFO1_TYPE_PUBLIC 0x0000U 3272 #define PBE_BLE5_RAM_FL2INFO1_TYPE_RANDOM 0x0002U 3273 3274 // Field: [0:0] en 3275 // 3276 // Enable 3277 #define PBE_BLE5_RAM_FL2INFO1_EN 0x0001U 3278 #define PBE_BLE5_RAM_FL2INFO1_EN_M 0x0001U 3279 #define PBE_BLE5_RAM_FL2INFO1_EN_S 0U 3280 #define PBE_BLE5_RAM_FL2INFO1_EN_DIS 0x0000U 3281 #define PBE_BLE5_RAM_FL2INFO1_EN_EN 0x0001U 3282 3283 //****************************************************************************** 3284 // Register: FL2ADRL1 3285 //****************************************************************************** 3286 // Field: [15:0] val 3287 // 3288 // bits 15:0 of address 3289 #define PBE_BLE5_RAM_FL2ADRL1_VAL_W 16U 3290 #define PBE_BLE5_RAM_FL2ADRL1_VAL_M 0xFFFFU 3291 #define PBE_BLE5_RAM_FL2ADRL1_VAL_S 0U 3292 3293 //****************************************************************************** 3294 // Register: FL2ADRM1 3295 //****************************************************************************** 3296 // Field: [15:0] val 3297 // 3298 // bits 31:16 of address 3299 #define PBE_BLE5_RAM_FL2ADRM1_VAL_W 16U 3300 #define PBE_BLE5_RAM_FL2ADRM1_VAL_M 0xFFFFU 3301 #define PBE_BLE5_RAM_FL2ADRM1_VAL_S 0U 3302 3303 //****************************************************************************** 3304 // Register: FL2ADRH1 3305 //****************************************************************************** 3306 // Field: [15:0] val 3307 // 3308 // bits 47:32 of address 3309 #define PBE_BLE5_RAM_FL2ADRH1_VAL_W 16U 3310 #define PBE_BLE5_RAM_FL2ADRH1_VAL_M 0xFFFFU 3311 #define PBE_BLE5_RAM_FL2ADRH1_VAL_S 0U 3312 3313 //****************************************************************************** 3314 // Register: FL2INFO2 3315 //****************************************************************************** 3316 // Field: [15:15] matchtmp 3317 // 3318 // Temporary variable used in matching, ignore from CM0 3319 #define PBE_BLE5_RAM_FL2INFO2_MATCHTMP 0x8000U 3320 #define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_M 0x8000U 3321 #define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_S 15U 3322 #define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_NOMATCH 0x0000U 3323 #define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_MATCH 0x8000U 3324 3325 // Field: [14:4] reserved 3326 // 3327 // Reserved for future use 3328 #define PBE_BLE5_RAM_FL2INFO2_RESERVED_W 11U 3329 #define PBE_BLE5_RAM_FL2INFO2_RESERVED_M 0x7FF0U 3330 #define PBE_BLE5_RAM_FL2INFO2_RESERVED_S 4U 3331 3332 // Field: [3:3] privign 3333 // 3334 // Ignore control for privacy 3335 #define PBE_BLE5_RAM_FL2INFO2_PRIVIGN 0x0008U 3336 #define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_M 0x0008U 3337 #define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_S 3U 3338 #define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_NIGN 0x0000U 3339 #define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_IGN 0x0008U 3340 3341 // Field: [2:2] falign 3342 // 3343 // Ignore in accept list context 3344 #define PBE_BLE5_RAM_FL2INFO2_FALIGN 0x0004U 3345 #define PBE_BLE5_RAM_FL2INFO2_FALIGN_M 0x0004U 3346 #define PBE_BLE5_RAM_FL2INFO2_FALIGN_S 2U 3347 #define PBE_BLE5_RAM_FL2INFO2_FALIGN_NIGN 0x0000U 3348 #define PBE_BLE5_RAM_FL2INFO2_FALIGN_IGN 0x0004U 3349 3350 // Field: [1:1] type 3351 // 3352 // Address type 3353 #define PBE_BLE5_RAM_FL2INFO2_TYPE 0x0002U 3354 #define PBE_BLE5_RAM_FL2INFO2_TYPE_M 0x0002U 3355 #define PBE_BLE5_RAM_FL2INFO2_TYPE_S 1U 3356 #define PBE_BLE5_RAM_FL2INFO2_TYPE_PUBLIC 0x0000U 3357 #define PBE_BLE5_RAM_FL2INFO2_TYPE_RANDOM 0x0002U 3358 3359 // Field: [0:0] en 3360 // 3361 // Enable 3362 #define PBE_BLE5_RAM_FL2INFO2_EN 0x0001U 3363 #define PBE_BLE5_RAM_FL2INFO2_EN_M 0x0001U 3364 #define PBE_BLE5_RAM_FL2INFO2_EN_S 0U 3365 #define PBE_BLE5_RAM_FL2INFO2_EN_DIS 0x0000U 3366 #define PBE_BLE5_RAM_FL2INFO2_EN_EN 0x0001U 3367 3368 //****************************************************************************** 3369 // Register: FL2ADRL2 3370 //****************************************************************************** 3371 // Field: [15:0] val 3372 // 3373 // bits 15:0 of address 3374 #define PBE_BLE5_RAM_FL2ADRL2_VAL_W 16U 3375 #define PBE_BLE5_RAM_FL2ADRL2_VAL_M 0xFFFFU 3376 #define PBE_BLE5_RAM_FL2ADRL2_VAL_S 0U 3377 3378 //****************************************************************************** 3379 // Register: FL2ADRM2 3380 //****************************************************************************** 3381 // Field: [15:0] val 3382 // 3383 // bits 31:16 of address 3384 #define PBE_BLE5_RAM_FL2ADRM2_VAL_W 16U 3385 #define PBE_BLE5_RAM_FL2ADRM2_VAL_M 0xFFFFU 3386 #define PBE_BLE5_RAM_FL2ADRM2_VAL_S 0U 3387 3388 //****************************************************************************** 3389 // Register: FL2ADRH2 3390 //****************************************************************************** 3391 // Field: [15:0] val 3392 // 3393 // bits 47:32 of address 3394 #define PBE_BLE5_RAM_FL2ADRH2_VAL_W 16U 3395 #define PBE_BLE5_RAM_FL2ADRH2_VAL_M 0xFFFFU 3396 #define PBE_BLE5_RAM_FL2ADRH2_VAL_S 0U 3397 3398 //****************************************************************************** 3399 // Register: FL2INFO3 3400 //****************************************************************************** 3401 // Field: [15:15] matchtmp 3402 // 3403 // Temporary variable used in matching, ignore from CM0 3404 #define PBE_BLE5_RAM_FL2INFO3_MATCHTMP 0x8000U 3405 #define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_M 0x8000U 3406 #define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_S 15U 3407 #define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_NOMATCH 0x0000U 3408 #define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_MATCH 0x8000U 3409 3410 // Field: [14:4] reserved 3411 // 3412 // Reserved for future use 3413 #define PBE_BLE5_RAM_FL2INFO3_RESERVED_W 11U 3414 #define PBE_BLE5_RAM_FL2INFO3_RESERVED_M 0x7FF0U 3415 #define PBE_BLE5_RAM_FL2INFO3_RESERVED_S 4U 3416 3417 // Field: [3:3] privign 3418 // 3419 // Ignore control for privacy 3420 #define PBE_BLE5_RAM_FL2INFO3_PRIVIGN 0x0008U 3421 #define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_M 0x0008U 3422 #define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_S 3U 3423 #define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_NIGN 0x0000U 3424 #define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_IGN 0x0008U 3425 3426 // Field: [2:2] falign 3427 // 3428 // Ignore in accept list context 3429 #define PBE_BLE5_RAM_FL2INFO3_FALIGN 0x0004U 3430 #define PBE_BLE5_RAM_FL2INFO3_FALIGN_M 0x0004U 3431 #define PBE_BLE5_RAM_FL2INFO3_FALIGN_S 2U 3432 #define PBE_BLE5_RAM_FL2INFO3_FALIGN_NIGN 0x0000U 3433 #define PBE_BLE5_RAM_FL2INFO3_FALIGN_IGN 0x0004U 3434 3435 // Field: [1:1] type 3436 // 3437 // Address type 3438 #define PBE_BLE5_RAM_FL2INFO3_TYPE 0x0002U 3439 #define PBE_BLE5_RAM_FL2INFO3_TYPE_M 0x0002U 3440 #define PBE_BLE5_RAM_FL2INFO3_TYPE_S 1U 3441 #define PBE_BLE5_RAM_FL2INFO3_TYPE_PUBLIC 0x0000U 3442 #define PBE_BLE5_RAM_FL2INFO3_TYPE_RANDOM 0x0002U 3443 3444 // Field: [0:0] en 3445 // 3446 // Enable 3447 #define PBE_BLE5_RAM_FL2INFO3_EN 0x0001U 3448 #define PBE_BLE5_RAM_FL2INFO3_EN_M 0x0001U 3449 #define PBE_BLE5_RAM_FL2INFO3_EN_S 0U 3450 #define PBE_BLE5_RAM_FL2INFO3_EN_DIS 0x0000U 3451 #define PBE_BLE5_RAM_FL2INFO3_EN_EN 0x0001U 3452 3453 //****************************************************************************** 3454 // Register: FL2ADRL3 3455 //****************************************************************************** 3456 // Field: [15:0] val 3457 // 3458 // bits 15:0 of address 3459 #define PBE_BLE5_RAM_FL2ADRL3_VAL_W 16U 3460 #define PBE_BLE5_RAM_FL2ADRL3_VAL_M 0xFFFFU 3461 #define PBE_BLE5_RAM_FL2ADRL3_VAL_S 0U 3462 3463 //****************************************************************************** 3464 // Register: FL2ADRM3 3465 //****************************************************************************** 3466 // Field: [15:0] val 3467 // 3468 // bits 31:16 of address 3469 #define PBE_BLE5_RAM_FL2ADRM3_VAL_W 16U 3470 #define PBE_BLE5_RAM_FL2ADRM3_VAL_M 0xFFFFU 3471 #define PBE_BLE5_RAM_FL2ADRM3_VAL_S 0U 3472 3473 //****************************************************************************** 3474 // Register: FL2ADRH3 3475 //****************************************************************************** 3476 // Field: [15:0] val 3477 // 3478 // bits 47:32 of address 3479 #define PBE_BLE5_RAM_FL2ADRH3_VAL_W 16U 3480 #define PBE_BLE5_RAM_FL2ADRH3_VAL_M 0xFFFFU 3481 #define PBE_BLE5_RAM_FL2ADRH3_VAL_S 0U 3482 3483 //****************************************************************************** 3484 // Register: FL2INFO4 3485 //****************************************************************************** 3486 // Field: [15:15] matchtmp 3487 // 3488 // Temporary variable used in matching, ignore from CM0 3489 #define PBE_BLE5_RAM_FL2INFO4_MATCHTMP 0x8000U 3490 #define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_M 0x8000U 3491 #define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_S 15U 3492 #define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_NOMATCH 0x0000U 3493 #define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_MATCH 0x8000U 3494 3495 // Field: [14:4] reserved 3496 // 3497 // Reserved for future use 3498 #define PBE_BLE5_RAM_FL2INFO4_RESERVED_W 11U 3499 #define PBE_BLE5_RAM_FL2INFO4_RESERVED_M 0x7FF0U 3500 #define PBE_BLE5_RAM_FL2INFO4_RESERVED_S 4U 3501 3502 // Field: [3:3] privign 3503 // 3504 // Ignore control for privacy 3505 #define PBE_BLE5_RAM_FL2INFO4_PRIVIGN 0x0008U 3506 #define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_M 0x0008U 3507 #define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_S 3U 3508 #define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_NIGN 0x0000U 3509 #define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_IGN 0x0008U 3510 3511 // Field: [2:2] falign 3512 // 3513 // Ignore in accept list context 3514 #define PBE_BLE5_RAM_FL2INFO4_FALIGN 0x0004U 3515 #define PBE_BLE5_RAM_FL2INFO4_FALIGN_M 0x0004U 3516 #define PBE_BLE5_RAM_FL2INFO4_FALIGN_S 2U 3517 #define PBE_BLE5_RAM_FL2INFO4_FALIGN_NIGN 0x0000U 3518 #define PBE_BLE5_RAM_FL2INFO4_FALIGN_IGN 0x0004U 3519 3520 // Field: [1:1] type 3521 // 3522 // Address type 3523 #define PBE_BLE5_RAM_FL2INFO4_TYPE 0x0002U 3524 #define PBE_BLE5_RAM_FL2INFO4_TYPE_M 0x0002U 3525 #define PBE_BLE5_RAM_FL2INFO4_TYPE_S 1U 3526 #define PBE_BLE5_RAM_FL2INFO4_TYPE_PUBLIC 0x0000U 3527 #define PBE_BLE5_RAM_FL2INFO4_TYPE_RANDOM 0x0002U 3528 3529 // Field: [0:0] en 3530 // 3531 // Enable 3532 #define PBE_BLE5_RAM_FL2INFO4_EN 0x0001U 3533 #define PBE_BLE5_RAM_FL2INFO4_EN_M 0x0001U 3534 #define PBE_BLE5_RAM_FL2INFO4_EN_S 0U 3535 #define PBE_BLE5_RAM_FL2INFO4_EN_DIS 0x0000U 3536 #define PBE_BLE5_RAM_FL2INFO4_EN_EN 0x0001U 3537 3538 //****************************************************************************** 3539 // Register: FL2ADRL4 3540 //****************************************************************************** 3541 // Field: [15:0] val 3542 // 3543 // bits 15:0 of address 3544 #define PBE_BLE5_RAM_FL2ADRL4_VAL_W 16U 3545 #define PBE_BLE5_RAM_FL2ADRL4_VAL_M 0xFFFFU 3546 #define PBE_BLE5_RAM_FL2ADRL4_VAL_S 0U 3547 3548 //****************************************************************************** 3549 // Register: FL2ADRM4 3550 //****************************************************************************** 3551 // Field: [15:0] val 3552 // 3553 // bits 31:16 of address 3554 #define PBE_BLE5_RAM_FL2ADRM4_VAL_W 16U 3555 #define PBE_BLE5_RAM_FL2ADRM4_VAL_M 0xFFFFU 3556 #define PBE_BLE5_RAM_FL2ADRM4_VAL_S 0U 3557 3558 //****************************************************************************** 3559 // Register: FL2ADRH4 3560 //****************************************************************************** 3561 // Field: [15:0] val 3562 // 3563 // bits 47:32 of address 3564 #define PBE_BLE5_RAM_FL2ADRH4_VAL_W 16U 3565 #define PBE_BLE5_RAM_FL2ADRH4_VAL_M 0xFFFFU 3566 #define PBE_BLE5_RAM_FL2ADRH4_VAL_S 0U 3567 3568 //****************************************************************************** 3569 // Register: FL2INFO5 3570 //****************************************************************************** 3571 // Field: [15:15] matchtmp 3572 // 3573 // Temporary variable used in matching, ignore from CM0 3574 #define PBE_BLE5_RAM_FL2INFO5_MATCHTMP 0x8000U 3575 #define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_M 0x8000U 3576 #define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_S 15U 3577 #define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_NOMATCH 0x0000U 3578 #define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_MATCH 0x8000U 3579 3580 // Field: [14:4] reserved 3581 // 3582 // Reserved for future use 3583 #define PBE_BLE5_RAM_FL2INFO5_RESERVED_W 11U 3584 #define PBE_BLE5_RAM_FL2INFO5_RESERVED_M 0x7FF0U 3585 #define PBE_BLE5_RAM_FL2INFO5_RESERVED_S 4U 3586 3587 // Field: [3:3] privign 3588 // 3589 // Ignore control for privacy 3590 #define PBE_BLE5_RAM_FL2INFO5_PRIVIGN 0x0008U 3591 #define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_M 0x0008U 3592 #define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_S 3U 3593 #define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_NIGN 0x0000U 3594 #define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_IGN 0x0008U 3595 3596 // Field: [2:2] falign 3597 // 3598 // Ignore in accept list context 3599 #define PBE_BLE5_RAM_FL2INFO5_FALIGN 0x0004U 3600 #define PBE_BLE5_RAM_FL2INFO5_FALIGN_M 0x0004U 3601 #define PBE_BLE5_RAM_FL2INFO5_FALIGN_S 2U 3602 #define PBE_BLE5_RAM_FL2INFO5_FALIGN_NIGN 0x0000U 3603 #define PBE_BLE5_RAM_FL2INFO5_FALIGN_IGN 0x0004U 3604 3605 // Field: [1:1] type 3606 // 3607 // Address type 3608 #define PBE_BLE5_RAM_FL2INFO5_TYPE 0x0002U 3609 #define PBE_BLE5_RAM_FL2INFO5_TYPE_M 0x0002U 3610 #define PBE_BLE5_RAM_FL2INFO5_TYPE_S 1U 3611 #define PBE_BLE5_RAM_FL2INFO5_TYPE_PUBLIC 0x0000U 3612 #define PBE_BLE5_RAM_FL2INFO5_TYPE_RANDOM 0x0002U 3613 3614 // Field: [0:0] en 3615 // 3616 // Enable 3617 #define PBE_BLE5_RAM_FL2INFO5_EN 0x0001U 3618 #define PBE_BLE5_RAM_FL2INFO5_EN_M 0x0001U 3619 #define PBE_BLE5_RAM_FL2INFO5_EN_S 0U 3620 #define PBE_BLE5_RAM_FL2INFO5_EN_DIS 0x0000U 3621 #define PBE_BLE5_RAM_FL2INFO5_EN_EN 0x0001U 3622 3623 //****************************************************************************** 3624 // Register: FL2ADRL5 3625 //****************************************************************************** 3626 // Field: [15:0] val 3627 // 3628 // bits 15:0 of address 3629 #define PBE_BLE5_RAM_FL2ADRL5_VAL_W 16U 3630 #define PBE_BLE5_RAM_FL2ADRL5_VAL_M 0xFFFFU 3631 #define PBE_BLE5_RAM_FL2ADRL5_VAL_S 0U 3632 3633 //****************************************************************************** 3634 // Register: FL2ADRM5 3635 //****************************************************************************** 3636 // Field: [15:0] val 3637 // 3638 // bits 31:16 of address 3639 #define PBE_BLE5_RAM_FL2ADRM5_VAL_W 16U 3640 #define PBE_BLE5_RAM_FL2ADRM5_VAL_M 0xFFFFU 3641 #define PBE_BLE5_RAM_FL2ADRM5_VAL_S 0U 3642 3643 //****************************************************************************** 3644 // Register: FL2ADRH5 3645 //****************************************************************************** 3646 // Field: [15:0] val 3647 // 3648 // bits 47:32 of address 3649 #define PBE_BLE5_RAM_FL2ADRH5_VAL_W 16U 3650 #define PBE_BLE5_RAM_FL2ADRH5_VAL_M 0xFFFFU 3651 #define PBE_BLE5_RAM_FL2ADRH5_VAL_S 0U 3652 3653 //****************************************************************************** 3654 // Register: FL2INFO6 3655 //****************************************************************************** 3656 // Field: [15:15] matchtmp 3657 // 3658 // Temporary variable used in matching, ignore from CM0 3659 #define PBE_BLE5_RAM_FL2INFO6_MATCHTMP 0x8000U 3660 #define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_M 0x8000U 3661 #define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_S 15U 3662 #define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_NOMATCH 0x0000U 3663 #define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_MATCH 0x8000U 3664 3665 // Field: [14:4] reserved 3666 // 3667 // Reserved for future use 3668 #define PBE_BLE5_RAM_FL2INFO6_RESERVED_W 11U 3669 #define PBE_BLE5_RAM_FL2INFO6_RESERVED_M 0x7FF0U 3670 #define PBE_BLE5_RAM_FL2INFO6_RESERVED_S 4U 3671 3672 // Field: [3:3] privign 3673 // 3674 // Ignore control for privacy 3675 #define PBE_BLE5_RAM_FL2INFO6_PRIVIGN 0x0008U 3676 #define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_M 0x0008U 3677 #define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_S 3U 3678 #define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_NIGN 0x0000U 3679 #define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_IGN 0x0008U 3680 3681 // Field: [2:2] falign 3682 // 3683 // Ignore in accept list context 3684 #define PBE_BLE5_RAM_FL2INFO6_FALIGN 0x0004U 3685 #define PBE_BLE5_RAM_FL2INFO6_FALIGN_M 0x0004U 3686 #define PBE_BLE5_RAM_FL2INFO6_FALIGN_S 2U 3687 #define PBE_BLE5_RAM_FL2INFO6_FALIGN_NIGN 0x0000U 3688 #define PBE_BLE5_RAM_FL2INFO6_FALIGN_IGN 0x0004U 3689 3690 // Field: [1:1] type 3691 // 3692 // Address type 3693 #define PBE_BLE5_RAM_FL2INFO6_TYPE 0x0002U 3694 #define PBE_BLE5_RAM_FL2INFO6_TYPE_M 0x0002U 3695 #define PBE_BLE5_RAM_FL2INFO6_TYPE_S 1U 3696 #define PBE_BLE5_RAM_FL2INFO6_TYPE_PUBLIC 0x0000U 3697 #define PBE_BLE5_RAM_FL2INFO6_TYPE_RANDOM 0x0002U 3698 3699 // Field: [0:0] en 3700 // 3701 // Enable 3702 #define PBE_BLE5_RAM_FL2INFO6_EN 0x0001U 3703 #define PBE_BLE5_RAM_FL2INFO6_EN_M 0x0001U 3704 #define PBE_BLE5_RAM_FL2INFO6_EN_S 0U 3705 #define PBE_BLE5_RAM_FL2INFO6_EN_DIS 0x0000U 3706 #define PBE_BLE5_RAM_FL2INFO6_EN_EN 0x0001U 3707 3708 //****************************************************************************** 3709 // Register: FL2ADRL6 3710 //****************************************************************************** 3711 // Field: [15:0] val 3712 // 3713 // bits 15:0 of address 3714 #define PBE_BLE5_RAM_FL2ADRL6_VAL_W 16U 3715 #define PBE_BLE5_RAM_FL2ADRL6_VAL_M 0xFFFFU 3716 #define PBE_BLE5_RAM_FL2ADRL6_VAL_S 0U 3717 3718 //****************************************************************************** 3719 // Register: FL2ADRM6 3720 //****************************************************************************** 3721 // Field: [15:0] val 3722 // 3723 // bits 31:16 of address 3724 #define PBE_BLE5_RAM_FL2ADRM6_VAL_W 16U 3725 #define PBE_BLE5_RAM_FL2ADRM6_VAL_M 0xFFFFU 3726 #define PBE_BLE5_RAM_FL2ADRM6_VAL_S 0U 3727 3728 //****************************************************************************** 3729 // Register: FL2ADRH6 3730 //****************************************************************************** 3731 // Field: [15:0] val 3732 // 3733 // bits 47:32 of address 3734 #define PBE_BLE5_RAM_FL2ADRH6_VAL_W 16U 3735 #define PBE_BLE5_RAM_FL2ADRH6_VAL_M 0xFFFFU 3736 #define PBE_BLE5_RAM_FL2ADRH6_VAL_S 0U 3737 3738 //****************************************************************************** 3739 // Register: FL2INFO7 3740 //****************************************************************************** 3741 // Field: [15:15] matchtmp 3742 // 3743 // Temporary variable used in matching, ignore from CM0 3744 #define PBE_BLE5_RAM_FL2INFO7_MATCHTMP 0x8000U 3745 #define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_M 0x8000U 3746 #define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_S 15U 3747 #define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_NOMATCH 0x0000U 3748 #define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_MATCH 0x8000U 3749 3750 // Field: [14:4] reserved 3751 // 3752 // Reserved for future use 3753 #define PBE_BLE5_RAM_FL2INFO7_RESERVED_W 11U 3754 #define PBE_BLE5_RAM_FL2INFO7_RESERVED_M 0x7FF0U 3755 #define PBE_BLE5_RAM_FL2INFO7_RESERVED_S 4U 3756 3757 // Field: [3:3] privign 3758 // 3759 // Ignore control for privacy 3760 #define PBE_BLE5_RAM_FL2INFO7_PRIVIGN 0x0008U 3761 #define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_M 0x0008U 3762 #define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_S 3U 3763 #define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_NIGN 0x0000U 3764 #define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_IGN 0x0008U 3765 3766 // Field: [2:2] falign 3767 // 3768 // Ignore in accept list context 3769 #define PBE_BLE5_RAM_FL2INFO7_FALIGN 0x0004U 3770 #define PBE_BLE5_RAM_FL2INFO7_FALIGN_M 0x0004U 3771 #define PBE_BLE5_RAM_FL2INFO7_FALIGN_S 2U 3772 #define PBE_BLE5_RAM_FL2INFO7_FALIGN_NIGN 0x0000U 3773 #define PBE_BLE5_RAM_FL2INFO7_FALIGN_IGN 0x0004U 3774 3775 // Field: [1:1] type 3776 // 3777 // Address type 3778 #define PBE_BLE5_RAM_FL2INFO7_TYPE 0x0002U 3779 #define PBE_BLE5_RAM_FL2INFO7_TYPE_M 0x0002U 3780 #define PBE_BLE5_RAM_FL2INFO7_TYPE_S 1U 3781 #define PBE_BLE5_RAM_FL2INFO7_TYPE_PUBLIC 0x0000U 3782 #define PBE_BLE5_RAM_FL2INFO7_TYPE_RANDOM 0x0002U 3783 3784 // Field: [0:0] en 3785 // 3786 // Enable 3787 #define PBE_BLE5_RAM_FL2INFO7_EN 0x0001U 3788 #define PBE_BLE5_RAM_FL2INFO7_EN_M 0x0001U 3789 #define PBE_BLE5_RAM_FL2INFO7_EN_S 0U 3790 #define PBE_BLE5_RAM_FL2INFO7_EN_DIS 0x0000U 3791 #define PBE_BLE5_RAM_FL2INFO7_EN_EN 0x0001U 3792 3793 //****************************************************************************** 3794 // Register: FL2ADRL7 3795 //****************************************************************************** 3796 // Field: [15:0] val 3797 // 3798 // bits 15:0 of address 3799 #define PBE_BLE5_RAM_FL2ADRL7_VAL_W 16U 3800 #define PBE_BLE5_RAM_FL2ADRL7_VAL_M 0xFFFFU 3801 #define PBE_BLE5_RAM_FL2ADRL7_VAL_S 0U 3802 3803 //****************************************************************************** 3804 // Register: FL2ADRM7 3805 //****************************************************************************** 3806 // Field: [15:0] val 3807 // 3808 // bits 31:16 of address 3809 #define PBE_BLE5_RAM_FL2ADRM7_VAL_W 16U 3810 #define PBE_BLE5_RAM_FL2ADRM7_VAL_M 0xFFFFU 3811 #define PBE_BLE5_RAM_FL2ADRM7_VAL_S 0U 3812 3813 //****************************************************************************** 3814 // Register: FL2ADRH7 3815 //****************************************************************************** 3816 // Field: [15:0] val 3817 // 3818 // bits 47:32 of address 3819 #define PBE_BLE5_RAM_FL2ADRH7_VAL_W 16U 3820 #define PBE_BLE5_RAM_FL2ADRH7_VAL_M 0xFFFFU 3821 #define PBE_BLE5_RAM_FL2ADRH7_VAL_S 0U 3822 3823 //****************************************************************************** 3824 // Register: FL2INFO8 3825 //****************************************************************************** 3826 // Field: [15:15] matchtmp 3827 // 3828 // Temporary variable used in matching, ignore from CM0 3829 #define PBE_BLE5_RAM_FL2INFO8_MATCHTMP 0x8000U 3830 #define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_M 0x8000U 3831 #define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_S 15U 3832 #define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_NOMATCH 0x0000U 3833 #define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_MATCH 0x8000U 3834 3835 // Field: [14:4] reserved 3836 // 3837 // Reserved for future use 3838 #define PBE_BLE5_RAM_FL2INFO8_RESERVED_W 11U 3839 #define PBE_BLE5_RAM_FL2INFO8_RESERVED_M 0x7FF0U 3840 #define PBE_BLE5_RAM_FL2INFO8_RESERVED_S 4U 3841 3842 // Field: [3:3] privign 3843 // 3844 // Ignore control for privacy 3845 #define PBE_BLE5_RAM_FL2INFO8_PRIVIGN 0x0008U 3846 #define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_M 0x0008U 3847 #define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_S 3U 3848 #define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_NIGN 0x0000U 3849 #define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_IGN 0x0008U 3850 3851 // Field: [2:2] falign 3852 // 3853 // Ignore in accept list context 3854 #define PBE_BLE5_RAM_FL2INFO8_FALIGN 0x0004U 3855 #define PBE_BLE5_RAM_FL2INFO8_FALIGN_M 0x0004U 3856 #define PBE_BLE5_RAM_FL2INFO8_FALIGN_S 2U 3857 #define PBE_BLE5_RAM_FL2INFO8_FALIGN_NIGN 0x0000U 3858 #define PBE_BLE5_RAM_FL2INFO8_FALIGN_IGN 0x0004U 3859 3860 // Field: [1:1] type 3861 // 3862 // Address type 3863 #define PBE_BLE5_RAM_FL2INFO8_TYPE 0x0002U 3864 #define PBE_BLE5_RAM_FL2INFO8_TYPE_M 0x0002U 3865 #define PBE_BLE5_RAM_FL2INFO8_TYPE_S 1U 3866 #define PBE_BLE5_RAM_FL2INFO8_TYPE_PUBLIC 0x0000U 3867 #define PBE_BLE5_RAM_FL2INFO8_TYPE_RANDOM 0x0002U 3868 3869 // Field: [0:0] en 3870 // 3871 // Enable 3872 #define PBE_BLE5_RAM_FL2INFO8_EN 0x0001U 3873 #define PBE_BLE5_RAM_FL2INFO8_EN_M 0x0001U 3874 #define PBE_BLE5_RAM_FL2INFO8_EN_S 0U 3875 #define PBE_BLE5_RAM_FL2INFO8_EN_DIS 0x0000U 3876 #define PBE_BLE5_RAM_FL2INFO8_EN_EN 0x0001U 3877 3878 //****************************************************************************** 3879 // Register: FL2ADRL8 3880 //****************************************************************************** 3881 // Field: [15:0] val 3882 // 3883 // bits 15:0 of address 3884 #define PBE_BLE5_RAM_FL2ADRL8_VAL_W 16U 3885 #define PBE_BLE5_RAM_FL2ADRL8_VAL_M 0xFFFFU 3886 #define PBE_BLE5_RAM_FL2ADRL8_VAL_S 0U 3887 3888 //****************************************************************************** 3889 // Register: FL2ADRM8 3890 //****************************************************************************** 3891 // Field: [15:0] val 3892 // 3893 // bits 31:16 of address 3894 #define PBE_BLE5_RAM_FL2ADRM8_VAL_W 16U 3895 #define PBE_BLE5_RAM_FL2ADRM8_VAL_M 0xFFFFU 3896 #define PBE_BLE5_RAM_FL2ADRM8_VAL_S 0U 3897 3898 //****************************************************************************** 3899 // Register: FL2ADRH8 3900 //****************************************************************************** 3901 // Field: [15:0] val 3902 // 3903 // bits 47:32 of address 3904 #define PBE_BLE5_RAM_FL2ADRH8_VAL_W 16U 3905 #define PBE_BLE5_RAM_FL2ADRH8_VAL_M 0xFFFFU 3906 #define PBE_BLE5_RAM_FL2ADRH8_VAL_S 0U 3907 3908 //****************************************************************************** 3909 // Register: FL2INFO9 3910 //****************************************************************************** 3911 // Field: [15:15] matchtmp 3912 // 3913 // Temporary variable used in matching, ignore from CM0 3914 #define PBE_BLE5_RAM_FL2INFO9_MATCHTMP 0x8000U 3915 #define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_M 0x8000U 3916 #define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_S 15U 3917 #define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_NOMATCH 0x0000U 3918 #define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_MATCH 0x8000U 3919 3920 // Field: [14:4] reserved 3921 // 3922 // Reserved for future use 3923 #define PBE_BLE5_RAM_FL2INFO9_RESERVED_W 11U 3924 #define PBE_BLE5_RAM_FL2INFO9_RESERVED_M 0x7FF0U 3925 #define PBE_BLE5_RAM_FL2INFO9_RESERVED_S 4U 3926 3927 // Field: [3:3] privign 3928 // 3929 // Ignore control for privacy 3930 #define PBE_BLE5_RAM_FL2INFO9_PRIVIGN 0x0008U 3931 #define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_M 0x0008U 3932 #define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_S 3U 3933 #define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_NIGN 0x0000U 3934 #define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_IGN 0x0008U 3935 3936 // Field: [2:2] falign 3937 // 3938 // Ignore in accept list context 3939 #define PBE_BLE5_RAM_FL2INFO9_FALIGN 0x0004U 3940 #define PBE_BLE5_RAM_FL2INFO9_FALIGN_M 0x0004U 3941 #define PBE_BLE5_RAM_FL2INFO9_FALIGN_S 2U 3942 #define PBE_BLE5_RAM_FL2INFO9_FALIGN_NIGN 0x0000U 3943 #define PBE_BLE5_RAM_FL2INFO9_FALIGN_IGN 0x0004U 3944 3945 // Field: [1:1] type 3946 // 3947 // Address type 3948 #define PBE_BLE5_RAM_FL2INFO9_TYPE 0x0002U 3949 #define PBE_BLE5_RAM_FL2INFO9_TYPE_M 0x0002U 3950 #define PBE_BLE5_RAM_FL2INFO9_TYPE_S 1U 3951 #define PBE_BLE5_RAM_FL2INFO9_TYPE_PUBLIC 0x0000U 3952 #define PBE_BLE5_RAM_FL2INFO9_TYPE_RANDOM 0x0002U 3953 3954 // Field: [0:0] en 3955 // 3956 // Enable 3957 #define PBE_BLE5_RAM_FL2INFO9_EN 0x0001U 3958 #define PBE_BLE5_RAM_FL2INFO9_EN_M 0x0001U 3959 #define PBE_BLE5_RAM_FL2INFO9_EN_S 0U 3960 #define PBE_BLE5_RAM_FL2INFO9_EN_DIS 0x0000U 3961 #define PBE_BLE5_RAM_FL2INFO9_EN_EN 0x0001U 3962 3963 //****************************************************************************** 3964 // Register: FL2ADRL9 3965 //****************************************************************************** 3966 // Field: [15:0] val 3967 // 3968 // bits 15:0 of address 3969 #define PBE_BLE5_RAM_FL2ADRL9_VAL_W 16U 3970 #define PBE_BLE5_RAM_FL2ADRL9_VAL_M 0xFFFFU 3971 #define PBE_BLE5_RAM_FL2ADRL9_VAL_S 0U 3972 3973 //****************************************************************************** 3974 // Register: FL2ADRM9 3975 //****************************************************************************** 3976 // Field: [15:0] val 3977 // 3978 // bits 31:16 of address 3979 #define PBE_BLE5_RAM_FL2ADRM9_VAL_W 16U 3980 #define PBE_BLE5_RAM_FL2ADRM9_VAL_M 0xFFFFU 3981 #define PBE_BLE5_RAM_FL2ADRM9_VAL_S 0U 3982 3983 //****************************************************************************** 3984 // Register: FL2ADRH9 3985 //****************************************************************************** 3986 // Field: [15:0] val 3987 // 3988 // bits 47:32 of address 3989 #define PBE_BLE5_RAM_FL2ADRH9_VAL_W 16U 3990 #define PBE_BLE5_RAM_FL2ADRH9_VAL_M 0xFFFFU 3991 #define PBE_BLE5_RAM_FL2ADRH9_VAL_S 0U 3992 3993 //****************************************************************************** 3994 // Register: FL2INFO10 3995 //****************************************************************************** 3996 // Field: [15:15] matchtmp 3997 // 3998 // Temporary variable used in matching, ignore from CM0 3999 #define PBE_BLE5_RAM_FL2INFO10_MATCHTMP 0x8000U 4000 #define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_M 0x8000U 4001 #define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_S 15U 4002 #define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_NOMATCH 0x0000U 4003 #define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_MATCH 0x8000U 4004 4005 // Field: [14:4] reserved 4006 // 4007 // Reserved for future use 4008 #define PBE_BLE5_RAM_FL2INFO10_RESERVED_W 11U 4009 #define PBE_BLE5_RAM_FL2INFO10_RESERVED_M 0x7FF0U 4010 #define PBE_BLE5_RAM_FL2INFO10_RESERVED_S 4U 4011 4012 // Field: [3:3] privign 4013 // 4014 // Ignore control for privacy 4015 #define PBE_BLE5_RAM_FL2INFO10_PRIVIGN 0x0008U 4016 #define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_M 0x0008U 4017 #define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_S 3U 4018 #define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_NIGN 0x0000U 4019 #define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_IGN 0x0008U 4020 4021 // Field: [2:2] falign 4022 // 4023 // Ignore in accept list context 4024 #define PBE_BLE5_RAM_FL2INFO10_FALIGN 0x0004U 4025 #define PBE_BLE5_RAM_FL2INFO10_FALIGN_M 0x0004U 4026 #define PBE_BLE5_RAM_FL2INFO10_FALIGN_S 2U 4027 #define PBE_BLE5_RAM_FL2INFO10_FALIGN_NIGN 0x0000U 4028 #define PBE_BLE5_RAM_FL2INFO10_FALIGN_IGN 0x0004U 4029 4030 // Field: [1:1] type 4031 // 4032 // Address type 4033 #define PBE_BLE5_RAM_FL2INFO10_TYPE 0x0002U 4034 #define PBE_BLE5_RAM_FL2INFO10_TYPE_M 0x0002U 4035 #define PBE_BLE5_RAM_FL2INFO10_TYPE_S 1U 4036 #define PBE_BLE5_RAM_FL2INFO10_TYPE_PUBLIC 0x0000U 4037 #define PBE_BLE5_RAM_FL2INFO10_TYPE_RANDOM 0x0002U 4038 4039 // Field: [0:0] en 4040 // 4041 // Enable 4042 #define PBE_BLE5_RAM_FL2INFO10_EN 0x0001U 4043 #define PBE_BLE5_RAM_FL2INFO10_EN_M 0x0001U 4044 #define PBE_BLE5_RAM_FL2INFO10_EN_S 0U 4045 #define PBE_BLE5_RAM_FL2INFO10_EN_DIS 0x0000U 4046 #define PBE_BLE5_RAM_FL2INFO10_EN_EN 0x0001U 4047 4048 //****************************************************************************** 4049 // Register: FL2ADRL10 4050 //****************************************************************************** 4051 // Field: [15:0] val 4052 // 4053 // bits 15:0 of address 4054 #define PBE_BLE5_RAM_FL2ADRL10_VAL_W 16U 4055 #define PBE_BLE5_RAM_FL2ADRL10_VAL_M 0xFFFFU 4056 #define PBE_BLE5_RAM_FL2ADRL10_VAL_S 0U 4057 4058 //****************************************************************************** 4059 // Register: FL2ADRM10 4060 //****************************************************************************** 4061 // Field: [15:0] val 4062 // 4063 // bits 31:16 of address 4064 #define PBE_BLE5_RAM_FL2ADRM10_VAL_W 16U 4065 #define PBE_BLE5_RAM_FL2ADRM10_VAL_M 0xFFFFU 4066 #define PBE_BLE5_RAM_FL2ADRM10_VAL_S 0U 4067 4068 //****************************************************************************** 4069 // Register: FL2ADRH10 4070 //****************************************************************************** 4071 // Field: [15:0] val 4072 // 4073 // bits 47:32 of address 4074 #define PBE_BLE5_RAM_FL2ADRH10_VAL_W 16U 4075 #define PBE_BLE5_RAM_FL2ADRH10_VAL_M 0xFFFFU 4076 #define PBE_BLE5_RAM_FL2ADRH10_VAL_S 0U 4077 4078 //****************************************************************************** 4079 // Register: FL2INFO11 4080 //****************************************************************************** 4081 // Field: [15:15] matchtmp 4082 // 4083 // Temporary variable used in matching, ignore from CM0 4084 #define PBE_BLE5_RAM_FL2INFO11_MATCHTMP 0x8000U 4085 #define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_M 0x8000U 4086 #define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_S 15U 4087 #define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_NOMATCH 0x0000U 4088 #define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_MATCH 0x8000U 4089 4090 // Field: [14:4] reserved 4091 // 4092 // Reserved for future use 4093 #define PBE_BLE5_RAM_FL2INFO11_RESERVED_W 11U 4094 #define PBE_BLE5_RAM_FL2INFO11_RESERVED_M 0x7FF0U 4095 #define PBE_BLE5_RAM_FL2INFO11_RESERVED_S 4U 4096 4097 // Field: [3:3] privign 4098 // 4099 // Ignore control for privacy 4100 #define PBE_BLE5_RAM_FL2INFO11_PRIVIGN 0x0008U 4101 #define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_M 0x0008U 4102 #define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_S 3U 4103 #define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_NIGN 0x0000U 4104 #define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_IGN 0x0008U 4105 4106 // Field: [2:2] falign 4107 // 4108 // Ignore in accept list context 4109 #define PBE_BLE5_RAM_FL2INFO11_FALIGN 0x0004U 4110 #define PBE_BLE5_RAM_FL2INFO11_FALIGN_M 0x0004U 4111 #define PBE_BLE5_RAM_FL2INFO11_FALIGN_S 2U 4112 #define PBE_BLE5_RAM_FL2INFO11_FALIGN_NIGN 0x0000U 4113 #define PBE_BLE5_RAM_FL2INFO11_FALIGN_IGN 0x0004U 4114 4115 // Field: [1:1] type 4116 // 4117 // Address type 4118 #define PBE_BLE5_RAM_FL2INFO11_TYPE 0x0002U 4119 #define PBE_BLE5_RAM_FL2INFO11_TYPE_M 0x0002U 4120 #define PBE_BLE5_RAM_FL2INFO11_TYPE_S 1U 4121 #define PBE_BLE5_RAM_FL2INFO11_TYPE_PUBLIC 0x0000U 4122 #define PBE_BLE5_RAM_FL2INFO11_TYPE_RANDOM 0x0002U 4123 4124 // Field: [0:0] en 4125 // 4126 // Enable 4127 #define PBE_BLE5_RAM_FL2INFO11_EN 0x0001U 4128 #define PBE_BLE5_RAM_FL2INFO11_EN_M 0x0001U 4129 #define PBE_BLE5_RAM_FL2INFO11_EN_S 0U 4130 #define PBE_BLE5_RAM_FL2INFO11_EN_DIS 0x0000U 4131 #define PBE_BLE5_RAM_FL2INFO11_EN_EN 0x0001U 4132 4133 //****************************************************************************** 4134 // Register: FL2ADRL11 4135 //****************************************************************************** 4136 // Field: [15:0] val 4137 // 4138 // bits 15:0 of address 4139 #define PBE_BLE5_RAM_FL2ADRL11_VAL_W 16U 4140 #define PBE_BLE5_RAM_FL2ADRL11_VAL_M 0xFFFFU 4141 #define PBE_BLE5_RAM_FL2ADRL11_VAL_S 0U 4142 4143 //****************************************************************************** 4144 // Register: FL2ADRM11 4145 //****************************************************************************** 4146 // Field: [15:0] val 4147 // 4148 // bits 31:16 of address 4149 #define PBE_BLE5_RAM_FL2ADRM11_VAL_W 16U 4150 #define PBE_BLE5_RAM_FL2ADRM11_VAL_M 0xFFFFU 4151 #define PBE_BLE5_RAM_FL2ADRM11_VAL_S 0U 4152 4153 //****************************************************************************** 4154 // Register: FL2ADRH11 4155 //****************************************************************************** 4156 // Field: [15:0] val 4157 // 4158 // bits 47:32 of address 4159 #define PBE_BLE5_RAM_FL2ADRH11_VAL_W 16U 4160 #define PBE_BLE5_RAM_FL2ADRH11_VAL_M 0xFFFFU 4161 #define PBE_BLE5_RAM_FL2ADRH11_VAL_S 0U 4162 4163 //****************************************************************************** 4164 // Register: FL2INFO12 4165 //****************************************************************************** 4166 // Field: [15:15] matchtmp 4167 // 4168 // Temporary variable used in matching, ignore from CM0 4169 #define PBE_BLE5_RAM_FL2INFO12_MATCHTMP 0x8000U 4170 #define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_M 0x8000U 4171 #define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_S 15U 4172 #define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_NOMATCH 0x0000U 4173 #define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_MATCH 0x8000U 4174 4175 // Field: [14:4] reserved 4176 // 4177 // Reserved for future use 4178 #define PBE_BLE5_RAM_FL2INFO12_RESERVED_W 11U 4179 #define PBE_BLE5_RAM_FL2INFO12_RESERVED_M 0x7FF0U 4180 #define PBE_BLE5_RAM_FL2INFO12_RESERVED_S 4U 4181 4182 // Field: [3:3] privign 4183 // 4184 // Ignore control for privacy 4185 #define PBE_BLE5_RAM_FL2INFO12_PRIVIGN 0x0008U 4186 #define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_M 0x0008U 4187 #define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_S 3U 4188 #define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_NIGN 0x0000U 4189 #define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_IGN 0x0008U 4190 4191 // Field: [2:2] falign 4192 // 4193 // Ignore in accept list context 4194 #define PBE_BLE5_RAM_FL2INFO12_FALIGN 0x0004U 4195 #define PBE_BLE5_RAM_FL2INFO12_FALIGN_M 0x0004U 4196 #define PBE_BLE5_RAM_FL2INFO12_FALIGN_S 2U 4197 #define PBE_BLE5_RAM_FL2INFO12_FALIGN_NIGN 0x0000U 4198 #define PBE_BLE5_RAM_FL2INFO12_FALIGN_IGN 0x0004U 4199 4200 // Field: [1:1] type 4201 // 4202 // Address type 4203 #define PBE_BLE5_RAM_FL2INFO12_TYPE 0x0002U 4204 #define PBE_BLE5_RAM_FL2INFO12_TYPE_M 0x0002U 4205 #define PBE_BLE5_RAM_FL2INFO12_TYPE_S 1U 4206 #define PBE_BLE5_RAM_FL2INFO12_TYPE_PUBLIC 0x0000U 4207 #define PBE_BLE5_RAM_FL2INFO12_TYPE_RANDOM 0x0002U 4208 4209 // Field: [0:0] en 4210 // 4211 // Enable 4212 #define PBE_BLE5_RAM_FL2INFO12_EN 0x0001U 4213 #define PBE_BLE5_RAM_FL2INFO12_EN_M 0x0001U 4214 #define PBE_BLE5_RAM_FL2INFO12_EN_S 0U 4215 #define PBE_BLE5_RAM_FL2INFO12_EN_DIS 0x0000U 4216 #define PBE_BLE5_RAM_FL2INFO12_EN_EN 0x0001U 4217 4218 //****************************************************************************** 4219 // Register: FL2ADRL12 4220 //****************************************************************************** 4221 // Field: [15:0] val 4222 // 4223 // bits 15:0 of address 4224 #define PBE_BLE5_RAM_FL2ADRL12_VAL_W 16U 4225 #define PBE_BLE5_RAM_FL2ADRL12_VAL_M 0xFFFFU 4226 #define PBE_BLE5_RAM_FL2ADRL12_VAL_S 0U 4227 4228 //****************************************************************************** 4229 // Register: FL2ADRM12 4230 //****************************************************************************** 4231 // Field: [15:0] val 4232 // 4233 // bits 31:16 of address 4234 #define PBE_BLE5_RAM_FL2ADRM12_VAL_W 16U 4235 #define PBE_BLE5_RAM_FL2ADRM12_VAL_M 0xFFFFU 4236 #define PBE_BLE5_RAM_FL2ADRM12_VAL_S 0U 4237 4238 //****************************************************************************** 4239 // Register: FL2ADRH12 4240 //****************************************************************************** 4241 // Field: [15:0] val 4242 // 4243 // bits 47:32 of address 4244 #define PBE_BLE5_RAM_FL2ADRH12_VAL_W 16U 4245 #define PBE_BLE5_RAM_FL2ADRH12_VAL_M 0xFFFFU 4246 #define PBE_BLE5_RAM_FL2ADRH12_VAL_S 0U 4247 4248 //****************************************************************************** 4249 // Register: FL2INFO13 4250 //****************************************************************************** 4251 // Field: [15:15] matchtmp 4252 // 4253 // Temporary variable used in matching, ignore from CM0 4254 #define PBE_BLE5_RAM_FL2INFO13_MATCHTMP 0x8000U 4255 #define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_M 0x8000U 4256 #define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_S 15U 4257 #define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_NOMATCH 0x0000U 4258 #define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_MATCH 0x8000U 4259 4260 // Field: [14:4] reserved 4261 // 4262 // Reserved for future use 4263 #define PBE_BLE5_RAM_FL2INFO13_RESERVED_W 11U 4264 #define PBE_BLE5_RAM_FL2INFO13_RESERVED_M 0x7FF0U 4265 #define PBE_BLE5_RAM_FL2INFO13_RESERVED_S 4U 4266 4267 // Field: [3:3] privign 4268 // 4269 // Ignore control for privacy 4270 #define PBE_BLE5_RAM_FL2INFO13_PRIVIGN 0x0008U 4271 #define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_M 0x0008U 4272 #define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_S 3U 4273 #define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_NIGN 0x0000U 4274 #define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_IGN 0x0008U 4275 4276 // Field: [2:2] falign 4277 // 4278 // Ignore in accept list context 4279 #define PBE_BLE5_RAM_FL2INFO13_FALIGN 0x0004U 4280 #define PBE_BLE5_RAM_FL2INFO13_FALIGN_M 0x0004U 4281 #define PBE_BLE5_RAM_FL2INFO13_FALIGN_S 2U 4282 #define PBE_BLE5_RAM_FL2INFO13_FALIGN_NIGN 0x0000U 4283 #define PBE_BLE5_RAM_FL2INFO13_FALIGN_IGN 0x0004U 4284 4285 // Field: [1:1] type 4286 // 4287 // Address type 4288 #define PBE_BLE5_RAM_FL2INFO13_TYPE 0x0002U 4289 #define PBE_BLE5_RAM_FL2INFO13_TYPE_M 0x0002U 4290 #define PBE_BLE5_RAM_FL2INFO13_TYPE_S 1U 4291 #define PBE_BLE5_RAM_FL2INFO13_TYPE_PUBLIC 0x0000U 4292 #define PBE_BLE5_RAM_FL2INFO13_TYPE_RANDOM 0x0002U 4293 4294 // Field: [0:0] en 4295 // 4296 // Enable 4297 #define PBE_BLE5_RAM_FL2INFO13_EN 0x0001U 4298 #define PBE_BLE5_RAM_FL2INFO13_EN_M 0x0001U 4299 #define PBE_BLE5_RAM_FL2INFO13_EN_S 0U 4300 #define PBE_BLE5_RAM_FL2INFO13_EN_DIS 0x0000U 4301 #define PBE_BLE5_RAM_FL2INFO13_EN_EN 0x0001U 4302 4303 //****************************************************************************** 4304 // Register: FL2ADRL13 4305 //****************************************************************************** 4306 // Field: [15:0] val 4307 // 4308 // bits 15:0 of address 4309 #define PBE_BLE5_RAM_FL2ADRL13_VAL_W 16U 4310 #define PBE_BLE5_RAM_FL2ADRL13_VAL_M 0xFFFFU 4311 #define PBE_BLE5_RAM_FL2ADRL13_VAL_S 0U 4312 4313 //****************************************************************************** 4314 // Register: FL2ADRM13 4315 //****************************************************************************** 4316 // Field: [15:0] val 4317 // 4318 // bits 31:16 of address 4319 #define PBE_BLE5_RAM_FL2ADRM13_VAL_W 16U 4320 #define PBE_BLE5_RAM_FL2ADRM13_VAL_M 0xFFFFU 4321 #define PBE_BLE5_RAM_FL2ADRM13_VAL_S 0U 4322 4323 //****************************************************************************** 4324 // Register: FL2ADRH13 4325 //****************************************************************************** 4326 // Field: [15:0] val 4327 // 4328 // bits 47:32 of address 4329 #define PBE_BLE5_RAM_FL2ADRH13_VAL_W 16U 4330 #define PBE_BLE5_RAM_FL2ADRH13_VAL_M 0xFFFFU 4331 #define PBE_BLE5_RAM_FL2ADRH13_VAL_S 0U 4332 4333 //****************************************************************************** 4334 // Register: FL2INFO14 4335 //****************************************************************************** 4336 // Field: [15:15] matchtmp 4337 // 4338 // Temporary variable used in matching, ignore from CM0 4339 #define PBE_BLE5_RAM_FL2INFO14_MATCHTMP 0x8000U 4340 #define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_M 0x8000U 4341 #define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_S 15U 4342 #define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_NOMATCH 0x0000U 4343 #define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_MATCH 0x8000U 4344 4345 // Field: [14:4] reserved 4346 // 4347 // Reserved for future use 4348 #define PBE_BLE5_RAM_FL2INFO14_RESERVED_W 11U 4349 #define PBE_BLE5_RAM_FL2INFO14_RESERVED_M 0x7FF0U 4350 #define PBE_BLE5_RAM_FL2INFO14_RESERVED_S 4U 4351 4352 // Field: [3:3] privign 4353 // 4354 // Ignore control for privacy 4355 #define PBE_BLE5_RAM_FL2INFO14_PRIVIGN 0x0008U 4356 #define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_M 0x0008U 4357 #define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_S 3U 4358 #define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_NIGN 0x0000U 4359 #define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_IGN 0x0008U 4360 4361 // Field: [2:2] falign 4362 // 4363 // Ignore in accept list context 4364 #define PBE_BLE5_RAM_FL2INFO14_FALIGN 0x0004U 4365 #define PBE_BLE5_RAM_FL2INFO14_FALIGN_M 0x0004U 4366 #define PBE_BLE5_RAM_FL2INFO14_FALIGN_S 2U 4367 #define PBE_BLE5_RAM_FL2INFO14_FALIGN_NIGN 0x0000U 4368 #define PBE_BLE5_RAM_FL2INFO14_FALIGN_IGN 0x0004U 4369 4370 // Field: [1:1] type 4371 // 4372 // Address type 4373 #define PBE_BLE5_RAM_FL2INFO14_TYPE 0x0002U 4374 #define PBE_BLE5_RAM_FL2INFO14_TYPE_M 0x0002U 4375 #define PBE_BLE5_RAM_FL2INFO14_TYPE_S 1U 4376 #define PBE_BLE5_RAM_FL2INFO14_TYPE_PUBLIC 0x0000U 4377 #define PBE_BLE5_RAM_FL2INFO14_TYPE_RANDOM 0x0002U 4378 4379 // Field: [0:0] en 4380 // 4381 // Enable 4382 #define PBE_BLE5_RAM_FL2INFO14_EN 0x0001U 4383 #define PBE_BLE5_RAM_FL2INFO14_EN_M 0x0001U 4384 #define PBE_BLE5_RAM_FL2INFO14_EN_S 0U 4385 #define PBE_BLE5_RAM_FL2INFO14_EN_DIS 0x0000U 4386 #define PBE_BLE5_RAM_FL2INFO14_EN_EN 0x0001U 4387 4388 //****************************************************************************** 4389 // Register: FL2ADRL14 4390 //****************************************************************************** 4391 // Field: [15:0] val 4392 // 4393 // bits 15:0 of address 4394 #define PBE_BLE5_RAM_FL2ADRL14_VAL_W 16U 4395 #define PBE_BLE5_RAM_FL2ADRL14_VAL_M 0xFFFFU 4396 #define PBE_BLE5_RAM_FL2ADRL14_VAL_S 0U 4397 4398 //****************************************************************************** 4399 // Register: FL2ADRM14 4400 //****************************************************************************** 4401 // Field: [15:0] val 4402 // 4403 // bits 31:16 of address 4404 #define PBE_BLE5_RAM_FL2ADRM14_VAL_W 16U 4405 #define PBE_BLE5_RAM_FL2ADRM14_VAL_M 0xFFFFU 4406 #define PBE_BLE5_RAM_FL2ADRM14_VAL_S 0U 4407 4408 //****************************************************************************** 4409 // Register: FL2ADRH14 4410 //****************************************************************************** 4411 // Field: [15:0] val 4412 // 4413 // bits 47:32 of address 4414 #define PBE_BLE5_RAM_FL2ADRH14_VAL_W 16U 4415 #define PBE_BLE5_RAM_FL2ADRH14_VAL_M 0xFFFFU 4416 #define PBE_BLE5_RAM_FL2ADRH14_VAL_S 0U 4417 4418 //****************************************************************************** 4419 // Register: FL2INFO15 4420 //****************************************************************************** 4421 // Field: [15:15] matchtmp 4422 // 4423 // Temporary variable used in matching, ignore from CM0 4424 #define PBE_BLE5_RAM_FL2INFO15_MATCHTMP 0x8000U 4425 #define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_M 0x8000U 4426 #define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_S 15U 4427 #define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_NOMATCH 0x0000U 4428 #define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_MATCH 0x8000U 4429 4430 // Field: [14:4] reserved 4431 // 4432 // Reserved for future use 4433 #define PBE_BLE5_RAM_FL2INFO15_RESERVED_W 11U 4434 #define PBE_BLE5_RAM_FL2INFO15_RESERVED_M 0x7FF0U 4435 #define PBE_BLE5_RAM_FL2INFO15_RESERVED_S 4U 4436 4437 // Field: [3:3] privign 4438 // 4439 // Ignore control for privacy 4440 #define PBE_BLE5_RAM_FL2INFO15_PRIVIGN 0x0008U 4441 #define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_M 0x0008U 4442 #define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_S 3U 4443 #define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_NIGN 0x0000U 4444 #define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_IGN 0x0008U 4445 4446 // Field: [2:2] falign 4447 // 4448 // Ignore in accept list context 4449 #define PBE_BLE5_RAM_FL2INFO15_FALIGN 0x0004U 4450 #define PBE_BLE5_RAM_FL2INFO15_FALIGN_M 0x0004U 4451 #define PBE_BLE5_RAM_FL2INFO15_FALIGN_S 2U 4452 #define PBE_BLE5_RAM_FL2INFO15_FALIGN_NIGN 0x0000U 4453 #define PBE_BLE5_RAM_FL2INFO15_FALIGN_IGN 0x0004U 4454 4455 // Field: [1:1] type 4456 // 4457 // Address type 4458 #define PBE_BLE5_RAM_FL2INFO15_TYPE 0x0002U 4459 #define PBE_BLE5_RAM_FL2INFO15_TYPE_M 0x0002U 4460 #define PBE_BLE5_RAM_FL2INFO15_TYPE_S 1U 4461 #define PBE_BLE5_RAM_FL2INFO15_TYPE_PUBLIC 0x0000U 4462 #define PBE_BLE5_RAM_FL2INFO15_TYPE_RANDOM 0x0002U 4463 4464 // Field: [0:0] en 4465 // 4466 // Enable 4467 #define PBE_BLE5_RAM_FL2INFO15_EN 0x0001U 4468 #define PBE_BLE5_RAM_FL2INFO15_EN_M 0x0001U 4469 #define PBE_BLE5_RAM_FL2INFO15_EN_S 0U 4470 #define PBE_BLE5_RAM_FL2INFO15_EN_DIS 0x0000U 4471 #define PBE_BLE5_RAM_FL2INFO15_EN_EN 0x0001U 4472 4473 //****************************************************************************** 4474 // Register: FL2ADRL15 4475 //****************************************************************************** 4476 // Field: [15:0] val 4477 // 4478 // bits 15:0 of address 4479 #define PBE_BLE5_RAM_FL2ADRL15_VAL_W 16U 4480 #define PBE_BLE5_RAM_FL2ADRL15_VAL_M 0xFFFFU 4481 #define PBE_BLE5_RAM_FL2ADRL15_VAL_S 0U 4482 4483 //****************************************************************************** 4484 // Register: FL2ADRM15 4485 //****************************************************************************** 4486 // Field: [15:0] val 4487 // 4488 // bits 31:16 of address 4489 #define PBE_BLE5_RAM_FL2ADRM15_VAL_W 16U 4490 #define PBE_BLE5_RAM_FL2ADRM15_VAL_M 0xFFFFU 4491 #define PBE_BLE5_RAM_FL2ADRM15_VAL_S 0U 4492 4493 //****************************************************************************** 4494 // Register: FL2ADRH15 4495 //****************************************************************************** 4496 // Field: [15:0] val 4497 // 4498 // bits 47:32 of address 4499 #define PBE_BLE5_RAM_FL2ADRH15_VAL_W 16U 4500 #define PBE_BLE5_RAM_FL2ADRH15_VAL_M 0xFFFFU 4501 #define PBE_BLE5_RAM_FL2ADRH15_VAL_S 0U 4502 4503 4504 #endif // __PBE_BLE5_RAM_REGS_H 4505
