1 /*
2  * Copyright (c) 2024 Microchip Technology Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC5_PORT92_V1_H
7 #define _MEC5_PORT92_V1_H
8 
9 /** @addtogroup Device_Peripheral_peripherals
10   * @{
11   */
12 
13 /**
14   * @brief Keyboard Port92 emulation (MEC_PORT92)
15   */
16 
17 typedef struct mec_port92_regs {                /*!< (@ 0x400F2000) MEC_PORT92 Structure                                       */
18   __IM  uint8_t   HP92D;                        /*!< (@ 0x00000000) Port92 Host accessible register                            */
19   __IM  uint8_t   RESERVED[255];
20   __IOM uint8_t   CTRLGA20;                     /*!< (@ 0x00000100) EC-only: Port92 Gate A20 control                           */
21   __IM  uint8_t   RESERVED1[7];
22   __OM  uint8_t   SETGA20L;                     /*!< (@ 0x00000108) EC-only: Port92 Set Gate A20                               */
23   __IM  uint8_t   RESERVED2[3];
24   __OM  uint8_t   RSTGA20L;                     /*!< (@ 0x0000010C) EC-only: Port92 Reset Gate A20                             */
25   __IM  uint8_t   RESERVED3[547];
26   __IOM uint8_t   P92ACT;                       /*!< (@ 0x00000330) Port92 Logical device activate                             */
27 } MEC_PORT92_Type;                              /*!< Size = 817 (0x331)                                                        */
28 
29 /** @} */ /* End of group Device_Peripheral_peripherals */
30 
31 /** @addtogroup PosMask_peripherals
32   * @{
33   */
34 /* =======================================================  CTRLGA20  ======================================================== */
35 #define MEC_PORT92_CTRLGA20_GA20_Pos      (0UL)                     /*!< GA20 (Bit 0)                                          */
36 #define MEC_PORT92_CTRLGA20_GA20_Msk      (0x1UL)                   /*!< GA20 (Bitfield-Mask: 0x01)                            */
37 /* ========================================================  P92ACT  ========================================================= */
38 #define MEC_PORT92_P92ACT_ENABLE_Pos      (0UL)                     /*!< ENABLE (Bit 0)                                        */
39 #define MEC_PORT92_P92ACT_ENABLE_Msk      (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
40 
41 /** @} */ /* End of group PosMask_peripherals */
42 
43 #endif /* _MEC5_PORT92_V1_H */
44