1 /*
2 * Copyright 2017-2023 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_FLEXRAM_H_
10 #define FSL_FLEXRAM_H_
11
12 #include "fsl_common.h"
13 #include "fsl_flexram_allocate.h"
14
15 /*!
16 * @addtogroup flexram
17 * @{
18 */
19
20 /******************************************************************************
21 * Definitions.
22 *****************************************************************************/
23
24 /*! @name Driver version */
25 /*! @{ */
26 /*! @brief Driver version. */
27 #define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 3U, 0U))
28 /*! @} */
29
30 /*! @brief Get ECC error detailed information. */
31 #ifndef FLEXRAM_ECC_ERROR_DETAILED_INFO
32 #define FLEXRAM_ECC_ERROR_DETAILED_INFO \
33 0U /* Define to zero means get raw ECC error information, which needs parse it by user. */
34 #endif
35
36 /*! @brief Flexram write/read selection. */
37 enum
38 {
39 kFLEXRAM_Read = 0U, /*!< read */
40 kFLEXRAM_Write = 1U, /*!< write */
41 };
42
43 /*! @brief Interrupt status flag mask */
44 enum
45 {
46 kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< OCRAM accesses unallocated address */
47 kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< DTCM accesses unallocated address */
48 kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< ITCM accesses unallocated address */
49
50 #if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
51 kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< OCRAM magic address match */
52 kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< DTCM magic address match */
53 kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< ITCM magic address match */
54
55 #if defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC
56 kFLEXRAM_OCRAMECCMultiError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK,
57 kFLEXRAM_OCRAMECCSingleError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK,
58 kFLEXRAM_ITCMECCMultiError = FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK,
59 kFLEXRAM_ITCMECCSingleError = FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK,
60 kFLEXRAM_D0TCMECCMultiError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK,
61 kFLEXRAM_D0TCMECCSingleError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK,
62 kFLEXRAM_D1TCMECCMultiError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK,
63 kFLEXRAM_D1TCMECCSingleError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
64
65 kFLEXRAM_InterruptStatusAll =
66 FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
67 FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
68 FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK |
69 FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK |
70 FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK |
71 FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK |
72 FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
73 #else
74 kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
75 FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
76 FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,
77 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
78
79 /*!< all the interrupt status mask */
80 #else
81 kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
82 FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */
83 #endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
84
85 };
86
87 /*! @brief FLEXRAM TCM access mode.
88 * Fast access mode expected to be finished in 1-cycle;
89 * Wait access mode expected to be finished in 2-cycle.
90 * Wait access mode is a feature of the flexram and it should be used when
91 * the CPU clock is too fast to finish TCM access in 1-cycle.
92 * Normally, fast mode is the default mode, the efficiency of the TCM access will better.
93 */
94 typedef enum _flexram_tcm_access_mode
95 {
96 kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */
97 kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */
98 } flexram_tcm_access_mode_t;
99
100 /*! @brief FLEXRAM TCM support size */
101 enum
102 {
103 kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size be 32KB */
104 kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size be 64KB */
105 kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size be 128KB */
106 kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size be 256KB */
107 kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size be 512KB */
108 };
109
110 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
111 /*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */
112 typedef enum _flexram_memory_type
113 {
114 kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */
115 kFLEXRAM_ITCM = 1U, /*!< Memory type ITCM */
116 kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */
117 kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */
118 } flexram_memory_type_t;
119
120 /*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */
121 typedef struct _flexram_ecc_error_type
122 {
123 uint8_t SingleBitPos; /*!< Bit position of the bit to inject ECC Error. */
124 uint8_t SecondBitPos; /*!< Bit position of the second bit to inject multi-bit ECC Error */
125 bool Fource1BitDataInversion; /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */
126 bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write
127 access */
128 bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory
129 write access */
130 bool FourceContiNCDataInversion; /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on
131 memory write access */
132 } flexram_ecc_error_type_t;
133
134 /*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */
135 typedef struct _flexram_ocram_ecc_single_error_info
136 {
137 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
138 uint8_t OcramSingleErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM single-bit ECC error. */
139 uint8_t OcramSingleErrorECCSyndrome; /*!< OCRAM corresponding ECC syndrome of OCRAM single-bit ECC error,
140 which can be used to locate the Error bit using a look-up table. */
141 #else
142 uint32_t OcramSingleErrorInfo; /*!< Ocram single error information, user should parse it by themself. */
143 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
144 uint32_t OcramSingleErrorAddr; /*!< Ocram single error address */
145 uint32_t OcramSingleErrorDataLSB; /*!< Ocram single error data LSB */
146 uint32_t OcramSingleErrorDataMSB; /*!< Ocram single error data MSB */
147 } flexram_ocram_ecc_single_error_info_t;
148
149 /*! @brief FLEXRAM ocram ecc multiple error information, including multiple error information, error address, error data
150 */
151 typedef struct _flexram_ocram_ecc_multi_error_info
152 {
153 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
154 uint8_t OcramMultiErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM multi-bit ECC error. */
155 #else
156 uint32_t OcramMultiErrorInfo; /*!< Ocram single error information, user should parse it by themself. */
157 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
158 uint32_t OcramMultiErrorAddr; /*!< Ocram multiple error address */
159 uint32_t OcramMultiErrorDataLSB; /*!< Ocram multiple error data LSB */
160 uint32_t OcramMultiErrorDataMSB; /*!< Ocram multiple error data MSB */
161 } flexram_ocram_ecc_multi_error_info_t;
162
163 /*! @brief FLEXRAM itcm ecc single error information, including single error information, error address, error data */
164 typedef struct _flexram_itcm_ecc_single_error_info
165 {
166 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
167 uint8_t ItcmSingleErrorTCMWriteRead; /*!< itcm single-bit ECC error corresponding tcm_wr value, which is to tell
168 whether it is a write access(0x01) or a read access(0x00). */
169 uint8_t ItcmSingleErrorTCMAccessSize; /*!< itcm single-bit ECC error corresponding tcm access size,
170 which should be 3 (64bit). */
171 uint8_t ItcmSingleErrorTCMMaster; /*!< itcm single-bit ECC error corresponding tcm_master,
172 which is to tell the requester of the current access. */
173 uint8_t ItcmSingleErrorTCMPrivilege; /*!< itcm single-bit ECC error corresponding tcm_priv,
174 which is to tell the privilege level of access. */
175 uint8_t ItcmSingleErrorBitPostion; /*!< itcm single-bit ECC error corresponding bit postion. */
176 #else
177 uint32_t ItcmSingleErrorInfo; /*!< itcm single error information, user should parse it by themself. */
178 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
179 uint32_t ItcmSingleErrorAddr; /*!< itcm single error address */
180 uint32_t ItcmSingleErrorDataLSB; /*!< itcm single error data LSB */
181 uint32_t ItcmSingleErrorDataMSB; /*!< itcm single error data MSB */
182 } flexram_itcm_ecc_single_error_info_t;
183
184 /*! @brief FLEXRAM itcm ecc multiple error information, including multiple error information, error address, error data
185 */
186 typedef struct _flexram_itcm_ecc_multi_error_info
187 {
188 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
189 uint8_t ItcmMultiErrorTCMWriteRead; /*!< itcm multiple-bit ECC error corresponding tcm_wr value, which is to tell
190 whether it is a write access(0x01) or a read access(0x00). */
191 uint8_t ItcmMultiErrorTCMAccessSize; /*!< itcm multiple-bit ECC error corresponding tcm access size,
192 which should be 3 (64bit). */
193 uint8_t ItcmMultiErrorTCMMaster; /*!< itcm multiple-bit ECC error corresponding tcm_master,
194 which is to tell the requester of the current access. */
195 uint8_t ItcmMultiErrorTCMPrivilege; /*!< itcm multiple-bit ECC error corresponding tcm_priv,
196 which is to tell the privilege level of access. */
197 uint8_t ItcmMultiErrorECCSyndrome; /*!< itcm multiple-bit ECC error corresponding syndrome,
198 which can not be used to locate the Error bit using a look-up table. */
199 #else
200 uint32_t ItcmMultiErrorInfo; /*!< itcm multiple error information, user should parse it by themself. */
201 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
202 uint32_t ItcmMultiErrorAddr; /*!< itcm multiple error address */
203 uint32_t ItcmMultiErrorDataLSB; /*!< itcm multiple error data LSB */
204 uint32_t ItcmMultiErrorDataMSB; /*!< itcm multiple error data MSB */
205 } flexram_itcm_ecc_multi_error_info_t;
206
207 /*! @brief FLEXRAM dtcm ecc single error information, including single error information, error address, error data */
208 typedef struct _flexram_dtcm_ecc_single_error_info
209 {
210 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
211 uint8_t DtcmSingleErrorTCMWriteRead; /*!< dtcm single-bit ECC error corresponding tcm_wr value, which is to tell
212 whether it is a write access(0x01) or a read access(0x00). */
213 uint8_t DtcmSingleErrorTCMAccessSize; /*!< dtcm single-bit ECC error corresponding tcm access size,
214 which should be 2 (32bit). */
215 uint8_t DtcmSingleErrorTCMMaster; /*!< dtcm single-bit ECC error corresponding tcm_master,
216 which is to tell the requester of the current access. */
217 uint8_t DtcmSingleErrorTCMPrivilege; /*!< dtcm single-bit ECC error corresponding tcm_priv,
218 which is to tell the privilege level of access. */
219 uint8_t DtcmSingleErrorBitPostion; /*!< dtcm single-bit ECC error corresponding bit postion. */
220 #else
221 uint32_t DtcmSingleErrorInfo; /*!< dtcm single error information, user should parse it by themself. */
222 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
223 uint32_t DtcmSingleErrorAddr; /*!< dtcm single error address */
224 uint32_t DtcmSingleErrorData; /*!< dtcm single error data */
225 } flexram_dtcm_ecc_single_error_info_t;
226
227 /*! @brief FLEXRAM dtcm ecc multiple error information, including multiple error information, error address, error data
228 */
229 typedef struct _flexram_dtcm_ecc_multi_error_info
230 {
231 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
232 uint8_t DtcmMultiErrorTCMWriteRead; /*!< dtcm multiple-bit ECC error corresponding tcm_wr value, which is to tell
233 whether it is a write access(0x01) or a read access(0x00). */
234 uint8_t DtcmMultiErrorTCMAccessSize; /*!< dtcm multiple-bit ECC error corresponding tcm access size,
235 which should be 3 (64bit). */
236 uint8_t DtcmMultiErrorTCMMaster; /*!< dtcm multiple-bit ECC error corresponding tcm_master,
237 which is to tell the requester of the current access. */
238 uint8_t DtcmMultiErrorTCMPrivilege; /*!< dtcm multiple-bit ECC error corresponding tcm_priv,
239 which is to tell the privilege level of access. */
240 uint8_t DtcmMultiErrorECCSyndrome; /*!< dtcm multiple-bit ECC error corresponding syndrome,
241 which can not be used to locate the Error bit using a look-up table. */
242 #else
243 uint32_t DtcmMultiErrorInfo; /*!< dtcm multiple error information, user should parse it by themself. */
244 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
245 uint32_t DtcmMultiErrorAddr; /*!< dtcm multiple error address */
246 uint32_t DtcmMultiErrorData; /*!< dtcm multiple error data */
247 } flexram_dtcm_ecc_multi_error_info_t;
248
249 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
250
251 /*******************************************************************************
252 * APIs
253 ******************************************************************************/
254
255 #if defined(__cplusplus)
256 extern "C" {
257 #endif
258
259 /*!
260 * @name Initialization and de-initialization
261 * @{
262 */
263
264 /*!
265 * @brief FLEXRAM module initialization function.
266 *
267 * @param base FLEXRAM base address.
268 */
269 void FLEXRAM_Init(FLEXRAM_Type *base);
270
271 /*!
272 * @brief De-initializes the FLEXRAM.
273 *
274 */
275 void FLEXRAM_Deinit(FLEXRAM_Type *base);
276
277 /*! @} */
278
279 /*!
280 * @name Status
281 * @{
282 */
283 /*!
284 * @brief FLEXRAM module gets interrupt status.
285 *
286 * @param base FLEXRAM base address.
287 */
FLEXRAM_GetInterruptStatus(FLEXRAM_Type * base)288 static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base)
289 {
290 return base->INT_STATUS & (uint32_t)kFLEXRAM_InterruptStatusAll;
291 }
292
293 /*!
294 * @brief FLEXRAM module clears interrupt status.
295 *
296 * @param base FLEXRAM base address.
297 * @param status Status to be cleared.
298 */
FLEXRAM_ClearInterruptStatus(FLEXRAM_Type * base,uint32_t status)299 static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status)
300 {
301 base->INT_STATUS |= status;
302 }
303
304 /*!
305 * @brief FLEXRAM module enables interrupt status.
306 *
307 * @param base FLEXRAM base address.
308 * @param status Status to be enabled.
309 */
FLEXRAM_EnableInterruptStatus(FLEXRAM_Type * base,uint32_t status)310 static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
311 {
312 base->INT_STAT_EN |= status;
313 }
314
315 /*!
316 * @brief FLEXRAM module disable interrupt status.
317 *
318 * @param base FLEXRAM base address.
319 * @param status Status to be disabled.
320 */
FLEXRAM_DisableInterruptStatus(FLEXRAM_Type * base,uint32_t status)321 static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
322 {
323 base->INT_STAT_EN &= ~status;
324 }
325
326 /*! @} */
327
328 /*!
329 * @name Interrupts
330 * @{
331 */
332
333 /*!
334 * @brief FLEXRAM module enables interrupt.
335 *
336 * @param base FLEXRAM base address.
337 * @param status Status interrupt to be enabled.
338 */
FLEXRAM_EnableInterruptSignal(FLEXRAM_Type * base,uint32_t status)339 static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
340 {
341 base->INT_SIG_EN |= status;
342 }
343
344 /*!
345 * @brief FLEXRAM module disables interrupt.
346 *
347 * @param base FLEXRAM base address.
348 * @param status Status interrupt to be disabled.
349 */
FLEXRAM_DisableInterruptSignal(FLEXRAM_Type * base,uint32_t status)350 static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
351 {
352 base->INT_SIG_EN &= ~status;
353 }
354 /*! @} */
355
356 /*!
357 * @brief FLEXRAM module sets TCM read access mode
358 *
359 * @param base FLEXRAM base address.
360 * @param mode Access mode.
361 */
FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type * base,flexram_tcm_access_mode_t mode)362 static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
363 {
364 base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
365 base->TCM_CTRL |= (uint32_t)mode;
366 }
367
368 /*!
369 * @brief FLEXRAM module set TCM write access mode
370 *
371 * @param base FLEXRAM base address.
372 * @param mode Access mode.
373 */
FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type * base,flexram_tcm_access_mode_t mode)374 static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
375 {
376 base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
377 base->TCM_CTRL |= (uint32_t)mode;
378 }
379
380 /*!
381 * @brief FLEXRAM module force ram clock on
382 *
383 * @param base FLEXRAM base address.
384 * @param enable Enable or disable clock force on.
385 */
FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type * base,bool enable)386 static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable)
387 {
388 if (enable)
389 {
390 base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
391 }
392 else
393 {
394 base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
395 }
396 }
397
398 #if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
399 /*!
400 * @brief FLEXRAM OCRAM magic addr configuration.
401 * When read/write access hit magic address, it will generate interrupt.
402 * @param base FLEXRAM base address.
403 * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
404 * @param rwSel Read/write selection. 0 for read access while 1 for write access.
405 */
FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type * base,uint16_t magicAddr,uint32_t rwSel)406 static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
407 {
408 base->OCRAM_MAGIC_ADDR = FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) |
409 FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
410 }
411
412 /*!
413 * @brief FLEXRAM DTCM magic addr configuration.
414 * When read/write access hits magic address, it will generate interrupt.
415 * @param base FLEXRAM base address.
416 * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
417 * @param rwSel Read/write selection. 0 for read access while 1 write access.
418 */
FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type * base,uint16_t magicAddr,uint32_t rwSel)419 static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
420 {
421 base->DTCM_MAGIC_ADDR = FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) |
422 FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
423 }
424
425 /*!
426 * @brief FLEXRAM ITCM magic addr configuration.
427 * When read/write access hits magic address, it will generate interrupt.
428 * @param base FLEXRAM base address.
429 * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
430 * @param rwSel Read/write selection. 0 for read access while 1 for write access.
431 */
FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type * base,uint16_t magicAddr,uint32_t rwSel)432 static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
433 {
434 base->ITCM_MAGIC_ADDR = FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) |
435 FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
436 }
437 #endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
438
439 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
440 /*!
441 * @brief FLEXRAM get ocram ecc single error information.
442 * @param base FLEXRAM base address.
443 * @param OcramECCEnable ocram ecc enablement.
444 * @param TcmECCEnable tcm(itcm/d0tcm/d1tcm) ecc enablement.
445 */
446 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
447
448 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION) && (FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION))
449 /*!
450 * @brief FLEXRAM ECC error injection.
451 * @param base FLEXRAM base address.
452 * @param memory memory type, such as OCRAM/ITCM/DTCM.
453 * @param error ECC error type.
454 */
455 void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error);
456 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION */
457
458 /*!
459 * @brief FLEXRAM get ocram ecc single error information.
460 * @param base FLEXRAM base address.
461 * @param info ecc error information.
462 */
463 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info);
464
465 /*!
466 * @brief FLEXRAM get ocram ecc multiple error information.
467 * @param base FLEXRAM base address.
468 * @param info ecc error information.
469 */
470 void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info);
471
472 /*!
473 * @brief FLEXRAM get itcm ecc single error information.
474 * @param base FLEXRAM base address.
475 * @param info ecc error information.
476 */
477 void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info);
478
479 /*!
480 * @brief FLEXRAM get itcm ecc multiple error information.
481 * @param base FLEXRAM base address.
482 * @param info ecc error information.
483 */
484 void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info);
485
486 /*!
487 * @brief FLEXRAM get d0tcm ecc single error information.
488 * @param base FLEXRAM base address.
489 * @param info ecc error information.
490 * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM.
491 */
492 void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank);
493
494 /*!
495 * @brief FLEXRAM get d0tcm ecc multiple error information.
496 * @param base FLEXRAM base address.
497 * @param info ecc error information.
498 * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM.
499 */
500 void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank);
501
502 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
503
504 #if defined(__cplusplus)
505 }
506 #endif
507
508 /*! @}*/
509
510 #endif
511
