1 /*! 2 \file gd32e50x_dac.h 3 \brief definitions for the DAC 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_DAC_H 38 #define GD32E50X_DAC_H 39 40 #include "gd32e50x.h" 41 42 /* DAC definitions */ 43 #define DAC DAC_BASE 44 45 /* registers definitions */ 46 #define DAC_CTL0 REG32(DAC + 0x00000000U) /*!< DAC control register 0 */ 47 #define DAC_SWT REG32(DAC + 0x00000004U) /*!< DAC software trigger register */ 48 #define OUT0_R12DH REG32(DAC + 0x00000008U) /*!< DAC_OUT0 12-bit right-aligned data holding register */ 49 #define OUT0_L12DH REG32(DAC + 0x0000000CU) /*!< DAC_OUT0 12-bit left-aligned data holding register */ 50 #define OUT0_R8DH REG32(DAC + 0x00000010U) /*!< DAC_OUT0 8-bit right-aligned data holding register */ 51 #define OUT1_R12DH REG32(DAC + 0x00000014U) /*!< DAC_OUT1 12-bit right-aligned data holding register */ 52 #define OUT1_L12DH REG32(DAC + 0x00000018U) /*!< DAC_OUT1 12-bit left-aligned data holding register */ 53 #define OUT1_R8DH REG32(DAC + 0x0000001CU) /*!< DAC_OUT1 8-bit right-aligned data holding register */ 54 #define DACC_R12DH REG32(DAC + 0x00000020U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ 55 #define DACC_L12DH REG32(DAC + 0x00000024U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ 56 #define DACC_R8DH REG32(DAC + 0x00000028U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ 57 #define OUT0_DO REG32(DAC + 0x0000002CU) /*!< DAC_OUT0 data output register */ 58 #define OUT1_DO REG32(DAC + 0x00000030U) /*!< DAC_OUT1 data output register */ 59 #define DAC_STAT0 REG32(DAC + 0x00000034U) /*!< DAC status register 0 */ 60 #define DAC_CTL1 REG32(DAC + 0x00000080U) /*!< DAC control register 1 */ 61 #define DAC_STAT1 REG32(DAC + 0x00000084U) /*!< DAC status register 1 */ 62 63 /* bits definitions */ 64 /* DAC_CTL0 */ 65 #define DAC_CTL0_DEN0 BIT(0) /*!< DAC_OUT0 enable/disable bit */ 66 #define DAC_CTL0_DBOFF0 BIT(1) /*!< DAC_OUT0 output buffer turn on/turn off bit */ 67 #define DAC_CTL0_DTEN0 BIT(2) /*!< DAC_OUT0 trigger enable/disable bit */ 68 #define DAC_CTL0_DTSEL0 BITS(3, 5) /*!< DAC_OUT0 trigger source selection enable/disable bits */ 69 #define DAC_CTL0_DWM0 BITS(6, 7) /*!< DAC_OUT0 noise wave mode */ 70 #define DAC_CTL0_DWBW0 BITS(8, 11) /*!< DAC_OUT0 noise wave bit width */ 71 #define DAC_CTL0_DDMAEN0 BIT(12) /*!< DAC_OUT0 DMA enable/disable bit */ 72 #define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DAC_OUT0 DMA underrun interrupt enable/disable bit */ 73 #define DAC_CTL0_DTSEL0_3 BIT(14) /*!< DAC_OUT0 trigger selection bit[3], refer to DTSEL1[2:0] */ 74 #define DAC_CTL0_DEN1 BIT(16) /*!< DAC_OUT1 enable/disable bit */ 75 #define DAC_CTL0_DBOFF1 BIT(17) /*!< DAC_OUT1 output buffer turn on/turn off bit */ 76 #define DAC_CTL0_DTEN1 BIT(18) /*!< DAC_OUT1 trigger enable/disable bit */ 77 #define DAC_CTL0_DTSEL1 BITS(19, 21) /*!< DAC_OUT1 trigger source selection enable/disable bits */ 78 #define DAC_CTL0_DWM1 BITS(22, 23) /*!< DAC_OUT1 noise wave mode */ 79 #define DAC_CTL0_DWBW1 BITS(24, 27) /*!< DAC_OUT1 noise wave bit width */ 80 #define DAC_CTL0_DDMAEN1 BIT(28) /*!< DAC_OUT1 DMA enable/disable bit */ 81 #define DAC_CTL0_DDUDRIE1 BIT(29) /*!< DAC_OUT1 DMA underrun interrupt enable/disable bit */ 82 #define DAC_CTL0_DTSEL1_3 BIT(30) /*!< DAC_OUT1 trigger selection bit[3], refer to DTSEL1[2:0] */ 83 84 /* DAC_SWT */ 85 #define DAC_SWT_SWTR0 BIT(0) /*!< DAC_OUT0 software trigger bit, cleared by hardware */ 86 #define DAC_SWT_SWTR1 BIT(1) /*!< DAC_OUT1 software trigger bit, cleared by hardware */ 87 88 /* OUT0_R12DH */ 89 #define OUT0_R12DH_OUT0_DH BITS(0, 11) /*!< DAC_OUT0 12-bit right-aligned data bits */ 90 91 /* OUT0_L12DH */ 92 #define OUT0_L12DH_OUT0_DH BITS(4, 15) /*!< DAC_OUT0 12-bit left-aligned data bits */ 93 94 /* OUT0_R8DH */ 95 #define OUT0_R8DH_OUT0_DH BITS(0, 7) /*!< DAC_OUT0 8-bit right-aligned data bits */ 96 97 /* OUT1_R12DH */ 98 #define OUT1_R12DH_OUT1_DH BITS(0, 11) /*!< DAC_OUT1 12-bit right-aligned data bits */ 99 100 /* OUT1_L12DH */ 101 #define OUT1_L12DH_OUT1_DH BITS(4, 15) /*!< DAC_OUT1 12-bit left-aligned data bits */ 102 103 /* OUT1_R8DH */ 104 #define OUT1_R8DH_OUT1_DH BITS(0, 7) /*!< DAC_OUT1 8-bit right-aligned data bits */ 105 106 /* DACC_R12DH */ 107 #define DACC_R12DH_OUT0_DH BITS(0, 11) /*!< DAC concurrent mode DAC_OUT0 12-bit right-aligned data bits */ 108 #define DACC_R12DH_OUT1_DH BITS(16, 27) /*!< DAC concurrent mode DAC_OUT1 12-bit right-aligned data bits */ 109 110 /* DACC_L12DH */ 111 #define DACC_L12DH_OUT0_DH BITS(4, 15) /*!< DAC concurrent mode DAC_OUT0 12-bit left-aligned data bits */ 112 #define DACC_L12DH_OUT1_DH BITS(20, 31) /*!< DAC concurrent mode DAC_OUT1 12-bit left-aligned data bits */ 113 114 /* DACC_R8DH */ 115 #define DACC_R8DH_OUT0_DH BITS(0, 7) /*!< DAC concurrent mode DAC_OUT0 8-bit right-aligned data bits */ 116 #define DACC_R8DH_OUT1_DH BITS(8, 15) /*!< DAC concurrent mode DAC_OUT1 8-bit right-aligned data bits */ 117 118 /* OUT0_DO */ 119 #define OUT0_DO_OUT0_DO BITS(0, 11) /*!< DAC_OUT0 12-bit output data bits */ 120 121 /* OUT1_DO */ 122 #define OUT1_DO_OUT1_DO BITS(0, 11) /*!< DAC_OUT1 12-bit output data bits */ 123 124 /* DAC_STAT0 */ 125 #define DAC_STAT0_DDUDR0 BIT(13) /*!< DAC_OUT0 DMA underrun flag */ 126 #define DAC_STAT0_DDUDR1 BIT(29) /*!< DAC_OUT1 DMA underrun flag */ 127 128 /* DAC_CTL1 */ 129 #define DAC_CTL1_FIFOEN0 BIT(0) /*!< DAC_OUT0 data FIFO enable */ 130 #define DAC_CTL1_FIFOOVRIE0 BIT(1) /*!< DAC_OUT0 FIFO overflow interrupt enable */ 131 #define DAC_CTL1_FIFOUDRIE0 BIT(2) /*!< DAC_OUT0 FIFO underflow interrupt enable */ 132 #define DAC_CTL1_FIFOEN1 BIT(16) /*!< DAC_OUT1 data FIFO enable */ 133 #define DAC_CTL1_FIFOOVRIE1 BIT(17) /*!< DAC_OUT1 FIFO overflow interrupt enable */ 134 #define DAC_CTL1_FIFOUDRIE1 BIT(18) /*!< DAC_OUT1 FIFO underflow interrupt enable */ 135 136 /* DAC_STAT1 */ 137 #define DAC_STAT1_FF0 BIT(0) /*!< DAC_OUT0 FIFO full flag */ 138 #define DAC_STAT1_FE0 BIT(1) /*!< DAC_OUT0 FIFO empty flag */ 139 #define DAC_STAT1_FIFOOVR0 BIT(2) /*!< DAC_OUT0 FIFO overflow flag */ 140 #define DAC_STAT1_FIFOUDR0 BIT(3) /*!< DAC_OUT0 FIFO underflow flag */ 141 #define DAC_STAT1_FIFONUM0 BITS(4, 6) /*!< number of data in the DAC_OUT0 FIFO */ 142 #define DAC_STAT1_FF1 BIT(16) /*!< DAC_OUT0 FIFO full flag */ 143 #define DAC_STAT1_FE1 BIT(17) /*!< DAC_OUT0 FIFO empty flag */ 144 #define DAC_STAT1_FIFOOVR1 BIT(18) /*!< DAC_OUT0 FIFO overflow flag */ 145 #define DAC_STAT1_FIFOUDR1 BIT(19) /*!< DAC_OUT0 FIFO underflow flag */ 146 #define DAC_STAT1_FIFONUM1 BITS(20, 22) /*!< number of data in the DAC_OUT0 FIFO */ 147 148 /* constants definitions */ 149 /* DAC trigger source */ 150 #define CTL0_DTSEL(regval) (BITS(3, 5) & ((uint32_t)(regval) << 3)) 151 #define DAC_TRIGGER_T5_TRGO CTL0_DTSEL(0) /*!< TIMER5 TRGO */ 152 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD)) 153 #define DAC_TRIGGER_T7_TRGO CTL0_DTSEL(1) /*!< TIMER7 TRGO(for GD32E50X_HD and GD32E50X_XD devices, except for 48 pin chips) */ 154 #elif defined(GD32E50X_CL) 155 #define DAC_TRIGGER_T2_TRGO CTL0_DTSEL(1) /*!< TIMER2 TRGO(for GD32E50X_CL devices ) */ 156 #endif /* GD32E50X_HD and GD32E50X_XD */ 157 #define DAC_TRIGGER_T6_TRGO CTL0_DTSEL(2) /*!< TIMER6 TRGO */ 158 #define DAC_TRIGGER_T4_TRGO CTL0_DTSEL(3) /*!< TIMER4 TRGO */ 159 #define DAC_TRIGGER_T1_TRGO CTL0_DTSEL(4) /*!< TIMER1 TRGO */ 160 #define DAC_TRIGGER_T3_TRGO CTL0_DTSEL(5) /*!< TIMER3 TRGO */ 161 #define DAC_TRIGGER_EXTI_9 CTL0_DTSEL(6) /*!< EXTI interrupt line9 event */ 162 #define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(7) /*!< software trigger */ 163 #if !defined (GD32EPRT) 164 #define DAC_TRIGGER_SHRTIMER_DACTRIG0 (DAC_CTL0_DTSEL0_3 | CTL0_DTSEL(0)) /*!< SHRTIMER_DACTRIG0 trigger */ 165 #define DAC_TRIGGER_SHRTIMER_DACTRIG1 (DAC_CTL0_DTSEL0_3 | CTL0_DTSEL(1)) /*!< SHRTIMER_DACTRIG1 trigger */ 166 #define DAC_TRIGGER_SHRTIMER_DACTRIG2 (DAC_CTL0_DTSEL0_3 | CTL0_DTSEL(2)) /*!< SHRTIMER_DACTRIG2 trigger */ 167 #endif /* defined (GD32E50X_HD) && defined (GD32E50X_XD) && defined (GD32E50X_CL) */ 168 /* DAC noise wave mode */ 169 #define CTL0_DWM(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6)) 170 #define DAC_WAVE_DISABLE CTL0_DWM(0) /*!< wave disable */ 171 #define DAC_WAVE_MODE_LFSR CTL0_DWM(1) /*!< LFSR noise mode */ 172 #define DAC_WAVE_MODE_TRIANGLE CTL0_DWM(2) /*!< triangle noise mode */ 173 174 /* DAC noise wave bit width */ 175 #define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8)) 176 #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ 177 #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ 178 #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ 179 #define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ 180 #define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ 181 #define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ 182 #define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ 183 #define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ 184 #define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ 185 #define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ 186 #define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ 187 #define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ 188 189 /* unmask LFSR bits in DAC LFSR noise mode */ 190 #define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ 191 #define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ 192 #define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ 193 #define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ 194 #define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ 195 #define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ 196 #define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ 197 #define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ 198 #define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ 199 #define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ 200 #define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ 201 #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ 202 203 /* DAC data alignment */ 204 #define DATA_ALIGN(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) 205 #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */ 206 #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */ 207 #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */ 208 209 /* triangle amplitude in DAC triangle noise mode */ 210 #define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ 211 #define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ 212 #define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ 213 #define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ 214 #define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ 215 #define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ 216 #define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ 217 #define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ 218 #define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ 219 #define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ 220 #define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ 221 #define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ 222 223 /* DAC output channel definitions */ 224 #define DAC_OUT_0 ((uint8_t)0x00U) /*!< DAC_OUT0 */ 225 #define DAC_OUT_1 ((uint8_t)0x01U) /*!< DAC_OUT1 */ 226 227 /* DAC interrupt */ 228 #define DAC_INT_DDUDRIE0 DAC_CTL0_DDUDRIE0 /*!< DAC_OUT0 DMA underrun interrupt enable */ 229 #define DAC_INT_FIFOOVRIE0 DAC_CTL1_FIFOOVRIE0 /*!< DAC_OUT0 FIFO overflow interrupt enable */ 230 #define DAC_INT_FIFOUDRIE0 DAC_CTL1_FIFOUDRIE0 /*!< DAC_OUT0 FIFO underflow interrupt enable */ 231 #define DAC_INT_DDUDRIE1 DAC_CTL0_DDUDRIE1 /*!< DAC_OUT1 DMA underrun interrupt enable */ 232 #define DAC_INT_FIFOOVRIE1 DAC_CTL1_FIFOOVRIE1 /*!< DAC_OUT1 FIFO overflow interrupt enable */ 233 #define DAC_INT_FIFOUDRIE1 DAC_CTL1_FIFOUDRIE1 /*!< DAC_OUT1 FIFO underflow interrupt enable */ 234 235 /* DAC interrupt flag */ 236 #define DAC_INT_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DAC_OUT0 DMA underrun interrupt flag */ 237 #define DAC_INT_FLAG_FIFOOVR0 DAC_STAT1_FIFOOVR0 /*!< DAC_OUT0 FIFO overflow interrupt flag */ 238 #define DAC_INT_FLAG_FIFOUDR0 DAC_STAT1_FIFOUDR0 /*!< DAC_OUT0 FIFO underflow interrupt flag */ 239 #define DAC_INT_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DAC_OUT1 DMA underrun interrupt flag */ 240 #define DAC_INT_FLAG_FIFOOVR1 DAC_STAT1_FIFOOVR1 /*!< DAC_OUT1 FIFO overflow interrupt flag */ 241 #define DAC_INT_FLAG_FIFOUDR1 DAC_STAT1_FIFOUDR1 /*!< DAC_OUT1 FIFO underflow interrupt flag */ 242 243 /* DAC flag */ 244 #define DAC_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DAC_OUT0 DMA underrun flag */ 245 #define DAC_FLAG_FF0 DAC_STAT1_FF0 /*!< DAC_OUT0 FIFO full flag */ 246 #define DAC_FLAG_FE0 DAC_STAT1_FE0 /*!< DAC_OUT0 FIFO empty flag */ 247 #define DAC_FLAG_FIFOOVR0 DAC_STAT1_FIFOOVR0 /*!< DAC_OUT0 FIFO overflow flag */ 248 #define DAC_FLAG_FIFOUDR0 DAC_STAT1_FIFOUDR0 /*!< DAC_OUT0 FIFO underflow flag */ 249 #define DAC_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DAC_OUT1 DMA underrun flag */ 250 #define DAC_FLAG_FF1 DAC_STAT1_FF1 /*!< DAC_OUT1 FIFO full flag */ 251 #define DAC_FLAG_FE1 DAC_STAT1_FE1 /*!< DAC_OUT1 FIFO empty flag */ 252 #define DAC_FLAG_FIFOOVR1 DAC_STAT1_FIFOOVR1 /*!< DAC_OUT1 FIFO overflow flag */ 253 #define DAC_FLAG_FIFOUDR1 DAC_STAT1_FIFOUDR1 /*!< DAC_OUT1 FIFO underflow flag */ 254 255 /* function declarations */ 256 /* initialization functions */ 257 /* deinitialize DAC */ 258 void dac_deinit(void); 259 /* enable DAC */ 260 void dac_enable(uint8_t dac_out); 261 /* disable DAC */ 262 void dac_disable(uint8_t dac_out); 263 /* enable DAC DMA */ 264 void dac_dma_enable(uint8_t dac_out); 265 /* disable DAC DMA */ 266 void dac_dma_disable(uint8_t dac_out); 267 /* enable DAC output buffer */ 268 void dac_output_buffer_enable(uint8_t dac_out); 269 /* disable DAC output buffer */ 270 void dac_output_buffer_disable(uint8_t dac_out); 271 /* get DAC output value */ 272 uint16_t dac_output_value_get(uint8_t dac_out); 273 /* set DAC data holding register value */ 274 void dac_data_set(uint8_t dac_out, uint32_t dac_align, uint16_t data); 275 /* enable DAC output FIFO */ 276 void dac_output_fifo_enable(uint8_t dac_out); 277 /* disable DAC output FIFO */ 278 void dac_output_fifo_disable(uint8_t dac_out); 279 /* get DAC output FIFO number */ 280 uint16_t dac_output_fifo_number_get(uint8_t dac_out); 281 282 /* DAC trigger configuration */ 283 /* enable DAC trigger */ 284 void dac_trigger_enable(uint8_t dac_out); 285 /* disable DAC trigger */ 286 void dac_trigger_disable(uint8_t dac_out); 287 /* configure DAC trigger source */ 288 void dac_trigger_source_config(uint8_t dac_out, uint32_t triggersource); 289 /* enable DAC software trigger */ 290 void dac_software_trigger_enable(uint8_t dac_out); 291 /* disable DAC software trigger */ 292 void dac_software_trigger_disable(uint8_t dac_out); 293 294 /* DAC wave mode configuration */ 295 /* configure DAC wave mode */ 296 void dac_wave_mode_config(uint8_t dac_out, uint32_t wave_mode); 297 /* configure DAC wave bit width */ 298 void dac_wave_bit_width_config(uint8_t dac_out, uint32_t bit_width); 299 /* configure DAC LFSR noise mode */ 300 void dac_lfsr_noise_config(uint8_t dac_out, uint32_t unmask_bits); 301 /* configure DAC triangle noise mode */ 302 void dac_triangle_noise_config(uint8_t dac_out, uint32_t amplitude); 303 304 /* DAC concurrent mode configuration */ 305 /* enable DAC concurrent mode */ 306 void dac_concurrent_enable(void); 307 /* disable DAC concurrent mode */ 308 void dac_concurrent_disable(void); 309 /* enable DAC concurrent software trigger */ 310 void dac_concurrent_software_trigger_enable(void); 311 /* disable DAC concurrent software trigger */ 312 void dac_concurrent_software_trigger_disable(void); 313 /* enable DAC concurrent buffer function */ 314 void dac_concurrent_output_buffer_enable(void); 315 /* disable DAC concurrent buffer function */ 316 void dac_concurrent_output_buffer_disable(void); 317 /* set DAC concurrent mode data holding register value */ 318 void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); 319 320 /* interrupt and flag functions */ 321 /* get DAC flag */ 322 FlagStatus dac_flag_get(uint8_t dac_out, uint32_t flag); 323 /* clear DAC flag */ 324 void dac_flag_clear(uint8_t dac_out, uint32_t flag); 325 /* enable DAC interrupt */ 326 void dac_interrupt_enable(uint8_t dac_out, uint32_t interrupt); 327 /* disable DAC interrupt */ 328 void dac_interrupt_disable(uint8_t dac_out, uint32_t interrupt); 329 /* get DAC interrupt flag */ 330 FlagStatus dac_interrupt_flag_get(uint8_t dac_out, uint32_t int_flag); 331 /* clear DAC interrupt flag */ 332 void dac_interrupt_flag_clear(uint8_t dac_out, uint32_t int_flag); 333 334 #endif /* GD32E50X_DAC_H */ 335
