1 /** 2 * \file 3 * 4 * \brief Component description for OSC32KCTRL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_OSC32KCTRL_COMPONENT_ 30 #define _SAML21_OSC32KCTRL_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR OSC32KCTRL */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_OSC32KCTRL 32k Oscillators Control */ 36 /*@{*/ 37 38 #define OSC32KCTRL_U2246 39 #define REV_OSC32KCTRL 0x110 40 41 /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 46 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ 47 uint32_t :30; /*!< bit: 2..31 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } OSC32KCTRL_INTENCLR_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ 54 #define OSC32KCTRL_INTENCLR_RESETVALUE _U(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 55 56 #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ 57 #define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) 58 #define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ 59 #define OSC32KCTRL_INTENCLR_OSC32KRDY (_U(0x1) << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos) 60 #define OSC32KCTRL_INTENCLR_MASK _U(0x00000003) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ 61 62 /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 67 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ 68 uint32_t :30; /*!< bit: 2..31 Reserved */ 69 } bit; /*!< Structure used for bit access */ 70 uint32_t reg; /*!< Type used for register access */ 71 } OSC32KCTRL_INTENSET_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 #define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ 75 #define OSC32KCTRL_INTENSET_RESETVALUE _U(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ 76 77 #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ 78 #define OSC32KCTRL_INTENSET_XOSC32KRDY (_U(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) 79 #define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */ 80 #define OSC32KCTRL_INTENSET_OSC32KRDY (_U(0x1) << OSC32KCTRL_INTENSET_OSC32KRDY_Pos) 81 #define OSC32KCTRL_INTENSET_MASK _U(0x00000003) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ 82 83 /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 84 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 85 typedef union { // __I to avoid read-modify-write on write-to-clear register 86 struct { 87 __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 88 __I uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ 89 __I uint32_t :30; /*!< bit: 2..31 Reserved */ 90 } bit; /*!< Structure used for bit access */ 91 uint32_t reg; /*!< Type used for register access */ 92 } OSC32KCTRL_INTFLAG_Type; 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 #define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 96 #define OSC32KCTRL_INTFLAG_RESETVALUE _U(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 97 98 #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ 99 #define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) 100 #define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */ 101 #define OSC32KCTRL_INTFLAG_OSC32KRDY (_U(0x1) << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos) 102 #define OSC32KCTRL_INTFLAG_MASK _U(0x00000003) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ 103 104 /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 106 typedef union { 107 struct { 108 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 109 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ 110 uint32_t :30; /*!< bit: 2..31 Reserved */ 111 } bit; /*!< Structure used for bit access */ 112 uint32_t reg; /*!< Type used for register access */ 113 } OSC32KCTRL_STATUS_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ 117 #define OSC32KCTRL_STATUS_RESETVALUE _U(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ 118 119 #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ 120 #define OSC32KCTRL_STATUS_XOSC32KRDY (_U(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) 121 #define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */ 122 #define OSC32KCTRL_STATUS_OSC32KRDY (_U(0x1) << OSC32KCTRL_STATUS_OSC32KRDY_Pos) 123 #define OSC32KCTRL_STATUS_MASK _U(0x00000003) /**< \brief (OSC32KCTRL_STATUS) MASK Register */ 124 125 /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */ 126 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 127 typedef union { 128 struct { 129 uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ 130 uint32_t :29; /*!< bit: 3..31 Reserved */ 131 } bit; /*!< Structure used for bit access */ 132 uint32_t reg; /*!< Type used for register access */ 133 } OSC32KCTRL_RTCCTRL_Type; 134 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 135 136 #define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */ 137 #define OSC32KCTRL_RTCCTRL_RESETVALUE _U(0x00000000) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */ 138 139 #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ 140 #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 141 #define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)) 142 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ 143 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ 144 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val _U(0x2) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 145 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val _U(0x3) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */ 146 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 147 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ 148 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 149 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 150 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 151 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 152 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 153 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 154 #define OSC32KCTRL_RTCCTRL_MASK _U(0x00000007) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ 155 156 /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef union { 159 struct { 160 uint32_t :1; /*!< bit: 0 Reserved */ 161 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 162 uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 163 uint32_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ 164 uint32_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ 165 uint32_t :1; /*!< bit: 5 Reserved */ 166 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 167 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 168 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 169 uint32_t :1; /*!< bit: 11 Reserved */ 170 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 171 uint32_t :19; /*!< bit: 13..31 Reserved */ 172 } bit; /*!< Structure used for bit access */ 173 uint32_t reg; /*!< Type used for register access */ 174 } OSC32KCTRL_XOSC32K_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ 178 #define OSC32KCTRL_XOSC32K_RESETVALUE _U(0x00000080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ 179 180 #define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ 181 #define OSC32KCTRL_XOSC32K_ENABLE (_U(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) 182 #define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ 183 #define OSC32KCTRL_XOSC32K_XTALEN (_U(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) 184 #define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ 185 #define OSC32KCTRL_XOSC32K_EN32K (_U(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) 186 #define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ 187 #define OSC32KCTRL_XOSC32K_EN1K (_U(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) 188 #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ 189 #define OSC32KCTRL_XOSC32K_RUNSTDBY (_U(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) 190 #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ 191 #define OSC32KCTRL_XOSC32K_ONDEMAND (_U(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) 192 #define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ 193 #define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) 194 #define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos)) 195 #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ 196 #define OSC32KCTRL_XOSC32K_WRTLOCK (_U(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) 197 #define OSC32KCTRL_XOSC32K_MASK _U(0x000017DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ 198 199 /* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ 200 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 201 typedef union { 202 struct { 203 uint32_t :1; /*!< bit: 0 Reserved */ 204 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 205 uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ 206 uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ 207 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 208 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 209 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 210 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 211 uint32_t :1; /*!< bit: 11 Reserved */ 212 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 213 uint32_t :3; /*!< bit: 13..15 Reserved */ 214 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ 215 uint32_t :9; /*!< bit: 23..31 Reserved */ 216 } bit; /*!< Structure used for bit access */ 217 uint32_t reg; /*!< Type used for register access */ 218 } OSC32KCTRL_OSC32K_Type; 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 220 221 #define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ 222 #define OSC32KCTRL_OSC32K_RESETVALUE _U(0x003F0080) /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ 223 224 #define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */ 225 #define OSC32KCTRL_OSC32K_ENABLE (_U(0x1) << OSC32KCTRL_OSC32K_ENABLE_Pos) 226 #define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */ 227 #define OSC32KCTRL_OSC32K_EN32K (_U(0x1) << OSC32KCTRL_OSC32K_EN32K_Pos) 228 #define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */ 229 #define OSC32KCTRL_OSC32K_EN1K (_U(0x1) << OSC32KCTRL_OSC32K_EN1K_Pos) 230 #define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */ 231 #define OSC32KCTRL_OSC32K_RUNSTDBY (_U(0x1) << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) 232 #define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */ 233 #define OSC32KCTRL_OSC32K_ONDEMAND (_U(0x1) << OSC32KCTRL_OSC32K_ONDEMAND_Pos) 234 #define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */ 235 #define OSC32KCTRL_OSC32K_STARTUP_Msk (_U(0x7) << OSC32KCTRL_OSC32K_STARTUP_Pos) 236 #define OSC32KCTRL_OSC32K_STARTUP(value) (OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos)) 237 #define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */ 238 #define OSC32KCTRL_OSC32K_WRTLOCK (_U(0x1) << OSC32KCTRL_OSC32K_WRTLOCK_Pos) 239 #define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */ 240 #define OSC32KCTRL_OSC32K_CALIB_Msk (_U(0x7F) << OSC32KCTRL_OSC32K_CALIB_Pos) 241 #define OSC32KCTRL_OSC32K_CALIB(value) (OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos)) 242 #define OSC32KCTRL_OSC32K_MASK _U(0x007F17CE) /**< \brief (OSC32KCTRL_OSC32K) MASK Register */ 243 244 /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ 245 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 246 typedef union { 247 struct { 248 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 249 uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */ 250 uint32_t :2; /*!< bit: 13..14 Reserved */ 251 uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ 252 uint32_t :16; /*!< bit: 16..31 Reserved */ 253 } bit; /*!< Structure used for bit access */ 254 uint32_t reg; /*!< Type used for register access */ 255 } OSC32KCTRL_OSCULP32K_Type; 256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 257 258 #define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 259 260 #define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ 261 #define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U(0x1F) << OSC32KCTRL_OSCULP32K_CALIB_Pos) 262 #define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos)) 263 #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ 264 #define OSC32KCTRL_OSCULP32K_WRTLOCK (_U(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) 265 #define OSC32KCTRL_OSCULP32K_MASK _U(0x00009F00) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ 266 267 /** \brief OSC32KCTRL hardware registers */ 268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 269 typedef struct { 270 __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 271 __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 272 __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 273 __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 274 __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */ 275 __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control */ 276 __IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ 277 __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 278 } Osc32kctrl; 279 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 280 281 /*@}*/ 282 283 #endif /* _SAML21_OSC32KCTRL_COMPONENT_ */ 284
