1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32H7xx_HAL_FLASH_EX_H 20 #define STM32H7xx_HAL_FLASH_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32h7xx_hal_def.h" 28 29 /** @addtogroup STM32H7xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup FLASHEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief FLASH Erase structure definition 44 */ 45 typedef struct 46 { 47 uint32_t TypeErase; /*!< Mass erase or sector Erase. 48 This parameter can be a value of @ref FLASHEx_Type_Erase */ 49 50 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. 51 This parameter must be a value of @ref FLASHEx_Banks */ 52 53 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled 54 This parameter must be a value of @ref FLASH_Sectors */ 55 56 uint32_t NbSectors; /*!< Number of sectors to be erased. 57 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ 58 59 uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism 60 This parameter must be a value of @ref FLASHEx_Voltage_Range */ 61 62 } FLASH_EraseInitTypeDef; 63 64 65 /** 66 * @brief FLASH Option Bytes Program structure definition 67 */ 68 typedef struct 69 { 70 uint32_t OptionType; /*!< Option byte to be configured. 71 This parameter can be a value of @ref FLASHEx_Option_Type */ 72 73 uint32_t WRPState; /*!< Write protection activation or deactivation. 74 This parameter can be a value of @ref FLASHEx_WRP_State */ 75 76 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. 77 The value of this parameter depend on device used within the same series */ 78 79 uint32_t RDPLevel; /*!< Set the read protection level. 80 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ 81 82 uint32_t BORLevel; /*!< Set the BOR Level. 83 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ 84 85 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 86 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ 87 88 uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / 89 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ 90 91 uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . 92 This parameter must be a value of @ref FLASHEx_Banks */ 93 94 uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not 95 when RDP level decreased from Level 1 to Level 0 or during a mass erase. 96 This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ 97 98 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 99 This parameter must be a value between begin and end of a bank */ 100 101 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 102 This parameter must be a value between PCROP Start address and end of a bank */ 103 104 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 105 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ 106 107 uint32_t BootAddr0; /*!< Boot Address 0. 108 This parameter must be a value between begin and end of a bank */ 109 110 uint32_t BootAddr1; /*!< Boot Address 1. 111 This parameter must be a value between begin and end of a bank */ 112 #if defined(DUAL_CORE) 113 uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 114 or both. 115 This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ 116 117 uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0. 118 This parameter must be a value between begin and end of a bank */ 119 120 uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1. 121 This parameter must be a value between begin and end of a bank */ 122 #endif /*DUAL_CORE*/ 123 124 uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not 125 when RDP level decreased from Level 1 to Level 0 or during a mass erase. 126 This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ 127 128 uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. 129 This parameter must be a value between begin address and end address of bank1 */ 130 131 uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. 132 This parameter must be a value between Secure Area Start address and end address of a bank1 */ 133 134 #if defined (FLASH_OTPBL_LOCKBL) 135 uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. 136 This parameter must be a value of @ref FLASHEx_OTP_Blocks */ 137 #endif /* FLASH_OTPBL_LOCKBL */ 138 139 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 140 uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM. 141 This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ 142 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 143 144 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 145 uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost. 146 This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */ 147 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 148 149 } FLASH_OBProgramInitTypeDef; 150 151 /** 152 * @brief FLASH Erase structure definition 153 */ 154 typedef struct 155 { 156 uint32_t TypeCRC; /*!< CRC Selection Type. 157 This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ 158 159 uint32_t BurstSize; /*!< CRC Burst Size. 160 This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ 161 162 uint32_t Bank; /*!< Select bank where CRC computation is enabled. 163 This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ 164 165 uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation 166 This parameter must be a value of @ref FLASH_Sectors */ 167 168 uint32_t NbSectors; /*!< Number of sectors to be computed. 169 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ 170 171 uint32_t CRCStartAddr; /*!< CRC Start address. 172 This parameter must be a value between begin address and end address of a bank */ 173 174 uint32_t CRCEndAddr; /*!< CRC End address. 175 This parameter must be a value between CRC Start address and end address of a bank */ 176 177 } FLASH_CRCInitTypeDef; 178 179 #if (USE_FLASH_ECC == 1U) 180 /** 181 * @brief ECC Info Structure definition 182 */ 183 typedef struct 184 { 185 uint32_t Area; /*!< Area from which an ECC was detected. 186 This parameter can be a value of @ref FLASHEx_ECC_Area */ 187 188 uint32_t Address; /*!< ECC error address */ 189 190 } FLASH_EccInfoTypeDef; 191 #endif /* USE_FLASH_ECC */ 192 193 /** 194 * @} 195 */ 196 /* Exported constants --------------------------------------------------------*/ 197 198 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants 199 * @{ 200 */ 201 202 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase 203 * @{ 204 */ 205 #define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ 206 #define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ 207 /** 208 * @} 209 */ 210 211 #if defined (FLASH_CR_PSIZE) 212 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range 213 * @{ 214 */ 215 #define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ 216 #define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ 217 #define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ 218 #define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ 219 /** 220 * @} 221 */ 222 #endif /* FLASH_CR_PSIZE */ 223 224 /** @defgroup FLASHEx_WRP_State FLASH WRP State 225 * @{ 226 */ 227 #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ 228 #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ 229 /** 230 * @} 231 */ 232 233 #if (USE_FLASH_ECC == 1U) 234 /** @defgroup FLASH_ECC_Area FLASH ECC Area 235 * @brief FLASH ECC Area 236 * @{ 237 */ 238 #define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ 239 #define FLASH_ECC_AREA_USER_BANK2 0x00000001U /*!< FLASH bank 2 area */ 240 /** 241 * @} 242 */ 243 #endif /* USE_FLASH_ECC */ 244 245 /** @defgroup FLASHEx_Option_Type FLASH Option Type 246 * @{ 247 */ 248 #define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ 249 #define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ 250 #define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ 251 #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ 252 #define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ 253 #define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ 254 #if defined (DUAL_CORE) 255 #define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ 256 #define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ 257 #define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ 258 #else /* Single core */ 259 #define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ 260 #endif /*DUAL_CORE*/ 261 #if defined (FLASH_OTPBL_LOCKBL) 262 #define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */ 263 #endif /* FLASH_OTPBL_LOCKBL */ 264 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 265 #define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */ 266 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 267 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 268 #define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */ 269 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 270 271 #if defined (DUAL_CORE) 272 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 273 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 274 OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */ 275 #elif defined (FLASH_OTPBL_LOCKBL) 276 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 277 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 278 OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */ 279 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) 280 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 281 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 282 OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */ 283 #else 284 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 285 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 286 OPTIONBYTE_BOOTADD) /*!< All option byte configuration */ 287 #endif /* DUAL_CORE */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection 293 * @{ 294 */ 295 #define OB_RDP_LEVEL_0 0xAA00U 296 #define OB_RDP_LEVEL_1 0x5500U 297 #define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 298 it s no more possible to go back to level 1 or 0 */ 299 /** 300 * @} 301 */ 302 303 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog 304 * @{ 305 */ 306 #define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */ 307 #define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP 313 * @{ 314 */ 315 #define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ 316 #define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY 322 * @{ 323 */ 324 #define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ 325 #define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP 331 * @{ 332 */ 333 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ 334 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY 340 * @{ 341 */ 342 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ 343 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level 349 * @{ 350 */ 351 #define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ 352 #define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ 353 #define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ 354 #define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ 355 /** 356 * @} 357 */ 358 359 360 361 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address 362 * @{ 363 */ 364 #define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ 365 #define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ 366 #define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ 367 #define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ 368 #define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ 369 #define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ 370 #define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup FLASH_Latency FLASH Latency 376 * @{ 377 */ 378 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ 379 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ 380 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ 381 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ 382 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ 383 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ 384 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ 385 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ 386 387 /* Unused FLASH Latency defines */ 388 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ 389 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ 390 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ 391 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ 392 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ 393 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ 394 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ 395 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ 396 /** 397 * @} 398 */ 399 400 /** @defgroup FLASHEx_Banks FLASH Banks 401 * @{ 402 */ 403 #define FLASH_BANK_1 0x01U /*!< Bank 1 */ 404 #if defined (DUAL_BANK) 405 #define FLASH_BANK_2 0x02U /*!< Bank 2 */ 406 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 407 #endif /* DUAL_BANK */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP 413 * @{ 414 */ 415 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 416 is decreased from Level 1 to Level 0 or during a mass erase */ 417 #define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is 418 decreased from Level 1 to Level 0 (full mass erase) */ 419 420 /** 421 * @} 422 */ 423 424 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection 425 * @{ 426 */ 427 #if (FLASH_SECTOR_TOTAL == 128) 428 #define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ 429 #define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ 430 #define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ 431 #define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ 432 #define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ 433 #define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ 434 #define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ 435 #define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ 436 #define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ 437 #define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ 438 #define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ 439 #define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ 440 #define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ 441 #define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ 442 #define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ 443 #define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ 444 #define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ 445 #define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ 446 #define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ 447 #define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ 448 #define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ 449 #define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ 450 #define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ 451 #define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ 452 #define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ 453 #define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ 454 #define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ 455 #define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ 456 #define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ 457 #define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ 458 #define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ 459 #define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ 460 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ 461 #else 462 #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ 463 #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ 464 #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ 465 #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ 466 #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ 467 #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ 468 #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ 469 #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ 470 #define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ 471 #endif /* FLASH_SECTOR_TOTAL == 128 */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY 477 * @{ 478 */ 479 #define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ 480 #define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE 486 * @{ 487 */ 488 #define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ 489 #define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ 490 #define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ 491 #define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ 492 /** 493 * @} 494 */ 495 496 #if defined(DUAL_CORE) 497 /** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7 498 * @{ 499 */ 500 #define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */ 501 #define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */ 502 503 /** 504 * @} 505 */ 506 507 /** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4 508 * @{ 509 */ 510 #define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */ 511 #define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */ 512 /** 513 * @} 514 */ 515 #endif /* DUAL_CORE */ 516 517 /** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW 518 * @{ 519 */ 520 #define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ 521 #define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ 522 /** 523 * @} 524 */ 525 526 #if defined(DUAL_CORE) 527 /** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW 528 * @{ 529 */ 530 #define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/ 531 #define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/ 532 /** 533 * @} 534 */ 535 #endif 536 537 /** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 538 * @{ 539 */ 540 #define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ 541 #define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ 542 /** 543 * @} 544 */ 545 546 /** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 547 * @{ 548 */ 549 #define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ 550 #define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ 551 /** 552 * @} 553 */ 554 555 #if defined (FLASH_OPTSR_NRST_STOP_D2) 556 /** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 557 * @{ 558 */ 559 #define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */ 560 #define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2 566 * @{ 567 */ 568 #define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */ 569 #define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */ 570 /** 571 * @} 572 */ 573 #endif /* FLASH_OPTSR_NRST_STOP_D2 */ 574 575 #if defined (DUAL_BANK) 576 /** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK 577 * @{ 578 */ 579 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ 580 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ 581 /** 582 * @} 583 */ 584 #endif /* DUAL_BANK */ 585 586 /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV 587 * @{ 588 */ 589 #define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ 590 #define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ 591 /** 592 * @} 593 */ 594 595 #if defined (FLASH_OPTSR_VDDMMC_HSLV) 596 /** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV 597 * @{ 598 */ 599 #define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */ 600 #define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */ 601 /** 602 * @} 603 */ 604 #endif /* FLASH_OPTSR_VDDMMC_HSLV */ 605 606 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 607 /** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST 608 * @{ 609 */ 610 #define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */ 611 #define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */ 612 /** 613 * @} 614 */ 615 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 616 617 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 618 /** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED 619 * @{ 620 */ 621 #define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */ 622 #define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */ 623 #define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */ 624 #define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */ 625 /** 626 * @} 627 */ 628 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 629 630 /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type 631 * @{ 632 */ 633 #define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ 634 #define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ 635 #define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ 636 #define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ 637 #define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ 638 #define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ 639 #define OB_USER_SECURITY 0x0040U /*!< security selection */ 640 #define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ 641 #if defined (DUAL_BANK) 642 #define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ 643 #endif /* DUAL_BANK */ 644 #if defined (FLASH_OPTSR_VDDMMC_HSLV) 645 #define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */ 646 #endif /* FLASH_OPTSR_VDDMMC_HSLV */ 647 #if defined (DUAL_CORE) 648 #define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ 649 #define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ 650 #define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ 651 #endif /*DUAL_CORE*/ 652 #if defined (FLASH_OPTSR_NRST_STOP_D2) 653 #define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */ 654 #define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */ 655 #endif /* FLASH_OPTSR_NRST_STOP_D2 */ 656 657 #if defined (DUAL_CORE) 658 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 659 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 660 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ 661 OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ 662 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) 663 #elif defined (FLASH_OPTSR_VDDMMC_HSLV) 664 #if defined (DUAL_BANK) 665 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 666 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 667 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ 668 OB_USER_VDDMMC_HSLV) 669 #else 670 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 671 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 672 OB_USER_SECURITY | OB_USER_IOHSLV |\ 673 OB_USER_VDDMMC_HSLV) 674 #endif /* DUAL_BANK */ 675 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) 676 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 677 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 678 OB_USER_SECURITY | OB_USER_IOHSLV |\ 679 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) 680 #else /* Single core */ 681 #if defined (DUAL_BANK) 682 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 683 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 684 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) 685 #else 686 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 687 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 688 OB_USER_SECURITY | OB_USER_IOHSLV ) 689 #endif /* DUAL_BANK */ 690 #endif /* DUAL_CORE */ 691 /** 692 * @} 693 */ 694 695 /** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION 696 * @{ 697 */ 698 #define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ 699 #define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ 700 #define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ 701 /** 702 * @} 703 */ 704 705 /** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP 706 * @{ 707 */ 708 #define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level 709 is decreased from Level 1 to Level 0 or during a mass erase */ 710 #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is 711 decreased from Level 1 to Level 0 (full mass erase) */ 712 /** 713 * @} 714 */ 715 716 /** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type 717 * @{ 718 */ 719 #define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ 720 #define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ 721 #define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ 722 /** 723 * @} 724 */ 725 726 /** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size 727 * @{ 728 */ 729 #define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ 730 #define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ 731 #define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ 732 #define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ 733 /** 734 * @} 735 */ 736 737 /** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay 738 * @{ 739 */ 740 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ 741 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ 742 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ 743 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ 744 /** 745 * @} 746 */ 747 748 #if defined (FLASH_OTPBL_LOCKBL) 749 /** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks 750 * @{ 751 */ 752 #define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ 753 #define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ 754 #define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ 755 #define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ 756 #define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ 757 #define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ 758 #define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ 759 #define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ 760 #define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ 761 #define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ 762 #define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ 763 #define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ 764 #define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ 765 #define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ 766 #define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ 767 #define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ 768 #define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */ 769 /** 770 * @} 771 */ 772 #endif /* FLASH_OTPBL_LOCKBL */ 773 /** 774 * @} 775 */ 776 777 /* Exported macro ------------------------------------------------------------*/ 778 /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros 779 * @{ 780 */ 781 /** 782 * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) 783 * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. 784 * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) 785 * @retval The FLASH Boot Base Address 786 */ 787 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) 788 789 #if defined (FLASH_CR_PSIZE) 790 /** 791 * @brief Set the FLASH Program/Erase parallelism. 792 * @param __PSIZE__ FLASH Program/Erase parallelism 793 * This parameter can be a value of @ref FLASH_Program_Parallelism 794 * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) 795 * @retval none 796 */ 797 #if defined (DUAL_BANK) 798 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ 799 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ 800 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) 801 #else 802 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) 803 #endif /* DUAL_BANK */ 804 805 /** 806 * @brief Get the FLASH Program/Erase parallelism. 807 * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) 808 * @retval FLASH Program/Erase parallelism 809 * This return value can be a value of @ref FLASH_Program_Parallelism 810 */ 811 #if defined (DUAL_BANK) 812 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ 813 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ 814 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) 815 #else 816 #define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) 817 #endif /* DUAL_BANK */ 818 819 #endif /* FLASH_CR_PSIZE */ 820 821 /** 822 * @brief Set the FLASH Programming Delay. 823 * @param __DELAY__ FLASH Programming Delay 824 * This parameter can be a value of @ref FLASHEx_Programming_Delay 825 * @retval none 826 */ 827 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) 828 829 /** 830 * @brief Get the FLASH Programming Delay. 831 * @retval FLASH Programming Delay 832 * This return value can be a value of @ref FLASHEx_Programming_Delay 833 */ 834 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) 835 /** 836 * @} 837 */ 838 839 /* Exported functions --------------------------------------------------------*/ 840 /** @addtogroup FLASHEx_Exported_Functions 841 * @{ 842 */ 843 844 /** @addtogroup FLASHEx_Exported_Functions_Group1 845 * @{ 846 */ 847 /* Extension Program operation functions *************************************/ 848 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); 849 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 850 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 851 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 852 853 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); 854 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); 855 #if defined (DUAL_BANK) 856 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); 857 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); 858 #endif /* DUAL_BANK */ 859 860 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); 861 862 /** 863 * @} 864 */ 865 866 #if (USE_FLASH_ECC == 1U) 867 /** @addtogroup FLASHEx_Exported_Functions_Group3 868 * @{ 869 */ 870 void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); 871 void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); 872 void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void); 873 void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void); 874 #if defined (DUAL_BANK) 875 void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void); 876 void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void); 877 #endif /* DUAL_BANK */ 878 879 void HAL_FLASHEx_EnableEccDetectionInterrupt(void); 880 void HAL_FLASHEx_DisableEccDetectionInterrupt(void); 881 void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void); 882 void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void); 883 #if defined (DUAL_BANK) 884 void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void); 885 void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void); 886 #endif /* DUAL_BANK */ 887 888 void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); 889 void HAL_FLASHEx_BusFault_IRQHandler(void); 890 891 __weak void HAL_FLASHEx_EccDetectionCallback(void); 892 __weak void HAL_FLASHEx_EccCorrectionCallback(void); 893 /** 894 * @} 895 */ 896 #endif /* USE_FLASH_ECC */ 897 898 /** 899 * @} 900 */ 901 /* Private types -------------------------------------------------------------*/ 902 /* Private variables ---------------------------------------------------------*/ 903 /* Private constants ---------------------------------------------------------*/ 904 /* Private macros ------------------------------------------------------------*/ 905 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 906 * @{ 907 */ 908 909 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters 910 * @{ 911 */ 912 913 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 914 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 915 916 #if defined (FLASH_CR_PSIZE) 917 #define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ 918 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ 919 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ 920 ((RANGE) == FLASH_VOLTAGE_RANGE_4)) 921 #endif /* FLASH_CR_PSIZE */ 922 923 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ 924 ((VALUE) == OB_WRPSTATE_ENABLE)) 925 926 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ 927 (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) 928 929 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) 930 931 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 932 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 933 ((LEVEL) == OB_RDP_LEVEL_2)) 934 935 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) 936 937 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) 938 939 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) 940 941 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) 942 943 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) 944 945 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ 946 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) 947 948 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 949 ((LATENCY) == FLASH_LATENCY_1) || \ 950 ((LATENCY) == FLASH_LATENCY_2) || \ 951 ((LATENCY) == FLASH_LATENCY_3) || \ 952 ((LATENCY) == FLASH_LATENCY_4) || \ 953 ((LATENCY) == FLASH_LATENCY_5) || \ 954 ((LATENCY) == FLASH_LATENCY_6) || \ 955 ((LATENCY) == FLASH_LATENCY_7) || \ 956 ((LATENCY) == FLASH_LATENCY_8) || \ 957 ((LATENCY) == FLASH_LATENCY_9) || \ 958 ((LATENCY) == FLASH_LATENCY_10) || \ 959 ((LATENCY) == FLASH_LATENCY_11) || \ 960 ((LATENCY) == FLASH_LATENCY_12) || \ 961 ((LATENCY) == FLASH_LATENCY_13) || \ 962 ((LATENCY) == FLASH_LATENCY_14) || \ 963 ((LATENCY) == FLASH_LATENCY_15)) 964 965 #define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) 966 967 #if (FLASH_SECTOR_TOTAL == 8U) 968 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) 969 #else 970 #define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U) 971 #endif /* FLASH_SECTOR_TOTAL == 8U */ 972 973 #define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ 974 ((CONFIG) == OB_PCROP_RDP_ERASE)) 975 976 #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ 977 ((CONFIG) == OB_SECURE_RDP_ERASE)) 978 979 #if defined (DUAL_BANK) 980 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 981 #endif /* DUAL_BANK */ 982 983 #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) 984 985 #if defined (FLASH_OPTSR_VDDMMC_HSLV) 986 #define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE)) 987 #endif /* FLASH_OPTSR_VDDMMC_HSLV */ 988 989 #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) 990 #if defined (DUAL_CORE) 991 #define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) 992 #endif /* DUAL_CORE */ 993 #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) 994 995 #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) 996 997 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) 998 999 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) 1000 1001 #define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ 1002 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) 1003 1004 #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) 1005 1006 #if defined (DUAL_CORE) 1007 #define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) 1008 1009 #define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) 1010 #endif /* DUAL_CORE */ 1011 1012 #if defined (FLASH_OPTSR_NRST_STOP_D2) 1013 #define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) 1014 1015 #define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) 1016 #endif /* FLASH_OPTSR_NRST_STOP_D2 */ 1017 1018 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 1019 #define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \ 1020 ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB)) 1021 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 1022 1023 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 1024 #define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE)) 1025 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 1026 1027 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ 1028 (((TYPE) & ~OB_USER_ALL) == 0U)) 1029 1030 #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ 1031 ((VALUE) == OB_BOOT_ADD1) || \ 1032 ((VALUE) == OB_BOOT_ADD_BOTH)) 1033 1034 #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ 1035 ((VALUE) == FLASH_CRC_SECTORS) || \ 1036 ((VALUE) == FLASH_CRC_BANK)) 1037 1038 #if defined (FLASH_OTPBL_LOCKBL) 1039 #define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U)) 1040 #endif /* FLASH_OTPBL_LOCKBL */ 1041 /** 1042 * @} 1043 */ 1044 1045 /** 1046 * @} 1047 */ 1048 1049 /* Private functions ---------------------------------------------------------*/ 1050 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 1051 * @{ 1052 */ 1053 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); 1054 /** 1055 * @} 1056 */ 1057 1058 /** 1059 * @} 1060 */ 1061 1062 /** 1063 * @} 1064 */ 1065 1066 #ifdef __cplusplus 1067 } 1068 #endif 1069 1070 #endif /* STM32H7xx_HAL_FLASH_EX_H */ 1071 1072
