1 /**************************************************************************//** 2 * @file opa_reg.h 3 * @version V1.00 4 * @brief OPA register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 * 9 *****************************************************************************/ 10 #ifndef __OPA_REG_H__ 11 #define __OPA_REG_H__ 12 13 #if defined ( __CC_ARM ) 14 #pragma anon_unions 15 #endif 16 17 /** 18 @addtogroup REGISTER Control Register 19 @{ 20 */ 21 22 /** 23 @addtogroup OPA OP Amplifier(OPA) 24 Memory Mapped Structure for OPA Controller 25 @{ */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var OPA_T::CTL 33 * Offset: 0x00 OP Amplifier Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |OPEN0 |OP Amplifier 0 Enable Bit 38 * | | |0 = OP amplifier 0 Disabled. 39 * | | |1 = OP amplifier 0 Enabled. 40 * | | |Note: OP amplifier 0 output needs wait stable 20us after OPEN0 is set. 41 * |[1] |OPEN1 |OP Amplifier 1 Enable Bit 42 * | | |0 = OP amplifier 1 Disabled. 43 * | | |1 = OP amplifier 1 Enabled. 44 * | | |Note: OP amplifier 1 output needs wait stable 20us after OPEN1 is set. 45 * |[2] |OPEN2 |OP Amplifier 2 Enable Bit 46 * | | |0 = OP amplifier 2 Disabled. 47 * | | |1 = OP amplifier 2 Enabled. 48 * | | |Note: OP amplifier 2 output needs wait stable 20us after OPEN2 is set. 49 * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit 50 * | | |0 = OP amplifier 0 schmitt trigger non-invert buffer Disabled. 51 * | | |1 = OP amplifier 0 schmitt trigger non-invert buffer Enabled. 52 * |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit 53 * | | |0 = OP amplifier 1 schmitt trigger non-invert buffer Disabled. 54 * | | |1 = OP amplifier 1 schmitt trigger non-invert buffer Enabled. 55 * |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit 56 * | | |0 = OP amplifier 2 schmitt trigger non-invert buffer Disabled. 57 * | | |1 = OP amplifier 2 schmitt trigger non-invert buffer Enabled. 58 * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit 59 * | | |0 = OP amplifier 0 digital output interrupt function Disabled. 60 * | | |1 = OP amplifier 0 digital output interrupt function Enabled. 61 * | | |Note: The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, an OPA interrupt request is generated. 62 * |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit 63 * | | |0 = OP amplifier 1 digital output interrupt function Disabled. 64 * | | |1 = OP amplifier 1 digital output interrupt function Enabled. 65 * | | |Note: The OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, an OPA interrupt request is generated. 66 * |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit 67 * | | |0 = OP amplifier 2 digital output interrupt function Disabled. 68 * | | |1 = OP amplifier 2 digital output interrupt function Enabled. 69 * | | |Note: The OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, an OPA interrupt request is generated. 70 * |[12] |OPDOWKE0 |OP Amplifier 0 Schmitt Trigger Digital Output Wake-up Enable Bit 71 * | | |0 = OP amplifier 0 digital output wake-up function Disabled. 72 * | | |1 = OP amplifier 0 digital output wake-up function Enabled. 73 * | | |Note: If OPDOWKE0 is set to 1 and the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in power-down mode, an OPA wake-up is generated. 74 * |[13] |OPDOWKE1 |OP Amplifier 1 Schmitt Trigger Digital Output Wake-up Enable Bit 75 * | | |0 = OP amplifier 1 digital output wake-up function Disabled. 76 * | | |1 = OP amplifier 1 digital output wake-up function Enabled. 77 * | | |Note: If OPDOWKE1 is set to 1 and the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in power-down mode, an OPA wake-up is generated. 78 * |[14] |OPDOWKE2 |OP Amplifier 2 Schmitt Trigger Digital Output Wake-up Enable Bit 79 * | | |0 = OP amplifier 2 digital output wake-up function Disabled. 80 * | | |1 = OP amplifier 2 digital output wake-up function Enabled. 81 * | | |Note: If OPDOWKE2 is set to 1 and the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state in power-down mode, an OPA wake-up is generated. 82 * @var OPA_T::MODE0 83 * Offset: 0x04 OP Amplifier Mode Control Register0 84 * --------------------------------------------------------------------------------------------------- 85 * |Bits |Field |Descriptions 86 * | :----: | :----: | :---- | 87 * |[3:0] |POSCHEN |OP Amplifier 0 Positvie Input Channel Enable Bit 88 * | | |00000 = disable all positive input channel. 89 * | | |00001 = enable OPA0_P0. 90 * | | |00010 = enable OPA0_P1. 91 * | | |00100 = enable DAC0_OUT. 92 * | | |01000 = enable DAC1_OUT. 93 * | | |10000 = enable OPA1_int_OUT. 94 * | | |Note 1: OPA1_int_OUT means the input from OPA1 internal output 95 * | | |Note 2: For example: if POSCHEN is selected as 00011, PGA0_P0 and PGA0_P1 are both enabled. 96 * |[11:8] |NEGCHEN |OP Amplifier 0 Negative Input Channel Enable Bit 97 * | | |0000 = disable all negative input channel. 98 * | | |0001 = OPA0_N0. 99 * | | |0010 = OPA0_N1. 100 * | | |0100 = OPA1_int_OUT. 101 * | | |1000 = Vf_int. 102 * | | |Note 1: OPA_int_OUT means the input from OPA1 internal output 103 * | | |Note 2: For example: if NEGCHEN is selected as 0011, OPA0_N0 and OPA0_N1 are both enabled. 104 * |[18:16] |GAIN |OP Amplifier 0 Gain Control 105 * | | |3'b000: normal mode 106 * | | |3'b001: Gain x1 107 * | | |3'b010: Gain x2 108 * | | |3'b011: Gain x4 109 * | | |3'b100: Gain x8 110 * | | |3'b101: Gain x16 111 * | | |3'b110: Gian x32 112 * | | |3'b111: Reserved 113 * | | |Note: when inverting gain setting, these bits represent gain -1x, -3x, -5x, -7x, -15x, -31x from GIAIN = 3'b001 to 3'b110 respectively. 114 * |[20] |OUTOE |OP Amplifier 0 Output Enable Bit 115 * | | |0 = OP Amplifier 0 Output floating. 116 * | | |1 = OP Amplifier 0 Output to PAD. 117 * |[23] |LMODE |Low Power Mode Enable Bit 118 * | | |0= OPA operate at normal mode. 119 * | | |1= OPA operate at low power mode. 120 * |[25:24] |SWSEL |OP Amplifier 0 Resistor End Switch Selection 121 * | | |00 = input channel from OPA0 negative channel 0 (OPA0_N0) is enabled. 122 * | | |01 = input channel connected to AVSS is enabled. 123 * | | |10 = input channel connected to OPA1_int_OUT is enabled. 124 * | | |11 = Reserved. 125 * @var OPA_T::MODE1 126 * Offset: 0x08 OP Amplifier Mode Control Register1 127 * --------------------------------------------------------------------------------------------------- 128 * |Bits |Field |Descriptions 129 * | :----: | :----: | :---- | 130 * |[3:0] |POSCHEN |OP Amplifier 1 Positvie Input Channel Enable Bit 131 * | | |00000 = disable all positive input channel. 132 * | | |00001 = OPA1_P0. 133 * | | |00010 = OPA1_P1. 134 * | | |00100 = DAC0_OUT. 135 * | | |01000 = DAC1_OUT. 136 * | | |10000 = OPA0_int_OUT. 137 * | | |Note 1: OPA0_int_OUT means the input from OPA0 internal output 138 * | | |Note 2: For example: if POSCHEN is selected as 00011, PGA1_P0 and PGA1_P1 are both enabled. 139 * |[11:8] |NEGCHEN |OP Amplifier 1 Negative Input Channel Enable Bit 140 * | | |0000 = disable all negative input channel. 141 * | | |0001 = OPA1_N0. 142 * | | |0010 = OPA1_N1. 143 * | | |0100 = OPA0_int_OUT. 144 * | | |1000 = Vf_int. 145 * | | |Note 1: OPA0_int_OUT means the input from OPA0 internal output 146 * | | |Note 2: For example: if NEGCHEN is selected as 0011, PGA1_N0 and PGA1_N1 are both enabled. 147 * |[18:16] |GAIN |OP Amplifier 1 Gain Control 148 * | | |3'b000: normal mode 149 * | | |3'b001: Gain x1 150 * | | |3'b010: Gain x2 151 * | | |3'b011: Gain x4 152 * | | |3'b100: Gain x8 153 * | | |3'b101: Gain x16 154 * | | |3'b110: Gian x32 155 * | | |3'b111: Reserved 156 * | | |Note: when inverting gain setting, these bits represent gain -1x, -3x, -5x, -7x, -15x, -31x from GIAIN = 3'b001 to 3'b110 respectively. 157 * |[20] |OUTOE |OP Amplifier 1 Output Enable Bit 158 * | | |0 = OP Amplifier 1 Output floating. 159 * | | |1 = OP Amplifier 1 Output to PAD. 160 * |[23] |LMODE |Low Power Mode Enable Bit 161 * | | |0= OPA operates at normal mode. 162 * | | |1= OPA operates at low power mode. 163 * |[25:24] |SWSEL |OP Amplifier Resistor End Switch Selection 164 * | | |00 = input channel from OPA1 negative channel 0 (OPA1_N0) is enabled. 165 * | | |01 = input channel connected to AVSS is enabled. 166 * | | |10 = input channel connected to OPA0_int_OUT is enabled. 167 * | | |11 = Reserved. 168 * @var OPA_T::MODE2 169 * Offset: 0x0C OP Amplifier Mode Control Register2 170 * --------------------------------------------------------------------------------------------------- 171 * |Bits |Field |Descriptions 172 * | :----: | :----: | :---- | 173 * |[4:0] |POSCHEN |OP Amplifier 2 Positvie Input Channel Enable Bit 174 * | | |00000 = disable all positive input channel. 175 * | | |00001 = OPA2_P0. 176 * | | |00010 = OPA2_P1. 177 * | | |00100 = DAC0_OUT. 178 * | | |01000 = DAC1_OUT. 179 * | | |10000 = OPA1_int_OUT. 180 * | | |Note 1: OPA1_int_OUT means the input from OPA1 internal output 181 * | | |Note 2: For example: if POSCHEN is selected as 00011, PGA2_P0 and PGA2_P1 are both enabled. 182 * |[11:8] |NEGCHEN |OP Amplifier 2 Negative Input Channel Enable Bit 183 * | | |0000 = disable all negative input channel. 184 * | | |0001 = OPA2_N0. 185 * | | |0010 = OPA2_N1. 186 * | | |0100 = OPA1_int_OUT. 187 * | | |1000 = Vf_int. 188 * | | |Note 1: OPA1_int_OUT means the input from OPA1 internal output 189 * | | |Note 2: For example: if NEGCHEN is selected as 0011, PGA2_N0 and PGA2_N1 are both enabled. 190 * |[18:16] |GAIN |OP Amplifier 2 Gain Control 191 * | | |3'b000: normal mode 192 * | | |3'b001: Gain x1 193 * | | |3'b010: Gain x2 194 * | | |3'b011: Gain x4 195 * | | |3'b100: Gain x8 196 * | | |3'b101: Gain x16 197 * | | |3'b110: Gian x32 198 * | | |3'b111: Reserved 199 * | | |Note: when inverting gain setting, these bits represent gain -1x, -3x, -5x, -7x, -15x, -31x from GIAIN = 3'b001 to 3'b110 respectively. 200 * |[20] |OUTOE |OP Amplifier 2 Output Enable Bit 201 * | | |0 = OP Amplifier 2 Output floating. 202 * | | |1 = OP Amplifier 2 Output to PAD. 203 * |[23] |LMODE |Low Power Mode Enable Bit 204 * | | |0= OPA operate at normal mode. 205 * | | |1= OPA operate at low power mode. 206 * |[25:24] |SWSEL |OP Amplifier Resistor End Switch Selection 207 * | | |00 = input channel from OPA2 negative channel 0 (OPA2_N0) is enabled. 208 * | | |01 = input channel connected to AVSS is enabled. 209 * | | |10 = input channel connected to OPA1_int_OUT is enabled. 210 * | | |11 = Reserved. 211 * @var OPA_T::STATUS 212 * Offset: 0x20 OP Amplifier Status Register 213 * --------------------------------------------------------------------------------------------------- 214 * |Bits |Field |Descriptions 215 * | :----: | :----: | :---- | 216 * |[0] |OPDO0 |OP Amplifier 0 Digital Output 217 * | | |Synchronized to the APB clock to allow reading by software 218 * | | |Cleared when the Schmitt trigger buffer is disabled (OPDOEN0 = 0) 219 * |[1] |OPDO1 |OP Amplifier 1 Digital Output 220 * | | |Synchronized to the APB clock to allow reading by software 221 * | | |Cleared when the Schmitt trigger buffer is disabled (OPDOEN1 = 0) 222 * |[2] |OPDO2 |OP Amplifier 2 Digital Output 223 * | | |Synchronized to the APB clock to allow reading by software 224 * | | |Cleared when the Schmitt trigger buffer is disabled (OPDOEN2 = 0) 225 * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag 226 * | | |If chip is not in power-down mode, OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state 227 * | | |If chip is in power-down mode, OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state and OPDOWKE0 is set to 1 228 * | | |This bit is cleared by writing 1 to it. 229 * |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag 230 * | | |If chip is not in power-down mode, OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state 231 * | | |If chip is in power-down mode, OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state and OPDOWKE1 is set to 1 232 * | | |This bit is cleared by writing 1 to it. 233 * |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag 234 * | | |If chip is not in power-down mode, OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state 235 * | | |If chip is in power-down mode, OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state and OPDOWKE2 is set to 1 236 * | | |This bit is cleared by writing 1 to it. 237 * |[8] |OPDOWKF0 |OP Amplifier 0 Schmitt Trigger Digital Output Wake-Up Flag 238 * | | |OPDOWKF0 wake-up flag is set by hardware whenever OPDOWKE0 is set to 1 and the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in chip power-down mode 239 * | | |This bit is cleared by writing 1 to it. 240 * |[9] |OPDOWKF1 |OP Amplifier 1 Schmitt Trigger Digital Output Wake-Up Flag 241 * | | |OPDOWKF1 wake-up flag is set by hardware whenever OPDOWKE1 is set to 1 and the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in chip power-down mode 242 * | | |This bit is cleared by writing 1 to it. 243 * |[10] |OPDOWKF2 |OP Amplifier 2 Schmitt Trigger Digital Output Wake-Up Flag 244 * | | |OPDOWKF2 wake-up flag is set by hardware whenever OPDOWKE2 is set to 1 and the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state in chip power-down mode 245 * | | |This bit is cleared by writing 1 to it. 246 * @var OPA_T::CALCTL 247 * Offset: 0x24 OP Amplifier Calibration Control Register 248 * --------------------------------------------------------------------------------------------------- 249 * |Bits |Field |Descriptions 250 * | :----: | :----: | :---- | 251 * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit 252 * | | |0 = Calibration is stopped. 253 * | | |1 = Calibration is triggered. 254 * | | |Note 1: Before this bit is enabled, OPEN0 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 255 * | | |Note 2: Hardware will auto clear this bit when calibration is finished. 256 * |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit 257 * | | |0 = Calibration is stopped. 258 * | | |1 = Calibration is triggered. 259 * | | |Note 1: Before this bit is enabled, OPEN1 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 260 * | | |Note 2: Hardware will auto clear this bit when calibration is finished. 261 * |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit 262 * | | |0 = Calibration is stopped,. 263 * | | |1 = Calibration is triggered. 264 * | | |Note 1: Before this bit is enabled, OPEN2 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 265 * | | |Note 2: Hardware will auto clear this bit when calibration is finished. 266 * |[5:4] |CALCLK0 |OP Amplifier 0 Calibration Clock Rate Selection 267 * | | |00 = 1 kHz. 268 * | | |01 = Reserved. 269 * | | |10 = Reserved. 270 * | | |11 = Reserved. 271 * |[7:6] |CALCLK1 |OP Amplifier 1 Calibration Clock Rate Selection 272 * | | |00 = 1 kHz. 273 * | | |01 = Reserved. 274 * | | |10 = Reserved. 275 * | | |11 = Reserved. 276 * |[9:8] |CALCLK2 |OP Amplifier 2 Calibration Clock Rate Selection 277 * | | |00 = 1 kHz. 278 * | | |01 = Reserved. 279 * | | |10 = Reserved. 280 * | | |11 = Reserved. 281 * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection 282 * | | |0 = VREF is AVDD. 283 * | | |1 = VREF from high vcm to low vcm. 284 * |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection 285 * | | |0 = VREF is AVDD. 286 * | | |1 = VREF from high vcm to low vcm. 287 * |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection 288 * | | |0 = VREF is AVDD. 289 * | | |1 = VREF from high vcm to low vcm. 290 * |[24] |TRIMOPT0 |OPA0 Calibration Trim Option 291 * | | |0 = Calibration trim from NMOS to PMOS 292 * | | |1 = Calibration trim from PMOS to NMOS 293 * | | |Note: This option is only effective when CALRVS0 = 0 (OPA_CALCTL[4]) 294 * |[25] |TRIMOPT1 |OPA1 Calibration Trim Option 295 * | | |0 = Calibration trim from NMOS to PMOS. 296 * | | |1 = Calibration trim from PMOS to NMOS. 297 * | | |Note: This option is only effective when CALRVS1 = 0 (OPA_CALCTL[5]) 298 * |[26] |TRIMOPT2 |OPA2 Calibration Trim Option 299 * | | |0 = Calibration trim from NMOS to PMOS. 300 * | | |1 = Calibration trim from PMOS to NMOS. 301 * | | |Note: This option is only effective when CALRVS2 = 0 (OPA_CALCTL[6]) 302 * @var OPA_T::CALST 303 * Offset: 0x28 OP Amplifier Calibration Status Register 304 * --------------------------------------------------------------------------------------------------- 305 * |Bits |Field |Descriptions 306 * | :----: | :----: | :---- | 307 * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status 308 * | | |0 = Calibrating. 309 * | | |1 = Calibration Done. 310 * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS 311 * | | |0 = Pass. 312 * | | |1 = Fail. 313 * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS 314 * | | |0 = Pass. 315 * | | |1 = Fail. 316 * |[4] |DONE1 |OP Amplifier 1 Calibration Done Status 317 * | | |0 = Calibrating. 318 * | | |1 = Calibration Done. 319 * |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS 320 * | | |0 = Pass. 321 * | | |1 = Fail. 322 * |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS 323 * | | |0 = Pass. 324 * | | |1 = Fail. 325 * |[8] |DONE2 |OP Amplifier 2 Calibration Done Status 326 * | | |0 = Calibrating. 327 * | | |1 = Calibration Done. 328 * |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS 329 * | | |0 = Pass. 330 * | | |1 = Fail. 331 * |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS 332 * | | |0 = Pass. 333 * | | |1 = Fail. 334 */ 335 __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */ 336 __IO uint32_t MODE0; /*!< [0x0004] OP Amplifier Mode Control Register0 */ 337 __IO uint32_t MODE1; /*!< [0x0008] OP Amplifier Mode Control Register1 */ 338 __IO uint32_t MODE2; /*!< [0x000c] OP Amplifier Mode Control Register2 */ 339 __I uint32_t RESERVE0[4]; 340 __IO uint32_t STATUS; /*!< [0x0020] OP Amplifier Status Register */ 341 __IO uint32_t CALCTL; /*!< [0x0024] OP Amplifier Calibration Control Register */ 342 __I uint32_t CALST; /*!< [0x0028] OP Amplifier Calibration Status Register */ 343 344 } OPA_T; 345 346 /** 347 @addtogroup OPA_CONST OPA Bit Field Definition 348 Constant Definitions for OPA Controller 349 @{ */ 350 351 #define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */ 352 #define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */ 353 354 #define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */ 355 #define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */ 356 357 #define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */ 358 #define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */ 359 360 #define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */ 361 #define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */ 362 363 #define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */ 364 #define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */ 365 366 #define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */ 367 #define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */ 368 369 #define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */ 370 #define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */ 371 372 #define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */ 373 #define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */ 374 375 #define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */ 376 #define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */ 377 378 #define OPA_CTL_OPDOWKE0_Pos (12) /*!< OPA_T::CTL: OPDOWKE0 Position */ 379 #define OPA_CTL_OPDOWKE0_Msk (0x1ul << OPA_CTL_OPDOWKE0_Pos) /*!< OPA_T::CTL: OPDOWKE0 Mask */ 380 381 #define OPA_CTL_OPDOWKE1_Pos (13) /*!< OPA_T::CTL: OPDOWKE1 Position */ 382 #define OPA_CTL_OPDOWKE1_Msk (0x1ul << OPA_CTL_OPDOWKE1_Pos) /*!< OPA_T::CTL: OPDOWKE1 Mask */ 383 384 #define OPA_CTL_OPDOWKE2_Pos (14) /*!< OPA_T::CTL: OPDOWKE2 Position */ 385 #define OPA_CTL_OPDOWKE2_Msk (0x1ul << OPA_CTL_OPDOWKE2_Pos) /*!< OPA_T::CTL: OPDOWKE2 Mask */ 386 387 #define OPA_MODE_POSCHEN_Pos (0) /*!< OPA_T::MODE0: POSCHEN Position */ 388 #define OPA_MODE_POSCHEN_Msk (0x1fUL << OPA_MODE_POSCHEN_Pos) /*!< OPA_T::MODE0: POSCHEN Mask */ 389 390 #define OPA_MODE_NEGCHEN_Pos (8) /*!< OPA_T::MODE0: NEGCHEN Position */ 391 #define OPA_MODE_NEGCHEN_Msk (0xfUL << OPA_MODE_NEGCHEN_Pos) /*!< OPA_T::MODE0: NEGCHEN Mask */ 392 393 #define OPA_MODE_GAIN_Pos (16) /*!< OPA_T::MODE0: GAIN Position */ 394 #define OPA_MODE_GAIN_Msk (0x7UL << OPA_MODE_GAIN_Pos) /*!< OPA_T::MODE0: GAIN Mask */ 395 396 #define OPA_MODE_OUTOE_Pos (20) /*!< OPA_T::MODE0: OUTOE Position */ 397 #define OPA_MODE_OUTOE_Msk (0x1UL << OPA_MODE_OUTOE_Pos) /*!< OPA_T::MODE0: OUTOE Mask */ 398 399 #define OPA_MODE_LMODE_Pos (23) /*!< OPA_T::MODE0: LMODE Position */ 400 #define OPA_MODE_LMODE_Msk (0x1UL << OPA_MODE_LMODE_Pos) /*!< OPA_T::MODE0: LMODE Mask */ 401 402 #define OPA_MODE_SWSEL_Pos (24) /*!< OPA_T::MODE0: SWSEL Position */ 403 #define OPA_MODE_SWSEL_Msk (0x3UL << OPA_MODE_SWSEL_Pos) /*!< OPA_T::MODE0: SWSEL Mask */ 404 405 #define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */ 406 #define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */ 407 408 #define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */ 409 #define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */ 410 411 #define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */ 412 #define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */ 413 414 #define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */ 415 #define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */ 416 417 #define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */ 418 #define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */ 419 420 #define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */ 421 #define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */ 422 423 #define OPA_STATUS_OPDOWKF0_Pos (8) /*!< OPA_T::STATUS: OPDOWKF0 Position */ 424 #define OPA_STATUS_OPDOWKF0_Msk (0x1ul << OPA_STATUS_OPDOWKF0_Pos) /*!< OPA_T::STATUS: OPDOWKF0 Mask */ 425 426 #define OPA_STATUS_OPDOWKF1_Pos (9) /*!< OPA_T::STATUS: OPDOWKF1 Position */ 427 #define OPA_STATUS_OPDOWKF1_Msk (0x1ul << OPA_STATUS_OPDOWKF1_Pos) /*!< OPA_T::STATUS: OPDOWKF1 Mask */ 428 429 #define OPA_STATUS_OPDOWKF2_Pos (10) /*!< OPA_T::STATUS: OPDOWKF2 Position */ 430 #define OPA_STATUS_OPDOWKF2_Msk (0x1ul << OPA_STATUS_OPDOWKF2_Pos) /*!< OPA_T::STATUS: OPDOWKF2 Mask */ 431 432 #define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */ 433 #define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */ 434 435 #define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */ 436 #define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */ 437 438 #define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */ 439 #define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */ 440 441 #define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */ 442 #define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */ 443 444 #define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */ 445 #define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */ 446 447 #define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */ 448 #define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */ 449 450 #define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */ 451 #define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */ 452 453 #define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */ 454 #define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */ 455 456 #define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */ 457 #define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */ 458 459 #define OPA_CALCTL_TRIMOPT0_Pos (24) /*!< OPA_T::CALCTL: TRIMOPT0 Position */ 460 #define OPA_CALCTL_TRIMOPT0_Msk (0x1ul << OPA_CALCTL_TRIMOPT0_Pos) /*!< OPA_T::CALCTL: TRIMOPT0 Mask */ 461 462 #define OPA_CALCTL_TRIMOPT1_Pos (25) /*!< OPA_T::CALCTL: TRIMOPT1 Position */ 463 #define OPA_CALCTL_TRIMOPT1_Msk (0x1ul << OPA_CALCTL_TRIMOPT1_Pos) /*!< OPA_T::CALCTL: TRIMOPT1 Mask */ 464 465 #define OPA_CALCTL_TRIMOPT2_Pos (26) /*!< OPA_T::CALCTL: TRIMOPT2 Position */ 466 #define OPA_CALCTL_TRIMOPT2_Msk (0x1ul << OPA_CALCTL_TRIMOPT2_Pos) /*!< OPA_T::CALCTL: TRIMOPT2 Mask */ 467 468 #define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */ 469 #define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */ 470 471 #define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */ 472 #define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */ 473 474 #define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */ 475 #define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */ 476 477 #define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */ 478 #define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */ 479 480 #define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */ 481 #define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */ 482 483 #define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */ 484 #define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */ 485 486 #define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */ 487 #define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */ 488 489 #define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */ 490 #define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */ 491 492 #define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */ 493 #define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */ 494 495 /**@}*/ /* OPA_CONST */ 496 /**@}*/ /* end of OPA register group */ 497 /**@}*/ /* end of REGISTER group */ 498 499 #if defined ( __CC_ARM ) 500 #pragma no_anon_unions 501 #endif 502 503 #endif /* __OPA_REG_H__ */ 504
