1 /**************************************************************************//** 2 * @file opa_reg.h 3 * @version V1.00 4 * @brief OPA register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __OPA_REG_H__ 10 #define __OPA_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup OPA OP Amplifier(OPA) 23 Memory Mapped Structure for OPA Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var OPA_T::CTL 32 * Offset: 0x00 OP Amplifier Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |OPEN0 |OP Amplifier 0 Enable Bit 37 * | | |0 = OP amplifier0 Disabled. 38 * | | |1 = OP amplifier0 Enabled. 39 * | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set. 40 * |[1] |OPEN1 |OP Amplifier 1 Enable Bit 41 * | | |0 = OP amplifier1 Disabled. 42 * | | |1 = OP amplifier1 Enabled. 43 * | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set. 44 * |[2] |OPEN2 |OP Amplifier 2 Enable Bit 45 * | | |0 = OP amplifier2 Disabled. 46 * | | |1 = OP amplifier2 Enabled. 47 * | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set. 48 * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit 49 * | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled. 50 * | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled. 51 * |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit 52 * | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled. 53 * | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled. 54 * |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit 55 * | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled. 56 * | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled. 57 * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit 58 * | | |0 = OP Amplifier 0 digital output interrupt function Disabled. 59 * | | |1 = OP Amplifier 0 digital output interrupt function Enabled. 60 * | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated. 61 * |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit 62 * | | |0 = OP Amplifier 1 digital output interrupt function Disabled. 63 * | | |1 = OP Amplifier 1 digital output interrupt function Enabled. 64 * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated. 65 * |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit 66 * | | |0 = OP Amplifier 2 digital output interrupt function Disabled. 67 * | | |1 = OP Amplifier 2 digital output interrupt function Enabled. 68 * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated. 69 * @var OPA_T::STATUS 70 * Offset: 0x04 OP Amplifier Status Register 71 * --------------------------------------------------------------------------------------------------- 72 * |Bits |Field |Descriptions 73 * | :----: | :----: | :---- | 74 * |[0] |OPDO0 |OP Amplifier 0 Digital Output 75 * | | |Synchronized to the APB clock to allow reading by software 76 * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0) 77 * |[1] |OPDO1 |OP Amplifier 1 Digital Output 78 * | | |Synchronized to the APB clock to allow reading by software 79 * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0) 80 * |[2] |OPDO2 |OP Amplifier 2 Digital Output 81 * | | |Synchronized to the APB clock to allow reading by software 82 * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0) 83 * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag 84 * | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state 85 * | | |This bit is cleared by writing 1 to it. 86 * |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag 87 * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state 88 * | | |This bit is cleared by writing 1 to it. 89 * |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag 90 * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state 91 * | | |This bit is cleared by writing 1 to it. 92 * @var OPA_T::CALCTL 93 * Offset: 0x08 OP Amplifier Calibration Control Register 94 * --------------------------------------------------------------------------------------------------- 95 * |Bits |Field |Descriptions 96 * | :----: | :----: | :---- | 97 * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit 98 * | | |0 = Stop, hardware auto clear. 99 * | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance. 100 * |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit 101 * | | |0 = Stop, hardware auto clear. 102 * | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance. 103 * |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit 104 * | | |0 = Stop, hardware auto clear. 105 * | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance. 106 * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection 107 * | | |0 = VREF is AVDD. 108 * | | |1 = VREF from high vcm to low vcm. 109 * |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection 110 * | | |0 = VREF is AVDD. 111 * | | |1 = VREF from high vcm to low vcm. 112 * |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection 113 * | | |0 = VREF is AVDD. 114 * | | |1 = VREF from high vcm to low vcm. 115 * @var OPA_T::CALST 116 * Offset: 0x0C OP Amplifier Calibration Status Register 117 * --------------------------------------------------------------------------------------------------- 118 * |Bits |Field |Descriptions 119 * | :----: | :----: | :---- | 120 * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status 121 * | | |0 = Calibrating. 122 * | | |1 = Calibration Done. 123 * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS 124 * | | |0 = Pass. 125 * | | |1 = Fail. 126 * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS 127 * | | |0 = Pass. 128 * | | |1 = Fail. 129 * |[4] |DONE1 |OP Amplifier 1 Calibration Done Status 130 * | | |0 = Calibrating. 131 * | | |1 = Calibration Done. 132 * |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS 133 * | | |0 = Pass. 134 * | | |1 = Fail. 135 * |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS 136 * | | |0 = Pass. 137 * | | |1 = Fail. 138 * |[8] |DONE2 |OP Amplifier 2 Calibration Done Status 139 * | | |0 = Calibrating. 140 * | | |1 = Calibration Done. 141 * |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS 142 * | | |0 = Pass. 143 * | | |1 = Fail. 144 * |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS 145 * | | |0 = Pass. 146 * | | |1 = Fail. 147 */ 148 __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */ 149 __IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */ 150 __IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */ 151 __I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */ 152 153 } OPA_T; 154 155 /** 156 @addtogroup OPA_CONST OPA Bit Field Definition 157 Constant Definitions for OPA Controller 158 @{ */ 159 160 #define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */ 161 #define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */ 162 163 #define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */ 164 #define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */ 165 166 #define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */ 167 #define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */ 168 169 #define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */ 170 #define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */ 171 172 #define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */ 173 #define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */ 174 175 #define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */ 176 #define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */ 177 178 #define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */ 179 #define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */ 180 181 #define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */ 182 #define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */ 183 184 #define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */ 185 #define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */ 186 187 #define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */ 188 #define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */ 189 190 #define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */ 191 #define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */ 192 193 #define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */ 194 #define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */ 195 196 #define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */ 197 #define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */ 198 199 #define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */ 200 #define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */ 201 202 #define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */ 203 #define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */ 204 205 #define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */ 206 #define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */ 207 208 #define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */ 209 #define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */ 210 211 #define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */ 212 #define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */ 213 214 #define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */ 215 #define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */ 216 217 #define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */ 218 #define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */ 219 220 #define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */ 221 #define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */ 222 223 #define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */ 224 #define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */ 225 226 #define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */ 227 #define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */ 228 229 #define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */ 230 #define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */ 231 232 #define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */ 233 #define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */ 234 235 #define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */ 236 #define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */ 237 238 #define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */ 239 #define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */ 240 241 #define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */ 242 #define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */ 243 244 #define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */ 245 #define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */ 246 247 #define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */ 248 #define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */ 249 250 #define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */ 251 #define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */ 252 253 #define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */ 254 #define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */ 255 256 #define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */ 257 #define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */ 258 259 /**@}*/ /* OPA_CONST */ 260 /**@}*/ /* end of OPA register group */ 261 /**@}*/ /* end of REGISTER group */ 262 263 #if defined ( __CC_ARM ) 264 #pragma no_anon_unions 265 #endif 266 267 #endif /* __OPA_REG_H__ */ 268 269
