1# Configuration file for pinctrl generation (except F1 series).
2#
3# This file contains a list of pin configuration templates used to generate the
4# pinctrl files. Each entry can have the following fields:
5#
6#   - name (mandatory): This is the pin function name, e.g. UART_TX. It is used
7#     to group pin configurations alphabetically in the generated pinctrl files.
8#
9#   - match (mandatory): This is a regular expression used to match against
10#     STM32 xml database pin configuration names. The regular expression should
11#     be as precise as possible. Note that it needs to be escaped here in the
12#     configuration file.
13#     Note: Specific "ANALOG" value allows generation of analog pins
14#     configuration
15#
16#   - mode (optional): Mode setting (analog, alternate). Mode needs to
17#     be set according to the following rules:
18#       * Pin operates in analog configuration: analog
19#       * Pin operates in alternate function configuration: alternate
20#     In default case, mode could be infered from CubeMX SoC description files
21#     and can be omitted.
22#
23#   - bias (optional): Bias setting (disable, pull-up, pull-down). Equivalent to
24#     "disable" (a.k.a floating) if not set.
25#
26#   - drive (optional): Drive setting (push-pull, open-drain). Equivalent to
27#     "push-pull" if not set.
28#
29#   - slew-rate (optional): Slew rate setting (low-speed, medium-speed,
30#     high-speed, very-high-speed). Equivalent to "low-speed" if not set.
31#
32#   - variant (optional): Defines an alternative pin configuration. This is used
33#     to provide multiple configurations of a pin function (slave, master,
34#     low-power, ...).
35#
36
37---
38- name: Analog
39  match: "ANALOG"
40  mode: analog
41
42- name: ADC_IN / ADC_INN / ADC_INP
43  match: "^ADC(?:\\d+)?_IN[NP]?\\d+$"
44
45- name: ADC_VINM / ADC_VINP
46  match: "^ADC(?:\\d+)?_VIN[PM]\\d+$"
47
48- name: CAN_RX
49  match: "^CAN\\d*_RX$"
50  bias: pull-up
51
52- name: CAN_TX
53  match: "^CAN\\d*_TX$"
54
55- name: DAC_OUT
56  match: "^DAC(?:\\d+)?_OUT\\d+$"
57
58- name: DCMI
59  match: "^DCMI_(?:HSYNC|PIXCLK|VSYNC|D[0-7])$"
60  slew-rate: very-high-speed
61
62- name: DFSDM
63  match: "^DFSDM[1-2]_(DATIN[0-7]|CKIN[0-7]|CKOUT)$"
64  slew-rate: very-high-speed
65  mode: alternate
66
67- name: ETH_COL
68  match: "^ETH_COL$"
69  slew-rate: very-high-speed
70
71- name: ETH_CRS
72  match: "^ETH_CRS$"
73  slew-rate: very-high-speed
74
75- name: ETH_CRS_DV
76  match: "^ETH_CRS_DV$"
77  slew-rate: very-high-speed
78
79- name: ETH_MDC
80  match: "^ETH_MDC$"
81  slew-rate: very-high-speed
82
83- name: ETH_MDIO
84  match: "^ETH_MDIO$"
85  slew-rate: very-high-speed
86
87- name: ETH_PPS_OUT
88  match: "^ETH_PPS_OUT$"
89  slew-rate: very-high-speed
90
91- name: ETH_REF_CLK
92  match: "^ETH_REF_CLK$"
93  slew-rate: very-high-speed
94
95- name: ETH_RX_CLK
96  match: "^ETH_RX_CLK$"
97  slew-rate: very-high-speed
98
99- name: ETH_RX_DV
100  match: "^ETH_RX_DV$"
101  slew-rate: very-high-speed
102
103- name: ETH_RX_ER
104  match: "^ETH_RX_ER$"
105  slew-rate: very-high-speed
106
107- name: ETH_RXD0
108  match: "^ETH_RXD0$"
109  slew-rate: very-high-speed
110
111- name: ETH_RXD1
112  match: "^ETH_RXD1$"
113  slew-rate: very-high-speed
114
115- name: ETH_RXD2
116  match: "^ETH_RXD2$"
117  slew-rate: very-high-speed
118
119- name: ETH_RXD3
120  match: "^ETH_RXD3$"
121  slew-rate: very-high-speed
122
123- name: ETH_TX_CLK
124  match: "^ETH_TX_CLK$"
125  slew-rate: very-high-speed
126
127- name: ETH_TX_EN
128  match: "^ETH_TX_EN$"
129  slew-rate: very-high-speed
130
131- name: ETH_TXD0
132  match: "^ETH_TXD0$"
133  slew-rate: very-high-speed
134
135- name: ETH_TXD1
136  match: "^ETH_TXD1$"
137  slew-rate: very-high-speed
138
139- name: ETH_TXD2
140  match: "^ETH_TXD2$"
141  slew-rate: very-high-speed
142
143- name: ETH_TXD3
144  match: "^ETH_TXD3$"
145  slew-rate: very-high-speed
146
147- name: FDCAN_RX
148  match: "^FDCAN\\d+_RX$"
149
150- name: FDCAN_TX
151  match: "^FDCAN\\d+_TX$"
152
153- name: FMC
154  match: "^FMC_(?:NL|NADV|CLK|NBL[0-3]|A\\d+|D\\d+|NE[1-4]|NOE|NWE|NWAIT|NCE|INT|SDCLK|SDNWE|SDCKE[0-1]|SDNE[0-1]|SDNRAS|SDNCAS)$"
155  bias: pull-up
156  slew-rate: very-high-speed
157
158- name: HRTIM_CH
159  match: "^HRTIM\\d+_CH[A-F]\\d+$"
160
161- name: HRTIM_EEV
162  match: "^HRTIM\\d+_EEV\\d+$"
163
164- name: HRTIM_FLT
165  match: "^HRTIM\\d+_FLT[A-F]\\d+$"
166
167- name: HRTIM_SCIN / HRTIM_SCOUT
168  match: "^HRTIM\\d+_SC(IN|OUT)$"
169
170- name: I2C_SCL
171  match: "^I2C\\d+_SCL$"
172  drive: open-drain
173  bias: pull-up
174
175- name: I2C_SDA
176  match: "^I2C\\d+_SDA$"
177  drive: open-drain
178  bias: pull-up
179
180- name: I2C_SMBA
181  match: "^I2C\\d+_SMBA$"
182  bias: pull-up
183
184- name: I2S_MCK
185  match: "^I2S\\d+_MCK$"
186  slew-rate: very-high-speed
187
188- name: I2S_CK
189  match: "^I2S\\d+_CK$"
190  slew-rate: very-high-speed
191
192- name: I2S_WS
193  match: "^I2S\\d+_WS$"
194
195- name: I2S_SD
196  match: "^I2S\\d+_SD$"
197
198- name: I3C_SCL
199  match: "^I3C\\d+_SCL$"
200  slew-rate: very-high-speed
201
202- name: I3C_SDA
203  match: "^I3C\\d+_SDA$"
204  slew-rate: very-high-speed
205
206- name: JTAG PORT
207  match: ^(SYS|DEBUG)_((JTMS-)?SWDIO|(JTCK-)?SWCLK|JTDI|JTDO(-TRACESWO|-SWO)?|(NJ)?JTRST)$
208
209- name: LTDC
210  match: "^LTDC_(?:DE|CLK|HSYNC|VSYNC|R[0-7]|G[0-7]|B[0-7])$"
211
212- name: OCTOSPI
213  match: "^OCTOSPI(.*)(?:CLK|NCS|DQS|IO[0-7])$"
214  slew-rate: very-high-speed
215
216- name: RCC_MCO
217  match: "^RCC_MCO_?(\\d+)?$"
218  mode: alternate
219  slew-rate: very-high-speed
220
221- name: QUADSPI
222  match: "^QUADSPI(\\d+)?_(?:CLK|NCS|BK1_NCS|BK1_IO[0-3]|BK2_NCS|BK2_IO[0-3])$"
223  slew-rate: very-high-speed
224
225- name: XSPIM
226  match: "^XSPIM(.*)(?:CLK|NCS[1-2]|DQS[0-1]|IO\\d+)$"
227  slew-rate: very-high-speed
228
229- name: SAI
230  match: "^SAI\\d+_(?:D\\d+)?(?:CK\\d+)?(?:FS_A)?(?:FS_B)?(?:MCLK_A)?(?:MCLK_B)?(?:SD_A)?(?:SD_B)?(?:SCK_A)?(?:SCK_B)?(?:EXTCLK)?$"
231
232- name: SDMMC
233  match: "^SDMMC\\d+_(?:CK)?(?:CKIN)?(?:CDIR)?(?:CMD)?(?:D\\d+)?(?:D0DIR)?(?:D123DIR)?$"
234  slew-rate: very-high-speed
235  bias: pull-up
236
237- name: SDIO
238  match: "^SDIO_(?:CK)?(?:CKIN)?(?:CDIR)?(?:CMD)?(?:D\\d+)?(?:D0DIR)?(?:D123DIR)?$"
239  slew-rate: very-high-speed
240  bias: pull-up
241
242- name: SPI_MISO
243  match: "^SPI\\d+_MISO$"
244  bias: pull-down
245
246- name: SPI_MOSI
247  match: "^SPI\\d+_MOSI$"
248  bias: pull-down
249
250# NOTE: The SPI_SCK pins speed must be set to very-high-speed to avoid last data
251# bit corruption which is a known issue on multiple STM32F4 series SPI
252# peripheral (ref. ES0182 Rev 12, 2.5.12, p. 22).
253- name: SPI_SCK
254  match: "^SPI\\d+_SCK$"
255  slew-rate: very-high-speed
256  bias: pull-down
257
258- name: SPI_NSS
259  match: "^SPI\\d+_NSS$"
260  bias: pull-up
261
262- name: TIM_BKIN
263  match: "^TIM\\d+_BKIN\\d?$"
264
265- name: TIM_CH / TIM_CHN
266  match: "^TIM\\d+_CH\\d+N?$"
267
268- name: TSC
269  match: "^TSC_(?:G\\d+_IO\\d+|SYNC)$"
270
271- name: UART_CTS / USART_CTS / LPUART_CTS
272  match: "^(?:LP)?US?ART\\d+_CTS$"
273  bias: pull-up
274
275- name: UART_RTS / USART_RTS / LPUART_RTS
276  match: "^(?:LP)?US?ART\\d+_RTS$"
277  drive: push-pull
278
279- name: UART_DE / USART_DE / LPUART_DE
280  match: "^(?:LP)?US?ART\\d+_DE$"
281  drive: push-pull
282
283- name: UART_TX / USART_TX / LPUART_TX
284  match: "^(?:LP)?US?ART\\d+_TX$"
285  bias: pull-up
286
287- name: UART_RX / USART_RX / LPUART_RX
288  match: "^(?:LP)?US?ART\\d+_RX$"
289
290- name: UCPD
291  match: "^UCPD\\d+_CC\\d+N?$"
292  mode: analog
293
294- name: USB_OTG_FS
295  match: "^USB_OTG_FS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
296
297- name: USB_OTG_HS
298  match: "^USB_OTG_HS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
299
300- name: USB_OTG_HS_ULPI
301  match: "^USB_OTG_HS_ULPI_(?:CK)?(?:DIR)?(?:STP)?(?:NXT)?(?:D\\d+)?$"
302  slew-rate: high-speed
303
304- name: USB
305  match: "^USB_(?:DM)?(?:DP)?(?:NOE)?$"
306
307