1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_FLASH_H 21 #define STM32U5xx_HAL_FLASH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FLASH 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup FLASH_Exported_Types FLASH Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief FLASH Erase structure definition 45 */ 46 typedef struct 47 { 48 uint32_t TypeErase; /*!< Mass erase or page erase. 49 This parameter can be a value of @ref FLASH_Type_Erase */ 50 uint32_t Banks; /*!< Select bank to erase. 51 This parameter must be a value of @ref FLASH_Banks 52 (FLASH_BANK_BOTH should be used only for mass erase) */ 53 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 54 This parameter must be a value between 0 and (max number of pages in the bank - 1) 55 (eg : 127 for 2MB dual bank) */ 56 uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and 57 (max number of pages in the bank - value of initial page)*/ 58 } FLASH_EraseInitTypeDef; 59 60 /** 61 * @brief FLASH Option Bytes Program structure definition 62 */ 63 typedef struct 64 { 65 uint32_t OptionType; /*!< Option byte to be configured. 66 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 67 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 68 Only one WRP area could be programmed at the same time. 69 This parameter can be value of @ref FLASH_OB_WRP_Area */ 70 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 71 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 72 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 73 This parameter must be a value between WRPStartOffset 74 and (max number of pages in the bank - 1) */ 75 FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP). 76 This parameter can be set to ENABLE or DISABLE */ 77 uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). 78 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 79 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 80 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 81 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 82 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 83 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 84 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, 85 @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, 86 @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, 87 @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, 88 @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, 89 @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, 90 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, 91 @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, 92 @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */ 93 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 94 uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). 95 This parameter must be a value of @ref FLASH_OB_WMSEC */ 96 uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). 97 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 98 uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). This parameter must be a value 99 between WMSecStartPage and (max number of pages in the bank - 1) */ 100 uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). 101 This parameter must be a value between WMSecStartPage and WMSecEndPage */ 102 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 103 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 104 #endif /* __ARM_FEATURE_CMSE */ 105 uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). 106 This parameter must be a value of @ref FLASH_OB_BOOTADDR */ 107 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 108 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 109 uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). 110 This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ 111 uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */ 112 uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */ 113 } FLASH_OBProgramInitTypeDef; 114 115 /** 116 * @brief FLASH handle Structure definition 117 */ 118 typedef struct 119 { 120 HAL_LockTypeDef Lock; /* FLASH locking object */ 121 uint32_t ErrorCode; /* FLASH error code */ 122 uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing 123 or not in IT context */ 124 uint32_t Address; /* Internal variable to save address selected for program 125 in IT context */ 126 uint32_t Bank; /* Internal variable to save current bank selected during erase 127 in IT context */ 128 uint32_t Page; /* Internal variable to define the current page which is being erased 129 in IT context */ 130 uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 131 } FLASH_ProcessTypeDef; 132 133 /** 134 * @} 135 */ 136 137 /* Exported constants --------------------------------------------------------*/ 138 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 139 * @{ 140 */ 141 142 /** @defgroup FLASH_Flags FLASH Flags Definition 143 * @{ 144 */ 145 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 146 #define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */ 147 #define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */ 148 #define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */ 149 #define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */ 150 #define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */ 151 #define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */ 152 #define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */ 153 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 154 #define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */ 155 #define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */ 156 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 157 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 158 159 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 160 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) 161 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 162 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) 163 #else 164 #define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */ 165 #define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */ 166 #define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */ 167 #define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */ 168 #define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */ 169 #define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */ 170 #define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */ 171 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 172 #define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */ 173 #define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ 174 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 175 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 176 177 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 178 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 179 FLASH_FLAG_OPTWERR) 180 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 181 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) 182 #endif /* __ARM_FEATURE_CMSE */ 183 /** 184 * @} 185 */ 186 187 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 188 * @brief FLASH Interrupt definition 189 * @{ 190 */ 191 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 192 #define FLASH_IT_EOP FLASH_SECCR_EOPIE /*!< End of FLASH Operation Interrupt source */ 193 #define FLASH_IT_OPERR FLASH_SECCR_ERRIE /*!< Error Interrupt source */ 194 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 195 #else 196 #define FLASH_IT_EOP FLASH_NSCR_EOPIE /*!< End of FLASH Operation Interrupt source */ 197 #define FLASH_IT_OPERR FLASH_NSCR_ERRIE /*!< Error Interrupt source */ 198 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 199 #endif /* __ARM_FEATURE_CMSE */ 200 /** 201 * @} 202 */ 203 204 /** @defgroup FLASH_Error FLASH Error 205 * @{ 206 */ 207 #define HAL_FLASH_ERROR_NONE 0x00000000U 208 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 209 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 210 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 211 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 212 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 213 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 214 #define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR 215 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC 216 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 217 /** 218 * @} 219 */ 220 221 /** @defgroup FLASH_Type_Erase FLASH Erase Type 222 * @{ 223 */ 224 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 225 #define FLASH_TYPEERASE_PAGES FLASH_SECCR_PER /*!< Secure pages erase 226 activation */ 227 #define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase 228 activation */ 229 #define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_MER1 | FLASH_SECCR_MER2) /*!< Secure flash mass erase 230 activation */ 231 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_MER1 | FLASH_NSCR_MER2 | FLASH_NON_SECURE_MASK) /*!< Non-secure flash 232 mass erase activation */ 233 #else 234 #define FLASH_TYPEERASE_PAGES FLASH_NSCR_PER /*!< Pages erase activation */ 235 #define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_MER1 | FLASH_NSCR_MER2) /*!< Flash mass erase activation */ 236 #endif /* __ARM_FEATURE_CMSE */ 237 /** 238 * @} 239 */ 240 241 /** @defgroup FLASH_Banks FLASH Banks 242 * @{ 243 */ 244 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 245 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 246 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup FLASH_Type_Program FLASH Program Type 252 * @{ 253 */ 254 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 255 #define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR_PG /*!< Program a quad-word (128-bit) 256 at a specified secure address */ 257 #define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) 258 at a specified non-secure address */ 259 #define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR_PG | FLASH_SECCR_BWR) /*!< Program a burst (8xquad-word) 260 at a specified secure address */ 261 #define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR_PG | FLASH_NSCR_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst 262 (8xquad-word) at a specified non-secure address */ 263 #else 264 #define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR_PG /*!<Program a quad-word (128-bit) 265 at a specified address */ 266 #define FLASH_TYPEPROGRAM_BURST (FLASH_NSCR_PG | FLASH_NSCR_BWR) /*!<Program a burst (8xquad-word) 267 at a specified address */ 268 #endif /* __ARM_FEATURE_CMSE */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 274 * @{ 275 */ 276 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 277 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 278 #define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ 279 #define OPTIONBYTE_BOOTADDR 0x00000008U /*!< Boot address option byte configuration */ 280 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 281 #define OPTIONBYTE_WMSEC 0x00000010U /*!< Watermark-based secure area option byte configuration */ 282 #define OPTIONBYTE_BOOT_LOCK 0x00000020U /*!< Boot lock option byte configuration */ 283 #endif /* __ARM_FEATURE_CMSE */ 284 #define OPTIONBYTE_RDPKEY 0x00000040U /*!< RDP Key option byte configuration */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 290 * @{ 291 */ 292 #define OB_WRPAREA_BANK1_AREAA 0x01U /*!< Flash Bank 1 Area A */ 293 #define OB_WRPAREA_BANK1_AREAB 0x02U /*!< Flash Bank 1 Area B */ 294 #define OB_WRPAREA_BANK2_AREAA 0x04U /*!< Flash Bank 2 Area A */ 295 #define OB_WRPAREA_BANK2_AREAB 0x08U /*!< Flash Bank 2 Area B */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 301 * @{ 302 */ 303 #define OB_RDP_LEVEL_0 0xAAU 304 #define OB_RDP_LEVEL_0_5 0x55U 305 #define OB_RDP_LEVEL_1 0xBBU 306 #define OB_RDP_LEVEL_2 0xCCU 307 /** 308 * @} 309 */ 310 311 /** @defgroup FLASH_OB_RDP_Key_Type FLASH Option Bytes Read Protection Key Type 312 * @{ 313 */ 314 #define OB_RDP_KEY_OEM1 0x01U /*!< OEM1 key */ 315 #define OB_RDP_KEY_OEM2 0x02U /*!< OEM2 key */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 321 * @{ 322 */ 323 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 324 #define OB_USER_NRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ 325 #define OB_USER_NRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ 326 #define OB_USER_NRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */ 327 #define OB_USER_SRAM_RST 0x00000010U /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ 328 #define OB_USER_IWDG_SW 0x00000020U /*!< Independent watchdog selection */ 329 #define OB_USER_IWDG_STOP 0x00000040U /*!< Independent watchdog counter freeze in stop mode */ 330 #define OB_USER_IWDG_STDBY 0x00000080U /*!< Independent watchdog counter freeze in standby mode */ 331 #define OB_USER_WWDG_SW 0x00000100U /*!< Window watchdog selection */ 332 #define OB_USER_SWAP_BANK 0x00000200U /*!< Swap banks */ 333 #define OB_USER_DUALBANK 0x00000400U /*!< Dual-Bank on 1MB/512kB Flash memory devices */ 334 #define OB_USER_BKPRAM_ECC 0x00000800U /*!< Backup RAM ECC detection and correction enable */ 335 #if defined(SRAM3_BASE) 336 #define OB_USER_SRAM3_ECC 0x00001000U /*!< SRAM3 ECC detection and correction enable */ 337 #endif /* SRAM3_BASE */ 338 #define OB_USER_SRAM2_ECC 0x00002000U /*!< SRAM2 ECC detection and correction enable */ 339 #define OB_USER_SRAM2_RST 0x00004000U /*!< SRAM2 Erase when system reset */ 340 #define OB_USER_NSWBOOT0 0x00008000U /*!< Software BOOT0 */ 341 #define OB_USER_NBOOT0 0x00010000U /*!< nBOOT0 option bit */ 342 #define OB_USER_PA15_PUPEN 0x00020000U /*!< PA15 pull-up enable option bit */ 343 #define OB_USER_IO_VDD_HSLV 0x00040000U /*!< High speed IO at low voltage configuration bit */ 344 #define OB_USER_IO_VDDIO2_HSLV 0x00080000U /*!< High speed IO at low VDDIO2 voltage configuration bit */ 345 #define OB_USER_TZEN 0x00100000U /*!< Global TrustZone security enable */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 351 * @{ 352 */ 353 #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold 354 is around 1.7V */ 355 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold 356 is around 2.0V */ 357 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold 358 is around 2.2V */ 359 #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_1 | FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold 360 is around 2.5V */ 361 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold 362 is around 2.8V */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 368 * @{ 369 */ 370 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 371 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 372 /** 373 * @} 374 */ 375 376 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 377 * @{ 378 */ 379 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 380 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 381 /** 382 * @} 383 */ 384 385 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 386 * @{ 387 */ 388 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 389 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes User SRAM Erase On Reset Type 395 * @{ 396 */ 397 #define OB_SRAM_RST_ERASE 0x00000000U /*!< All SRAMs (except SRAM2 and BKPSRAM) erased 398 when a system reset occurs */ 399 #define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< All SRAMs (except SRAM2 and BKPSRAM) not erased 400 when a system reset occurs */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 406 * @{ 407 */ 408 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 409 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 415 * @{ 416 */ 417 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 418 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 424 * @{ 425 */ 426 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 427 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 433 * @{ 434 */ 435 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 436 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH Option Bytes User Swap banks 442 * @{ 443 */ 444 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank 1 is located at address offset 0x0, 445 Bank 2 is located at 0x100000 */ 446 #define OB_SWAP_BANK_ENABLE FLASH_OPTR_SWAP_BANK /*!< Bank 1 is located at address offset 0x100000, 447 Bank 2 is located at 0x0 */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 453 * @{ 454 */ 455 #define OB_DUALBANK_SINGLE 0x00000000U /*!< 1MB/512KB Single-bank Flash */ 456 #define OB_DUALBANK_DUAL FLASH_OPTR_DUALBANK /*!< 1MB/512KB Dual-bank Flash */ 457 /** 458 * @} 459 */ 460 461 /** @defgroup FLASH_OB_USER_BKPRAM_RST FLASH Option Bytes User BKPRAM ECC check 462 * @{ 463 */ 464 #define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */ 465 #define OB_BKPRAM_ECC_DISABLE FLASH_OPTR_BKPRAM_ECC /*!< BKPRAM ECC check disable */ 466 /** 467 * @} 468 */ 469 470 /** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check 471 * @{ 472 */ 473 #define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */ 474 #define OB_SRAM3_ECC_DISABLE FLASH_OPTR_SRAM3_ECC /*!< SRAM3 ECC check disable */ 475 /** 476 * @} 477 */ 478 479 /** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check 480 * @{ 481 */ 482 #define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */ 483 #define OB_SRAM2_ECC_DISABLE FLASH_OPTR_SRAM2_ECC /*!< SRAM2 ECC check disable */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 489 * @{ 490 */ 491 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 492 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 498 * @{ 499 */ 500 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 501 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from BOOT0 pin */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 507 * @{ 508 */ 509 #define OB_NBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 510 #define OB_NBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 511 /** 512 * @} 513 */ 514 515 /** @defgroup FLASH_OB_USER_PA15_PUPEN FLASH Option Bytes User PA15 pull-up enable option bit 516 * @{ 517 */ 518 #define OB_PA15_PUP_DISABLE 0x00000000U /*!< USB power delivery dead-battery 519 enabled / TDI pull-up deactivated */ 520 #define OB_PA15_PUP_ENABLE FLASH_OPTR_PA15_PUPEN /*!< USB power delivery dead-battery 521 disabled / TDI pull-up activated */ 522 /** 523 * @} 524 */ 525 526 /** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes User High speed IO at low voltage configuration bit 527 * @{ 528 */ 529 #define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled 530 (VDD can exceed 2.5 V) */ 531 #define OB_IO_VDD_HSLV_ENABLE FLASH_OPTR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled 532 (VDD remains below 2.5 V) */ 533 /** 534 * @} 535 */ 536 537 /** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes User High speed IO at low VDDIO2 voltage configuration bit 538 * @{ 539 */ 540 #define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature disabled 541 (VDDIO2 can exceed 2.5 V) */ 542 #define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature enabled 543 (VDDIO2 remains below 2.5 V) */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone 549 * @{ 550 */ 551 #define OB_TZEN_DISABLE 0x00000000U /*!< Global TrustZone security disabled */ 552 #define OB_TZEN_ENABLE FLASH_OPTR_TZEN /*!< Global TrustZone security enabled */ 553 /** 554 * @} 555 */ 556 557 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 558 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 559 * @{ 560 */ 561 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */ 562 #define OB_BOOT_LOCK_ENABLE FLASH_SECBOOTADD0R_BOOT_LOCK /*!< Boot lock enable */ 563 /** 564 * @} 565 */ 566 567 /** @defgroup FLASH_OB_WMSEC FLASH Option Bytes Watermarked-based security configuration 568 * @{ 569 */ 570 #define OB_WMSEC_AREA1 FLASH_BANK_1 /*!< Watermarked-based security area for bank 1 */ 571 #define OB_WMSEC_AREA2 FLASH_BANK_2 /*!< Watermarked-based security area for bank 2 */ 572 573 #define OB_WMSEC_SECURE_AREA_CONFIG 0x00000010U /*!< Configure Watermarked-based security area */ 574 #define OB_WMSEC_HDP_AREA_CONFIG 0x00000020U /*!< Configure Watermarked-based secure hide area */ 575 #define OB_WMSEC_HDP_AREA_ENABLE 0x00000080U /*!< Enable Watermarked-based secure hide area */ 576 #define OB_WMSEC_HDP_AREA_DISABLE 0x00000100U /*!< Disable Watermarked-based secure hide area */ 577 /** 578 * @} 579 */ 580 #endif /* __ARM_FEATURE_CMSE */ 581 582 /** @defgroup FLASH_OB_BOOTADDR FLASH Option Bytes Boot address 583 * @{ 584 */ 585 #define OB_BOOTADDR_NS0 0x00000001U /*!< Non-secure boot address 0 */ 586 #define OB_BOOTADDR_NS1 0x00000002U /*!< Non-secure boot address 1 */ 587 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 588 #define OB_BOOTADDR_SEC0 0x00000004U /*!< Secure boot address 0 */ 589 #endif /* __ARM_FEATURE_CMSE */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup FLASH_Latency FLASH Latency 595 * @{ 596 */ 597 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 598 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 599 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 600 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 601 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 602 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 603 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 604 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 605 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 606 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 607 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 608 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 609 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 610 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 611 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 612 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup FLASH_Keys FLASH Keys 618 * @{ 619 */ 620 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 621 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 622 to unlock the FLASH registers access */ 623 624 #define FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank 1 power down key1 */ 625 #define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank 1 power down key2: used with FLASH_PDKEY1_1 626 to unlock the PDREQ1 bit in FLASH_ACR */ 627 628 #define FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank 2 power down key1 */ 629 #define FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank 2 power down key2: used with FLASH_PDKEY2_1 630 to unlock the PDREQ2 bit in FLASH_ACR */ 631 632 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 633 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 634 to allow option bytes operations */ 635 /** 636 * @} 637 */ 638 639 /** 640 * @} 641 */ 642 643 /* Exported macros -----------------------------------------------------------*/ 644 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 645 * @brief macros to control FLASH features 646 * @{ 647 */ 648 649 /** 650 * @brief Set the FLASH Latency. 651 * @param __LATENCY__ FLASH Latency 652 * This parameter can be one of the following values : 653 * @arg FLASH_LATENCY_0: FLASH Zero wait state 654 * @arg FLASH_LATENCY_1: FLASH One wait state 655 * @arg FLASH_LATENCY_2: FLASH Two wait states 656 * @arg FLASH_LATENCY_3: FLASH Three wait states 657 * @arg FLASH_LATENCY_4: FLASH Four wait states 658 * @arg FLASH_LATENCY_5: FLASH Five wait states 659 * @arg FLASH_LATENCY_6: FLASH Six wait states 660 * @arg FLASH_LATENCY_7: FLASH Seven wait states 661 * @arg FLASH_LATENCY_8: FLASH Eight wait states 662 * @arg FLASH_LATENCY_9: FLASH Nine wait states 663 * @arg FLASH_LATENCY_10: FLASH Ten wait states 664 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 665 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 666 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 667 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 668 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 669 * @retval None 670 */ 671 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) 672 673 /** 674 * @brief Get the FLASH Latency. 675 * @retval FLASH Latency 676 * This return value can be one of the following values : 677 * @arg FLASH_LATENCY_0: FLASH Zero wait state 678 * @arg FLASH_LATENCY_1: FLASH One wait state 679 * @arg FLASH_LATENCY_2: FLASH Two wait states 680 * @arg FLASH_LATENCY_3: FLASH Three wait states 681 * @arg FLASH_LATENCY_4: FLASH Four wait states 682 * @arg FLASH_LATENCY_5: FLASH Five wait states 683 * @arg FLASH_LATENCY_6: FLASH Six wait states 684 * @arg FLASH_LATENCY_7: FLASH Seven wait states 685 * @arg FLASH_LATENCY_8: FLASH Eight wait states 686 * @arg FLASH_LATENCY_9: FLASH Nine wait states 687 * @arg FLASH_LATENCY_10: FLASH Ten wait states 688 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 689 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 690 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 691 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 692 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 693 */ 694 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 695 696 /** 697 * @brief Enable the FLASH prefetch buffer. 698 * @retval None 699 */ 700 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 701 702 /** 703 * @brief Disable the FLASH prefetch buffer. 704 * @retval None 705 */ 706 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 707 708 /** 709 * @brief Enable the FLASH power down during Low-Power sleep mode 710 * @retval none 711 */ 712 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 713 714 /** 715 * @brief Disable the FLASH power down during Low-Power sleep mode 716 * @retval none 717 */ 718 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 719 720 /** 721 * @} 722 */ 723 724 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 725 * @brief macros to handle FLASH interrupts 726 * @{ 727 */ 728 729 /** 730 * @brief Enable the specified FLASH interrupt. 731 * @param __INTERRUPT__ FLASH interrupt 732 * This parameter can be any combination of the following values: 733 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 734 * @arg FLASH_IT_OPERR: Error Interrupt 735 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 736 * @retval none 737 */ 738 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 739 /* Enable secure FLASH interrupts from the secure world */ 740 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 741 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 742 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 743 { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 744 } while(0) 745 /* Enable non-secure FLASH interrupts from the secure world */ 746 #define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 747 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 748 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 749 { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 750 } while(0) 751 #else 752 /* Enable non-secure FLASH interrupts from the non-secure world */ 753 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 754 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 755 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 756 { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 757 } while(0) 758 #endif /* __ARM_FEATURE_CMSE */ 759 760 /** 761 * @brief Disable the specified FLASH interrupt. 762 * @param __INTERRUPT__ FLASH interrupt 763 * This parameter can be any combination of the following values: 764 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 765 * @arg FLASH_IT_OPERR: Error Interrupt 766 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 767 * @retval none 768 */ 769 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 770 /* Disable secure FLASH interrupts from the secure world */ 771 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 772 { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 773 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 774 { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));}\ 775 } while(0) 776 /* Disable non-secure FLASH interrupts from the secure world */ 777 #define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 778 { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 779 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 780 { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & \ 781 (~FLASH_IT_ECCC))); }\ 782 } while(0) 783 #else 784 /* Disable non-secure FLASH interrupts from the non-secure world */ 785 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 786 { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 787 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 788 { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 789 } while(0) 790 #endif /* __ARM_FEATURE_CMSE */ 791 792 /** 793 * @brief Check whether the specified FLASH flag is set or not. 794 * @param __FLAG__ specifies the FLASH flag to check. 795 * This parameter can be one of the following values: 796 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 797 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 798 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 799 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 800 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 801 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 802 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 803 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 804 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 805 * @arg FLASH_FLAG_WDW: FLASH Wait Data to Write flag 806 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 807 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 808 * @retval The new state of FLASH_FLAG (SET or RESET). 809 */ 810 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 811 /* Get secure FLASH flags from the secure world */ 812 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 813 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 814 ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ 815 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ 816 (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) 817 /* Get non-secure FLASH flags from the secure world */ 818 #define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 819 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 820 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 821 #else 822 /* Get non-secure FLASH flags from the non-secure world */ 823 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 824 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 825 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 826 #endif /* __ARM_FEATURE_CMSE */ 827 828 /** 829 * @brief Clear the FLASH's pending flags. 830 * @param __FLAG__ specifies the FLASH flags to clear. 831 * This parameter can be any combination of the following values: 832 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 833 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 834 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 835 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 836 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 837 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 838 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 839 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 840 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 841 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 842 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 843 * @retval None 844 */ 845 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 846 /* Clear secure FLASH flags from the secure world */ 847 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ 848 { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 849 if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) \ 850 { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ 851 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \ 852 FLASH_FLAG_OPTWERR)) != 0U) \ 853 { WRITE_REG(FLASH->SECSR, ((__FLAG__) & \ 854 ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); }\ 855 } while(0) 856 /* Clear non-secure FLASH flags from the secure world */ 857 #define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ 858 { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 859 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ 860 { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ 861 ~(FLASH_FLAG_ECCR_ERRORS))); }\ 862 } while(0) 863 #else 864 /* Clear non-secure FLASH flags from the non-secure world */ 865 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ 866 { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 867 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ 868 { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ 869 ~(FLASH_FLAG_ECCR_ERRORS))); }\ 870 } while(0) 871 #endif /* __ARM_FEATURE_CMSE */ 872 /** 873 * @} 874 */ 875 876 /* Include FLASH HAL Extended module */ 877 #include "stm32u5xx_hal_flash_ex.h" 878 879 880 /* Exported functions --------------------------------------------------------*/ 881 /** @addtogroup FLASH_Exported_Functions 882 * @{ 883 */ 884 885 /* Program operation functions ***********************************************/ 886 /** @addtogroup FLASH_Exported_Functions_Group1 887 * @{ 888 */ 889 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); 890 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); 891 /* FLASH IRQ handler method */ 892 void HAL_FLASH_IRQHandler(void); 893 /* Callbacks in non blocking modes */ 894 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 895 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 896 /** 897 * @} 898 */ 899 900 /* Peripheral Control functions **********************************************/ 901 /** @addtogroup FLASH_Exported_Functions_Group2 902 * @{ 903 */ 904 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 905 HAL_StatusTypeDef HAL_FLASH_Lock(void); 906 /* Option bytes control */ 907 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 908 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 909 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 910 /** 911 * @} 912 */ 913 914 /* Peripheral State functions ************************************************/ 915 /** @addtogroup FLASH_Exported_Functions_Group3 916 * @{ 917 */ 918 uint32_t HAL_FLASH_GetError(void); 919 /** 920 * @} 921 */ 922 923 /** 924 * @} 925 */ 926 927 /* Private variables ---------------------------------------------------------*/ 928 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 929 * @{ 930 */ 931 extern FLASH_ProcessTypeDef pFlash; 932 /** 933 * @} 934 */ 935 936 /* Private constants --------------------------------------------------------*/ 937 /** @defgroup FLASH_Private_Constants FLASH Private Constants 938 * @{ 939 */ 940 941 #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ 942 943 #define FLASH_NON_SECURE_MASK 0x80000000U 944 945 #define FLASH_NB_WORDS_IN_BURST 32 946 947 /** 948 * @} 949 */ 950 951 /* Private macros ------------------------------------------------------------*/ 952 /** @defgroup FLASH_Private_Macros FLASH Private Macros 953 * @{ 954 */ 955 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 956 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 957 ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ 958 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 959 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) 960 #else 961 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 962 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 963 #endif /* __ARM_FEATURE_CMSE */ 964 965 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 966 ((BANK) == FLASH_BANK_2) || \ 967 ((BANK) == FLASH_BANK_BOTH)) 968 969 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 970 ((BANK) == FLASH_BANK_2)) 971 972 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 973 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ 974 ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ 975 ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ 976 ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) 977 #else 978 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ 979 ((VALUE) == FLASH_TYPEPROGRAM_BURST)) 980 #endif /* __ARM_FEATURE_CMSE */ 981 982 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 983 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ 984 (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) 985 #else 986 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) 987 #endif /* __ARM_FEATURE_CMSE */ 988 989 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE)\ 990 && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) 991 992 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 993 994 #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) 995 996 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 997 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 998 OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \ 999 OPTIONBYTE_RDPKEY))) 1000 #else 1001 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 1002 OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) 1003 #endif /* __ARM_FEATURE_CMSE */ 1004 1005 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 1006 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 1007 1008 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 1009 ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ 1010 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 1011 ((LEVEL) == OB_RDP_LEVEL_2)) 1012 1013 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFFU) && ((TYPE) != 0U)) 1014 1015 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 1016 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 1017 ((LEVEL) == OB_BOR_LEVEL_4)) 1018 1019 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 1020 1021 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 1022 1023 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 1024 1025 #define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE)) 1026 1027 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 1028 1029 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 1030 1031 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 1032 1033 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 1034 1035 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 1036 1037 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 1038 1039 #define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) 1040 1041 #define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) 1042 1043 #define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) 1044 1045 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 1046 1047 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 1048 1049 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_NBOOT0_RESET) || ((VALUE) == OB_NBOOT0_SET)) 1050 1051 #define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE)) 1052 1053 #define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) 1054 1055 #define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE)\ 1056 || ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) 1057 1058 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 1059 1060 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1061 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 1062 1063 #define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F3U) != 0U) && \ 1064 (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFF80CU) == 0U)) 1065 1066 #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && \ 1067 (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ 1068 ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && \ 1069 (((WMSEC) & OB_WMSEC_AREA1) == 0U))) 1070 #endif /* __ARM_FEATURE_CMSE */ 1071 1072 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1073 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ 1074 ((CFG) == OB_BOOTADDR_SEC0)) 1075 #else 1076 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) 1077 #endif /* __ARM_FEATURE_CMSE */ 1078 1079 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 1080 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 1081 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 1082 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 1083 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 1084 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 1085 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1086 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1087 1088 #define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \ 1089 ((TYPE) == OB_RDP_KEY_OEM2)) 1090 1091 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1092 #define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) 1093 #else 1094 #define IS_FLASH_SECURE_OPERATION() (0U) 1095 #endif /* __ARM_FEATURE_CMSE */ 1096 /** 1097 * @} 1098 */ 1099 1100 /* Private functions ---------------------------------------------------------*/ 1101 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 1102 * @{ 1103 */ 1104 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 1105 /** 1106 * @} 1107 */ 1108 1109 /** 1110 * @} 1111 */ 1112 1113 /** 1114 * @} 1115 */ 1116 1117 #ifdef __cplusplus 1118 } 1119 #endif 1120 1121 #endif /* STM32U5xx_HAL_FLASH_H */ 1122 1123
