1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32U5xx_HAL_FLASH_H 22 #define STM32U5xx_HAL_FLASH_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_def.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FLASH 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FLASH_Exported_Types FLASH Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief FLASH Erase structure definition 46 */ 47 typedef struct 48 { 49 uint32_t TypeErase; /*!< Mass erase or page erase. 50 This parameter can be a value of @ref FLASH_Type_Erase */ 51 uint32_t Banks; /*!< Select bank to erase. 52 This parameter must be a value of @ref FLASH_Banks 53 (FLASH_BANK_BOTH should be used only for mass erase) */ 54 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 55 This parameter must be a value between 0 and (max number of pages in the bank - 1) 56 (eg : 127 for 2MB dual bank) */ 57 uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and 58 (max number of pages in the bank - value of initial page)*/ 59 } FLASH_EraseInitTypeDef; 60 61 /** 62 * @brief FLASH Option Bytes Program structure definition 63 */ 64 typedef struct 65 { 66 uint32_t OptionType; /*!< Option byte to be configured. 67 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 68 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 69 Only one WRP area could be programmed at the same time. 70 This parameter can be value of @ref FLASH_OB_WRP_Area */ 71 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 72 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 73 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 74 This parameter must be a value between WRPStartOffset 75 and (max number of pages in the bank - 1) */ 76 FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP). 77 This parameter can be set to ENABLE or DISABLE */ 78 uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). 79 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 80 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 81 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 82 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 83 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 84 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 85 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, 86 @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, 87 @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, 88 @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, 89 @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, 90 @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, 91 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, 92 @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, 93 @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */ 94 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 95 uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). 96 This parameter must be a value of @ref FLASH_OB_WMSEC */ 97 uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). 98 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 99 uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). This parameter must be a value 100 between WMSecStartPage and (max number of pages in the bank - 1) */ 101 uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). 102 This parameter must be a value between WMSecStartPage and WMSecEndPage */ 103 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 104 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 105 #endif /* __ARM_FEATURE_CMSE */ 106 uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). 107 This parameter must be a value of @ref FLASH_OB_BOOTADDR */ 108 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 109 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 110 uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). 111 This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ 112 uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */ 113 uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */ 114 } FLASH_OBProgramInitTypeDef; 115 116 /** 117 * @brief FLASH handle Structure definition 118 */ 119 typedef struct 120 { 121 HAL_LockTypeDef Lock; /* FLASH locking object */ 122 uint32_t ErrorCode; /* FLASH error code */ 123 uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing 124 or not in IT context */ 125 uint32_t Address; /* Internal variable to save address selected for program 126 in IT context */ 127 uint32_t Bank; /* Internal variable to save current bank selected during erase 128 in IT context */ 129 uint32_t Page; /* Internal variable to define the current page which is being erased 130 in IT context */ 131 uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 132 } FLASH_ProcessTypeDef; 133 134 /** 135 * @} 136 */ 137 138 /* Exported constants --------------------------------------------------------*/ 139 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 140 * @{ 141 */ 142 143 /** @defgroup FLASH_Flags FLASH Flags Definition 144 * @{ 145 */ 146 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 147 #define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */ 148 #define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */ 149 #define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */ 150 #define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */ 151 #define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */ 152 #define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */ 153 #define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */ 154 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 155 #define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */ 156 #define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */ 157 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 158 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 159 160 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 161 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) 162 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 163 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) 164 #else 165 #define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */ 166 #define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */ 167 #define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */ 168 #define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */ 169 #define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */ 170 #define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */ 171 #define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */ 172 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 173 #define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */ 174 #define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ 175 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 176 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 177 178 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 179 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 180 FLASH_FLAG_OPTWERR) 181 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 182 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) 183 #endif /* __ARM_FEATURE_CMSE */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 189 * @brief FLASH Interrupt definition 190 * @{ 191 */ 192 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 193 #define FLASH_IT_EOP FLASH_SECCR_EOPIE /*!< End of FLASH Operation Interrupt source */ 194 #define FLASH_IT_OPERR FLASH_SECCR_ERRIE /*!< Error Interrupt source */ 195 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 196 #else 197 #define FLASH_IT_EOP FLASH_NSCR_EOPIE /*!< End of FLASH Operation Interrupt source */ 198 #define FLASH_IT_OPERR FLASH_NSCR_ERRIE /*!< Error Interrupt source */ 199 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 200 #endif /* __ARM_FEATURE_CMSE */ 201 /** 202 * @} 203 */ 204 205 /** @defgroup FLASH_Error FLASH Error 206 * @{ 207 */ 208 #define HAL_FLASH_ERROR_NONE 0x00000000U 209 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 210 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 211 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 212 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 213 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 214 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 215 #define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR 216 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC 217 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 218 /** 219 * @} 220 */ 221 222 /** @defgroup FLASH_Type_Erase FLASH Erase Type 223 * @{ 224 */ 225 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 226 #define FLASH_TYPEERASE_PAGES FLASH_SECCR_PER /*!< Secure pages erase 227 activation */ 228 #define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase 229 activation */ 230 #define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_MER1 | FLASH_SECCR_MER2) /*!< Secure flash mass erase 231 activation */ 232 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_MER1 | FLASH_NSCR_MER2 | FLASH_NON_SECURE_MASK) /*!< Non-secure flash 233 mass erase activation */ 234 #else 235 #define FLASH_TYPEERASE_PAGES FLASH_NSCR_PER /*!< Pages erase activation */ 236 #define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_MER1 | FLASH_NSCR_MER2) /*!< Flash mass erase activation */ 237 #endif /* __ARM_FEATURE_CMSE */ 238 /** 239 * @} 240 */ 241 242 /** @defgroup FLASH_Banks FLASH Banks 243 * @{ 244 */ 245 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 246 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 247 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 248 /** 249 * @} 250 */ 251 252 /** @defgroup FLASH_Type_Program FLASH Program Type 253 * @{ 254 */ 255 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 256 #define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR_PG /*!< Program a quad-word (128-bit) 257 at a specified secure address */ 258 #define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) 259 at a specified non-secure address */ 260 #define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR_PG | FLASH_SECCR_BWR) /*!< Program a burst (8xquad-word) 261 at a specified secure address */ 262 #define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR_PG | FLASH_NSCR_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst 263 (8xquad-word) at a specified non-secure address */ 264 #else 265 #define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR_PG /*!<Program a quad-word (128-bit) 266 at a specified address */ 267 #define FLASH_TYPEPROGRAM_BURST (FLASH_NSCR_PG | FLASH_NSCR_BWR) /*!<Program a burst (8xquad-word) 268 at a specified address */ 269 #endif /* __ARM_FEATURE_CMSE */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 275 * @{ 276 */ 277 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 278 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 279 #define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ 280 #define OPTIONBYTE_BOOTADDR 0x00000008U /*!< Boot address option byte configuration */ 281 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 282 #define OPTIONBYTE_WMSEC 0x00000010U /*!< Watermark-based secure area option byte configuration */ 283 #define OPTIONBYTE_BOOT_LOCK 0x00000020U /*!< Boot lock option byte configuration */ 284 #endif /* __ARM_FEATURE_CMSE */ 285 #define OPTIONBYTE_RDPKEY 0x00000040U /*!< RDP Key option byte configuration */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 291 * @{ 292 */ 293 #define OB_WRPAREA_BANK1_AREAA 0x01U /*!< Flash Bank 1 Area A */ 294 #define OB_WRPAREA_BANK1_AREAB 0x02U /*!< Flash Bank 1 Area B */ 295 #define OB_WRPAREA_BANK2_AREAA 0x04U /*!< Flash Bank 2 Area A */ 296 #define OB_WRPAREA_BANK2_AREAB 0x08U /*!< Flash Bank 2 Area B */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 302 * @{ 303 */ 304 #define OB_RDP_LEVEL_0 0xAAU 305 #define OB_RDP_LEVEL_0_5 0x55U 306 #define OB_RDP_LEVEL_1 0xBBU 307 #define OB_RDP_LEVEL_2 0xCCU 308 /** 309 * @} 310 */ 311 312 /** @defgroup FLASH_OB_RDP_Key_Type FLASH Option Bytes Read Protection Key Type 313 * @{ 314 */ 315 #define OB_RDP_KEY_OEM1 0x01U /*!< OEM1 key */ 316 #define OB_RDP_KEY_OEM2 0x02U /*!< OEM2 key */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 322 * @{ 323 */ 324 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 325 #define OB_USER_NRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ 326 #define OB_USER_NRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ 327 #define OB_USER_NRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */ 328 #define OB_USER_SRAM134_RST 0x00000010U /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ 329 #define OB_USER_IWDG_SW 0x00000020U /*!< Independent watchdog selection */ 330 #define OB_USER_IWDG_STOP 0x00000040U /*!< Independent watchdog counter freeze in stop mode */ 331 #define OB_USER_IWDG_STDBY 0x00000080U /*!< Independent watchdog counter freeze in standby mode */ 332 #define OB_USER_WWDG_SW 0x00000100U /*!< Window watchdog selection */ 333 #define OB_USER_SWAP_BANK 0x00000200U /*!< Swap banks */ 334 #define OB_USER_DUALBANK 0x00000400U /*!< Dual-Bank on 1MB/512kB Flash memory devices */ 335 #define OB_USER_BKPRAM_ECC 0x00000800U /*!< Backup RAM ECC detection and correction enable */ 336 #define OB_USER_SRAM3_ECC 0x00001000U /*!< SRAM3 ECC detection and correction enable */ 337 #define OB_USER_SRAM2_ECC 0x00002000U /*!< SRAM2 ECC detection and correction enable */ 338 #define OB_USER_SRAM2_RST 0x00004000U /*!< SRAM2 Erase when system reset */ 339 #define OB_USER_NSWBOOT0 0x00008000U /*!< Software BOOT0 */ 340 #define OB_USER_NBOOT0 0x00010000U /*!< nBOOT0 option bit */ 341 #define OB_USER_PA15_PUPEN 0x00020000U /*!< PA15 pull-up enable option bit */ 342 #define OB_USER_IO_VDD_HSLV 0x00040000U /*!< High speed IO at low voltage configuration bit */ 343 #define OB_USER_IO_VDDIO2_HSLV 0x00080000U /*!< High speed IO at low VDDIO2 voltage configuration bit */ 344 #define OB_USER_TZEN 0x00100000U /*!< Global TrustZone security enable */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 350 * @{ 351 */ 352 #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold 353 is around 1.7V */ 354 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold 355 is around 2.0V */ 356 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold 357 is around 2.2V */ 358 #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_1 | FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold 359 is around 2.5V */ 360 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold 361 is around 2.8V */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 367 * @{ 368 */ 369 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 370 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 376 * @{ 377 */ 378 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 379 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 385 * @{ 386 */ 387 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 388 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup FLASH_OB_USER_SRAM134_RST FLASH Option Bytes User SRAM134 Erase On Reset Type 394 * @{ 395 */ 396 #define OB_SRAM134_RST_ERASE 0x00000000U /*!< SRAM1, SRAM3 and SRAM4 erased 397 when a system reset occurs */ 398 #define OB_SRAM134_RST_NOT_ERASE FLASH_OPTR_SRAM134_RST /*!< SRAM1, SRAM3 and SRAM4 are not erased 399 when a system reset occurs */ 400 /** 401 * @} 402 */ 403 404 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 405 * @{ 406 */ 407 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 408 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 414 * @{ 415 */ 416 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 417 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 423 * @{ 424 */ 425 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 426 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 427 /** 428 * @} 429 */ 430 431 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 432 * @{ 433 */ 434 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 435 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH Option Bytes User Swap banks 441 * @{ 442 */ 443 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank 1 is located at address offset 0x0, 444 Bank 2 is located at 0x100000 */ 445 #define OB_SWAP_BANK_ENABLE FLASH_OPTR_SWAP_BANK /*!< Bank 1 is located at address offset 0x100000, 446 Bank 2 is located at 0x0 */ 447 /** 448 * @} 449 */ 450 451 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 452 * @{ 453 */ 454 #define OB_DUALBANK_SINGLE 0x00000000U /*!< 1MB/512KB Single-bank Flash */ 455 #define OB_DUALBANK_DUAL FLASH_OPTR_DUALBANK /*!< 1MB/512KB Dual-bank Flash */ 456 /** 457 * @} 458 */ 459 460 /** @defgroup FLASH_OB_USER_BKPRAM_RST FLASH Option Bytes User BKPRAM ECC check 461 * @{ 462 */ 463 #define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */ 464 #define OB_BKPRAM_ECC_DISABLE FLASH_OPTR_BKPRAM_ECC /*!< BKPRAM ECC check disable */ 465 /** 466 * @} 467 */ 468 469 /** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check 470 * @{ 471 */ 472 #define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */ 473 #define OB_SRAM3_ECC_DISABLE FLASH_OPTR_SRAM3_ECC /*!< SRAM3 ECC check disable */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check 479 * @{ 480 */ 481 #define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */ 482 #define OB_SRAM2_ECC_DISABLE FLASH_OPTR_SRAM2_ECC /*!< SRAM2 ECC check disable */ 483 /** 484 * @} 485 */ 486 487 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 488 * @{ 489 */ 490 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 491 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 492 /** 493 * @} 494 */ 495 496 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 497 * @{ 498 */ 499 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 500 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from BOOT0 pin */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 506 * @{ 507 */ 508 #define OB_NBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 509 #define OB_NBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup FLASH_OB_USER_PA15_PUPEN FLASH Option Bytes User PA15 pull-up enable option bit 515 * @{ 516 */ 517 #define OB_PA15_PUP_DISABLE 0x00000000U /*!< USB power delivery dead-battery 518 enabled / TDI pull-up deactivated */ 519 #define OB_PA15_PUP_ENABLE FLASH_OPTR_PA15_PUPEN /*!< USB power delivery dead-battery 520 disabled / TDI pull-up activated */ 521 /** 522 * @} 523 */ 524 525 /** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes User High speed IO at low voltage configuration bit 526 * @{ 527 */ 528 #define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled 529 (VDD can exceed 2.5 V) */ 530 #define OB_IO_VDD_HSLV_ENABLE FLASH_OPTR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled 531 (VDD remains below 2.5 V) */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes User High speed IO at low VDDIO2 voltage configuration bit 537 * @{ 538 */ 539 #define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature disabled 540 (VDDIO2 can exceed 2.5 V) */ 541 #define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature enabled 542 (VDDIO2 remains below 2.5 V) */ 543 /** 544 * @} 545 */ 546 547 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone 548 * @{ 549 */ 550 #define OB_TZEN_DISABLE 0x00000000U /*!< Global TrustZone security disabled */ 551 #define OB_TZEN_ENABLE FLASH_OPTR_TZEN /*!< Global TrustZone security enabled */ 552 /** 553 * @} 554 */ 555 556 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 557 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 558 * @{ 559 */ 560 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */ 561 #define OB_BOOT_LOCK_ENABLE FLASH_SECBOOTADD0R_BOOT_LOCK /*!< Boot lock enable */ 562 /** 563 * @} 564 */ 565 566 /** @defgroup FLASH_OB_WMSEC FLASH Option Bytes Watermarked-based security configuration 567 * @{ 568 */ 569 #define OB_WMSEC_AREA1 FLASH_BANK_1 /*!< Watermarked-based security area for bank 1 */ 570 #define OB_WMSEC_AREA2 FLASH_BANK_2 /*!< Watermarked-based security area for bank 2 */ 571 572 #define OB_WMSEC_SECURE_AREA_CONFIG 0x00000010U /*!< Configure Watermarked-based security area */ 573 #define OB_WMSEC_HDP_AREA_CONFIG 0x00000020U /*!< Configure Watermarked-based secure hide area */ 574 #define OB_WMSEC_HDP_AREA_ENABLE 0x00000080U /*!< Enable Watermarked-based secure hide area */ 575 #define OB_WMSEC_HDP_AREA_DISABLE 0x00000100U /*!< Disable Watermarked-based secure hide area */ 576 /** 577 * @} 578 */ 579 #endif /* __ARM_FEATURE_CMSE */ 580 581 /** @defgroup FLASH_OB_BOOTADDR FLASH Option Bytes Boot address 582 * @{ 583 */ 584 #define OB_BOOTADDR_NS0 0x00000001U /*!< Non-secure boot address 0 */ 585 #define OB_BOOTADDR_NS1 0x00000002U /*!< Non-secure boot address 1 */ 586 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 587 #define OB_BOOTADDR_SEC0 0x00000004U /*!< Secure boot address 0 */ 588 #endif /* __ARM_FEATURE_CMSE */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup FLASH_Latency FLASH Latency 594 * @{ 595 */ 596 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 597 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 598 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 599 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 600 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 601 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 602 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 603 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 604 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 605 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 606 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 607 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 608 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 609 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 610 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 611 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup FLASH_Keys FLASH Keys 617 * @{ 618 */ 619 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 620 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 621 to unlock the FLASH registers access */ 622 623 #define FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank 1 power down key1 */ 624 #define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank 1 power down key2: used with FLASH_PDKEY1_1 625 to unlock the PDREQ1 bit in FLASH_ACR */ 626 627 #define FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank 2 power down key1 */ 628 #define FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank 2 power down key2: used with FLASH_PDKEY2_1 629 to unlock the PDREQ2 bit in FLASH_ACR */ 630 631 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 632 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 633 to allow option bytes operations */ 634 /** 635 * @} 636 */ 637 638 /** 639 * @} 640 */ 641 642 /* Exported macros -----------------------------------------------------------*/ 643 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 644 * @brief macros to control FLASH features 645 * @{ 646 */ 647 648 /** 649 * @brief Set the FLASH Latency. 650 * @param __LATENCY__ FLASH Latency 651 * This parameter can be one of the following values : 652 * @arg FLASH_LATENCY_0: FLASH Zero wait state 653 * @arg FLASH_LATENCY_1: FLASH One wait state 654 * @arg FLASH_LATENCY_2: FLASH Two wait states 655 * @arg FLASH_LATENCY_3: FLASH Three wait states 656 * @arg FLASH_LATENCY_4: FLASH Four wait states 657 * @arg FLASH_LATENCY_5: FLASH Five wait states 658 * @arg FLASH_LATENCY_6: FLASH Six wait states 659 * @arg FLASH_LATENCY_7: FLASH Seven wait states 660 * @arg FLASH_LATENCY_8: FLASH Eight wait states 661 * @arg FLASH_LATENCY_9: FLASH Nine wait states 662 * @arg FLASH_LATENCY_10: FLASH Ten wait states 663 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 664 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 665 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 666 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 667 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 668 * @retval None 669 */ 670 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) 671 672 /** 673 * @brief Get the FLASH Latency. 674 * @retval FLASH Latency 675 * This return value can be one of the following values : 676 * @arg FLASH_LATENCY_0: FLASH Zero wait state 677 * @arg FLASH_LATENCY_1: FLASH One wait state 678 * @arg FLASH_LATENCY_2: FLASH Two wait states 679 * @arg FLASH_LATENCY_3: FLASH Three wait states 680 * @arg FLASH_LATENCY_4: FLASH Four wait states 681 * @arg FLASH_LATENCY_5: FLASH Five wait states 682 * @arg FLASH_LATENCY_6: FLASH Six wait states 683 * @arg FLASH_LATENCY_7: FLASH Seven wait states 684 * @arg FLASH_LATENCY_8: FLASH Eight wait states 685 * @arg FLASH_LATENCY_9: FLASH Nine wait states 686 * @arg FLASH_LATENCY_10: FLASH Ten wait states 687 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 688 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 689 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 690 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 691 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 692 */ 693 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 694 695 /** 696 * @brief Enable the FLASH prefetch buffer. 697 * @retval None 698 */ 699 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 700 701 /** 702 * @brief Disable the FLASH prefetch buffer. 703 * @retval None 704 */ 705 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 706 707 /** 708 * @brief Enable the FLASH power down during Low-Power sleep mode 709 * @retval none 710 */ 711 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 712 713 /** 714 * @brief Disable the FLASH power down during Low-Power sleep mode 715 * @retval none 716 */ 717 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 718 719 /** 720 * @} 721 */ 722 723 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 724 * @brief macros to handle FLASH interrupts 725 * @{ 726 */ 727 728 /** 729 * @brief Enable the specified FLASH interrupt. 730 * @param __INTERRUPT__ FLASH interrupt 731 * This parameter can be any combination of the following values: 732 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 733 * @arg FLASH_IT_OPERR: Error Interrupt 734 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 735 * @retval none 736 */ 737 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 738 /* Enable secure FLASH interrupts from the secure world */ 739 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 740 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 741 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 742 { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 743 } while(0) 744 /* Enable non-secure FLASH interrupts from the secure world */ 745 #define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 746 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 747 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 748 { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 749 } while(0) 750 #else 751 /* Enable non-secure FLASH interrupts from the non-secure world */ 752 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 753 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 754 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 755 { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 756 } while(0) 757 #endif /* __ARM_FEATURE_CMSE */ 758 759 /** 760 * @brief Disable the specified FLASH interrupt. 761 * @param __INTERRUPT__ FLASH interrupt 762 * This parameter can be any combination of the following values: 763 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 764 * @arg FLASH_IT_OPERR: Error Interrupt 765 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 766 * @retval none 767 */ 768 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 769 /* Disable secure FLASH interrupts from the secure world */ 770 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 771 { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 772 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 773 { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));}\ 774 } while(0) 775 /* Disable non-secure FLASH interrupts from the secure world */ 776 #define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 777 { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ 778 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 779 { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & \ 780 (~FLASH_IT_ECCC))); }\ 781 } while(0) 782 #else 783 /* Disable non-secure FLASH interrupts from the non-secure world */ 784 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ 785 { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 786 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ 787 { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 788 } while(0) 789 #endif /* __ARM_FEATURE_CMSE */ 790 791 /** 792 * @brief Check whether the specified FLASH flag is set or not. 793 * @param __FLAG__ specifies the FLASH flag to check. 794 * This parameter can be one of the following values: 795 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 796 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 797 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 798 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 799 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 800 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 801 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 802 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 803 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 804 * @arg FLASH_FLAG_WDW: FLASH Wait Data to Write flag 805 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 806 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 807 * @retval The new state of FLASH_FLAG (SET or RESET). 808 */ 809 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 810 /* Get secure FLASH flags from the secure world */ 811 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 812 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 813 ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ 814 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ 815 (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) 816 /* Get non-secure FLASH flags from the secure world */ 817 #define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 818 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 819 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 820 #else 821 /* Get non-secure FLASH flags from the non-secure world */ 822 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 823 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 824 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 825 #endif /* __ARM_FEATURE_CMSE */ 826 827 /** 828 * @brief Clear the FLASH's pending flags. 829 * @param __FLAG__ specifies the FLASH flags to clear. 830 * This parameter can be any combination of the following values: 831 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 832 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 833 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 834 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 835 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 836 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 837 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 838 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 839 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 840 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 841 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 842 * @retval None 843 */ 844 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 845 /* Clear secure FLASH flags from the secure world */ 846 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ 847 { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 848 if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) \ 849 { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ 850 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \ 851 FLASH_FLAG_OPTWERR)) != 0U) \ 852 { WRITE_REG(FLASH->SECSR, ((__FLAG__) & \ 853 ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); }\ 854 } while(0) 855 /* Clear non-secure FLASH flags from the secure world */ 856 #define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ 857 { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 858 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ 859 { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ 860 ~(FLASH_FLAG_ECCR_ERRORS))); }\ 861 } while(0) 862 #else 863 /* Clear non-secure FLASH flags from the non-secure world */ 864 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ 865 { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 866 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ 867 { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ 868 ~(FLASH_FLAG_ECCR_ERRORS))); }\ 869 } while(0) 870 #endif /* __ARM_FEATURE_CMSE */ 871 /** 872 * @} 873 */ 874 875 /* Include FLASH HAL Extended module */ 876 #include "stm32u5xx_hal_flash_ex.h" 877 878 879 /* Exported functions --------------------------------------------------------*/ 880 /** @addtogroup FLASH_Exported_Functions 881 * @{ 882 */ 883 884 /* Program operation functions ***********************************************/ 885 /** @addtogroup FLASH_Exported_Functions_Group1 886 * @{ 887 */ 888 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); 889 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); 890 /* FLASH IRQ handler method */ 891 void HAL_FLASH_IRQHandler(void); 892 /* Callbacks in non blocking modes */ 893 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 894 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 895 /** 896 * @} 897 */ 898 899 /* Peripheral Control functions **********************************************/ 900 /** @addtogroup FLASH_Exported_Functions_Group2 901 * @{ 902 */ 903 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 904 HAL_StatusTypeDef HAL_FLASH_Lock(void); 905 /* Option bytes control */ 906 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 907 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 908 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 909 /** 910 * @} 911 */ 912 913 /* Peripheral State functions ************************************************/ 914 /** @addtogroup FLASH_Exported_Functions_Group3 915 * @{ 916 */ 917 uint32_t HAL_FLASH_GetError(void); 918 /** 919 * @} 920 */ 921 922 /** 923 * @} 924 */ 925 926 /* Private variables ---------------------------------------------------------*/ 927 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 928 * @{ 929 */ 930 extern FLASH_ProcessTypeDef pFlash; 931 /** 932 * @} 933 */ 934 935 /* Private constants --------------------------------------------------------*/ 936 /** @defgroup FLASH_Private_Constants FLASH Private Constants 937 * @{ 938 */ 939 940 #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ 941 942 #define FLASH_NON_SECURE_MASK 0x80000000U 943 944 #define FLASH_NB_WORDS_IN_BURST 32 945 946 /** 947 * @} 948 */ 949 950 /* Private macros ------------------------------------------------------------*/ 951 /** @defgroup FLASH_Private_Macros FLASH Private Macros 952 * @{ 953 */ 954 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 955 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 956 ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ 957 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 958 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) 959 #else 960 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 961 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 962 #endif /* __ARM_FEATURE_CMSE */ 963 964 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 965 ((BANK) == FLASH_BANK_2) || \ 966 ((BANK) == FLASH_BANK_BOTH)) 967 968 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 969 ((BANK) == FLASH_BANK_2)) 970 971 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 972 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ 973 ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ 974 ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ 975 ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) 976 #else 977 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ 978 ((VALUE) == FLASH_TYPEPROGRAM_BURST)) 979 #endif /* __ARM_FEATURE_CMSE */ 980 981 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 982 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ 983 (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) 984 #else 985 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) 986 #endif /* __ARM_FEATURE_CMSE */ 987 988 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE)\ 989 && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) 990 991 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 992 993 #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) 994 995 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 996 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 997 OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \ 998 OPTIONBYTE_RDPKEY))) 999 #else 1000 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 1001 OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) 1002 #endif /* __ARM_FEATURE_CMSE */ 1003 1004 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 1005 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 1006 1007 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 1008 ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ 1009 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 1010 ((LEVEL) == OB_RDP_LEVEL_2)) 1011 1012 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFFU) && ((TYPE) != 0U)) 1013 1014 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 1015 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 1016 ((LEVEL) == OB_BOR_LEVEL_4)) 1017 1018 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 1019 1020 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 1021 1022 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 1023 1024 #define IS_OB_USER_SRAM134_RST(VALUE) (((VALUE) == OB_SRAM134_RST_ERASE) || ((VALUE) == OB_SRAM134_RST_NOT_ERASE)) 1025 1026 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 1027 1028 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 1029 1030 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 1031 1032 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 1033 1034 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 1035 1036 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 1037 1038 #define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) 1039 1040 #define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) 1041 1042 #define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) 1043 1044 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 1045 1046 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 1047 1048 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_NBOOT0_RESET) || ((VALUE) == OB_NBOOT0_SET)) 1049 1050 #define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE)) 1051 1052 #define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) 1053 1054 #define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE)\ 1055 || ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) 1056 1057 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 1058 1059 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1060 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 1061 1062 #define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F3U) != 0U) && \ 1063 (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFF80CU) == 0U)) 1064 1065 #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && \ 1066 (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ 1067 ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && \ 1068 (((WMSEC) & OB_WMSEC_AREA1) == 0U))) 1069 #endif /* __ARM_FEATURE_CMSE */ 1070 1071 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1072 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ 1073 ((CFG) == OB_BOOTADDR_SEC0)) 1074 #else 1075 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) 1076 #endif /* __ARM_FEATURE_CMSE */ 1077 1078 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 1079 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 1080 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 1081 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 1082 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 1083 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 1084 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1085 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1086 1087 #define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \ 1088 ((TYPE) == OB_RDP_KEY_OEM2)) 1089 1090 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1091 #define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) 1092 #else 1093 #define IS_FLASH_SECURE_OPERATION() (0U) 1094 #endif /* __ARM_FEATURE_CMSE */ 1095 /** 1096 * @} 1097 */ 1098 1099 /* Private functions ---------------------------------------------------------*/ 1100 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 1101 * @{ 1102 */ 1103 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 1104 /** 1105 * @} 1106 */ 1107 1108 /** 1109 * @} 1110 */ 1111 1112 /** 1113 * @} 1114 */ 1115 1116 #ifdef __cplusplus 1117 } 1118 #endif 1119 1120 #endif /* STM32U5xx_HAL_FLASH_H */ 1121 1122
