1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Netc_Eth_Ip.c
9 *
10 * @addtogroup NETC_ETH_DRIVER NETC_ETH Driver
11 * @internal
12 * @{
13 */
14
15 #ifdef __cplusplus
16 extern "C"{
17 #endif
18
19 /*==================================================================================================
20 * INCLUDE FILES
21 * 1) system and project includes
22 * 2) needed interfaces from external units
23 * 3) internal and external interfaces from this unit
24 ==================================================================================================*/
25 #include "Netc_Eth_Ip.h"
26 #include "OsIf.h" /* Used for timeouts. */
27 #include "SchM_Eth_43_NETC.h"
28
29 #if(NETC_ETH_IP_DEV_ERROR_DETECT == STD_ON)
30 #include "Devassert.h"
31 #endif
32 #if(NETC_ETH_IP_HAS_CACHE_MANAGEMENT == STD_ON)
33 #include "Cache_Ip.h"
34 #endif
35
36 /*==================================================================================================
37 * SOURCE FILE VERSION INFORMATION
38 ==================================================================================================*/
39 #define NETC_ETH_IP_VENDOR_ID_C 43
40 #define NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION_C 4
41 #define NETC_ETH_IP_AR_RELEASE_MINOR_VERSION_C 7
42 #define NETC_ETH_IP_AR_RELEASE_REVISION_VERSION_C 0
43 #define NETC_ETH_IP_SW_MAJOR_VERSION_C 1
44 #define NETC_ETH_IP_SW_MINOR_VERSION_C 0
45 #define NETC_ETH_IP_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * FILE VERSION CHECKS
49 ==================================================================================================*/
50 /* Checks against Netc_Eth_Ip.h */
51 #if (NETC_ETH_IP_VENDOR_ID_C != NETC_ETH_IP_VENDOR_ID)
52 #error "Netc_Eth_Ip.c and Netc_Eth_Ip.h have different vendor ids"
53 #endif
54 #if (( NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION) || \
55 ( NETC_ETH_IP_AR_RELEASE_MINOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MINOR_VERSION) || \
56 ( NETC_ETH_IP_AR_RELEASE_REVISION_VERSION_C != NETC_ETH_IP_AR_RELEASE_REVISION_VERSION))
57 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
58 #endif
59 #if (( NETC_ETH_IP_SW_MAJOR_VERSION_C != NETC_ETH_IP_SW_MAJOR_VERSION) || \
60 ( NETC_ETH_IP_SW_MINOR_VERSION_C != NETC_ETH_IP_SW_MINOR_VERSION) || \
61 ( NETC_ETH_IP_SW_PATCH_VERSION_C != NETC_ETH_IP_SW_PATCH_VERSION))
62 #error "Software Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
63 #endif
64
65 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
66 /* Checks against OsIf.h */
67 #if ((NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
68 (NETC_ETH_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION))
69 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and OsIf.h are different!"
70 #endif
71 #endif
72
73 /*==================================================================================================
74 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
75 ==================================================================================================*/
76
77 /*==================================================================================================
78 * LOCAL MACROS
79 ==================================================================================================*/
80 #define NETC_ETH_IP_NANO_TO_SECONDS(x) ((x)/1000000000U)
81 #define NETC_ETH_IP_GET_NANOSECONDS(x) ((x)%1000000000U)
82 /*==================================================================================================
83 * LOCAL CONSTANTS
84 ==================================================================================================*/
85 /* Formula for speed: 10Mbps * (PSPEED+1) */
86 #define NETC_ETH_IP_SHAPING_PSPEED_2000MBITS (199U)
87
88 #define NETC_ETH_IP_SECONDS_LOW_MASK_U64 (0xFFFFFFFFULL)
89
90 #define NETC_ETH_IP_FATAL_ERROR (0x1u)
91 #define NETC_ETH_IP_NON_FATAL_ERROR (0x2u)
92 #define NETC_ETH_IP_CORRECTABLE_ERROR (0x4u)
93 #define NETC_ETH_IP_PSI0_FUNCTION_INDEX (4u)
94 #define NETC_ETH_IP_CLEAR_ERROR_STATUS_MASK (0x80000000U)
95
96 #define NETC_ETH_IP_UCORR_STATUS_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK)
97 #define NETC_ETH_IP_CORR_STATUS_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK)
98 #define NETC_ETH_IP_UCORR_ERR_MASK_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK)
99 #define NETC_ETH_IP_CORR_ERR_MASK_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK)
100 #define NETC_ETH_IP_UCORR_ERR_MASK_SHIFT (NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT)
101 #define NETC_ETH_IP_CORR_ERR_MASK_SHIFT (NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT)
102 #define NETC_ETH_IP_UCORR_SEV_MASK ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK)
103 /*==================================================================================================
104 * LOCAL VARIABLES
105 ==================================================================================================*/
106
107 /*==================================================================================================
108 * GLOBAL CONSTANTS
109 ==================================================================================================*/
110 #define ETH_43_NETC_START_SEC_VAR_INIT_UNSPECIFIED
111 #include "Eth_43_NETC_MemMap.h"
112 extern Netc_Eth_Ip_SiBaseType *netcSIsBase[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
113 extern Netc_Eth_Ip_VfBaseType *netcVFBase[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
114 extern Netc_Eth_Ip_PCIeBaseType *netcPCIePFBase[FEATURE_NETC_NUMBER_OF_FUNC];
115 #define ETH_43_NETC_STOP_SEC_VAR_INIT_UNSPECIFIED
116 #include "Eth_43_NETC_MemMap.h"
117
118 #define ETH_43_NETC_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
119 #include "Eth_43_NETC_MemMap.h"
120 VAR_SEC_NOCACHE(MACFilterHashTableAddrs) extern Netc_Eth_Ip_MACFilterHashTableEntryType *MACFilterHashTableAddrs[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
121
122 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
123 #include "Eth_43_NETC_MemMap.h"
124
125 #if ((NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON) || (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON))
126 #define ETH_43_NETC_START_SEC_CONST_BOOLEAN
127 #include "Eth_43_NETC_MemMap.h"
128
129 #if (NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
130 /** @brief Table storing information related to the method of Tx Data Buffers Management.*/
131 static const boolean Netc_Eth_Ip_ControllerHasExternalTxBufferManagement[FEATURE_NETC_ETH_NUMBER_OF_CTRLS] = NETC_ETH_IP_INST_HAS_EXTERNAL_TX_BUFFERS;
132 #endif
133
134 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
135 /** @brief Table storing information related to the method of Rx Data Buffers Management.*/
136 static const boolean Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[FEATURE_NETC_ETH_NUMBER_OF_CTRLS] = NETC_ETH_IP_INST_HAS_EXTERNAL_RX_BUFFERS;
137 #endif
138
139 #define ETH_43_NETC_STOP_SEC_CONST_BOOLEAN
140 #include "Eth_43_NETC_MemMap.h"
141
142 #endif /* ((NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON) || (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)) */
143 /*==================================================================================================
144 * GLOBAL VARIABLES
145 ==================================================================================================*/
146
147 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
148 #ifdef NETC_ETH_0_USED
149 #define ETH_43_NETC_START_SEC_VAR_CLEARED_UNSPECIFIED
150 #include "Eth_43_NETC_MemMap.h"
151 /** @brief Store timestamp information of transmitted frames. */
152 extern volatile Netc_Eth_Ip_TxManagementInfoType Netc_Eth_Ip_TxManagementInfoBuff[NETC_ETH_IP_NUM_OF_PHYSICAL_CTRLS][NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR];
153 extern volatile Netc_Eth_Ip_TxTimestampInfoType Netc_Eth_Ip_TxTimestampInfoBuff[NETC_ETH_IP_NUM_OF_PHYSICAL_CTRLS][NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR];
154 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
155 #include "Eth_43_NETC_MemMap.h"
156 #endif /* NETC_ETH_0_USED */
157
158 #define ETH_43_NETC_START_SEC_VAR_CLEARED_32
159 #include "Eth_43_NETC_MemMap.h"
160 #ifdef NETC_ETH_0_USED
161 /** @brief Store timestamp information of transmitted frames. */
162
163 static uint32 TxTimestampInfoBuffIdx = 0U;
164
165 #endif /* NETC_ETH_0_USED */
166
167 static uint32 Netc_Eth_Ip_RxTimestampID = (uint32)0U;
168
169 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_32
170 #include "Eth_43_NETC_MemMap.h"
171
172 /** @brief Store timestamp information of received frames. */
173 /** TODO: get the maximum of descr between variants */
174 extern volatile Netc_Eth_Ip_RxTimestampInfoType Netc_Eth_Ip_RxTimestampInfoBuff[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_RXRINGS][NETC_ETH_IP_MAX_NUMBER_OF_RXDESCRIPTORS];
175 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
176
177 #define ETH_43_NETC_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
178 #include "Eth_43_NETC_MemMap.h"
179
180 /** @brief Pointers to NETC internal driver state for each controller(SI). */
181 VAR_SEC_NOCACHE(Netc_Eth_Ip_apxState) Netc_Eth_Ip_StateType *Netc_Eth_Ip_apxState[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
182
183 /** @brief List of Error Reporting structures that aggregate information for each Pcie function in case of an error reported to the Event Collector. EMDIO, TIMER, SWITCH, ENETC, PSI0, VSI1-7*/
184 VAR_SEC_NOCACHE(Netc_Eth_Ip_ErrorStatus) volatile Netc_Eth_Ip_PcieFunctionErrorsReported Netc_Eth_Ip_ErrorStatus[FEATURE_NETC_NUMBER_OF_FUNC + FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS + 1U];
185
186 /* Enabled status for Time Aware Shaper for PSI */
187 VAR_SEC_NOCACHE(Netc_Eth_Ip_PortTimeAwareShaperEnabled) static boolean Netc_Eth_Ip_PortTimeAwareShaperEnabled = FALSE;
188
189 /* Table entries for Time Aware Shaping configuration */
190 VAR_SEC_NOCACHE(Netc_Eth_Ip_EthTimeGateSchedulingEntryData) static Netc_Eth_Ip_TimeGateSchedulingEntryDataType Netc_Eth_Ip_EthTimeGateSchedulingEntryData;
191
192 /* The frequency of the NETC module for computing CBS parameters */
193 VAR_SEC_NOCACHE(Netc_Eth_Ip_NetcClockFrequency) static uint32 Netc_Eth_Ip_NetcClockFrequency = 0U;
194
195 /* Key element data for ingress port filter table */
196 VAR_SEC_NOCACHE(IPFKeyeData) static volatile uint32 IPFKeyeData[NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN];
197
198 /* a 16 bytes aligned table request data buffer */
199 VAR_SEC_NOCACHE(Netc_Eth_Ip_EnetcTableDataBuffer) VAR_ALIGN(static volatile Netc_Eth_Ip_EnetcTableDataType Netc_Eth_Ip_EnetcTableDataBuffer, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
200
201 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
202 #include "Eth_43_NETC_MemMap.h"
203
204 #if (NETC_ETH_IP_HAS_CACHE_MANAGEMENT == STD_ON)
205 /* FEATURE_NETC_CACHABLE_BUFFERS_LMEM and FEATURE_NETC_CACHABLE_BUFFERS_CORE are generated based on the
206 platform and the core type in case both cache IPs are supported.
207 These macros must be both defined for the driver when the cache management feature is enabled.
208 They must not be simultaneosly enabled at runtime.*/
209 #ifdef FEATURE_NETC_CACHABLE_BUFFERS_LMEM
210 #ifdef FEATURE_NETC_CACHABLE_BUFFERS_CORE
211 #define ETH_43_NETC_START_SEC_CONST_UNSPECIFIED
212 #include "Eth_43_NETC_MemMap.h"
213 #if (FEATURE_NETC_CACHABLE_BUFFERS_LMEM > 0U)
214 /** @brief Global variable which contains the type of CACHE Type used on the current platform.
215 * CACHE_IP_LMEM is using LMEM peripheral.
216 * CACHE_IP_CORE is using SCB peripheral.
217 */
218 static const Cache_Ip_Type CacheType = CACHE_IP_LMEM;
219 #elif (FEATURE_NETC_CACHABLE_BUFFERS_CORE > 0U)
220 /** @brief Global variable which contains the type of CACHE Type used on the current platform.
221 * CACHE_IP_LMEM is using LMEM peripheral.
222 * CACHE_IP_CORE is using SCB peripheral.
223 */
224 static const Cache_Ip_Type CacheType = CACHE_IP_CORE;
225 #endif
226 #define ETH_43_NETC_STOP_SEC_CONST_UNSPECIFIED
227 #include "Eth_43_NETC_MemMap.h"
228 #endif /* defined (FEATURE_NETC_CACHABLE_BUFFERS_CORE) */
229 #endif /* defined (FEATURE_NETC_CACHABLE_BUFFERS_LMEM) */
230 #endif /*NETC_HAS_CACHE_MANAGEMENT == STD_ON */
231
232 /*==================================================================================================
233 * LOCAL FUNCTION PROTOTYPES
234 ==================================================================================================*/
235 #define ETH_43_NETC_START_SEC_CODE
236 #include "Eth_43_NETC_MemMap.h"
237 /**
238 * @brief For each controller(station interface) state structure will be initialized.
239 *
240 * @param ctrlIndex
241 * @param config
242 */
243 static void Netc_Eth_Ip_InitStateStructure(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
244 /**
245 * @brief Initialize all BD rings for the current SI.
246 *
247 * @param ctrlIndex Number of the current SI.
248 * @param config General configuration of the controller.
249 */
250 static void Netc_Eth_Ip_InitTxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
251 static void Netc_Eth_Ip_InitRxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
252
253 /**
254 * @brief
255 *
256 * @param ctrlIndex
257 */
258 static void Netc_Eth_Ip_InitCBDR(uint8 ctrlIndex);
259
260 /**
261 * @brief This function will be used to enable and set all the configuration for interrupt.
262 * @details Number of defaults MSI entries in table for ENETC is 48.
263 *
264 * @param ctrlIndex Number of the current SI.
265 * @param config General configuration of the controller.
266 */
267 void Netc_Eth_Ip_EnableIrq(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
268
269 /**
270 * @brief Prepare to use a timeout.
271 *
272 * @param StartTimeOut Current value of selected counter.
273 * @param ElapsedTimeOut Reset elapsed time to 0.
274 * @param TimeoutTicksOut TimeoutUs converted from microsecond units to ticks units.
275 * @param TimeoutUs Timeout value in microsecond.
276 */
277 static inline void Netc_Eth_Ip_StartTimeOut(uint32 *StartTimeOut,
278 uint32 *ElapsedTimeOut,
279 uint32 *TimeoutTicksOut,
280 uint32 TimeoutUs);
281
282 /**
283 * @brief Checks for timeout expiration condition.
284 *
285 * @param StartTimeInOut Initial value of the counter.
286 * @param ElapsedTimeInOut Current ticks passed.
287 * @param TimeoutTicks Number of ticks after timout will be activated.
288 *
289 * @return boolean TRUE - timout activated.
290 * FALSE - timeout is not yet reached.
291 */
292 static inline boolean Netc_Eth_Ip_TimeoutExpired(uint32 *StartTimeInOut,
293 uint32 *ElapsedTimeInOut,
294 uint32 TimeoutTicks);
295 /**
296 * @brief Add MAC addr in the software table.
297 *
298 * @param CtrlIndex Index of the SI.
299 * @param HashValue Computed hash value.
300 * @param MacAddr MAC address.
301 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
302 * NETC_ETH_IP_STATUS_MAC_ADDR_TABLE_FULL - MAC table used for hash filter is full
303 */
304 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddMACFilterEntry(uint8 CtrlIndex, uint8 HashValue, const uint8 *MacAddr);
305
306 /**
307 * @brief Compute has value for MAC addr.
308 *
309 * @param MacAddr MAC address.
310 * @return uint8 Hash value for MacAddr.
311 */
312 static inline uint8 Netc_Eth_Ip_ComputeMACHashValue(const uint8 *MacAddr);
313
314 /**
315 * @brief Send message from the VSI to PSI.
316 *
317 * @param VsiId Index of the VSI.
318 * @param MsgAction Type of action. Description in types.
319 * @param MacAddr MAC address.
320 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
321 * NETC_ETH_IP_STATUS_ERROR - unsuccessfully operation
322 * NETC_ETH_IP_STATUS_MAC_ADDR_TABLE_FULL - MAC table used for hash filter is full
323 * NETC_ETH_IP_STATUS_TIMEOUT - Only for VSIs - the command was not processed in the allotted time
324 * NETC_ETH_IP_STATUS_MAC_ADDR_NOT_FOUND - the current destination MAC was not
325 * found in the hash filter table
326 */
327 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsiMsg(uint8 VsiId, \
328 Netc_Eth_Ip_VsiToPsiMsgActionType MsgAction, \
329 const uint8 *MacAddr, \
330 uint16 * PsiRspMessage );
331 /**
332 * @brief Remove MAC addr in the software table.
333 *
334 * @param CtrlIndex Index of the SI.
335 * @param HashValue Computed hash value.
336 * @param MacAddr MAC address.
337 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
338 * NETC_ETH_IP_STATUS_ERROR - unsuccessfully operation
339 * NETC_ETH_IP_STATUS_MAC_ADDR_NOT_FOUND - the current destination MAC was not
340 * found in the hash filter table
341 */
342 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteMACFilterEntry(const uint8 CtrlIndex, \
343 const uint8 HashValue, \
344 const uint8 *MacAddr);
345
346 /**
347 * @brief Wait until the command is send from the VSI to the PSI.
348 *
349 * @param VsiId Index of the SI.
350 * @param MsgCommandConfig Message command.
351 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
352 * NETC_ETH_IP_STATUS_TIMEOUT - Only for VSIs - the command was not processed in the allotted time
353 */
354 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(uint8 VsiId, const Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig, uint16 * PsiRspMessage);
355
356 /**
357 * @brief Performs a transformation to a hardware specific value which sets the
358 * packets threshold for tx colaescing interrupt.
359 * The return value is a hardware specific value which will be set in the ICTT part of the TBxICR0 register. It will be
360 * the greatest value which satisfies the following formula.
361 * PacketsThreshold >= 2 ^(TwoPow-1)
362 *
363 *
364 * @param PacketsThreshold The number of packets for coalescing interrupt.
365 * @return uint8 Hardware specific value which will be set in the ICTT part of the TBxICR0 register. It will be
366 * the greatest value which satisfies the following formula.
367 */
368 static uint8 Netc_Eth_Ip_CoalescingTxPacketsConversion (uint16 PacketsThreshold);
369
370 /**
371 * @brief Setup the PCIE Event collector Error reporting registers
372 *
373 * @param psi0Config User Configuration
374 * @return Netc_Eth_Ip_StatusType Error in case the memory access wasn't enabled beforehand.
375 */
376 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetupErrorReporting(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config);
377
378 #if (NETC_ETH_IP_NUMBER_OF_VLAN_FILTER_ENTRIES > 0U)
379 /**
380 * @brief VLAN Filter table configuration function
381 *
382 * @param[in] Config: Pointer to the configuration for initalisation
383 *
384 * @return Result of the operation
385 * @retval 0 : E_OK, success
386 * @retval 1 : E_NOT_OK, fail
387 */
388 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigVLANFilterTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
389 #endif
390
391 /*!
392 * @brief : Function for initializing NTMP table.
393 * @details : Function enables the netc controller, initializes the tables and then diasbles the netc controller
394 *
395 * @param[in] ctrlIndex controller index
396 * @param[in] config controller configuration
397 *
398 */
399 static inline void Netc_Eth_Ip_InitNTMPTables(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
400
401 /*==================================================================================================
402 * LOCAL FUNCTIONS
403 ==================================================================================================*/
Netc_Eth_Ip_GetCurrentTick(uint8 ctrlIndex,Netc_Eth_Ip_TimeType * TimePtr)404 static void Netc_Eth_Ip_GetCurrentTick(uint8 ctrlIndex, Netc_Eth_Ip_TimeType *TimePtr)
405 {
406 /* Read the low register, then immediately read the high register to get a synchronised 64-bit time value */
407 (*TimePtr).nanosecondsL = (uint32)(netcSIsBase[ctrlIndex]->SICTR0);
408 (*TimePtr).nanosecondsH = (uint32)(netcSIsBase[ctrlIndex]->SICTR1);
409 }
410
Netc_Eth_Ip_StartTimeOut(uint32 * StartTimeOut,uint32 * ElapsedTimeOut,uint32 * TimeoutTicksOut,uint32 TimeoutUs)411 static inline void Netc_Eth_Ip_StartTimeOut(uint32 *StartTimeOut,
412 uint32 *ElapsedTimeOut,
413 uint32 *TimeoutTicksOut,
414 uint32 TimeoutUs)
415 {
416 *StartTimeOut = OsIf_GetCounter(NETC_ETH_IP_TIMEOUT_TYPE);
417 *ElapsedTimeOut = 0U;
418 *TimeoutTicksOut = OsIf_MicrosToTicks(TimeoutUs, NETC_ETH_IP_TIMEOUT_TYPE);
419 }
420
Netc_Eth_Ip_TimeoutExpired(uint32 * StartTimeInOut,uint32 * ElapsedTimeInOut,uint32 TimeoutTicks)421 static inline boolean Netc_Eth_Ip_TimeoutExpired(uint32 *StartTimeInOut,
422 uint32 *ElapsedTimeInOut,
423 uint32 TimeoutTicks)
424 {
425 *ElapsedTimeInOut += OsIf_GetElapsed(StartTimeInOut, NETC_ETH_IP_TIMEOUT_TYPE);
426
427 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE);
428 }
429
Netc_Eth_Ip_InitStateStructure(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)430 static void Netc_Eth_Ip_InitStateStructure(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
431 {
432 uint8 u8RxBDIdx;
433 uint8 u8TxBDIdx;
434 uint32 currBDIdx;
435
436 for (u8RxBDIdx = 0U; u8RxBDIdx < (*config->siConfig).NumberOfRxBDR; u8RxBDIdx++)
437 {
438 config->stateStructure->RxCurrentDesc[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
439 config->stateStructure->FirstRxRingDescAddr[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
440 config->stateStructure->RxRingSize[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].ringSize;
441 config->stateStructure->rxCurrentIndex[u8RxBDIdx] = 0U;
442 config->stateStructure->FirstRxDataBufferAddr[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].Buffer;
443 config->stateStructure->RxDataBuffMaxLenAddr[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].maxBuffLen;
444 config->stateStructure->RxCallback[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].Callback;
445 /* If at least one controller has the Rx Interrupt coalesing enabled, then set the right threshold for all
446 (0 if it is disabled, the configurated value if it is enabled).*/
447 config->stateStructure->RxTimerThreshold[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].TimerThreshold;
448 config->stateStructure->RxPacketsThreshold[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].PacketsThreshold;
449 }
450
451 for (u8TxBDIdx = 0U; u8TxBDIdx < (*config->siConfig).NumberOfTxBDR; u8TxBDIdx++)
452 {
453 config->stateStructure->LogicTxProducerIndex[u8TxBDIdx] = 0U;
454 config->stateStructure->lastTxDataBuffAddrIdx[u8TxBDIdx] = 0U;
455 config->stateStructure->FirstTxRingDescAddr[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].RingDesc;
456 config->stateStructure->TxRingSize[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].ringSize;
457 config->stateStructure->TxBufferLength[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].bufferLen;
458 config->stateStructure->TxCallback[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].Callback;
459 config->stateStructure->FirstTxDataBufferAddr[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].Buffer;
460 config->stateStructure->TxDataBuffMaxLenAddr[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].maxBuffLen;
461 /* If at least one controller has the tx Interrupt coalesing enabled, then set the right threshold for all
462 (0 if it is disabled, the configurated value if it is enabled).*/
463 config->stateStructure->TxTimerThreshold[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].TimerThreshold;
464 config->stateStructure->TxPacketsThreshold[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].PacketsThreshold;
465
466 for (currBDIdx = 0; currBDIdx < (*config->paCtrlTxRingConfig)[u8TxBDIdx].ringSize; currBDIdx++)
467 {
468 config->stateStructure->LockTxBuffDescr[u8TxBDIdx][currBDIdx] = FALSE;
469 }
470 }
471 /* Keep the interrupt setting for using information later. Per driver implementation the interrupts are enabled at controller level
472 (either all rings or none have interrupts enabled)m we will check the first ring value configured. */
473 config->stateStructure->RxInterrupts = (*config->siConfig).RxInterrupts;
474 config->stateStructure->TxInterrupts = (*config->siConfig).TxInterrupts;
475 config->stateStructure->VSItoPSIMsgCommand = (*config->siConfig).VSItoPSIMsgCommand;
476 config->stateStructure->NumberOfTxBDR = (*config->siConfig).NumberOfTxBDR;
477 config->stateStructure->NumberOfRxBDR = (*config->siConfig).NumberOfRxBDR;
478 config->stateStructure->SiType = config->SiType;
479 config->stateStructure->MACFilterTableMaxNumOfEntries = (*config->siConfig).MACFilterTableMaxNumOfEntries;
480 config->stateStructure->CtrlLogicalIndex = (*config->siConfig).CtrlLogicalIndex;
481 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
482 config->stateStructure->RxDataBuffAddr = (*config).rxExternalBuffersAddr;
483 #endif
484
485 /*SI runtime permissions */
486 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
487 {
488 config->stateStructure->SIGeneralConfig = config->generalConfig->stationInterfaceGeneralConfig;
489 config->stateStructure->generalConfig = config->generalConfig;
490
491 config->stateStructure->PcieAerUncorrectableErrEnabled = (*config->generalConfig).enableUncorrectableErrors;
492 config->stateStructure->PcieAerCorrectableErrEnabled = (*config->generalConfig).enableCorrectableErrors;
493 config->stateStructure->PcieAerErrorReportingCallback = (*config->generalConfig).errorReportingCallback;
494 }
495 else
496 {
497 config->stateStructure->SIGeneralConfig = NULL_PTR;
498 config->stateStructure->generalConfig = NULL_PTR;
499
500 config->stateStructure->PcieAerUncorrectableErrEnabled = FALSE;
501 config->stateStructure->PcieAerCorrectableErrEnabled = FALSE;
502 config->stateStructure->PcieAerErrorReportingCallback = NULL_PTR;
503 }
504
505 config->stateStructure->EnetcCommandBDConfig.commandBDAddr = (*config->siConfig).commandBDConfig.commandBDAddr;
506 config->stateStructure->EnetcCommandBDConfig.lengthCBDR = (*config->siConfig).commandBDConfig.lengthCBDR;
507
508
509
510 Netc_Eth_Ip_apxState[ctrlIndex] = config->stateStructure;
511 }
512
Netc_Eth_Ip_InitTxBD(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)513 static void Netc_Eth_Ip_InitTxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
514 {
515 uint8 currentTxBDR;
516 uint32 currBDIdx;
517 Netc_Eth_Ip_TxBDRType *TempTxDescr;
518
519 /* Loop through all the transmission rings used by the current controller. */
520 for (currentTxBDR = 0U; currentTxBDR < (*config->siConfig).NumberOfTxBDR; currentTxBDR++)
521 {
522 /* Enable the queue and write the configured values for priority and weight */
523 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBMR = NETC_F3_SI0_TBMR_PRIO((*config->paCtrlTxRingConfig)[currentTxBDR].Priority) | \
524 NETC_F3_SI0_TBMR_WRR((*config->paCtrlTxRingConfig)[currentTxBDR].Weight) | \
525 NETC_F3_SI0_TBMR_EN_MASK;
526 /* Initialize the producer and the consumer indexe with 0 value. */
527 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBPIR = 0U;
528 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBCIR = 0U;
529 /* Write the length of the ring */
530 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBLENR = (*config->paCtrlTxRingConfig)[currentTxBDR].ringSize;
531 /* Store the address of the first buffer descriptor in the current ring. */
532 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBBAR0 = (uint32)(*config->paCtrlTxRingConfig)[currentTxBDR].RingDesc;
533
534 TempTxDescr = (*config->paCtrlTxRingConfig)[currentTxBDR].RingDesc;
535 /* Loop through all descriptors of the ring. */
536 for (currBDIdx = 0U; currBDIdx < (*config->paCtrlTxRingConfig)[currentTxBDR].ringSize; currBDIdx++)
537 {
538 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
539 #ifdef NETC_ETH_0_USED
540 if (((uint8)0U == ctrlIndex) && ((uint8)0U == currentTxBDR))
541 {
542 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][currBDIdx].TxTimestampFlag = FALSE;
543 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][currBDIdx].ManagementFrameFlag = FALSE;
544 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][currBDIdx].TxTimestampRcvFlag = FALSE;
545 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][currBDIdx].TxTimeStampID = (uint16)0xFFFFU;
546 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][currBDIdx].TxBuffId = (uint16)0xFFFFU;
547 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][currBDIdx].PortIndex = (uint8)0xFFU;
548 }
549 #endif
550 #endif
551 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS)
552 if (!Netc_Eth_Ip_ControllerHasExternalTxBufferManagement[ctrlIndex])
553 {
554 /* Write in the buffer descriptor the address of the allocated buffer */
555 TempTxDescr->dataBuffAddr = (uint32)((*config->paCtrlTxRingConfig)[currentTxBDR].Buffer) + \
556 (uint32)(currBDIdx * (*config->paCtrlTxRingConfig)[currentTxBDR].maxBuffLen);
557 }
558 #endif
559
560 /* Write in the buffer descriptor the address of the allocated buffer */
561 TempTxDescr->dataBuffAddr = (uint32)((*config->paCtrlTxRingConfig)[currentTxBDR].Buffer) + \
562 (uint32)(currBDIdx * (*config->paCtrlTxRingConfig)[currentTxBDR].maxBuffLen);
563
564 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
565 /* Write in the buffer descriptor the extended bit */
566 TempTxDescr->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK);
567 TempTxDescr->extendBuffConfig = (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));
568 #else
569 /* For the last descriptor write the final flag */
570 TempTxDescr->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK)));
571 #endif
572 TempTxDescr++;
573 }
574 }
575 }
576
Netc_Eth_Ip_InitRxBD(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)577 static void Netc_Eth_Ip_InitRxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
578 {
579 uint8 u8RxBDIdx;
580 uint32 DataBuffIndex;
581 Netc_Eth_Ip_RxBDRType *pTempDescr;
582
583 for (u8RxBDIdx = 0U; u8RxBDIdx < (*config->siConfig).NumberOfRxBDR; u8RxBDIdx++)
584 {
585 /* Enable the queue and enable the extended mode for it */
586 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBMR = NETC_F3_SI0_RBMR_EN_MASK;
587 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
588 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBMR |= NETC_F3_SI0_RBMR_BDS_MASK;
589 #endif
590 /* Write the producer and consumer indexes with 0 */
591 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBPIR = 0U;
592 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBCIR = 0U;
593 /* Write the length of the ring */
594 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBLENR = (*config->paCtrlRxRingConfig)[u8RxBDIdx].ringSize;
595 /* Write in the transmission BDR register the address to the receive buffer descriptor. */
596 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBBAR0 = (uint32)(*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
597 /* Maximum size of the receive packet. Drop all packets with a bigger size. */
598 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBBSR = (*config->paCtrlRxRingConfig)[u8RxBDIdx].bufferLen;
599
600 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
601 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
602 {
603 #endif
604 pTempDescr = (*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
605 /* Loop through all descriptors of the queue */
606 for (DataBuffIndex = 0U; DataBuffIndex < (*config->paCtrlRxRingConfig)[u8RxBDIdx].ringSize; DataBuffIndex++)
607 {
608 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
609 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].RingIdx = (uint8)0xFF;
610 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].ReceivedDataPtr = NULL_PTR;
611 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].TimestampID = (uint32)0U;
612 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].TimestampValueInvalidForSwt = (boolean)TRUE;
613 #endif
614 pTempDescr->configRxBD[0U] = (uint32)((*config->paCtrlRxRingConfig)[u8RxBDIdx].Buffer) + \
615 (uint32)(DataBuffIndex * (*config->paCtrlRxRingConfig)[u8RxBDIdx].maxBuffLen);
616 pTempDescr++;
617 }
618 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
619 }
620 #endif
621
622 }
623 }
624
Netc_Eth_Ip_InitCBDR(uint8 ctrlIndex)625 static void Netc_Eth_Ip_InitCBDR(uint8 ctrlIndex)
626 {
627
628 netcSIsBase[ctrlIndex]->SICBDRBAR0 = (uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr);
629 netcSIsBase[ctrlIndex]->SICBDRLENR = NETC_F3_SI0_SICBDRLENR_LENGTH(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.lengthCBDR);
630 netcSIsBase[ctrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(0U);
631 netcSIsBase[ctrlIndex]->SICBDRCIR = NETC_F3_SI0_SICBDRCIR_BDR_INDEX(0U);
632 netcSIsBase[ctrlIndex]->SICBDRMR = NETC_F3_SI0_SICBDRMR_EN(1U);
633 }
634
Netc_Eth_Ip_EnableIrq(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)635 void Netc_Eth_Ip_EnableIrq(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
636 {
637 uint8 rxBDRIndex;
638 uint8 txBDRIndex;
639 Netc_Eth_Ip_MSITable *msiTableConfig;
640 Netc_Eth_Ip_VfBaseType *VSIConfig;
641 uint32* msiBaseAddr[] = NETC_ETH_IP_MSI_BASE_PTRS;
642 NETC_F3_PCI_HDR_TYPE0_Type *PSIConfig = IP_NETC__NETC_F3_PCI_HDR_TYPE0;
643
644 msiTableConfig = (Netc_Eth_Ip_MSITable *)msiBaseAddr[ctrlIndex];
645
646 if (((*config->siConfig).RxInterrupts != 0U) || ((*config->siConfig).TxInterrupts != 0U))
647 {
648 /* Enable MSI-X for configured function(SI).This will let MSI-X to request service. */
649 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
650 {
651 PSIConfig->PCI_CFC_MSIX_MSG_CTL |= NETC_ETH_IP_MSI_MSG_CTL_ENABLE_MASK;
652 }
653 else
654 {
655 VSIConfig = netcVFBase[ctrlIndex];
656 VSIConfig->PCI_CFC_MSIX_MSG_CTL |= NETC_ETH_IP_MSI_MSG_CTL_ENABLE_MASK;
657 }
658
659 if ((*config->siConfig).TxInterrupts != 0U)
660 {
661 msiTableConfig->msiTable[NETC_ETH_IP_TX_MSI_TABLE_INDEX].msgAddr = (*config->siConfig).txMruMailboxAddr;
662 msiTableConfig->msiTable[NETC_ETH_IP_TX_MSI_TABLE_INDEX].controlVector = 0x0U;
663 msiTableConfig->msiTable[NETC_ETH_IP_TX_MSI_TABLE_INDEX].msgData = 0xFFFFFFFFU;
664
665 for (txBDRIndex = 0U; txBDRIndex < (*config->siConfig).NumberOfTxBDR; txBDRIndex++)
666 {
667 netcSIsBase[ctrlIndex]->SIMSITRVR[txBDRIndex] = NETC_ETH_IP_TX_MSI_TABLE_INDEX;
668 }
669 }
670
671 if ((*config->siConfig).RxInterrupts != 0U)
672 {
673 msiTableConfig->msiTable[NETC_ETH_IP_RX_MSI_TABLE_INDEX].msgAddr = (*config->siConfig).rxMruMailboxAddr;
674 msiTableConfig->msiTable[NETC_ETH_IP_RX_MSI_TABLE_INDEX].controlVector = 0x0U;
675 msiTableConfig->msiTable[NETC_ETH_IP_RX_MSI_TABLE_INDEX].msgData = 0xFFFFFFFFU;
676
677 for (rxBDRIndex = 0U; rxBDRIndex < (*config->siConfig).NumberOfRxBDR; rxBDRIndex++)
678 {
679 netcSIsBase[ctrlIndex]->BDR_NUM[rxBDRIndex].RBICR0 |= NETC_F3_SI0_RBICR0_ICPT(1U);
680 netcSIsBase[ctrlIndex]->BDR_NUM[rxBDRIndex].RBICR0 |= NETC_F3_SI0_RBICR0_ICEN_MASK;
681 netcSIsBase[ctrlIndex]->SIMSIRRVR[rxBDRIndex] = NETC_ETH_IP_RX_MSI_TABLE_INDEX;
682 }
683 }
684
685 if ((NETC_ETH_IP_PHYSICAL_SI == config->SiType) &&
686 ((*config->siConfig).siMsgMruMailboxAddr != NULL_PTR))
687 {
688 netcSIsBase[ctrlIndex]->INTERRUPT.PSI.PSIIER |= 0xFE00FEU;
689 }
690 }
691
692
693 if ((*config->siConfig).siMsgMruMailboxAddr != NULL_PTR)
694 {
695 msiTableConfig->msiTable[NETC_ETH_IP_SITOSI_MESSAGE_MSI_TABLE_INDEX].msgAddr = (*config->siConfig).siMsgMruMailboxAddr;
696 msiTableConfig->msiTable[NETC_ETH_IP_SITOSI_MESSAGE_MSI_TABLE_INDEX].controlVector = 0x0U;
697 msiTableConfig->msiTable[NETC_ETH_IP_SITOSI_MESSAGE_MSI_TABLE_INDEX].msgData = 0xFFFFFFFFU;
698
699 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
700 {
701 netcSIsBase[ctrlIndex]->INTERRUPT.PSI.PSIIER |= 0xFE00FEU;
702 }
703 }
704
705 }
706
Netc_Eth_Ip_ComputeMACHashValue(const uint8 * MacAddr)707 static inline uint8 Netc_Eth_Ip_ComputeMACHashValue(const uint8 *MacAddr)
708 {
709 uint8 HashValue = 0U;
710 uint8 h0;
711 uint8 h1;
712 uint8 h2;
713 uint8 h3;
714 uint8 h4;
715 uint8 h5;
716
717 h0 = ((NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
718 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
719 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
720 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
721 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
722 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
723 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
724 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[5U])));
725
726 h1 = ((NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
727 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
728 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
729 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
730 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
731 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
732 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
733 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[5U])));
734
735 h2 = ((NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
736 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
737 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
738 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
739 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
740 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
741 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
742 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[5U])));
743
744 h3 = ((NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
745 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
746 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
747 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
748 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
749 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
750 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
751 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[5U])));
752
753 h4 = ((NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
754 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
755 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
756 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
757 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
758 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
759 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[5U])) ^ \
760 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[5U])));
761
762 h5 = ((NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
763 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
764 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
765 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
766 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
767 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
768 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[5U])) ^ \
769 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[5U])));
770
771 HashValue = (h5 << (uint8)5U) | (h4 << (uint8)4U) | (h3 << (uint8)3U) | (h2 << (uint8)2U) | (h1 << (uint8)1U) | h0;
772
773 return HashValue;
774 }
775
Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(uint8 VsiId,const Netc_Eth_Ip_VsiToPsiMsgType * MsgCommandConfig,uint16 * PsiRspMessage)776 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(uint8 VsiId, const Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig, uint16 * PsiRspMessage )
777 {
778 uint32 StartTime;
779 uint32 ElapsedTime;
780 uint32 TimeoutTicks;
781 Netc_Eth_Ip_StatusType Status;
782 Netc_Eth_Ip_StatusType PSIResponseStatus;
783
784 /*Assure the data to be sent is synchronised*/
785 MCAL_DATA_SYNC_BARRIER();
786 /* Set message command address(aligned at 64) and the size of it(6 bits code). */
787 ((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGSNDAR0 = ((uint32)MsgCommandConfig | NETC_ETH_IP_VSITOPSI_MSG_SIZE);
788
789 /* Wait until the message sent is processed by PSI. */
790 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
791 do
792 {
793 /* Return the status of the message command. */
794 if (NETC_ETH_IP_VSI_MSG_PROGRESS_STATUS != \
795 (((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGSR & NETC_ETH_IP_VSI_MSG_PROGRESS_STATUS))
796 {
797
798 Status = (Netc_Eth_Ip_StatusType)((uint16)(((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGSR) & NETC_ETH_IP_VSI_MSG_STATUS);
799
800 /* If the message was successfully transmited, copy the index value, or the user defined Message Code, received from PSI */
801 if(NETC_ETH_IP_STATUS_SUCCESS == Status )
802 {
803 PSIResponseStatus = (Netc_Eth_Ip_StatusType) (((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGRR >> NETC_ETH_IP_PSI_MSG_POS );
804
805 if(NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL == PSIResponseStatus)
806 {
807 Status = NETC_ETH_IP_STATUS_SUCCESS;
808 }
809 else if(NETC_ETH_IP_PSITOVSI_SYNC_STATUS_TRUE == PSIResponseStatus)
810 {
811 /*load sync state into the output partameter*/
812 *PsiRspMessage = TRUE;
813 Status = NETC_ETH_IP_STATUS_SUCCESS;
814 }
815 else if(NETC_ETH_IP_PSITOVSI_SYNC_STATUS_FALSE == PSIResponseStatus)
816 {
817 *PsiRspMessage = FALSE;
818 Status = NETC_ETH_IP_STATUS_SUCCESS;
819 }
820 else /*PSI Status Return have only 4 value*/
821 {
822 Status = NETC_ETH_IP_STATUS_ERROR;
823 }
824 }
825
826 break;
827 }
828 else
829 {
830 Status = NETC_ETH_IP_STATUS_TIMEOUT;
831 }
832 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
833
834 return Status;
835 }
836
Netc_Eth_Ip_AddMACFilterEntry(uint8 CtrlIndex,uint8 HashValue,const uint8 * MacAddr)837 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddMACFilterEntry(uint8 CtrlIndex, uint8 HashValue, const uint8 *MacAddr)
838 {
839 uint8 CurrentEntry;
840 uint8 CurrentMACByte;
841 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_MAC_ADDR_TABLE_FULL;
842
843 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
844 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
845 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
846 #endif
847
848 for(CurrentEntry = 0U; CurrentEntry < Netc_Eth_Ip_apxState[CtrlIndex]->MACFilterTableMaxNumOfEntries; CurrentEntry++)
849 {
850 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00();
851 if(FALSE == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus)
852 {
853 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus = TRUE;
854 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00();
855
856 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].HashValue = HashValue;
857 for(CurrentMACByte = 0U; CurrentMACByte < NETC_ETH_IP_MAC_BYTES_SIZE;CurrentMACByte++)
858 {
859 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].MACAddr[CurrentMACByte] = MacAddr[CurrentMACByte];
860 }
861 Status = NETC_ETH_IP_STATUS_SUCCESS;
862 break;
863 }
864 else
865 {
866 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00();
867 }
868 }
869 return Status;
870 }
871
Netc_Eth_Ip_DeleteMACFilterEntry(const uint8 CtrlIndex,const uint8 HashValue,const uint8 * MacAddr)872 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteMACFilterEntry(const uint8 CtrlIndex, const uint8 HashValue, const uint8 *MacAddr)
873 {
874 uint8 MACBytesMached;
875 uint8 CurrentEntry;
876 Netc_Eth_Ip_StatusType Status;
877 boolean MatchedEntry = FALSE;
878 uint8 HashNumOfMatches = 0U;
879
880 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
881 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
882 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
883 #endif
884
885 for(CurrentEntry = 0U; CurrentEntry < Netc_Eth_Ip_apxState[CtrlIndex]->MACFilterTableMaxNumOfEntries; CurrentEntry++)
886 {
887 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
888 if ((TRUE == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus) && \
889 (HashValue == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].HashValue)
890 )
891 {
892 HashNumOfMatches++;
893
894 /* There will be one entry removed at a time. */
895 if(MatchedEntry == FALSE)
896 {
897 MACBytesMached = 0U;
898 while ( (MacAddr[MACBytesMached] == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].MACAddr[MACBytesMached]) && (MACBytesMached < NETC_ETH_IP_MAC_BYTES_SIZE) )
899 {
900 MACBytesMached++;
901 }
902
903 if(NETC_ETH_IP_MAC_BYTES_SIZE == MACBytesMached)
904 {
905 /* Provide data was matched. */
906 MatchedEntry = TRUE;
907 /* Mark entry as an empty slot. */
908 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus = FALSE;
909 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
910 }
911 else
912 {
913 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
914 }
915 }
916 else
917 {
918 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
919 }
920 }
921 else
922 {
923 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
924 }
925 }
926
927 if(MatchedEntry)
928 {
929 if(1U == HashNumOfMatches)
930 {
931 Status = NETC_ETH_IP_STATUS_DELETE_MAC_ADDR;
932 }
933 else
934 {
935 Status = NETC_ETH_IP_STATUS_SUCCESS;
936 }
937 }
938 else
939 {
940 Status = NETC_ETH_IP_STATUS_MAC_ADDR_NOT_FOUND;
941 }
942
943 return Status;
944 }
945
Netc_Eth_Ip_VsiToPsiMsg(uint8 VsiId,Netc_Eth_Ip_VsiToPsiMsgActionType MsgAction,const uint8 * MacAddr,uint16 * PsiRspMessage)946 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsiMsg(uint8 VsiId, \
947 Netc_Eth_Ip_VsiToPsiMsgActionType MsgAction, \
948 const uint8 *MacAddr, \
949 uint16 * PsiRspMessage)
950 {
951 Netc_Eth_Ip_StatusType Status;
952 Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig = Netc_Eth_Ip_apxState[VsiId]->VSItoPSIMsgCommand;
953
954 switch (MsgAction)
955 {
956 case NETC_ETH_IP_VSITOPSI_MAC_ADDR_SET:
957 {
958 /* Set class for command message. */
959 MsgCommandConfig->Class = (uint8)0U;
960 MsgCommandConfig->Command = (uint8)0U;
961 /* Set MAC address. */
962 MsgCommandConfig->Data[0U] = (uint8)0U;
963 MsgCommandConfig->Data[1U] = (uint8)0U;
964 MsgCommandConfig->Data[2U] = MacAddr[0U];
965 MsgCommandConfig->Data[3U] = MacAddr[1U];
966 MsgCommandConfig->Data[4U] = MacAddr[2U];
967 MsgCommandConfig->Data[5U] = MacAddr[3U];
968 MsgCommandConfig->Data[6U] = MacAddr[4U];
969 MsgCommandConfig->Data[7U] = MacAddr[5u];
970 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
971 break;
972 }
973 case NETC_ETH_IP_VSITOPSI_ADD_RX_MAC_ADDR_FILTER:
974 {
975 /* Set class for command message. */
976 MsgCommandConfig->Class = (uint8)1U;
977 MsgCommandConfig->Command = (uint8)0U;
978 /* Compute the hash value for the MAC address. */
979 MsgCommandConfig->Data[0U] = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
980 MsgCommandConfig->Data[1U] = (uint8)0U;
981 /* Exact match(EM) will be deactivated when hash table is used. */
982 MsgCommandConfig->Data[2U] = (uint8)0U;
983
984 Status = Netc_Eth_Ip_AddMACFilterEntry(VsiId, MsgCommandConfig->Data[0U], MacAddr);
985
986 if(NETC_ETH_IP_STATUS_SUCCESS == Status)
987 {
988 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
989 }
990 break;
991 }
992 case NETC_ETH_IP_VSITOPSI_DELETE_RX_MAC_ADDR_FILTER:
993 {
994 /* Compute the hash value for the MAC address. */
995 MsgCommandConfig->Data[0U] = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
996 Status = Netc_Eth_Ip_DeleteMACFilterEntry(VsiId, MsgCommandConfig->Data[0U], MacAddr);
997
998 if(NETC_ETH_IP_STATUS_DELETE_MAC_ADDR == Status)
999 {
1000 /* Set class for command message. */
1001 MsgCommandConfig->Class = (uint8)1U;
1002 MsgCommandConfig->Command = (uint8)1U;
1003 MsgCommandConfig->Data[1U] = (uint8)0U;
1004 /* Exact match(EM) will be deactivated when hash table is used. */
1005 MsgCommandConfig->Data[2U] = (uint8)0U;
1006 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1007 }
1008
1009 break;
1010 }
1011 case NETC_ETH_IP_VSITOPSI_ENABLE_MULTICAST:
1012 {
1013 /* Set class for command message. */
1014 MsgCommandConfig->Class = (uint8)0x10U;
1015 MsgCommandConfig->Command = (uint8)0x00U;
1016 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1017 break;
1018 }
1019 case NETC_ETH_IP_VSITOPSI_DISABLE_MULTICAST:
1020 {
1021 /* Set class for command message. */
1022 MsgCommandConfig->Class = (uint8)0x10U;
1023 MsgCommandConfig->Command = (uint8)0x10U;
1024 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1025 break;
1026 }
1027 case NETC_ETH_IP_VSITOPSI_CLOSE_FILTER:
1028 {
1029 /* Set class for command message. */
1030 MsgCommandConfig->Class = (uint8)0x10U;
1031 MsgCommandConfig->Command = (uint8)0x20U;
1032 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1033 break;
1034 }
1035 case NETC_ETH_IP_VSITOPSI_GET_SYNC_STATE:
1036 {
1037 /* Set class for command message. */
1038 MsgCommandConfig->Class = (uint8)0x20U;
1039 MsgCommandConfig->Command = (uint8)0x00U;
1040 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1041 break;
1042 }
1043 default:
1044 {
1045 Status = NETC_ETH_IP_STATUS_UNSUPPORTED;
1046 break;
1047 }
1048 }
1049
1050 return Status;
1051 }
1052
1053 /*FUNCTION**********************************************************************
1054 *
1055 * Function Name : Netc_Eth_Ip_CoalescingTxPacketsConversion
1056 * Description : Internal function for converting a number of packets to a hardware specific value using the formula:
1057 * PacketsThreshold - no of packets
1058 * TwoPow = hardware specific value which will be set in the ICTT part of the TBxICR0 register. It will be
1059 * the greatest value which satisfies the following formula.
1060 * PacketsThreshold >= 2 ^(TwoPow-1)
1061 *
1062 *END**************************************************************************/
Netc_Eth_Ip_CoalescingTxPacketsConversion(uint16 PacketsThreshold)1063 static uint8 Netc_Eth_Ip_CoalescingTxPacketsConversion (uint16 PacketsThreshold)
1064 {
1065 uint16 RegVal = 1U;
1066 uint8 TwoPow = 0;
1067
1068 for(TwoPow = 1U; TwoPow < 16U; TwoPow++)
1069 {
1070 RegVal *= 2U;
1071
1072 if (RegVal > PacketsThreshold)
1073 {
1074 break;
1075 }
1076 }
1077
1078 return TwoPow;
1079 }
1080
1081 /*FUNCTION**********************************************************************
1082 *
1083 * Function Name : Netc_Eth_Ip_SendCommand
1084 * Description : Internal function for adding an entry with different commands to command ring.
1085 *
1086 *END**************************************************************************/
Netc_Eth_Ip_SendCommand(const uint8 CtrlIndex,const NetcEth_Ip_ReqHeaderTableOperationDataType * OperationData)1087 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendCommand(const uint8 CtrlIndex, const NetcEth_Ip_ReqHeaderTableOperationDataType *OperationData)
1088 {
1089 uint32 producerIdx;
1090 uint32 consumerIdx;
1091 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1092 uint32 PreviousProducerIdx;
1093 uint32 statusField;
1094 uint32 rrBit;
1095 uint32 errorField;
1096 uint32 StartTime;
1097 uint32 ElapsedTime;
1098 uint32 TimeoutTicks;
1099 boolean TimeExpired;
1100
1101 /* read the producer and consumer index register */
1102 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
1103 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1104
1105 /* check if the ring is full */
1106 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
1107 {
1108 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
1109 }
1110 else
1111 {
1112 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16();
1113 /* +++ fill in the NTMP request message header +++ */
1114 /* set the table address */
1115 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_ADDR_L] = (uint32)(&Netc_Eth_Ip_EnetcTableDataBuffer);
1116
1117 /* set the length of request and response data buffer */
1118 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_LENGTHFIELD] = (NETC_ETH_IP_CMDBD_REQFMT_REQUEST_LENGTH(OperationData->ReqBuffLength) | NETC_ETH_IP_CMDBD_REQFMT_RESPONSE_LENGTH(OperationData->RspBuffLength));
1119
1120 /* set RR = 0, CCI = 0, protocol version = 2, table id, access method and cmd */
1121 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] = 0x0; /* clear this field first */
1122 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CMD(OperationData->Cmd);
1123 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_ACCESS_METHOD(OperationData->AccessMethod);
1124 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_TABLE_ID(OperationData->TableId);
1125 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_VERSION(OperationData->Version);
1126 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CCI(OperationData->CmdCompletionInt);
1127 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_RR(0U); /* RR bit has to be set to 0 */
1128
1129 /* set NTMP version to 2.0*/
1130 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_NPFFIELD] = NETC_ETH_IP_CMDBD_REQFMT_NPF_FIELD(NETC_ETH_IP_CMDBD_REQFMT_NTMP_PROTOCOL_VERSION);
1131 /* --- fill in the NTMP request message header --- */
1132 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16();
1133
1134 /* +++ write the produce index register and enable hardware to consume the command +++ */
1135 PreviousProducerIdx = producerIdx; /* save the produce index before incrementing it manually */
1136 if ((producerIdx + 0x1UL) == ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) /* adjust producer index */
1137 {
1138 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, then it would start from 0 again */
1139 }
1140 else
1141 {
1142 producerIdx += 0x1UL; /* increase the producer index manually */
1143 }
1144
1145 /* This is needed to make sure the descriptor gets updated with the latest values, before
1146 incrementing the producer index to start the actual operation */
1147 MCAL_DATA_SYNC_BARRIER();
1148
1149 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
1150 /* --- write the produce index register and enable hardware to consume the command --- */
1151
1152 /* +++ to make sure the hardware consumes and processes the command completely +++ */
1153 /* Setup timeout timer */
1154 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1155 do {
1156 statusField = Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[PreviousProducerIdx].MessageHeaderDataField[NETC_ETH_IP_RSPHEADER_STATUS_FIELD_INDEX]; /* get status field in the response data buffer */
1157 rrBit = ((statusField & (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_RR_MASK)) >> (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_RR_SHIFT)); /* get the value of RR bit in the response data buffer */
1158 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1159 } while ((rrBit != 0x1U) && (FALSE == TimeExpired)); /* wait the hardware consume the command and check RR bit to see if the processing is completed (rrBit = 1). */
1160 /* --- to make sure the hardware consumes and processes the command completely --- */
1161
1162 /* return the value of ERROR field in response data buffer indicating if there is an error for processing the command */
1163 errorField = ((statusField & (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_ERROR_MASK)) >> (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_ERROR_SHIFT));
1164 if (errorField != 0U)
1165 {
1166 status = (Netc_Eth_Ip_StatusType)errorField; /* ERROR field should be 0. */
1167 }
1168 }
1169 return status;
1170 }
1171
1172 /*FUNCTION**********************************************************************
1173 *
1174 * Function Name : Netc_Eth_Ip_SendNTMP1Command_ShortFormat
1175 * Description : Internal function for adding an entry with different commands to command ring (short format) for NTMP V1.0.
1176 *
1177 *END**************************************************************************/
Netc_Eth_Ip_SendNTMP1Command_ShortFormat(uint8 CtrlIndex,const NetcEth_Ip_SetMessageHeaderTableOperationDataType * OperationData)1178 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendNTMP1Command_ShortFormat(uint8 CtrlIndex, const NetcEth_Ip_SetMessageHeaderTableOperationDataType *OperationData)
1179 {
1180 uint32 producerIdx;
1181 uint32 consumerIdx;
1182 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1183 uint32 PreviousConsumerIdx;
1184 uint8 statusField;
1185 uint32 StartTime;
1186 uint32 ElapsedTime;
1187 uint32 TimeoutTicks;
1188 boolean TimeExpired;
1189
1190 /* read the producer and consumer index register */
1191 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
1192 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1193
1194 /* check if the ring is full */
1195 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
1196 {
1197 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
1198 }
1199 else
1200 {
1201 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17();
1202 /* Fill in the configured data */
1203 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L] = OperationData->Data0;
1204 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_H] = OperationData->Data1;
1205 if (OperationData->Command == 0U)
1206 {
1207 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_1] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_EN(0x1U);
1208 }
1209 else
1210 {
1211 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_1] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_EN(0x0U);
1212 }
1213 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_2] = 0x0UL;
1214 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_3] = 0x0UL;
1215 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_4] = (uint32)OperationData->SI_Bitmap;
1216 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_LENGTH_INDEX] = OperationData->Index;
1217
1218 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SF(0x1U);
1219 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CI(0x0U);
1220 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_STATUS(0x0U);
1221 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CLASS(OperationData->Class);
1222 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_COMMAND(OperationData->Command);
1223 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17();
1224
1225 /* +++ write the producer index register and enable hardware to consume the command +++ */
1226 PreviousConsumerIdx = consumerIdx;
1227 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == 0U) /* adjust producer index */
1228 {
1229 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, the producer index should start from 0 again */
1230 }
1231 else
1232 {
1233 producerIdx += 0x1UL; /* increase the producer index manually */
1234 }
1235
1236 /* This is needed to make sure the descriptor gets updated with the latest values, before
1237 incrementing the producer index to start the actual operation */
1238 MCAL_DATA_SYNC_BARRIER();
1239
1240 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
1241 /* --- write the producer index register and enable hardware to consume the command --- */
1242
1243 /* +++ to make sure the hardware consumes and processes the command completely +++ */
1244 /* Setup timeout timer */
1245 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1246 do {
1247 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1248 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1249 } while ((consumerIdx == PreviousConsumerIdx) && (FALSE == TimeExpired)); /* wait the hardware consume the command. */
1250 /* --- to make sure the hardware consumes and processes the command completely --- */
1251
1252 if (TRUE == TimeExpired)
1253 {
1254 status = NETC_ETH_IP_STATUS_ERROR;
1255 }
1256 else
1257 {
1258 statusField = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_GET_STATUS(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[consumerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD]); /* get status field in the response data buffer */
1259 if (statusField != 0U)
1260 {
1261 status = NETC_ETH_IP_STATUS_ERROR; /* STATUS field should be 0. */
1262 }
1263 }
1264 }
1265 return status;
1266 }
1267
1268 /*FUNCTION**********************************************************************
1269 *
1270 * Function Name : Netc_Eth_Ip_SetVLANFilterTableEntry
1271 * Description : Internal function for adding an entry to the VLAN Filter Table.
1272
1273 * implements Netc_Eth_Ip_AddVLANFilterTableEntry_Activity
1274 *END**************************************************************************/
Netc_Eth_Ip_AddVLANFilterTableEntry(const uint8 ctrlIndex,const Netc_Eth_Ip_VLANFilterTableEntryDataType * VLANTableEntry)1275 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddVLANFilterTableEntry( const uint8 ctrlIndex, const Netc_Eth_Ip_VLANFilterTableEntryDataType *VLANTableEntry)
1276 {
1277 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1278 NetcEth_Ip_SetMessageHeaderTableOperationDataType TableData = {0U};
1279
1280 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1281 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1282 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
1283 #endif
1284
1285 /* Fill in the configured data */
1286 TableData.Data0 = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SET_TPID(VLANTableEntry->TPID);
1287 TableData.Data0 |= (uint32)VLANTableEntry->VLANId;
1288 TableData.SI_Bitmap = VLANTableEntry->SIBitmap;
1289 TableData.Index = VLANTableEntry->VLANFilterTable_EID;
1290 /* Class 2 for VLAN Filter Table */
1291 TableData.Class = 2U;
1292 /* Command 0 for adding an entry to the VLAN Filter Table */
1293 TableData.Command = 0U;
1294 status = Netc_Eth_Ip_SendNTMP1Command_ShortFormat(ctrlIndex, &TableData);
1295 return status;
1296 }
1297
1298 /*FUNCTION**********************************************************************
1299 *
1300 * Function Name : Netc_Eth_Ip_QueryVLANFilterTableEntry
1301 * Description : Internal function for querying the VLAN Filter Table.
1302 *
1303 * implements Netc_Eth_Ip_QueryVLANFilterTableEntry_Activity
1304 *END**************************************************************************/
Netc_Eth_Ip_QueryVLANFilterTableEntry(const uint8 ctrlIndex,Netc_Eth_Ip_VLANFilterTableEntryDataType * VLANTableEntry)1305 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryVLANFilterTableEntry(const uint8 ctrlIndex, Netc_Eth_Ip_VLANFilterTableEntryDataType *VLANTableEntry)
1306 {
1307 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1308 NetcEth_Ip_SetMessageHeaderTableOperationDataType TableData = {0U};
1309 uint32 producerIdx;
1310 uint32 lengthOfCmDB;
1311
1312 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1313 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1314 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
1315 #endif
1316
1317 /* Fill in the table entry ID */
1318 TableData.Index = VLANTableEntry->VLANFilterTable_EID;
1319 /* Class 2 for VLAN Filter Table */
1320 TableData.Class = 2U;
1321 /* Command 1 for adding an entry to the VLAN Filter Table */
1322 TableData.Command = 1U;
1323 status = Netc_Eth_Ip_SendNTMP1Command_ShortFormat(ctrlIndex, &TableData);
1324 producerIdx = netcSIsBase[ctrlIndex]->SICBDRPIR;
1325
1326 /* the value stored in producer index register indicates the index of next entry */
1327 if (producerIdx > 0UL)
1328 {
1329 producerIdx -= 1UL;
1330 }
1331 else /* producerIdx increased from 15 to 0, will set it to 15, or length minus 1 */
1332 {
1333 lengthOfCmDB = ((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD);
1334 producerIdx = lengthOfCmDB - 0x1UL;
1335 }
1336
1337 if (status == NETC_ETH_IP_STATUS_SUCCESS)
1338 {
1339 VLANTableEntry->TPID = (Netc_Eth_Ip_VlanProtocolIdentifierType)NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_GET_TPID(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L]);
1340 VLANTableEntry->VLANId = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L] & 0x00000FFFU);
1341 VLANTableEntry->SIBitmap = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_4]);
1342 }
1343 return status;
1344 }
1345
1346 #if (NETC_ETH_IP_NUMBER_OF_VLAN_FILTER_ENTRIES > 0)
1347 /*FUNCTION**********************************************************************
1348 *
1349 * Function Name : Netc_Eth_Ip_ConfigVLANFilterTable
1350 * Description : Add the configured entries to the VLAN Filter Table.
1351 *
1352 *END**************************************************************************/
Netc_Eth_Ip_ConfigVLANFilterTable(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)1353 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigVLANFilterTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
1354 {
1355 uint8 VLANFilterTableIdx;
1356 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1357 Netc_Eth_Ip_VLANFilterTableEntryDataType VLANTableEntry = {0};
1358
1359 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1360 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1361 #endif
1362
1363 for (VLANFilterTableIdx = 0U; VLANFilterTableIdx < Config->generalConfig->NumberOfVLANFilterEntries; VLANFilterTableIdx++)
1364 {
1365 VLANTableEntry = (*(Config->generalConfig->VLANTableEntries))[VLANFilterTableIdx];
1366 status = Netc_Eth_Ip_AddVLANFilterTableEntry(ctrlIndex, &VLANTableEntry);
1367 }
1368
1369 return status;
1370 }
1371 #endif
1372
1373 /*FUNCTION**********************************************************************
1374 *
1375 * Function Name : Netc_Eth_Ip_SendNTMP1Command_ShortFormat
1376 * Description : Internal function for adding an entry with different commands to command ring (short format) for NTMP V1.0.
1377 *
1378 *END**************************************************************************/
Netc_Eth_Ip_SendNTMP1Command_LongFormat(uint8 CtrlIndex,const NetcEth_Ip_SetMessageHeaderTableOperationDataType * OperationData)1379 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendNTMP1Command_LongFormat(uint8 CtrlIndex, const NetcEth_Ip_SetMessageHeaderTableOperationDataType *OperationData)
1380 {
1381 uint32 producerIdx;
1382 uint32 consumerIdx;
1383 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1384 uint32 PreviousConsumerIdx;
1385 uint8 statusField;
1386 uint32 StartTime;
1387 uint32 ElapsedTime;
1388 uint32 TimeoutTicks;
1389 boolean TimeExpired;
1390
1391 /* read the producer and consumer index register */
1392 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
1393 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1394
1395 /* check if the ring is full */
1396 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
1397 {
1398 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
1399 }
1400 else
1401 {
1402 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18();
1403 /* Fill in the configured data */
1404 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L] = OperationData->Data0;
1405 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_H] = 0x0UL;
1406 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_1] = 0x0UL;
1407 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_2] = 0x0UL;
1408 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_3] = 0x0UL;
1409 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_4] = 0x0UL;
1410 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_LENGTH_INDEX] = OperationData->Index | ((uint32)(OperationData->Length) << 16U);
1411
1412 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SF(OperationData->Format);
1413 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CI(0x0U);
1414 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_STATUS(0x0U);
1415 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CLASS(OperationData->Class);
1416 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_COMMAND(OperationData->Command);
1417 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18();
1418
1419
1420 /* +++ write the producer index register and enable hardware to consume the command +++ */
1421 PreviousConsumerIdx = consumerIdx;
1422 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == 0U) /* adjust producer index */
1423 {
1424 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, the producer index should start from 0 again */
1425 }
1426 else
1427 {
1428 producerIdx += 0x1UL; /* increase the producer index manually */
1429 }
1430
1431 /* This is needed to make sure the descriptor gets updated with the latest values, before
1432 incrementing the producer index to start the actual operation */
1433 MCAL_DATA_SYNC_BARRIER();
1434
1435 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
1436 /* --- write the produce index register and enable hardware to consume the command --- */
1437
1438 /* +++ to make sure the hardware consumes and processes the command completely +++ */
1439 /* Setup timeout timer */
1440 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1441 do {
1442 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1443 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1444 } while ((consumerIdx == PreviousConsumerIdx) && (FALSE == TimeExpired)); /* wait the hardware consume the command. */
1445 /* --- to make sure the hardware consumes and processes the command completely --- */
1446
1447 if (TRUE == TimeExpired)
1448 {
1449 status = NETC_ETH_IP_STATUS_TIMEOUT;
1450 }
1451 else
1452 {
1453 statusField = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_GET_STATUS(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[consumerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD]); /* get status field in the response data buffer */
1454 if (statusField != 0U)
1455 {
1456 status = NETC_ETH_IP_STATUS_ERROR; /* STATUS field should be 0. */
1457 }
1458 }
1459 }
1460 return status;
1461 }
1462
1463 /*FUNCTION**********************************************************************
1464 *
1465 * Function Name : Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat
1466 * Description : Internal function for querying statistics of a RFS entry with t commands to command ring (short format) for NTMP V1.0.
1467 *
1468 *END**************************************************************************/
Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat(const uint8 CtrlIndex,const NetcEth_Ip_SetMessageHeaderTableOperationDataType * OperationData)1469 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat(const uint8 CtrlIndex, const NetcEth_Ip_SetMessageHeaderTableOperationDataType *OperationData)
1470 {
1471 uint32 producerIdx;
1472 uint32 consumerIdx;
1473 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1474 uint32 PreviousConsumerIdx;
1475 uint8 statusField;
1476 uint32 StartTime;
1477 uint32 ElapsedTime;
1478 uint32 TimeoutTicks;
1479 boolean TimeExpired;
1480
1481 /* read the producer and consumer index register */
1482 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
1483 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1484
1485 /* check if the ring is full */
1486 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
1487 {
1488 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
1489 }
1490 else
1491 {
1492 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19();
1493 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_LENGTH_INDEX] = OperationData->Index | (((uint32)(OperationData->Length)) << 16U);
1494 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SF(OperationData->Format);
1495 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CI(0x0U);
1496 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_STATUS(0x0U);
1497 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CLASS(OperationData->Class);
1498 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_COMMAND(OperationData->Command);
1499 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19();
1500
1501
1502 /* +++ write the producer index register and enable hardware to consume the command +++ */
1503 PreviousConsumerIdx = consumerIdx;
1504 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == 0U) /* adjust producer index */
1505 {
1506 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, the producer index should start from 0 again */
1507 }
1508 else
1509 {
1510 producerIdx += 0x1UL; /* increase the producer index manually */
1511 }
1512
1513 /* This is needed to make sure the descriptor gets updated with the latest values, before
1514 incrementing the producer index to start the actual operation */
1515 MCAL_DATA_SYNC_BARRIER();
1516
1517 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
1518 /* --- write the produce index register and enable hardware to consume the command --- */
1519
1520 /* +++ to make sure the hardware consumes and processes the command completely +++ */
1521 /* Setup timeout timer */
1522 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1523 do {
1524 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1525 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1526 } while ((consumerIdx == PreviousConsumerIdx) && (FALSE == TimeExpired)); /* wait the hardware consume the command. */
1527 /* --- to make sure the hardware consumes and processes the command completely --- */
1528
1529 if (TRUE == TimeExpired)
1530 {
1531 status = NETC_ETH_IP_STATUS_TIMEOUT;
1532 }
1533 else
1534 {
1535 statusField = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_GET_STATUS(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[consumerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD]); /* get status field in the response data buffer */
1536 if (statusField != 0U)
1537 {
1538 status = NETC_ETH_IP_STATUS_ERROR; /* STATUS field should be 0. */
1539 }
1540 }
1541 }
1542 return status;
1543 }
1544
1545 /*FUNCTION**********************************************************************
1546 *
1547 * Function Name : Netc_Eth_Ip_FillRfsSetDataBuffer
1548 * Description : Internal function for filling a local static buffer with the configured data for a Rfs table entry
1549 *
1550 *END**************************************************************************/
Netc_Eth_Ip_FillRfsSetDataBuffer(uint32 * RfsSetDataBuffer,const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)1551 static void Netc_Eth_Ip_FillRfsSetDataBuffer(uint32 * RfsSetDataBuffer, const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)
1552 {
1553 uint8 i;
1554
1555 for(i = 0; i < NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE; i++)
1556 {
1557 RfsSetDataBuffer[i] = 0;
1558 }
1559
1560 /*EN, MODE, RESULT fields */
1561 RfsSetDataBuffer[28] = (uint32)(RfsTableEntry->Result) | ((uint32)(RfsTableEntry->Mode) << NETC_ETH_IP_RFS_ENTRY_MODE_FIELD_SHIFT) | ((uint32)(RfsTableEntry->Enable) << NETC_ETH_IP_RFS_ENTRY_EN_FIELD_SHIFT);
1562
1563 /*L4_PROTOCOL, L4_PROTOCOL_MASK, IP_PRESENT, IP_PRESENT_M, L4_PROT_PRESENT, L4_PROT_PRESENT_M,
1564 TCP_OR_UDP_PRESENT, TCP_OR_UDP_PRESENT_M, IPV4_IPV6, IPV4_IPV6_M, UDP_TCP, UDP_TCP_M fields */
1565 RfsSetDataBuffer[27] = (uint32)(RfsTableEntry->L4Protocol) | ((uint32)(RfsTableEntry->L4ProtocolMask) << NETC_ETH_IP_RFS_ENTRY_L4PROTMASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->IpPresent) << NETC_ETH_IP_RFS_ENTRY_IPPRESENT_FIELD_SHIFT)
1566 | ((uint32)(RfsTableEntry->IpPresentMask) << NETC_ETH_IP_RFS_ENTRY_IPPRESENTMASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->L4ProtPresent) << NETC_ETH_IP_RFS_ENTRY_L4PROTPRESENT_FIELD_SHIFT) | ((uint32)(RfsTableEntry->L4ProtPresentMask) << NETC_ETH_IP_RFS_ENTRY_L4PROTPRESENTMASK_FIELD_SHIFT)
1567 | ((uint32)(RfsTableEntry->TcpUdpPresent) << NETC_ETH_IP_RFS_ENTRY_TCPUDPPRESENT_FIELD_SHIFT) | ((uint32)(RfsTableEntry->TcpUdpPresentMask) << NETC_ETH_IP_RFS_ENTRY_TCPUDPPRESENTMASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->Ipv4Ipv6) << NETC_ETH_IP_RFS_ENTRY_IPV4IPV6_FIELD_SHIFT)
1568 | ((uint32)(RfsTableEntry->Ipv4Ipv6Mask)<< NETC_ETH_IP_RFS_ENTRY_IPV4IPV6MASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->UdpTcp) << NETC_ETH_IP_RFS_ENTRY_UDPTCP_FIELD_SHIFT) | ((uint32)(RfsTableEntry->UdpTcpMask) << NETC_ETH_IP_RFS_ENTRY_UDPTCPMASK_FIELD_SHIFT);
1569
1570 /* RFS Table bytes (Offset 0x68) corresponding to RfsSetDataBuffer position 26 are reserved */
1571
1572 /*L4_DEST_PORT, L4_DEST_PORT_MASK fields */
1573 RfsSetDataBuffer[25] = (uint32) (RfsTableEntry->L4DestPort) | (uint32)(RfsTableEntry->L4DestPortMask << NETC_ETH_IP_RFS_ENTRY_L4DESTPORTMASK_FIELD_SHIFT);
1574
1575 /*L4_SOURCE_PORT, L4_SOURCE_PORT_MASK fields */
1576 RfsSetDataBuffer[24] = (uint32) (RfsTableEntry->L4SrcPort) | (uint32)(RfsTableEntry->L4SrcPortMask << NETC_ETH_IP_RFS_ENTRY_L4SRCPORTMASK_FIELD_SHIFT);
1577
1578 /* RFS Table bytes (Offset 0x5C and 0x58) corresponding to RfsSetDataBuffer positions 23 and 22 are reserved */
1579
1580 /*DEST_IP_ADDR_MASK field*/
1581 RfsSetDataBuffer[21] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrMaskHigh);
1582 RfsSetDataBuffer[20] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrMaskHigh);
1583 RfsSetDataBuffer[19] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrMaskLow);
1584 RfsSetDataBuffer[18] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrMaskLow);
1585
1586 /*DEST_IP_ADDR field*/
1587 RfsSetDataBuffer[17] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrHigh);
1588 RfsSetDataBuffer[16] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrHigh);
1589 RfsSetDataBuffer[15] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrLow);
1590 RfsSetDataBuffer[14] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrLow);
1591
1592 /*SRC_IP_ADDR_MASK field*/
1593 RfsSetDataBuffer[13] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrMaskHigh);
1594 RfsSetDataBuffer[12] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrMaskHigh);
1595 RfsSetDataBuffer[11] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrMaskLow);
1596 RfsSetDataBuffer[10] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrMaskLow);
1597
1598 /*SRC_IP_ADDR field*/
1599 RfsSetDataBuffer[9] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrHigh);
1600 RfsSetDataBuffer[8] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrHigh);
1601 RfsSetDataBuffer[7] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrLow);
1602 RfsSetDataBuffer[6] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrLow);
1603
1604 /* RFS Table bytes (Offset 0x00 to 0x14) corresponding to RfsSetDataBuffer positions 0 to 15 are reserved */
1605 }
1606
1607 /*FUNCTION**********************************************************************
1608 *
1609 * Function Name : Netc_Eth_Ip_SetRfsTableEntry
1610 * Description : Internal function for adding an entry to the Rceive Flow Steering Table.
1611 *
1612 * implements Netc_Eth_Ip_AddRfsTableEntry_Activity
1613 *END**************************************************************************/
Netc_Eth_Ip_AddRfsTableEntry(const uint8 ctrlIndex,const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)1614 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddRfsTableEntry(const uint8 ctrlIndex, const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)
1615 {
1616 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1617 NetcEth_Ip_SetMessageHeaderTableOperationDataType TableData = {0U};
1618 static uint32 RfsSetDataBuffer[NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE];
1619
1620
1621 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1622 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1623 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
1624 #endif
1625
1626 /* Fill in the configured data. */
1627 Netc_Eth_Ip_FillRfsSetDataBuffer(RfsSetDataBuffer, RfsTableEntry);
1628
1629 /* RFS Data buffer address.
1630 There is an alignment restrictions for the data address to be 16-byte aligned;
1631 hardware ignores the least significant 4 bits of the ADDR field. */
1632 TableData.Data0 = (uint32) &RfsSetDataBuffer;
1633 TableData.Length = (uint16)( NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE * 4U);
1634 TableData.Index = RfsTableEntry->RfsTableEntryId;
1635
1636 /*Set the format to Long format */
1637 TableData.Format = 0;
1638 /* Class 4 for RFS Table */
1639 TableData.Class = 4U;
1640 /* Command 0 for adding an entry to the RFS Table */
1641 TableData.Command = 0U;
1642 status = Netc_Eth_Ip_SendNTMP1Command_LongFormat(ctrlIndex, &TableData);
1643 return status;
1644 }
1645
1646 /*FUNCTION**********************************************************************
1647 *
1648 * Function Name : Netc_Eth_Ip_QueryRfsTableEntry
1649 * Description : Internal function for querying the Receive Flow Steering Table.
1650 *
1651 * implements Netc_Eth_Ip_QueryRfsTableEntry_Activity
1652 *END**************************************************************************/
Netc_Eth_Ip_QueryRfsTableEntry(const uint8 ctrlIndex,uint8 RfsEntryIdx,uint32 * RfsTableEntryAddr)1653 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryRfsTableEntry(const uint8 ctrlIndex, uint8 RfsEntryIdx, uint32 * RfsTableEntryAddr)
1654 {
1655 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1656 NetcEth_Ip_SetMessageHeaderTableOperationDataType TableData = {0U};
1657
1658 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1659 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1660 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
1661 #endif
1662
1663 /* Fill in the table entry ID */
1664 TableData.Index = RfsEntryIdx;
1665 /* Fill in the table entry address */
1666 TableData.Data0 = (uint32)RfsTableEntryAddr;
1667 /* Fill in the table entry length */
1668 TableData.Length = (uint16)( NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE * 4U);
1669 /* Class 4 for RFS Table */
1670 TableData.Class = 4U;
1671 /* Command 1 for adding an querrying to the RFS Table (Long format) */
1672 TableData.Command = 1U;
1673 /*Long format*/
1674 TableData.Format = 0U;
1675
1676 status = Netc_Eth_Ip_SendNTMP1Command_LongFormat(ctrlIndex, &TableData);
1677
1678 return status;
1679 }
1680
1681 /*FUNCTION**********************************************************************
1682 *
1683 * Function Name : Netc_Eth_Ip_QueryStatisticsRfsTableEntry
1684 * Description : Internal function for querying the Receive Flow Steering Table.
1685 *
1686 * implements Netc_Eth_Ip_QueryStatisticsRfsTableEntry_Activity
1687 *END**************************************************************************/
Netc_Eth_Ip_QueryStatisticsRfsTableEntry(const uint8 ctrlIndex,uint8 RfsEntryIdx,uint32 * MatchedFramesNb)1688 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryStatisticsRfsTableEntry(const uint8 ctrlIndex, uint8 RfsEntryIdx, uint32 * MatchedFramesNb)
1689 {
1690 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1691 NetcEth_Ip_SetMessageHeaderTableOperationDataType TableData = {0U};
1692 uint32 producerIdx;
1693 uint32 lengthOfCmDB;
1694
1695 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1696 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1697 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
1698 #endif
1699
1700 /* Fill in the table entry ID */
1701 TableData.Index = RfsEntryIdx;
1702 /* Class 4 for RFS Table */
1703 TableData.Class = 4U;
1704 /* Command 1 for adding an querrying statistical information for RFS Table Entry (Short Format) */
1705 TableData.Command = 2U;
1706 /*Short Format*/
1707 TableData.Format = 1U;
1708
1709 /*To check what format should be sent here*/
1710 status = Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat(ctrlIndex, &TableData);
1711
1712 producerIdx = netcSIsBase[ctrlIndex]->SICBDRPIR;
1713
1714 /* the value stored in producer index register indicates the index of next entry */
1715 if (producerIdx > 0UL)
1716 {
1717 producerIdx -= 1UL;
1718 }
1719 else /* producerIdx increased from 15 to 0, will set it to 15, or length minus 1 */
1720 {
1721 lengthOfCmDB = ((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD);
1722 producerIdx = lengthOfCmDB - 0x1UL;
1723 }
1724
1725 if (status == NETC_ETH_IP_STATUS_SUCCESS)
1726 {
1727 /*Get the number of matched frames */
1728 *MatchedFramesNb = Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L];
1729 }
1730 return status;
1731 }
1732
1733 /*FUNCTION**********************************************************************
1734 *
1735 * Function Name : Netc_Eth_Ip_ConfigRfsTable
1736 * Description : Add the configured entries to the Receive Flow Steering Table.
1737 *
1738 *END**************************************************************************/
Netc_Eth_Ip_ConfigRfsTable(const uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)1739 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigRfsTable(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
1740 {
1741 uint32 RfsTableIdx;
1742 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1743 Netc_Eth_Ip_RfsEntryType RfsTableEntry = {0};
1744
1745 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1746 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1747 #endif
1748
1749 /*Add configured entries into the RFS table*/
1750 for (RfsTableIdx = 0U; RfsTableIdx < Config->RfsEntriesNb; RfsTableIdx++)
1751 {
1752 RfsTableEntry = (*(Config->RfsConfigTable))[RfsTableIdx];
1753 status = Netc_Eth_Ip_AddRfsTableEntry(ctrlIndex, &RfsTableEntry);
1754 }
1755
1756 /* Enable Port Receive Flow Steering Mode */
1757 IP_NETC__ENETC0_BASE->PRFSMR = NETC_F3_PRFSMR_RFSE(1);
1758
1759 return status;
1760 }
1761
1762 /*FUNCTION**********************************************************************
1763 *
1764 * Function Name : Netc_Eth_Ip_ConfigPortTimeGateScheduling
1765 * Description : Ethernet ENETC enables or disables Time Gate Scheduling function.
1766 *
1767 * implements Netc_Eth_Ip_ConfigPortTimeGateScheduling_Activity
1768 *END**************************************************************************/
Netc_Eth_Ip_ConfigPortTimeGateScheduling(const uint8 CtrlIndex,const boolean Enable)1769 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigPortTimeGateScheduling( const uint8 CtrlIndex, const boolean Enable )
1770 {
1771 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1772 uint32 RegValue;
1773 uint32 GateControlListState;
1774 uint32 StartTime;
1775 uint32 ElapsedTime;
1776 uint32 TimeoutTicks;
1777 boolean TimeExpired;
1778
1779 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1780 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1781 #endif
1782
1783 (void)CtrlIndex;
1784 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13();
1785 /* read the reg value first */
1786 RegValue = IP_NETC__ENETC0_PORT->PTGSCR;
1787 if ((RegValue & ENETC_PORT_PTGSCR_TGE_MASK) != ENETC_PORT_PTGSCR_TGE_MASK) /* time gating is disabled */
1788 {
1789 if (TRUE == Enable)
1790 {
1791 /* Software must also wait until PTGAGLSR[TG] is deasserted before re-enabling. */
1792 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1793 do {
1794 /* get the state of gate control list */
1795 GateControlListState = (IP_NETC__ENETC0_PORT->PTGAGLSR & ENETC_PORT_PTGAGLSR_TG_MASK);
1796 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1797 } while ((GateControlListState != 0x0U) && (FALSE == TimeExpired));
1798
1799 if (GateControlListState == 0x0U)
1800 {
1801 RegValue |= ENETC_PORT_PTGSCR_TGE(1U); /* Enable time gating */
1802 }
1803 else
1804 {
1805 status = NETC_ETH_IP_STATUS_ERROR; /* fail to enable time gating because Operational gate control list is active */
1806 }
1807 }
1808 }
1809 else /* time gating is enabled */
1810 {
1811 if (FALSE == Enable)
1812 {
1813 RegValue &= ~ENETC_PORT_PTGSCR_TGE(1U); /* Disable time gating */
1814 }
1815 }
1816
1817 if (status == NETC_ETH_IP_STATUS_SUCCESS)
1818 {
1819 /* write it back. */
1820 IP_NETC__ENETC0_PORT->PTGSCR = RegValue;
1821 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13();
1822
1823 /* if time gate scheduling is enabled, and entry data is configured, then adds the entry */
1824 if ( (TRUE == Enable) && (TRUE == Netc_Eth_Ip_PortTimeAwareShaperEnabled))
1825 {
1826 status = Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry(0U, &Netc_Eth_Ip_EthTimeGateSchedulingEntryData);
1827 /* fail to add or update the time gate schedulling table entry */
1828 if (status != NETC_ETH_IP_STATUS_SUCCESS)
1829 {
1830 status = NETC_ETH_IP_STATUS_ERROR;
1831 }
1832 }
1833 }
1834 else
1835 {
1836 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13();
1837 }
1838
1839 return status;
1840 }
1841
FillInGateControlListData(const uint8 * OperationTimeIdx,const Netc_Eth_Ip_TimeGateSchedulingEntryDataType * TimeGateSchedulingTableEntry)1842 static inline void FillInGateControlListData(const uint8 *OperationTimeIdx, const Netc_Eth_Ip_TimeGateSchedulingEntryDataType *TimeGateSchedulingTableEntry)
1843 {
1844 uint8 CFGEDataIdx;
1845 uint16 GateEntryIdx;
1846 uint8 HostRequest;
1847
1848 if (*OperationTimeIdx == 1U)
1849 {
1850 CFGEDataIdx = 0U;
1851
1852 for (GateEntryIdx = 0U; GateEntryIdx < TimeGateSchedulingTableEntry->AdminControlListLength; GateEntryIdx++)
1853 {
1854 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)(NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA5) + CFGEDataIdx] = TimeGateSchedulingTableEntry->GateEntryAdminControlListData[GateEntryIdx].AdminTimeInterval;
1855 /* convert gate operation type */
1856 switch (TimeGateSchedulingTableEntry->GateEntryAdminControlListData[GateEntryIdx].AdminGateOperationType)
1857 {
1858 case NETC_ETH_HOST_REQUEST_UNCHANGED:
1859 HostRequest = 0U;
1860 break;
1861 case NETC_ETH_HOST_REQUEST_HOLD:
1862 HostRequest = 1U;
1863 break;
1864 case NETC_ETH_HOST_REQUEST_RELEASE:
1865 HostRequest = 2U;
1866 break;
1867 default:
1868 HostRequest = 0U;
1869 break;
1870 }
1871 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)(NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA6) + CFGEDataIdx] = NETC_ETH_IP_TGSTABLE_CFGE_ADMIN_TC_STATES(TimeGateSchedulingTableEntry->GateEntryAdminControlListData[GateEntryIdx].AdminTrafficClassGateStates) \
1872 | NETC_ETH_IP_TGSTABLE_CFGE_ADMIN_HR_CB(HostRequest);
1873
1874 CFGEDataIdx += 2U; /* CFGE data field index increased by 2 */
1875 }
1876
1877 }
1878 }
1879
1880 /*FUNCTION**********************************************************************
1881 *
1882 * Function Name : Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry
1883 * Description : Ethernet ENETC adds or updates Time Gate Scheduling table entry function.
1884 *
1885 * implements Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry_Activity
1886 *END**************************************************************************/
Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry(const uint8 CtrlIndex,const Netc_Eth_Ip_TimeGateSchedulingEntryDataType * TimeGateSchedulingTableEntry)1887 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry( const uint8 CtrlIndex,
1888 const Netc_Eth_Ip_TimeGateSchedulingEntryDataType *TimeGateSchedulingTableEntry
1889 )
1890 {
1891 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1892 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData;
1893 uint8 OperationTimes;
1894 uint8 OperationTimeIdx;
1895 volatile uint64 CurrentTime = 0;
1896 uint32 CycleFactor;
1897 uint64 NewBaseTime;
1898 uint32 LookaheadTime;
1899
1900 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1901 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1902 DevAssert(TimeGateSchedulingTableEntry != NULL_PTR);
1903 #endif
1904
1905 /* AdminControlListLength = 0U means to reset the gate control list or add the time gate scheduling entry without gate control list */
1906 OperationTimes = (TimeGateSchedulingTableEntry->AdminControlListLength > 0U) ? 2U : 1U;
1907
1908 /* for adding or updating gate control list, we'll have to remove the gate control list firstly */
1909 for (OperationTimeIdx = 0U; OperationTimeIdx < OperationTimes; OperationTimeIdx++)
1910 {
1911 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14();
1912 /* ++++++ initialize the table request data buffer ++++++ */
1913 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(1U); /* fill in Actions field */
1914 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = TimeGateSchedulingTableEntry->TimeGateSchedulingTable_EID; /* fill in Entry ID */
1915 /* fill in CFGE_DATA */
1916 /* get the current time from 1588 timer */
1917 CurrentTime = IP_NETC__TMR0_BASE->TMR_CUR_TIME_L; /* should read the Lower register first */
1918 CurrentTime |= ((uint64)(IP_NETC__TMR0_BASE->TMR_CUR_TIME_H)) << NETC_ETH_IP_32BIT_SHIFT;
1919 /* get lookaheadtime */
1920 LookaheadTime = IP_NETC__NETC_IERB->CFG_ENETC_INST[0U].ETGSLR + IP_NETC__ENETC0_PORT->PTGSATOR;
1921
1922 /* calculate the NewBaseTime */
1923 if (TimeGateSchedulingTableEntry->AdminBaseTime >= (CurrentTime + LookaheadTime))
1924 {
1925 NewBaseTime = TimeGateSchedulingTableEntry->AdminBaseTime;
1926 }
1927 else
1928 {
1929 CycleFactor = (uint32)(CurrentTime + LookaheadTime - TimeGateSchedulingTableEntry->AdminBaseTime) / (TimeGateSchedulingTableEntry->AdminCycleTime);
1930 NewBaseTime = TimeGateSchedulingTableEntry->AdminBaseTime + (((uint64)CycleFactor + 1UL) * (uint64)(TimeGateSchedulingTableEntry->AdminCycleTime));
1931 }
1932 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = (uint32)(NewBaseTime & (0xFFFFFFFFUL));
1933 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = (uint32)(NewBaseTime >> NETC_ETH_IP_32BIT_SHIFT);
1934 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2] = TimeGateSchedulingTableEntry->AdminCycleTime;
1935 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3] = TimeGateSchedulingTableEntry->AdminCycleTimeExt;
1936 /* set Administrative Control List Length to 0 for removing the admin gate control list or adding an entry with no administrative gate control list */
1937 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = (OperationTimeIdx == 0U) ? 0x0UL : (uint32)(TimeGateSchedulingTableEntry->AdminControlListLength);
1938
1939 FillInGateControlListData(&OperationTimeIdx, TimeGateSchedulingTableEntry);
1940 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14();
1941
1942 /* ------ initialize the table request data buffer ------ */
1943
1944 /* fill in operation data for config field of Request Header*/
1945 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
1946 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
1947 OperationData.TableId = NETC_ETH_IP_TIME_GATE_SCHEDULING_TABLE_ID;
1948 OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* only support NETC_ETH_ENTRY_ID_MATCH method */
1949 OperationData.Cmd = NETC_ETH_UPDATE_CMD; /* can only use "update" command to add or update an time gate scheduling table entry */
1950 OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
1951 OperationData.RspBuffLength = (NETC_ETH_IP_TGSTABLE_RSPBUFFER_LEN);
1952
1953 /* send "update" command to add/remove gate control list */
1954 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
1955 #if defined(ERR_IPV_NETC_051243)
1956 #if (STD_ON == ERR_IPV_NETC_051243)
1957 /* Error code 0x8A is not a real error. check it on Errata. */
1958 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
1959 {
1960 status = NETC_ETH_IP_STATUS_SUCCESS;
1961 }
1962 #endif
1963 #endif
1964 }
1965
1966 return status;
1967 }
1968
1969 /* inline function for initializing time gate scheduling table entries data during ENETC init */
Netc_Eth_Ip_InitTimeGateSchedulingTableEntryData(const Netc_Eth_Ip_ConfigType * Config)1970 static inline void Netc_Eth_Ip_InitTimeGateSchedulingTableEntryData(const Netc_Eth_Ip_ConfigType * Config)
1971 {
1972 uint8 GateControlListIdx;
1973
1974 if (((*Config->generalConfig).portTimeAwareShaperEnable) == TRUE)
1975 {
1976 /* set the flag for ports */
1977 Netc_Eth_Ip_PortTimeAwareShaperEnabled = TRUE;
1978
1979 /* write register PTGSATOR. */
1980 IP_NETC__ENETC0_PORT->PTGSATOR = (uint32)((*Config->generalConfig).portTimeGateSchedulingAdvanceTimeOffsetReg);
1981
1982 /* Fill in the data structure for time gate scheduling */
1983 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.TimeGateSchedulingTable_EID = 0U;
1984 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminBaseTime = (*Config->generalConfig).portEgressAdminBaseTime;
1985 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTime = (*Config->generalConfig).portEgressAdminCycleTime;
1986 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTimeExt = (*Config->generalConfig).portEgressAdminCycleTimeExt;
1987 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength = (*Config->generalConfig).numberOfGateControlListEntries;
1988 for (GateControlListIdx = 0U; GateControlListIdx < Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength; GateControlListIdx++)
1989 {
1990 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[GateControlListIdx].AdminTimeInterval = (*(*Config->generalConfig).TimeGateControlListEntries)[GateControlListIdx].AdminTimeInterval;
1991 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[GateControlListIdx].AdminTrafficClassGateStates = (*(*Config->generalConfig).TimeGateControlListEntries)[GateControlListIdx].AdminTrafficClassGateStates;
1992 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[GateControlListIdx].AdminGateOperationType = (*(*Config->generalConfig).TimeGateControlListEntries)[GateControlListIdx].AdminGateOperationType;
1993 }
1994 }
1995
1996 }
1997
1998 #if defined(ERR_IPV_NETC_E051130)
1999 #if (STD_ON == ERR_IPV_NETC_E051130)
2000 /* Workaround for ERR051130:
2001 Egress time gate scheduling can get corrupted when functional level reset is applied or when time gating is disabled
2002 */
2003 /* Added 2 fake time gate control list entries for clearing the internal context for time gate scheduling feature */
Netc_Eth_Ip_InitTimeGateSchedulingFeature(uint8 ctrlIndex)2004 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_InitTimeGateSchedulingFeature(uint8 ctrlIndex)
2005 {
2006 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
2007 volatile uint64 CurrentTime = 0;
2008 uint8 EntryIdx;
2009
2010 /* fill in struct Netc_Eth_Ip_TimeGateSchedulingEntryDataType */
2011 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.TimeGateSchedulingTable_EID = 0U; /* for pseudo port of ENETC */
2012 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTime = 4000000U; /* it should be greater than the sum of time interval */
2013 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTimeExt = 100000U;
2014 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength = 2U; /* 2 entries */
2015
2016 /* get the current time from 1588 timer */
2017 CurrentTime = IP_NETC__TMR0_BASE->TMR_CUR_TIME_L; /* should read the Lower register first */
2018 CurrentTime |= ((uint64)(IP_NETC__TMR0_BASE->TMR_CUR_TIME_H)) << NETC_ETH_IP_32BIT_SHIFT;
2019 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminBaseTime = CurrentTime; /* set base time to current time */
2020
2021 /* fill in gate control list entries data */
2022 for (EntryIdx = 0U; EntryIdx < Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength; EntryIdx++)
2023 {
2024 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[EntryIdx].AdminTimeInterval = 2000000U; /* the value is equal to transmit 128bytes + 20 bytes (header) frame with port speed 10M */
2025 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[EntryIdx].AdminTrafficClassGateStates = 0xFFU; /* all open */
2026 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[EntryIdx].AdminGateOperationType = NETC_ETH_HOST_REQUEST_UNCHANGED;
2027 }
2028
2029 /* add these 2 gate control list entries */
2030 Status = Netc_Eth_Ip_ConfigPortTimeGateScheduling(ctrlIndex, TRUE);
2031
2032 return Status;
2033 }
2034 #endif
2035 #endif
2036
2037 /*FUNCTION**********************************************************************
2038 *
2039 * Function Name : Netc_Eth_Ip_GetMatchedEntries
2040 * Description : Function for getting matched table entries. Num_Matched field indicates if it matches an entry.
2041 *
2042 *END**************************************************************************/
Netc_Eth_Ip_GetMatchedEntries(uint8 CtrlIndex,uint32 * NumOfEntry)2043 static void Netc_Eth_Ip_GetMatchedEntries(uint8 CtrlIndex, uint32 *NumOfEntry)
2044 {
2045 uint32 producerIdx;
2046 uint32 statusField;
2047 uint32 lengthOfCmDB;
2048
2049 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
2050
2051 /* the value stored in producer index register indicates the index of next entry */
2052 if (producerIdx > 0UL)
2053 {
2054 producerIdx -= 1UL;
2055 }
2056 else /* producerIdx increased from 15 to 0, will set it to 15, or length minus 1 */
2057 {
2058 lengthOfCmDB = ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD);
2059 producerIdx = lengthOfCmDB - 0x1UL;
2060 }
2061
2062 /* get status field in the response data buffer for the matched fdb entry */
2063 statusField = Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_RSPHEADER_STATUS_FIELD_INDEX];
2064
2065 /* NUM_MATCHED should equal or greater than 1 if the entry exists for any commands. */
2066 *NumOfEntry = (statusField & (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_NUMMATCHED_MASK));
2067
2068 }
2069
2070 /*FUNCTION**********************************************************************
2071 *
2072 * Function Name : Netc_Eth_Ip_AddOrUpdateRatePolicerTableEntry
2073 * Description : Add or Update rate policer table entry function.
2074 *
2075 *
2076 *END**************************************************************************/
Netc_Eth_Ip_AddOrUpdateRatePolicerTableEntry(const uint8 CtrlIndex,Netc_Eth_Ip_CommandsType Cmd,uint32 * MatchedEntries,const Netc_Eth_Ip_RatePolicerEntryDataType * RatePolicerTableEntry)2077 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateRatePolicerTableEntry( const uint8 CtrlIndex,
2078 Netc_Eth_Ip_CommandsType Cmd,
2079 uint32 *MatchedEntries,
2080 const Netc_Eth_Ip_RatePolicerEntryDataType * RatePolicerTableEntry
2081 )
2082 {
2083 Netc_Eth_Ip_StatusType status;
2084 uint32 ActionsData;
2085 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData = {0U};
2086
2087 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2088 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2089 DevAssert(RatePolicerTableEntry != NULL_PTR);
2090 DevAssert(MatchedEntries != NULL_PTR);
2091 #endif
2092
2093 /* clear the variable MatchedEntries first */
2094 *MatchedEntries = 0U;
2095
2096 /* only support Add and Update commands */
2097 if ((NETC_ETH_ADD_CMD != Cmd) && (NETC_ETH_UPDATE_CMD != Cmd))
2098 {
2099 status = NETC_ETH_IP_STATUS_UNSUPPORTED; /* not supported command */
2100 }
2101 else
2102 {
2103 /* set table version and CFGEU, FEEU, ... flag */
2104 ActionsData = (NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(RatePolicerTableEntry->ConfigurationElementUpdate ? 1U : 0U) \
2105 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_FEEU(RatePolicerTableEntry->FunctionalEnableElementUpdate ? 1U : 0U)) \
2106 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_PSEU(RatePolicerTableEntry->PolicerStateElementUpdate ? 1U : 0U) \
2107 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_STSEU(RatePolicerTableEntry->StatisticsElementUpdate ? 1U : 0U) \
2108 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
2109
2110 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15();
2111 /* ------initialize the table request data buffer------ */
2112 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
2113 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = RatePolicerTableEntry->RatePolicerEntryId; /* fill in Entry_ID field (Access Key) */
2114 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cir; /* CFGE CIR field */
2115 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cbs; /* CFGE CBS field */
2116 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Eir; /* CFGE EIR field */
2117 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ebs; /* CFGE EBS field */
2118 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_MREN((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Mren) ? 1U : 0U) \
2119 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_DOY((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Doy) ? 1U : 0U) \
2120 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CM((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cm) ? 1U : 0U) \
2121 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CF((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cf) ? 1U : 0U) \
2122 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_NDOR((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ndor) ? 1U : 0U) \
2123 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_SDU_TYPE(RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType);
2124
2125 /* fill in Functional Enable Element Data */
2126 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] |= (NETC_ETH_IP_RATEPOLICERTABLE_FEE_DATA_FEN(RatePolicerTableEntry->RatePolicerFunctionEnable ? 1U : 0U) << NETC_ETH_IP_16BIT_SHIFT);
2127 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15();
2128
2129 /* fill in operation data for config field of Request Header*/
2130 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
2131 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
2132 OperationData.TableId = NETC_ETH_IP_RATE_POLICER_TABLE_ID;
2133 OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for Add and Update command, the Access Method should only be NETC_ETH_ENTRY_ID_MATCH */
2134 OperationData.Cmd = Cmd;
2135 OperationData.ReqBuffLength = (NETC_ETH_IP_RATEPOLICERTABLE_REQBUFFER_LEN);
2136 OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN);
2137
2138 /* send command */
2139 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
2140 #if defined(ERR_IPV_NETC_051243)
2141 #if (STD_ON == ERR_IPV_NETC_051243)
2142 /* Error code 0x8A is not a real error. check it on Errata. */
2143 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
2144 {
2145 #endif
2146 #else
2147 if (status == NETC_ETH_IP_STATUS_SUCCESS)
2148 {
2149 #endif
2150 status = NETC_ETH_IP_STATUS_SUCCESS;
2151 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
2152 }
2153 }
2154
2155 return status;
2156 }
2157
2158 /*FUNCTION**********************************************************************
2159 *
2160 * Function Name : Netc_Eth_Ip_QueryRatePolicerTableEntry
2161 * Description : Query Rate policer table entry function.
2162 *
2163 *
2164 *END**************************************************************************/
2165 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryRatePolicerTableEntry( const uint8 CtrlIndex,
2166 uint32 *MatchedEntries,
2167 uint32 RatePolicerEntryId,
2168 Netc_Eth_Ip_RatePolicerEntryRspDataType * RatePolicerTableEntry
2169 )
2170 {
2171 Netc_Eth_Ip_StatusType status;
2172 uint32 ActionsData;
2173 uint32 CfgeConfigBits;
2174 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData = {0U};
2175 uint8 SduType;
2176 uint64 TempTableDataField;
2177
2178 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2179 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2180 DevAssert(MatchedEntries != NULL_PTR);
2181 DevAssert(RatePolicerTableEntry != NULL_PTR);
2182 #endif
2183
2184 /* clear the variable MatchedEntries first */
2185 *MatchedEntries = 0U;
2186
2187 /* always do the full query. 0x0 = Full query. */
2188 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
2189 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
2190
2191 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21();
2192 /* ------initialize the table request data buffer------ */
2193 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
2194 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = RatePolicerEntryId; /* fill in Entry_ID field (Access Key) */
2195 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21();
2196
2197 /* fill in operation data for config field of Request Header*/
2198 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
2199 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
2200 OperationData.TableId = NETC_ETH_IP_RATE_POLICER_TABLE_ID;
2201 OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for query command, always uses NETC_ETH_ENTRY_ID_MATCH method */
2202 OperationData.Cmd = NETC_ETH_QUERY_CMD;
2203 OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
2204 OperationData.RspBuffLength = (NETC_ETH_IP_RATEPOLICERTABLE_RSPBUFFER_LEN); /* set response data buffer length */
2205
2206 /* send command */
2207 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
2208 #if defined(ERR_IPV_NETC_051243)
2209 #if (STD_ON == ERR_IPV_NETC_051243)
2210 /* Error code 0x8A is not a real error. check it on Errata. */
2211 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
2212 {
2213 #endif
2214 #else
2215 if (status == NETC_ETH_IP_STATUS_SUCCESS)
2216 {
2217 #endif
2218 status = NETC_ETH_IP_STATUS_SUCCESS;
2219 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
2220
2221 /* found a matched entry */
2222 if (1U == *MatchedEntries)
2223 {
2224 /* fill in "Netc_Eth_Ip_RatePolicerEntryDataType" structure with data in response data buffer */
2225 RatePolicerTableEntry->RatePolicerEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[0U];
2226 /* fill in STSE data */
2227 TempTableDataField = ((uint64)Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U]) << NETC_ETH_IP_32BIT_SHIFT;
2228 RatePolicerTableEntry->RatePolicerStseData.Stse_ByteCount = TempTableDataField | (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U]);
2229 RatePolicerTableEntry->RatePolicerStseData.Stse_DropFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[3U];
2230 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr0GrnFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U];
2231 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr1GrnFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U];
2232 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr2YlwFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U];
2233 RatePolicerTableEntry->RatePolicerStseData.Stse_RemarkYlwFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U];
2234 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr3RedFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[13U];
2235 RatePolicerTableEntry->RatePolicerStseData.Stse_RemarkRedFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[15U];
2236 RatePolicerTableEntry->RatePolicerStseData.Stse_Lts = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[17U];
2237 RatePolicerTableEntry->RatePolicerStseData.Stse_CommittedTokenBucketInteger = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[18U];
2238 RatePolicerTableEntry->RatePolicerStseData.Stse_CommittedTokenBucketFractional = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[19U]; /* 1 sign bit + 31 bits fractional */
2239 RatePolicerTableEntry->RatePolicerStseData.Stse_ExcessTokenBucketInteger = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[20U];
2240 RatePolicerTableEntry->RatePolicerStseData.Stse_ExcessTokenBucketFranctional = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[21U]; /* 1 sign bit + 31 bits fractional */
2241 /* fill in CFGE data */
2242 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cir = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[22U];
2243 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cbs = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[23U];
2244 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Eir = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[24U];
2245 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ebs = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[25U];
2246 CfgeConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[26U];
2247 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Mren = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_MREN_MASK) == 0U) ? FALSE : TRUE;
2248 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Doy = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_DOY_MASK) == 0U) ? FALSE : TRUE;
2249 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cm = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CM_MASK) == 0U) ? FALSE : TRUE;
2250 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cf = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CF_MASK) == 0U) ? FALSE : TRUE;
2251 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ndor = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_NDOR_MASK) == 0U) ? FALSE : TRUE;
2252 SduType = (uint8)((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_SDU_TYPE_MASK) >> NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_SDU_TYPE_SHIFT);
2253 switch (SduType)
2254 {
2255 case 0U:
2256 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_PPDU;
2257 break;
2258 case 1U:
2259 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_MPDU;
2260 break;
2261 case 2U:
2262 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_MSDU;
2263 break;
2264 default:
2265 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_RSDTYPE;
2266 break;
2267 }
2268 /* fill FEE data */
2269 RatePolicerTableEntry->RatePolicerFunctionEnable = (((CfgeConfigBits >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_RATEPOLICERTABLE_FEE_DATA_FEN_MASK) == 0U) ? FALSE : TRUE;
2270 /* fill PSE data */
2271 RatePolicerTableEntry->MarkRedFlag = (((CfgeConfigBits >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_MREN_MASK) == 0U) ? FALSE : TRUE;
2272 }
2273 }
2274
2275 return status;
2276 }
2277
2278 /*FUNCTION**********************************************************************
2279 *
2280 * Function Name : Netc_Eth_Ip_DeleteRatePolicerTableEntry
2281 * Description : Delete Rate policer table entry function.
2282 *
2283 *
2284 *END**************************************************************************/
2285 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteRatePolicerTableEntry( const uint8 CtrlIndex,
2286 uint32 *MatchedEntries,
2287 uint32 RatePolicerEntryId
2288 )
2289 {
2290 Netc_Eth_Ip_StatusType status;
2291 uint32 ActionsData = 0U;
2292 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData = {0U};
2293
2294 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2295 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2296 DevAssert(MatchedEntries != NULL_PTR);
2297 #endif
2298
2299 /* clear the variable MatchedEntries first */
2300 *MatchedEntries = 0U;
2301 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22();
2302 /* ------initialize the table request data buffer------ */
2303 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* Delete command will ignore ActionsData data field */
2304 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = RatePolicerEntryId; /* fill in Entry_ID field (Access Key) */
2305 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22();
2306
2307 /* fill in operation data for config field of Request Header*/
2308 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
2309 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
2310 OperationData.TableId = NETC_ETH_IP_RATE_POLICER_TABLE_ID;
2311 OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for delete command, always uses NETC_ETH_ENTRY_ID_MATCH method */
2312 OperationData.Cmd = NETC_ETH_DELETE_CMD;
2313 OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
2314 OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN); /* set response data buffer with normal length */
2315
2316 /* send the "Delete" command */
2317 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
2318 #if defined(ERR_IPV_NETC_051243)
2319 #if (STD_ON == ERR_IPV_NETC_051243)
2320 /* Error code 0x8A is not a real error. check it on Errata. */
2321 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
2322 {
2323 #endif
2324 #else
2325 if (status == NETC_ETH_IP_STATUS_SUCCESS)
2326 {
2327 #endif
2328 status = NETC_ETH_IP_STATUS_SUCCESS;
2329 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
2330 }
2331
2332 return status;
2333 }
2334
2335 Netc_Eth_Ip_StatusType Netc_Eth_Ip_CheckFrameStatus(uint8 ctrlIndex,
2336 uint8 ring,
2337 uint32 ConsumerIndex,
2338 const uint8 *buff,
2339 Netc_Eth_Ip_TimestampType *timeStampInfo,
2340 Netc_Eth_Ip_TxStatusType *txStatus)
2341
2342 {
2343
2344 Netc_Eth_Ip_TxBDRType *txBDR;
2345 uint32 LastDescrCheckIndex;
2346 volatile uint32 CurrDescrCheckIndex;
2347 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
2348 uint32 currentTimeHigh;
2349 uint32 currentTimeLow;
2350 uint64 nanoSeconds;
2351 #ifdef NETC_ETH_0_USED
2352 uint16 TimestampInfoIndex;
2353 #endif /* NETC_ETH_0_USED */
2354 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
2355 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2356
2357 LastDescrCheckIndex= Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring];
2358 /* Get the addres of the current BDR to get status for it. */
2359 CurrDescrCheckIndex = (uint32)( (LastDescrCheckIndex + NETC_ETH_IP_PRODUCER_INCR) % \
2360 (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring] );
2361
2362 /* Verification that the current frame we check is mapped on the right BD in hardware
2363 In Autosar case this check will never happen because the frame buffers are always provided in order
2364 from the upper layer.
2365 */
2366 #ifdef MCAL_ENABLE_FAULT_INJECTION
2367 MCAL_FAULT_INJECTION_POINT(ETH_READ_BUFFER_ADDRESS_FIP);
2368 #endif
2369 if (buff == Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffAddr[ring][LastDescrCheckIndex])
2370 {
2371 if ((ConsumerIndex != LastDescrCheckIndex) && \
2372 ((boolean)TRUE == Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][LastDescrCheckIndex]))
2373 {
2374 /* Get the descriptor corresponding to the buff pointer (by looping through the descriptors) */
2375 txBDR = (Netc_Eth_Ip_TxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ring]) + (((uint32)(LastDescrCheckIndex / NETC_ETH_IP_PRODUCER_INCR)) * ((uint32)(sizeof(Netc_Eth_Ip_TxBDRType)))));
2376
2377 /* Check if there was a writeback in the descriptor */
2378 if (NETC_ETH_IP_TXBD_WRITEBACK_MASK == (txBDR->buffConfig & NETC_ETH_IP_TXBD_WRITEBACK_MASK))
2379 {
2380 /* Check the STATUS bitfield and read the possible errors and store them in info */
2381 if (0U != (uint16)(((Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->FlagsAndStatus & NETC_ETH_IP_TX_WB_STATUS_MASK))
2382 {
2383 *txStatus = (Netc_Eth_Ip_TxStatusType)(((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->FlagsAndStatus & NETC_ETH_IP_TX_WB_STATUS_MASK);
2384 }
2385 else
2386 {
2387 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
2388 /* Get the frame Timestamp */
2389 if (NULL_PTR != timeStampInfo)
2390 {
2391 /*Read the HIGH Part from SICTR registers in a succesive manner, first the LOW part, then imediately, the HIGH part*/
2392 currentTimeLow = (uint32)(netcSIsBase[ctrlIndex]->SICTR0);
2393 currentTimeHigh = (uint32)(netcSIsBase[ctrlIndex]->SICTR1);
2394
2395 /*Check for overflow on Low part of the timer*/
2396 if( (uint32) (((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->Timestamp) > currentTimeLow)
2397 {
2398 currentTimeHigh--;
2399 }
2400
2401 nanoSeconds = (uint64) ( (uint64)(((uint64)currentTimeHigh) << 32U) | (uint64)((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->Timestamp );
2402
2403 /*Take the nanoseconds*/
2404 timeStampInfo->nanoseconds = (uint32) (NETC_ETH_IP_GET_NANOSECONDS(((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->Timestamp));
2405
2406 /*Take the seconds, the low part of 32bits*/
2407 timeStampInfo->seconds = (uint32) (NETC_ETH_IP_NANO_TO_SECONDS(nanoSeconds) & NETC_ETH_IP_SECONDS_LOW_MASK_U64);
2408
2409 /*Take the seconds, the high part of 16bits*/
2410 timeStampInfo->secondsHi = (uint16) ((NETC_ETH_IP_NANO_TO_SECONDS(nanoSeconds) >> 32U) & 0xFFFFU);
2411 }
2412
2413 #ifdef NETC_ETH_0_USED
2414 if(((uint8)0U == ring) && ((uint8)0U == ctrlIndex))
2415 {
2416 TimestampInfoIndex = (0U != ConsumerIndex) ? ((uint16)ConsumerIndex) : (Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring]);
2417 Netc_Eth_Ip_TxManagementInfoBuff[0U][(TimestampInfoIndex / NETC_ETH_IP_PRODUCER_INCR) - 1U].TxTimeStampID = (uint16)(((Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->TxTimestampID);
2418 }
2419 #endif
2420 #else
2421 (void)timeStampInfo;
2422 #endif
2423
2424 }
2425 }
2426 else
2427 {
2428 /* The writeback will only be set if there is a problem sending the frame.
2429 If the frame is sent successfully the status needs to be set manually */
2430 *txStatus = NETC_ETH_TX_NO_ERR;
2431 }
2432 /* Update status of the data buffer. */
2433 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][LastDescrCheckIndex] = FALSE;
2434 /* Update the value for the last data buffer checked for the next call. */
2435 Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring] = CurrDescrCheckIndex;
2436 }
2437 else
2438 {
2439 status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
2440 }
2441 }
2442 else
2443 {
2444 status = NETC_ETH_IP_STATUS_BUFF_NOT_FOUND;
2445 }
2446
2447 return status;
2448 }
2449
2450 /*FUNCTION**********************************************************************
2451 *
2452 * Function Name : Netc_Eth_Ip_ConfigCreditBasedShaperReg
2453 * Description : Internal function for configuring credit based shaper registers.
2454 *
2455 *END**************************************************************************/
2456 static inline void Netc_Eth_Ip_ConfigCreditBasedShaperReg(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
2457 {
2458 uint8 trafficClass;
2459 uint32 localPtcTmSDUR;
2460
2461 (void)ctrlIndex;
2462 if(config->generalConfig->cbsConfig != NULL_PTR)
2463 {
2464 for(trafficClass = 0U; trafficClass < NETC_ETH_IP_NUMBER_OF_PRIORITIES; trafficClass++)
2465 {
2466 /* Coonfigure the maximum frame size per shaping class, Max 2000 */
2467 localPtcTmSDUR = IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCTMSDUR;
2468 localPtcTmSDUR &= ~ENETC_PORT_PTCTMSDUR_MAXSDU_MASK;
2469 localPtcTmSDUR |= ENETC_PORT_PTCTMSDUR_MAXSDU(config->generalConfig->cbsConfig[trafficClass]->EthMaxSizedFrame);
2470 IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCTMSDUR = localPtcTmSDUR;
2471
2472 IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCCBSR0 = ENETC_PORT_PTCCBSR0_CBSE(config->generalConfig->cbsConfig[trafficClass]->EthEgressCBShaperEnable ? 1U : 0U)
2473 | ENETC_PORT_PTCCBSR0_BW(config->generalConfig->cbsConfig[trafficClass]->EthEgressCBShaperBandwidth);
2474 IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCCBSR1 = ENETC_PORT_PTCCBSR1_HI_CREDIT(config->generalConfig->cbsConfig[trafficClass]->EthEgressHiCredit);
2475 }
2476 }
2477 }
2478
2479 /*FUNCTION**********************************************************************
2480 *
2481 * Function Name : Netc_Eth_Ip_SetupErrorReporting
2482 * Description : Internal function for configuring register used in reporting error to Pcie Event collector.
2483 *
2484 *END**************************************************************************/
2485 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetupErrorReporting(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config)
2486 {
2487 /** @brief Enum with the generic Pcie Functions present in the NETC SOC. */
2488 const Netc_Eth_Ip_PcieFunction Netc_Eth_Ip_PcieFunctionMapping[FEATURE_NETC_NUMBER_OF_FUNC] = {TIMER, EMDIO, SWITCH, ENETC};
2489
2490 uint8 u8Iterator = 0U;
2491 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
2492
2493 if (
2494 ((IP_NETC__NETC_F0_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
2495 NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
2496 (NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
2497 NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U) ||
2498 ((IP_NETC__NETC_F1_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
2499 NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
2500 (NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
2501 NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U) ||
2502 ((IP_NETC__NETC_F2_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
2503 NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
2504 (NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
2505 NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U) ||
2506 ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
2507 NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
2508 (NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
2509 NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U)
2510 )
2511 {
2512 Status = NETC_ETH_IP_STATUS_ERROR;
2513 }
2514
2515 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator++)
2516 {
2517 /* Initialize the error reporting structure which will revel the status on SWITCH, TIMER, EMDIO and ENETC */
2518 Netc_Eth_Ip_ErrorStatus[u8Iterator].Function = Netc_Eth_Ip_PcieFunctionMapping[u8Iterator];
2519 Netc_Eth_Ip_ErrorStatus[u8Iterator].StatusErrors = 0U;
2520 }
2521
2522 /* Initialize the error reporting structure which will reveal the status for PSI */
2523 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].Function = PSI;
2524 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors = 0U;
2525
2526 for (u8Iterator = FEATURE_NETC_NUMBER_OF_FUNC+1U; u8Iterator < (FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS + FEATURE_NETC_NUMBER_OF_FUNC); u8Iterator++)
2527 {
2528 /* Initialize the error reporting structure which will reveal the status on each VSI */
2529 Netc_Eth_Ip_ErrorStatus[u8Iterator].Function = VSI;
2530 Netc_Eth_Ip_ErrorStatus[u8Iterator].StatusErrors = 0U;
2531 }
2532
2533 /*For the Event Collector to assert INTA for a reported error, it must clear the interrupt disable bit:*/
2534 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCI_CFH_CMD = ierc_pci_PCI_CFH_CMD_INTR_DISABLE(0u);
2535
2536 /* Enable the Pcie AER Error Reporting */
2537 if (psi0Config->enableUncorrectableErrors)
2538 {
2539 /* For the Event Collector to assert INTA for a reported error, it must enable the reporting of the error
2540 When set, this bit enables the generation of an interrupt when a fatal error is reported by any of the Integrated Endpoints (iEPs)
2541 or the Event Collector itself.*/
2542 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCIE_CFC_AER_ROOT_ERR_CMD |= (ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN(1U) |
2543 ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN(1U));
2544 /*Unmask interrupts for ENETC0, SWITCH, TIMER, EMDIO*/
2545 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator++ )
2546 {
2547 netcPCIePFBase[u8Iterator]->PCIE_CFC_AER_UCORR_ERR_MASK = NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(0U);
2548 }
2549
2550 /*Unmask interrupts for PSI0*/
2551 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_MASK = NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(0U);
2552
2553 /*Unmask interrupts for vfs*/
2554 for (u8Iterator = 1U; u8Iterator < FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS; u8Iterator++ )
2555 {
2556 netcVFBase[u8Iterator]->PCIE_CFC_AER_UCORR_ERR_MASK = NETC_VF1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(0U);
2557 }
2558
2559 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_ETH_NUMBER_OF_CTRLS; u8Iterator++ )
2560 {
2561 netcSIsBase[u8Iterator]->SIUPECR = NETC_F3_SI0_SIUPECR_RD(0U);
2562 netcSIsBase[u8Iterator]->SIUNSBECR = NETC_F3_SI0_SIUNSBECR_THRESHOLD(psi0Config->errorReportingSystemBusErrorsThreshold);
2563 netcSIsBase[u8Iterator]->SIUNMECR = NETC_F3_SI0_SIUNMECR_RD(0U) | NETC_F3_SI0_SIUNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
2564 netcSIsBase[u8Iterator]->SIUFSBECR = NETC_F3_SI0_SIUFSBECR_RD(0U);
2565 netcSIsBase[u8Iterator]->SIUFMECR = NETC_F3_SI0_SIUFMECR_RD(0U);
2566 netcSIsBase[u8Iterator]->SIUFIECR = NETC_F3_SI0_SIUFIECR_RD(0U);
2567 }
2568
2569 /* Switch system bus error. */
2570 IP_NETC__SW0_COMMON->UNSBECR = NETC_F2_COMMON_UNSBECR_THRESHOLD(psi0Config->errorReportingSystemBusErrorsThreshold);
2571
2572
2573 IP_NETC__SW0_COMMON->UNMACECR = ~NETC_F2_COMMON_UNMACECR_PORT0(0U) |
2574 ~NETC_F2_COMMON_UNMACECR_PORT1(0U) |
2575 ~NETC_F2_COMMON_UNMACECR_PORT2(0U);
2576 IP_NETC__ENETC0_COMMON->UNMACECR = NETC_F3_COMMON_UNMACECR_PORT0(0u);
2577
2578 /*Internal memory multi bit ECC error */
2579 IP_NETC__NETC_PRIV->UNMECR = NETC_PRIV_UNMECR_RD(0U) | NETC_PRIV_UNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
2580 IP_NETC__ENETC0_COMMON->UNMECR = NETC_F3_COMMON_UNMECR_RD(0U) | NETC_F3_COMMON_UNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
2581 IP_NETC__SW0_COMMON->UNMECR = NETC_F2_COMMON_UNMECR_RD(0U) | NETC_F2_COMMON_UNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
2582
2583 /*integrity error Uncorrectable Non-Fatal Integrity Faults */
2584 ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUNIECR = NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold) | NETC_F1_GLOBAL_EMDIOUNIECR_RD(0U);
2585
2586 /*integrity error Uncorrectable Non-Fatal Integrity Faults*/
2587 IP_NETC__NETC_PRIV->UNIECR = NETC_PRIV_UNIECR_RD(0U) |NETC_PRIV_UNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold);
2588 IP_NETC__ENETC0_COMMON->UNIECR = NETC_F3_COMMON_UNIECR_RD(0U) | NETC_F3_COMMON_UNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold);
2589 IP_NETC__SW0_COMMON->UNIECR = NETC_F2_COMMON_UNIECR_RD(0U) | NETC_F2_COMMON_UNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold);
2590
2591 ((IP_NETC__TMR0_GLOBAL->ERROR).TIMER).TUFSBECR = NETC_F0_GLOBAL_TUFSBECR_RD(0U);
2592 ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUFSBECR = NETC_F1_GLOBAL_EMDIOUFSBECR_RD(0U);
2593 IP_NETC__SW0_COMMON->UFSBECR = NETC_F2_COMMON_UFSBECR_RD(0U);
2594
2595 IP_NETC__NETC_PRIV->UFMECR = NETC_PRIV_UFMECR_RD(0U);
2596 IP_NETC__ENETC0_COMMON->UFMECR = NETC_F3_COMMON_UFMECR_RD(0U) ;
2597 IP_NETC__SW0_COMMON->UFMECR = NETC_F2_COMMON_UFMECR_RD(0U);
2598
2599 IP_NETC__NETC_PRIV->UFIECR = NETC_PRIV_UFIECR_RD(0U);
2600 IP_NETC__ENETC0_COMMON->UFIECR = NETC_F3_COMMON_UFIECR_RD(0U) ;
2601 IP_NETC__SW0_COMMON->UFIECR = NETC_F2_COMMON_UFIECR_RD(0U);
2602
2603 IP_NETC__SW0_COMMON->UFSBECR = NETC_F2_COMMON_UFSBECR_RD(0U);
2604
2605 }
2606 if (psi0Config->enableCorrectableErrors)
2607 {
2608 /* For the Event Collector to assert INTA for a reported error, it must enable the reporting of the error
2609 When set, this bit enables the generation of an interrupt when a correctable error is reported by any of the Integrated Endpoints (iEPs)
2610 or the Event Collector itself.*/
2611 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCIE_CFC_AER_ROOT_ERR_CMD |= ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN(1U);
2612
2613 /* Function F0 (Timer) and F1 (EMDIO) must not clear mask bit, enabling reporting of correctable interrupts, to prevent loss of uncorrectable error reporting.*/
2614 for (u8Iterator = 2U; u8Iterator < FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator++ )
2615 {
2616 netcPCIePFBase[u8Iterator]->PCIE_CFC_AER_CORR_ERR_MASK = NETC_F0_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(0U);
2617 }
2618
2619 /*Unmask interrupts for PSI0*/
2620 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_MASK = NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(0U);
2621
2622 for (u8Iterator = 1U; u8Iterator < FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS; u8Iterator++ )
2623 {
2624 netcVFBase[u8Iterator]->PCIE_CFC_AER_CORR_ERR_MASK = NETC_VF1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(0U);
2625 }
2626
2627 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_ETH_NUMBER_OF_CTRLS; u8Iterator++ )
2628 {
2629 netcSIsBase[u8Iterator]->SICMECR = NETC_F3_SI0_SICMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold);
2630 }
2631
2632 IP_NETC__NETC_PRIV->CMECR = NETC_PRIV_CMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold);
2633 IP_NETC__ENETC0_COMMON->CMECR = NETC_F3_COMMON_CMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold) ;
2634 IP_NETC__SW0_COMMON->CMECR = NETC_F2_COMMON_CMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold);
2635 }
2636
2637 return Status;
2638 }
2639
2640 #if (NETC_ETH_MAX_NUMBER_OF_IPFTABLE_LIST > 0U)
2641 /* inline function for initializing ingress port filter table entries data during ENETC init */
2642 static inline void Netc_Eth_Ip_InitIPFTableEntryData(const Netc_Eth_Ip_ConfigType * Config, uint8 IPFTableListIdx, Netc_Eth_Ip_IngressPortFilterEntryDataType *IngressPortFilterTableEntry)
2643 {
2644 uint8 MacByteIdx;
2645 uint8 IpByteIdx;
2646 uint8 PayloadDataIdx;
2647
2648 IngressPortFilterTableEntry->IngressPortFilterEntryID = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterEntryID;
2649
2650 /* fill in cfge data */
2651 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeTargetForSelectedFilterAction = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeTargetForSelectedFilterAction;
2652 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeIpv = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeIpv;
2653 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeDr = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeDr;
2654 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeRelativePrecedentResolution = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeRelativePrecedentResolution;
2655 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideIpv = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeOverrideIpv;
2656 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideDr = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeOverrideDr;
2657 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeWakeOnLanTriggerEnable = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeWakeOnLanTriggerEnable;
2658 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterForwardingAction = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeFilterForwardingAction;
2659 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterAction = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeFilterAction;
2660
2661 /* fill in keye data */
2662 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePrecedence = 3U;
2663 IngressPortFilterTableEntry->IngressPortFilterkeyeData.keyeFrmAttributeFlags = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.keyeFrmAttributeFlags;
2664 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask;
2665 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint;
2666 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask;
2667 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation;
2668 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask;
2669 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Dst Mac Address */
2670 {
2671 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDstMacAddr[MacByteIdx];
2672 }
2673 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Dst Mac Address Mask */
2674 {
2675 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDstMacAddrMask[MacByteIdx];
2676 }
2677 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Src Mac Address */
2678 {
2679 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeSrcMacAddr[MacByteIdx];
2680 }
2681 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Src Mac Address Mask */
2682 {
2683 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeSrcMacAddrMask[MacByteIdx];
2684 }
2685 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation;
2686 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask;
2687 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherType = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeEtherType;
2688 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeEtherTypeMask;
2689 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocol = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPProtocol;
2690 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocolMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPProtocolMask;
2691 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Source Address */
2692 {
2693 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddress[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPSourceAddress[IpByteIdx];
2694 }
2695 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Source Address Mask */
2696 {
2697 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddressMask[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPSourceAddressMask[IpByteIdx];
2698 }
2699 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePort = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4SourcePort;
2700 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePortMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4SourcePortMask;
2701 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Destination Address */
2702 {
2703 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddress[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPDestinationAddress[IpByteIdx];
2704 }
2705 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Destination Address Mask */
2706 {
2707 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[IpByteIdx];
2708 }
2709 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPort = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4DestinationPort;
2710 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPortMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4DestinationPortMask;
2711
2712 /* fill in payload data */
2713 for (PayloadDataIdx = 0U; PayloadDataIdx < 24U; PayloadDataIdx++)
2714 {
2715 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[PayloadDataIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyePayloadBytes[PayloadDataIdx];
2716 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[PayloadDataIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyePayloadBytesMask[PayloadDataIdx];
2717 }
2718
2719 }
2720 #endif
2721
2722 /*==================================================================================================
2723 * GLOBAL FUNCTIONS
2724 ==================================================================================================*/
2725
2726 /*FUNCTION**********************************************************************
2727 *
2728 * Function Name : Netc_Eth_Ip_Init
2729 * implements Netc_Eth_Ip_Init_Activity
2730 *END**************************************************************************/
2731 Netc_Eth_Ip_StatusType Netc_Eth_Ip_Init(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
2732 {
2733 uint8 u8Iterator;
2734 uint8 siHwId;
2735 uint32 StartTime;
2736 uint32 ElapsedTime;
2737 uint32 TimeoutTicks;
2738 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
2739 Netc_Eth_Ip_IngressPortFilterEntryDataType IngressPortFilterTableEntry = {0U};
2740 uint8 IPFTableListIdx;
2741 uint32 MatchedEntries = 0UL;
2742
2743 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
2744 const Netc_Eth_Ip_GeneralSIConfigType *SiConfig;
2745 #endif
2746
2747 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2748 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2749 DevAssert(config != NULL_PTR);
2750 #endif
2751
2752 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
2753 {
2754 /* Use generalConfig to configure the general part of NETC */
2755
2756 /* Enable function to master memory transaction requests and enable function to respond to memory space accesses (register accesses).
2757 Setting this bit may trigger the locking of IERB registers if not already done either explicitly through the NETCRR[LOCK] bit,
2758 or an earlier function initializing. Setting memory access enable will load IERB register values into the function and start any
2759 initialization of local table memory.
2760 Poll OSR[STATE] bit and wait for 0b0 before continuing device configuration.
2761 */
2762 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCI_CFH_CMD = NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(1U) | NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS(1U);
2763
2764 /* Enable the VFs;Enable memory space for VFs */
2765 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_SRIOV_CTL |= NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_MASK | \
2766 NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_MASK;
2767
2768 /* Wait for a successfully ENETC init. */
2769 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
2770 do
2771 {
2772 if(NETC_F3_COMMON_OSR_STATE_MASK != (IP_NETC__ENETC0_COMMON->OSR & NETC_F3_COMMON_OSR_STATE_MASK))
2773 {
2774 Status = NETC_ETH_IP_STATUS_SUCCESS;
2775 break;
2776 }
2777 else
2778 {
2779 Status = NETC_ETH_IP_STATUS_TIMEOUT;
2780 }
2781 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
2782
2783 /** TODO: This will be supported later. */
2784 /* Configure the number of MSIs for all SIs - Port station interface a configuration register 2 (PSI0CFGR2 - PSI7CFGR2) */
2785
2786 /* Enable/disable MAC multicast/unicast promiscuous mode. */
2787 IP_NETC__ENETC0_BASE->PSIPMMR = ((uint32)((*config->generalConfig).maskMACPromiscuousMulticastEnable) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT) | \
2788 (uint32)((*config->generalConfig).maskMACPromiscuousUnicastEnable);
2789
2790 /* Set Layer 3 IPv4 Header checksum validation*/
2791 IP_NETC__ENETC0_BASE->PARCSCR = NETC_F3_PARCSCR_L4CD((*config->generalConfig).rxCheckSumOffloadingIPV4);
2792 /*
2793 Checking only TCP offload because when it is enabled, UDP is by default enabled in configuration
2794 Set Layer 4 TCP and UDP checksum validation
2795 */
2796 IP_NETC__ENETC0_BASE->PARCSCR = NETC_F3_PARCSCR_L3CD((*config->generalConfig).rxCheckSumOffloadingTCPUDP);
2797
2798 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
2799 /* Configure for Custom VLAN Ethertype 1 */
2800 IP_NETC__ENETC0_COMMON->CVLANR1 = config->generalConfig->CustomVlanEthertype1;
2801 /* Configure for Custom VLAN Ethertype 2 */
2802 IP_NETC__ENETC0_COMMON->CVLANR2 = config->generalConfig->CustomVlanEthertype2;
2803 #endif
2804
2805 /* Configure the VSIs using config->generalConfig */
2806 for (u8Iterator = 0U; u8Iterator < (*config->generalConfig).numberOfConfiguredSis; u8Iterator++)
2807 {
2808 /* Identify the PSI in the list of SIs to configure */
2809 siHwId = (*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].siId;
2810
2811 /* Enable PSI; In reset configuration PSI is already started, but to be sure that will not be any problems. */
2812 if (TRUE == (*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].enableSi)
2813 {
2814 /** Assure that SI is not enabled. */
2815 netcSIsBase[siHwId]->SIMR &= ~(NETC_F3_SI0_SIMR_EN_MASK);
2816
2817 if (ctrlIndex == siHwId)
2818 {
2819 /* Master enable for a station interface.*/
2820 IP_NETC__ENETC0_BASE->PMR = IP_NETC__ENETC0_BASE->PMR | (NETC_F3_PMR_SI0EN_MASK << siHwId);
2821
2822 /* For the PSI the MAC address will be configured both for the ENETC Port and for the PSI0 */
2823 /* Configure the port primary MAC address */
2824 IP_NETC__ENETC0_PORT->PMAR0 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[0U]) | \
2825 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[1U]) << 8U) | \
2826 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[2U]) << 16U) | \
2827 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[3U]) << 24U);
2828 IP_NETC__ENETC0_PORT->PMAR1 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[4U]) | \
2829 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[5U]) << 8U);
2830 IP_NETC__ENETC0_PORT->POR = 0U; /* Enable Rx and Tx Path for port (for S32N the default status for Rx and Tx path is disabled.) */
2831 }
2832 else
2833 {
2834
2835 /* Master enable for a station interface.*/
2836 IP_NETC__ENETC0_BASE->PMR = IP_NETC__ENETC0_BASE->PMR | (NETC_F3_PMR_SI0EN_MASK << siHwId);
2837
2838 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers */
2839 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR0 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[0U]) | \
2840 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[1U]) << 8U) | \
2841 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[2U]) << 16U) | \
2842 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[3U]) << 24U);
2843
2844 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR1 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[4U]) | \
2845 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[5U] )<< 8U);
2846 /* Configure where the PSI receives the message for enabled VSIs. */
2847 if(NULL_PTR != config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U])
2848 {
2849 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.VSI_NUM[siHwId - 1U].PSIVMSGRCVAR0 = (uint32)config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U] | \
2850 NETC_ETH_IP_VSITOPSI_MSG_SIZE;
2851 }
2852 }
2853
2854 /* Number of entries in a MSI table for the current SI. */
2855 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR2 = NETC_ETH_IP_NUM_OF_ENTRIES_MSITABLE;
2856
2857 /* Configure the number or TX and RX BD Rings for each SI */
2858 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_NUM_TX_BDR_MASK | NETC_F3_PSICFGR0_NUM_RX_BDR_MASK);
2859
2860 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_NUM_TX_BDR((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].NumberOfTxBDR) | \
2861 NETC_F3_PSICFGR0_NUM_RX_BDR((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].NumberOfRxBDR);
2862
2863 /* Configure the bandwidth weight for the current SI */
2864 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIBW((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].SIBandwidthWeight);
2865
2866 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
2867 SiConfig = &((*config->generalConfig->stationInterfaceGeneralConfig)[siHwId]);
2868
2869 if (TRUE == SiConfig->EnableSIVlan)
2870 {
2871 /* Enable VLAN and select tag protocol, priority code point, drop eligible indicator and VLAN identifier */
2872 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR = NETC_F3_PSIVLANR_TPID(SiConfig->SiVLANConfig.ProtocolIdentifier) |
2873 NETC_F3_PSIVLANR_PCP(SiConfig->SiVLANConfig.PriorityCodePoint) |
2874 NETC_F3_PSIVLANR_VID(SiConfig->SiVLANConfig.VlanIdentifier) |
2875 NETC_F3_PSIVLANR_E(1U) | NETC_F3_PSIVLANR_DEI((uint8)SiConfig->SiVLANConfig.DropIndicator);
2876 }
2877 else
2878 {
2879 /* Disable VLAN and select tag protocol */
2880 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR &= ~NETC_F3_PSIVLANR_E(1U);
2881 }
2882
2883 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_SIVC_MASK | NETC_F3_PSICFGR0_SIVIE_MASK | NETC_F3_PSICFGR0_VTE_MASK);
2884 /* Insert VLAN Ethertype and enable insertion of the SI-based VLAN into frames sent by this SI. This config apply for generic */
2885 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIVC(SiConfig->SIVlanControl) |
2886 NETC_F3_PSICFGR0_SIVIE((uint8)SiConfig->EnableSoftwareVlanInsert) |
2887 NETC_F3_PSICFGR0_VTE((SiConfig->EnableVLANTagExtract) ? 1U : 0U); ;
2888 #endif
2889
2890 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_ASE(((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].enableAntiSpoofing) ? 1U : 0U);
2891
2892 if (ctrlIndex != siHwId)
2893 {
2894 /* Enable bus for virtual function. */
2895 netcVFBase[u8Iterator]->PCI_CFH_CMD |= NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(1U);
2896 }
2897 }
2898 }
2899
2900 /** TODO: Advanced feature configuration. TBA later. */
2901 /* Configure the number of MAC and VLAN filter entries for all SIs - Port station interface 0 VSI MAC address filtering configuration register (PSI0VMAFCFGR) and
2902 Port station interface 0 VLAN filtering configuration register (PSI0VLANFCFGR)
2903 Port station interface a VSI MAC address filtering configuration register (PSI1VMAFCFGR - PSI7VMAFCFGR) and
2904 Port station interface a VLAN filtering configuration register (PSI1VLANFCFGR - PSI7VLANFCFGR)*/
2905 /* Configure the internal priority to ICM priority mapping - Receive IPV to ICM priority mapping register 0 (IPV2ICMPMR0) */
2906 /* Configure the IPV to traffic class assignment - Transmit priority to traffic class mapping register 0 (PRIO2TCMR0) */
2907 /* Configure speed and other settings in Port configuration register (PCR) */
2908
2909 if ((*config->generalConfig).enableCorrectableErrors || (*config->generalConfig).enableUncorrectableErrors)
2910 {
2911 Status = Netc_Eth_Ip_SetupErrorReporting(config->generalConfig);
2912 }
2913
2914 }
2915 else
2916 {
2917 /* Wait until PSI start current VSI. */
2918 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
2919 do
2920 {
2921 if (NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK == \
2922 ((netcVFBase[ctrlIndex]->PCI_CFH_CMD & NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK)))
2923 {
2924 Status = NETC_ETH_IP_STATUS_SUCCESS;
2925 break;
2926 }
2927 else
2928 {
2929 Status = NETC_ETH_IP_STATUS_TIMEOUT;
2930 }
2931 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
2932 }
2933
2934 /* Added to be sure this is not executed when VSI get a timeout. */
2935 if(NETC_ETH_IP_STATUS_SUCCESS == Status)
2936 {
2937 #if (NETC_ETH_IP_VLAN_SUPPORT == STD_ON)
2938 /** TODO: To be configured later when with al VLAN configurations. */
2939 /* Configure VLAN to IPV - Station interface VLAN to IPV mapping register 0 (SIVLANIPVMR0) and Station interface VLAN to IPV mapping register 1 (SIVLANIPVMR1) */
2940 /* Configure IPV to BDR - Station interface IPV to ring mapping register (SIIPVBDRMR0) */
2941 #endif
2942
2943 /* Initialize State structure */
2944 Netc_Eth_Ip_InitStateStructure(ctrlIndex, config);
2945
2946 /* Configure Command ring */
2947 Netc_Eth_Ip_InitCBDR(ctrlIndex);
2948
2949 /* only for PSI0 */
2950 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType)
2951 {
2952 /* pseudo port speed configuration*/
2953 IP_NETC__ENETC0_PORT->PCR &= ~ENETC_PORT_PCR_PSPEED_MASK;
2954 IP_NETC__ENETC0_PORT->PCR |= ENETC_PORT_PCR_PSPEED(NETC_ETH_IP_SHAPING_PSPEED_2000MBITS);
2955 /* clock frequency from configuration, used for credit based shapers*/
2956 Netc_Eth_Ip_NetcClockFrequency = config->netcClockFrequency;
2957 /* Configure Credit Based Shaper registers */
2958 Netc_Eth_Ip_ConfigCreditBasedShaperReg(ctrlIndex, config);
2959
2960 #if (NETC_ETH_MAX_NUMBER_OF_IPFTABLE_LIST > 0U)
2961 /* Initialize IPF table */
2962 if ((*config->generalConfig).numberOfIPFTableList > 0U)
2963 {
2964 /* Set the EN bit in Station interface mode register (SIMR) to enable psi0*/
2965 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
2966
2967 for (IPFTableListIdx = 0U; IPFTableListIdx < (*config->generalConfig).numberOfIPFTableList; IPFTableListIdx++)
2968 {
2969 /* init IPF table entry data */
2970 Netc_Eth_Ip_InitIPFTableEntryData(config, IPFTableListIdx, &IngressPortFilterTableEntry);
2971
2972 /* add static IPF table entries */
2973 Status = Netc_Eth_Ip_AddIngressPortFilterTableEntry(0U, &MatchedEntries, &IngressPortFilterTableEntry);
2974 }
2975
2976 /* Clear the EN bit in Station interface mode register (SIMR) to disalbe psi0 */
2977 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
2978 }
2979 #endif
2980 }
2981
2982 Netc_Eth_Ip_InitNTMPTables(ctrlIndex, config);
2983
2984 /* Initialize TX BDRs */
2985 Netc_Eth_Ip_InitTxBD(ctrlIndex, config);
2986 /* Initialize RX BDRs */
2987 Netc_Eth_Ip_InitRxBD(ctrlIndex, config);
2988
2989 /* Check if any interrupt is enabled and configure the hardware */
2990 if (((*config->siConfig).siMsgMruMailboxAddr != NULL_PTR) ||
2991 ((*config->siConfig).TxInterrupts != 0U) ||
2992 ((*config->siConfig).RxInterrupts != 0U))
2993 {
2994 /* Enable interrupts for the current controller. */
2995 Netc_Eth_Ip_EnableIrq(ctrlIndex, config);
2996 }
2997
2998 }
2999 return Status;
3000 }
3001
3002 /*FUNCTION**********************************************************************
3003 *
3004 * Function Name : Netc_Eth_Ip_ConfigureCreditBasedShaper
3005 * Description : function for configuring the CBS
3006 * implements Netc_Eth_Ip_ConfigureCreditBasedShaper_Activity
3007 *END**************************************************************************/
3008 Std_ReturnType Netc_Eth_Ip_ConfigureCreditBasedShaper(const uint8 ctrlIndex, const uint8 TrafficClass, const uint64 idleSlope)
3009 {
3010 Std_ReturnType status = E_OK;
3011 uint64 portTxRate;
3012 uint64 largeBandwidth;
3013 uint32 bandwidth;
3014 uint64 largeEgressHiCredit;
3015 uint32 egressHiCredit;
3016 uint32 Netc_Eth_Ip_MaxFrameSize;
3017
3018 #if(STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3019 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3020 /* A Slope of zero would cause a bandwidth of zero and this would cause a buffer leak */
3021 DevAssert(idleSlope > 0U);
3022 DevAssert(TrafficClass < NETC_ETH_IP_NUMBER_OF_PRIORITIES);
3023 #endif
3024
3025 (void)ctrlIndex;
3026
3027 /*This is a pseudo-port. */
3028 portTxRate = 2000000000UL;
3029
3030 largeBandwidth = idleSlope / (portTxRate / 10000UL); /* bandwidth is in % and 100th precision, so need to divide by 10000 */
3031 if( largeBandwidth < 100UL )
3032 {
3033 largeBandwidth = 100UL; /* Min of 1% bandwidth, otherwise frames would get stuck in the switch */
3034 }
3035 /* Round and convert to uint32 */
3036 bandwidth = (uint32)(largeBandwidth/100UL);
3037 bandwidth = ((uint64)((((uint64)bandwidth)*100UL)+50UL)>largeBandwidth)?bandwidth:(bandwidth+1UL);
3038
3039 /* High Credit in credits
3040 hiCredit (bits) = maxSizedFrame * (idleSlope / portTxRate)
3041 bandwidth = idleSlope / portTxRate
3042 Then:
3043 hiCredit (bits) = maxSizedFrame * bandwidth
3044
3045 hiCredit (credits) = hiCredit (bits) * (ClockFrequency / portTxRate)
3046 Then:
3047 hiCredit (credits) = maxSizedFrame * bandwidth * (ClockFrequency / portTxRate)
3048 */
3049 Netc_Eth_Ip_MaxFrameSize = IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCTMSDUR;
3050 largeEgressHiCredit = largeBandwidth * Netc_Eth_Ip_MaxFrameSize * (Netc_Eth_Ip_NetcClockFrequency / (portTxRate)) / 100UL; /* Bandwidth is in %, need to div by 100 */
3051 /* Round and convert to uint32 */
3052 egressHiCredit = (uint32)(largeEgressHiCredit/100UL);
3053 egressHiCredit = (((egressHiCredit*100UL)+50UL)>egressHiCredit)?egressHiCredit:(egressHiCredit+1UL);
3054 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07();
3055 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 &= ~ENETC_PORT_PTCCBSR0_BW_MASK;
3056 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 |= ENETC_PORT_PTCCBSR0_BW(bandwidth);
3057 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07();
3058 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR1 = ENETC_PORT_PTCCBSR1_HI_CREDIT(egressHiCredit);
3059
3060 return status;
3061 }
3062
3063 /*FUNCTION**********************************************************************
3064 *
3065 * Function Name : Netc_Eth_Ip_EnableCreditBasedShaper
3066 * Description : function for enabling a CBS
3067 * implements Netc_Eth_Ip_EnableCreditBasedShaper_Activity
3068 *END**************************************************************************/
3069 Std_ReturnType Netc_Eth_Ip_EnableCreditBasedShaper(const uint8 ctrlIndex, const uint8 TrafficClass, const boolean Enable)
3070 {
3071 Std_ReturnType status = E_OK;
3072
3073 #if(STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3074 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3075 DevAssert(TrafficClass < NETC_ETH_IP_NUMBER_OF_PRIORITIES);
3076 #endif
3077 (void)ctrlIndex;
3078 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08();
3079 /* clear the bit first */
3080 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 &= ~ENETC_PORT_PTCCBSR0_CBSE_MASK;
3081 /* write the bit */
3082 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 |= ENETC_PORT_PTCCBSR0_CBSE((TRUE==Enable)?1U:0U);
3083 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08();
3084
3085 return status;
3086 }
3087
3088 /*FUNCTION**********************************************************************
3089 *
3090 * Function Name : Netc_Eth_Ip_EnableController
3091 * implements Netc_Eth_Ip_EnableController_Activity
3092 *END**************************************************************************/
3093 Netc_Eth_Ip_StatusType Netc_Eth_Ip_EnableController(uint8 ctrlIndex)
3094 {
3095 uint8 ringCounter = 0U;
3096 /* Assumption: If the Coalescing ISR is enabled on the ctrlIndex, it means all the rings will have the ISR enabled.
3097 Context: If at least one controller has the Tx Coalesing Isr Enabled, TxCoalescingIsrEnabled will be true if the generated thresholds will not be 0. */
3098 boolean TxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[ctrlIndex]->TxTimerThreshold[0U] != 0U) &&
3099 (Netc_Eth_Ip_apxState[ctrlIndex]->TxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ;
3100 boolean RxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[ctrlIndex]->RxTimerThreshold[0U] != 0U) &&
3101 (Netc_Eth_Ip_apxState[ctrlIndex]->RxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ;
3102 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3103 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3104 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3105 #endif
3106 if ( Netc_Eth_Ip_apxState[ctrlIndex]->RxInterrupts != 0U)
3107 {
3108 /* Tx and Rx Interrupts enabled*/
3109 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR; ringCounter++)
3110 {
3111 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
3112 /* Write the interrupt settings as configured */
3113 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBIER |= (uint32)1U;
3114 if (RxCoalescingIsrEnabled)
3115 {
3116 /*If timer threshold is used it should be set when RBaICR0[ICEN]=0 to avoid missing a "first packet" received condition which starts the timer.*/
3117 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR1 |= NETC_F3_SI0_RBICR1_ICTT( Netc_Eth_Ip_apxState[ctrlIndex]->RxTimerThreshold[ringCounter]);
3118 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 |= NETC_F3_SI0_RBICR0_ICPT(Netc_Eth_Ip_apxState[ctrlIndex]->RxPacketsThreshold[ringCounter]);
3119 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 |= NETC_F3_SI0_RBICR0_ICEN(1U);
3120 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
3121 }
3122 else
3123 {
3124 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
3125 }
3126 }
3127 }
3128 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
3129 if ( Netc_Eth_Ip_apxState[ctrlIndex]->TxInterrupts != 0U)
3130 {
3131 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR; ringCounter++)
3132 {
3133
3134 if (TxCoalescingIsrEnabled)
3135 {
3136 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER = NETC_F3_SI0_TBIER_TXTIE(1U);
3137 /*If timer threshold is used it should be set when TBaICR0[ICEN]=0 to avoid missing a "firstpacket" transmitted condition which starts the timer.*/
3138 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR1 |= NETC_F3_SI0_TBICR1_ICTT( Netc_Eth_Ip_apxState[ctrlIndex]->TxTimerThreshold[ringCounter]);
3139 /*If packet threshold is used it should be set when TBaICR0[ICEN] is set */
3140 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR0 |= (NETC_F3_SI0_TBICR0_ICEN(1U) | NETC_F3_SI0_TBICR0_ICPT(Netc_Eth_Ip_apxState[ctrlIndex]->TxPacketsThreshold[ringCounter]));
3141
3142 }
3143 else
3144 {
3145 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER = NETC_F3_SI0_TBIER_TXFIE(1U);
3146 }
3147 }
3148 }
3149
3150 /* Set the EN bit in Station interface mode register (SIMR) */
3151 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
3152 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
3153
3154 return NETC_ETH_IP_STATUS_SUCCESS;
3155 }
3156
3157 /*FUNCTION**********************************************************************
3158 *
3159 * Function Name : Netc_Eth_Ip_DisableController
3160 * implements Netc_Eth_Ip_DisableController_Activity
3161 *END**************************************************************************/
3162 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DisableController(uint8 ctrlIndex)
3163 {
3164 uint32 ringCounter = 0U;
3165 uint32 currBDIdx = 0U;
3166 Netc_Eth_Ip_TxBDRType *txTmpBDR;
3167 Netc_Eth_Ip_RxBDRType *rxTmpBDR;
3168 boolean isPendingRing = FALSE;
3169 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
3170
3171 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3172 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3173 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3174 #endif
3175 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02();
3176
3177 /* Check whether any transmit pending ring haven been consumed before disable the SI */
3178 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR; ringCounter++)
3179 {
3180 if (netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBPIR != netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBCIR)
3181 {
3182 isPendingRing = TRUE;
3183 break;
3184 }
3185 }
3186
3187 if (isPendingRing == FALSE)
3188 {
3189 /* Clear the EN bit in Station interface mode register (SIMR) */
3190 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
3191
3192 /* Restore all information related with the TX operations. */
3193 /* Loop through all the configured transmission rings */
3194 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR; ringCounter++)
3195 {
3196 /* Write the interrupt settings as configured */
3197 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER &= ~NETC_F3_SI0_TBIER_TXTIE_MASK;
3198 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICEN_MASK;
3199 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER &= ~NETC_F3_SI0_TBIER_TXFIE_MASK;
3200 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR1 = 0U; /* &= ~NETC_F3_SI0_TBICR1_ICTT_MASK; */
3201 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICPT_MASK;
3202 /* Reset producer and consumer indexes. */
3203 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBPIR = 0U;
3204 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBCIR = 0U;
3205 txTmpBDR = Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ringCounter];
3206 /* Loop through all descriptors of the ring. */
3207 for (currBDIdx = 0U; currBDIdx < Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ringCounter]; currBDIdx++)
3208 {
3209 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3210 /* Write in the buffer descriptor the extended bit */
3211 txTmpBDR->buffConfig |= NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;
3212 txTmpBDR->extendBuffConfig |= (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));
3213 #else
3214 /* For the last descriptor write the final flag */
3215 txTmpBDR->buffConfig |= (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));
3216 #endif
3217 txTmpBDR++;
3218
3219 /* Reset TX state variable realted to each descriptor. */
3220 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ringCounter][currBDIdx] = FALSE;
3221 }
3222 /* Reset TX state variable realted to each ring. */
3223 Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ringCounter] = 0U;
3224 Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ringCounter] = 0U;
3225 Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ringCounter] = 0U;
3226 }
3227
3228 /* Restore all information related with the RX operations. */
3229 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR; ringCounter++)
3230 {
3231 /* Write the interrupt settings as configured */
3232 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBIER &= ~NETC_F3_SI0_RBIER_RXTIE_MASK;
3233 /* Write the producer and consumer indexes with 0 */
3234 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBPIR = 0U;
3235 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBCIR = 0U;
3236 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICEN_MASK;
3237 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR1 = 0U; /* &= ~NETC_F3_SI0_RBICR1_ICTT_MASK; Changed due to CWE violation*/
3238 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICPT_MASK;
3239 rxTmpBDR = Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ringCounter];
3240 /* Loop through all descriptors of the queue */
3241 for (currBDIdx = 0U; currBDIdx < Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ringCounter]; currBDIdx++)
3242 {
3243 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
3244 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
3245 {
3246 #endif
3247 rxTmpBDR->configRxBD[0U] = (uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxDataBufferAddr[ringCounter]) + \
3248 (uint32)(currBDIdx * Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ringCounter]);
3249 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
3250 }
3251 #endif
3252 rxTmpBDR->configRxBD[1U] = 0U;
3253 rxTmpBDR->configRxBD[2U] = 0U;
3254 rxTmpBDR->configRxBD[3U] = 0U;
3255 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3256 rxTmpBDR->extendConfigRxBD[0U] = 0U;
3257 rxTmpBDR->extendConfigRxBD[1U] = 0U;
3258 rxTmpBDR->extendConfigRxBD[2U] = 0U;
3259 rxTmpBDR->extendConfigRxBD[3U] = 0U;
3260 #endif
3261 rxTmpBDR++;
3262 }
3263
3264 /* Reset RX state variable realted to each ring. */
3265 Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ringCounter] = Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ringCounter];
3266 Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ringCounter] = 0U;
3267 }
3268 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02();
3269
3270 Status = NETC_ETH_IP_STATUS_SUCCESS;
3271 }
3272
3273 return Status;
3274 }
3275
3276 /*FUNCTION**********************************************************************
3277 *
3278 * Function Name : Netc_Eth_Ip_GetTxBuff
3279 * implements Netc_Eth_Ip_GetTxBuff_Activity
3280 *END**************************************************************************/
3281 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxBuff(uint8 ctrlIndex,
3282 uint8 ring,
3283 Netc_Eth_Ip_BufferType *buff,
3284 uint16 *buffId)
3285 {
3286 uint32 nextProducerIdx;
3287 uint32 currProducerIdx;
3288 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
3289
3290 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3291 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3292 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3293 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
3294 DevAssert(buff != NULL_PTR);
3295 #endif
3296
3297 currProducerIdx = Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring];
3298
3299 /* Get the next producer index and the overflow status for producer counter. */
3300 nextProducerIdx = currProducerIdx + NETC_ETH_IP_PRODUCER_INCR;
3301 if (nextProducerIdx >= (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring])
3302 {
3303 nextProducerIdx = 0U;
3304 }
3305
3306 /* Test frame length */
3307 if (buff->length < NETC_ETH_IP_MIN_FRAME_LENGTH)
3308 {
3309 status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
3310 }
3311 /* ATTENTION! This mechanism is implemented to be sure that producer index will NOT be equal with the consumer index. */
3312 else if(nextProducerIdx == Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
3313 {
3314 status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
3315 }
3316 else
3317 {
3318 if (buff->length > Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring])
3319 {
3320 status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
3321 buff->length = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]);
3322 }
3323 else
3324 {
3325 #if (NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
3326 if (!Netc_Eth_Ip_ControllerHasExternalTxBufferManagement[ctrlIndex])
3327 {
3328 #endif
3329 buff->data = (uint8*) ((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxDataBufferAddr[ring] + \
3330 (currProducerIdx * Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffMaxLenAddr[ring]));
3331 #if (NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
3332 }
3333 #endif
3334 /* If used, return the buffer index */
3335 if (buffId != NULL_PTR)
3336 {
3337 *buffId = (uint16)(currProducerIdx);
3338 }
3339
3340 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
3341 exection before the previous else if condition is completed. */
3342 MCAL_INSTRUCTION_SYNC_BARRIER();
3343 MCAL_DATA_SYNC_BARRIER();
3344 /* Marked the data buff as used. */
3345 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][currProducerIdx] = TRUE;
3346 }
3347 }
3348
3349 return status;
3350 }
3351
3352 /*FUNCTION**********************************************************************
3353 *
3354 * Function Name : Netc_Eth_Ip_GetTxMultiBuff
3355 * implements Netc_Eth_Ip_GetTxMultiBuff_Activity
3356 *END**************************************************************************/
3357 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxMultiBuff(uint8 ctrlIndex,
3358 uint8 ring,
3359 uint16 NumBuffers,
3360 const uint16 BufferLength[],
3361 uint16 *buffId)
3362 {
3363 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
3364 uint32 ProducerIndex;
3365 uint32 NextProducerIndex;
3366 uint16 FreeBuffers = 0U;
3367
3368 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3369 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3370 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3371 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
3372 #endif
3373
3374 ProducerIndex = (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring];
3375 NextProducerIndex = ProducerIndex;
3376
3377 /*Check if the first buffer has length of at least 16 bytes. The hardware limits the first buffer to be of at least 16bytes.*/
3378 if (BufferLength[NETC_ETH_IP_FIRST_BUFFER_IDX] < NETC_ETH_IP_MIN_FRAME_LENGTH)
3379 {
3380 Status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
3381 }
3382 else
3383 {
3384 while ((FreeBuffers < NumBuffers) && (NETC_ETH_IP_STATUS_SUCCESS == Status))
3385 {
3386 NextProducerIndex = (NextProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
3387 /* If the buffer descriptor is free */
3388 if (NextProducerIndex != Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
3389 {
3390 if (BufferLength[FreeBuffers] <= (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]))
3391 {
3392 FreeBuffers++;
3393 }
3394 else
3395 {
3396 Status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
3397 }
3398 }
3399 else
3400 {
3401 Status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
3402 }
3403 }
3404 }
3405
3406 if (FreeBuffers == NumBuffers)
3407 {
3408 *buffId = (uint16)(ProducerIndex);
3409 }
3410
3411 return Status;
3412 }
3413
3414 /*FUNCTION**********************************************************************
3415 *
3416 * Function Name : Netc_Eth_Ip_SendMultiBufferFrame
3417 * implements Netc_Eth_Ip_SendMultiBufferFrame_Activity
3418 *END**************************************************************************/
3419 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendMultiBufferFrame(uint8 ctrlIndex,
3420 uint8 ring,
3421 Netc_Eth_Ip_BufferType Buffers[],
3422 const Netc_Eth_Ip_TxOptionsType *options,
3423 uint16 NumBuffers)
3424 {
3425 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
3426 Netc_Eth_Ip_TxBDRType *txBD;
3427 uint16 FreeBuffers = 0U;
3428 uint16 BufferIndex = 0U;
3429 uint16 FrameLength = 0U;
3430 /* Read the producer index */
3431 uint32 ProducerIndex = (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring]; /* Increment the producer index; making sure it wraps around according to the length of the ring */
3432 uint32 NextProducerIndex = ProducerIndex;
3433 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
3434 Std_ReturnType CacheStatus = E_NOT_OK;
3435 #endif
3436
3437 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3438 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3439 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3440 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
3441 #endif
3442
3443 /*Check if the first buffer does not exceed 16 bytes. The hardware limits the first buffer to 16bytes.*/
3444 if (Buffers[NETC_ETH_IP_FIRST_BUFFER_IDX].length < NETC_ETH_IP_MIN_FRAME_LENGTH)
3445 {
3446 Status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
3447 }
3448 else
3449 {
3450 while ((FreeBuffers < NumBuffers) && (NETC_ETH_IP_STATUS_SUCCESS == Status))
3451 {
3452 NextProducerIndex = (NextProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
3453 /* If the buffer descriptor is free */
3454 if (NextProducerIndex != Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
3455 {
3456 /* If the Length doesn't exceed the size of the descriptor, move to next buffer */
3457 if (Buffers[FreeBuffers].length <= (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]))
3458 {
3459 FreeBuffers++;
3460 }
3461 else
3462 {
3463 Status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
3464 }
3465 /* Calculate the size of the whole frame */
3466 FrameLength += Buffers[BufferIndex].length;
3467 }
3468 else
3469 {
3470 Status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
3471 }
3472 }
3473 }
3474
3475 if (FreeBuffers == NumBuffers)
3476 {
3477 while (BufferIndex < NumBuffers)
3478 {
3479 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][ProducerIndex] = TRUE;
3480 /* Save the address of the external buffer to be used in GetTransmitStatus for correctly identifying the descriptor. */
3481 Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffAddr[ring][ProducerIndex] = Buffers[BufferIndex].data;
3482
3483 txBD = (Netc_Eth_Ip_TxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ring]) + (((uint32)(ProducerIndex / NETC_ETH_IP_PRODUCER_INCR)) * ((uint32)(sizeof(Netc_Eth_Ip_TxBDRType)))));
3484 /* Write buffer and frame length in the buffer descriptor. */
3485 txBD->length = (((uint32)FrameLength << 16U) | Buffers[BufferIndex].length);
3486 /* Write buffer address in the descriptor. */
3487 txBD->dataBuffAddr = (uint32)Buffers[BufferIndex].data;
3488 ProducerIndex = (ProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
3489
3490 /* Update buffer descriptor for transmission */
3491 if (BufferIndex != (NumBuffers - 1U))
3492 {
3493 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3494 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;
3495 txBD->extendBuffConfig = 0U;
3496 #else
3497 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK;
3498 #endif
3499 }
3500 else
3501 {
3502 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3503 /* Write in the buffer descriptor the extended bit */
3504 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;
3505 txBD->extendBuffConfig = NETC_ETH_IP_TXBD_FINAL_MASK;
3506 #else
3507 /* Write the final flag and clear writeback field. */
3508 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_FINAL_MASK;
3509 #endif
3510 }
3511
3512 if ((0U == BufferIndex) && (options != NULL_PTR))
3513 {
3514 if(NETC_ETH_IP_SWT_MANAGEMNT == options->Flag)
3515 {
3516 /* Set Flag(FL) type; set ingress or egress port value; set value of flag qualifier(FLQ). */
3517 txBD->buffConfig |= (((uint32)NETC_ETH_IP_FLQ_VALUE << NETC_ETH_IP_FLQ_SHIFT) | \
3518 ((uint32)(options->IngrOrEgrPortNumber) << NETC_ETH_IP_INGR_EGRESS_PORT_SHIFT));
3519 if(1U == options->SwtMgSendingOpt)
3520 {
3521 txBD->buffConfig |= ((((uint32)options->SwtMgSendingOpt) << NETC_ETH_IP_SMSO_SHIFT) | \
3522 (((uint32)options->TimestampRefReq) << NETC_ETH_IP_TSR_SHIFT) | \
3523 (((uint32)options->InternalPriority) << NETC_ETH_IP_IPV_SHIFT) | \
3524 (((uint32)options->DiscardResilience) << NETC_ETH_IP_DR_SHIFT));
3525 }
3526 }
3527 else if (NETC_ETH_IP_TXSTART == options->Flag)
3528 {
3529 txBD->buffConfig |= (((uint32)NETC_ETH_IP_TXSTART) << NETC_ETH_IP_FL_SHIFT) | \
3530 (((uint32)options->TxStartEnable) << NETC_ETH_IP_TSR_SHIFT) | \
3531 (options->TxStartTime);
3532 }
3533 else
3534 {
3535 /*MISRA C-2012 Rule 15.7*/
3536 }
3537 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3538 txBD->timestamp = options->Timestamp;
3539 txBD->extendVlanBuffConfig = ((((uint32)options->PriorityCodePoint) << NETC_ETH_IP_PCP_SHIFT) & NETC_ETH_IP_PCP_MASK) | \
3540 ((((uint32)options->DropEligible) << NETC_ETH_IP_DEI_SHIFT) & NETC_ETH_IP_DEI_MASK) | \
3541 ((((uint32)options->VlanID) << NETC_ETH_IP_VID_SHIFT) & NETC_ETH_IP_VID_MASK ) | \
3542 ((((uint32)options->TagProtocolID) << NETC_ETH_IP_TPID_SHIFT) & NETC_ETH_IP_TPID_MASK);
3543 txBD->extendBuffConfig |= (((uint32)options->ExtensionFlags) << NETC_ETH_IP_E_FLAGS_SHIFT) & NETC_ETH_IP_E_FLAGS_MASK;
3544 #endif
3545 }
3546
3547 BufferIndex++;
3548 }
3549 /* Writes in memory for BD are optimized and syncronization before starting transmission need to be done
3550 to assure that transmission BD is write correctly in memory. */
3551 MCAL_DATA_SYNC_BARRIER();
3552
3553 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
3554 /* Before sending, Flush + Invalidate cache in order write back the contents to main memory and mark the cache lines as invalid so that
3555 the future reads will be done from the memory. */
3556 CacheStatus = Cache_Ip_Clean(CacheType, CACHE_IP_DATA, TRUE);
3557 if (E_NOT_OK == CacheStatus)
3558 {
3559 Status = NETC_ETH_IP_STATUS_CACHE_ERROR;
3560 }
3561 else
3562 {
3563 #endif
3564 /* Update the current value of the producer index. */
3565 Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring] = (uint16)ProducerIndex;
3566 /* Write the producer index into register to start frame sending. */
3567 netcSIsBase[ctrlIndex]->BDR_NUM[ring].TBPIR = ProducerIndex;
3568
3569 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
3570 }
3571 #endif
3572 }
3573
3574 return Status;
3575 }
3576
3577 /*FUNCTION**********************************************************************
3578 *
3579 * Function Name : Netc_Eth_Ip_SendFrame
3580 * implements Netc_Eth_Ip_SendFrame_Activity
3581 *END**************************************************************************/
3582 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendFrame(uint8 ctrlIndex,
3583 uint8 ring,
3584 Netc_Eth_Ip_BufferType *buff,
3585 const Netc_Eth_Ip_TxOptionsType *options)
3586 {
3587 Netc_Eth_Ip_TxBDRType *txBD;
3588 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
3589 uint32 ProducerIndex;
3590 uint32 NextProducerIndex;
3591 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
3592 Std_ReturnType CacheStatus = E_NOT_OK;
3593 #endif
3594
3595 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3596 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3597 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3598 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
3599 DevAssert(buff != NULL_PTR);
3600 #endif
3601
3602 /* Read the producer index */
3603 ProducerIndex = (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring];
3604 /* Increment the producer index; making sure it wraps around according to the length of the ring */
3605 NextProducerIndex = (ProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
3606
3607 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS)
3608 /* Test frame length */
3609 if (buff->length < NETC_ETH_IP_MIN_FRAME_LENGTH)
3610 {
3611 Status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
3612 }
3613 else if (buff->length > Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring])
3614 {
3615 Status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
3616 buff->length = Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring];
3617 }
3618 else
3619 {
3620 /* ATTENTION! This mechanism is implemented to be sure that producer index will NOT be equal with the consumer index,
3621 because in the equality case the transmition will be stopped. */
3622 if(NextProducerIndex != Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
3623 {
3624 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
3625 exection before the previous else if condition is completed. */
3626 MCAL_INSTRUCTION_SYNC_BARRIER();
3627 MCAL_DATA_SYNC_BARRIER();
3628 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][ProducerIndex] = TRUE;
3629 #else
3630 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
3631 exection before the previous else if condition is completed. */
3632 MCAL_INSTRUCTION_SYNC_BARRIER();
3633 MCAL_DATA_SYNC_BARRIER();
3634 #endif /* NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS */
3635 /* Save the address of the external buffer to be used in GetTransmitStatus for correctly identifying the descriptor. */
3636 Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffAddr[ring][ProducerIndex] = buff->data;
3637
3638 txBD = (Netc_Eth_Ip_TxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ring]) + (uint32)((ProducerIndex / NETC_ETH_IP_PRODUCER_INCR) * ((uint32)(sizeof(Netc_Eth_Ip_TxBDRType)))));
3639 /* Write buffer and frame length in the buffer descriptor. */
3640 txBD->length = (((uint32)buff->length << 16U) | buff->length);
3641 /* Write buffer address in the descriptor. */
3642 txBD->dataBuffAddr = (uint32)buff->data;
3643
3644 /* Check if there was a writeback in the descriptor */
3645 if (NETC_ETH_IP_TXBD_WRITEBACK_MASK == (txBD->buffConfig & NETC_ETH_IP_TXBD_WRITEBACK_MASK))
3646 {
3647 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3648 /* Write in the buffer descriptor the extended bit */
3649 txBD->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK);
3650 txBD->extendBuffConfig = NETC_ETH_IP_TXBD_FINAL_MASK;
3651 #else
3652 /* Write the final flag and clear writeback field. */
3653 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_FINAL_MASK;
3654 #endif
3655 }
3656 else
3657 {
3658 /*MISRA C-2012 Rule 15.7*/
3659 }
3660
3661 if(options != NULL_PTR)
3662 {
3663 if(NETC_ETH_IP_SWT_MANAGEMNT == options->Flag)
3664 {
3665 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3666 #ifdef NETC_ETH_0_USED
3667 /* Resetting the management frame flag here is OK as long as there is no chance of re-using the position in the array
3668 before the message it points to is processed. This is indeed ensured by the ProvideTxBuffer function which needs to
3669 successfully provide a buffer if the SetManagementInfo function, which sets the flag, is to be called. */
3670 Netc_Eth_Ip_TxManagementInfoBuff[0U][ProducerIndex / NETC_ETH_IP_PRODUCER_INCR].ManagementFrameFlag = FALSE;
3671 #endif
3672 #endif
3673 /* Set Flag(FL) type; set ingress or egress port value; set value of flag qualifier(FLQ). */
3674 txBD->buffConfig |= ((((uint32)NETC_ETH_IP_FLQ_VALUE) << NETC_ETH_IP_FLQ_SHIFT) | \
3675 ((uint32)options->IngrOrEgrPortNumber << NETC_ETH_IP_INGR_EGRESS_PORT_SHIFT));
3676 if(1U == options->SwtMgSendingOpt)
3677 {
3678 txBD->buffConfig |= ((uint32)options->SwtMgSendingOpt << NETC_ETH_IP_SMSO_SHIFT) | \
3679 ((uint32)options->TimestampRefReq << NETC_ETH_IP_TSR_SHIFT) | \
3680 ((uint32)options->InternalPriority << NETC_ETH_IP_IPV_SHIFT) | \
3681 ((uint32)options->DiscardResilience << NETC_ETH_IP_DR_SHIFT);
3682 }
3683 }
3684 else if (NETC_ETH_IP_TXSTART == options->Flag)
3685 {
3686 txBD->buffConfig |= ((((uint32)NETC_ETH_IP_TXSTART) << NETC_ETH_IP_FL_SHIFT) |
3687 (((uint32)options->TxStartEnable) << NETC_ETH_IP_TSR_SHIFT) |
3688 (options->TxStartTime));
3689 }
3690 else
3691 {
3692 /*MISRA C-2012 Rule 15.7*/
3693 }
3694 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
3695 txBD->timestamp = options->Timestamp;
3696 txBD->extendVlanBuffConfig = ((((uint32)options->PriorityCodePoint) << NETC_ETH_IP_PCP_SHIFT) & NETC_ETH_IP_PCP_MASK) | \
3697 ((((uint32)options->DropEligible) << NETC_ETH_IP_DEI_SHIFT) & NETC_ETH_IP_DEI_MASK) | \
3698 ((((uint32)options->VlanID) << NETC_ETH_IP_VID_SHIFT) & NETC_ETH_IP_VID_MASK ) | \
3699 ((((uint32)options->TagProtocolID) << NETC_ETH_IP_TPID_SHIFT) & NETC_ETH_IP_TPID_MASK);
3700 txBD->extendBuffConfig |= (((uint32)options->ExtensionFlags) << NETC_ETH_IP_E_FLAGS_SHIFT) & NETC_ETH_IP_E_FLAGS_MASK;
3701 #endif
3702 }
3703
3704 /* Writes in memory for BD are optimized and syncronization before starting transmission need to be done
3705 to assure that transmission BD is write correctly in memory. */
3706 MCAL_DATA_SYNC_BARRIER();
3707
3708 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
3709 /* Before sending, Flush + Invalidate cache in order write back the contents to main memory and mark the cache lines as invalid so that
3710 the future reads will be done from the memory. */
3711 CacheStatus = Cache_Ip_Clean(CacheType, CACHE_IP_DATA, TRUE);
3712 if (E_NOT_OK == CacheStatus)
3713 {
3714 Status = NETC_ETH_IP_STATUS_CACHE_ERROR;
3715 }
3716 else
3717 {
3718 #endif
3719 /* Update the current value of the producer index. */
3720 Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring] = (uint16)NextProducerIndex;
3721 /* Write the producer index into register to start frame sending. */
3722 netcSIsBase[ctrlIndex]->BDR_NUM[ring].TBPIR = NextProducerIndex;
3723
3724 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
3725 }/* if (E_NOT_OK == CacheStatus) */
3726 #endif
3727
3728 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS)
3729 }
3730 else
3731 {
3732 Status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
3733 }
3734 }
3735 #endif
3736
3737 return Status;
3738 }
3739
3740 /*FUNCTION**********************************************************************
3741 *
3742
3743 * Function Name : Netc_Eth_Ip_GetTransmitStatus
3744 * implements Netc_Eth_Ip_GetTransmitStatus_Activity
3745 *END**************************************************************************/
3746 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTransmitStatus(uint8 ctrlIndex,
3747 uint8 ring,
3748 const Netc_Eth_Ip_BufferType *buff,
3749 Netc_Eth_Ip_TxInfoType *info)
3750 {
3751 uint32 ConsumerIndex;
3752 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
3753
3754 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3755 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3756 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
3757 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
3758 DevAssert(buff != NULL_PTR);
3759 #endif
3760 /* Read the consumer index */
3761 ConsumerIndex = netcSIsBase[ctrlIndex]->BDR_NUM[ring].TBCIR;
3762
3763 status = Netc_Eth_Ip_CheckFrameStatus(ctrlIndex, ring, ConsumerIndex, buff->data, &(info->timestamp), &(info->txStatus));
3764
3765 return status;
3766 }
3767
3768 /*FUNCTION**********************************************************************
3769 *
3770 * Function Name : Netc_Eth_Ip_ReleaseTxBuffers
3771 * implements Netc_Eth_Ip_ReleaseTxBuffers_Activity
3772 *END**************************************************************************/
3773 void Netc_Eth_Ip_ReleaseTxBuffers(const uint8 CtrlIdx, const uint8 Ring)
3774 {
3775 uint32 CurrDescrCheckIndex;
3776 uint32 ConsumerIndex;
3777 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3778 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3779 DevAssert(Netc_Eth_Ip_apxState[CtrlIdx] != NULL_PTR);
3780 DevAssert(Ring < Netc_Eth_Ip_apxState[CtrlIdx]->NumberOfTxBDR);
3781 #endif
3782
3783 /* Read the consumer index */
3784 ConsumerIndex = netcSIsBase[CtrlIdx]->BDR_NUM[Ring].TBCIR;
3785 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29();
3786
3787 CurrDescrCheckIndex = (Netc_Eth_Ip_apxState[CtrlIdx]->lastTxDataBuffAddrIdx[Ring]) % \
3788 (uint32)(Netc_Eth_Ip_apxState[CtrlIdx]->TxRingSize[Ring]);
3789
3790 while((TRUE == Netc_Eth_Ip_apxState[CtrlIdx]->LockTxBuffDescr[Ring][CurrDescrCheckIndex]) && \
3791 (ConsumerIndex != CurrDescrCheckIndex))
3792 {
3793 Netc_Eth_Ip_apxState[CtrlIdx]->LockTxBuffDescr[Ring][CurrDescrCheckIndex] = FALSE;
3794 CurrDescrCheckIndex = (CurrDescrCheckIndex + NETC_ETH_IP_PRODUCER_INCR) % \
3795 (uint32)(Netc_Eth_Ip_apxState[CtrlIdx]->TxRingSize[Ring]);
3796 }
3797
3798 Netc_Eth_Ip_apxState[CtrlIdx]->lastTxDataBuffAddrIdx[Ring] = CurrDescrCheckIndex;
3799 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29();
3800
3801 }
3802
3803 /*FUNCTION**********************************************************************
3804 *
3805 * Function Name : Netc_Eth_Ip_SetMacAddr
3806 * implements Netc_Eth_Ip_SetMacAddr_Activity
3807 *END**************************************************************************/
3808 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetMacAddr(uint8 CtrlIndex, const uint8 *MacAddr)
3809 {
3810 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
3811
3812 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3813 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3814 DevAssert(MacAddr != NULL_PTR);
3815 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
3816 #endif
3817
3818 /* If the controller is the PSI it should write directly the MAC address. */
3819 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
3820 {
3821 IP_NETC__ENETC0_PORT->PMAR0 = ((uint32)MacAddr[0U]) | ((uint32)MacAddr[1U] << 8U) | ((uint32)MacAddr[2U] << 16U) | ((uint32)MacAddr[3U] << 24U);
3822 IP_NETC__ENETC0_PORT->PMAR1 = ((uint32)MacAddr[4U]) | ((uint32)MacAddr[5U] << 8U);
3823 }
3824 /* If the controller is a VSI a mailbox request is sent to the PSI to change the MAC address. */
3825 else
3826 {
3827 uint16 PsiRspMessage;
3828 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_MAC_ADDR_SET, MacAddr, &PsiRspMessage);
3829 }
3830
3831 return Status;
3832 }
3833
3834 /*FUNCTION**********************************************************************
3835 *
3836 * Function Name : Netc_Eth_Ip_GetMacAddr
3837 * implements Netc_Eth_Ip_GetMacAddr_Activity
3838 *END**************************************************************************/
3839 void Netc_Eth_Ip_GetMacAddr(uint8 CtrlIndex, uint8 *MacAddr)
3840 {
3841 uint32 tempRegValue;
3842
3843 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3844 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3845 DevAssert(MacAddr != NULL_PTR);
3846 #endif
3847
3848 /* Get from physical Address lower register. */
3849 tempRegValue = netcSIsBase[CtrlIndex]->SIPMAR0;
3850 MacAddr[0U] = (uint8)(tempRegValue & 0xFFU);
3851 MacAddr[1U] = (uint8)((tempRegValue >> 8U) & 0xFFU);
3852 MacAddr[2U] = (uint8)((tempRegValue >> 16U) & 0xFFU);
3853 MacAddr[3U] = (uint8)((tempRegValue >> 24U) & 0xFFU);
3854
3855 /* Get from physical Address high register. */
3856 tempRegValue = netcSIsBase[CtrlIndex]->SIPMAR1;
3857 MacAddr[4U] = (uint8)(tempRegValue & 0xFFU);
3858 MacAddr[5U] = (uint8)((tempRegValue >> 8U) & 0xFFU);
3859 }
3860
3861 /*FUNCTION**********************************************************************
3862 *
3863 * Function Name : Netc_Eth_Ip_GetCounter
3864 * implements Netc_Eth_Ip_GetCounter_Activity
3865 *END**************************************************************************/
3866 uint32 Netc_Eth_Ip_GetCounter(uint8 CtrlIndex, Netc_Eth_Ip_CounterType Counter)
3867 {
3868 const volatile uint32 *CounterAddr;
3869
3870 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3871 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3872 #endif
3873 /* Compute addres of the counter. */
3874 CounterAddr = (volatile uint32 *)((uint32)netcSIsBase[CtrlIndex] + (uint32)Counter);
3875
3876 return *CounterAddr;
3877 }
3878
3879 /*!
3880 * @brief : Function for accessing two 32 bits counters.
3881 * @details : Function for extracting the counter value using base/offset
3882 *
3883 * @param[in] baseAddressValue base address in uint32
3884 * @param[in] offsetAddressValue offset from the base
3885 *
3886 * @return Register value
3887 */
3888 static inline uint64 Netc_Eth_Ip_Extract64bitsFrom32bitsReg(const uint32 baseAddressValue, const uint32 offsetAddressValue)
3889 {
3890 uint32 lessSignificantPtrValue;
3891 const volatile uint32 *ptrToLessSignificantData;
3892 uint64 lessSignificantAddressData, mostSignificantAddressData;
3893
3894 /* The most significant is higher in memory, the next address to get the next 32 bits */
3895 lessSignificantPtrValue = baseAddressValue + offsetAddressValue;
3896
3897 /* Convert back the numbers in pointers */
3898 ptrToLessSignificantData = (volatile uint32 *) lessSignificantPtrValue;
3899
3900 /* Note that there is only one higher value buffer, should be exclusive... semaphore, what about the other cores? High level problem to be aware of */
3901 lessSignificantAddressData = ptrToLessSignificantData[0U];
3902 mostSignificantAddressData = ptrToLessSignificantData[1U];
3903
3904 /* putting it all together */
3905 return ((mostSignificantAddressData << NETC_ETH_IP_32BIT_SHIFT) | lessSignificantAddressData);
3906 }
3907
3908 /*!
3909 * @brief : Function for accessing two 32 bits counters in a table.
3910 * @details : Function for getting the two 32 bits counters using two 32 bits accesses.
3911 *
3912 * @param[in] Reg 32bits register pointer
3913 *
3914 * @return Register value
3915 */
3916 static inline uint64 Netc_Eth_Ip_GetCounterLocal(const volatile uint32 *Reg)
3917 {
3918 return Netc_Eth_Ip_Extract64bitsFrom32bitsReg((uint32) Reg, 0U);
3919 }
3920
3921 /*!
3922 * @brief : Function for initializing NTMP table.
3923 * @details : Function enables the netc controller, initializes the tables and then diasbles the netc controller
3924 *
3925 * @param[in] ctrlIndex controller index
3926 * @param[in] config controller configuration
3927 *
3928 */
3929 static inline void Netc_Eth_Ip_InitNTMPTables(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
3930 {
3931 Netc_Eth_Ip_StatusType Status;
3932
3933 /* Tables initialization should be done after enabling the controller. Set the EN bit in Station interface mode register (SIMR) to enable psi0*/
3934 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
3935
3936 /* only for PSI0 */
3937 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType)
3938 {
3939 /* Init Time Gate Scheduling Table*/
3940 /* check if TAS is enabled or not on PSI0*/
3941 Netc_Eth_Ip_PortTimeAwareShaperEnabled = (*config->generalConfig).portTimeAwareShaperEnable;
3942
3943 if (TRUE == Netc_Eth_Ip_PortTimeAwareShaperEnabled)
3944 {
3945 #if defined(ERR_IPV_NETC_E051130)
3946 #if (STD_ON == ERR_IPV_NETC_E051130)
3947 /* Default time gate scheduling conditions on the pseudo port */
3948 Status = Netc_Eth_Ip_InitTimeGateSchedulingFeature(ctrlIndex);
3949 if (Status == NETC_ETH_IP_STATUS_SUCCESS)
3950 {
3951 #endif
3952 #endif
3953 /* Add time gate scheduling table entries data */
3954 Netc_Eth_Ip_InitTimeGateSchedulingTableEntryData(config);
3955 #if defined(ERR_IPV_NETC_E051130)
3956 #if (STD_ON == ERR_IPV_NETC_E051130)
3957 }
3958 #endif
3959 #endif
3960 }
3961
3962 /* Init Vlan Filter Table*/
3963 #if (NETC_ETH_IP_NUMBER_OF_VLAN_FILTER_ENTRIES > 0U)
3964 Netc_Eth_Ip_ConfigVLANFilterTable(ctrlIndex, config);
3965 #endif
3966 }
3967
3968 /* Init Receive Flow Steering Table */
3969 (void)Netc_Eth_Ip_ConfigRfsTable(ctrlIndex, config);
3970
3971 /* After table initializatios the controller should be disabled. Clear the EN bit in Station interface mode register (SIMR) to disalbe psi0 */
3972 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
3973 }
3974
3975 /*FUNCTION**********************************************************************
3976 *
3977 * Function Name : Netc_Eth_Ip_GetCounter64
3978 * implements Netc_Eth_Ip_GetCounter64_Activity
3979 *END**************************************************************************/
3980 uint64 Netc_Eth_Ip_GetCounter64(uint8 CtrlIndex, Netc_Eth_Ip_CounterType Counter)
3981 {
3982 uint64 CounterValue;
3983
3984 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3985 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3986 #endif
3987
3988 CounterValue = Netc_Eth_Ip_GetCounterLocal((volatile uint32 *)((uint32)netcSIsBase[CtrlIndex] + (uint32)Counter));
3989
3990 return CounterValue;
3991 }
3992
3993 /*FUNCTION**********************************************************************
3994 *
3995 * Function Name : Netc_Eth_Ip_IsFrameAvailable
3996 * implements Netc_Eth_Ip_IsFrameAvailable_Activity
3997 *END**************************************************************************/
3998 boolean Netc_Eth_Ip_IsFrameAvailable(uint8 ctrlIndex, uint8 ring)
3999 {
4000 const Netc_Eth_Ip_RxBDRType *rxBDR;
4001 boolean bFrameAvailable = FALSE;
4002 uint32 rxConsumerIdx;
4003 uint32 rxProducerIdx;
4004
4005 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4006 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4007 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
4008 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR);
4009 #endif
4010
4011 rxConsumerIdx = netcSIsBase[ctrlIndex]->BDR_NUM[ring].RBCIR;
4012 rxProducerIdx = netcSIsBase[ctrlIndex]->BDR_NUM[ring].RBPIR;
4013
4014 /* Get the current descriptor corresponding to the buff pointer (by looping through the descriptors) */
4015 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
4016
4017 /* If the producer index is different from consumer index, then a frame is in the point to be receive. */
4018 /* If the ready bit is set in the writeback descriptor at least a frame is available */
4019 if ( (rxProducerIdx != rxConsumerIdx) && \
4020 (NETC_ETH_IP_RXBD_READY_MASK == (rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_READY_MASK)) )
4021 {
4022 bFrameAvailable = TRUE;
4023 }
4024
4025 return bFrameAvailable;
4026 }
4027
4028 /*FUNCTION**********************************************************************
4029 *
4030 * Function Name : Netc_Eth_Ip_ReadFrame
4031 * implements Netc_Eth_Ip_ReadFrame_Activity
4032 *END**************************************************************************/
4033 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ReadFrame(uint8 ctrlIndex,
4034 uint8 ring,
4035 Netc_Eth_Ip_BufferType *buff,
4036 Netc_Eth_Ip_RxInfoType *info)
4037 {
4038 const Netc_Eth_Ip_RxBDRType *rxBDR;
4039 uint32 CurrLowTime = 0U;
4040 uint32 CurrHighTime = 0U;
4041 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4042 #ifdef NETC_ETH_0_USED
4043 Netc_Eth_Ip_TimeType LatestTxTimestamp = { 0U, 0U};
4044 const Netc_Eth_Ip_TxTimestampResponseType *TempTxResponse;
4045 uint16 TxTimestampID;
4046 #endif /* NETC_ETH_0_USED */
4047 #else /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
4048 (void)CurrLowTime;
4049 (void)CurrHighTime;
4050 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
4051 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
4052 uint32 rxIndex = 0;
4053 uint32 HostReason;
4054 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
4055 uint32 bufferIndex = 0;
4056 #endif
4057
4058 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4059 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4060 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
4061 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR);
4062 DevAssert(buff != NULL_PTR);
4063 #endif
4064 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
4065 Std_ReturnType CacheStatus = E_NOT_OK;
4066 #endif
4067 /* Get the current descriptor corresponding to the buff pointer (by looping through the descriptors) */
4068 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
4069 rxIndex = Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring];
4070 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
4071 bufferIndex = ring * NETC_ETH_MAX_NUMBER_OF_RXBD + rxIndex;
4072 #endif
4073 if (NETC_ETH_IP_RXBD_READY_MASK != (rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_READY_MASK))
4074 {
4075 status = NETC_ETH_IP_STATUS_RX_QUEUE_EMPTY;
4076 }
4077 else
4078 {
4079
4080 /* Store information about received frame. */
4081 if (NULL_PTR != info)
4082 {
4083 info->L4cksum = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_L4_FLAG_MASK) > 0U) ? TRUE : FALSE;
4084 info->L3cksum = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_L3_FLAG_MASK) > 0U) ? TRUE : FALSE;
4085 info->finalDes = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_FINAL_MASK) > 0U) ? TRUE : FALSE;
4086 info->timestampReceived = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_TIMESTAMP_FLAG_MASK) > 0U) ? TRUE : FALSE;
4087 info->vlanHeaderAvl = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_VLAN_HEAD_FLAG_MASK) > 0U) ? TRUE : FALSE;
4088 info->pktLen = (uint16)(rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_LENGTH_MASK);
4089 info->rxStatus = (Netc_Eth_Ip_RxStatusType)((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_ERROR_MASK) >> NETC_ETH_IP_RXBD_ERROR_SHIFT);
4090 info->hostReason = (Netc_Eth_Ip_HostReasonType)((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_HOST_REASON_MASK) >> NETC_ETH_IP_RXBD_HOST_REASON_SHIFT);
4091 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
4092 info->VlanInfo.ProtocolIdentifier = (Netc_Eth_Ip_VlanProtocolIdentifierType)(rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_TPID_MASK);
4093 info->VlanInfo.PriorityCodePoint = (uint8)((rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_PCP_MASK) >> NETC_ETH_IP_RXBD_PCP_SHIFT);
4094 info->VlanInfo.DropIndicator = (((uint8)((rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_DEI_MASK) >> NETC_ETH_IP_RXBD_DEI_SHIFT) == 1U) ?
4095 TRUE : FALSE);
4096 info->VlanInfo.VlanIdentifier = (uint16)((rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_VID_MASK) >> NETC_ETH_IP_RXBD_VID_SHIFT);
4097 #endif
4098 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4099 /* Read the low register then immediately the high register to get a synchronised 64-bit time value in nanoseconds */
4100 CurrLowTime = netcSIsBase[0U]->SICTR0;
4101 CurrHighTime = netcSIsBase[0U]->SICTR1;
4102 #endif
4103 }
4104
4105 if (NETC_ETH_RX_NO_RECEIVE_ERR == (Netc_Eth_Ip_RxStatusType)((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_ERROR_MASK) >> 16U))
4106 {
4107 HostReason = ((rxBDR->configRxBD[3U] >> NETC_ETH_IP_HOSTREASON_WB_SHIFT) & NETC_ETH_IP_HOSTREASON_WB_MASK);
4108
4109 if ((NETC_ETH_IP_HOSTREASON_REGULAR_FRAME == HostReason) || (NETC_ETH_IP_HOSTREASON_SW_PTP == HostReason))
4110 {
4111
4112 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
4113 /* Mark the cache lines as invalid in order to get the new data from data buffers from memory. */
4114 CacheStatus = Cache_Ip_Invalidate(CacheType, CACHE_IP_DATA);
4115 if (E_NOT_OK == CacheStatus)
4116 {
4117 status = NETC_ETH_IP_STATUS_CACHE_ERROR;
4118 }
4119 else
4120 {
4121 #endif
4122 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
4123 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
4124 {
4125 #endif
4126 /* All conditions meet, return buffer data details. */
4127 buff->data = (uint8 *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxDataBufferAddr[ring]) + \
4128 (rxIndex * Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring]));
4129 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
4130 }
4131 else
4132 {
4133 buff->data = (uint8*)Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffAddr[bufferIndex];
4134 }
4135 #endif
4136 buff->length = (uint16)(rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_LENGTH_MASK);
4137
4138
4139 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4140 if(CurrLowTime < rxBDR->extendConfigRxBD[0U])
4141 {
4142 CurrHighTime--;
4143 }
4144 if (NULL_PTR != info)
4145 {
4146 info->PacketTimestamp = (uint64)(rxBDR->extendConfigRxBD[0U]) | (uint64)(((uint64)(CurrHighTime)) << 32U);
4147 }
4148
4149 if (NETC_ETH_IP_HOSTREASON_SW_PTP == HostReason)
4150 {
4151 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
4152 exection before the previous else if condition is completed. */
4153 MCAL_INSTRUCTION_SYNC_BARRIER();
4154 MCAL_DATA_SYNC_BARRIER();
4155 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].RingIdx = ring;
4156 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].ReceivedDataPtr = buff->data;
4157 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].SourcePort = (uint8)(rxBDR->configRxBD[1U] & NETC_ETH_IP_RXBD_SRC_PORT_MASK);
4158
4159 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampValue.nanosecondsL = rxBDR->extendConfigRxBD[0U];
4160 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampValue.nanosecondsH = CurrHighTime;
4161
4162 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
4163 Netc_Eth_Ip_RxTimestampID = (Netc_Eth_Ip_RxTimestampID % (uint32)0xFFFFU) + (uint32)1U;
4164 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampID = Netc_Eth_Ip_RxTimestampID;
4165 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampValueInvalidForSwt = (boolean)FALSE;
4166 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
4167
4168 }
4169 #endif
4170
4171 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
4172 }
4173 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
4174 }
4175
4176 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4177 #ifdef NETC_ETH_0_USED
4178 else if(NETC_ETH_IP_HOSTREASON_TIMESTAMP == HostReason)
4179 {
4180 if((0U == ctrlIndex) && (0U == ring))
4181 {
4182 TempTxResponse = (Netc_Eth_Ip_TxTimestampResponseType *)Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
4183 TxTimestampID = TempTxResponse->TxTimestampID;
4184
4185 LatestTxTimestamp.nanosecondsL = TempTxResponse->Timestamp;
4186 LatestTxTimestamp.nanosecondsH = CurrHighTime;
4187 if(CurrLowTime < LatestTxTimestamp.nanosecondsL)
4188 {
4189 LatestTxTimestamp.nanosecondsH--;
4190 }
4191
4192 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][TxTimestampInfoBuffIdx].TimestampValue.nanosecondsL = LatestTxTimestamp.nanosecondsL;
4193 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][TxTimestampInfoBuffIdx].TimestampValue.nanosecondsH = LatestTxTimestamp.nanosecondsH;
4194 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][TxTimestampInfoBuffIdx].TxTimeStampID = TxTimestampID;
4195 TxTimestampInfoBuffIdx++;
4196 TxTimestampInfoBuffIdx = (NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR == TxTimestampInfoBuffIdx) ? 0U : TxTimestampInfoBuffIdx;
4197
4198 status = NETC_ETH_IP_STATUS_HOSTREASON_TIMESTAMP;
4199 }
4200 }
4201 #endif /* NETC_ETH_0_USED */
4202 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
4203 else
4204 {
4205 status = NETC_ETH_IP_STATUS_HOSTREASON_UNKNOWN;
4206 }
4207 }
4208 else
4209 {
4210 status = NETC_ETH_IP_STATUS_ERROR;
4211 }
4212
4213 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
4214 /* Go to the next index. */
4215 Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring] = (Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring] + 1U) % \
4216 Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ring];
4217
4218 /* Increment the pointer to the current descriptor. */
4219 Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring] = (Netc_Eth_Ip_RxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ring]) + \
4220 (((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring]) * ((uint32)(sizeof(Netc_Eth_Ip_RxBDRType)))));
4221 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
4222
4223 }
4224
4225 return status;
4226 }
4227
4228 /*FUNCTION**********************************************************************
4229 *
4230 * Function Name : Netc_Eth_Ip_ProvideRxBuff
4231 * implements Netc_Eth_Ip_ProvideRxBuff_Activity
4232 *END**************************************************************************/
4233 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ProvideRxBuff(uint8 ctrlIndex,
4234 uint8 ring,
4235 const Netc_Eth_Ip_BufferType *buff)
4236 {
4237 uint16 CurrentConsumerIndex;
4238 Netc_Eth_Ip_RxBDRType *RxBDR;
4239 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4240 uint32 bufferIndex;
4241 #endif
4242
4243 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4244 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4245 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
4246 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR);
4247
4248 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4249 if (Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
4250 {
4251 DevAssert(buff != NULL_PTR);
4252 }
4253 #endif /* (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS) */
4254
4255 #endif /* (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT) */
4256
4257 CurrentConsumerIndex = Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ring];
4258 RxBDR = (Netc_Eth_Ip_RxBDRType *)((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ring] + (((uint32)CurrentConsumerIndex) * ((uint32)(sizeof(Netc_Eth_Ip_RxBDRType)))));
4259
4260 /* Configure descriptor by setting the address of data buffer and clear the rest of it. */
4261 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4262 bufferIndex = ring * FEATURE_NETC_RX_BDR_COUNT + CurrentConsumerIndex;
4263
4264 /* In case the current controller has Internal Buffer Management for reception, restore the data buffer */
4265 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
4266 {
4267 #endif
4268 RxBDR->configRxBD[0U] = ((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxDataBufferAddr[ring] + \
4269 (uint32)(CurrentConsumerIndex * Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring]));
4270 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4271 }
4272 else
4273 {
4274 Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffAddr[bufferIndex] = (uint32)buff->data;
4275 RxBDR->configRxBD[0U] = (uint32)buff->data;
4276 }
4277 #else
4278 /* Avoid compiler warning */
4279 (void)buff;
4280 #endif
4281
4282 RxBDR->configRxBD[1U] = 0U;
4283 RxBDR->configRxBD[2U] = 0U;
4284 RxBDR->configRxBD[3U] = 0U;
4285 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4286 RxBDR->extendConfigRxBD[0U] = 0U;
4287 RxBDR->extendConfigRxBD[1U] = 0U;
4288 RxBDR->extendConfigRxBD[2U] = 0U;
4289 RxBDR->extendConfigRxBD[3U] = 0U;
4290 #endif
4291 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28();
4292 /* Update consumer index. */
4293 Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ring] = (CurrentConsumerIndex + 1U) % \
4294 Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ring];
4295 netcSIsBase[ctrlIndex]->BDR_NUM[ring].RBCIR = (uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ring]);
4296 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28();
4297
4298
4299 return NETC_ETH_IP_STATUS_SUCCESS;
4300 }
4301
4302 /*FUNCTION**********************************************************************
4303 *
4304 * Function Name : Netc_Eth_Ip_ProvideMultipleRxBuff
4305 * implements Netc_Eth_Ip_ProvideMultipleRxBuff_Activity
4306 *END**************************************************************************/
4307 void Netc_Eth_Ip_ProvideMultipleRxBuff(const uint8 CtrlIndex,
4308 const uint8 Ring,
4309 uint8* BuffList[],
4310 uint16* BuffListSize)
4311 {
4312 uint16 ConsumerIndex = 0U;
4313 uint16 LastRxConsumerRead = 0U;
4314 volatile Netc_Eth_Ip_RxBDRType *RxBDR;
4315 uint16 BuffListIndex = 0U;
4316
4317 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4318 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
4319 exection before the previous else if condition is completed. */
4320 MCAL_INSTRUCTION_SYNC_BARRIER();
4321 MCAL_DATA_SYNC_BARRIER();
4322 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4323 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
4324 DevAssert(Ring < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfRxBDR);
4325 DevAssert(BuffListSize != NULL_PTR);
4326 DevAssert(*BuffListSize > 1U);
4327 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4328 if (Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[CtrlIndex])
4329 {
4330 DevAssert(BuffList != NULL_PTR);
4331 }
4332 #endif
4333 #endif
4334
4335 ConsumerIndex = Netc_Eth_Ip_apxState[CtrlIndex]->LogicRxConsumerIndex[Ring];
4336 LastRxConsumerRead = Netc_Eth_Ip_apxState[CtrlIndex]->rxCurrentIndex[Ring];
4337 do
4338 {
4339 RxBDR = (Netc_Eth_Ip_RxBDRType *)((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->FirstRxRingDescAddr[Ring]) + ((uint32)ConsumerIndex * ((uint32)(sizeof(Netc_Eth_Ip_RxBDRType)))));
4340
4341 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4342 /* In case the current controller has Internal Buffer Management for reception */
4343 if (Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[CtrlIndex])
4344 {
4345 RxBDR->configRxBD[0U] = (uint32)BuffList[BuffListIndex];
4346 }
4347 else
4348 {
4349 #else
4350 (void)BuffList;
4351 #endif
4352 RxBDR->configRxBD[0U] = ((uint32)Netc_Eth_Ip_apxState[CtrlIndex]->FirstRxDataBufferAddr[Ring] + \
4353 (ConsumerIndex * (uint32)Netc_Eth_Ip_apxState[CtrlIndex]->RxDataBuffMaxLenAddr[Ring]));
4354
4355 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
4356 }
4357 #endif
4358 RxBDR->configRxBD[1U] = 0U;
4359 RxBDR->configRxBD[2U] = 0U;
4360 RxBDR->configRxBD[3U] = 0U;
4361
4362 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4363 RxBDR->extendConfigRxBD[0U] = 0U;
4364 RxBDR->extendConfigRxBD[1U] = 0U;
4365 RxBDR->extendConfigRxBD[2U] = 0U;
4366 RxBDR->extendConfigRxBD[3U] = 0U;
4367 #endif
4368 ConsumerIndex = (ConsumerIndex + (uint16)1U) % Netc_Eth_Ip_apxState[CtrlIndex]->RxRingSize[Ring];
4369 /* Go to the next buffer */
4370 BuffListIndex++;
4371 } while((ConsumerIndex != LastRxConsumerRead) && (BuffListIndex < *BuffListSize));
4372
4373 /* Return how many descriptors have been restored. */
4374 *BuffListSize = BuffListIndex;
4375
4376 /* Update consumer index. */
4377
4378 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
4379 exection before the previous else if condition is completed. */
4380 MCAL_INSTRUCTION_SYNC_BARRIER();
4381 MCAL_DATA_SYNC_BARRIER();
4382 Netc_Eth_Ip_apxState[CtrlIndex]->LogicRxConsumerIndex[Ring] = (uint16)ConsumerIndex;
4383 netcSIsBase[CtrlIndex]->BDR_NUM[Ring].RBCIR = ConsumerIndex;
4384 }
4385 /*FUNCTION**********************************************************************
4386 *
4387 * Function Name : Netc_Eth_Ip_GetPowerState
4388 * implements Netc_Eth_Ip_GetPowerState_Activity
4389 *END**************************************************************************/
4390 Netc_Eth_Ip_PowerStateType Netc_Eth_Ip_GetPowerState(uint8 CtrlIndex)
4391 {
4392 Netc_Eth_Ip_PowerStateType status = NETC_ETH_STATE_ACTIVE;
4393
4394 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4395 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4396 DevAssert(NULL_PTR != netcSIsBase[CtrlIndex]);
4397 #endif
4398
4399 if( 0U == (netcSIsBase[CtrlIndex]->SIMR & NETC_F3_SI0_SIMR_EN_MASK))
4400 {
4401 status = NETC_ETH_STATE_INACTIVE;
4402 }
4403 return status;
4404 }
4405
4406 /*FUNCTION**********************************************************************
4407 *
4408 * Function Name : Netc_Eth_Ip_AddMulticastDstAddrToHashFilter
4409 * implements Netc_Eth_Ip_AddMulticastDstAddrToHashFilter_Activity
4410 *END**************************************************************************/
4411 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddMulticastDstAddrToHashFilter(const uint8 CtrlIndex, \
4412 const uint8 *MacAddr)
4413 {
4414 uint8 HashValue;
4415 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
4416
4417 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4418 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4419 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
4420 #endif
4421
4422 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
4423 {
4424 HashValue = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
4425
4426 /* Add MAC entry in the software table. */
4427 Status = Netc_Eth_Ip_AddMACFilterEntry(CtrlIndex, HashValue, MacAddr);
4428
4429 if(NETC_ETH_IP_STATUS_SUCCESS == Status)
4430 {
4431 /* 64 entries in table, the 5th bit of the HashValue selects between registers used. */
4432 if(0U != ((uint32)HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER))
4433 {
4434 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
4435 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR1 |= (uint32)(1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
4436 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
4437
4438 }
4439 else
4440 {
4441 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
4442 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR0 |= (uint32)(1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
4443 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
4444
4445 }
4446 }
4447 }
4448 else
4449 {
4450 uint16 PsiRspMessage;
4451 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_ADD_RX_MAC_ADDR_FILTER, MacAddr, &PsiRspMessage);
4452 }
4453
4454 return Status;
4455 }
4456
4457 /*FUNCTION**********************************************************************
4458 *
4459 * Function Name : Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter
4460 * implements Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter_Activity
4461 *END**************************************************************************/
4462 Netc_Eth_Ip_StatusType Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter(const uint8 CtrlIndex, \
4463 const uint8 *MacAddr)
4464 {
4465 uint8 HashValue;
4466 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
4467
4468 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4469 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4470 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
4471 #endif
4472
4473 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
4474 {
4475 HashValue = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
4476
4477 Status = Netc_Eth_Ip_DeleteMACFilterEntry(CtrlIndex, HashValue, MacAddr);
4478
4479 if(NETC_ETH_IP_STATUS_DELETE_MAC_ADDR == Status)
4480 {
4481 /* 64 entries in table, the 5th bit of the HashValue selects between registers used. */
4482 if((HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER) != (uint8)0U)
4483 {
4484 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
4485 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR1 &= ~(uint32)(1U << ((uint32)HashValue & NETC_ETH_IP_HASH_VALUE));
4486 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
4487
4488 }
4489 else
4490 {
4491 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
4492 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR0 &= ~(uint32)(1U << ((uint32)HashValue & NETC_ETH_IP_HASH_VALUE));
4493 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
4494 }
4495
4496 /*Mark the status variable as STATUS_SUCCESS, after hash deletion, since IPW expects it */
4497 Status = NETC_ETH_IP_STATUS_SUCCESS;
4498 }
4499 }
4500 else
4501 {
4502 uint16 PsiRspMessage;
4503 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_DELETE_RX_MAC_ADDR_FILTER, MacAddr, &PsiRspMessage);
4504 }
4505
4506 return Status;
4507 }
4508
4509 /*FUNCTION**********************************************************************
4510 *
4511 * Function Name : Netc_Eth_Ip_SetMulticastForwardAll
4512 * implements Netc_Eth_Ip_SetMulticastForwardAll_Activity
4513 *END**************************************************************************/
4514 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetMulticastForwardAll(const uint8 CtrlIndex, const boolean EnableMulticast)
4515 {
4516 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
4517
4518 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4519 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4520 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
4521 #endif
4522
4523 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
4524 {
4525 if(EnableMulticast)
4526 {
4527 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
4528 /* Enable MAC multicast promiscuous mode. */
4529 IP_NETC__ENETC0_BASE->PSIPMMR |= ((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
4530 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
4531 }
4532 else
4533 {
4534 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
4535 /* Disable MAC multicast promiscuous mode. */
4536 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
4537 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
4538 }
4539 }
4540 else
4541 {
4542 uint16 PsiRspMessage;
4543 if(EnableMulticast)
4544 {
4545 /* Enable MAC multicast promiscuous mode. */
4546 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_ENABLE_MULTICAST, NULL_PTR, &PsiRspMessage);
4547 }
4548 else
4549 {
4550 /* Disable MAC multicast promiscuous mode. */
4551 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_DISABLE_MULTICAST, NULL_PTR, &PsiRspMessage);
4552 }
4553 }
4554
4555 return Status;
4556 }
4557
4558 /*FUNCTION**********************************************************************
4559 *
4560 * Function Name : Netc_Eth_Ip_CloseMulticastReceiving
4561 * implements Netc_Eth_Ip_CloseMulticastReceiving_Activity
4562 *END**************************************************************************/
4563 Netc_Eth_Ip_StatusType Netc_Eth_Ip_CloseMulticastReceiving(const uint8 CtrlIndex)
4564 {
4565 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
4566
4567 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4568 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4569 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
4570 #endif
4571
4572 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
4573 {
4574 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12();
4575 /* Disable MAC multicast promiscuous mode. */
4576 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
4577
4578 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR1 = 0x0U;
4579 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR0 = 0x0U;
4580
4581
4582 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12();
4583
4584 }
4585 else
4586 {
4587 uint16 PsiRspMessage;
4588 /* Disable MAC multicast promiscuous mode. */
4589 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_CLOSE_FILTER, NULL_PTR, &PsiRspMessage);
4590 }
4591
4592 return Status;
4593 }
4594
4595 /*FUNCTION**********************************************************************
4596 *
4597 * Function Name : Netc_Eth_Ip_SetTxCoalescingThresholds
4598 * implements Netc_Eth_Ip_SetTxCoalescingThresholds_Activity
4599 *END**************************************************************************/
4600 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetTxCoalescingThresholds(uint8 CtrlIdx, uint8 RingIdx, uint16 PacketsThreshold, uint32 TimerThreshold)
4601 {
4602
4603 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4604 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4605 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIdx]);
4606 #endif
4607 boolean TxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[CtrlIdx]->TxTimerThreshold[RingIdx] != 0U) &&
4608 (Netc_Eth_Ip_apxState[CtrlIdx]->TxPacketsThreshold[RingIdx] != 0U)) ? TRUE : FALSE ;
4609
4610 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
4611 uint8 HwValueOfPackets = 0U;
4612
4613 if (TxCoalescingIsrEnabled)
4614 {
4615 if (PacketsThreshold < Netc_Eth_Ip_apxState[CtrlIdx]->TxRingSize[RingIdx])
4616 {
4617 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05();
4618 /* First disable the Coalescing ISR AND clear the previous values. */
4619 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICEN_MASK;
4620 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR1 = 0U; /* &= ~NETC_F3_SI0_TBICR1_ICTT_MASK; */
4621 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICPT_MASK;
4622
4623 if (TimerThreshold != 0U)
4624 {
4625 /*If timer threshold is used it should be set when TBaICR0[ICEN]=0 to avoid missing a "firstpacket" transmitted condition which starts the timer.*/
4626 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR1 |= NETC_F3_SI0_TBICR1_ICTT(TimerThreshold);
4627 Netc_Eth_Ip_apxState[CtrlIdx]->TxTimerThreshold[RingIdx] = TimerThreshold;
4628 }
4629
4630 if (PacketsThreshold != 0U)
4631 {
4632 HwValueOfPackets = Netc_Eth_Ip_CoalescingTxPacketsConversion(PacketsThreshold);
4633 /*If packet threshold is used it should be set when TBaICR0[ICEN] is set */
4634 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 |= (NETC_F3_SI0_TBICR0_ICEN_MASK | NETC_F3_SI0_TBICR0_ICPT(HwValueOfPackets));
4635 Netc_Eth_Ip_apxState[CtrlIdx]->TxPacketsThreshold[RingIdx] = HwValueOfPackets;
4636 }
4637
4638 /* Case when the ICEN bit is not enabled when Timer Threshold is set */
4639 if ((PacketsThreshold == 0U) && (TimerThreshold != 0U))
4640 {
4641 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 |= NETC_F3_SI0_TBICR0_ICEN_MASK;
4642 }
4643 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05();
4644
4645 Status = NETC_ETH_IP_STATUS_SUCCESS;
4646 }
4647 }
4648
4649 return Status;
4650 }
4651
4652 /*FUNCTION**********************************************************************
4653 *
4654 * Function Name : Netc_Eth_Ip_SetRxCoalescingThresholds
4655 * implements Netc_Eth_Ip_SetRxCoalescingThresholds_Activity
4656 *END**************************************************************************/
4657 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetRxCoalescingThresholds(uint8 CtrlIdx, uint8 RingIdx, uint16 PacketsThreshold, uint32 TimerThreshold)
4658 {
4659
4660 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4661 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4662 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIdx]);
4663 #endif
4664 boolean RxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[CtrlIdx]->RxTimerThreshold[RingIdx] != 0U) &&
4665 (Netc_Eth_Ip_apxState[CtrlIdx]->RxPacketsThreshold[RingIdx] != 0U)) ? TRUE : FALSE ;
4666 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
4667
4668 if (RxCoalescingIsrEnabled)
4669 {
4670 if (PacketsThreshold <= Netc_Eth_Ip_apxState[CtrlIdx]->RxRingSize[RingIdx])
4671 {
4672 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04();
4673 /* First disable the Coalescing ISR AND clear the previous values. */
4674 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICEN_MASK;
4675 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR1 = 0U; /* &= ~NETC_F3_SI0_RBICR1_ICTT_MASK; Changed due to CWE violation*/
4676 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICPT_MASK;
4677
4678 if (PacketsThreshold != 0U )
4679 {
4680 /*If timer threshold is used it should be set when RBaICR0[ICEN]=0 to avoid missing a "first packet" received condition which starts the timer.*/
4681 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 |= NETC_F3_SI0_RBICR0_ICPT(PacketsThreshold);
4682 Netc_Eth_Ip_apxState[CtrlIdx]->RxPacketsThreshold[RingIdx] = PacketsThreshold;
4683 }
4684
4685 if (TimerThreshold != 0U)
4686 {
4687 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR1 |= NETC_F3_SI0_RBICR1_ICTT(TimerThreshold);
4688 Netc_Eth_Ip_apxState[CtrlIdx]->RxTimerThreshold[RingIdx] = TimerThreshold;
4689 }
4690
4691 if ((PacketsThreshold != 0U)|| (TimerThreshold != 0U))
4692 {
4693 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 |= NETC_F3_SI0_RBICR0_ICEN_MASK;
4694 }
4695 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04();
4696
4697 Status = NETC_ETH_IP_STATUS_SUCCESS;
4698 }
4699 }
4700
4701 return Status;
4702 }
4703
4704 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4705 #ifdef NETC_ETH_0_USED
4706 /*FUNCTION**********************************************************************
4707 *
4708 * Function Name : Netc_Eth_Ip_ManagementFrame
4709 * implements Netc_Eth_Ip_ManagementFrame_Activity
4710 *END**************************************************************************/
4711 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ManagementFrame(const uint8 CtrlIdx, uint16 BuffIdx, uint8 SwitchIndex, uint8 PortIndex, boolean Enable)
4712 {
4713 uint16 CurrentIndex;
4714 Netc_Eth_Ip_StatusType Status;
4715
4716 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4717 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4718 #endif
4719
4720 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIdx]->SiType)
4721 {
4722 CurrentIndex = Netc_Eth_Ip_apxState[CtrlIdx]->LogicTxProducerIndex[0U];
4723
4724 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].CtrlIdx = CtrlIdx;
4725 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].TxBuffId = BuffIdx;
4726 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].SwitchIndex = SwitchIndex;
4727 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].PortIndex = PortIndex;
4728 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].ManagementFrameFlag = Enable;
4729 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].TxTimestampFlag = FALSE;
4730 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].TxTimestampRcvFlag = FALSE;
4731
4732 Status = NETC_ETH_IP_STATUS_SUCCESS;
4733 }
4734 else
4735 {
4736 Status = NETC_ETH_IP_STATUS_UNSUPPORTED;
4737 }
4738
4739 return Status;
4740 }
4741
4742 /*FUNCTION**********************************************************************
4743 *
4744 * Function Name : Netc_Eth_Ip_TimestampTxFrame
4745 * implements Netc_Eth_Ip_TimestampTxFrame_Activity
4746 *END**************************************************************************/
4747 Netc_Eth_Ip_StatusType Netc_Eth_Ip_TimestampTxFrame(const uint8 CtrlIdx, const uint16 BuffIdx, const boolean Enable)
4748 {
4749 uint16 CurrentIndex;
4750 volatile Netc_Eth_Ip_TxManagementInfoType *TxMgmtInfo;
4751 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
4752 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIdx]->SiType)
4753 {
4754 CurrentIndex = Netc_Eth_Ip_apxState[CtrlIdx]->LogicTxProducerIndex[0U];
4755 TxMgmtInfo = &Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR];
4756
4757 if (TxMgmtInfo->TxBuffId == BuffIdx)
4758 {
4759 if ((TxMgmtInfo->ManagementFrameFlag == TRUE))
4760 {
4761 TxMgmtInfo->TxTimestampFlag = Enable;
4762 Status = NETC_ETH_IP_STATUS_SUCCESS;
4763 }
4764 }
4765 }
4766
4767 return Status;
4768 }
4769
4770 /*FUNCTION**********************************************************************
4771 *
4772 * Function Name : Netc_Eth_Ip_GetTxTimestampInfo
4773 * implements Netc_Eth_Ip_GetTxTimestampInfo_Activity
4774 *END**************************************************************************/
4775 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxTimestampInfo(const uint8 CtrlIdx, \
4776 const uint32 BuffIdx, \
4777 Netc_Eth_Ip_TxManagementInfoType **MgmtInfo, Netc_Eth_Ip_TxTimestampInfoType **TimestampInfo)
4778 {
4779 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
4780 uint32 BufferIdx;
4781 uint16 LatestTimestampID;
4782 boolean FirstTimestampFlag = FALSE;
4783 uint32 TsBufferIdx;
4784 *MgmtInfo = NULL_PTR;
4785 *TimestampInfo = NULL_PTR;
4786 uint16 tempBufferIdx;
4787 uint8 tempCtrlIdx;
4788
4789 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4790 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4791 #endif
4792
4793 /* Search for timestamps associated to the frame with BuffIdx */
4794 for(BufferIdx = 0U; BufferIdx < NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR; BufferIdx++)
4795 {
4796 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23();
4797 tempBufferIdx = Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxBuffId;
4798 tempCtrlIdx = Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].CtrlIdx;
4799 if ((BuffIdx == (uint32)tempBufferIdx) && (CtrlIdx == (uint32)tempCtrlIdx))
4800 {
4801 if (Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimestampFlag == (boolean)TRUE)
4802 {
4803 if (Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimestampRcvFlag == (boolean)FALSE)
4804 {
4805 /* Mark the first matching timestamp found */
4806 if(FALSE == FirstTimestampFlag)
4807 {
4808 LatestTimestampID = Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimeStampID;
4809 FirstTimestampFlag = TRUE;
4810 *MgmtInfo = (Netc_Eth_Ip_TxManagementInfoType *)&Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx];
4811 Status = NETC_ETH_IP_STATUS_SUCCESS;
4812 }
4813 else
4814 {
4815 /* Update to keep track only of the latest timestamp info found */
4816 if(Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimeStampID > LatestTimestampID)
4817 {
4818 LatestTimestampID = Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimeStampID;
4819 *MgmtInfo = (Netc_Eth_Ip_TxManagementInfoType *)&Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx];
4820 *TimestampInfo = NULL_PTR;
4821 }
4822 }
4823 for (TsBufferIdx = 0U; TsBufferIdx < NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR; TsBufferIdx++)
4824 {
4825 if (Netc_Eth_Ip_TxTimestampInfoBuff[0u][TsBufferIdx].TxTimeStampID == Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimeStampID)
4826 {
4827 Netc_Eth_Ip_TxManagementInfoBuff[0u][BufferIdx].TxTimestampRcvFlag = TRUE;
4828 *TimestampInfo = (Netc_Eth_Ip_TxTimestampInfoType *)&Netc_Eth_Ip_TxTimestampInfoBuff[0u][TsBufferIdx];
4829 break;
4830 }
4831 }
4832 }
4833 }
4834 }
4835 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23();
4836 }
4837
4838 return Status;
4839 }
4840
4841 /*FUNCTION**********************************************************************
4842 *
4843 * Function Name : Netc_Eth_Ip_ReleaseUnusedTxBuff
4844 *END**************************************************************************/
4845 void Netc_Eth_Ip_ReleaseUnusedTxBuff(uint8 CtrlIndex, uint8 Ring)
4846 {
4847 uint32 CurrentProducerIdx;
4848
4849 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4850 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4851 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
4852 DevAssert(Ring < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfTxBDR);
4853 #endif
4854
4855 CurrentProducerIdx = Netc_Eth_Ip_apxState[CtrlIndex]->LogicTxProducerIndex[Ring];
4856
4857 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
4858 exection before the previous else if condition is completed. */
4859 MCAL_INSTRUCTION_SYNC_BARRIER();
4860 MCAL_DATA_SYNC_BARRIER();
4861 Netc_Eth_Ip_apxState[CtrlIndex]->LockTxBuffDescr[Ring][CurrentProducerIdx] = FALSE;
4862 }
4863 #endif /* NETC_ETH_0_USED */
4864
4865 /*FUNCTION**********************************************************************
4866 *
4867 * Function Name : Netc_Eth_Ip_GetRxTimestampInfo
4868 * implements Netc_Eth_Ip_GetRxTimestampInfo_Activity
4869 *END**************************************************************************/
4870 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetRxTimestampInfo(const uint8 CtrlIdx, const uint8 *DataPtr, Netc_Eth_Ip_RxTimestampInfoType **RxTimestampInfo)
4871 {
4872 uint8 RingCounter;
4873 uint32 DescrCounter;
4874 uint32 LastRxTimestampID = (uint32)0U;
4875 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
4876
4877 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4878 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4879 DevAssert(DataPtr != NULL_PTR);
4880 #endif
4881
4882 *RxTimestampInfo = NULL_PTR;
4883
4884 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24();
4885 for (RingCounter = 0U; RingCounter < Netc_Eth_Ip_apxState[CtrlIdx]->NumberOfRxBDR; RingCounter++)
4886 {
4887 for(DescrCounter = 0U; DescrCounter < NETC_ETH_IP_MAX_NUMBER_OF_RXDESCRIPTORS; DescrCounter++)
4888 {
4889 /* Pointer for searched data was found. */
4890 if (DataPtr == Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].ReceivedDataPtr)
4891 {
4892 if(RingCounter == Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].RingIdx)
4893 {
4894 /* Assure that current data is valid. */
4895 if((boolean)FALSE == Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampValueInvalidForSwt)
4896 {
4897 if(Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampID > LastRxTimestampID)
4898 {
4899 Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampValueInvalidForSwt = (boolean)TRUE;
4900 LastRxTimestampID = Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampID;
4901 *RxTimestampInfo = (Netc_Eth_Ip_RxTimestampInfoType *)&Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter];
4902 Status = NETC_ETH_IP_STATUS_SUCCESS;
4903 }
4904 else
4905 {
4906 /* Mark the rest of timestamps as invalid.
4907 This mechanism will helps not to read wrong timestamps for consecutives calls of function. */
4908 Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampValueInvalidForSwt = (boolean)TRUE;
4909 }
4910 }
4911 }
4912 }
4913 }
4914 }
4915 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24();
4916
4917 return Status;
4918 }
4919
4920 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
4921
4922 /*FUNCTION**********************************************************************
4923 *
4924 * Function Name : Netc_Eth_Ip_GetSysTime
4925 * implements Netc_Eth_Ip_GetSysTime_Activity
4926 *END**************************************************************************/
4927 void Netc_Eth_Ip_GetSysTime(uint8 ctrlIndex, Netc_Eth_Ip_TimeType *TimePtr)
4928 {
4929
4930 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4931 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
4932 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4933 DevAssert(NULL_PTR != TimePtr );
4934 #endif
4935
4936 Netc_Eth_Ip_GetCurrentTick(ctrlIndex, TimePtr);
4937 }
4938
4939 /*FUNCTION**********************************************************************
4940 *
4941 * Function Name : Netc_Eth_Ip_Deinit
4942 * implements Netc_Eth_Ip_Deinit_Activity
4943 *END**************************************************************************/
4944 Netc_Eth_Ip_StatusType Netc_Eth_Ip_Deinit(uint8 ctrlIndex)
4945 {
4946 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4947 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4948 #endif
4949
4950 uint32 StartTime;
4951 uint32 ElapsedTime;
4952 uint32 TimeoutTicks;
4953 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
4954
4955 /*Check if the controller is VSI. Deinit is not supported for PSI*/
4956 if (NETC_ETH_IP_VIRTUAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType)
4957 {
4958 /*Initiate function level reset*/
4959 netcVFBase[ctrlIndex]->PCI_CFC_PCIE_DEV_CTL = NETC_F1_PCI_HDR_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(1U);
4960
4961 /* Wait until VSI FLR is complete */
4962 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
4963 do
4964 {
4965 if (NETC_F1_PCI_HDR_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(0U) == netcVFBase[ctrlIndex]->PCI_CFC_PCIE_DEV_CTL)
4966 {
4967 Status = NETC_ETH_IP_STATUS_SUCCESS;
4968 break;
4969 }
4970 else
4971 {
4972 Status = NETC_ETH_IP_STATUS_TIMEOUT;
4973 }
4974 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
4975
4976 /* Reset global state variable */
4977 Netc_Eth_Ip_apxState[ctrlIndex] = NULL_PTR;
4978 }
4979
4980 return Status;
4981 }
4982
4983 /*FUNCTION**********************************************************************
4984 *
4985 * Function Name : Netc_Eth_Ip_PCIe_AER_Handler
4986 *
4987 *END**************************************************************************/
4988 void Netc_Eth_Ip_PCIe_AER_Handler(uint8 ctrlIndex)
4989 {
4990 uint8 i = 0U;
4991 uint8 relativeIndex = 0U;
4992
4993 /* Error reporting for TIMER EMDIO SWITCH ENETC */
4994 for( i = 0U; i < FEATURE_NETC_NUMBER_OF_FUNC; i++)
4995 {
4996 Netc_Eth_Ip_ErrorStatus[i].StatusErrors = 0u;
4997 /* Error bit status check */
4998 if ((netcPCIePFBase[i]->PCIE_CFC_AER_UCORR_ERR_STAT & NETC_ETH_IP_UCORR_STATUS_BIT) != (uint32)0U)
4999 {
5000 /* Interrupt enable bit check
5001 Un-masked interrupts are marked as 0*/
5002 if ((netcPCIePFBase[i]->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_UCORR_ERR_MASK_SHIFT)) == (uint32)0U)
5003 {
5004 /* Clean error status bit */
5005 netcPCIePFBase[i]->PCIE_CFC_AER_UCORR_ERR_STAT = (uint32)NETC_ETH_IP_UCORR_STATUS_BIT;
5006 /* Report error in case this feature is enabled in configuration */
5007 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5008 {
5009 /*If the reg bit is 0 - Error is Non-fatal else is Fatal*/
5010 if((netcPCIePFBase[i]->PCIE_CFC_AER_UCORR_ERR_SEV & NETC_ETH_IP_UCORR_SEV_MASK) != 0U)
5011 {
5012 Netc_Eth_Ip_ErrorStatus[i].StatusErrors = NETC_ETH_IP_FATAL_ERROR;
5013 }
5014 else
5015 {
5016 Netc_Eth_Ip_ErrorStatus[i].StatusErrors = NETC_ETH_IP_NON_FATAL_ERROR;
5017 }
5018 }
5019
5020 }
5021 }
5022 if ((netcPCIePFBase[i]->PCIE_CFC_AER_CORR_ERR_STAT & NETC_ETH_IP_CORR_STATUS_BIT) != (uint32)0U)
5023 {
5024 /* Un-masked interrupts are marked as 0*/
5025 if ((netcPCIePFBase[i]->PCIE_CFC_AER_CORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_CORR_ERR_MASK_SHIFT)) == (uint32)0U)
5026 {
5027 netcPCIePFBase[i]->PCIE_CFC_AER_CORR_ERR_STAT = NETC_ETH_IP_CORR_STATUS_BIT;
5028 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerCorrectableErrEnabled)
5029 {
5030 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5031 Netc_Eth_Ip_ErrorStatus[i].StatusErrors |= NETC_ETH_IP_CORRECTABLE_ERROR;
5032 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5033
5034 }
5035 }
5036 }
5037 }
5038
5039 /* Error reporting for VSIx */
5040 for (i = FEATURE_NETC_NUMBER_OF_FUNC + 1U; i < (FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS + FEATURE_NETC_NUMBER_OF_FUNC + 1U); i++)
5041 {
5042 Netc_Eth_Ip_ErrorStatus[i].StatusErrors = 0u;
5043
5044 /* netcVFBase has the index 0 null since virtual station interfaces start from 1*/
5045 relativeIndex = i - FEATURE_NETC_NUMBER_OF_FUNC;
5046
5047 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_STAT & NETC_ETH_IP_UCORR_STATUS_BIT) != (uint32)0U)
5048 {
5049 /* Un-masked interrupts are marked as 0*/
5050 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_UCORR_ERR_MASK_SHIFT)) == (uint32)0U)
5051 {
5052
5053 netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_STAT = NETC_ETH_IP_UCORR_STATUS_BIT;
5054 /*If the reg bit is 0 - Error is Non-fatal else is Fatal*/
5055 if((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_SEV & NETC_ETH_IP_UCORR_SEV_MASK) != 0U)
5056 {
5057 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5058 {
5059 Netc_Eth_Ip_ErrorStatus[i].StatusErrors = NETC_ETH_IP_FATAL_ERROR;
5060
5061 }
5062 }
5063 else
5064 {
5065 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5066 {
5067 Netc_Eth_Ip_ErrorStatus[i].StatusErrors |= NETC_ETH_IP_NON_FATAL_ERROR;
5068
5069 }
5070 }
5071
5072 }
5073 }
5074 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_CORR_ERR_STAT & NETC_ETH_IP_CORR_STATUS_BIT) != (uint32)0U)
5075 {
5076 /* Un-masked interrupts are marked as 0*/
5077 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_CORR_ERR_MASK_SHIFT)) != (uint32)0U)
5078 {
5079 netcVFBase[relativeIndex]->PCIE_CFC_AER_CORR_ERR_STAT = NETC_ETH_IP_CORR_STATUS_BIT;
5080 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerCorrectableErrEnabled)
5081 {
5082 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5083 Netc_Eth_Ip_ErrorStatus[i].StatusErrors |= NETC_ETH_IP_CORRECTABLE_ERROR;
5084 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5085
5086 }
5087
5088 }
5089
5090 }
5091 }
5092
5093 /* Uncorrectable Error reporting for PSI0 */
5094 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_STAT & NETC_ETH_IP_UCORR_STATUS_BIT) != (uint32)0U)
5095 {
5096 /* Un-masked interrupts are marked as 0*/
5097 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_UCORR_ERR_MASK_SHIFT)) == (uint32)0U)
5098 {
5099 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_STAT = NETC_ETH_IP_UCORR_STATUS_BIT;
5100 /*If the reg bit is 0 - Error is Non-fatal else is Fatal*/
5101 if((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_SEV & NETC_ETH_IP_UCORR_SEV_MASK) != 0U)
5102 {
5103 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5104 {
5105 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors = NETC_ETH_IP_FATAL_ERROR;
5106 }
5107 }
5108 else
5109 {
5110 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5111 {
5112 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors = NETC_ETH_IP_NON_FATAL_ERROR;
5113 }
5114 }
5115
5116 }
5117 }
5118 /* Correctable Error reporting for PSI0 */
5119 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_STAT & NETC_ETH_IP_CORR_STATUS_BIT) != (uint32)0U)
5120 {
5121 /* Un-masked interrupts are marked as 0*/
5122 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_CORR_ERR_MASK_SHIFT)) == (uint32)0U)
5123 {
5124 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_STAT = NETC_ETH_IP_CORR_STATUS_BIT;
5125 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerCorrectableErrEnabled)
5126 {
5127 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5128 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors |= NETC_ETH_IP_CORRECTABLE_ERROR;
5129 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5130
5131 }
5132
5133 }
5134 }
5135
5136 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerErrorReportingCallback != NULL_PTR)
5137 {
5138 Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerErrorReportingCallback (ctrlIndex, (const Netc_Eth_Ip_PcieFunctionErrorsReported *)&Netc_Eth_Ip_ErrorStatus);
5139 }
5140 }
5141
5142 static inline boolean Netc_Eth_Ip_ClearErrorStatus (volatile uint32 *RegAddress)
5143 {
5144 boolean returnValue = FALSE;
5145
5146 if ((*RegAddress & NETC_ETH_IP_CLEAR_ERROR_STATUS_MASK) != 0U)
5147 {
5148 *RegAddress |= NETC_ETH_IP_CLEAR_ERROR_STATUS_MASK;
5149 returnValue = TRUE;
5150 }
5151
5152 return returnValue;
5153 }
5154
5155 /*FUNCTION**********************************************************************
5156 *
5157 * Function Name : Netc_Eth_Ip_EnableIngressPortFiltering
5158 * Description : Ethernet enables the ingress port filtering lookup function.
5159 * implements Netc_Eth_Ip_EnableIngressPortFiltering_Activity
5160 *END**************************************************************************/
5161 Std_ReturnType Netc_Eth_Ip_EnableIngressPortFiltering( const uint8 CtrlIndex, boolean Enable )
5162 {
5163 Std_ReturnType Status = E_OK;
5164 uint32 RegVal;
5165
5166 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5167 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
5168 #endif
5169
5170 (void)CtrlIndex;
5171
5172 /* Convert the value */
5173 RegVal = (Enable) ? (0x1UL) : (0x0UL);
5174
5175 /* write the PIPFCR[EN] bit */
5176 IP_NETC__ENETC0_PORT->PIPFCR = RegVal;
5177
5178 return Status;
5179 }
5180
5181 /* inline function for filling in Access Keye data in function Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff() */
5182 static inline Netc_Eth_Ip_StatusType FillInAccessKeyeData(const Netc_Eth_Ip_AccessMethodType accessMethod, const volatile uint32 *pAccessKey)
5183 {
5184 uint8 ItemIdx;
5185 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
5186
5187 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26();
5188 switch (accessMethod)
5189 {
5190 case NETC_ETH_ENTRY_ID_MATCH:
5191 /* fill in Entry_ID field */
5192 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = pAccessKey[0U];
5193 break;
5194 case NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH:
5195 /* Not Applicable for Ingress Port Filter table*/
5196 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
5197 break;
5198 case NETC_ETH_SEARCH_METHOD:
5199 /* fill in Resume_Entry_ID field */
5200 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = pAccessKey[0U];
5201 break;
5202 case NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH:
5203 /* fill in keye_data field */
5204 for (ItemIdx = 1U; ItemIdx <= NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN; ItemIdx++)
5205 {
5206 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ItemIdx] = pAccessKey[ItemIdx - 1U];
5207 }
5208 break;
5209 default:
5210 /* Not Applicable for Ingress Port Filter table*/
5211 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
5212 break;
5213 }
5214 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26();
5215
5216 return status;
5217 }
5218
5219 /*FUNCTION**********************************************************************
5220 *
5221 * Function Name : Netc_Eth_Ip_DumpErrorCapture
5222 * Description : Function used for getting statistics over an error reported by the Event collector interrupt
5223 * Prerequisites: Allocate an array of Netc_Eth_Ip_ErrorCaptureRegisterInformation with a length equal to
5224 * NETC_ETH_IP_MAX_UNCORRECTABLE_ERROR_REPORTING_STATISTICS_LENGTH or
5225 * NETC_ETH_IP_MAX_CORRECTABLE_ERROR_REPORTING_STATISTICS_LENGTH or sum of them in case both uncorrectable and correctable errors are reported
5226 * for the function.
5227 * implements Netc_Eth_Ip_DumpErrorCapture_Activity
5228 *END**************************************************************************/
5229 void Netc_Eth_Ip_DumpErrorCapture ( const uint8 ctrlIdx,
5230 const Netc_Eth_Ip_PcieFunction function,
5231 uint8 *numberOfRegisters,
5232 uint8 siIndex,
5233 Netc_Eth_Ip_ErrorCaptureRegisterInformation* Buffers[])
5234 {
5235 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5236 DevAssert(numberOfRegisters != NULL_PTR);
5237 DevAssert(Netc_Eth_Ip_apxState[ctrlIdx]->SiType == NETC_ETH_IP_PHYSICAL_SI);
5238 #endif
5239 uint8 countRegisters = 0U;
5240 uint32 sbStatus = 0U;
5241
5242 switch (function)
5243 {
5244 case EMDIO:
5245 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5246 {
5247 /*This is the EMDIO uncorrectable non-fatal integrity error status register*/
5248 if (Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *)&(((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUNIESR)))
5249 {
5250 if (Buffers[countRegisters] != NULL_PTR)
5251 {
5252 Buffers[countRegisters]->RegName = EMDIOUNIESR;
5253 Buffers[countRegisters]->RegRawValueLow = ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUNIESR;
5254 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5255 countRegisters++;
5256 }
5257 }
5258 /* EMDIO system bus error status register. */
5259 if (Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUFSBESR)))
5260 {
5261 if (Buffers[countRegisters] != NULL_PTR)
5262 {
5263 /* EMDIO system bus error. */
5264 Buffers[countRegisters]->RegName = EMDIOUFSBESR;
5265 Buffers[countRegisters]->RegRawValueLow = ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUFSBESR;
5266 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5267 countRegisters++;
5268 }
5269 }
5270 }
5271 *numberOfRegisters = countRegisters;
5272 break;
5273
5274 case SWITCH:
5275 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerCorrectableErrEnabled)
5276 {
5277 /* Internal memory single bit ECC error*/
5278 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->CMESR)))
5279 {
5280 if (Buffers[countRegisters] != NULL_PTR)
5281 {
5282 /* correctable memory error */
5283 Buffers[countRegisters]->RegName = CMESR;
5284 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->CMESR;
5285 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5286 countRegisters++;
5287 }
5288 }
5289 }
5290
5291 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5292 {
5293 /* Switch system bus error.*/
5294 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__SW0_COMMON->UNSBESR)))
5295 {
5296 if (Buffers[countRegisters] != NULL_PTR)
5297 {
5298 Buffers[countRegisters]->RegName = UNSBESR;
5299 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNSBESR;
5300 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5301 countRegisters++;
5302 }
5303 if (Buffers[countRegisters] != NULL_PTR)
5304 {
5305 /* Indicates how many system bus error events have been encountered. UNSBESR[SB_ID] indicates the last source*/
5306 Buffers[countRegisters]->RegName = UNSBECTR;
5307 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNSBECTR;
5308 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5309 countRegisters++;
5310 }
5311 }
5312
5313 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__SW0_COMMON->UNMESR0)))
5314 {
5315 if (Buffers[countRegisters] != NULL_PTR)
5316 {
5317 /* Memory ID + Syndrome*/
5318 Buffers[countRegisters]->RegName = UNMESR0;
5319 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNMESR0;
5320 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5321 countRegisters++;
5322 }
5323 if (Buffers[countRegisters] != NULL_PTR)
5324 {
5325 /* Address information (row) of last ECC event.*/
5326 Buffers[countRegisters]->RegName = UNMESR1;
5327 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNMESR1;
5328 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5329 countRegisters++;
5330 }
5331 if (Buffers[countRegisters] != NULL_PTR)
5332 {
5333 /* This is the uncorrectable non-fatal memory error count register which tracks how many events have been detected.*/
5334 Buffers[countRegisters]->RegName = UNMECTR;
5335 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNMECTR;
5336 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5337 countRegisters++;
5338 }
5339 }
5340 /* Incremented for each frame received with an error (except for undersized/fragment frame):
5341 FIFO overflow error
5342 CRC error
5343 Payload length error
5344 Jabber and oversized error
5345 Alignment error
5346 A non-fatal error has occurred in the Ethernet MAC bound to PORT0. See PMa_IEVENT for details and how to clear the event*/
5347 if((IP_NETC__SW0_COMMON->UNMACESR & (uint32)0x01) != (uint32)0U)
5348 {
5349 if (Buffers[countRegisters] != NULL_PTR)
5350 {
5351 Buffers[countRegisters]->RegName = PM0_RERR;
5352 Buffers[countRegisters]->RegRawValueLow = (uint32)(IP_NETC__SW0_ETH_MAC_PORT0->PM0_RERRN);
5353 Buffers[countRegisters]->RegRawValueHigh = (uint32)(IP_NETC__SW0_ETH_MAC_PORT0->PM0_RERRN >> 32U);
5354 countRegisters++;
5355 }
5356 if (Buffers[countRegisters] != NULL_PTR)
5357 {
5358 /* EventError.*/
5359 Buffers[countRegisters]->RegName = PM0_EVENT;
5360 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT0->PM0_IEVENT;
5361 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5362 countRegisters++;
5363 }
5364 if (Buffers[countRegisters] != NULL_PTR)
5365 {
5366 /* A count of received MAC frames / MAC frame fragments rejected due to unknown
5367 SMD value or arriving with an SMD-C when no frame is in progress.*/
5368 Buffers[countRegisters]->RegName = MAC_MERGE_MMFSECR0;
5369 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT0->MAC_MERGE_MMFSECR;
5370 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5371 countRegisters++;
5372 }
5373 if (Buffers[countRegisters] != NULL_PTR)
5374 {
5375 /* A count of MAC frames with reassembly errors.*/
5376 Buffers[countRegisters]->RegName = MAC_MERGE_MMFAECR0;
5377 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT0->MAC_MERGE_MMFAECR;
5378 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5379 countRegisters++;
5380 }
5381 }
5382 if((IP_NETC__SW0_COMMON->UNMACESR & (uint32)0x02) != (uint32)0U)
5383 {
5384 if (Buffers[countRegisters] != NULL_PTR)
5385 {
5386 Buffers[countRegisters]->RegName = PM1_RERR;
5387 Buffers[countRegisters]->RegRawValueLow = (uint32)(IP_NETC__SW0_ETH_MAC_PORT1->PM1_RERRN);
5388 Buffers[countRegisters]->RegRawValueHigh = (uint32)(IP_NETC__SW0_ETH_MAC_PORT1->PM1_RERRN >> 32U);
5389 countRegisters++;
5390 }
5391 if (Buffers[countRegisters] != NULL_PTR)
5392 {
5393 /* EventError.*/
5394 Buffers[countRegisters]->RegName = PM1_EVENT;
5395 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT1->PM1_IEVENT;
5396 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5397 countRegisters++;
5398 }
5399 if (Buffers[countRegisters] != NULL_PTR)
5400 {
5401 /* A count of received MAC frames / MAC frame fragments rejected due to unknown
5402 SMD value or arriving with an SMD-C when no frame is in progress.*/
5403 Buffers[countRegisters]->RegName = MAC_MERGE_MMFSECR1;
5404 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT1->MAC_MERGE_MMFSECR;
5405 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5406 countRegisters++;
5407 }
5408 if (Buffers[countRegisters] != NULL_PTR)
5409 {
5410 /* A count of MAC frames with reassembly errors.*/
5411 Buffers[countRegisters]->RegName = MAC_MERGE_MMFAECR1;
5412 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT1->MAC_MERGE_MMFAECR;
5413 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5414 countRegisters++;
5415 }
5416 }
5417 /* Integrity fault*/
5418 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->UNIESR)))
5419 {
5420 if (Buffers[countRegisters] != NULL_PTR)
5421 {
5422 Buffers[countRegisters]->RegName = UNIESR;
5423 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNIESR;
5424 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5425 countRegisters++;
5426 }
5427 /* Indicates the number of non-fatal integrity faults detected which includes internal FCS and parity errors.*/
5428 if (Buffers[countRegisters] != NULL_PTR)
5429 {
5430 Buffers[countRegisters]->RegName = UNIECTR;
5431 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNIECTR;
5432 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5433 countRegisters++;
5434 }
5435 }
5436 /* Fatal system bus error status register. */
5437 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->UFSBESR)))
5438 {
5439 if (Buffers[countRegisters] != NULL_PTR)
5440 {
5441 Buffers[countRegisters]->RegName = UFSBESR;
5442 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFSBESR;
5443 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5444 countRegisters++;
5445 }
5446 }
5447 /* Uncorrectable fatal memory error status register 0.*/
5448 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->UFMESR0)))
5449 {
5450 if (Buffers[countRegisters] != NULL_PTR)
5451 {
5452 Buffers[countRegisters]->RegName = UFMESR0;
5453 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFMESR0;
5454 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5455 countRegisters++;
5456 }
5457 if (Buffers[countRegisters] != NULL_PTR)
5458 {
5459 Buffers[countRegisters]->RegName = UFMESR1;
5460 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFMESR1;
5461 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5462 countRegisters++;
5463 }
5464 }
5465 /* Fatal integrity error status register. */
5466 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__SW0_COMMON->UFIESR)))
5467 {
5468 if (Buffers[countRegisters] != NULL_PTR)
5469 {
5470 Buffers[countRegisters]->RegName = UFIESR;
5471 Buffers[countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFIESR;
5472 Buffers[countRegisters]->RegRawValueHigh = 0U;
5473 countRegisters++;
5474 }
5475 }
5476 }
5477 /* Return the value of the registers that have been written */
5478 *numberOfRegisters = countRegisters;
5479
5480 break;
5481
5482 case TIMER:
5483 /* timer system bus error. */
5484 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5485 {
5486 if (Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(((IP_NETC__TMR0_GLOBAL->ERROR).TIMER).TUFSBESR )))
5487 {
5488 if (Buffers[countRegisters] != NULL_PTR)
5489 {
5490 Buffers[countRegisters]->RegName = TUFSBESR;
5491 Buffers[countRegisters]->RegRawValueLow = ((IP_NETC__TMR0_GLOBAL->ERROR).TIMER).TUFSBESR;
5492 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5493 countRegisters++;
5494 }
5495 }
5496 }
5497 *numberOfRegisters = countRegisters;
5498 break;
5499
5500 case ENETC:
5501 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerCorrectableErrEnabled)
5502 {
5503 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->CMESR)))
5504 {
5505 if (Buffers[countRegisters] != NULL_PTR)
5506 {
5507 /* correctable memory error */
5508 Buffers[countRegisters]->RegName = CMESR;
5509 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->CMESR;
5510 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5511 countRegisters++;
5512 }
5513 }
5514 }
5515
5516 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5517 {
5518 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UNMESR0)))
5519 {
5520 if (Buffers[countRegisters] != NULL_PTR)
5521 {
5522 /* Memory ID + Syndrome*/
5523 Buffers[countRegisters]->RegName = UNMESR0;
5524 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNMESR0;
5525 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5526 countRegisters++;
5527 }
5528 if (Buffers[countRegisters] != NULL_PTR)
5529 {
5530 /* Address information (row) of last ECC event.*/
5531 Buffers[countRegisters]->RegName = UNMESR1;
5532 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNMESR1;
5533 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5534 countRegisters++;
5535 }
5536 if (Buffers[countRegisters] != NULL_PTR)
5537 {
5538 /* This is the uncorrectable non-fatal memory error count register which tracks how many events have been detected.*/
5539 Buffers[countRegisters]->RegName = UNMECTR;
5540 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNMECTR;
5541 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5542 countRegisters++;
5543 }
5544 }
5545
5546 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UNIESR)))
5547 {
5548 if (Buffers[countRegisters] != NULL_PTR)
5549 {
5550 Buffers[countRegisters]->RegName = UNIESR;
5551 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNIESR;
5552 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5553 countRegisters++;
5554 }
5555 if (Buffers[countRegisters] != NULL_PTR)
5556 {
5557 Buffers[countRegisters]->RegName = UNIECTR;
5558 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNIECTR;
5559 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5560 countRegisters++;
5561 }
5562 }
5563
5564 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UFMESR0)))
5565 {
5566 if (Buffers[countRegisters] != NULL_PTR)
5567 {
5568 Buffers[countRegisters]->RegName = UFMESR0;
5569 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UFMESR0;
5570 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5571 countRegisters++;
5572 }
5573 if (Buffers[countRegisters] != NULL_PTR)
5574 {
5575 Buffers[countRegisters]->RegName = UFMESR1;
5576 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UFMESR1;
5577 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5578 countRegisters++;
5579 }
5580 }
5581
5582 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UFIESR)))
5583 {
5584 if (Buffers[countRegisters] != NULL_PTR)
5585 {
5586 Buffers[countRegisters]->RegName = UFIESR;
5587 Buffers[countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UFIESR;
5588 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5589 countRegisters++;
5590 }
5591 }
5592 }
5593 *numberOfRegisters = countRegisters;
5594 break;
5595
5596 case PSI:
5597 case VSI:
5598 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5599 DevAssert(siIndex < 8U);
5600 #endif
5601 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5602 {
5603 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(netcSIsBase[siIndex]->SIUPESR)))
5604 {
5605 if (Buffers[countRegisters] != NULL_PTR)
5606 {
5607 Buffers[countRegisters]->RegName = SIUPESR;
5608 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUPESR;
5609 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5610 countRegisters++;
5611 }
5612 if (Buffers[countRegisters] != NULL_PTR)
5613 {
5614 Buffers[countRegisters]->RegName = SIUPECTR;
5615 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUPECTR;
5616 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5617 countRegisters++;
5618 }
5619 }
5620 /* Multi-bit ECC error. */
5621 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(netcSIsBase[siIndex]->SIUNMESR0)))
5622 {
5623 if (Buffers[countRegisters] != NULL_PTR)
5624 {
5625 Buffers[countRegisters]->RegName = SIUNMESR0;
5626 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUNMESR0;
5627 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5628 countRegisters++;
5629 }
5630 if (Buffers[countRegisters] != NULL_PTR)
5631 {
5632 Buffers[countRegisters]->RegName = SIUNMESR1;
5633 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUNMESR1;
5634 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5635 countRegisters++;
5636 }
5637 if (Buffers[countRegisters] != NULL_PTR)
5638 {
5639 Buffers[countRegisters]->RegName = SIUNMECTR;
5640 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUNMECTR;
5641 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5642 countRegisters++;
5643 }
5644 }
5645 /* Fatal Multi-bit ECC error. */
5646 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(netcSIsBase[siIndex]->SIUFMESR0)))
5647 {
5648 if (Buffers[countRegisters] != NULL_PTR)
5649 {
5650 Buffers[countRegisters]->RegName = SIUFMESR0;
5651 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFMESR0;
5652 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5653 countRegisters++;
5654 }
5655 if (Buffers[countRegisters] != NULL_PTR)
5656 {
5657 Buffers[countRegisters]->RegName = SIUFMESR1;
5658 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFMESR1;
5659 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5660 countRegisters++;
5661 }
5662 }
5663
5664 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(netcSIsBase[siIndex]->SIUFSBESR)))
5665 {
5666 if (Buffers[countRegisters] != NULL_PTR)
5667 {
5668 Buffers[countRegisters]->RegName = SIUFSBESR;
5669 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFSBESR;
5670 Buffers[countRegisters]->RegRawValueHigh = 0U;
5671 countRegisters++;
5672 }
5673 for (uint8 idx = 0U; idx < Netc_Eth_Ip_apxState[ctrlIdx]->SIGeneralConfig[siIndex]->NumberOfTxBDR; idx++)
5674 {
5675 /*A system bus error has occurred during one or more transactions related to this transmit ring, including possibly
5676 the transmit BD writeback entry itself. To avoid the possibility of referencing unreliable
5677 BD writeback contents,
5678 See error detect register SIUNSBESR/SIUFSBESR for more information. Write 1 to clear.*/
5679 sbStatus= netcSIsBase[siIndex]->BDR_NUM[idx].TBSR;
5680
5681 if ((sbStatus & (uint32)0x00010000) != 0U)
5682 {
5683 sbStatus &= ~((uint32)0x00010000);
5684 netcSIsBase[siIndex]->BDR_NUM[idx].TBSR = sbStatus;
5685 if (Buffers[countRegisters] != NULL_PTR)
5686 {
5687 Buffers[countRegisters]->RegName = TBCIR;
5688 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->BDR_NUM[idx].TBCIR;
5689 /* save also the current BDR with error */
5690 Buffers[countRegisters]->RegRawValueHigh = (uint32)idx;
5691 countRegisters++;
5692 }
5693 }
5694 }
5695 for (uint8 idx = 0U; idx < Netc_Eth_Ip_apxState[ctrlIdx]->SIGeneralConfig[siIndex]->NumberOfRxBDR; idx++)
5696 {
5697 sbStatus= netcSIsBase[siIndex]->BDR_NUM[idx].RBSR;
5698 if ((sbStatus & (uint32)0x00010000) != 0U)
5699 {
5700 sbStatus &= ~((uint32)0x00010000);
5701 netcSIsBase[siIndex]->BDR_NUM[idx].RBSR = sbStatus;
5702 if (Buffers[countRegisters] != NULL_PTR)
5703 {
5704 Buffers[countRegisters]->RegName = RBPIR;
5705 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->BDR_NUM[idx].RBPIR;
5706 /* save also the current BDR with error */
5707 Buffers[countRegisters]->RegRawValueHigh = (uint32)idx;
5708 countRegisters++;
5709 }
5710 }
5711 }
5712
5713 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *) &(netcSIsBase[siIndex]->SIUFIESR)))
5714 {
5715 if (Buffers[countRegisters] != NULL_PTR)
5716 {
5717 Buffers[countRegisters]->RegName = SIUFIESR;
5718 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFIESR;
5719 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5720 countRegisters++;
5721 }
5722 }
5723 }
5724 }
5725 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerCorrectableErrEnabled)
5726 {
5727 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(netcSIsBase[siIndex]->SICMESR)))
5728 {
5729 if (Buffers[countRegisters] != NULL_PTR)
5730 {
5731 Buffers[countRegisters]->RegName = SICMESR;
5732 Buffers[countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SICMESR;
5733 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5734 countRegisters++;
5735 }
5736 }
5737 }
5738 *numberOfRegisters = countRegisters;
5739 break;
5740
5741 default:
5742 *numberOfRegisters = countRegisters;
5743 break;
5744 }
5745 }
5746 /*FUNCTION**********************************************************************
5747 * Function Name : Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff
5748 * Description : Internal function for initializing the Ingress Port Filter Table Request Data Buffer.
5749 *
5750 *END**************************************************************************/
5751 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff( uint32 ActionsData,
5752 const volatile uint32 *pAccessKey,
5753 const Netc_Eth_Ip_IngressPortFilterCfgeDataType *pCfgeData,
5754 Netc_Eth_Ip_AccessMethodType accessMethod
5755 )
5756 {
5757 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
5758
5759 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
5760 /* ------initialize the table request data buffer------ */
5761 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
5762
5763 /* initialize ACCESS_KEY */
5764 status = FillInAccessKeyeData(accessMethod, pAccessKey);
5765
5766 /* initialize CFGE_DATA. This portion is present only for commands which perform an update or add. */
5767 if (pCfgeData != NULL_PTR)
5768 {
5769
5770 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_INGRESSPORTFILTER_CFGE_CONFIG_FIELD] = (NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_IPV(pCfgeData->CfgeIpv) \
5771 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_OIPV(pCfgeData->CfgeOverrideIpv ? 1U : 0U) \
5772 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_DR(pCfgeData->CfgeDr) \
5773 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_ODR(pCfgeData->CfgeOverrideDr ? 1U : 0U) \
5774 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTFA(pCfgeData->CfgeFilterForwardingAction) \
5775 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_WOLTE(pCfgeData->CfgeWakeOnLanTriggerEnable ? 1U : 0U) \
5776 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTA(pCfgeData->CfgeFilterAction) \
5777 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_RPR(pCfgeData->CfgeRelativePrecedentResolution));
5778 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_INGRESSPORTFILTER_CFGE_FLTATGT_FIELD] = pCfgeData->CfgeTargetForSelectedFilterAction;
5779
5780 }
5781 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
5782
5783 return status;
5784 }
5785
5786 /*FUNCTION**********************************************************************
5787 *
5788 * Function Name : Netc_Eth_Ip_AddIngressPortFilterTableEntry
5789 * Description : Ethernet adds Ingress Port Filter table entry function.
5790 * implements Netc_Eth_Ip_AddIngressPortFilterTableEntry_Activity
5791 *END**************************************************************************/
5792 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddIngressPortFilterTableEntry( uint8 CtrlIndex,
5793 uint32 *MatchedEntries,
5794 Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry
5795 )
5796 {
5797 Netc_Eth_Ip_StatusType status;
5798 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData;
5799 uint32 ActionsData;
5800 uint8 ByteIdx;
5801 uint8 CfgeDataIdx;
5802 uint8 PayloadIdx;
5803
5804 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5805 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
5806 DevAssert(MatchedEntries != NULL_PTR);
5807 DevAssert(IngressPortFilterTableEntry != NULL_PTR);
5808 #endif
5809
5810 /* clear the variable MatchedEntries first */
5811 *MatchedEntries = 0U;
5812
5813 /* set STSEU and CFGEU flag */
5814 ActionsData = (NETC_ETH_IP_IPFTABLE_REQFMT_ACTIONS_FIELD_STSEU(1U) | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(1U));
5815
5816 /* inialize KEYE_DATA */
5817 IPFKeyeData[0U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePrecedence;
5818 IPFKeyeData[2U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask) << NETC_ETH_IP_16BIT_SHIFT) \
5819 | IngressPortFilterTableEntry->IngressPortFilterkeyeData.keyeFrmAttributeFlags;
5820 IPFKeyeData[3U] = NETC_ETH_IP_IPFTABLE_KEYE_DATA_DSCPMASK(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask) \
5821 | NETC_ETH_IP_IPFTABLE_KEYE_DATA_DIFFSCP(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint);
5822 IPFKeyeData[4U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask) << NETC_ETH_IP_16BIT_SHIFT) \
5823 | (IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation << NETC_ETH_IP_8BIT_SHIFT); /* big endian for TCI */
5824 IPFKeyeData[5U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[1U]) << NETC_ETH_IP_8BIT_SHIFT) \
5825 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[2U]) << NETC_ETH_IP_16BIT_SHIFT) \
5826 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[3U]) << NETC_ETH_IP_24BIT_SHIFT);
5827 IPFKeyeData[6U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[4U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[5U]) << NETC_ETH_IP_8BIT_SHIFT) \
5828 | (((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[1U]) << NETC_ETH_IP_8BIT_SHIFT)) << NETC_ETH_IP_16BIT_SHIFT);
5829 IPFKeyeData[7U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[2U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[3U]) << NETC_ETH_IP_8BIT_SHIFT) \
5830 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[4U]) << NETC_ETH_IP_16BIT_SHIFT) \
5831 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[5U]) << NETC_ETH_IP_24BIT_SHIFT);
5832 IPFKeyeData[8U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[1U]) << NETC_ETH_IP_8BIT_SHIFT) \
5833 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[2U]) << NETC_ETH_IP_16BIT_SHIFT) \
5834 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[3U]) << NETC_ETH_IP_24BIT_SHIFT);
5835 IPFKeyeData[9U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[4U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[5U]) << NETC_ETH_IP_8BIT_SHIFT) \
5836 | (((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[1U]) << NETC_ETH_IP_8BIT_SHIFT)) << NETC_ETH_IP_16BIT_SHIFT);
5837 IPFKeyeData[10U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[2U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[3U]) << NETC_ETH_IP_8BIT_SHIFT) \
5838 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[4U]) << NETC_ETH_IP_16BIT_SHIFT) \
5839 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[5U]) << NETC_ETH_IP_24BIT_SHIFT);
5840 IPFKeyeData[11U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask) << NETC_ETH_IP_16BIT_SHIFT) \
5841 | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation;
5842 IPFKeyeData[12U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask) << NETC_ETH_IP_16BIT_SHIFT) \
5843 | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask;
5844 IPFKeyeData[13U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocolMask) << NETC_ETH_IP_8BIT_SHIFT) | (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocol);
5845 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5846 {
5847 IPFKeyeData[ByteIdx + 17U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddress[ByteIdx];
5848 }
5849 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5850 {
5851 IPFKeyeData[ByteIdx + 23U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddressMask[ByteIdx];
5852 }
5853 IPFKeyeData[27U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePortMask) << NETC_ETH_IP_16BIT_SHIFT) | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePort;
5854 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5855 {
5856 IPFKeyeData[ByteIdx + 29U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddress[ByteIdx];
5857 }
5858 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5859 {
5860 IPFKeyeData[ByteIdx + 35U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[ByteIdx];
5861 }
5862 IPFKeyeData[39U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPortMask) << NETC_ETH_IP_16BIT_SHIFT) | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPort;
5863
5864 CfgeDataIdx = 0U;
5865 PayloadIdx = 0U;
5866 for (ByteIdx = 0U; ByteIdx < 12U; ByteIdx++)
5867 {
5868 IPFKeyeData[CfgeDataIdx + 41U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx]) \
5869 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx]) << NETC_ETH_IP_8BIT_SHIFT) \
5870 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx + 1U]) << NETC_ETH_IP_16BIT_SHIFT) \
5871 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx + 1U]) << NETC_ETH_IP_24BIT_SHIFT);
5872 PayloadIdx++;
5873 CfgeDataIdx++;
5874 }
5875
5876 /* only supports "NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH" access method */
5877 status = Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff(ActionsData, &IPFKeyeData[0U], &(IngressPortFilterTableEntry->IngressPortFilterCfgeData), NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH);
5878 if (NETC_ETH_IP_STATUS_SUCCESS == status)
5879 {
5880 /* fill in operation data for config field of Request Header*/
5881 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
5882 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
5883 OperationData.TableId = NETC_ETH_IP_INGRESS_PORT_FILTER_TABLE_ID;
5884 OperationData.AccessMethod = NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH; /* for Adding an ingress port filter entry, the Access Method should only be NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH */
5885 OperationData.Cmd = NETC_ETH_ADD_FOLLOWEDBY_QUERY_CMD; /* can only use "Add followed by a Query" command to add an ingress port filter table entry */
5886 OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
5887 OperationData.RspBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_RSPBUFFER_LEN);
5888
5889 /* send command */
5890 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
5891 #if defined(ERR_IPV_NETC_051243)
5892 #if (STD_ON == ERR_IPV_NETC_051243)
5893 /* Error code 0x8A is not a real error. check it on Errata. */
5894 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
5895 {
5896 #endif
5897 #else
5898 if (status == NETC_ETH_IP_STATUS_SUCCESS)
5899 {
5900 #endif
5901 status = NETC_ETH_IP_STATUS_SUCCESS;
5902 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
5903 /* It's an "Add followed by a Query", but even if this entry is added successfully, the MatchedEntry is still 0. So here we can not check the MatchedEntries parameter. */
5904 IngressPortFilterTableEntry->IngressPortFilterEntryID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U]; /* Get the Entry_ID from response data buffer */
5905 }
5906 }
5907 else
5908 {
5909 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
5910 }
5911
5912 return status;
5913 }
5914
5915 /* inline function for filling in part of keye data in function FillInIPFTableEntryData() */
5916 static inline void Netc_Eth_Ip_FillInKeyeDataForIPF(Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry)
5917 {
5918 uint8 ByteIdx;
5919 uint8 PayloadIdx;
5920 uint8 CfgeDataIdx;
5921
5922 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
5923 for (ByteIdx = 2U; ByteIdx < 6U; ByteIdx++)
5924 {
5925 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[12U] & NETC_ETH_IP_0XFF_MASK);
5926 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[12U] >>= NETC_ETH_IP_8BIT_SHIFT;
5927 }
5928 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
5929
5930 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[13U] & NETC_ETH_IP_0XFFFF_MASK);
5931 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[13U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
5932 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherType = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[14U] & NETC_ETH_IP_0XFFFF_MASK);
5933 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[14U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
5934 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocol = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[15U] & NETC_ETH_IP_0XFF_MASK);
5935 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocolMask = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[15U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
5936 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5937 {
5938 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddress[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 19U];
5939 }
5940 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5941 {
5942 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddressMask[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 25U];
5943 }
5944 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePort = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[29U] & NETC_ETH_IP_0XFFFF_MASK);
5945 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePortMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[29U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
5946 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5947 {
5948 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddress[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 31U];
5949 }
5950 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5951 {
5952 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 37U];
5953 }
5954 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPort = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[41U] & NETC_ETH_IP_0XFFFF_MASK);
5955 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPortMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[41U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
5956
5957 CfgeDataIdx = 0U;
5958 PayloadIdx = 0U;
5959 for (ByteIdx = 0U; ByteIdx < 12U; ByteIdx++)
5960 {
5961 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] & NETC_ETH_IP_0XFF_MASK);
5962 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx + 1U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
5963 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
5964 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx + 1U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
5965 PayloadIdx++;
5966 CfgeDataIdx++;
5967 }
5968 }
5969
5970 /* inline function for filling in IngressPortFilterTableEntry data in function Netc_Eth_Ip_QueryIngressPortFilterTableEntry() */
5971 static inline void Netc_Eth_Ip_FillInIPFTableEntryData(Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry)
5972 {
5973 uint8 ByteIdx;
5974 uint32 CfgeData;
5975
5976 /* fill in structure Netc_Eth_Ip_IngressPortFilterEntryDataType with data from response data buffer */
5977 IngressPortFilterTableEntry->IngressPortFilterEntryID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U]; /* Entry_ID */
5978
5979 /* KEYE_DATA */
5980 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePrecedence = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U] & NETC_ETH_IP_0XFFFF_MASK);
5981 IngressPortFilterTableEntry->IngressPortFilterkeyeData.keyeFrmAttributeFlags = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U] & NETC_ETH_IP_0XFFFF_MASK);
5982 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U] & NETC_ETH_IP_0XFFFF0000_MASK) >> NETC_ETH_IP_16BIT_SHIFT);
5983 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U] & NETC_ETH_IP_IPFTABLE_KEYE_DATA_DIFFSCP_MASK);
5984 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U] & NETC_ETH_IP_IPFTABLE_KEYE_DATA_DSCPMASK_MASK) \
5985 >> NETC_ETH_IP_IPFTABLE_KEYE_DATA_DSCPMASK_SHIFT);
5986 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[6U] & NETC_ETH_IP_0XFFFF_MASK);
5987 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[6U] & NETC_ETH_IP_0XFFFF0000_MASK) >> NETC_ETH_IP_16BIT_SHIFT);
5988 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
5989
5990 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
5991 {
5992 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U] & NETC_ETH_IP_0XFF_MASK);
5993 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U] >>= NETC_ETH_IP_8BIT_SHIFT;
5994 }
5995
5996 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[4U] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] & NETC_ETH_IP_0XFF_MASK);
5997 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[5U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
5998 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[0U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
5999 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[1U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
6000 for (ByteIdx = 2U; ByteIdx < 6U; ByteIdx++)
6001 {
6002 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U] & NETC_ETH_IP_0XFF_MASK);
6003 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U] >>= NETC_ETH_IP_8BIT_SHIFT;
6004 }
6005 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
6006 {
6007 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[10U] & NETC_ETH_IP_0XFF_MASK);
6008 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[10U] >>= NETC_ETH_IP_8BIT_SHIFT;
6009 }
6010 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
6011
6012 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[4U] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] & NETC_ETH_IP_0XFF_MASK);
6013 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[5U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
6014 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[0U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
6015 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[1U] = ((uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
6016
6017 Netc_Eth_Ip_FillInKeyeDataForIPF(IngressPortFilterTableEntry); /* fill in the rest part of the KEYE_DATA */
6018
6019 /* Match Count data */
6020 IngressPortFilterTableEntry->IngressPortFilterMatchCount = (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[55U]);
6021 IngressPortFilterTableEntry->IngressPortFilterMatchCount |= ((uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[56U]) << NETC_ETH_IP_32BIT_SHIFT);
6022
6023 /* CFGE_DATA */
6024 CfgeData = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[57U]; /* config field in CFGE_DATA */
6025 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeIpv = (uint8)(CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_IPV_MASK);
6026 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideIpv = (((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_OIPV_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_OIPV_SHIFT) != 0x0UL) ? TRUE : FALSE;
6027 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeDr = (uint8)((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_DR_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_DR_SHIFT);
6028 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideDr = (((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_ODR_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_ODR_SHIFT) != 0x0UL) ? TRUE : FALSE;
6029 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterForwardingAction = ((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTFA_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTFA_SHIFT);
6030 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeWakeOnLanTriggerEnable = (((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_WOLTE_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_WOLTE_SHIFT) != 0x0UL) ? TRUE : FALSE;
6031 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterAction = ((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTA_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTA_SHIFT);
6032 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeRelativePrecedentResolution = (uint8)((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_RPR_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_RPR_SHIFT);
6033 }
6034
6035 /*FUNCTION**********************************************************************
6036 *
6037 * Function Name : Netc_Eth_Ip_QueryIngressPortFilterTableEntry
6038 * Description : Ethernet querys Ingress Port Filter table entry function.
6039 * implements Netc_Eth_Ip_QueryIngressPortFilterTableEntry_Activity
6040 *END**************************************************************************/
6041 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryIngressPortFilterTableEntry( const uint8 CtrlIndex,
6042 uint32 *MatchedEntries,
6043 Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry
6044 )
6045 {
6046 Netc_Eth_Ip_StatusType status;
6047 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData;
6048 uint32 KeyeData[NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN];
6049 uint32 ActionsData;
6050
6051
6052 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6053 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
6054 DevAssert(MatchedEntries != NULL_PTR);
6055 DevAssert(IngressPortFilterTableEntry != NULL_PTR);
6056 #endif
6057
6058 /* clear the variable MatchedEntries first */
6059 *MatchedEntries = 0U;
6060
6061 /* only support "full query" */
6062 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY);
6063
6064 /* inialize KEYE_DATA with Entry_ID */
6065 KeyeData[0U] = IngressPortFilterTableEntry->IngressPortFilterEntryID;
6066
6067 status = Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff(ActionsData, &KeyeData[0U], NULL_PTR, NETC_ETH_ENTRY_ID_MATCH);
6068 if (NETC_ETH_IP_STATUS_SUCCESS == status)
6069 {
6070 /* fill in operation data for config field of Request Header*/
6071 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
6072 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
6073 OperationData.TableId = NETC_ETH_IP_INGRESS_PORT_FILTER_TABLE_ID;
6074 OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
6075 OperationData.Cmd = NETC_ETH_QUERY_CMD;
6076 OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
6077 OperationData.RspBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_RSPBUFFER_LEN);
6078
6079 /* send command */
6080 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
6081 #if defined(ERR_IPV_NETC_051243)
6082 #if (STD_ON == ERR_IPV_NETC_051243)
6083 /* Error code 0x8A is not a real error. check it on Errata. */
6084 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
6085 {
6086 #endif
6087 #else
6088 if (status == NETC_ETH_IP_STATUS_SUCCESS)
6089 {
6090 #endif
6091 status = NETC_ETH_IP_STATUS_SUCCESS;
6092 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
6093 /* if found a matched entry, then fill in the structure */
6094 if (1U == *MatchedEntries)
6095 {
6096 Netc_Eth_Ip_FillInIPFTableEntryData(IngressPortFilterTableEntry);
6097 }
6098 }
6099 }
6100 else
6101 {
6102 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
6103 }
6104
6105 return status;
6106 }
6107
6108 /*FUNCTION**********************************************************************
6109 *
6110 * Function Name : Netc_Eth_Ip_DeleteIngressPortFilterTableEntry
6111 * Description : Ethernet deletes Ingress Port Filter table entry function.
6112 * implements Netc_Eth_Ip_DeleteIngressPortFilterTableEntry_Activity
6113 *END**************************************************************************/
6114 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteIngressPortFilterTableEntry( const uint8 CtrlIndex,
6115 uint32 *MatchedEntries,
6116 uint32 IngressPortFilterEntryId
6117 )
6118 {
6119 Netc_Eth_Ip_StatusType status;
6120 NetcEth_Ip_ReqHeaderTableOperationDataType OperationData;
6121 uint32 KeyeData[1U];
6122 uint32 ActionsData = 0x0UL;
6123
6124 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6125 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
6126 DevAssert(MatchedEntries != NULL_PTR);
6127 #endif
6128
6129 /* clear the variable MatchedEntries first */
6130 *MatchedEntries = 0U;
6131
6132 /* inialize KEYE_DATA with Entry_ID */
6133 KeyeData[0U] = IngressPortFilterEntryId;
6134
6135 status = Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff(ActionsData, &KeyeData[0U], NULL_PTR, NETC_ETH_ENTRY_ID_MATCH);
6136 if (NETC_ETH_IP_STATUS_SUCCESS == status)
6137 {
6138 /* fill in operation data for config field of Request Header*/
6139 OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
6140 OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
6141 OperationData.TableId = NETC_ETH_IP_INGRESS_PORT_FILTER_TABLE_ID;
6142 OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
6143 OperationData.Cmd = NETC_ETH_DELETE_CMD;
6144 OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
6145 OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_4BYTE_LEN);
6146
6147 /* send command */
6148 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &OperationData);
6149 #if defined(ERR_IPV_NETC_051243)
6150 #if (STD_ON == ERR_IPV_NETC_051243)
6151 /* Error code 0x8A is not a real error. check it on Errata. */
6152 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
6153 {
6154 #endif
6155 #else
6156 if (status == NETC_ETH_IP_STATUS_SUCCESS)
6157 {
6158 #endif
6159 status = NETC_ETH_IP_STATUS_SUCCESS;
6160 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
6161 }
6162 }
6163 else
6164 {
6165 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
6166 }
6167
6168 return status;
6169 }
6170
6171
6172 /*FUNCTION**********************************************************************
6173 *
6174 * Function Name : Netc_Eth_Ip_GetSyncState
6175 * Description : Get Timer Syncronization state function.
6176 * implements Netc_Eth_Ip_GetSyncState_Activity
6177 *END**************************************************************************/
6178 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetSyncState( const uint8 CtrlIndex,
6179 boolean *SyncState
6180 )
6181 {
6182 static volatile uint16 PSIRspMessage;
6183 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
6184
6185 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6186 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6187 DevAssert(SyncState != NULL_PTR);
6188 #endif
6189
6190 /* If the controller is of physical type it can directly read the sync state from the register,
6191 otherwise it must use VSI to PSI messaging to request a read from the PSI */
6192 if(Netc_Eth_Ip_apxState[CtrlIndex]->SiType == NETC_ETH_IP_PHYSICAL_SI)
6193 {
6194 *SyncState = (boolean)(IP_NETC__ENETC0_SI0->SITSR & NETC_F3_SI0_SITSR_SYNC_MASK);
6195 }
6196 else
6197 {
6198 status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_GET_SYNC_STATE, NULL_PTR, (uint16 *) &PSIRspMessage);
6199 *SyncState = (boolean) PSIRspMessage;
6200 }
6201
6202 return status;
6203 }
6204
6205 /*FUNCTION**********************************************************************
6206 *
6207 * Function Name : Netc_Eth_Ip_SetSiPhysAddr
6208 * Description : Set the MAC addresses of PSI/VSIs from the PSI controller .
6209 * implements Netc_Eth_Ip_SetSiPhysAddr_Activity
6210 *END**************************************************************************/
6211 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetSiPhysAddr( const uint8 CtrlIndex,
6212 const uint8 SiId,
6213 const uint8 *MacAddr
6214 )
6215 {
6216 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
6217
6218 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6219 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
6220 DevAssert(SiId < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6221 #endif
6222
6223 /*Check if the controller is PSI. MAC changing allowed only for PSI */
6224 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
6225 {
6226 /*VSI MAC change*/
6227 if(NETC_ETH_IP_PHYSICAL_SI != Netc_Eth_Ip_apxState[SiId]->SiType)
6228 {
6229 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers. */
6230 IP_NETC__ENETC0_BASE->NUM_SI[SiId].PSIPMAR0 = (uint32)MacAddr[0U] | \
6231 ((uint32)MacAddr[1U] << 8U ) | \
6232 ((uint32)MacAddr[2U] << 16U) | \
6233 ((uint32)MacAddr[3U] << 24U);
6234 IP_NETC__ENETC0_BASE->NUM_SI[SiId].PSIPMAR1 = (uint32)MacAddr[4U] | \
6235 ((uint32)MacAddr[5U] << 8U);
6236 }
6237 else
6238 {
6239 /* For the PSI the MAC address will be configured both for the ENETC Port and for the PSI0 */
6240 /* Configure the port primary MAC address */
6241 IP_NETC__ENETC0_PORT->PMAR0 = (uint32)MacAddr[0U] | \
6242 ((uint32)MacAddr[1U] << 8U) | \
6243 ((uint32)MacAddr[2U] << 16U) | \
6244 ((uint32)MacAddr[3U] << 24U);
6245 IP_NETC__ENETC0_PORT->PMAR1 = (uint32)MacAddr[4U] | \
6246 ((uint32)MacAddr[5U] << 8U);
6247 }
6248
6249 }
6250 else
6251 {
6252 status = NETC_ETH_IP_STATUS_UNSUPPORTED;
6253 }
6254
6255
6256 return status;
6257 }
6258
6259 #define ETH_43_NETC_STOP_SEC_CODE
6260 #include "Eth_43_NETC_MemMap.h"
6261
6262 #ifdef __cplusplus
6263 }
6264 #endif
6265
6266 /** @} */
6267
