1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Netc_Eth_Ip.c
9 *
10 * @addtogroup NETC_ETH_DRIVER NETC_ETH Driver
11 * @internal
12 * @{
13 */
14
15 #ifdef __cplusplus
16 extern "C"{
17 #endif
18
19 /*==================================================================================================
20 * INCLUDE FILES
21 * 1) system and project includes
22 * 2) needed interfaces from external units
23 * 3) internal and external interfaces from this unit
24 ==================================================================================================*/
25 #include "Netc_Eth_Ip.h"
26 #include "OsIf.h" /* Used for timeouts. */
27 #include "SchM_Eth_43_NETC.h"
28
29 #if(NETC_ETH_IP_DEV_ERROR_DETECT == STD_ON)
30 #include "Devassert.h"
31 #endif
32 #if(NETC_ETH_IP_HAS_CACHE_MANAGEMENT == STD_ON)
33 #include "Cache_Ip.h"
34 #endif
35
36 /*==================================================================================================
37 * SOURCE FILE VERSION INFORMATION
38 ==================================================================================================*/
39 #define NETC_ETH_IP_VENDOR_ID_C 43
40 #define NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION_C 4
41 #define NETC_ETH_IP_AR_RELEASE_MINOR_VERSION_C 7
42 #define NETC_ETH_IP_AR_RELEASE_REVISION_VERSION_C 0
43 #define NETC_ETH_IP_SW_MAJOR_VERSION_C 2
44 #define NETC_ETH_IP_SW_MINOR_VERSION_C 0
45 #define NETC_ETH_IP_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * FILE VERSION CHECKS
49 ==================================================================================================*/
50 /* Checks against Netc_Eth_Ip.h */
51 #if (NETC_ETH_IP_VENDOR_ID_C != NETC_ETH_IP_VENDOR_ID)
52 #error "Netc_Eth_Ip.c and Netc_Eth_Ip.h have different vendor ids"
53 #endif
54 #if (( NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION) || \
55 ( NETC_ETH_IP_AR_RELEASE_MINOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MINOR_VERSION) || \
56 ( NETC_ETH_IP_AR_RELEASE_REVISION_VERSION_C != NETC_ETH_IP_AR_RELEASE_REVISION_VERSION))
57 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
58 #endif
59 #if (( NETC_ETH_IP_SW_MAJOR_VERSION_C != NETC_ETH_IP_SW_MAJOR_VERSION) || \
60 ( NETC_ETH_IP_SW_MINOR_VERSION_C != NETC_ETH_IP_SW_MINOR_VERSION) || \
61 ( NETC_ETH_IP_SW_PATCH_VERSION_C != NETC_ETH_IP_SW_PATCH_VERSION))
62 #error "Software Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
63 #endif
64
65 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
66 /* Checks against OsIf.h */
67 #if ((NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
68 (NETC_ETH_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION))
69 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and OsIf.h are different!"
70 #endif
71 #endif
72
73 /*==================================================================================================
74 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
75 ==================================================================================================*/
76
77 /*==================================================================================================
78 * LOCAL MACROS
79 ==================================================================================================*/
80 #define NETC_ETH_IP_NANO_TO_SECONDS(x) ((x)/1000000000U)
81 #define NETC_ETH_IP_GET_NANOSECONDS(x) ((uint64)(x)%1000000000ULL)
82 /*==================================================================================================
83 * LOCAL CONSTANTS
84 ==================================================================================================*/
85 /* Formula for speed: 10Mbps * (PSPEED+1) */
86 #define NETC_ETH_IP_SHAPING_PSPEED_2000MBITS (199U)
87
88 #define NETC_ETH_IP_SECONDS_LOW_MASK_U64 (0xFFFFFFFFULL)
89
90 #define NETC_ETH_IP_FATAL_ERROR (0x1u)
91 #define NETC_ETH_IP_NON_FATAL_ERROR (0x2u)
92 #define NETC_ETH_IP_CORRECTABLE_ERROR (0x4u)
93 #define NETC_ETH_IP_PSI0_FUNCTION_INDEX (4u)
94 #define NETC_ETH_IP_CLEAR_ERROR_STATUS_MASK (0x80000000U)
95
96 #define NETC_ETH_IP_UCORR_STATUS_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK)
97 #define NETC_ETH_IP_CORR_STATUS_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK)
98 #define NETC_ETH_IP_UCORR_ERR_MASK_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK)
99 #define NETC_ETH_IP_CORR_ERR_MASK_BIT ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK)
100 #define NETC_ETH_IP_UCORR_ERR_MASK_SHIFT (NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT)
101 #define NETC_ETH_IP_CORR_ERR_MASK_SHIFT (NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT)
102 #define NETC_ETH_IP_UCORR_SEV_MASK ((uint32)NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK)
103 #define NETC_ETH_IP_AER_ROOT_CLEAR_STATUS_MASK ((uint32)(0x7F))
104
105 /*==================================================================================================
106 * LOCAL VARIABLES
107 ==================================================================================================*/
108
109 #if defined(ERR_IPV_NETC_051587)
110 #if (STD_ON == ERR_IPV_NETC_051587)
111 static boolean Netc_Eth_Ip_TGSAdminListRegistered;
112 #endif
113 #endif
114
115 /*==================================================================================================
116 * GLOBAL CONSTANTS
117 ==================================================================================================*/
118 #define ETH_43_NETC_START_SEC_VAR_INIT_UNSPECIFIED
119 #include "Eth_43_NETC_MemMap.h"
120 extern Netc_Eth_Ip_SiBaseType *netcSIsBase[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
121 extern Netc_Eth_Ip_VfBaseType *netcVFBase[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
122 extern Netc_Eth_Ip_PCIeBaseType *netcPCIePFBase[FEATURE_NETC_NUMBER_OF_FUNC];
123 #define ETH_43_NETC_STOP_SEC_VAR_INIT_UNSPECIFIED
124 #include "Eth_43_NETC_MemMap.h"
125
126 #define ETH_43_NETC_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
127 #include "Eth_43_NETC_MemMap.h"
128 VAR_SEC_NOCACHE(MACFilterHashTableAddrs) extern Netc_Eth_Ip_MACFilterHashTableEntryType *MACFilterHashTableAddrs[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
129
130 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
131 #include "Eth_43_NETC_MemMap.h"
132
133 #if ((NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON) || (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON))
134 #define ETH_43_NETC_START_SEC_CONST_BOOLEAN
135 #include "Eth_43_NETC_MemMap.h"
136
137 #if (NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
138 /** @brief Table storing information related to the method of Tx Data Buffers Management.*/
139 static const boolean Netc_Eth_Ip_ControllerHasExternalTxBufferManagement[FEATURE_NETC_ETH_NUMBER_OF_CTRLS] = NETC_ETH_IP_INST_HAS_EXTERNAL_TX_BUFFERS;
140 #endif
141
142 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
143 /** @brief Table storing information related to the method of Rx Data Buffers Management.*/
144 static const boolean Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[FEATURE_NETC_ETH_NUMBER_OF_CTRLS] = NETC_ETH_IP_INST_HAS_EXTERNAL_RX_BUFFERS;
145 #endif
146
147 #define ETH_43_NETC_STOP_SEC_CONST_BOOLEAN
148 #include "Eth_43_NETC_MemMap.h"
149
150 #endif /* ((NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON) || (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)) */
151 /*==================================================================================================
152 * GLOBAL VARIABLES
153 ==================================================================================================*/
154
155 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
156 #ifdef NETC_ETH_0_USED
157 /** @brief Store timestamp information of transmitted frames. */
158 extern volatile Netc_Eth_Ip_TxManagementInfoType Netc_Eth_Ip_TxManagementInfoBuff[NETC_ETH_IP_NUM_OF_PHYSICAL_CTRLS][NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR / NETC_ETH_IP_PRODUCER_INCR];
159 extern volatile Netc_Eth_Ip_TxTimestampInfoType Netc_Eth_Ip_TxTimestampInfoBuff[NETC_ETH_IP_NUM_OF_PHYSICAL_CTRLS][NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR / NETC_ETH_IP_PRODUCER_INCR];
160 #endif /* NETC_ETH_0_USED */
161
162 #define ETH_43_NETC_START_SEC_VAR_CLEARED_32
163 #include "Eth_43_NETC_MemMap.h"
164 #ifdef NETC_ETH_0_USED
165 /** @brief Store timestamp information of transmitted frames. */
166
167 static uint32 TxTimestampInfoBuffIdx = 0U;
168
169 #endif /* NETC_ETH_0_USED */
170
171 static uint32 Netc_Eth_Ip_RxTimestampID = (uint32)0U;
172
173 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_32
174 #include "Eth_43_NETC_MemMap.h"
175
176 /** @brief Store timestamp information of received frames. */
177 /** TODO: get the maximum of descr between variants */
178 extern volatile Netc_Eth_Ip_RxTimestampInfoType Netc_Eth_Ip_RxTimestampInfoBuff[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_RXRINGS][NETC_ETH_IP_MAX_NUMBER_OF_RXDESCRIPTORS];
179 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
180
181 #define ETH_43_NETC_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
182 #include "Eth_43_NETC_MemMap.h"
183
184 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
185 #if (NETC_ETH_IP_FILL_LEVEL_API_ENABLE == STD_ON)
186 /** @brief Structures used to measure the usage of the FIFOs*/
187 VAR_SEC_NOCACHE(Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff) volatile uint16 Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_RXRINGS];
188 VAR_SEC_NOCACHE(Netc_Eth_Ip_Tx_FillLevelInfo) volatile Netc_Eth_Ip_FillLevelInfo Netc_Eth_Ip_Tx_FillLevelInfo[FEATURE_NETC_ETH_NUMBER_OF_CTRLS][NETC_ETH_IP_MAX_NUMBER_OF_TXRINGS];
189 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
190 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
191
192 /** @brief Pointers to NETC internal driver state for each controller(SI). */
193 VAR_SEC_NOCACHE(Netc_Eth_Ip_apxState) Netc_Eth_Ip_StateType *Netc_Eth_Ip_apxState[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
194
195 /** @brief List of Error Reporting structures that aggregate information for each Pcie function in case of an error reported to the Event Collector. EMDIO, TIMER, SWITCH, ENETC, PSI0, VSI1-7*/
196 VAR_SEC_NOCACHE(Netc_Eth_Ip_ErrorStatus) static volatile Netc_Eth_Ip_PcieFunctionErrorsReported Netc_Eth_Ip_ErrorStatus[FEATURE_NETC_NUMBER_OF_FUNC + FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS];
197
198 /* Enabled status for Time Aware Shaper for PSI */
199 VAR_SEC_NOCACHE(Netc_Eth_Ip_PortTimeAwareShaperEnabled) static boolean Netc_Eth_Ip_PortTimeAwareShaperEnabled = FALSE;
200
201 /* Table entries for Time Aware Shaping configuration */
202 VAR_SEC_NOCACHE(Netc_Eth_Ip_EthTimeGateSchedulingEntryData) static Netc_Eth_Ip_TimeGateSchedulingEntryDataType Netc_Eth_Ip_EthTimeGateSchedulingEntryData;
203
204 /* The frequency of the NETC module for computing CBS parameters */
205 VAR_SEC_NOCACHE(Netc_Eth_Ip_NetcClockFrequency) static uint32 Netc_Eth_Ip_NetcClockFrequency = 0U;
206
207 /* a 16 bytes aligned table request data buffer */
208 VAR_SEC_NOCACHE(Netc_Eth_Ip_EnetcTableDataBuffer) VAR_ALIGN(static volatile Netc_Eth_Ip_EnetcTableDataType Netc_Eth_Ip_EnetcTableDataBuffer, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
209 VAR_SEC_NOCACHE(Netc_Eth_Ip_OperationData) static VAR_ALIGN(Netc_Eth_Ip_ReqHeaderTableOperationDataType Netc_Eth_Ip_OperationData, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
210
211 VAR_SEC_NOCACHE(Netc_Eth_Ip_TableData) static VAR_ALIGN(Netc_Eth_Ip_SetMessageHeaderTableOperationDataType Netc_Eth_Ip_TableData, NETC_ETH_IP_TABLE_ALIGNED_SIZE)
212
213 /* Local copy of the pointer to the configuration data. */
214 VAR_SEC_NOCACHE(Netc_Eth_Ip_ConfigPtr) static const Netc_Eth_Ip_ConfigType * Netc_Eth_Ip_ConfigPtr[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
215
216
217
218 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
219 #include "Eth_43_NETC_MemMap.h"
220
221 #define ETH_43_NETC_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
222 #include "Eth_43_NETC_MemMap.h"
223
224 VAR_SEC_NOCACHE(Netc_Eth_Ip_RfsSetDataBuffer) static VAR_ALIGN(uint32 Netc_Eth_Ip_RfsSetDataBuffer[NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE], NETC_ETH_IP_TABLE_ALIGNED_SIZE)
225 /* Key element data for ingress port filter table */
226 VAR_SEC_NOCACHE(Netc_Eth_Ip_IPFKeyeData) static volatile VAR_ALIGN(uint32 Netc_Eth_Ip_IPFKeyeData[NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN], NETC_ETH_IP_TABLE_ALIGNED_SIZE)
227
228 #define ETH_43_NETC_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
229 #include "Eth_43_NETC_MemMap.h"
230
231 #if (NETC_ETH_IP_HAS_CACHE_MANAGEMENT == STD_ON)
232 /* FEATURE_NETC_CACHABLE_BUFFERS_LMEM and FEATURE_NETC_CACHABLE_BUFFERS_CORE are generated based on the
233 platform and the core type in case both cache IPs are supported.
234 These macros must be both defined for the driver when the cache management feature is enabled.
235 They must not be simultaneosly enabled at runtime.*/
236 #ifdef FEATURE_NETC_CACHABLE_BUFFERS_LMEM
237 #ifdef FEATURE_NETC_CACHABLE_BUFFERS_CORE
238 #define ETH_43_NETC_START_SEC_CONST_UNSPECIFIED
239 #include "Eth_43_NETC_MemMap.h"
240 #if (FEATURE_NETC_CACHABLE_BUFFERS_LMEM > 0U)
241 /** @brief Global variable which contains the type of CACHE Type used on the current platform.
242 * CACHE_IP_LMEM is using LMEM peripheral.
243 * CACHE_IP_CORE is using SCB peripheral.
244 */
245 static const Cache_Ip_Type CacheType = CACHE_IP_LMEM;
246 #elif (FEATURE_NETC_CACHABLE_BUFFERS_CORE > 0U)
247 /** @brief Global variable which contains the type of CACHE Type used on the current platform.
248 * CACHE_IP_LMEM is using LMEM peripheral.
249 * CACHE_IP_CORE is using SCB peripheral.
250 */
251 static const Cache_Ip_Type CacheType = CACHE_IP_CORE;
252 #endif
253 #define ETH_43_NETC_STOP_SEC_CONST_UNSPECIFIED
254 #include "Eth_43_NETC_MemMap.h"
255 #endif /* defined (FEATURE_NETC_CACHABLE_BUFFERS_CORE) */
256 #endif /* defined (FEATURE_NETC_CACHABLE_BUFFERS_LMEM) */
257 #endif /*NETC_HAS_CACHE_MANAGEMENT == STD_ON */
258
259 /*==================================================================================================
260 * LOCAL FUNCTION PROTOTYPES
261 ==================================================================================================*/
262 #define ETH_43_NETC_START_SEC_CODE
263 #include "Eth_43_NETC_MemMap.h"
264 /**
265 * @brief For each controller(station interface) state structure will be initialized.
266 *
267 * @param ctrlIndex
268 * @param config
269 */
270 static void Netc_Eth_Ip_InitStateStructure(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
271 /**
272 * @brief Initialize all BD rings for the current SI.
273 *
274 * @param ctrlIndex Number of the current SI.
275 * @param config General configuration of the controller.
276 */
277 static void Netc_Eth_Ip_InitTxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
278 static void Netc_Eth_Ip_InitRxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
279
280 /**
281 * @brief
282 *
283 * @param ctrlIndex
284 */
285 static void Netc_Eth_Ip_InitCBDR(uint8 ctrlIndex);
286
287
288 /**
289 * @brief
290 *
291 * @param ctrlIndex
292 * @param config General configuration of the controller.
293 */
294 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_InitSI(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
295
296 #if (NETC_ETH_MAX_NUMBER_OF_IPFTABLE_LIST > 0U)
297 /**
298 * @brief Initialize IPF table
299 *
300 * @param ctrlIndex
301 * @param config General configuration of the controller.
302 */
303 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_InitIngressPortFilterTable(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
304 /**
305 * @brief Initializing ingress port filter table entries data during ENETC init
306 *
307 * @param config General configuration of the controller.
308 * @param IPFTableListIdx
309 * @param IngressPortFilterTableEntry
310 */
311 static inline void Netc_Eth_Ip_InitIPFTableEntryData(const Netc_Eth_Ip_ConfigType * Config, uint8 IPFTableListIdx, Netc_Eth_Ip_IngressPortFilterEntryDataType *IngressPortFilterTableEntry);
312 #endif
313
314 /**
315 * @brief Local function used by Netc_Eth_Ip_EnableIrq to enable and set the configuration for interrupt.
316 * @details Number of defaults MSI entries in table for ENETC is 48.
317 *
318 * @param ctrlIndex Number of the current SI.
319 * @param config General configuration of the controller.
320 * @param msiTableConfig MSI entries
321 */
322 static inline void Netc_Eth_Ip_EnableIrq_ConfigMsiTableTx(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config, Netc_Eth_Ip_MSITable* const msiTableConfig);
323
324 /**
325 * @brief Local function used by Netc_Eth_Ip_EnableIrq to enable and set the configuration for interrupt.
326 * @details Number of defaults MSI entries in table for ENETC is 48.
327 *
328 * @param ctrlIndex Number of the current SI.
329 * @param config General configuration of the controller.
330 * @param msiTableConfig MSI entries
331 */
332 static inline void Netc_Eth_Ip_EnableIrq_ConfigMsiTableRx(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config, Netc_Eth_Ip_MSITable* const msiTableConfig);
333
334 /**
335 * @brief This function will be used to enable and set all the configuration for interrupt.
336 * @details Number of defaults MSI entries in table for ENETC is 48.
337 *
338 * @param ctrlIndex Number of the current SI.
339 * @param config General configuration of the controller.
340 */
341 static inline void Netc_Eth_Ip_EnableIrq(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
342
343 /**
344 * @brief Prepare to use a timeout.
345 *
346 * @param StartTimeOut Current value of selected counter.
347 * @param ElapsedTimeOut Reset elapsed time to 0.
348 * @param TimeoutTicksOut TimeoutUs converted from microsecond units to ticks units.
349 * @param TimeoutUs Timeout value in microsecond.
350 */
351 static inline void Netc_Eth_Ip_StartTimeOut(uint32 *StartTimeOut,
352 uint32 *ElapsedTimeOut,
353 uint32 *TimeoutTicksOut,
354 uint32 TimeoutUs);
355
356 /**
357 * @brief Checks for timeout expiration condition.
358 *
359 * @param StartTimeInOut Initial value of the counter.
360 * @param ElapsedTimeInOut Current ticks passed.
361 * @param TimeoutTicks Number of ticks after timout will be activated.
362 *
363 * @return boolean TRUE - timout activated.
364 * FALSE - timeout is not yet reached.
365 */
366 static inline boolean Netc_Eth_Ip_TimeoutExpired(uint32 *StartTimeInOut,
367 uint32 *ElapsedTimeInOut,
368 uint32 TimeoutTicks);
369 /**
370 * @brief Add MAC addr in the software table.
371 *
372 * @param CtrlIndex Index of the SI.
373 * @param HashValue Computed hash value.
374 * @param MacAddr MAC address.
375 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
376 * NETC_ETH_IP_STATUS_MAC_ADDR_TABLE_FULL - MAC table used for hash filter is full
377 */
378 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddMACFilterEntry(uint8 CtrlIndex, uint8 HashValue, const uint8 *MacAddr);
379
380 /**
381 * @brief Compute has value for MAC addr.
382 *
383 * @param MacAddr MAC address.
384 * @return uint8 Hash value for MacAddr.
385 */
386 static inline uint8 Netc_Eth_Ip_ComputeMACHashValue(const uint8 *MacAddr);
387
388 /**
389 * @brief Send message from the VSI to PSI.
390 *
391 * @param VsiId Index of the VSI.
392 * @param MsgAction Type of action. Description in types.
393 * @param MacAddr MAC address.
394 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
395 * NETC_ETH_IP_STATUS_ERROR - unsuccessfully operation
396 * NETC_ETH_IP_STATUS_MAC_ADDR_TABLE_FULL - MAC table used for hash filter is full
397 * NETC_ETH_IP_STATUS_TIMEOUT - Only for VSIs - the command was not processed in the allotted time
398 * NETC_ETH_IP_STATUS_MAC_ADDR_NOT_FOUND - the current destination MAC was not
399 * found in the hash filter table
400 */
401 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsiMsg(uint8 VsiId, \
402 Netc_Eth_Ip_VsiToPsiMsgActionType MsgAction, \
403 const uint8 *MacAddr, \
404 uint16 * PsiRspMessage );
405 /**
406 * @brief Remove MAC addr in the software table.
407 *
408 * @param CtrlIndex Index of the SI.
409 * @param HashValue Computed hash value.
410 * @param MacAddr MAC address.
411 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
412 * NETC_ETH_IP_STATUS_ERROR - unsuccessfully operation
413 * NETC_ETH_IP_STATUS_MAC_ADDR_NOT_FOUND - the current destination MAC was not
414 * found in the hash filter table
415 */
416 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteMACFilterEntry(const uint8 CtrlIndex, \
417 const uint8 HashValue, \
418 const uint8 *MacAddr);
419
420 /**
421 * @brief Wait until the command is send from the VSI to the PSI.
422 *
423 * @param VsiId Index of the SI.
424 * @param MsgCommandConfig Message command.
425 * @return Netc_Eth_Ip_StatusType NETC_ETH_IP_STATUS_SUCCESS - successfully operation
426 * NETC_ETH_IP_STATUS_TIMEOUT - Only for VSIs - the command was not processed in the allotted time
427 */
428 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(uint8 VsiId, const Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig, uint16 * PsiRspMessage);
429
430 /**
431 * @brief Performs a transformation to a hardware specific value which sets the
432 * packets threshold for tx colaescing interrupt.
433 * The return value is a hardware specific value which will be set in the ICTT part of the TBxICR0 register. It will be
434 * the greatest value which satisfies the following formula.
435 * PacketsThreshold >= 2 ^(TwoPow-1)
436 *
437 *
438 * @param PacketsThreshold The number of packets for coalescing interrupt.
439 * @return uint8 Hardware specific value which will be set in the ICTT part of the TBxICR0 register. It will be
440 * the greatest value which satisfies the following formula.
441 */
442 static uint8 Netc_Eth_Ip_CoalescingTxPacketsConversion (uint16 PacketsThreshold);
443
444 /**
445 * @brief Setup the PCIE Event collector Error reporting registers
446 *
447 * @param psi0Config User Configuration
448 * @return Netc_Eth_Ip_StatusType Error in case the memory access wasn't enabled beforehand.
449 */
450 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetupErrorReporting(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config);
451
452 #if (NETC_ETH_IP_NUMBER_OF_VLAN_FILTER_ENTRIES > 0U)
453 /**
454 * @brief VLAN Filter table configuration function
455 *
456 * @param[in] Config: Pointer to the configuration for initalisation
457 *
458 * @return Result of the operation
459 * @retval 0 : E_OK, success
460 * @retval 1 : E_NOT_OK, fail
461 */
462 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigVLANFilterTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
463 #endif
464
465 #if (NETC_ETH_IP_NUMBER_OF_RP_ENTRIES > 0U)
466 /**
467 * @brief Rate Policer table configuration function
468 *
469 * @param[in] Config: Pointer to the configuration for initalisation
470 *
471 * @return Result of the operation
472 * @retval 0 : E_OK, success
473 * @retval 1 : E_NOT_OK, fail
474 */
475 static Std_ReturnType Netc_Eth_Ip_ConfigRatePolicerTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
476 #endif
477
478 #if (NETC_ETH_NUMBER_OF_STREAMIDENTIFICATION_ENTRIES > 0U)
479 /**
480 * @brief IngressStreamIdentification table configuration function
481 *
482 * @param[in] Config: Pointer to the configuration of one Ethernet Switch for initalisation
483 *
484 * @return Result of the operation
485 * @retval 0 : E_OK, success
486 * @retval 1 : E_NOT_OK, fail
487 */
488 static Std_ReturnType Netc_Eth_Ip_ConfigISITable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
489 #endif
490
491 #if (NETC_ETH_NUMBER_OF_INGRESSSTREAM_ENTRIES > 0U)
492 /**
493 * @brief IngressStream table configuration function
494 *
495 * @param[in] Config: Pointer to the configuration of one Ethernet Switch for initalisation
496 *
497 * @return Result of the operation
498 * @retval 0 : E_OK, success
499 * @retval 1 : E_NOT_OK, fail
500 */
501 static Std_ReturnType Netc_Eth_Ip_ConfigIngressStreamTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
502 #endif
503
504 #if (NETC_ETH_NUMBER_OF_SGCL_ENTRIES > 0U)
505 /**
506 * @brief Stream Gate Control List configuration function
507 *
508 * @param[in] Config: Pointer to the configuration of one Ethernet Switch for initalisation
509 *
510 * @return Result of the operation
511 * @retval 0 : E_OK, success
512 * @retval 1 : E_NOT_OK, fail
513 */
514 static Std_ReturnType Netc_Eth_Ip_ConfigSGCL(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
515 #endif
516
517 #if (NETC_ETH_NUMBER_OF_SGI_ENTRIES > 0U)
518 /**
519 * @brief Stream Gate Instance configuration function
520 *
521 * @param[in] Config: Pointer to the configuration of one Ethernet Switch for initalisation
522 *
523 * @return Result of the operation
524 * @retval 0 : E_OK, success
525 * @retval 1 : E_NOT_OK, fail
526 */
527 static Std_ReturnType Netc_Eth_Ip_ConfigSGI(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config);
528 #endif
529
530 /*!
531 * @brief
532 * @details
533 *
534 * @param[in] BufferIndex
535 * @param[in] options
536 * @param[in] txBD
537 */
538 static inline void Netc_Eth_Ip_ConfigureBufferDescriptors(const uint16 BufferIndex, const Netc_Eth_Ip_TxOptionsType *options, Netc_Eth_Ip_TxBDRType *txBD);
539
540 /*!
541 * @brief : Local function used by Netc_Eth_Ip_Init
542 * @details : Function used by Netc_Eth_Ip_Init for firt step initialization
543 *
544 * @param[in] ctrlIndex controller index
545 * @param[in] config controller configuration
546 */
547 static inline void Netc_Eth_Ip_Init_FirstPart(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
548
549 /*!
550 * @brief : Local function used by Netc_Eth_Ip_Init
551 * @details : Function used by Netc_Eth_Ip_Init for second step initialization
552 *
553 * @param[in] ctrlIndex controller index
554 * @param[in] config controller configuration
555 */
556 static inline void Netc_Eth_Ip_Init_SecondPart(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
557
558
559 /*!
560 * @brief : Function for initializing NTMP table.
561 * @details : Function enables the netc controller, initializes the tables and then diasbles the netc controller
562 *
563 * @param[in] ctrlIndex controller index
564 * @param[in] config controller configuration
565 */
566 static inline void Netc_Eth_Ip_InitSI_ConfigureVSI(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
567
568 /*!
569 * @brief : Function for initializing NTMP table.
570 * @details : Function enables the netc controller, initializes the tables and then diasbles the netc controller
571 *
572 * @param[in] ctrlIndex controller index
573 * @param[in] config controller configuration
574 *
575 */
576 static inline void Netc_Eth_Ip_InitNTMPTables(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
577
578 /*!
579 * @brief : Internal function for reading the error status registers for EMDIO
580
581 * @param[in] ctrlIdx controller index
582 * @param[in] Buffers Memory location where the information will be stored
583 *
584 * @return Number of registers read.
585 */
586 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForEMDIO (const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
587
588 /*!
589 * @brief : Internal function for reading the system bus non fatal error status registers for SWITCH
590 *
591 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
592 * @param[in] Buffers Memory location where the information will be stored
593 *
594 */
595 static inline void Netc_Eth_Ip_GetSystemBusErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
596
597 /*!
598 * @brief : Internal function for reading the Uncorrectable non-fatal memory error status registers for SWITCH
599 *
600 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
601 * @param[in] Buffers Memory location where the information will be stored
602 *
603 */
604 static inline void Netc_Eth_Ip_GetMemoryErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
605
606 /*!
607 * @brief : Internal function for reading the Port0 error status registers for SWITCH
608 *
609 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
610 * @param[in] Buffers Memory location where the information will be stored
611 *
612 */
613 static inline void Netc_Eth_Ip_GetPort0ErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
614
615 /*!
616 * @brief : Internal function for reading the Port1 error status registers for SWITCH
617 *
618 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
619 * @param[in] Buffers Memory location where the information will be stored
620 *
621 */
622 static inline void Netc_Eth_Ip_GetPort1ErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
623
624 /*!
625 * @brief : Internal function for reading the uncorrectable non-fatal integrity error statistics registers for SWITCH
626 *
627 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
628 * @param[in] Buffers Memory location where the information will be stored
629 *
630 */
631 static inline void Netc_Eth_Ip_GetIntegrityFaultStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
632
633 /*!
634 * @brief : Internal function for reading the fatal error statistics registers for SWITCH
635 *
636 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
637 * @param[in] Buffers Memory location where the information will be stored
638 *
639 */
640 static inline void Netc_Eth_Ip_GetFatalErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
641
642 /*!
643 * @brief : Internal function for reading the Correctable error statistics registers for SWITCH
644 *
645 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
646 * @param[in] Buffers Memory location where the information will be stored
647 *
648 */
649 static inline void Netc_Eth_Ip_GetCorrectableErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
650
651 /*!
652 * @brief : Internal function for gathering error statistics information for SWITCH
653
654 * @param[in] ctrlIdx controller index
655 * @param[in] Buffers Memory location where the information will be stored
656 *
657 * @return Number of registers read.
658 */
659 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForSWITCH (const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
660
661 /*!
662 * @brief : Internal function for gathering error statistics information for TIMER
663 *
664 * @param[in] ctrlIdx controller index
665 * @param[in] Buffers Memory location where the information will be stored
666 *
667 * @return Number of registers read.
668 */
669 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForTIMER(const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
670
671 /*!
672 * @brief : Internal function for reading the Correctable error statistics registers for ENETC
673 *
674 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
675 * @param[in] Buffers Memory location where the information will be stored
676 *
677 */
678 static inline void Netc_Eth_Ip_GetCorrectableErrorStatisticsForENETC (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
679
680 /*!
681 * @brief : Internal function for reading the memory error statistics registers for ENETC
682 *
683 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
684 * @param[in] Buffers Memory location where the information will be stored
685 *
686 */
687 static inline void Netc_Eth_Ip_GetMemoryErrorStatisticsForENETC(uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
688
689 /*!
690 * @brief : Internal function for reading the integrity error statistics registers for ENETC
691 *
692 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
693 * @param[in] Buffers Memory location where the information will be stored
694 *
695 */
696 static inline void Netc_Eth_Ip_GetIntegrityFaultStatisticsForENETC (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
697
698 /*!
699 * @brief : nternal function for reading the fatal error statistics registers for ENETC
700 *
701 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
702 * @param[in] Buffers Memory location where the information will be stored
703 *
704 */
705 static inline void Netc_Eth_Ip_GetFatalErrorStatisticsForENETC (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
706
707 /*!
708 * @brief : Internal function for gathering error statistics information for enetc
709
710 * @param[in] ctrlIdx controller index
711 * @param[in] Buffers Memory location where the information will be stored
712 *
713 * @return Number of registers read.
714 */
715 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForENETC(const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
716
717 /*!
718 * @brief : Internal function for reading the programming error statistics registers for for a SI (siIndex).
719 *
720 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
721 * @param[in] siIndex The index of SI.
722 * @param[in] Buffers Memory location where the information will be stored
723 *
724 */
725 static inline void Netc_Eth_Ip_GetProgrammingErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
726
727 /*!
728 * @brief : Internal function for reading the MEMORY error statistics registers for for a SI (siIndex).
729 *
730 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
731 * @param[in] siIndex The index of SI.
732 * @param[in] Buffers Memory location where the information will be stored
733 *
734 */
735 static inline void Netc_Eth_Ip_GetMemoryErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
736
737 /*!
738 * @brief : Internal function for reading the FATAL MEMORY error statistics registers for for a SI (siIndex).
739 *
740 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
741 * @param[in] siIndex The index of SI.
742 * @param[in] Buffers Memory location where the information will be stored
743 *
744 */
745 static inline void Netc_Eth_Ip_GetFatalMemoryErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
746
747 /*!
748 * @brief : Internal function for reading the FATAL integrity error statistics registers for for a SI (siIndex).
749 *
750 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
751 * @param[in] siIndex The index of SI.
752 * @param[in] Buffers Memory location where the information will be stored
753 *
754 */
755 static inline void Netc_Eth_Ip_GetFatalIntegrityErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
756
757 /*!
758 * @brief : Internal function for reading the FATAL system bus error statistics registers for for a SI (siIndex).
759 *
760 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
761 * @param[in] siIndex The index of SI.
762 * @param[in] Buffers Memory location where the information will be stored
763 *
764 */
765 static inline void Netc_Eth_Ip_GetFatalSystemBusErrorStatisticsForSI (uint8 *countRegisters, const uint8 ctrlIdx, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
766
767 /*!
768 * @brief : Internal function for reading the correctable error statistics registers for for a SI (siIndex).
769 *
770 * @param[in] StartPoint The start point index of the Buffers array where the information shall be stored.
771 * @param[in] siIndex The index of SI.
772 * @param[in] Buffers Memory location where the information will be stored
773 *
774 */
775 static inline void Netc_Eth_Ip_GetCorrectableErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
776
777 /*!
778 * @brief : Internal function for gathering error statistics information for si
779
780 * @param[in] ctrlIdx controller index
781 * @param[in] siIndex The index of SI.
782 * @param[in] Buffers Memory location where the information will be stored
783 *
784 * @return Number of registers read.
785 */
786 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForSI(const uint8 ctrlIdx, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[]);
787
788 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF))
789 /*!
790 * @brief : Local fuction used by Netc_Eth_Ip_ReadFrame
791 * @details
792 * @param[in] ctrlIndex
793 * @param[in] ring
794 * @param[in] status
795 * @param[in] CurrLowTime
796 * @return VOID
797 */
798 static inline void Netc_Eth_Ip_HostReasonTimeStamp(uint8 ctrlIndex,
799 uint8 ring,
800 Netc_Eth_Ip_StatusType* status,
801 uint32 CurrLowTime
802 );
803 #endif
804
805 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT))
806 /*!
807 * @brief : Local fuction used by Netc_Eth_Ip_ReadFrame
808 * @details
809 * @param[in] ctrlIndex
810 * @param[in] ring
811 * @param[in] tagBytes
812 * @param[in] buff
813 * @return VOID
814 */
815 static inline void Netc_Eth_Ip_ReadFrame_AddCustomRxTagHeader(uint8 ctrlIndex,
816 uint8 ring,
817 const uint8* tagBytes,
818 Netc_Eth_Ip_BufferType *buff
819 );
820 #endif /* defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT) */
821
822 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON==NETC_ETH_IP_CUSTOM_TAG_SUPPORT))
823 /*!
824 * @brief : Local fuction used by Netc_Eth_Ip_ReadFrame
825 * @details
826 * @param[in] ctrlIndex
827 * @param[in] ring
828 * @param[in] tagBytes
829 * @param[in] HostReason
830 */
831 static inline void Netc_Eth_Ip_ReadFrame_CustomizedTPID(uint8 ctrlIndex,
832 uint8 ring,
833 uint8 *tagBytes,
834 uint32 HostReason
835 );
836 #endif
837
838 /*!
839 * @brief : Local fuction used by Netc_Eth_Ip_ConfigPortTimeGateScheduling function
840 * @details
841 * @param[in] RegValue
842 * @param[in] status
843 * @return VOID
844 */
845 static inline void Netc_Eth_Ip_ConfigPortTimeGateScheduling_GateControlState(uint32* const RegValue, Netc_Eth_Ip_StatusType* const status);
846
847 /*!
848 * @brief : Local fuction used by Netc_Eth_Ip_ReadFrame
849 * @details
850 * @param[in] ctrlIndex
851 * @param[in] ring
852 * @param[in] buff
853 * @return VOID
854 */
855 static inline void Netc_Eth_Ip_ReadFrame_ReturnBufferDetails(uint8 ctrlIndex,
856 uint8 ring,
857 Netc_Eth_Ip_BufferType *buff
858 );
859
860 /*!
861 * @brief : Local fuction used by Netc_Eth_Ip_EnableController
862 * @details
863 * @param[in] ctrlIndex
864 * @return VOID
865 */
866 static inline void Netc_Eth_Ip_EnableController_RxCoalescing(uint8 ctrlIndex);
867
868 /*!
869 * @brief : Local fuction used by Netc_Eth_Ip_EnableController
870 * @details
871 * @param[in] ctrlIndex
872 * @return VOID
873 */
874 static inline void Netc_Eth_Ip_EnableController_TxCoalescing(uint8 ctrlIndex);
875
876 /*!
877 * @brief : Local fuction used by Netc_Eth_Ip_SetupErrorReporting
878 * @details
879 * @param[in] ctrlIndex
880 * @return VOID
881 */
882 static inline void Netc_Eth_Ip_SetupErrorReporting_EnableUncorrectableErrors(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config);
883
884 /*!
885 * @brief : Local fuction used by Netc_Eth_Ip_SetupErrorReporting
886 * @details
887 * @param[in] ctrlIndex
888 * @return VOID
889 */
890 static inline void Netc_Eth_Ip_SetupErrorReporting_EnableCorrectableErrors(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config);
891
892 /*!
893 * @brief : Local fuction used by Netc_Eth_Ip_DeleteMACFilterEntry
894 * @details
895 * @param[in] CtrlIndex
896 * @param[in] MatchedEntry
897 * @param[in] CurrentEntry
898 * @param[in] MacAddr
899 * @return VOID
900 */
901 static inline void Netc_Eth_Ip_DeleteMACFilterEntry_MarkEntryEmpty(const uint8 CtrlIndex,
902 boolean* const MatchedEntry,
903 const uint8 CurrentEntry,
904 const uint8 *MacAddr);
905
906 /*!
907 * @brief : Internal function for processing the interrupt status for VSIx
908 * @param[in] ctrlIdx controller index
909 * @param[in] index index in the ErrorStatus structure
910 * @return VOID
911 */
912 static inline void Netc_Eth_Ip_ProcessErrorStatusForInterruptForVSIs(const uint8 ctrlIndex, const uint8 index);
913
914 /*!
915 * @brief : Internal function for processing the interrupt status for EMDIO, TIMER,SWTICH, ENETC
916 * @param[in] ctrlIdx controller index
917 * @param[in] index index in the ErrorStatus structure
918 * @return VOID
919 */
920 static inline void Netc_Eth_Ip_ProcessErrorStatusForInterruptForFunctions(const uint8 ctrlIndex, const uint8 index);
921
922 /*==================================================================================================
923 * LOCAL FUNCTIONS
924 ==================================================================================================*/
Netc_Eth_Ip_GetCurrentTick(uint8 ctrlIndex,Netc_Eth_Ip_TimeType * TimePtr)925 static void Netc_Eth_Ip_GetCurrentTick(uint8 ctrlIndex, Netc_Eth_Ip_TimeType *TimePtr)
926 {
927 /* Read the low register, then immediately read the high register to get a synchronised 64-bit time value */
928 (*TimePtr).nanosecondsL = (uint32)(netcSIsBase[ctrlIndex]->SICTR0);
929 (*TimePtr).nanosecondsH = (uint32)(netcSIsBase[ctrlIndex]->SICTR1);
930 }
931
Netc_Eth_Ip_StartTimeOut(uint32 * StartTimeOut,uint32 * ElapsedTimeOut,uint32 * TimeoutTicksOut,uint32 TimeoutUs)932 static inline void Netc_Eth_Ip_StartTimeOut(uint32 *StartTimeOut,
933 uint32 *ElapsedTimeOut,
934 uint32 *TimeoutTicksOut,
935 uint32 TimeoutUs)
936 {
937 *StartTimeOut = OsIf_GetCounter(NETC_ETH_IP_TIMEOUT_TYPE);
938 *ElapsedTimeOut = 0U;
939 *TimeoutTicksOut = OsIf_MicrosToTicks(TimeoutUs, NETC_ETH_IP_TIMEOUT_TYPE);
940 }
941
Netc_Eth_Ip_TimeoutExpired(uint32 * StartTimeInOut,uint32 * ElapsedTimeInOut,uint32 TimeoutTicks)942 static inline boolean Netc_Eth_Ip_TimeoutExpired(uint32 *StartTimeInOut,
943 uint32 *ElapsedTimeInOut,
944 uint32 TimeoutTicks)
945 {
946 *ElapsedTimeInOut += OsIf_GetElapsed(StartTimeInOut, NETC_ETH_IP_TIMEOUT_TYPE);
947
948 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE);
949 }
950
Netc_Eth_Ip_InitStateStructure(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)951 static void Netc_Eth_Ip_InitStateStructure(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
952 {
953 uint8 u8RxBDIdx;
954 uint8 u8TxBDIdx;
955 uint32 currBDIdx;
956
957 for (u8RxBDIdx = 0U; u8RxBDIdx < (*config->siConfig).NumberOfRxBDR; u8RxBDIdx++)
958 {
959 config->stateStructure->RxCurrentDesc[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
960 config->stateStructure->FirstRxRingDescAddr[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
961 config->stateStructure->RxRingSize[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].ringSize;
962 config->stateStructure->rxCurrentIndex[u8RxBDIdx] = 0U;
963 config->stateStructure->FirstRxDataBufferAddr[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].Buffer;
964 config->stateStructure->RxDataBuffMaxLenAddr[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].maxBuffLen;
965 config->stateStructure->RxCallback[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].Callback;
966 /* If at least one controller has the Rx Interrupt coalesing enabled, then set the right threshold for all
967 (0 if it is disabled, the configurated value if it is enabled).*/
968 config->stateStructure->RxTimerThreshold[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].TimerThreshold;
969 config->stateStructure->RxPacketsThreshold[u8RxBDIdx] = (*config->paCtrlRxRingConfig)[u8RxBDIdx].PacketsThreshold;
970 }
971
972 for (u8TxBDIdx = 0U; u8TxBDIdx < (*config->siConfig).NumberOfTxBDR; u8TxBDIdx++)
973 {
974 config->stateStructure->LogicTxProducerIndex[u8TxBDIdx] = 0U;
975 config->stateStructure->lastTxDataBuffAddrIdx[u8TxBDIdx] = 0U;
976 config->stateStructure->FirstTxRingDescAddr[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].RingDesc;
977 config->stateStructure->TxRingSize[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].ringSize;
978 config->stateStructure->TxBufferLength[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].bufferLen;
979 config->stateStructure->TxCallback[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].Callback;
980 config->stateStructure->FirstTxDataBufferAddr[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].Buffer;
981 config->stateStructure->TxDataBuffMaxLenAddr[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].maxBuffLen;
982 /* If at least one controller has the tx Interrupt coalesing enabled, then set the right threshold for all
983 (0 if it is disabled, the configurated value if it is enabled).*/
984 config->stateStructure->TxTimerThreshold[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].TimerThreshold;
985 config->stateStructure->TxPacketsThreshold[u8TxBDIdx] = (*config->paCtrlTxRingConfig)[u8TxBDIdx].PacketsThreshold;
986
987 for (currBDIdx = 0; currBDIdx < (*config->paCtrlTxRingConfig)[u8TxBDIdx].ringSize; currBDIdx++)
988 {
989 config->stateStructure->LockTxBuffDescr[u8TxBDIdx][currBDIdx] = FALSE;
990 }
991 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
992 #if (NETC_ETH_IP_FILL_LEVEL_API_ENABLE == STD_ON)
993 Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][u8TxBDIdx].TotalNumberOfBuff = config->stateStructure->TxRingSize[u8TxBDIdx] - (uint16)1U;
994 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
995 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
996 }
997 /* Keep the interrupt setting for using information later. Per driver implementation the interrupts are enabled at controller level
998 (either all rings or none have interrupts enabled)m we will check the first ring value configured. */
999 config->stateStructure->RxInterrupts = (*config->siConfig).RxInterrupts;
1000 config->stateStructure->TxInterrupts = (*config->siConfig).TxInterrupts;
1001 config->stateStructure->VSItoPSIMsgCommand = (*config->siConfig).VSItoPSIMsgCommand;
1002 config->stateStructure->NumberOfTxBDR = (*config->siConfig).NumberOfTxBDR;
1003 config->stateStructure->NumberOfRxBDR = (*config->siConfig).NumberOfRxBDR;
1004 config->stateStructure->SiType = config->SiType;
1005 config->stateStructure->MACFilterTableMaxNumOfEntries = (*config->siConfig).MACFilterTableMaxNumOfEntries;
1006 config->stateStructure->CtrlLogicalIndex = (*config->siConfig).CtrlLogicalIndex;
1007 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
1008 config->stateStructure->RxDataBuffAddr = (*config).rxExternalBuffersAddr;
1009 #endif
1010
1011 /*SI runtime permissions */
1012 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
1013 {
1014 config->stateStructure->SIGeneralConfig = config->generalConfig->stationInterfaceGeneralConfig;
1015 config->stateStructure->generalConfig = config->generalConfig;
1016
1017 config->stateStructure->PcieAerUncorrectableErrEnabled = (*config->generalConfig).enableUncorrectableErrors;
1018 config->stateStructure->PcieAerCorrectableErrEnabled = (*config->generalConfig).enableCorrectableErrors;
1019 config->stateStructure->PcieAerErrorReportingCallback = (*config->generalConfig).errorReportingCallback;
1020 }
1021 else
1022 {
1023 config->stateStructure->SIGeneralConfig = NULL_PTR;
1024 config->stateStructure->generalConfig = NULL_PTR;
1025
1026 config->stateStructure->PcieAerUncorrectableErrEnabled = FALSE;
1027 config->stateStructure->PcieAerCorrectableErrEnabled = FALSE;
1028 config->stateStructure->PcieAerErrorReportingCallback = NULL_PTR;
1029 }
1030
1031 config->stateStructure->EnetcCommandBDConfig.commandBDAddr = (*config->siConfig).commandBDConfig.commandBDAddr;
1032 config->stateStructure->EnetcCommandBDConfig.lengthCBDR = (*config->siConfig).commandBDConfig.lengthCBDR;
1033
1034
1035
1036 Netc_Eth_Ip_apxState[ctrlIndex] = config->stateStructure;
1037 }
1038
Netc_Eth_Ip_InitTxBD(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1039 static void Netc_Eth_Ip_InitTxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1040 {
1041 uint8 currentTxBDR;
1042 uint32 currBDIdx;
1043 Netc_Eth_Ip_TxBDRType *TempTxDescr;
1044
1045 /* Loop through all the transmission rings used by the current controller. */
1046 for (currentTxBDR = 0U; currentTxBDR < (*config->siConfig).NumberOfTxBDR; currentTxBDR++)
1047 {
1048 /* Enable the queue and write the configured values for priority and weight */
1049 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBMR = NETC_F3_SI0_TBMR_PRIO((*config->paCtrlTxRingConfig)[currentTxBDR].Priority) | \
1050 NETC_F3_SI0_TBMR_WRR((*config->paCtrlTxRingConfig)[currentTxBDR].Weight) | \
1051 NETC_F3_SI0_TBMR_EN_MASK;
1052 /* Initialize the producer and the consumer indexe with 0 value. */
1053 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBPIR = 0U;
1054 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBCIR = 0U;
1055 /* Write the length of the ring */
1056 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBLENR = (*config->paCtrlTxRingConfig)[currentTxBDR].ringSize;
1057 /* Store the address of the first buffer descriptor in the current ring. */
1058 netcSIsBase[ctrlIndex]->BDR_NUM[currentTxBDR].TBBAR0 = (uint32)(*config->paCtrlTxRingConfig)[currentTxBDR].RingDesc;
1059
1060 TempTxDescr = (*config->paCtrlTxRingConfig)[currentTxBDR].RingDesc;
1061 /* Loop through all descriptors of the ring. */
1062 for (currBDIdx = 0U; currBDIdx < (*config->paCtrlTxRingConfig)[currentTxBDR].ringSize; currBDIdx++)
1063 {
1064 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS)
1065 if (!Netc_Eth_Ip_ControllerHasExternalTxBufferManagement[ctrlIndex])
1066 {
1067 /* Write in the buffer descriptor the address of the allocated buffer */
1068 TempTxDescr->dataBuffAddr = (uint32)((*config->paCtrlTxRingConfig)[currentTxBDR].Buffer) + \
1069 (uint32)(currBDIdx * (*config->paCtrlTxRingConfig)[currentTxBDR].maxBuffLen);
1070 }
1071 #endif
1072
1073 /* Write in the buffer descriptor the address of the allocated buffer */
1074 TempTxDescr->dataBuffAddr = (uint32)((*config->paCtrlTxRingConfig)[currentTxBDR].Buffer) + \
1075 (uint32)(currBDIdx * (*config->paCtrlTxRingConfig)[currentTxBDR].maxBuffLen);
1076
1077 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
1078 /* Write in the buffer descriptor the extended bit */
1079 TempTxDescr->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK);
1080 TempTxDescr->extendBuffConfig = (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));
1081 #else
1082 /* For the last descriptor write the final flag */
1083 TempTxDescr->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK)));
1084 #endif
1085 TempTxDescr++;
1086 }
1087 }
1088 }
1089
Netc_Eth_Ip_InitRxBD(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1090 static void Netc_Eth_Ip_InitRxBD(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1091 {
1092 uint8 u8RxBDIdx;
1093 uint32 DataBuffIndex;
1094 Netc_Eth_Ip_RxBDRType *pTempDescr;
1095
1096 for (u8RxBDIdx = 0U; u8RxBDIdx < (*config->siConfig).NumberOfRxBDR; u8RxBDIdx++)
1097 {
1098 /* Enable the queue and enable the extended mode for it */
1099 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBMR = NETC_F3_SI0_RBMR_EN_MASK;
1100 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
1101 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBMR |= NETC_F3_SI0_RBMR_BDS_MASK;
1102 #endif
1103 /* Write the producer and consumer indexes with 0 */
1104 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBPIR = 0U;
1105 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBCIR = 0U;
1106 /* Write the length of the ring */
1107 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBLENR = (*config->paCtrlRxRingConfig)[u8RxBDIdx].ringSize;
1108 /* Write in the transmission BDR register the address to the receive buffer descriptor. */
1109 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBBAR0 = (uint32)(*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
1110 /* Maximum size of the receive packet. Drop all packets with a bigger size. */
1111 netcSIsBase[ctrlIndex]->BDR_NUM[u8RxBDIdx].RBBSR = (*config->paCtrlRxRingConfig)[u8RxBDIdx].bufferLen;
1112
1113 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
1114 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
1115 {
1116 #endif
1117 pTempDescr = (*config->paCtrlRxRingConfig)[u8RxBDIdx].RingDesc;
1118 /* Loop through all descriptors of the queue */
1119 for (DataBuffIndex = 0U; DataBuffIndex < (*config->paCtrlRxRingConfig)[u8RxBDIdx].ringSize; DataBuffIndex++)
1120 {
1121 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
1122 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].RingIdx = (uint8)0xFF;
1123 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].ReceivedDataPtr = NULL_PTR;
1124 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].TimestampID = (uint32)0U;
1125 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].TimestampValueInvalidForSwt = (boolean)TRUE;
1126 #endif
1127 pTempDescr->configRxBD[0U] = (uint32)((*config->paCtrlRxRingConfig)[u8RxBDIdx].Buffer) + \
1128 (uint32)(DataBuffIndex * (*config->paCtrlRxRingConfig)[u8RxBDIdx].maxBuffLen);
1129 pTempDescr++;
1130 }
1131 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
1132 }
1133 #endif
1134
1135 }
1136 }
1137
Netc_Eth_Ip_Init_IpvToBdrMapping(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1138 static void Netc_Eth_Ip_Init_IpvToBdrMapping(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1139 {
1140 netcSIsBase[ctrlIndex]->SIIPVBDRMR0 =
1141 NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR(config->siConfig->ipvToBDR[0]) |
1142 NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR(config->siConfig->ipvToBDR[1]) |
1143 NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR(config->siConfig->ipvToBDR[2]) |
1144 NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR(config->siConfig->ipvToBDR[3]) |
1145 NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR(config->siConfig->ipvToBDR[4]) |
1146 NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR(config->siConfig->ipvToBDR[5]) |
1147 NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR(config->siConfig->ipvToBDR[6]) |
1148 NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR(config->siConfig->ipvToBDR[7]);
1149 }
1150
Netc_Eth_Ip_Init_VlanToIpvMapping(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1151 static void Netc_Eth_Ip_Init_VlanToIpvMapping(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1152 {
1153 /* Define default values for IPV and DR in case enableVlanToIpvMapping is disabled or the incomming frame doesn't have VLAN data. */
1154 if (ctrlIndex == 0U)
1155 {
1156 IP_NETC__ENETC0_PORT->PQOSMR |= (ENETC_PORT_PQOSMR_DDR(config->generalConfig->defaultDR) |
1157 ENETC_PORT_PQOSMR_DIPV(config->generalConfig->defaultIPV) |
1158 ENETC_PORT_PQOSMR_VS(1U)); /* PQOSMR[VS] = 1 --> outer tag is considered. */
1159 /* PQOSMR[VE] = 1 --> enable the use of VLAN tag data to determine IPV and DR, over the default settings. */
1160 }
1161
1162 /* Configure the receive BD rings assignment to group by setting SIRBGCR register according to the rules defined in the register definition.*/
1163 netcSIsBase[ctrlIndex]->SIRBGCR |= NETC_F3_SI0_SIRBGCR_NUM_GROUPS(1U); /* 1 Group, if 0 --> all incomming frames are received by RX BD Ring 0 regardles. */
1164
1165 if(ctrlIndex == 0U)
1166 {
1167 netcSIsBase[ctrlIndex]->SIRBGCR |= NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP(8U); /* 9 rings group PSI0 */
1168 }
1169 else
1170 {
1171 netcSIsBase[ctrlIndex]->SIRBGCR |= NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP(7U); /* 8 rings group for other SIs */
1172 }
1173
1174 /* Default receive group = 0. The default receive group is used when there is no match for RFS and RSS is disabled. */
1175 netcSIsBase[ctrlIndex]->SIMR &= (netcSIsBase[ctrlIndex]->SIMR ^ NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP(1U));
1176
1177 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
1178 if(config->siConfig->enableVlanToIpvMapping == TRUE)
1179 {
1180 /* enableVlanToIpvMapping == true -> VLAN tag PCP+DEI field is used to map to an IPV value by the SI (SIVLANIPVMR0/1 registers). */
1181 netcSIsBase[ctrlIndex]->SIMR |= (NETC_F3_SI1_SIMR_V2IPVE(1U));
1182 netcSIsBase[ctrlIndex]->SIVLANIPVMR0 =
1183 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0(config->siConfig->vlanToIpv[0])|
1184 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1(config->siConfig->vlanToIpv[1])|
1185 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2(config->siConfig->vlanToIpv[2])|
1186 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3(config->siConfig->vlanToIpv[3])|
1187 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4(config->siConfig->vlanToIpv[4])|
1188 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5(config->siConfig->vlanToIpv[5])|
1189 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6(config->siConfig->vlanToIpv[6])|
1190 NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7(config->siConfig->vlanToIpv[7]);
1191 netcSIsBase[ctrlIndex]->SIVLANIPVMR1 =
1192 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8(config->siConfig->vlanToIpv[8]) |
1193 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9(config->siConfig->vlanToIpv[9]) |
1194 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10(config->siConfig->vlanToIpv[10])|
1195 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11(config->siConfig->vlanToIpv[11])|
1196 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12(config->siConfig->vlanToIpv[12])|
1197 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13(config->siConfig->vlanToIpv[13])|
1198 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14(config->siConfig->vlanToIpv[14])|
1199 NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15(config->siConfig->vlanToIpv[15]);
1200 }
1201 else
1202 { /* enableVlanToIpvMapping == false -> The port default IPV is used (PQOSMR[DIPV] and PQOSMR[DDR]) */
1203 #endif
1204 /* V2IPVE is toggled off. 011 &= (011 ^ 010) , 001 &= (001 ^ 010) */
1205 netcSIsBase[ctrlIndex]->SIMR &= (netcSIsBase[ctrlIndex]->SIMR ^ NETC_F3_SI0_SIMR_V2IPVE(1U));
1206 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
1207 }
1208 #endif
1209 }
1210
Netc_Eth_Ip_InitCBDR(uint8 ctrlIndex)1211 static void Netc_Eth_Ip_InitCBDR(uint8 ctrlIndex)
1212 {
1213
1214 netcSIsBase[ctrlIndex]->SICBDRBAR0 = (uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr);
1215 netcSIsBase[ctrlIndex]->SICBDRLENR = NETC_F3_SI0_SICBDRLENR_LENGTH(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.lengthCBDR);
1216 netcSIsBase[ctrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(0U);
1217 netcSIsBase[ctrlIndex]->SICBDRCIR = NETC_F3_SI0_SICBDRCIR_BDR_INDEX(0U);
1218 netcSIsBase[ctrlIndex]->SICBDRMR = NETC_F3_SI0_SICBDRMR_EN(1U);
1219 }
1220
1221
Netc_Eth_Ip_EnableIrq_ConfigMsiTableTx(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config,Netc_Eth_Ip_MSITable * const msiTableConfig)1222 static inline void Netc_Eth_Ip_EnableIrq_ConfigMsiTableTx(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config, Netc_Eth_Ip_MSITable* const msiTableConfig)
1223 {
1224 uint8 txBDRIndex;
1225 msiTableConfig->msiTable[NETC_ETH_IP_TX_MSI_TABLE_INDEX].msgAddr = (*config->siConfig).txMruMailboxAddr;
1226 msiTableConfig->msiTable[NETC_ETH_IP_TX_MSI_TABLE_INDEX].controlVector = 0x0U;
1227 msiTableConfig->msiTable[NETC_ETH_IP_TX_MSI_TABLE_INDEX].msgData = 0xFFFFFFFFU;
1228
1229 for (txBDRIndex = 0U; txBDRIndex < (*config->siConfig).NumberOfTxBDR; txBDRIndex++)
1230 {
1231 netcSIsBase[ctrlIndex]->SIMSITRVR[txBDRIndex] = NETC_ETH_IP_TX_MSI_TABLE_INDEX;
1232 }
1233 }
1234
Netc_Eth_Ip_EnableIrq_ConfigMsiTableRx(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config,Netc_Eth_Ip_MSITable * const msiTableConfig)1235 static inline void Netc_Eth_Ip_EnableIrq_ConfigMsiTableRx(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config, Netc_Eth_Ip_MSITable* const msiTableConfig)
1236 {
1237 uint8 rxBDRIndex;
1238 msiTableConfig->msiTable[NETC_ETH_IP_RX_MSI_TABLE_INDEX].msgAddr = (*config->siConfig).rxMruMailboxAddr;
1239 msiTableConfig->msiTable[NETC_ETH_IP_RX_MSI_TABLE_INDEX].controlVector = 0x0U;
1240 msiTableConfig->msiTable[NETC_ETH_IP_RX_MSI_TABLE_INDEX].msgData = 0xFFFFFFFFU;
1241
1242 for (rxBDRIndex = 0U; rxBDRIndex < (*config->siConfig).NumberOfRxBDR; rxBDRIndex++)
1243 {
1244 netcSIsBase[ctrlIndex]->BDR_NUM[rxBDRIndex].RBICR0 |= NETC_F3_SI0_RBICR0_ICPT(1U);
1245 netcSIsBase[ctrlIndex]->BDR_NUM[rxBDRIndex].RBICR0 |= NETC_F3_SI0_RBICR0_ICEN_MASK;
1246 netcSIsBase[ctrlIndex]->SIMSIRRVR[rxBDRIndex] = NETC_ETH_IP_RX_MSI_TABLE_INDEX;
1247 }
1248 }
1249
Netc_Eth_Ip_EnableIrq(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1250 static inline void Netc_Eth_Ip_EnableIrq(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1251 {
1252 Netc_Eth_Ip_MSITable *msiTableConfig;
1253 Netc_Eth_Ip_VfBaseType *VSIConfig;
1254 NETC_F3_PCI_HDR_TYPE0_Type *PSIConfig;
1255 uint32* msiBaseAddr[] = NETC_ETH_IP_MSI_BASE_PTRS;
1256
1257 msiTableConfig = (Netc_Eth_Ip_MSITable *)msiBaseAddr[ctrlIndex];
1258
1259 if ((0U != (*config->siConfig).TxInterrupts) && \
1260 (NULL_PTR != (*config->siConfig).txMruMailboxAddr))
1261 {
1262 Netc_Eth_Ip_EnableIrq_ConfigMsiTableTx(ctrlIndex, config, msiTableConfig);
1263 }
1264
1265 if ((0U != (*config->siConfig).RxInterrupts) && \
1266 (NULL_PTR != (*config->siConfig).rxMruMailboxAddr))
1267 {
1268 Netc_Eth_Ip_EnableIrq_ConfigMsiTableRx(ctrlIndex, config, msiTableConfig);
1269 }
1270
1271 /* Enable MSI-X for configured function(SI).This will let MSI-X to request service. */
1272 if((TRUE == (*config->siConfig).EnableSIMsgInterrupt) && \
1273 (NETC_ETH_IP_PHYSICAL_SI == config->SiType) && \
1274 (NULL_PTR != (*config->siConfig).siMsgMruMailboxAddr))
1275 {
1276 /* Set the mailbox where PSI will receive the messages from VSIs. */
1277 msiTableConfig->msiTable[NETC_ETH_IP_SITOSI_MESSAGE_MSI_TABLE_INDEX].msgAddr = (*config->siConfig).siMsgMruMailboxAddr;
1278 msiTableConfig->msiTable[NETC_ETH_IP_SITOSI_MESSAGE_MSI_TABLE_INDEX].controlVector = 0x0U;
1279 msiTableConfig->msiTable[NETC_ETH_IP_SITOSI_MESSAGE_MSI_TABLE_INDEX].msgData = 0xFFFFFFFFU;
1280
1281 /* Enable the interrupt for all the other VSIs.
1282 The VSIs can be configured on other cores and there is no information if them are using or not SI messaging support. */
1283 netcSIsBase[ctrlIndex]->INTERRUPT.PSI.PSIIER |= 0xFE00FEU;
1284 }
1285
1286 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
1287 {
1288 PSIConfig = IP_NETC__NETC_F3_PCI_HDR_TYPE0;
1289 PSIConfig->PCI_CFC_MSIX_MSG_CTL |= NETC_ETH_IP_MSI_MSG_CTL_ENABLE_MASK;
1290 }
1291 else
1292 {
1293 VSIConfig = netcVFBase[ctrlIndex];
1294 VSIConfig->PCI_CFC_MSIX_MSG_CTL |= NETC_ETH_IP_MSI_MSG_CTL_ENABLE_MASK;
1295 }
1296 }
1297
Netc_Eth_Ip_ConfigPortTimeGateScheduling_GateControlState(uint32 * const RegValue,Netc_Eth_Ip_StatusType * const status)1298 static inline void Netc_Eth_Ip_ConfigPortTimeGateScheduling_GateControlState(uint32* const RegValue, Netc_Eth_Ip_StatusType* const status)
1299 {
1300 uint32 GateControlListState;
1301 uint32 StartTime;
1302 uint32 ElapsedTime;
1303 uint32 TimeoutTicks;
1304 boolean TimeExpired;
1305 /* Software must also wait until PTGAGLSR[TG] is deasserted before re-enabling. */
1306 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1307 do {
1308 /* get the state of gate control list */
1309 GateControlListState = (IP_NETC__ENETC0_PORT->PTGAGLSR & ENETC_PORT_PTGAGLSR_TG_MASK);
1310 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1311 } while ((GateControlListState != 0x0U) && (FALSE == TimeExpired));
1312
1313 if (GateControlListState == 0x0U)
1314 {
1315 *RegValue |= ENETC_PORT_PTGSCR_TGE(1U); /* Enable time gating */
1316 }
1317 else
1318 {
1319 *status = NETC_ETH_IP_STATUS_ERROR; /* fail to enable time gating because Operational gate control list is active */
1320 }
1321 }
1322
Netc_Eth_Ip_InitSI(const uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1323 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_InitSI(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1324 {
1325 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
1326 uint32 StartTime;
1327 uint32 ElapsedTime;
1328 uint32 TimeoutTicks;
1329
1330 if (NETC_ETH_IP_PHYSICAL_SI == config->SiType)
1331 {
1332 /* Use generalConfig to configure the general part of NETC */
1333
1334 /*Workaround for errata ERR051300: Disable all netc watchdogs to avoid watchdog timeout*/
1335 #if defined(ERR_IPV_NETC_051300)
1336 #if (STD_ON == ERR_IPV_NETC_051300)
1337 IP_NETC__NETC_PRIV->NETCWDTR = NETC_PRIV_NETCWDTR_MCED(1U) | NETC_PRIV_NETCWDTR_MCPD(1U) | NETC_PRIV_NETCWDTR_PCED(1U) | NETC_PRIV_NETCWDTR_HTAD(1U);
1338 #endif
1339 #endif
1340
1341 /* Enable function to master memory transaction requests and enable function to respond to memory space accesses (register accesses).
1342 Setting this bit may trigger the locking of IERB registers if not already done either explicitly through the NETCRR[LOCK] bit,
1343 or an earlier function initializing. Setting memory access enable will load IERB register values into the function and start any
1344 initialization of local table memory.
1345 Poll OSR[STATE] bit and wait for 0b0 before continuing device configuration.
1346 */
1347 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCI_CFH_CMD = NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(1U) | NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS(1U);
1348
1349 /* Enable the VFs;Enable memory space for VFs */
1350 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_SRIOV_CTL |= NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_MASK | \
1351 NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_MASK;
1352
1353 /* Wait for a successfully ENETC init. */
1354 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1355 do
1356 {
1357 if(NETC_F3_COMMON_OSR_STATE_MASK != (IP_NETC__ENETC0_COMMON->OSR & NETC_F3_COMMON_OSR_STATE_MASK))
1358 {
1359 Status = NETC_ETH_IP_STATUS_SUCCESS;
1360 break;
1361 }
1362 else
1363 {
1364 Status = NETC_ETH_IP_STATUS_TIMEOUT;
1365 }
1366 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
1367
1368 /** TODO: This will be supported later. */
1369 /* Configure the number of MSIs for all SIs - Port station interface a configuration register 2 (PSI0CFGR2 - PSI7CFGR2) */
1370
1371 /* Enable/disable MAC multicast/unicast promiscuous mode. */
1372 IP_NETC__ENETC0_BASE->PSIPMMR = ((uint32)((*config->generalConfig).maskMACPromiscuousMulticastEnable) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT) | \
1373 (uint32)((*config->generalConfig).maskMACPromiscuousUnicastEnable);
1374
1375 /* Set Layer 3 IPv4 Header checksum validation*/
1376 IP_NETC__ENETC0_BASE->PARCSCR = NETC_F3_PARCSCR_L4CD((*config->generalConfig).rxCheckSumOffloadingIPV4);
1377 /*
1378 Checking only TCP offload because when it is enabled, UDP is by default enabled in configuration
1379 Set Layer 4 TCP and UDP checksum validation
1380 */
1381 IP_NETC__ENETC0_BASE->PARCSCR |= NETC_F3_PARCSCR_L3CD((*config->generalConfig).rxCheckSumOffloadingTCPUDP);
1382
1383 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
1384 /* Configure for Custom VLAN Ethertype 1 */
1385 IP_NETC__ENETC0_COMMON->CVLANR1 = config->generalConfig->CustomVlanEthertype1;
1386 /* Configure for Custom VLAN Ethertype 2 */
1387 IP_NETC__ENETC0_COMMON->CVLANR2 = config->generalConfig->CustomVlanEthertype2;
1388 /* Enable/disable MAC VLAN promiscuous mode and permssion of the SI to receive untagged traffic while the VLAN support is enabled for ENTC0. */
1389 IP_NETC__ENETC0_BASE->PSIPVMR =(uint32)((*config->generalConfig).maskMACVLANPromiscuousEnable) |
1390 config->generalConfig->maskVLANAllowUntaggedEnable ;
1391 /*Disable OAI - Outer As Inner*/
1392 IP_NETC__ENETC0_BASE->PVCLCTR = NETC_F3_PVCLCTR_OAI(0U);
1393 /*Enable VS - VLAN Select*/
1394 IP_NETC__ENETC0_BASE->PSIVLANFMR = NETC_F3_PSIVLANFMR_VS(1U);
1395 #endif
1396 Netc_Eth_Ip_InitSI_ConfigureVSI(ctrlIndex, config);
1397
1398 /** TODO: Advanced feature configuration. TBA later. */
1399 /* Configure the number of MAC and VLAN filter entries for all SIs - Port station interface 0 VSI MAC address filtering configuration register (PSI0VMAFCFGR) and
1400 Port station interface 0 VLAN filtering configuration register (PSI0VLANFCFGR)
1401 Port station interface a VSI MAC address filtering configuration register (PSI1VMAFCFGR - PSI7VMAFCFGR) and
1402 Port station interface a VLAN filtering configuration register (PSI1VLANFCFGR - PSI7VLANFCFGR)*/
1403 /* Configure the internal priority to ICM priority mapping - Receive IPV to ICM priority mapping register 0 (IPV2ICMPMR0) */
1404 /* Configure the IPV to traffic class assignment - Transmit priority to traffic class mapping register 0 (PRIO2TCMR0) */
1405 IP_NETC__ENETC0_BASE->PRIO2TCMR0 = NETC_F3_PRIO2TCMR0_PRIO0TC((uint32)((*config->generalConfig).priorityToTrafficClassic[0])) |
1406 NETC_F3_PRIO2TCMR0_PRIO1TC((uint32)((*config->generalConfig).priorityToTrafficClassic[1])) |
1407 NETC_F3_PRIO2TCMR0_PRIO2TC((uint32)((*config->generalConfig).priorityToTrafficClassic[2])) |
1408 NETC_F3_PRIO2TCMR0_PRIO3TC((uint32)((*config->generalConfig).priorityToTrafficClassic[3])) |
1409 NETC_F3_PRIO2TCMR0_PRIO4TC((uint32)((*config->generalConfig).priorityToTrafficClassic[4])) |
1410 NETC_F3_PRIO2TCMR0_PRIO5TC((uint32)((*config->generalConfig).priorityToTrafficClassic[5])) |
1411 NETC_F3_PRIO2TCMR0_PRIO6TC((uint32)((*config->generalConfig).priorityToTrafficClassic[6])) |
1412 NETC_F3_PRIO2TCMR0_PRIO7TC((uint32)((*config->generalConfig).priorityToTrafficClassic[7]));
1413
1414 /* Configure speed and other settings in Port configuration register (PCR) */
1415
1416 if ((*config->generalConfig).enableCorrectableErrors || (*config->generalConfig).enableUncorrectableErrors)
1417 {
1418 Status = Netc_Eth_Ip_SetupErrorReporting(config->generalConfig);
1419 }
1420
1421 }
1422 else
1423 {
1424 /* Wait until PSI start current VSI. */
1425 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1426 do
1427 {
1428 if (NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK == \
1429 ((netcVFBase[ctrlIndex]->PCI_CFH_CMD & NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK)))
1430 {
1431 Status = NETC_ETH_IP_STATUS_SUCCESS;
1432 break;
1433 }
1434 else
1435 {
1436 Status = NETC_ETH_IP_STATUS_TIMEOUT;
1437 }
1438 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
1439 }
1440
1441 return Status;
1442 }
1443
1444 #if (NETC_ETH_MAX_NUMBER_OF_IPFTABLE_LIST > 0U)
Netc_Eth_Ip_InitIngressPortFilterTable(const uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * config)1445 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_InitIngressPortFilterTable(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
1446 {
1447 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
1448 Netc_Eth_Ip_IngressPortFilterEntryDataType IngressPortFilterTableEntry = {0U};
1449 uint8 IPFTableListIdx;
1450 uint32 MatchedEntries = 0UL;
1451
1452 /* Initialize IPF table */
1453 if ((*config->generalConfig).numberOfIPFTableList > 0U)
1454 {
1455 /* Set the EN bit in Station interface mode register (SIMR) to enable psi0*/
1456 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
1457
1458 for (IPFTableListIdx = 0U; IPFTableListIdx < (*config->generalConfig).numberOfIPFTableList; IPFTableListIdx++)
1459 {
1460 /* init IPF table entry data */
1461 Netc_Eth_Ip_InitIPFTableEntryData(config, IPFTableListIdx, &IngressPortFilterTableEntry);
1462
1463 /* add static IPF table entries */
1464 Status = Netc_Eth_Ip_AddIngressPortFilterTableEntry(0U, &MatchedEntries, &IngressPortFilterTableEntry);
1465 }
1466
1467 /* Clear the EN bit in Station interface mode register (SIMR) to disalbe psi0 */
1468 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
1469 }
1470
1471 return Status;
1472 }
1473 #endif
1474
Netc_Eth_Ip_ComputeMACHashValue(const uint8 * MacAddr)1475 static inline uint8 Netc_Eth_Ip_ComputeMACHashValue(const uint8 *MacAddr)
1476 {
1477 uint8 HashValue = 0U;
1478 uint8 h0;
1479 uint8 h1;
1480 uint8 h2;
1481 uint8 h3;
1482 uint8 h4;
1483 uint8 h5;
1484
1485 h0 = ((NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1486 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1487 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1488 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1489 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1490 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1491 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1492 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[5U])));
1493
1494 h1 = ((NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1495 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1496 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1497 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1498 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1499 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1500 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1501 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[5U])));
1502
1503 h2 = ((NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1504 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1505 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1506 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1507 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1508 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1509 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1510 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[5U])));
1511
1512 h3 = ((NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1513 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1514 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1515 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1516 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1517 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1518 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1519 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[5U])));
1520
1521 h4 = ((NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1522 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1523 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1524 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1525 (NETC_ETH_IP_BIT4_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1526 (NETC_ETH_IP_BIT2_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1527 (NETC_ETH_IP_BIT0_VALUE_FROM_BYTE(MacAddr[5U])) ^ \
1528 (NETC_ETH_IP_BIT6_VALUE_FROM_BYTE(MacAddr[5U])));
1529
1530 h5 = ((NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[0U])) ^ \
1531 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[1U])) ^ \
1532 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1533 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[2U])) ^ \
1534 (NETC_ETH_IP_BIT5_VALUE_FROM_BYTE(MacAddr[3U])) ^ \
1535 (NETC_ETH_IP_BIT3_VALUE_FROM_BYTE(MacAddr[4U])) ^ \
1536 (NETC_ETH_IP_BIT1_VALUE_FROM_BYTE(MacAddr[5U])) ^ \
1537 (NETC_ETH_IP_BIT7_VALUE_FROM_BYTE(MacAddr[5U])));
1538
1539 HashValue = (h5 << (uint8)5U) | (h4 << (uint8)4U) | (h3 << (uint8)3U) | (h2 << (uint8)2U) | (h1 << (uint8)1U) | h0;
1540
1541 return HashValue;
1542 }
1543
Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(uint8 VsiId,const Netc_Eth_Ip_VsiToPsiMsgType * MsgCommandConfig,uint16 * PsiRspMessage)1544 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(uint8 VsiId, const Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig, uint16 * PsiRspMessage )
1545 {
1546 uint32 StartTime;
1547 uint32 ElapsedTime;
1548 uint32 TimeoutTicks;
1549 Netc_Eth_Ip_StatusType Status;
1550 Netc_Eth_Ip_StatusType PSIResponseStatus;
1551
1552 /*Assure the data to be sent is synchronised*/
1553 MCAL_DATA_SYNC_BARRIER();
1554 /* Set message command address(aligned at 64) and the size of it(6 bits code). */
1555 ((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGSNDAR0 = ((uint32)MsgCommandConfig | NETC_ETH_IP_VSITOPSI_MSG_SIZE);
1556
1557 /* Wait until the message sent is processed by PSI. */
1558 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
1559 do
1560 {
1561 /* Return the status of the message command. */
1562 if (NETC_ETH_IP_VSI_MSG_PROGRESS_STATUS != \
1563 (((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGSR & NETC_ETH_IP_VSI_MSG_PROGRESS_STATUS))
1564 {
1565
1566 Status = (Netc_Eth_Ip_StatusType)((uint16)(((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGSR) & NETC_ETH_IP_VSI_MSG_STATUS);
1567
1568 /* If the message was successfully transmited, copy the index value, or the user defined Message Code, received from PSI */
1569 if(NETC_ETH_IP_STATUS_SUCCESS == Status )
1570 {
1571 PSIResponseStatus = (Netc_Eth_Ip_StatusType) (((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.VSI_A.VSIMSGRR >> NETC_ETH_IP_PSI_MSG_POS );
1572
1573 switch(PSIResponseStatus)
1574 {
1575 case NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL:
1576 {
1577 Status = NETC_ETH_IP_STATUS_SUCCESS;
1578 break;
1579 }
1580 case NETC_ETH_IP_PSITOVSI_SYNC_STATUS_TRUE:
1581 {
1582 /*load sync state into the output partameter*/
1583 *PsiRspMessage = 1U;
1584 Status = NETC_ETH_IP_STATUS_SUCCESS;
1585 break;
1586 }
1587 case NETC_ETH_IP_PSITOVSI_SYNC_STATUS_FALSE:
1588 {
1589 *PsiRspMessage = 0U;
1590 Status = NETC_ETH_IP_STATUS_SUCCESS;
1591 break;
1592 }
1593 #if defined(ERR_IPV_NETC_051247)
1594 #if (STD_ON == ERR_IPV_NETC_051247)
1595 case NETC_ETH_IP_PSITOVSI_MSG_INTEGRITY_ERROR:
1596 {
1597 Status = NETC_ETH_IP_STATUS_ERROR;
1598 break;
1599 }
1600 #endif
1601 #endif
1602 default:
1603 {
1604 Status = NETC_ETH_IP_STATUS_ERROR;
1605 break;
1606 }
1607 }
1608 }
1609 break;
1610 }
1611 else
1612 {
1613 Status = NETC_ETH_IP_STATUS_TIMEOUT;
1614 }
1615 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
1616
1617 return Status;
1618 }
1619
Netc_Eth_Ip_AddMACFilterEntry(uint8 CtrlIndex,uint8 HashValue,const uint8 * MacAddr)1620 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddMACFilterEntry(uint8 CtrlIndex, uint8 HashValue, const uint8 *MacAddr)
1621 {
1622 uint8 CurrentEntry;
1623 uint8 CurrentMACByte;
1624 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_MAC_ADDR_TABLE_FULL;
1625
1626 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1627 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1628 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
1629 #endif
1630
1631 for(CurrentEntry = 0U; CurrentEntry < Netc_Eth_Ip_apxState[CtrlIndex]->MACFilterTableMaxNumOfEntries; CurrentEntry++)
1632 {
1633 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00();
1634 if(FALSE == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus)
1635 {
1636 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus = TRUE;
1637 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00();
1638
1639 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].HashValue = HashValue;
1640 for(CurrentMACByte = 0U; CurrentMACByte < NETC_ETH_IP_MAC_BYTES_SIZE;CurrentMACByte++)
1641 {
1642 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].MACAddr[CurrentMACByte] = MacAddr[CurrentMACByte];
1643 }
1644 Status = NETC_ETH_IP_STATUS_SUCCESS;
1645 break;
1646 }
1647 else
1648 {
1649 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00();
1650 }
1651 }
1652 return Status;
1653 }
1654
Netc_Eth_Ip_DeleteMACFilterEntry(const uint8 CtrlIndex,const uint8 HashValue,const uint8 * MacAddr)1655 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteMACFilterEntry(const uint8 CtrlIndex, const uint8 HashValue, const uint8 *MacAddr)
1656 {
1657 uint8 CurrentEntry;
1658 Netc_Eth_Ip_StatusType Status;
1659 boolean MatchedEntry = FALSE;
1660 uint8 HashNumOfMatches = 0U;
1661
1662 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
1663 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
1664 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
1665 #endif
1666
1667 for(CurrentEntry = 0U; CurrentEntry < Netc_Eth_Ip_apxState[CtrlIndex]->MACFilterTableMaxNumOfEntries; CurrentEntry++)
1668 {
1669 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
1670 if ((TRUE == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus) && \
1671 (HashValue == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].HashValue)
1672 )
1673 {
1674 HashNumOfMatches++;
1675 Netc_Eth_Ip_DeleteMACFilterEntry_MarkEntryEmpty(CtrlIndex, &MatchedEntry, CurrentEntry, MacAddr);
1676 }
1677 else
1678 {
1679 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
1680 }
1681 }
1682
1683 if(MatchedEntry)
1684 {
1685 if(1U == HashNumOfMatches)
1686 {
1687 Status = NETC_ETH_IP_STATUS_DELETE_MAC_ADDR;
1688 }
1689 else
1690 {
1691 Status = NETC_ETH_IP_STATUS_SUCCESS;
1692 }
1693 }
1694 else
1695 {
1696 Status = NETC_ETH_IP_STATUS_MAC_ADDR_NOT_FOUND;
1697 }
1698
1699 return Status;
1700 }
1701 #if defined(ERR_IPV_NETC_051247)
1702 #if (STD_ON == ERR_IPV_NETC_051247)
Netc_Eth_Ip_VsiMsgCalculateCRC8(const Netc_Eth_Ip_VsiToPsiMsgType * MsgCommandConfig,uint8 MsgLength)1703 uint8 Netc_Eth_Ip_VsiMsgCalculateCRC8(const Netc_Eth_Ip_VsiToPsiMsgType * MsgCommandConfig, uint8 MsgLength)
1704 {
1705 uint8 Data;
1706 uint8 Crc = (uint8) 0U;
1707 uint8 ByteNb;
1708 uint8 BitNb;
1709
1710 /* Calculate modulo 2 division for each message byte. */
1711 for(ByteNb = 0U; ByteNb < MsgLength; ByteNb++)
1712 {
1713 if(ByteNb == 0U) /* Class field*/
1714 {
1715 Data = MsgCommandConfig->Class;
1716 }
1717 else if(ByteNb == 1U) /* Command field*/
1718 {
1719 Data = MsgCommandConfig->Command;
1720 }
1721 else /* Data field array. ByteNb - 2 to start indexing Data field array from 0 */
1722 {
1723 Data = MsgCommandConfig->Data[ByteNb - 2U];
1724 }
1725
1726 /* Take the next byte into the Crc */
1727 Crc ^= Data;
1728
1729 /* Calculate modulo 2 division bit by bit */
1730 for(BitNb = 8U; BitNb > 0U; BitNb--)
1731 {
1732 if((Crc & ((uint8) 1U << (uint8) 7U)) != (uint8) 0U)
1733 {
1734 Crc = (Crc << (uint8) 1U) ^ (uint8) NETC_ETH_IP_VSI_MSG_POLYNOMIAL;
1735 }
1736 else
1737 {
1738 Crc = Crc << (uint8) 1U;
1739 }
1740 }
1741 }
1742
1743 return Crc;
1744 }
1745 #endif
1746 #endif
1747
1748 /* Local function to clear the VSI to PSI message buffer */
Netc_Eth_Ip_ClearVsiToPsiMsgBuff(Netc_Eth_Ip_VsiToPsiMsgType * MsgCommandConfig,uint8 Size)1749 static inline void Netc_Eth_Ip_ClearVsiToPsiMsgBuff(Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig, uint8 Size)
1750 {
1751 uint8 DataIdx;
1752
1753 MsgCommandConfig->Class = (uint8)0U;
1754 MsgCommandConfig->Command = (uint8)0U;
1755
1756 for(DataIdx = 0; DataIdx < (Size - (uint8) 2U); DataIdx++)
1757 {
1758 MsgCommandConfig->Data[DataIdx] = (uint8)0U;
1759 }
1760 }
1761
Netc_Eth_Ip_VsiToPsiMsg(uint8 VsiId,Netc_Eth_Ip_VsiToPsiMsgActionType MsgAction,const uint8 * MacAddr,uint16 * PsiRspMessage)1762 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsiMsg(uint8 VsiId, \
1763 Netc_Eth_Ip_VsiToPsiMsgActionType MsgAction, \
1764 const uint8 *MacAddr, \
1765 uint16 * PsiRspMessage)
1766 {
1767 Netc_Eth_Ip_StatusType Status;
1768 Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig = Netc_Eth_Ip_apxState[VsiId]->VSItoPSIMsgCommand;
1769
1770 /*Clear the buffer before sending a new command */
1771 Netc_Eth_Ip_ClearVsiToPsiMsgBuff(MsgCommandConfig, ((uint8) sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8) NETC_ETH_IP_VSITOPSI_MSG_SIZE));
1772
1773 switch (MsgAction)
1774 {
1775 case NETC_ETH_IP_VSITOPSI_MAC_ADDR_SET:
1776 {
1777 /* Set class for command message. */
1778 MsgCommandConfig->Class = (uint8)0U;
1779 MsgCommandConfig->Command = (uint8)0U;
1780 /* Set MAC address. */
1781 MsgCommandConfig->Data[0U] = (uint8)0U;
1782 MsgCommandConfig->Data[1U] = (uint8)0U;
1783 MsgCommandConfig->Data[2U] = MacAddr[0U];
1784 MsgCommandConfig->Data[3U] = MacAddr[1U];
1785 MsgCommandConfig->Data[4U] = MacAddr[2U];
1786 MsgCommandConfig->Data[5U] = MacAddr[3U];
1787 MsgCommandConfig->Data[6U] = MacAddr[4U];
1788 MsgCommandConfig->Data[7U] = MacAddr[5U];
1789 #if defined(ERR_IPV_NETC_051247)
1790 #if (STD_ON == ERR_IPV_NETC_051247)
1791 /* Calculate CRC, for the number of transmited bytes (10 bytes for this command), and assign it to Data fields last byte */
1792 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1793 #endif
1794 #endif
1795 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1796 break;
1797 }
1798 case NETC_ETH_IP_VSITOPSI_ADD_RX_MAC_ADDR_FILTER:
1799 {
1800 /* Set class for command message. */
1801 MsgCommandConfig->Class = (uint8)1U;
1802 MsgCommandConfig->Command = (uint8)0U;
1803 /* Compute the hash value for the MAC address. */
1804 MsgCommandConfig->Data[0U] = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
1805 MsgCommandConfig->Data[1U] = (uint8)0U;
1806 /* Exact match(EM) will be deactivated when hash table is used. */
1807 MsgCommandConfig->Data[2U] = (uint8)0U;
1808 #if defined(ERR_IPV_NETC_051247)
1809 #if (STD_ON == ERR_IPV_NETC_051247)
1810 /* Calculate CRC, for the number of transmited bytes (5 bytes for this command), and assign it to Data fields last byte */
1811 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1812 #endif
1813 #endif
1814 Status = Netc_Eth_Ip_AddMACFilterEntry(VsiId, MsgCommandConfig->Data[0U], MacAddr);
1815
1816 if(NETC_ETH_IP_STATUS_SUCCESS == Status)
1817 {
1818 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1819 }
1820 break;
1821 }
1822 case NETC_ETH_IP_VSITOPSI_DELETE_RX_MAC_ADDR_FILTER:
1823 {
1824 /* Compute the hash value for the MAC address. */
1825 MsgCommandConfig->Data[0U] = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
1826 Status = Netc_Eth_Ip_DeleteMACFilterEntry(VsiId, MsgCommandConfig->Data[0U], MacAddr);
1827
1828 if(NETC_ETH_IP_STATUS_DELETE_MAC_ADDR == Status)
1829 {
1830 /* Set class for command message. */
1831 MsgCommandConfig->Class = (uint8)1U;
1832 MsgCommandConfig->Command = (uint8)1U;
1833 MsgCommandConfig->Data[1U] = (uint8)0U;
1834 /* Exact match(EM) will be deactivated when hash table is used. */
1835 MsgCommandConfig->Data[2U] = (uint8)0U;
1836 #if defined(ERR_IPV_NETC_051247)
1837 #if (STD_ON == ERR_IPV_NETC_051247)
1838 /* Calculate CRC, for the number of transmited bytes (5 bytes for this command), and assign it to Data fields last byte */
1839 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1840 #endif
1841 #endif
1842 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1843 }
1844
1845 break;
1846 }
1847 case NETC_ETH_IP_VSITOPSI_ENABLE_MULTICAST:
1848 {
1849 /* Set class for command message. */
1850 MsgCommandConfig->Class = (uint8)0x10U;
1851 MsgCommandConfig->Command = (uint8)0x00U;
1852 #if defined(ERR_IPV_NETC_051247)
1853 #if (STD_ON == ERR_IPV_NETC_051247)
1854 /* Calculate CRC, for the number of transmited bytes (2 bytes for this command), and assign it to Data fields last byte */
1855 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1856 #endif
1857 #endif
1858 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1859 break;
1860 }
1861 case NETC_ETH_IP_VSITOPSI_DISABLE_MULTICAST:
1862 {
1863 /* Set class for command message. */
1864 MsgCommandConfig->Class = (uint8)0x10U;
1865 MsgCommandConfig->Command = (uint8)0x10U;
1866 #if defined(ERR_IPV_NETC_051247)
1867 #if (STD_ON == ERR_IPV_NETC_051247)
1868 /* Calculate CRC, for the number of transmited bytes (2 bytes for this command), and assign it to Data fields last byte */
1869 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1870 #endif
1871 #endif
1872 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1873 break;
1874 }
1875 case NETC_ETH_IP_VSITOPSI_CLOSE_FILTER:
1876 {
1877 /* Set class for command message. */
1878 MsgCommandConfig->Class = (uint8)0x10U;
1879 MsgCommandConfig->Command = (uint8)0x20U;
1880 #if defined(ERR_IPV_NETC_051247)
1881 #if (STD_ON == ERR_IPV_NETC_051247)
1882 /* Calculate CRC, for the number of transmited bytes (2 bytes for this command), and assign it to Data fields last byte */
1883 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1884 #endif
1885 #endif
1886 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1887 break;
1888 }
1889 case NETC_ETH_IP_VSITOPSI_GET_SYNC_STATE:
1890 {
1891 /* Set class for command message. */
1892 MsgCommandConfig->Class = (uint8)0x20U;
1893 MsgCommandConfig->Command = (uint8)0x00U;
1894 #if defined(ERR_IPV_NETC_051247)
1895 #if (STD_ON == ERR_IPV_NETC_051247)
1896 /* Calculate CRC, for the number of transmited bytes (2 bytes for this command), and assign it to Data fields last byte */
1897 MsgCommandConfig->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] = Netc_Eth_Ip_VsiMsgCalculateCRC8( MsgCommandConfig, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U));
1898 #endif
1899 #endif
1900 Status = Netc_Eth_Ip_WaitVsiToPsiMsgTransmission(VsiId, MsgCommandConfig, PsiRspMessage);
1901 break;
1902 }
1903 default:
1904 {
1905 Status = NETC_ETH_IP_STATUS_UNSUPPORTED;
1906 break;
1907 }
1908 }
1909
1910 return Status;
1911 }
1912
1913 /*FUNCTION**********************************************************************
1914 *
1915 * Function Name : Netc_Eth_Ip_CoalescingTxPacketsConversion
1916 * Description : Internal function for converting a number of packets to a hardware specific value using the formula:
1917 * PacketsThreshold - no of packets
1918 * TwoPow = hardware specific value which will be set in the ICTT part of the TBxICR0 register. It will be
1919 * the greatest value which satisfies the following formula.
1920 * PacketsThreshold >= 2 ^(TwoPow-1)
1921 *
1922 *END**************************************************************************/
Netc_Eth_Ip_CoalescingTxPacketsConversion(uint16 PacketsThreshold)1923 static uint8 Netc_Eth_Ip_CoalescingTxPacketsConversion (uint16 PacketsThreshold)
1924 {
1925 uint16 RegVal = 1U;
1926 uint8 TwoPow = 0;
1927
1928 for(TwoPow = 1U; TwoPow < 16U; TwoPow++)
1929 {
1930 RegVal *= 2U;
1931
1932 if (RegVal > PacketsThreshold)
1933 {
1934 break;
1935 }
1936 }
1937
1938 return TwoPow;
1939 }
1940
1941 /*FUNCTION**********************************************************************
1942 *
1943 * Function Name : Netc_Eth_Ip_SendCommand
1944 * Description : Internal function for adding an entry with different commands to command ring.
1945 *
1946 *END**************************************************************************/
Netc_Eth_Ip_SendCommand(const uint8 CtrlIndex,const Netc_Eth_Ip_ReqHeaderTableOperationDataType * OperationData)1947 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendCommand(const uint8 CtrlIndex, const Netc_Eth_Ip_ReqHeaderTableOperationDataType *OperationData)
1948 {
1949 uint32 producerIdx;
1950 uint32 consumerIdx;
1951 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
1952 uint32 PreviousProducerIdx;
1953 uint32 statusField;
1954 uint32 rrBit;
1955 uint32 errorField;
1956 uint32 StartTime;
1957 uint32 ElapsedTime;
1958 uint32 TimeoutTicks;
1959 boolean TimeExpired;
1960
1961 /* read the producer and consumer index register */
1962 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
1963 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
1964
1965 /* check if the ring is full */
1966 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
1967 {
1968 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
1969 }
1970 else
1971 {
1972 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16();
1973 /* +++ fill in the NTMP request message header +++ */
1974 /* set the table address */
1975 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_ADDR_L] = (uint32)(&Netc_Eth_Ip_EnetcTableDataBuffer);
1976
1977 /* set the length of request and response data buffer */
1978 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_LENGTHFIELD] = (NETC_ETH_IP_CMDBD_REQFMT_REQUEST_LENGTH(OperationData->ReqBuffLength) | NETC_ETH_IP_CMDBD_REQFMT_RESPONSE_LENGTH(OperationData->RspBuffLength));
1979
1980 /* set RR = 0, CCI = 0, protocol version = 2, table id, access method and cmd */
1981 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] = 0x0; /* clear this field first */
1982 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CMD(OperationData->Cmd);
1983 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_ACCESS_METHOD(OperationData->AccessMethod);
1984 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_TABLE_ID(OperationData->TableId);
1985 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_VERSION(OperationData->Version);
1986 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CCI(OperationData->CmdCompletionInt);
1987 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_CONFIGFIELD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_RR(0U); /* RR bit has to be set to 0 */
1988
1989 /* set NTMP version to 2.0*/
1990 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_REQHEADER_NPFFIELD] = NETC_ETH_IP_CMDBD_REQFMT_NPF_FIELD(NETC_ETH_IP_CMDBD_REQFMT_NTMP_PROTOCOL_VERSION);
1991 /* --- fill in the NTMP request message header --- */
1992 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16();
1993
1994 /* +++ write the produce index register and enable hardware to consume the command +++ */
1995 PreviousProducerIdx = producerIdx; /* save the produce index before incrementing it manually */
1996 if ((producerIdx + 0x1UL) == ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) /* adjust producer index */
1997 {
1998 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, then it would start from 0 again */
1999 }
2000 else
2001 {
2002 producerIdx += 0x1UL; /* increase the producer index manually */
2003 }
2004
2005 /* This is needed to make sure the descriptor gets updated with the latest values, before
2006 incrementing the producer index to start the actual operation */
2007 MCAL_DATA_SYNC_BARRIER();
2008
2009 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
2010 /* --- write the produce index register and enable hardware to consume the command --- */
2011
2012 /* +++ to make sure the hardware consumes and processes the command completely +++ */
2013 /* Setup timeout timer */
2014 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
2015 do {
2016 statusField = Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[PreviousProducerIdx].MessageHeaderDataField[NETC_ETH_IP_RSPHEADER_STATUS_FIELD_INDEX]; /* get status field in the response data buffer */
2017 rrBit = ((statusField & (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_RR_MASK)) >> (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_RR_SHIFT)); /* get the value of RR bit in the response data buffer */
2018 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
2019 } while ((rrBit != 0x1U) && (FALSE == TimeExpired)); /* wait the hardware consume the command and check RR bit to see if the processing is completed (rrBit = 1). */
2020 /* --- to make sure the hardware consumes and processes the command completely --- */
2021
2022 /* return the value of ERROR field in response data buffer indicating if there is an error for processing the command */
2023 errorField = ((statusField & (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_ERROR_MASK)) >> (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_ERROR_SHIFT));
2024 if (errorField != 0U)
2025 {
2026 status = (Netc_Eth_Ip_StatusType)errorField; /* ERROR field should be 0. */
2027 }
2028 }
2029 return status;
2030 }
2031
2032 /*FUNCTION**********************************************************************
2033 *
2034 * Function Name : Netc_Eth_Ip_SendNTMP1Command_ShortFormat
2035 * Description : Internal function for adding an entry with different commands to command ring (short format) for NTMP V1.0.
2036 *
2037 *END**************************************************************************/
Netc_Eth_Ip_SendNTMP1Command_ShortFormat(uint8 CtrlIndex,const Netc_Eth_Ip_SetMessageHeaderTableOperationDataType * OperationData)2038 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendNTMP1Command_ShortFormat(uint8 CtrlIndex, const Netc_Eth_Ip_SetMessageHeaderTableOperationDataType *OperationData)
2039 {
2040 uint32 producerIdx;
2041 uint32 consumerIdx;
2042 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2043 uint32 PreviousConsumerIdx;
2044 uint8 statusField;
2045 uint32 StartTime;
2046 uint32 ElapsedTime;
2047 uint32 TimeoutTicks;
2048 boolean TimeExpired;
2049
2050 /* read the producer and consumer index register */
2051 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
2052 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
2053
2054 /* check if the ring is full */
2055 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
2056 {
2057 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
2058 }
2059 else
2060 {
2061 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17();
2062 /* Fill in the configured data */
2063 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L] = OperationData->Data0;
2064 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_H] = OperationData->Data1;
2065 if (OperationData->Command == 0U)
2066 {
2067 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_1] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_EN(0x1U);
2068 }
2069 else
2070 {
2071 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_1] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_EN(0x0U);
2072 }
2073 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_2] = 0x0UL;
2074 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_3] = 0x0UL;
2075 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_4] = (uint32)OperationData->SI_Bitmap;
2076 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_LENGTH_INDEX] = OperationData->Index;
2077
2078 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SF(0x1U);
2079 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CI(0x0U);
2080 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_STATUS(0x0U);
2081 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CLASS(OperationData->Class);
2082 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_COMMAND(OperationData->Command);
2083 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17();
2084
2085 /* +++ write the producer index register and enable hardware to consume the command +++ */
2086 PreviousConsumerIdx = consumerIdx;
2087 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == 0U) /* adjust producer index */
2088 {
2089 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, the producer index should start from 0 again */
2090 }
2091 else
2092 {
2093 producerIdx += 0x1UL; /* increase the producer index manually */
2094 }
2095
2096 /* This is needed to make sure the descriptor gets updated with the latest values, before
2097 incrementing the producer index to start the actual operation */
2098 MCAL_DATA_SYNC_BARRIER();
2099
2100 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
2101 /* --- write the producer index register and enable hardware to consume the command --- */
2102
2103 /* +++ to make sure the hardware consumes and processes the command completely +++ */
2104 /* Setup timeout timer */
2105 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
2106 do {
2107 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
2108 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
2109 } while ((consumerIdx == PreviousConsumerIdx) && (FALSE == TimeExpired)); /* wait the hardware consume the command. */
2110 /* --- to make sure the hardware consumes and processes the command completely --- */
2111
2112 if (TRUE == TimeExpired)
2113 {
2114 status = NETC_ETH_IP_STATUS_ERROR;
2115 }
2116 else
2117 {
2118 statusField = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_GET_STATUS(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[consumerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD]); /* get status field in the response data buffer */
2119 if (statusField != 0U)
2120 {
2121 status = NETC_ETH_IP_STATUS_ERROR; /* STATUS field should be 0. */
2122 }
2123 }
2124 }
2125 return status;
2126 }
2127
2128 /*FUNCTION**********************************************************************
2129 *
2130 * Function Name : Netc_Eth_Ip_AddVLANFilterTableEntry
2131 * Description : Internal function for adding an entry to the VLAN Filter Table.
2132
2133 * implements Netc_Eth_Ip_AddVLANFilterTableEntry_Activity
2134 *END**************************************************************************/
Netc_Eth_Ip_AddVLANFilterTableEntry(const uint8 ctrlIndex,const Netc_Eth_Ip_VLANFilterTableEntryDataType * VLANTableEntry)2135 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddVLANFilterTableEntry( const uint8 ctrlIndex, const Netc_Eth_Ip_VLANFilterTableEntryDataType *VLANTableEntry)
2136 {
2137 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2138
2139 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2140 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2141 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
2142 #endif
2143
2144 /* Fill in the configured data */
2145 Netc_Eth_Ip_TableData.Data0 = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SET_TPID(VLANTableEntry->TPID);
2146 Netc_Eth_Ip_TableData.Data0 |= (uint32)VLANTableEntry->VLANId;
2147 Netc_Eth_Ip_TableData.SI_Bitmap = VLANTableEntry->SIBitmap;
2148 Netc_Eth_Ip_TableData.Index = VLANTableEntry->VLANFilterTable_EID;
2149 /* Class 2 for VLAN Filter Table */
2150 Netc_Eth_Ip_TableData.Class = 2U;
2151 /* Command 0 for adding an entry to the VLAN Filter Table */
2152 Netc_Eth_Ip_TableData.Command = 0U;
2153 status = Netc_Eth_Ip_SendNTMP1Command_ShortFormat(ctrlIndex, &Netc_Eth_Ip_TableData);
2154 return status;
2155 }
2156
2157 /*FUNCTION**********************************************************************
2158 *
2159 * Function Name : Netc_Eth_Ip_QueryVLANFilterTableEntry
2160 * Description : Internal function for querying the VLAN Filter Table.
2161 *
2162 * implements Netc_Eth_Ip_QueryVLANFilterTableEntry_Activity
2163 *END**************************************************************************/
Netc_Eth_Ip_QueryVLANFilterTableEntry(const uint8 ctrlIndex,Netc_Eth_Ip_VLANFilterTableEntryDataType * VLANTableEntry)2164 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryVLANFilterTableEntry(const uint8 ctrlIndex, Netc_Eth_Ip_VLANFilterTableEntryDataType *VLANTableEntry)
2165 {
2166 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2167 uint32 producerIdx;
2168 uint32 lengthOfCmDB;
2169
2170 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2171 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2172 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
2173 #endif
2174
2175 /* Fill in the table entry ID */
2176 Netc_Eth_Ip_TableData.Index = VLANTableEntry->VLANFilterTable_EID;
2177 /* Class 2 for VLAN Filter Table */
2178 Netc_Eth_Ip_TableData.Class = 2U;
2179 /* Command 1 for adding an entry to the VLAN Filter Table */
2180 Netc_Eth_Ip_TableData.Command = 1U;
2181 status = Netc_Eth_Ip_SendNTMP1Command_ShortFormat(ctrlIndex, &Netc_Eth_Ip_TableData);
2182 producerIdx = netcSIsBase[ctrlIndex]->SICBDRPIR;
2183
2184 /* the value stored in producer index register indicates the index of next entry */
2185 if (producerIdx > 0UL)
2186 {
2187 producerIdx -= 1UL;
2188 }
2189 else /* producerIdx increased from 15 to 0, will set it to 15, or length minus 1 */
2190 {
2191 lengthOfCmDB = ((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD);
2192 producerIdx = lengthOfCmDB - 0x1UL;
2193 }
2194
2195 if (status == NETC_ETH_IP_STATUS_SUCCESS)
2196 {
2197 VLANTableEntry->TPID = (Netc_Eth_Ip_VlanProtocolIdentifierType)NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_GET_TPID(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L]);
2198 VLANTableEntry->VLANId = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L] & 0x00000FFFU);
2199 VLANTableEntry->SIBitmap = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_4]);
2200 }
2201 return status;
2202 }
2203
2204 #if (NETC_ETH_IP_NUMBER_OF_VLAN_FILTER_ENTRIES > 0)
2205 /*FUNCTION**********************************************************************
2206 *
2207 * Function Name : Netc_Eth_Ip_ConfigVLANFilterTable
2208 * Description : Add the configured entries to the VLAN Filter Table.
2209 *
2210 *END**************************************************************************/
Netc_Eth_Ip_ConfigVLANFilterTable(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2211 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigVLANFilterTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2212 {
2213 uint8 VLANFilterTableIdx;
2214 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2215 Netc_Eth_Ip_VLANFilterTableEntryDataType VLANTableEntry = {0};
2216
2217 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2218 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2219 #endif
2220
2221 for (VLANFilterTableIdx = 0U; VLANFilterTableIdx < Config->generalConfig->NumberOfVLANFilterEntries; VLANFilterTableIdx++)
2222 {
2223 VLANTableEntry = (*(Config->generalConfig->VLANTableEntries))[VLANFilterTableIdx];
2224 status = Netc_Eth_Ip_AddVLANFilterTableEntry(ctrlIndex, &VLANTableEntry);
2225 }
2226
2227 return status;
2228 }
2229 #endif
2230
2231 #if (NETC_ETH_IP_NUMBER_OF_RP_ENTRIES > 0)
2232 /*FUNCTION**********************************************************************
2233 *
2234 * Function Name : Netc_Eth_Ip_ConfigRatePolicerTable
2235 * Description : Add the configured entries to the Rate Policer Table.
2236 *
2237 *END**************************************************************************/
Netc_Eth_Ip_ConfigRatePolicerTable(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2238 static Std_ReturnType Netc_Eth_Ip_ConfigRatePolicerTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2239 {
2240 uint8 RPTableIdx;
2241 Std_ReturnType status = E_OK;
2242 Netc_Eth_Ip_StatusType CmdStatus = NETC_ETH_IP_STATUS_SUCCESS;
2243 Netc_Eth_Ip_RatePolicerEntryDataType RPTableEntry = {0};
2244 uint32 MatchedEntries = 0UL;
2245
2246 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2247 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2248 #endif
2249
2250 for (RPTableIdx = 0U; RPTableIdx < Config->generalConfig->NumberOfRPTableEntries; RPTableIdx++)
2251 {
2252 RPTableEntry = (*(Config->generalConfig->RPTableEntries))[RPTableIdx];
2253 CmdStatus = Netc_Eth_Ip_AddOrUpdateRatePolicerTableEntry(ctrlIndex, NETC_ETH_ADD_CMD, &MatchedEntries, &RPTableEntry);
2254
2255 if (CmdStatus != NETC_ETH_IP_STATUS_SUCCESS)
2256 {
2257 status = E_NOT_OK;
2258 break;
2259 }
2260 }
2261
2262 return status;
2263 }
2264 #endif
2265
2266 #if (NETC_ETH_NUMBER_OF_STREAMIDENTIFICATION_ENTRIES > 0U)
2267 /*FUNCTION**********************************************************************
2268 *
2269 * Function Name : Netc_Eth_Ip_ConfigISITable
2270 * Description : function for configuring the IngressStreamIdentification Table for the switch
2271 *
2272 *END**************************************************************************/
Netc_Eth_Ip_ConfigISITable(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2273 static Std_ReturnType Netc_Eth_Ip_ConfigISITable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2274 {
2275 uint32 MatchedEntries = 0U;
2276 uint8 FrmKeyWordIdx;
2277 uint8 IsiEntryIdx;
2278 Netc_Eth_Ip_IngrStremIdentificationTableDataType IsiTableEntry = {0};
2279
2280 Std_ReturnType status = E_OK;
2281 Netc_Eth_Ip_StatusType CBDRStatus;
2282
2283 /* Add key construction rules */
2284 IP_NETC__SW0_COMMON->ISIDKC0CR0 = (*(Config->generalConfig->EthKeyConstruction))[0U].EthKeyConstructionRegValue;
2285 IP_NETC__SW0_COMMON->ISIDKC1CR0 = (*(Config->generalConfig->EthKeyConstruction))[1U].EthKeyConstructionRegValue;
2286
2287 /* Add payload field values */
2288 IP_NETC__SW0_COMMON->ISIDKC0PF0CR = (*(Config->generalConfig->EthKeyConstruction))[0U].EthPayloadField0RegValue;
2289 IP_NETC__SW0_COMMON->ISIDKC0PF1CR = (*(Config->generalConfig->EthKeyConstruction))[0U].EthPayloadField1RegValue;
2290 IP_NETC__SW0_COMMON->ISIDKC1PF0CR = (*(Config->generalConfig->EthKeyConstruction))[1U].EthPayloadField0RegValue;
2291 IP_NETC__SW0_COMMON->ISIDKC1PF1CR = (*(Config->generalConfig->EthKeyConstruction))[1U].EthPayloadField1RegValue;
2292
2293 /* Add static IngressStreamIdentification entries */
2294 for (IsiEntryIdx = 0U; IsiEntryIdx < Config->generalConfig->NumberOfIsiEntries; IsiEntryIdx++)
2295 {
2296 IsiTableEntry.IngrStreamIdenResumeEntryId = (*(Config->generalConfig->IsiEntries))[IsiEntryIdx].IngrStreamIdenResumeEntryId;
2297 IsiTableEntry.IngrStreamIdenEntryId = (*(Config->generalConfig->IsiEntries))[IsiEntryIdx].IngrStreamIdenEntryId;
2298 IsiTableEntry.IngrStreamEntryId = (*(Config->generalConfig->IsiEntries))[IsiEntryIdx].IngrStreamEntryId;
2299 IsiTableEntry.Keye_Keytype = (*(Config->generalConfig->IsiEntries))[IsiEntryIdx].Keye_Keytype;
2300 for(FrmKeyWordIdx = 0; FrmKeyWordIdx < 3; FrmKeyWordIdx++)
2301 {
2302 IsiTableEntry.Keye_FrmKey[FrmKeyWordIdx] = (*(Config->generalConfig->IsiEntries))[IsiEntryIdx].Keye_FrmKey[FrmKeyWordIdx];
2303 }
2304 CBDRStatus = Netc_Eth_Ip_AddOrUpdateIngrStreamIdentificationTableEntry(ctrlIndex, NETC_ETH_ADD_CMD, &MatchedEntries, &IsiTableEntry);
2305 /* fail to add the static IngressStreamIdentification entry */
2306 if ((CBDRStatus != NETC_ETH_IP_STATUS_SUCCESS) || (MatchedEntries != 0U))
2307 {
2308 status = E_NOT_OK;
2309 break;
2310 }
2311
2312 }
2313 return status;
2314 }
2315 #endif
2316
2317 #if (NETC_ETH_NUMBER_OF_INGRESSSTREAM_ENTRIES > 0U)
2318 /*FUNCTION**********************************************************************
2319 *
2320 * Function Name : Netc_Eth_Ip_ConfigIngressStreamTable
2321 * Description : function for configuring the IngressStream Table for the switch
2322 *
2323 *END**************************************************************************/
Netc_Eth_Ip_ConfigIngressStreamTable(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2324 static Std_ReturnType Netc_Eth_Ip_ConfigIngressStreamTable(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2325 {
2326 uint32 MatchedEntries = 0U;
2327 uint8 IngrStrEntryIdx = 0U;
2328
2329 Std_ReturnType status = E_OK;
2330 Netc_Eth_Ip_StatusType CBDRStatus;
2331 Netc_Eth_Ip_IngressStreamEntryDataType IngrStrTableEntry = {0};
2332
2333 for (IngrStrEntryIdx = 0U; IngrStrEntryIdx < Config->generalConfig->NumberOfIngrStreamEntries; IngrStrEntryIdx++)
2334 {
2335 IngrStrTableEntry = (*(Config->generalConfig->IngressStreamEntries))[IngrStrEntryIdx];
2336
2337 /*Add Ingress Stream Table entry*/
2338 CBDRStatus = Netc_Eth_Ip_AddOrUpdateIngressStreamTableEntry(ctrlIndex, NETC_ETH_ADD_CMD, &MatchedEntries, &IngrStrTableEntry);
2339
2340 if (CBDRStatus != NETC_ETH_IP_STATUS_SUCCESS)
2341 {
2342 status = E_NOT_OK;
2343 break;
2344 }
2345
2346 }
2347
2348 return status;
2349 }
2350 #endif
2351
2352 #if (NETC_ETH_NUMBER_OF_SGCL_ENTRIES > 0U)
2353 /*FUNCTION**********************************************************************
2354 *
2355 * Function Name : Netc_Eth_Ip_ConfigSGCL
2356 * Description : function for configuring the Stream Gate Control Lists for the switch
2357 *
2358 *END**************************************************************************/
Netc_Eth_Ip_ConfigSGCL(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2359 static Std_ReturnType Netc_Eth_Ip_ConfigSGCL(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2360 {
2361 Std_ReturnType status = E_OK;
2362 Netc_Eth_Ip_StatusType CBDRStatus = NETC_ETH_IP_STATUS_SUCCESS;
2363 uint32 SGCLIndex = 0U;
2364 uint32 MatchedEntries = 0UL;
2365 Netc_Eth_Ip_SGCLTableDataType SGCLTableEntry = {0};
2366
2367 for (SGCLIndex = 0U; SGCLIndex < Config->generalConfig->NumberOfSGCLEntries; SGCLIndex++)
2368 {
2369 SGCLTableEntry = (*(Config->generalConfig->StreamGateControlListEntries))[SGCLIndex];
2370 CBDRStatus = Netc_Eth_Ip_AddStreamGateControlListTableEntry(ctrlIndex, NETC_ETH_ADD_CMD, &MatchedEntries, &SGCLTableEntry);
2371
2372 if (CBDRStatus != NETC_ETH_IP_STATUS_SUCCESS)
2373 {
2374 status = E_NOT_OK;
2375 break;
2376 }
2377 }
2378
2379 return status;
2380 }
2381 #endif
2382
2383 #if (NETC_ETH_NUMBER_OF_SGI_ENTRIES > 0U)
2384 /*FUNCTION**********************************************************************
2385 *
2386 * Function Name : Netc_Eth_Ip_ConfigSGI
2387 * Description : function for configuring the Stream Gate Instance Table for the switch
2388 *
2389 *END**************************************************************************/
Netc_Eth_Ip_ConfigSGI(uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2390 static Std_ReturnType Netc_Eth_Ip_ConfigSGI(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2391 {
2392 Std_ReturnType status = E_OK;
2393 Netc_Eth_Ip_StatusType CBDRStatus = NETC_ETH_IP_STATUS_SUCCESS;
2394 uint32 SGIIndex = 0U;
2395 uint32 MatchedEntries = 0UL;
2396 Netc_Eth_Ip_StreamGateInstanceEntryDataType SGITableEntry = {0};
2397
2398 for (SGIIndex = 0U; SGIIndex < Config->generalConfig->NumberOfSGIEntries; SGIIndex++)
2399 {
2400 SGITableEntry = (*(Config->generalConfig->StreamGateInstanceEntries))[SGIIndex];
2401 CBDRStatus = Netc_Eth_Ip_AddOrUpdateStreamGateInstanceTableEntry(ctrlIndex, NETC_ETH_ADD_CMD, &MatchedEntries, &SGITableEntry);
2402
2403 if (CBDRStatus != NETC_ETH_IP_STATUS_SUCCESS)
2404 {
2405 status = E_NOT_OK;
2406 break;
2407 }
2408 }
2409
2410 return status;
2411 }
2412 #endif
2413
2414 /*FUNCTION**********************************************************************
2415 *
2416 * Function Name : Netc_Eth_Ip_SendNTMP1Command_LongFormat
2417 * Description : Internal function for adding an entry with different commands to command ring (long format) for NTMP V1.0.
2418 *
2419 *END**************************************************************************/
Netc_Eth_Ip_SendNTMP1Command_LongFormat(uint8 CtrlIndex,const Netc_Eth_Ip_SetMessageHeaderTableOperationDataType * OperationData)2420 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendNTMP1Command_LongFormat(uint8 CtrlIndex, const Netc_Eth_Ip_SetMessageHeaderTableOperationDataType *OperationData)
2421 {
2422 uint32 producerIdx;
2423 uint32 consumerIdx;
2424 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2425 uint32 PreviousConsumerIdx;
2426 uint8 statusField;
2427 uint32 StartTime;
2428 uint32 ElapsedTime;
2429 uint32 TimeoutTicks;
2430 boolean TimeExpired;
2431
2432 /* read the producer and consumer index register */
2433 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
2434 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
2435
2436 /* check if the ring is full */
2437 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
2438 {
2439 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
2440 }
2441 else
2442 {
2443 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18();
2444 /* Fill in the configured data */
2445 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L] = OperationData->Data0;
2446 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_H] = 0x0UL;
2447 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_1] = 0x0UL;
2448 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_2] = 0x0UL;
2449 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_3] = 0x0UL;
2450 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_DATA_4] = 0x0UL;
2451 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_LENGTH_INDEX] = OperationData->Index | ((uint32)(OperationData->Length) << 16U);
2452
2453 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SF(OperationData->Format);
2454 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CI(0x0U);
2455 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_STATUS(0x0U);
2456 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CLASS(OperationData->Class);
2457 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_COMMAND(OperationData->Command);
2458 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18();
2459
2460
2461 /* +++ write the producer index register and enable hardware to consume the command +++ */
2462 PreviousConsumerIdx = consumerIdx;
2463 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == 0U) /* adjust producer index */
2464 {
2465 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, the producer index should start from 0 again */
2466 }
2467 else
2468 {
2469 producerIdx += 0x1UL; /* increase the producer index manually */
2470 }
2471
2472 /* This is needed to make sure the descriptor gets updated with the latest values, before
2473 incrementing the producer index to start the actual operation */
2474 MCAL_DATA_SYNC_BARRIER();
2475
2476 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
2477 /* --- write the produce index register and enable hardware to consume the command --- */
2478
2479 /* +++ to make sure the hardware consumes and processes the command completely +++ */
2480 /* Setup timeout timer */
2481 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
2482 do {
2483 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
2484 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
2485 } while ((consumerIdx == PreviousConsumerIdx) && (FALSE == TimeExpired)); /* wait the hardware consume the command. */
2486 /* --- to make sure the hardware consumes and processes the command completely --- */
2487
2488 if (TRUE == TimeExpired)
2489 {
2490 status = NETC_ETH_IP_STATUS_TIMEOUT;
2491 }
2492 else
2493 {
2494 statusField = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_RFS_GET_STATUS(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[consumerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD]); /* get status field in the response data buffer */
2495 if (statusField != 0U)
2496 {
2497 status = NETC_ETH_IP_STATUS_ERROR; /* STATUS field should be 0. */
2498 }
2499 }
2500 }
2501 return status;
2502 }
2503
2504 /*FUNCTION**********************************************************************
2505 *
2506 * Function Name : Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat
2507 * Description : Internal function for querying statistics of a RFS entry with t commands to command ring (short format) for NTMP V1.0.
2508 *
2509 *END**************************************************************************/
Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat(const uint8 CtrlIndex,const Netc_Eth_Ip_SetMessageHeaderTableOperationDataType * OperationData)2510 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat(const uint8 CtrlIndex, const Netc_Eth_Ip_SetMessageHeaderTableOperationDataType *OperationData)
2511 {
2512 uint32 producerIdx;
2513 uint32 consumerIdx;
2514 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2515 uint32 PreviousConsumerIdx;
2516 uint8 statusField;
2517 uint32 StartTime;
2518 uint32 ElapsedTime;
2519 uint32 TimeoutTicks;
2520 boolean TimeExpired;
2521
2522 /* read the producer and consumer index register */
2523 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
2524 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
2525
2526 /* check if the ring is full */
2527 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == consumerIdx)
2528 {
2529 status = NETC_ETH_IP_CBDRSTATUS_RINGFULL; /* the ring is full */
2530 }
2531 else
2532 {
2533 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19();
2534 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_LENGTH_INDEX] = OperationData->Index | (((uint32)(OperationData->Length)) << 16U);
2535 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_SF(OperationData->Format);
2536 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CI(0x0U);
2537 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_STATUS(0x0U);
2538 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_CLASS(OperationData->Class);
2539 Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD] |= NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_COMMAND(OperationData->Command);
2540 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19();
2541
2542
2543 /* +++ write the producer index register and enable hardware to consume the command +++ */
2544 PreviousConsumerIdx = consumerIdx;
2545 if (((producerIdx + 0x1UL) % ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD)) == 0U) /* adjust producer index */
2546 {
2547 producerIdx = 0x0UL; /* when producerIdx equals ACTUAL_CBDR_LENGTH minus 1, the producer index should start from 0 again */
2548 }
2549 else
2550 {
2551 producerIdx += 0x1UL; /* increase the producer index manually */
2552 }
2553
2554 /* This is needed to make sure the descriptor gets updated with the latest values, before
2555 incrementing the producer index to start the actual operation */
2556 MCAL_DATA_SYNC_BARRIER();
2557
2558 netcSIsBase[CtrlIndex]->SICBDRPIR = NETC_F3_SI0_SICBDRPIR_BDR_INDEX(producerIdx);
2559 /* --- write the produce index register and enable hardware to consume the command --- */
2560
2561 /* +++ to make sure the hardware consumes and processes the command completely +++ */
2562 /* Setup timeout timer */
2563 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
2564 do {
2565 consumerIdx = netcSIsBase[CtrlIndex]->SICBDRCIR;
2566 TimeExpired = Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
2567 } while ((consumerIdx == PreviousConsumerIdx) && (FALSE == TimeExpired)); /* wait the hardware consume the command. */
2568 /* --- to make sure the hardware consumes and processes the command completely --- */
2569
2570 if (TRUE == TimeExpired)
2571 {
2572 status = NETC_ETH_IP_STATUS_TIMEOUT;
2573 }
2574 else
2575 {
2576 statusField = NETC_ETH_IP_CMDBD_REQFMT_CONFIG_FIELD_RFS_GET_STATUS(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[consumerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_CMD]); /* get status field in the response data buffer */
2577 if (statusField != 0U)
2578 {
2579 status = NETC_ETH_IP_STATUS_ERROR; /* STATUS field should be 0. */
2580 }
2581 }
2582 }
2583 return status;
2584 }
2585
2586 /*FUNCTION**********************************************************************
2587 *
2588 * Function Name : Netc_Eth_Ip_FillRfsSetDataBuffer
2589 * Description : Internal function for filling a local static buffer with the configured data for a Rfs table entry
2590 *
2591 *END**************************************************************************/
Netc_Eth_Ip_FillRfsSetDataBuffer(uint32 * RfsSetDataBuffer,const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)2592 static void Netc_Eth_Ip_FillRfsSetDataBuffer(uint32 * RfsSetDataBuffer, const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)
2593 {
2594 uint8 i;
2595
2596 for(i = 0; i < NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE; i++)
2597 {
2598 RfsSetDataBuffer[i] = 0;
2599 }
2600
2601 /*EN, MODE, RESULT fields */
2602 RfsSetDataBuffer[28] = (uint32)(RfsTableEntry->Result) | ((uint32)(RfsTableEntry->Mode) << NETC_ETH_IP_RFS_ENTRY_MODE_FIELD_SHIFT) | ((uint32)(RfsTableEntry->Enable) << NETC_ETH_IP_RFS_ENTRY_EN_FIELD_SHIFT);
2603
2604 /*L4_PROTOCOL, L4_PROTOCOL_MASK, IP_PRESENT, IP_PRESENT_M, L4_PROT_PRESENT, L4_PROT_PRESENT_M,
2605 TCP_OR_UDP_PRESENT, TCP_OR_UDP_PRESENT_M, IPV4_IPV6, IPV4_IPV6_M, UDP_TCP, UDP_TCP_M fields */
2606 RfsSetDataBuffer[27] = (uint32)(RfsTableEntry->L4Protocol) | ((uint32)(RfsTableEntry->L4ProtocolMask) << NETC_ETH_IP_RFS_ENTRY_L4PROTMASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->IpPresent) << NETC_ETH_IP_RFS_ENTRY_IPPRESENT_FIELD_SHIFT)
2607 | ((uint32)(RfsTableEntry->IpPresentMask) << NETC_ETH_IP_RFS_ENTRY_IPPRESENTMASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->L4ProtPresent) << NETC_ETH_IP_RFS_ENTRY_L4PROTPRESENT_FIELD_SHIFT) | ((uint32)(RfsTableEntry->L4ProtPresentMask) << NETC_ETH_IP_RFS_ENTRY_L4PROTPRESENTMASK_FIELD_SHIFT)
2608 | ((uint32)(RfsTableEntry->TcpUdpPresent) << NETC_ETH_IP_RFS_ENTRY_TCPUDPPRESENT_FIELD_SHIFT) | ((uint32)(RfsTableEntry->TcpUdpPresentMask) << NETC_ETH_IP_RFS_ENTRY_TCPUDPPRESENTMASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->Ipv4Ipv6) << NETC_ETH_IP_RFS_ENTRY_IPV4IPV6_FIELD_SHIFT)
2609 | ((uint32)(RfsTableEntry->Ipv4Ipv6Mask)<< NETC_ETH_IP_RFS_ENTRY_IPV4IPV6MASK_FIELD_SHIFT) | ((uint32)(RfsTableEntry->UdpTcp) << NETC_ETH_IP_RFS_ENTRY_UDPTCP_FIELD_SHIFT) | ((uint32)(RfsTableEntry->UdpTcpMask) << NETC_ETH_IP_RFS_ENTRY_UDPTCPMASK_FIELD_SHIFT);
2610
2611 /* RFS Table bytes (Offset 0x68) corresponding to RfsSetDataBuffer position 26 are reserved */
2612
2613 /*L4_DEST_PORT, L4_DEST_PORT_MASK fields */
2614 RfsSetDataBuffer[25] = (uint32) (RfsTableEntry->L4DestPort) | (uint32)(RfsTableEntry->L4DestPortMask << NETC_ETH_IP_RFS_ENTRY_L4DESTPORTMASK_FIELD_SHIFT);
2615
2616 /*L4_SOURCE_PORT, L4_SOURCE_PORT_MASK fields */
2617 RfsSetDataBuffer[24] = (uint32) (RfsTableEntry->L4SrcPort) | (uint32)(RfsTableEntry->L4SrcPortMask << NETC_ETH_IP_RFS_ENTRY_L4SRCPORTMASK_FIELD_SHIFT);
2618
2619 /* RFS Table bytes (Offset 0x5C and 0x58) corresponding to RfsSetDataBuffer positions 23 and 22 are reserved */
2620
2621 /*DEST_IP_ADDR_MASK field*/
2622 RfsSetDataBuffer[21] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrMaskHigh);
2623 RfsSetDataBuffer[20] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrMaskHigh);
2624 RfsSetDataBuffer[19] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrMaskLow);
2625 RfsSetDataBuffer[18] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrMaskLow);
2626
2627 /*DEST_IP_ADDR field*/
2628 RfsSetDataBuffer[17] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrHigh);
2629 RfsSetDataBuffer[16] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrHigh);
2630 RfsSetDataBuffer[15] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->DestIpAddrLow);
2631 RfsSetDataBuffer[14] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->DestIpAddrLow);
2632
2633 /*SRC_IP_ADDR_MASK field*/
2634 RfsSetDataBuffer[13] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrMaskHigh);
2635 RfsSetDataBuffer[12] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrMaskHigh);
2636 RfsSetDataBuffer[11] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrMaskLow);
2637 RfsSetDataBuffer[10] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrMaskLow);
2638
2639 /*SRC_IP_ADDR field*/
2640 RfsSetDataBuffer[9] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrHigh);
2641 RfsSetDataBuffer[8] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrHigh);
2642 RfsSetDataBuffer[7] = (uint32) NETC_ETH_IP_64BYTE_TO_SECOND_WORD(RfsTableEntry->SrcIpAddrLow);
2643 RfsSetDataBuffer[6] = (uint32) NETC_ETH_IP_64BYTE_TO_FIRST_WORD(RfsTableEntry->SrcIpAddrLow);
2644
2645 /* RFS Table bytes (Offset 0x00 to 0x14) corresponding to RfsSetDataBuffer positions 0 to 15 are reserved */
2646 }
2647
2648 /*FUNCTION**********************************************************************
2649 *
2650 * Function Name : Netc_Eth_Ip_SetRfsTableEntry
2651 * Description : Internal function for adding an entry to the Rceive Flow Steering Table.
2652 *
2653 * implements Netc_Eth_Ip_AddRfsTableEntry_Activity
2654 *END**************************************************************************/
Netc_Eth_Ip_AddRfsTableEntry(const uint8 ctrlIndex,const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)2655 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddRfsTableEntry(const uint8 ctrlIndex, const Netc_Eth_Ip_RfsEntryType * RfsTableEntry)
2656 {
2657 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2658
2659
2660 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2661 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2662 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
2663 #endif
2664
2665 /* Fill in the configured data. */
2666 Netc_Eth_Ip_FillRfsSetDataBuffer(Netc_Eth_Ip_RfsSetDataBuffer, RfsTableEntry);
2667
2668 /* RFS Data buffer address.
2669 There is an alignment restrictions for the data address to be 16-byte aligned;
2670 hardware ignores the least significant 4 bits of the ADDR field. */
2671 Netc_Eth_Ip_TableData.Data0 = (uint32) &Netc_Eth_Ip_RfsSetDataBuffer;
2672 Netc_Eth_Ip_TableData.Length = (uint16)( NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE * 4U);
2673 Netc_Eth_Ip_TableData.Index = RfsTableEntry->RfsTableEntryId;
2674
2675 /*Set the format to Long format */
2676 Netc_Eth_Ip_TableData.Format = 0;
2677 /* Class 4 for RFS Table */
2678 Netc_Eth_Ip_TableData.Class = 4U;
2679 /* Command 0 for adding an entry to the RFS Table */
2680 Netc_Eth_Ip_TableData.Command = 0U;
2681 status = Netc_Eth_Ip_SendNTMP1Command_LongFormat(ctrlIndex, &Netc_Eth_Ip_TableData);
2682 return status;
2683 }
2684
2685 /*FUNCTION**********************************************************************
2686 *
2687 * Function Name : Netc_Eth_Ip_QueryRfsTableEntry
2688 * Description : Internal function for querying the Receive Flow Steering Table.
2689 *
2690 * implements Netc_Eth_Ip_QueryRfsTableEntry_Activity
2691 *END**************************************************************************/
Netc_Eth_Ip_QueryRfsTableEntry(const uint8 ctrlIndex,uint8 RfsEntryIdx,uint32 * RfsTableEntryAddr)2692 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryRfsTableEntry(const uint8 ctrlIndex, uint8 RfsEntryIdx, uint32 * RfsTableEntryAddr)
2693 {
2694 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2695
2696 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2697 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2698 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
2699 #endif
2700
2701 /* Fill in the table entry ID */
2702 Netc_Eth_Ip_TableData.Index = RfsEntryIdx;
2703 /* Fill in the table entry address */
2704 Netc_Eth_Ip_TableData.Data0 = (uint32)RfsTableEntryAddr;
2705 /* Fill in the table entry length */
2706 Netc_Eth_Ip_TableData.Length = (uint16)( NETC_ETH_RFS_ENTRY_SET_DATA_BUFFER_SIZE * 4U);
2707 /* Class 4 for RFS Table */
2708 Netc_Eth_Ip_TableData.Class = 4U;
2709 /* Command 1 for adding an querrying to the RFS Table (Long format) */
2710 Netc_Eth_Ip_TableData.Command = 1U;
2711 /*Long format*/
2712 Netc_Eth_Ip_TableData.Format = 0U;
2713
2714 status = Netc_Eth_Ip_SendNTMP1Command_LongFormat(ctrlIndex, &Netc_Eth_Ip_TableData);
2715
2716 return status;
2717 }
2718
2719 /*FUNCTION**********************************************************************
2720 *
2721 * Function Name : Netc_Eth_Ip_QueryStatisticsRfsTableEntry
2722 * Description : Internal function for querying the Receive Flow Steering Table.
2723 *
2724 * implements Netc_Eth_Ip_QueryStatisticsRfsTableEntry_Activity
2725 *END**************************************************************************/
Netc_Eth_Ip_QueryStatisticsRfsTableEntry(const uint8 ctrlIndex,uint8 RfsEntryIdx,uint32 * MatchedFramesNb)2726 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryStatisticsRfsTableEntry(const uint8 ctrlIndex, uint8 RfsEntryIdx, uint32 * MatchedFramesNb)
2727 {
2728 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2729 uint32 producerIdx;
2730 uint32 lengthOfCmDB;
2731
2732 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2733 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2734 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
2735 #endif
2736
2737 /* Fill in the table entry ID */
2738 Netc_Eth_Ip_TableData.Index = RfsEntryIdx;
2739 /* Class 4 for RFS Table */
2740 Netc_Eth_Ip_TableData.Class = 4U;
2741 /* Command 1 for adding an querrying statistical information for RFS Table Entry (Short Format) */
2742 Netc_Eth_Ip_TableData.Command = 2U;
2743 /*Short Format*/
2744 Netc_Eth_Ip_TableData.Format = 1U;
2745
2746 /*To check what format should be sent here*/
2747 status = Netc_Eth_Ip_SendNTMP1Command_RfsShortFormat(ctrlIndex, &Netc_Eth_Ip_TableData);
2748
2749 producerIdx = netcSIsBase[ctrlIndex]->SICBDRPIR;
2750
2751 /* the value stored in producer index register indicates the index of next entry */
2752 if (producerIdx > 0UL)
2753 {
2754 producerIdx -= 1UL;
2755 }
2756 else /* producerIdx increased from 15 to 0, will set it to 15, or length minus 1 */
2757 {
2758 lengthOfCmDB = ((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD);
2759 producerIdx = lengthOfCmDB - 0x1UL;
2760 }
2761
2762 if (status == NETC_ETH_IP_STATUS_SUCCESS)
2763 {
2764 /*Get the number of matched frames */
2765 *MatchedFramesNb = Netc_Eth_Ip_apxState[ctrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_CBD_ADDR_L];
2766 }
2767 return status;
2768 }
2769
2770 /*FUNCTION**********************************************************************
2771 *
2772 * Function Name : Netc_Eth_Ip_ConfigRfsTable
2773 * Description : Add the configured entries to the Receive Flow Steering Table.
2774 *
2775 *END**************************************************************************/
Netc_Eth_Ip_ConfigRfsTable(const uint8 ctrlIndex,const Netc_Eth_Ip_ConfigType * Config)2776 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigRfsTable(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType * Config)
2777 {
2778 uint32 RfsTableIdx;
2779 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2780 Netc_Eth_Ip_RfsEntryType RfsTableEntry = {0};
2781
2782 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2783 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2784 #endif
2785
2786 /*Add configured entries into the RFS table*/
2787 for (RfsTableIdx = 0U; RfsTableIdx < Config->RfsEntriesNb; RfsTableIdx++)
2788 {
2789 RfsTableEntry = (*(Config->RfsConfigTable))[RfsTableIdx];
2790 status = Netc_Eth_Ip_AddRfsTableEntry(ctrlIndex, &RfsTableEntry);
2791 }
2792
2793 /* Enable Port Receive Flow Steering Mode */
2794 IP_NETC__ENETC0_BASE->PRFSMR = NETC_F3_PRFSMR_RFSE(1);
2795
2796 return status;
2797 }
2798
2799 /*FUNCTION**********************************************************************
2800 *
2801 * Function Name : Netc_Eth_Ip_ConfigPortTimeGateScheduling
2802 * Description : Ethernet ENETC enables or disables Time Gate Scheduling function.
2803 *
2804 * implements Netc_Eth_Ip_ConfigPortTimeGateScheduling_Activity
2805 *END**************************************************************************/
Netc_Eth_Ip_ConfigPortTimeGateScheduling(const uint8 CtrlIndex,const boolean Enable)2806 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ConfigPortTimeGateScheduling( const uint8 CtrlIndex, const boolean Enable )
2807 {
2808 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2809 uint32 RegValue;
2810
2811 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2812 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2813 #endif
2814
2815 (void)CtrlIndex;
2816 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13();
2817 /* read the reg value first */
2818 RegValue = IP_NETC__ENETC0_PORT->PTGSCR;
2819 if ((RegValue & ENETC_PORT_PTGSCR_TGE_MASK) != ENETC_PORT_PTGSCR_TGE_MASK) /* time gating is disabled */
2820 {
2821 if (TRUE == Enable)
2822 {
2823 Netc_Eth_Ip_ConfigPortTimeGateScheduling_GateControlState(&RegValue, &status);
2824 }
2825 }
2826 else /* time gating is enabled */
2827 {
2828 if (FALSE == Enable)
2829 {
2830 RegValue &= ~ENETC_PORT_PTGSCR_TGE(1U); /* Disable time gating */
2831 }
2832 }
2833
2834 if (status == NETC_ETH_IP_STATUS_SUCCESS)
2835 {
2836 /* write it back. */
2837 IP_NETC__ENETC0_PORT->PTGSCR = RegValue;
2838 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13();
2839
2840 /* if time gate scheduling is enabled, and entry data is configured, then adds the entry */
2841 if ( (TRUE == Enable) && (TRUE == Netc_Eth_Ip_PortTimeAwareShaperEnabled))
2842 {
2843 status = Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry(0U, &Netc_Eth_Ip_EthTimeGateSchedulingEntryData);
2844 /* fail to add or update the time gate schedulling table entry */
2845 if (status != NETC_ETH_IP_STATUS_SUCCESS)
2846 {
2847 status = NETC_ETH_IP_STATUS_ERROR;
2848 }
2849 }
2850 }
2851 else
2852 {
2853 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13();
2854 }
2855
2856 return status;
2857 }
2858
FillInGateControlListData(const uint8 * OperationTimeIdx,const Netc_Eth_Ip_TimeGateSchedulingEntryDataType * TimeGateSchedulingTableEntry)2859 static inline void FillInGateControlListData(const uint8 *OperationTimeIdx, const Netc_Eth_Ip_TimeGateSchedulingEntryDataType *TimeGateSchedulingTableEntry)
2860 {
2861 uint8 CFGEDataIdx;
2862 uint16 GateEntryIdx;
2863 uint8 HostRequest;
2864
2865 if (*OperationTimeIdx == 1U)
2866 {
2867 CFGEDataIdx = 0U;
2868
2869 for (GateEntryIdx = 0U; GateEntryIdx < TimeGateSchedulingTableEntry->AdminControlListLength; GateEntryIdx++)
2870 {
2871 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)(NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA5) + CFGEDataIdx] = TimeGateSchedulingTableEntry->GateEntryAdminControlListData[GateEntryIdx].AdminTimeInterval;
2872 /* convert gate operation type */
2873 switch (TimeGateSchedulingTableEntry->GateEntryAdminControlListData[GateEntryIdx].AdminGateOperationType)
2874 {
2875 case NETC_ETH_HOST_REQUEST_UNCHANGED:
2876 HostRequest = 0U;
2877 break;
2878 case NETC_ETH_HOST_REQUEST_HOLD:
2879 HostRequest = 1U;
2880 break;
2881 case NETC_ETH_HOST_REQUEST_RELEASE:
2882 HostRequest = 2U;
2883 break;
2884 default:
2885 HostRequest = 0U;
2886 break;
2887 }
2888 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)(NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA6) + CFGEDataIdx] = NETC_ETH_IP_TGSTABLE_CFGE_ADMIN_TC_STATES(TimeGateSchedulingTableEntry->GateEntryAdminControlListData[GateEntryIdx].AdminTrafficClassGateStates) \
2889 | NETC_ETH_IP_TGSTABLE_CFGE_ADMIN_HR_CB(HostRequest);
2890
2891 CFGEDataIdx += 2U; /* CFGE data field index increased by 2 */
2892 }
2893
2894 }
2895 }
2896
2897 /*FUNCTION**********************************************************************
2898 *
2899 * Function Name : Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry
2900 * Description : Ethernet ENETC adds or updates Time Gate Scheduling table entry function.
2901 *
2902 * implements Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry_Activity
2903 *END**************************************************************************/
Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry(const uint8 CtrlIndex,const Netc_Eth_Ip_TimeGateSchedulingEntryDataType * TimeGateSchedulingTableEntry)2904 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateTimeGateSchedulingTableEntry( const uint8 CtrlIndex,
2905 const Netc_Eth_Ip_TimeGateSchedulingEntryDataType *TimeGateSchedulingTableEntry
2906 )
2907 {
2908 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
2909 uint8 OperationTimes;
2910 uint8 OperationTimeIdx;
2911 volatile uint64 CurrentTime = 0;
2912 uint32 CycleFactor;
2913 uint64 NewBaseTime;
2914 uint32 LookaheadTime;
2915 #if defined(ERR_IPV_NETC_051587)
2916 #if (STD_ON == ERR_IPV_NETC_051587)
2917 uint32 AdminCtrlListLength;
2918 uint32 CmdProccesingTime;
2919 uint64 CalculatedTime;
2920 uint32 NetcClkPeriod;
2921 #endif
2922 #endif
2923
2924 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
2925 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
2926 DevAssert(TimeGateSchedulingTableEntry != NULL_PTR);
2927 #endif
2928
2929 /* AdminControlListLength = 0U means to reset the gate control list or add the time gate scheduling entry without gate control list */
2930 OperationTimes = (TimeGateSchedulingTableEntry->AdminControlListLength > 0U) ? 2U : 1U;
2931
2932 /* for adding or updating gate control list, we'll have to remove the gate control list firstly */
2933 for (OperationTimeIdx = 0U; OperationTimeIdx < OperationTimes; OperationTimeIdx++)
2934 {
2935 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14();
2936 /* ++++++ initialize the table request data buffer ++++++ */
2937 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(1U); /* fill in Actions field */
2938 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = TimeGateSchedulingTableEntry->TimeGateSchedulingTable_EID; /* fill in Entry ID */
2939 /* fill in CFGE_DATA */
2940 /* get the current time from 1588 timer */
2941 CurrentTime = Netc_EthSwt_Ip_TimerBase->TMR_CUR_TIME_L; /* should read the Lower register first */
2942 CurrentTime |= ((uint64)(Netc_EthSwt_Ip_TimerBase->TMR_CUR_TIME_H)) << NETC_ETH_IP_32BIT_SHIFT;
2943 /* get lookaheadtime */
2944 LookaheadTime = IP_NETC__NETC_IERB->CFG_ENETC_INST[0U].ETGSLR + IP_NETC__ENETC0_PORT->PTGSATOR;
2945
2946 /* calculate the NewBaseTime */
2947 #if defined(ERR_IPV_NETC_051587)
2948 #if (STD_ON == ERR_IPV_NETC_051587)
2949 NetcClkPeriod = (Netc_EthSwt_Ip_TimerBase->TMR_CTRL & TMR0_BASE_TMR_CTRL_TCLK_PERIOD_MASK) >> TMR0_BASE_TMR_CTRL_TCLK_PERIOD_SHIFT;
2950 AdminCtrlListLength = (uint32)(TimeGateSchedulingTableEntry->AdminControlListLength);
2951 CmdProccesingTime = (300U + ((uint32)(AdminCtrlListLength)*7U) + (AdminCtrlListLength*AdminCtrlListLength*5U)) * NetcClkPeriod;
2952 CalculatedTime = (uint64)CurrentTime + (uint64)LookaheadTime + (uint64)CmdProccesingTime + ((uint64)2U * (uint64)TimeGateSchedulingTableEntry->AdminCycleTime);
2953
2954 if ((Netc_Eth_Ip_TGSAdminListRegistered == (boolean)FALSE) || \
2955 (TimeGateSchedulingTableEntry->AdminBaseTime >= CalculatedTime))
2956 #else
2957 if (TimeGateSchedulingTableEntry->AdminBaseTime >= (CurrentTime + LookaheadTime))
2958 #endif
2959 #else
2960 if (TimeGateSchedulingTableEntry->AdminBaseTime >= (CurrentTime + LookaheadTime))
2961 #endif
2962 {
2963 NewBaseTime = TimeGateSchedulingTableEntry->AdminBaseTime;
2964 }
2965 else
2966 {
2967 #if defined(ERR_IPV_NETC_051587)
2968 #if (STD_ON == ERR_IPV_NETC_051587)
2969 CycleFactor = (uint32)(((((uint64)CurrentTime + (uint64)LookaheadTime + (uint64)CmdProccesingTime) - TimeGateSchedulingTableEntry->AdminBaseTime) / (uint64)TimeGateSchedulingTableEntry->AdminCycleTime) + 2U);
2970 #else
2971 CycleFactor = ((uint32)(CurrentTime + LookaheadTime - TimeGateSchedulingTableEntry->AdminBaseTime)) / (TimeGateSchedulingTableEntry->AdminCycleTime);
2972 #endif
2973 #else
2974 CycleFactor = ((uint32)(CurrentTime + LookaheadTime - TimeGateSchedulingTableEntry->AdminBaseTime)) / (TimeGateSchedulingTableEntry->AdminCycleTime);
2975 #endif
2976 NewBaseTime = TimeGateSchedulingTableEntry->AdminBaseTime + (((uint64)CycleFactor + 1UL) * (uint64)(TimeGateSchedulingTableEntry->AdminCycleTime));
2977 }
2978 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = (uint32)(NewBaseTime & (0xFFFFFFFFUL));
2979 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = (uint32)(NewBaseTime >> NETC_ETH_IP_32BIT_SHIFT);
2980 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2] = TimeGateSchedulingTableEntry->AdminCycleTime;
2981 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3] = TimeGateSchedulingTableEntry->AdminCycleTimeExt;
2982 /* set Administrative Control List Length to 0 for removing the admin gate control list or adding an entry with no administrative gate control list */
2983 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = (OperationTimeIdx == 0U) ? 0x0UL : (uint32)(TimeGateSchedulingTableEntry->AdminControlListLength);
2984
2985 FillInGateControlListData(&OperationTimeIdx, TimeGateSchedulingTableEntry);
2986 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14();
2987
2988 /* ------ initialize the table request data buffer ------ */
2989
2990 /* fill in operation data for config field of Request Header*/
2991 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
2992 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
2993 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_TIME_GATE_SCHEDULING_TABLE_ID;
2994 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* only support NETC_ETH_ENTRY_ID_MATCH method */
2995 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_UPDATE_CMD; /* can only use "update" command to add or update an time gate scheduling table entry */
2996 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TGSTABLE_ADD_REQBUFFER_LEN);
2997 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TGSTABLE_RSPBUFFER_LEN);
2998
2999 /* send "update" command to add/remove gate control list */
3000 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3001
3002 #if defined(ERR_IPV_NETC_051254)
3003 #if (STD_ON == ERR_IPV_NETC_051254)
3004 if (NETC_ETH_CBDRSTATUS_ADMIN_BASE_TIME_IS_MORE_THAN_1S == status)
3005 {
3006 /* set Administrative Control List Length to 0 for removing the admin gate control list */
3007 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = 0x0UL;
3008 FillInGateControlListData(&OperationTimeIdx, TimeGateSchedulingTableEntry);
3009
3010 /* send "update" command to remove gate control list */
3011 (void)Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3012
3013 }
3014 #endif
3015 #endif
3016 #if defined(ERR_IPV_NETC_051243)
3017 #if (STD_ON == ERR_IPV_NETC_051243)
3018 /* Error code 0x8A is not a real error. check it on Errata. */
3019 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3020 {
3021 status = NETC_ETH_IP_STATUS_SUCCESS;
3022 }
3023 #endif
3024 #endif
3025 }
3026
3027 #if defined(ERR_IPV_NETC_051587)
3028 #if (STD_ON == ERR_IPV_NETC_051587)
3029 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3030 {
3031 Netc_Eth_Ip_TGSAdminListRegistered = (boolean)TRUE;
3032 }
3033 #endif
3034 #endif
3035
3036 return status;
3037 }
3038
3039 /* inline function for initializing time gate scheduling table entries data during ENETC init */
Netc_Eth_Ip_InitTimeGateSchedulingTableEntryData(const Netc_Eth_Ip_ConfigType * Config)3040 static inline void Netc_Eth_Ip_InitTimeGateSchedulingTableEntryData(const Netc_Eth_Ip_ConfigType * Config)
3041 {
3042 uint8 GateControlListIdx;
3043
3044 if (((*Config->generalConfig).portTimeAwareShaperEnable) == TRUE)
3045 {
3046 /* set the flag for ports */
3047 Netc_Eth_Ip_PortTimeAwareShaperEnabled = TRUE;
3048
3049 /* write register PTGSATOR. */
3050 IP_NETC__ENETC0_PORT->PTGSATOR = (uint32)((*Config->generalConfig).portTimeGateSchedulingAdvanceTimeOffsetReg);
3051
3052 /* Fill in the data structure for time gate scheduling */
3053 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.TimeGateSchedulingTable_EID = 0U;
3054 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminBaseTime = (*Config->generalConfig).portEgressAdminBaseTime;
3055 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTime = (*Config->generalConfig).portEgressAdminCycleTime;
3056 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTimeExt = (*Config->generalConfig).portEgressAdminCycleTimeExt;
3057 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength = (*Config->generalConfig).numberOfGateControlListEntries;
3058 for (GateControlListIdx = 0U; GateControlListIdx < Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength; GateControlListIdx++)
3059 {
3060 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[GateControlListIdx].AdminTimeInterval = (*(*Config->generalConfig).TimeGateControlListEntries)[GateControlListIdx].AdminTimeInterval;
3061 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[GateControlListIdx].AdminTrafficClassGateStates = (*(*Config->generalConfig).TimeGateControlListEntries)[GateControlListIdx].AdminTrafficClassGateStates;
3062 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[GateControlListIdx].AdminGateOperationType = (*(*Config->generalConfig).TimeGateControlListEntries)[GateControlListIdx].AdminGateOperationType;
3063 }
3064 }
3065
3066 }
3067
3068 #if defined(ERR_IPV_NETC_E051130)
3069 #if (STD_ON == ERR_IPV_NETC_E051130)
3070 /* Workaround for ERR051130:
3071 Egress time gate scheduling can get corrupted when functional level reset is applied or when time gating is disabled
3072 */
3073 /* Added 2 fake time gate control list entries for clearing the internal context for time gate scheduling feature */
Netc_Eth_Ip_InitTimeGateSchedulingFeature(uint8 ctrlIndex)3074 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_InitTimeGateSchedulingFeature(uint8 ctrlIndex)
3075 {
3076 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
3077 volatile uint64 CurrentTime = 0;
3078 uint8 EntryIdx;
3079
3080 /* fill in struct Netc_Eth_Ip_TimeGateSchedulingEntryDataType */
3081 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.TimeGateSchedulingTable_EID = 0U; /* for pseudo port of ENETC */
3082 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTime = 4000000U; /* it should be greater than the sum of time interval */
3083 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminCycleTimeExt = 100000U;
3084 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength = 2U; /* 2 entries */
3085
3086 /* get the current time from 1588 timer */
3087 CurrentTime = Netc_EthSwt_Ip_TimerBase->TMR_CUR_TIME_L; /* should read the Lower register first */
3088 CurrentTime |= ((uint64)(Netc_EthSwt_Ip_TimerBase->TMR_CUR_TIME_H)) << NETC_ETH_IP_32BIT_SHIFT;
3089 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminBaseTime = CurrentTime; /* set base time to current time */
3090
3091 /* fill in gate control list entries data */
3092 for (EntryIdx = 0U; EntryIdx < Netc_Eth_Ip_EthTimeGateSchedulingEntryData.AdminControlListLength; EntryIdx++)
3093 {
3094 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[EntryIdx].AdminTimeInterval = 2000000U; /* the value is equal to transmit 128bytes + 20 bytes (header) frame with port speed 10M */
3095 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[EntryIdx].AdminTrafficClassGateStates = 0xFFU; /* all open */
3096 Netc_Eth_Ip_EthTimeGateSchedulingEntryData.GateEntryAdminControlListData[EntryIdx].AdminGateOperationType = NETC_ETH_HOST_REQUEST_UNCHANGED;
3097 }
3098
3099 /* add these 2 gate control list entries */
3100 Status = Netc_Eth_Ip_ConfigPortTimeGateScheduling(ctrlIndex, TRUE);
3101
3102 return Status;
3103 }
3104 #endif
3105 #endif
3106
3107 /*FUNCTION**********************************************************************
3108 *
3109 * Function Name : Netc_Eth_Ip_GetMatchedEntries
3110 * Description : Function for getting matched table entries. Num_Matched field indicates if it matches an entry.
3111 *
3112 *END**************************************************************************/
Netc_Eth_Ip_GetMatchedEntries(uint8 CtrlIndex,uint32 * NumOfEntry)3113 static void Netc_Eth_Ip_GetMatchedEntries(uint8 CtrlIndex, uint32 *NumOfEntry)
3114 {
3115 uint32 producerIdx;
3116 uint32 statusField;
3117 uint32 lengthOfCmDB;
3118
3119 producerIdx = netcSIsBase[CtrlIndex]->SICBDRPIR;
3120
3121 /* the value stored in producer index register indicates the index of next entry */
3122 if (producerIdx > 0UL)
3123 {
3124 producerIdx -= 1UL;
3125 }
3126 else /* producerIdx increased from 15 to 0, will set it to 15, or length minus 1 */
3127 {
3128 lengthOfCmDB = ((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.lengthCBDR) * NETC_ETH_IP_SET_OF_BD);
3129 producerIdx = lengthOfCmDB - 0x1UL;
3130 }
3131
3132 /* get status field in the response data buffer for the matched fdb entry */
3133 statusField = Netc_Eth_Ip_apxState[CtrlIndex]->EnetcCommandBDConfig.commandBDAddr[producerIdx].MessageHeaderDataField[NETC_ETH_IP_RSPHEADER_STATUS_FIELD_INDEX];
3134
3135 /* NUM_MATCHED should equal or greater than 1 if the entry exists for any commands. */
3136 *NumOfEntry = (statusField & (NETC_ETH_IP_CMDBD_RSPFMT_STATUS_FIELD_NUMMATCHED_MASK));
3137
3138 }
3139
Netc_Eth_Ip_AddOrUpdateRatePolicerTableEntry(const uint8 CtrlIndex,Netc_Eth_Ip_CommandsType Cmd,uint32 * MatchedEntries,const Netc_Eth_Ip_RatePolicerEntryDataType * RatePolicerTableEntry)3140 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateRatePolicerTableEntry( const uint8 CtrlIndex,
3141 Netc_Eth_Ip_CommandsType Cmd,
3142 uint32 *MatchedEntries,
3143 const Netc_Eth_Ip_RatePolicerEntryDataType * RatePolicerTableEntry
3144 )
3145 {
3146 Netc_Eth_Ip_StatusType status;
3147 uint32 ActionsData;
3148
3149 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3150 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3151 DevAssert(RatePolicerTableEntry != NULL_PTR);
3152 DevAssert(MatchedEntries != NULL_PTR);
3153 #endif
3154
3155 /* clear the variable MatchedEntries first */
3156 *MatchedEntries = 0U;
3157
3158 /* only support Add and Update commands */
3159 if ((NETC_ETH_ADD_CMD != Cmd) && (NETC_ETH_UPDATE_CMD != Cmd))
3160 {
3161 status = NETC_ETH_IP_STATUS_UNSUPPORTED; /* not supported command */
3162 }
3163 else
3164 {
3165 /* set table version and CFGEU, FEEU, ... flag */
3166 ActionsData = (NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(RatePolicerTableEntry->ConfigurationElementUpdate ? 1U : 0U) \
3167 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_FEEU(RatePolicerTableEntry->FunctionalEnableElementUpdate ? 1U : 0U)) \
3168 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_PSEU(RatePolicerTableEntry->PolicerStateElementUpdate ? 1U : 0U) \
3169 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_STSEU(RatePolicerTableEntry->StatisticsElementUpdate ? 1U : 0U) \
3170 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3171
3172 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15();
3173 /* ------initialize the table request data buffer------ */
3174 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3175 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = RatePolicerTableEntry->RatePolicerEntryId; /* fill in Entry_ID field (Access Key) */
3176 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cir; /* CFGE CIR field */
3177 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cbs; /* CFGE CBS field */
3178 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Eir; /* CFGE EIR field */
3179 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3] = RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ebs; /* CFGE EBS field */
3180 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_MREN((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Mren) ? 1U : 0U) \
3181 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_DOY((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Doy) ? 1U : 0U) \
3182 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CM((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cm) ? 1U : 0U) \
3183 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CF((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cf) ? 1U : 0U) \
3184 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_NDOR((RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ndor) ? 1U : 0U) \
3185 | NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_SDU_TYPE(RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType);
3186
3187 /* fill in Functional Enable Element Data */
3188 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] |= (NETC_ETH_IP_RATEPOLICERTABLE_FEE_DATA_FEN(RatePolicerTableEntry->RatePolicerFunctionEnable ? 1U : 0U) << NETC_ETH_IP_16BIT_SHIFT);
3189 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15();
3190
3191 /* fill in operation data for config field of Request Header*/
3192 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3193 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3194 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_RATE_POLICER_TABLE_ID;
3195 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for Add and Update command, the Access Method should only be NETC_ETH_ENTRY_ID_MATCH */
3196 Netc_Eth_Ip_OperationData.Cmd = Cmd;
3197 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_RATEPOLICERTABLE_REQBUFFER_LEN);
3198 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN);
3199
3200 /* send command */
3201 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3202 #if defined(ERR_IPV_NETC_051243)
3203 #if (STD_ON == ERR_IPV_NETC_051243)
3204 /* Error code 0x8A is not a real error. check it on Errata. */
3205 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3206 {
3207 #endif
3208 #else
3209 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3210 {
3211 #endif
3212 status = NETC_ETH_IP_STATUS_SUCCESS;
3213 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3214 }
3215 }
3216
3217 return status;
3218 }
3219
3220 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryRatePolicerTableEntry( const uint8 CtrlIndex,
3221 uint32 *MatchedEntries,
3222 uint32 RatePolicerEntryId,
3223 Netc_Eth_Ip_RatePolicerEntryRspDataType * RatePolicerTableEntry
3224 )
3225 {
3226 Netc_Eth_Ip_StatusType status;
3227 uint32 ActionsData;
3228 uint32 CfgeConfigBits;
3229 uint8 SduType;
3230 uint64 TempTableDataField;
3231
3232 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3233 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3234 DevAssert(MatchedEntries != NULL_PTR);
3235 DevAssert(RatePolicerTableEntry != NULL_PTR);
3236 #endif
3237
3238 /* clear the variable MatchedEntries first */
3239 *MatchedEntries = 0U;
3240
3241 /* always do the full query. 0x0 = Full query. */
3242 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
3243 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3244
3245 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21();
3246 /* ------initialize the table request data buffer------ */
3247 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3248 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = RatePolicerEntryId; /* fill in Entry_ID field (Access Key) */
3249 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21();
3250
3251 /* fill in operation data for config field of Request Header*/
3252 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3253 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3254 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_RATE_POLICER_TABLE_ID;
3255 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for query command, always uses NETC_ETH_ENTRY_ID_MATCH method */
3256 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
3257 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
3258 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_RATEPOLICERTABLE_RSPBUFFER_LEN); /* set response data buffer length */
3259
3260 /* send command */
3261 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3262 #if defined(ERR_IPV_NETC_051243)
3263 #if (STD_ON == ERR_IPV_NETC_051243)
3264 /* Error code 0x8A is not a real error. check it on Errata. */
3265 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3266 {
3267 #endif
3268 #else
3269 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3270 {
3271 #endif
3272 status = NETC_ETH_IP_STATUS_SUCCESS;
3273 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3274
3275 /* found a matched entry */
3276 if (1U == *MatchedEntries)
3277 {
3278 /* fill in "Netc_Eth_Ip_RatePolicerEntryDataType" structure with data in response data buffer */
3279 RatePolicerTableEntry->RatePolicerEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[0U];
3280 /* fill in STSE data */
3281 TempTableDataField = ((uint64)Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U]) << NETC_ETH_IP_32BIT_SHIFT;
3282 RatePolicerTableEntry->RatePolicerStseData.Stse_ByteCount = TempTableDataField | (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U]);
3283 RatePolicerTableEntry->RatePolicerStseData.Stse_DropFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[3U];
3284 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr0GrnFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U];
3285 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr1GrnFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U];
3286 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr2YlwFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U];
3287 RatePolicerTableEntry->RatePolicerStseData.Stse_RemarkYlwFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U];
3288 RatePolicerTableEntry->RatePolicerStseData.Stse_Dr3RedFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[13U];
3289 RatePolicerTableEntry->RatePolicerStseData.Stse_RemarkRedFrames = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[15U];
3290 RatePolicerTableEntry->RatePolicerStseData.Stse_Lts = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[17U];
3291 RatePolicerTableEntry->RatePolicerStseData.Stse_CommittedTokenBucketInteger = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[18U];
3292 RatePolicerTableEntry->RatePolicerStseData.Stse_CommittedTokenBucketFractional = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[19U]; /* 1 sign bit + 31 bits fractional */
3293 RatePolicerTableEntry->RatePolicerStseData.Stse_ExcessTokenBucketInteger = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[20U];
3294 RatePolicerTableEntry->RatePolicerStseData.Stse_ExcessTokenBucketFranctional = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[21U]; /* 1 sign bit + 31 bits fractional */
3295 /* fill in CFGE data */
3296 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cir = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[22U];
3297 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cbs = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[23U];
3298 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Eir = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[24U];
3299 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ebs = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[25U];
3300 CfgeConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[26U];
3301 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Mren = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_MREN_MASK) == 0U) ? FALSE : TRUE;
3302 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Doy = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_DOY_MASK) == 0U) ? FALSE : TRUE;
3303 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cm = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CM_MASK) == 0U) ? FALSE : TRUE;
3304 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Cf = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_CF_MASK) == 0U) ? FALSE : TRUE;
3305 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_Ndor = ((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_NDOR_MASK) == 0U) ? FALSE : TRUE;
3306 SduType = (uint8)((CfgeConfigBits & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_SDU_TYPE_MASK) >> NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_SDU_TYPE_SHIFT);
3307 switch (SduType)
3308 {
3309 case 0U:
3310 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_PPDU;
3311 break;
3312 case 1U:
3313 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_MPDU;
3314 break;
3315 case 2U:
3316 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_MSDU;
3317 break;
3318 default:
3319 RatePolicerTableEntry->RatePolicerCfgeData.Cfge_SduType = NETC_ETH_IP_RSDTYPE;
3320 break;
3321 }
3322 /* fill FEE data */
3323 RatePolicerTableEntry->RatePolicerFunctionEnable = (((CfgeConfigBits >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_RATEPOLICERTABLE_FEE_DATA_FEN_MASK) == 0U) ? FALSE : TRUE;
3324 /* fill PSE data */
3325 RatePolicerTableEntry->MarkRedFlag = (((CfgeConfigBits >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_RATEPOLICERTABLE_CFGE_DATA_MREN_MASK) == 0U) ? FALSE : TRUE;
3326 }
3327 }
3328
3329 return status;
3330 }
3331
3332 /*FUNCTION**********************************************************************
3333 *
3334 * Function Name : Netc_Eth_Ip_DeleteRatePolicerTableEntry
3335 * Description : Delete Rate policer table entry function.
3336 *
3337 *
3338 *END**************************************************************************/
3339 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteRatePolicerTableEntry( const uint8 CtrlIndex,
3340 uint32 *MatchedEntries,
3341 uint32 RatePolicerEntryId
3342 )
3343 {
3344 Netc_Eth_Ip_StatusType status;
3345 uint32 ActionsData = 0U;
3346
3347 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3348 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3349 DevAssert(MatchedEntries != NULL_PTR);
3350 #endif
3351
3352 /* clear the variable MatchedEntries first */
3353 *MatchedEntries = 0U;
3354 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22();
3355 /* ------initialize the table request data buffer------ */
3356 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* Delete command will ignore ActionsData data field */
3357 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = RatePolicerEntryId; /* fill in Entry_ID field (Access Key) */
3358 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22();
3359
3360 /* fill in operation data for config field of Request Header*/
3361 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3362 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3363 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_RATE_POLICER_TABLE_ID;
3364 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for delete command, always uses NETC_ETH_ENTRY_ID_MATCH method */
3365 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_DELETE_CMD;
3366 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
3367 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN); /* set response data buffer with normal length */
3368
3369 /* send the "Delete" command */
3370 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3371 #if defined(ERR_IPV_NETC_051243)
3372 #if (STD_ON == ERR_IPV_NETC_051243)
3373 /* Error code 0x8A is not a real error. check it on Errata. */
3374 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3375 {
3376 #endif
3377 #else
3378 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3379 {
3380 #endif
3381 status = NETC_ETH_IP_STATUS_SUCCESS;
3382 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3383 }
3384
3385 return status;
3386 }
3387
3388 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateIngrStreamIdentificationTableEntry( const uint8 CtrlIndex,
3389 Netc_Eth_Ip_CommandsType Cmd,
3390 uint32 *MatchedEntries,
3391 const Netc_Eth_Ip_IngrStremIdentificationTableDataType * ISITableEntry
3392 )
3393 {
3394 Netc_Eth_Ip_StatusType status;
3395 uint32 ActionsData;
3396 uint8 FrmKeyIdx;
3397
3398 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3399 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3400 DevAssert(ISITableEntry != NULL_PTR);
3401 DevAssert(MatchedEntries != NULL_PTR);
3402 #endif
3403
3404 /* clear the variable MatchedEntries first */
3405 *MatchedEntries = 0U;
3406
3407 /* only support Add and Update commands */
3408 if ((NETC_ETH_ADD_CMD != Cmd) && (NETC_ETH_UPDATE_CMD != Cmd))
3409 {
3410 status = NETC_ETH_IP_STATUS_UNSUPPORTED; /* not supported command */
3411 }
3412 else
3413 {
3414 /* set table version and update actions*/
3415 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(1U) \
3416 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3417
3418 /* ------initialize the table request data buffer------ */
3419 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3420 /* fill in KEYE_DATA */
3421 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = NETC_ETH_IP_ISITABLE_KEYE_KEYTYPE(ISITableEntry->Keye_Keytype) \
3422 | NETC_ETH_IP_ISITABLE_KEYE_SRCPORTID(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
3423 | NETC_ETH_IP_ISITABLE_KEYE_SPM(NETC_ETH_IP_BD_ZERO_ENTRY_ID);
3424
3425 for (FrmKeyIdx = 0U; FrmKeyIdx < 4U; FrmKeyIdx++)
3426 {
3427 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0 + FrmKeyIdx] = ISITableEntry->Keye_FrmKey[FrmKeyIdx]; /* [Ricky]TODO: need to check the data format, big endian */
3428 }
3429 /* fill in CFGE_DATA */
3430 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = ISITableEntry->IngrStreamEntryId; /* IS_EID */
3431
3432 /* fill in operation data for config field of Request Header*/
3433 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3434 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3435 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_IDEN_TABLE_ID;
3436 /* for Add and Update command, the Access Method should only be NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH */
3437 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH;
3438 Netc_Eth_Ip_OperationData.Cmd = Cmd;
3439 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_ISITABLE_ADD_REQBUFFER_LEN);
3440 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_4BYTE_LEN);
3441
3442 /* send command */
3443 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3444 #if defined(ERR_IPV_NETC_051243)
3445 #if (STD_ON == ERR_IPV_NETC_051243)
3446 /* Error code 0x8A is not a real error. check it on Errata. */
3447 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3448 {
3449 #endif
3450 #else
3451 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3452 {
3453 #endif
3454 status = NETC_ETH_IP_STATUS_SUCCESS;
3455 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3456 }
3457 }
3458
3459 return status;
3460 }
3461
3462 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryIngrStreamIdentificationTableEntry( const uint8 CtrlIndex,
3463 uint32 *MatchedEntries,
3464 Netc_Eth_Ip_IngrStremIdentificationTableDataType * ISITableEntry
3465 )
3466 {
3467 Netc_Eth_Ip_StatusType status;
3468 uint32 ActionsData;
3469 uint32 ConfigBits;
3470 uint8 FrmKeyIdx;
3471
3472 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3473 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3474 DevAssert(ISITableEntry != NULL_PTR);
3475 DevAssert(MatchedEntries != NULL_PTR);
3476 #endif
3477
3478
3479 /* clear the variable MatchedEntries first */
3480 *MatchedEntries = 0U;
3481
3482 /* always do the full query. 0x0 = Full query. */
3483 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
3484 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3485
3486 /* ------initialize the table request data buffer------ */
3487 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3488 /* fill in KEYE_DATA */
3489 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = NETC_ETH_IP_ISITABLE_KEYE_KEYTYPE(ISITableEntry->Keye_Keytype) \
3490 | NETC_ETH_IP_ISITABLE_KEYE_SRCPORTID(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
3491 | NETC_ETH_IP_ISITABLE_KEYE_SPM(NETC_ETH_IP_BD_ZERO_ENTRY_ID);
3492
3493 for (FrmKeyIdx = 0U; FrmKeyIdx < 4U; FrmKeyIdx++)
3494 {
3495 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0 + FrmKeyIdx] = ISITableEntry->Keye_FrmKey[FrmKeyIdx]; /* [Ricky]TODO: need to check the data format, big endian */
3496 }
3497
3498 /* fill in operation data for config field of Request Header*/
3499 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3500 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3501 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_IDEN_TABLE_ID;
3502 /* for query function, always uses NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH method */
3503 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH;
3504 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
3505 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_ISITABLE_QUERY_REQBUFFER_LEN); /* set request data buffer length */
3506 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_ISITABLE_RSQBUFFER_LEN); /* set response data buffer length */
3507
3508 /* send command */
3509 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3510 #if defined(ERR_IPV_NETC_051243)
3511 #if (STD_ON == ERR_IPV_NETC_051243)
3512 /* Error code 0x8A is not a real error. check it on Errata. */
3513 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3514 {
3515 #endif
3516 #else
3517 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3518 {
3519 #endif
3520 status = NETC_ETH_IP_STATUS_SUCCESS;
3521 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3522
3523 /* found a matched entry */
3524 if (1U == *MatchedEntries)
3525 {
3526 /* fill in "Netc_Eth_Ip_IngrStremIdentificationTableDataType" structure with data in response data buffer */
3527 ISITableEntry->IngrStreamIdenEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U];
3528
3529 /* fill in KEYE data */
3530 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U];
3531 ISITableEntry->Keye_Keytype = (ConfigBits & NETC_ETH_IP_ISITABLE_KEYE_KEYTYPE_MASK);
3532
3533 for (FrmKeyIdx = 0U; FrmKeyIdx < 4U; FrmKeyIdx++)
3534 {
3535 ISITableEntry->Keye_FrmKey[FrmKeyIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[3U + FrmKeyIdx];
3536 }
3537
3538 /* fill in CFGE data */
3539 ISITableEntry->IngrStreamEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U];
3540 }
3541 }
3542
3543 return status;
3544 }
3545
3546 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteIngrStreamIdentificationTableEntry( const uint8 CtrlIndex,
3547 uint32 *MatchedEntries,
3548 const Netc_Eth_Ip_IngrStremIdentificationTableDataType * ISITableEntry
3549 )
3550 {
3551 Netc_Eth_Ip_StatusType status;
3552 uint32 ActionsData = 0U;
3553 uint8 FrmKeyIdx;
3554
3555 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3556 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3557 DevAssert(ISITableEntry != NULL_PTR);
3558 DevAssert(MatchedEntries != NULL_PTR);
3559 #endif
3560
3561 /* clear the variable MatchedEntries first */
3562 *MatchedEntries = 0U;
3563
3564 /* ------initialize the table request data buffer------ */
3565 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3566 /* fill in KEYE_DATA */
3567 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = NETC_ETH_IP_ISITABLE_KEYE_KEYTYPE(ISITableEntry->Keye_Keytype) \
3568 | NETC_ETH_IP_ISITABLE_KEYE_SRCPORTID(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
3569 | NETC_ETH_IP_ISITABLE_KEYE_SPM(NETC_ETH_IP_BD_ZERO_ENTRY_ID);
3570
3571 for (FrmKeyIdx = 0U; FrmKeyIdx < 4U; FrmKeyIdx++)
3572 {
3573 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0 + FrmKeyIdx] = ISITableEntry->Keye_FrmKey[FrmKeyIdx]; /* [Ricky]TODO: need to check the data format, big endian */
3574 }
3575
3576 /* fill in operation data for config field of Request Header*/
3577 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3578 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3579 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_IDEN_TABLE_ID;
3580 /* for query function, always uses NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH method */
3581 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH;
3582 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_DELETE_CMD;
3583 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_ISITABLE_QUERY_REQBUFFER_LEN); /* set request data buffer length */
3584 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_4BYTE_LEN); /* set response data buffer length */
3585
3586 /* send command */
3587 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3588 #if defined(ERR_IPV_NETC_051243)
3589 #if (STD_ON == ERR_IPV_NETC_051243)
3590 /* Error code 0x8A is not a real error. check it on Errata. */
3591 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3592 #else
3593 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3594 #endif
3595 #else
3596 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3597 #endif
3598 {
3599 status = NETC_ETH_IP_STATUS_SUCCESS;
3600 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3601 }
3602
3603 return status;
3604 }
3605
3606 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_SearchAndFillIngrStreamIdentificationTable( const uint8 CtrlIndex,
3607 uint32 * ResumeEntryId,
3608 uint16 * NumOfExistingEntry,
3609 Netc_Eth_Ip_IngrStremIdentificationTableDataType * ISITableEntry
3610 )
3611 {
3612 Netc_Eth_Ip_StatusType status;
3613 uint32 ActionsData;
3614 uint32 ConfigBits;
3615 uint32 MatchedEntries = 0x0UL;
3616 uint8 FrmKeyIdx;
3617 uint8 TableMemIdx;
3618
3619 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3620 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3621 DevAssert(ISITableEntry != NULL_PTR);
3622 DevAssert(ResumeEntryId != NULL_PTR);
3623 #endif
3624
3625 /* always do the full query. 0x0 = Full query. */
3626 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
3627 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3628
3629 /* ------initialize the table request data buffer------ */
3630 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3631 /* fill in KEYE_DATA field */
3632 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = *ResumeEntryId;
3633
3634 /* clear the memory for searching, otherwise will get 0x89 error code */
3635 for (TableMemIdx = 0U; TableMemIdx < 6U; TableMemIdx++)
3636 {
3637 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0 + TableMemIdx] = 0U;
3638 }
3639
3640 /* fill in operation data for config field of Request Header*/
3641 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3642 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3643 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_IDEN_TABLE_ID;
3644 /* query function with NETC_ETH_SEARCH_METHOD method */
3645 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_SEARCH_METHOD;
3646 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
3647 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_ISITABLE_QUERY_REQBUFFER_LEN); /* set request data buffer length */
3648 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_ISITABLE_RSQBUFFER_LEN); /* set response data buffer length */
3649
3650 /* send command */
3651 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3652 #if defined(ERR_IPV_NETC_051243)
3653 #if (STD_ON == ERR_IPV_NETC_051243)
3654 /* Error code 0x8A is not a real error. check it on Errata. */
3655 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3656 {
3657 #endif
3658 #else
3659 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3660 {
3661 #endif
3662 status = NETC_ETH_IP_STATUS_SUCCESS;
3663 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, &MatchedEntries);
3664
3665 /* get the resume_entry_id and be ready for the next query operation */
3666 *ResumeEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[0U];
3667
3668 /* ERR051048: NETC: Management command with search action responds with incorrect NUM_MATCHED */
3669 /* found a matched entry */
3670 if ((1U == MatchedEntries) && (*ResumeEntryId != NETC_ETH_IP_BD_NULL_ENTRY_ID))
3671 {
3672 /* fill in "Netc_Eth_Ip_IngrStremIdentificationTableDataType" structure with data in response data buffer */
3673 ISITableEntry[*NumOfExistingEntry].IngrStreamIdenEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U];
3674
3675 /* fill in KEYE data */
3676 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U];
3677 ISITableEntry[*NumOfExistingEntry].Keye_Keytype = (ConfigBits & NETC_ETH_IP_ISITABLE_KEYE_KEYTYPE_MASK);
3678
3679 for (FrmKeyIdx = 0U; FrmKeyIdx < 2U; FrmKeyIdx++)
3680 {
3681 ISITableEntry[*NumOfExistingEntry].Keye_FrmKey[FrmKeyIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[3U + FrmKeyIdx];
3682 }
3683
3684 /* fill in CFGE data */
3685 ISITableEntry[*NumOfExistingEntry].IngrStreamEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U];
3686
3687 /* increase the NumOfExistingEntry */
3688 (*NumOfExistingEntry) += 1U;
3689 }
3690 }
3691
3692 return status;
3693 }
3694
3695 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetIngrStreamIdentificationTable( const uint8 CtrlIndex,
3696 uint16 * NumberOfElements,
3697 Netc_Eth_Ip_IngrStremIdentificationTableDataType * ISITableList
3698 )
3699 {
3700 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
3701 uint16 NumOfExistingEntry = 0U;
3702 uint32 ResumeId = NETC_ETH_IP_BD_NULL_ENTRY_ID;
3703
3704 /* [notes]: we will have to read entries one by one because of the errata ERR051048.
3705 - ERR051048: NETC: Management command with search action responds with incorrect NUM_MATCHED
3706 - Description: The NUM_MATCHED field in the command NTMP response header may be incorrect when
3707 the search access method is used for the following tables: FDB table 15, L2 IPv4 Multicast
3708 Filter table 16, VLAN Filter table 18, Ingress Stream Identification table 30, or Ingress Stream
3709 Filter table 32.
3710 - Workaround: For the query command, limit the message response buffer size (RESPONSE_LENGTH field in the request header)
3711 so that NETC returns no more than one entry at a time. Under this condition, the NUM_MATCHED field value is correct
3712 */
3713
3714 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3715 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3716 DevAssert(NumberOfElements != NULL_PTR);
3717 DevAssert(*NumberOfElements != 0U);
3718 DevAssert(ISITableList != NULL_PTR);
3719 #endif
3720
3721 do
3722 {
3723 /* check if the ISITableList is full or we get all existing entries */
3724 if ((NumOfExistingEntry >= *NumberOfElements) || (status != NETC_ETH_IP_STATUS_SUCCESS))
3725 {
3726 break;
3727 }
3728
3729 status = Netc_Eth_Ip_SearchAndFillIngrStreamIdentificationTable(CtrlIndex, &ResumeId, &NumOfExistingEntry, ISITableList);
3730
3731 } while (ResumeId != NETC_ETH_IP_BD_NULL_ENTRY_ID); /* ResumeId == NETC_ETH_IP_BD_NULL_ENTRY_ID means the query operation is completed */
3732
3733 /* return the Number of elements which are currently available in the EthSwitch module or number of elements copied to ISITableList*/
3734 *NumberOfElements = NumOfExistingEntry;
3735
3736 return status;
3737 }
3738
3739 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateStreamGateInstanceTableEntry( const uint8 CtrlIndex,
3740 Netc_Eth_Ip_CommandsType Cmd,
3741 uint32 *MatchedEntries,
3742 const Netc_Eth_Ip_StreamGateInstanceEntryDataType * StreamGateInstanceTableEntry
3743 )
3744 {
3745 Netc_Eth_Ip_StatusType status;
3746 uint32 ActionsData;
3747
3748 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3749 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3750 DevAssert(StreamGateInstanceTableEntry != NULL_PTR);
3751 DevAssert(MatchedEntries != NULL_PTR);
3752 #endif
3753
3754 /* clear the variable MatchedEntries first */
3755 *MatchedEntries = 0U;
3756
3757 /* only support Add and Update commands */
3758 if ((NETC_ETH_ADD_CMD != Cmd) && (NETC_ETH_UPDATE_CMD != Cmd))
3759 {
3760 status = NETC_ETH_IP_STATUS_UNSUPPORTED; /* not supported command */
3761 }
3762 else
3763 {
3764 /* set table version and update actions*/
3765 ActionsData = NETC_ETH_IP_SGITABLE_REQFMT_ACFGEU(1U) \
3766 | NETC_ETH_IP_SGITABLE_REQFMT_CFGEU(1U) \
3767 | NETC_ETH_IP_SGITABLE_REQFMT_SGISEU(1U) \
3768 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3769
3770 /* ------initialize the table request data buffer------ */
3771 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3772 /* fill in KEYE_DATA */
3773 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = StreamGateInstanceTableEntry->SGIEntryId; /* fill in Entry_ID */
3774 /* fill in ACFGE_DATA */
3775 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = StreamGateInstanceTableEntry->AdminSGCLEntryId;
3776 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = (uint32)(StreamGateInstanceTableEntry->AdminBaseTime & 0xFFFFFFFFUL);
3777 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2] = (uint32)(StreamGateInstanceTableEntry->AdminBaseTime >> NETC_ETH_IP_32BIT_SHIFT);
3778 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3] = StreamGateInstanceTableEntry->AdminCycleTimeExt;
3779 /* fill in CFGE_DATA and ICFGE_DATA */
3780 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = (NETC_ETH_IP_SGITABLE_CFGE_OEXEN(StreamGateInstanceTableEntry->Cfge_Oexen ? 1U : 0U) \
3781 | NETC_ETH_IP_SGITABLE_CFGE_IRXEN(StreamGateInstanceTableEntry->Cfge_Irxen ? 1U : 0U) \
3782 | NETC_ETH_IP_SGITABLE_CFGE_SDUTYPE(StreamGateInstanceTableEntry->SduType) \
3783 | (NETC_ETH_IP_SGITABLE_ICFGE_IPV(StreamGateInstanceTableEntry->Icfge_Ipv) << NETC_ETH_IP_8BIT_SHIFT) \
3784 | (NETC_ETH_IP_SGITABLE_ICFGE_OIPV(StreamGateInstanceTableEntry->Icfge_Oipv ? 1U : 0U) << NETC_ETH_IP_8BIT_SHIFT) \
3785 | (NETC_ETH_IP_SGITABLE_ICFGE_GST(StreamGateInstanceTableEntry->Icfge_Gst) << NETC_ETH_IP_8BIT_SHIFT) \
3786 | (NETC_ETH_IP_SGITABLE_ICFGE_CTD(NETC_ETH_IP_BD_ZERO_ENTRY_ID) << NETC_ETH_IP_8BIT_SHIFT)) & 0xFFFFU;
3787
3788 /* fill in operation data for config field of Request Header*/
3789 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3790 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3791 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_STREAM_GATE_INSTANCE_TABLE_ID;
3792 /* for Add and Update command, the Access Method should only be NETC_ETH_ENTRY_ID_MATCH */
3793 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
3794 Netc_Eth_Ip_OperationData.Cmd = Cmd;
3795 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_SGITABLE_REQBUFFER_LEN);
3796 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN);
3797
3798 /* send command */
3799 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3800 #if defined(ERR_IPV_NETC_051243)
3801 #if (STD_ON == ERR_IPV_NETC_051243)
3802 /* Error code 0x8A is not a real error. check it on Errata. */
3803 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3804 {
3805 #endif
3806 #else
3807 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3808 {
3809 #endif
3810 status = NETC_ETH_IP_STATUS_SUCCESS;
3811 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3812 }
3813 }
3814
3815 return status;
3816 }
3817
3818 /*FUNCTION**********************************************************************
3819 *
3820 * Function Name : Netc_Eth_Ip_QueryStreamGateInstanceTableEntry
3821 * Description : Ethernet Switch query Ingress Stream Filter table entry function.
3822 *
3823 *END**************************************************************************/
3824 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryStreamGateInstanceTableEntry( const uint8 CtrlIndex,
3825 uint32 *MatchedEntries,
3826 uint32 SGIEntryId,
3827 Netc_Eth_Ip_StreamGateInstanceEntryRspDataType * SGITableEntryRspData
3828 )
3829 {
3830 Netc_Eth_Ip_StatusType status;
3831 uint32 ActionsData;
3832 uint32 ConfigBits;
3833 uint8 SduType;
3834
3835 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3836 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3837 DevAssert(MatchedEntries != NULL_PTR);
3838 DevAssert(SGITableEntryRspData != NULL_PTR);
3839 #endif
3840
3841 /* clear the variable MatchedEntries first */
3842 *MatchedEntries = 0U;
3843
3844 /* always do the full query. 0x0 = Full query. */
3845 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
3846 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
3847
3848 /* ------initialize the table request data buffer------ */
3849 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
3850 /* fill in ACCESS_KEY field */
3851 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = SGIEntryId;
3852
3853 /* fill in operation data for config field of Request Header*/
3854 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3855 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3856 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_STREAM_GATE_INSTANCE_TABLE_ID;
3857 /* for query function, always uses NETC_ETH_ENTRY_ID_MATCH method */
3858 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
3859 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
3860 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
3861 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_SGITABLE_RSPBUFFER_LEN); /* set response data buffer length */
3862
3863 /* send command */
3864 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3865 #if defined(ERR_IPV_NETC_051243)
3866 #if (STD_ON == ERR_IPV_NETC_051243)
3867 /* Error code 0x8A is not a real error. check it on Errata. */
3868 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3869 {
3870 #endif
3871 #else
3872 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3873 {
3874 #endif
3875 status = NETC_ETH_IP_STATUS_SUCCESS;
3876 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3877
3878 /* found a matched entry */
3879 if (1U == *MatchedEntries)
3880 {
3881 /* fill in "Netc_Eth_Ip_StreamGateInstanceEntryRspDataType" structure with data in response data buffer */
3882 SGITableEntryRspData->SGIEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[0U];
3883 /* fill in SGISE_DATA */
3884 SGITableEntryRspData->OperationalSGCLEntryID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U];
3885 SGITableEntryRspData->ConfigChangeTime = ((uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[3U]) << NETC_ETH_IP_32BIT_SHIFT);
3886 SGITableEntryRspData->ConfigChangeTime |= (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U]);
3887 SGITableEntryRspData->OperationalBaseTime = ((uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U]) << NETC_ETH_IP_32BIT_SHIFT);
3888 SGITableEntryRspData->OperationalBaseTime |= (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U]);
3889 SGITableEntryRspData->OperationalCycleTimeExt = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[6U];
3890 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U];
3891 SGITableEntryRspData->SGISEOex = (uint8)(ConfigBits & NETC_ETH_IP_SGITABLE_SGISE_OEX_MASK);
3892 SGITableEntryRspData->SGISEIrx = (uint8)((ConfigBits & NETC_ETH_IP_SGITABLE_SGISE_IRX_MASK) >> NETC_ETH_IP_SGITABLE_SGISE_IRX_SHIFT);
3893 SGITableEntryRspData->SGISEState = (uint8)((ConfigBits & NETC_ETH_IP_SGITABLE_SGISE_STATE_MASK) >> NETC_ETH_IP_SGITABLE_SGISE_STATE_SHIFT);
3894
3895 /* fill in CFGE data */
3896 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U] >> NETC_ETH_IP_8BIT_SHIFT;
3897 SGITableEntryRspData->Cfge_Oexen = ((ConfigBits & NETC_ETH_IP_SGITABLE_CFGE_OEXEN_MASK) == 0U) ? FALSE : TRUE;
3898 SGITableEntryRspData->Cfge_Irxen = ((ConfigBits & NETC_ETH_IP_SGITABLE_CFGE_IRXEN_MASK) == 0U) ? FALSE : TRUE;
3899 SduType = (uint8)((ConfigBits & NETC_ETH_IP_SGITABLE_CFGE_SDUTYPE_MASK) >> NETC_ETH_IP_SGITABLE_CFGE_SDUTYPE_SHIFT);
3900 switch (SduType)
3901 {
3902 case 0U:
3903 SGITableEntryRspData->SduType = NETC_ETH_IP_PPDU;
3904 break;
3905 case 1U:
3906 SGITableEntryRspData->SduType = NETC_ETH_IP_MPDU;
3907 break;
3908 case 2U:
3909 SGITableEntryRspData->SduType = NETC_ETH_IP_MSDU;
3910 break;
3911 default:
3912 SGITableEntryRspData->SduType = NETC_ETH_IP_RSDTYPE;
3913 break;
3914 }
3915
3916 /* fill in ICFGE data */
3917 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U] >> NETC_ETH_IP_16BIT_SHIFT;
3918 SGITableEntryRspData->Icfge_Ipv = (uint8)(ConfigBits & NETC_ETH_IP_SGITABLE_ICFGE_IPV_MASK);
3919 SGITableEntryRspData->Icfge_Oipv = ((ConfigBits & NETC_ETH_IP_SGITABLE_ICFGE_OIPV_MASK) == 0U) ? FALSE : TRUE;
3920 SGITableEntryRspData->Icfge_Gst = (ConfigBits & NETC_ETH_IP_SGITABLE_ICFGE_GST_MASK) >> NETC_ETH_IP_SGITABLE_ICFGE_GST_SHIFT;
3921
3922 /* fill in ACFGE data */
3923 SGITableEntryRspData->AdminSGCLEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U];
3924 SGITableEntryRspData->AdminBaseTime = (((uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[10U])) << NETC_ETH_IP_32BIT_SHIFT);
3925 SGITableEntryRspData->AdminBaseTime |= (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U]);
3926 SGITableEntryRspData->AdminCycleTimeExt = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U];
3927 }
3928 }
3929
3930 return status;
3931 }
3932
3933 /*FUNCTION**********************************************************************
3934 *
3935 * Function Name : Netc_Eth_Ip_DeleteStreamGateInstanceTableEntry
3936 * Description : Ethernet Switch delete Stream Gate Instance table entry function.
3937 *
3938 *END**************************************************************************/
3939 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteStreamGateInstanceTableEntry( const uint8 CtrlIndex,
3940 uint32 *MatchedEntries,
3941 uint32 SGIEntryId
3942 )
3943 {
3944 Netc_Eth_Ip_StatusType status;
3945 uint32 ActionsData = 0U;
3946
3947 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
3948 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
3949 DevAssert(MatchedEntries != NULL_PTR);
3950 #endif
3951
3952 /* clear the variable MatchedEntries first */
3953 *MatchedEntries = 0U;
3954 /* ------initialize the table request data buffer------ */
3955 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* Delete command will ignore ActionsData data field */
3956 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = SGIEntryId; /* fill in Entry_ID field (Access Key) */
3957
3958 /* fill in operation data for config field of Request Header*/
3959 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
3960 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
3961 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_STREAM_GATE_INSTANCE_TABLE_ID;
3962 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for delete command, always uses NETC_ETH_ENTRY_ID_MATCH method */
3963 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_DELETE_CMD;
3964 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
3965 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN); /* set response data buffer with normal length */
3966
3967 /* send the "Delete" command */
3968 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
3969 #if defined(ERR_IPV_NETC_051243)
3970 #if (STD_ON == ERR_IPV_NETC_051243)
3971 /* Error code 0x8A is not a real error. check it on Errata. */
3972 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
3973 #else
3974 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3975 #endif
3976 #else
3977 if (status == NETC_ETH_IP_STATUS_SUCCESS)
3978 #endif
3979 {
3980 status = NETC_ETH_IP_STATUS_SUCCESS;
3981 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
3982 }
3983
3984 return status;
3985 }
3986
3987 /*FUNCTION**********************************************************************
3988 *
3989 * Function Name : Netc_Eth_Ip_AddStreamGateControlListTableEntry
3990 * Description : Ethernet Switch Add Stream Gate Control List table entry function.
3991 *
3992 *END**************************************************************************/
3993 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddStreamGateControlListTableEntry( const uint8 CtrlIndex,
3994 Netc_Eth_Ip_CommandsType Cmd,
3995 uint32 *MatchedEntries,
3996 const Netc_Eth_Ip_SGCLTableDataType * SGCLTableEntry
3997 )
3998 {
3999 Netc_Eth_Ip_StatusType status;
4000 uint32 ActionsData;
4001 uint8 ListIdx;
4002
4003 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4004 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4005 DevAssert(SGCLTableEntry != NULL_PTR);
4006 DevAssert(MatchedEntries != NULL_PTR);
4007 if (SGCLTableEntry->Cfge_ListLength > 0U)
4008 {
4009 DevAssert(SGCLTableEntry->ListEntries != NULL_PTR);
4010 }
4011 #endif
4012
4013 /* clear the variable MatchedEntries first */
4014 *MatchedEntries = 0U;
4015
4016 /* only support Add command */
4017 if (NETC_ETH_ADD_CMD != Cmd)
4018 {
4019 status = NETC_ETH_IP_STATUS_UNSUPPORTED; /* not supported command */
4020 }
4021 else
4022 {
4023 /* set table version*/
4024 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
4025
4026 /* ------initialize the table request data buffer------ */
4027 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
4028 /* fill in ACCESS_KEY */
4029 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = SGCLTableEntry->SGCLEntryId; /* fill in Entry_ID */
4030 /* fill in CFGE_DATA */
4031 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = SGCLTableEntry->Cfge_CycleTime;
4032 /* Software must set LIST_LENGTH to N-1, where N is the size of the list being configured LIST_LENGTH=(N-1). will do it reversely when querying */
4033 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = NETC_ETH_IP_SGCLTABLE_CFGE_LISTLEN((uint8)(SGCLTableEntry->Cfge_ListLength - 1U)) \
4034 | NETC_ETH_IP_SGCLTABLE_CFGE_EXTOIPV((SGCLTableEntry->Cfge_ExtOIPV) ? 1U : 0U) \
4035 | NETC_ETH_IP_SGCLTABLE_CFGE_EXTIPV(SGCLTableEntry->Cfge_ExtIpv) \
4036 | NETC_ETH_IP_SGCLTABLE_CFGE_EXTCTD(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4037 | NETC_ETH_IP_SGCLTABLE_CFGE_EXTGTST(SGCLTableEntry->Cfge_ExtGtst);
4038
4039 /* fill in list entries data */
4040 if (SGCLTableEntry->Cfge_ListLength > 0U)
4041 {
4042 for (ListIdx = 0U; ListIdx < SGCLTableEntry->Cfge_ListLength; ListIdx++)
4043 {
4044 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2 + (2U * ListIdx)] = SGCLTableEntry->ListEntries[ListIdx].SGCL_TimeInterval;
4045 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[(uint8)NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3 + (2U * ListIdx)] = NETC_ETH_IP_SGCLTABLE_CFGE_IOM(SGCLTableEntry->ListEntries[ListIdx].SGCL_IntervalOctetsMax) \
4046 | NETC_ETH_IP_SGCLTABLE_CFGE_IPV(SGCLTableEntry->ListEntries[ListIdx].SGCL_Ipv) \
4047 | NETC_ETH_IP_SGCLTABLE_CFGE_OIPV((SGCLTableEntry->ListEntries[ListIdx].SGCL_Oipv) ? 1U : 0U) \
4048 | NETC_ETH_IP_SGCLTABLE_CFGE_CTD(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4049 | NETC_ETH_IP_SGCLTABLE_CFGE_IOMEN((SGCLTableEntry->ListEntries[ListIdx].SGCL_IntervalOctetMaxEnable) ? 1U : 0U) \
4050 | NETC_ETH_IP_SGCLTABLE_CFGE_GTST(SGCLTableEntry->ListEntries[ListIdx].SGCL_GateState);
4051 }
4052 }
4053
4054 /* fill in operation data for config field of Request Header*/
4055 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
4056 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
4057 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_STREAM_GATE_CTRL_LIST_TABLE_ID;
4058 /* for Add and Update command, the Access Method should only be NETC_ETH_ENTRY_ID_MATCH */
4059 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
4060 Netc_Eth_Ip_OperationData.Cmd = Cmd;
4061 /* the request and response data buffer length are variable based on the length of control list*/
4062 Netc_Eth_Ip_OperationData.ReqBuffLength = (uint16)((uint8)(16U + (8U * SGCLTableEntry->Cfge_ListLength)));
4063 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN);
4064
4065 /* send command */
4066 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
4067 #if defined(ERR_IPV_NETC_051243)
4068 #if (STD_ON == ERR_IPV_NETC_051243)
4069 /* Error code 0x8A is not a real error. check it on Errata. */
4070 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
4071 {
4072 #endif
4073 #else
4074 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4075 {
4076 #endif
4077 status = NETC_ETH_IP_STATUS_SUCCESS;
4078 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
4079 }
4080 }
4081
4082 return status;
4083 }
4084
4085 /*FUNCTION**********************************************************************
4086 *
4087 * Function Name : Netc_Eth_Ip_QueryStreamGateControlListTableEntry
4088 * Description : Ethernet Switch query Ingress Stream Control List table entry function.
4089 *
4090 *END**************************************************************************/
4091 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryStreamGateControlListTableEntry( const uint8 CtrlIndex,
4092 uint32 *MatchedEntries,
4093 uint32 SGCLEntryId,
4094 uint8 ListLen,
4095 Netc_Eth_Ip_SGCLTableDataType * SGCLTableEntryRspData
4096 )
4097 {
4098 Netc_Eth_Ip_StatusType status;
4099 uint32 ActionsData;
4100 uint32 ConfigBits;
4101 uint8 ListIdx;
4102
4103 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4104 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4105 DevAssert(MatchedEntries != NULL_PTR);
4106 DevAssert(SGCLTableEntryRspData != NULL_PTR);
4107 if (ListLen > 0U)
4108 {
4109 DevAssert(SGCLTableEntryRspData->ListEntries != NULL_PTR);
4110 }
4111 #endif
4112
4113 /* clear the variable MatchedEntries first */
4114 *MatchedEntries = 0U;
4115
4116 /* always do the full query. 0x0 = Full query. */
4117 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
4118 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
4119
4120 /* ------initialize the table request data buffer------ */
4121 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
4122 /* fill in ACCESS_KEY field */
4123 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = SGCLEntryId;
4124
4125 /* fill in operation data for config field of Request Header*/
4126 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
4127 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
4128 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_STREAM_GATE_CTRL_LIST_TABLE_ID;
4129 /* for query function, always uses NETC_ETH_ENTRY_ID_MATCH method */
4130 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
4131 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
4132 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
4133 Netc_Eth_Ip_OperationData.RspBuffLength = (uint16)((uint8)(16U + (8U * ListLen))); /* set response data buffer length */
4134
4135 /* send command */
4136 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
4137 #if defined(ERR_IPV_NETC_051243)
4138 #if (STD_ON == ERR_IPV_NETC_051243)
4139 /* Error code 0x8A is not a real error. check it on Errata. */
4140 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
4141 {
4142 #endif
4143 #else
4144 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4145 {
4146 #endif
4147 status = NETC_ETH_IP_STATUS_SUCCESS;
4148 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
4149
4150 /* found a matched entry */
4151 if (1U == *MatchedEntries)
4152 {
4153 /* fill in "Netc_Eth_Ip_SGCLTableDataType" structure with data in response data buffer */
4154 SGCLTableEntryRspData->SGCLEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[0U];
4155
4156 /* fill in SGCLSE_DATA */
4157 SGCLTableEntryRspData->Sgclse_RefCount = (Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U] & NETC_ETH_IP_SGCLTABLE_SGCLSE_REFCOUNT_MASK);
4158
4159 /* fill in CFGE data */
4160 SGCLTableEntryRspData->Cfge_CycleTime = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U];
4161 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[3U];
4162 SGCLTableEntryRspData->Cfge_ListLength = (uint8)(ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_LISTLEN_MASK) + 1U;
4163 SGCLTableEntryRspData->Cfge_ExtIpv = (uint8)((ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_EXTIPV_MASK) >> NETC_ETH_IP_SGCLTABLE_CFGE_EXTIPV_SHIFT);
4164 SGCLTableEntryRspData->Cfge_ExtOIPV = ((ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_EXTOIPV_MASK) == 0x0UL) ? FALSE : TRUE;
4165 SGCLTableEntryRspData->Cfge_ExtGtst = (ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_EXTGTST_MASK) >> NETC_ETH_IP_SGCLTABLE_CFGE_EXTGTST_SHIFT;
4166
4167 if (SGCLTableEntryRspData->Cfge_ListLength > 0U)
4168 {
4169 for (ListIdx = 0U; ListIdx < SGCLTableEntryRspData->Cfge_ListLength; ListIdx++)
4170 {
4171 SGCLTableEntryRspData->ListEntries[ListIdx].SGCL_TimeInterval = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U + (2U * ListIdx)];
4172 ConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U + (2U * ListIdx)];
4173 SGCLTableEntryRspData->ListEntries[ListIdx].SGCL_IntervalOctetsMax = ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_IOM_MASK;
4174 SGCLTableEntryRspData->ListEntries[ListIdx].SGCL_Ipv = (uint8)((ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_IPV_MASK) >> NETC_ETH_IP_SGCLTABLE_CFGE_IPV_SHIFT);
4175 SGCLTableEntryRspData->ListEntries[ListIdx].SGCL_Oipv = ((ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_OIPV_MASK) == 0x0UL) ? FALSE : TRUE;
4176 SGCLTableEntryRspData->ListEntries[ListIdx].SGCL_IntervalOctetMaxEnable = ((ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_IOMEN_MASK) == 0x0UL) ? FALSE : TRUE;
4177 SGCLTableEntryRspData->ListEntries[ListIdx].SGCL_GateState = (ConfigBits & NETC_ETH_IP_SGCLTABLE_CFGE_GTST_MASK) >> NETC_ETH_IP_SGCLTABLE_CFGE_GTST_SHIFT;
4178 }
4179 }
4180 }
4181 }
4182
4183 return status;
4184 }
4185
4186 /*FUNCTION**********************************************************************
4187 *
4188 * Function Name : Netc_Eth_Ip_DeleteStreamGateControlListTableEntry
4189 * Description : Ethernet Switch delete Stream Gate Instance table entry function.
4190 *
4191 *END**************************************************************************/
4192 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteStreamGateControlListTableEntry( const uint8 CtrlIndex,
4193 uint32 *MatchedEntries,
4194 uint32 SGCLEntryId
4195 )
4196 {
4197 Netc_Eth_Ip_StatusType status;
4198 uint32 ActionsData = 0U;
4199
4200 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4201 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4202 DevAssert(MatchedEntries != NULL_PTR);
4203 #endif
4204
4205 /* clear the variable MatchedEntries first */
4206 *MatchedEntries = 0U;
4207 /* ------initialize the table request data buffer------ */
4208 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* Delete command will ignore ActionsData data field */
4209 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = SGCLEntryId; /* fill in Entry_ID field (Access Key) */
4210
4211 /* fill in operation data for config field of Request Header*/
4212 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
4213 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
4214 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_STREAM_GATE_CTRL_LIST_TABLE_ID;
4215 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for delete command, always uses NETC_ETH_ENTRY_ID_MATCH method */
4216 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_DELETE_CMD;
4217 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
4218 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN); /* set response data buffer with normal length */
4219
4220 /* send the "Delete" command */
4221 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
4222 #if defined(ERR_IPV_NETC_051243)
4223 #if (STD_ON == ERR_IPV_NETC_051243)
4224 /* Error code 0x8A is not a real error. check it on Errata. */
4225 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
4226 #else
4227 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4228 #endif
4229 #else
4230 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4231 #endif
4232 {
4233 status = NETC_ETH_IP_STATUS_SUCCESS;
4234 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
4235 }
4236
4237 return status;
4238 }
4239
4240 /*FUNCTION**********************************************************************
4241 *
4242 * Function Name : Netc_Eth_Ip_AddOrUpdateIngressStreamTableEntry
4243 * Description : Ethernet Switch Add or Update ingress stream table entry function.
4244 *
4245 *END**************************************************************************/
4246 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddOrUpdateIngressStreamTableEntry( const uint8 CtrlIndex,
4247 Netc_Eth_Ip_CommandsType Cmd,
4248 uint32 *MatchedEntries,
4249 const Netc_Eth_Ip_IngressStreamEntryDataType * IngressStreamTableEntry
4250 )
4251 {
4252 Netc_Eth_Ip_StatusType status;
4253 uint32 ActionsData;
4254
4255 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4256 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4257 DevAssert(IngressStreamTableEntry != NULL_PTR);
4258 DevAssert(MatchedEntries != NULL_PTR);
4259 #endif
4260
4261 /* clear the variable MatchedEntries first */
4262 *MatchedEntries = 0U;
4263
4264 /* only support Add and Update commands */
4265 if ((NETC_ETH_ADD_CMD != Cmd) && (NETC_ETH_UPDATE_CMD != Cmd))
4266 {
4267 status = NETC_ETH_IP_STATUS_UNSUPPORTED; /* not supported command */
4268 }
4269 else
4270 {
4271 /* set table version and CFGEU flag */
4272 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(1U) \
4273 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
4274
4275 /* ------initialize the table request data buffer------ */
4276 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
4277 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = IngressStreamTableEntry->IngressStreamEntryId; /* fill in Entry_ID field (Access Key) */
4278 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA0] = NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SFE((IngressStreamTableEntry->IngressStreamCfgeData.StreamFilteringEnable) ? 1U : 0U) \
4279 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_IPV(IngressStreamTableEntry->IngressStreamCfgeData.InternalPriorityValue) \
4280 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OIPV((IngressStreamTableEntry->IngressStreamCfgeData.OverrideIPV) ? 1U : 0U) \
4281 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_DR(IngressStreamTableEntry->IngressStreamCfgeData.DropResilience) \
4282 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ODR((IngressStreamTableEntry->IngressStreamCfgeData.OverrideDR) ? 1U : 0U) \
4283 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_IMIRE(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4284 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_TIMECAPE(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4285 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SPPD(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4286 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ISQA(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4287 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ORP((IngressStreamTableEntry->IngressStreamCfgeData.OverrideRatePolicerInstanceEID) ? 1U : 0U) \
4288 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OSGI((IngressStreamTableEntry->IngressStreamCfgeData.OverrideStreamGateInstanceEID) ? 1U : 0U) \
4289 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_HR(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4290 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_FA(IngressStreamTableEntry->IngressStreamCfgeData.ForwardingActions) \
4291 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SDUTYPE(IngressStreamTableEntry->IngressStreamCfgeData.SduType);
4292 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA1] = NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_MSDU(IngressStreamTableEntry->IngressStreamCfgeData.MaximumServiceDataUnit) \
4293 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_IFMELENCHG(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4294 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_EPORT(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4295 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OETEID(NETC_ETH_IP_BD_ZERO_ENTRY_ID) \
4296 | NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_CTD(NETC_ETH_IP_BD_ZERO_ENTRY_ID);
4297 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA2] = NETC_ETH_IP_BD_NULL_ENTRY_ID;
4298 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA3] = IngressStreamTableEntry->IngressStreamCfgeData.RatePolicer_EID;
4299 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA4] = IngressStreamTableEntry->IngressStreamCfgeData.StreamGateInstance_EID;
4300 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA5] = NETC_ETH_IP_BD_NULL_ENTRY_ID;
4301 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA6] = NETC_ETH_IP_BD_NULL_ENTRY_ID;
4302 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA7] = IngressStreamTableEntry->IngressStreamCfgeData.IngressStreamCounter_EID;
4303 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA8] = NETC_ETH_IP_BD_ZERO_ENTRY_ID;
4304 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_CFGEDATA9] = NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SIMAP(IngressStreamTableEntry->IngressStreamCfgeData.StationInterfaceMap);
4305
4306 /* fill in operation data for config field of Request Header*/
4307 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
4308 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
4309 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_TABLE_ID;
4310 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for Add and Update command, the Access Method should only be NETC_ETH_ENTRY_ID_MATCH */
4311 Netc_Eth_Ip_OperationData.Cmd = Cmd;
4312 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSSTREAMTABLE_REQBUFFER_LEN);
4313 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN);
4314
4315 /* send command */
4316 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
4317 #if defined(ERR_IPV_NETC_051243)
4318 #if (STD_ON == ERR_IPV_NETC_051243)
4319 /* Error code 0x8A is not a real error. check it on Errata. */
4320 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
4321 {
4322 #endif
4323 #else
4324 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4325 {
4326 #endif
4327 status = NETC_ETH_IP_STATUS_SUCCESS;
4328 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
4329 }
4330 }
4331
4332 return status;
4333 }
4334
4335 /*FUNCTION**********************************************************************
4336 *
4337 * Function Name : Netc_Eth_Ip_QueryIngressStreamTableEntry
4338 * Description : Ethernet Switch query Ingress Stream table entry function.
4339 *
4340 *END**************************************************************************/
4341 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryIngressStreamTableEntry( const uint8 CtrlIndex,
4342 uint32 *MatchedEntries,
4343 uint32 IngressStreamEntryId,
4344 Netc_Eth_Ip_IngressStreamEntryDataType * IngressStreamTableEntry
4345 )
4346 {
4347 Netc_Eth_Ip_StatusType status;
4348 uint32 ActionsData;
4349 uint32 CfgeConfigBits;
4350 uint32 CfgeConfigBits2;
4351 uint8 SduType;
4352
4353 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4354 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4355 DevAssert(MatchedEntries != NULL_PTR);
4356 DevAssert(IngressStreamTableEntry != NULL_PTR);
4357 #endif
4358
4359 /* clear the variable MatchedEntries first */
4360 *MatchedEntries = 0U;
4361
4362 /* always do the full query. 0x0 = Full query. */
4363 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY) \
4364 | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_TABLE_VERSIONS(0U);
4365
4366 /* ------initialize the table request data buffer------ */
4367 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
4368 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = IngressStreamEntryId; /* fill in Entry_ID field (Access Key) */
4369
4370 /* fill in operation data for config field of Request Header*/
4371 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
4372 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
4373 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_TABLE_ID;
4374 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for query command, always uses NETC_ETH_ENTRY_ID_MATCH method */
4375 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
4376 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
4377 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_INGRESSSTREAMTABLE_RSPBUFFER_LEN); /* set response data buffer length */
4378
4379 /* send command */
4380 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
4381 #if defined(ERR_IPV_NETC_051243)
4382 #if (STD_ON == ERR_IPV_NETC_051243)
4383 /* Error code 0x8A is not a real error. check it on Errata. */
4384 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
4385 {
4386 #endif
4387 #else
4388 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4389 {
4390 #endif
4391 status = NETC_ETH_IP_STATUS_SUCCESS;
4392 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
4393
4394 /* found a matched entry */
4395 if (1U == *MatchedEntries)
4396 {
4397 /* fill in "Netc_Eth_Ip_IngressStreamEntryDataType" structure with data in response data buffer */
4398 IngressStreamTableEntry->IngressStreamEntryId = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[0U];
4399 /* fill in CFGE data */
4400 CfgeConfigBits = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U];
4401 IngressStreamTableEntry->IngressStreamCfgeData.StreamFilteringEnable = ((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SFE_MASK) > 0U) ? TRUE : FALSE;
4402 IngressStreamTableEntry->IngressStreamCfgeData.InternalPriorityValue = (uint8)((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_IPV_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_IPV_SHIFT);
4403 IngressStreamTableEntry->IngressStreamCfgeData.OverrideIPV = (((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OIPV_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OIPV_SHIFT) > 0U) ? TRUE : FALSE;
4404 IngressStreamTableEntry->IngressStreamCfgeData.DropResilience = (uint8)((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_DR_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_DR_SHIFT);
4405 IngressStreamTableEntry->IngressStreamCfgeData.OverrideDR = (((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ODR_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ODR_SHIFT) > 0U) ? TRUE : FALSE;
4406 IngressStreamTableEntry->IngressStreamCfgeData.OverrideRatePolicerInstanceEID = (((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ORP_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_ORP_SHIFT) > 0U) ? TRUE : FALSE;
4407 IngressStreamTableEntry->IngressStreamCfgeData.OverrideStreamGateInstanceEID = (((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OSGI_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_OSGI_SHIFT) > 0U) ? TRUE : FALSE;
4408 IngressStreamTableEntry->IngressStreamCfgeData.ForwardingActions = ((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_FA_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_FA_SHIFT);
4409 SduType = (uint8)((CfgeConfigBits & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SDUTYPE_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SDUTYPE_SHIFT);
4410 switch (SduType)
4411 {
4412 case 0U:
4413 IngressStreamTableEntry->IngressStreamCfgeData.SduType = NETC_ETH_IP_PPDU;
4414 break;
4415 case 1U:
4416 IngressStreamTableEntry->IngressStreamCfgeData.SduType = NETC_ETH_IP_MPDU;
4417 break;
4418 case 2U:
4419 IngressStreamTableEntry->IngressStreamCfgeData.SduType = NETC_ETH_IP_MSDU;
4420 break;
4421 default:
4422 IngressStreamTableEntry->IngressStreamCfgeData.SduType = NETC_ETH_IP_RSDTYPE;
4423 break;
4424 }
4425
4426 CfgeConfigBits2 = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U];
4427 IngressStreamTableEntry->IngressStreamCfgeData.MaximumServiceDataUnit = (uint16)((CfgeConfigBits2 & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_MSDU_MASK) >> NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_MSDU_SHIFT);
4428
4429 IngressStreamTableEntry->IngressStreamCfgeData.RatePolicer_EID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U];
4430 IngressStreamTableEntry->IngressStreamCfgeData.StreamGateInstance_EID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U];
4431 IngressStreamTableEntry->IngressStreamCfgeData.IngressStreamCounter_EID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U];
4432 IngressStreamTableEntry->IngressStreamCfgeData.StationInterfaceMap = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[10U] & NETC_ETH_IP_INGRESSSTREAMTABLE_CFGE_SIMAP_MASK);
4433 }
4434 }
4435
4436 return status;
4437 }
4438
4439 /*FUNCTION**********************************************************************
4440 *
4441 * Function Name : Netc_Eth_Ip_DeleteIngressStreamTableEntry
4442 * Description : Ethernet Switch delete Ingress Stream table entry function.
4443 *
4444 *END**************************************************************************/
4445 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteIngressStreamTableEntry( const uint8 CtrlIndex,
4446 uint32 *MatchedEntries,
4447 uint32 IngressStreamEntryId
4448 )
4449 {
4450 Netc_Eth_Ip_StatusType status;
4451 uint32 ActionsData = 0U;
4452
4453 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
4454 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
4455 DevAssert(MatchedEntries != NULL_PTR);
4456 #endif
4457
4458 /* clear the variable MatchedEntries first */
4459 *MatchedEntries = 0U;
4460 /* ------initialize the table request data buffer------ */
4461 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* Delete command will ignore ActionsData data field */
4462 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = IngressStreamEntryId; /* fill in Entry_ID field (Access Key) */
4463
4464 /* fill in operation data for config field of Request Header*/
4465 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
4466 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
4467 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_STREAM_TABLE_ID;
4468 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH; /* for delete command, always uses NETC_ETH_ENTRY_ID_MATCH method */
4469 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_DELETE_CMD;
4470 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN); /* set request data buffer length */
4471 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN); /* set response data buffer with normal length */
4472
4473 /* send the "Delete" command */
4474 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
4475 #if defined(ERR_IPV_NETC_051243)
4476 #if (STD_ON == ERR_IPV_NETC_051243)
4477 /* Error code 0x8A is not a real error. check it on Errata. */
4478 if (((uint16)status == 0x8AU) || (status == NETC_ETH_IP_STATUS_SUCCESS))
4479 #else
4480 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4481 #endif
4482 #else
4483 if (status == NETC_ETH_IP_STATUS_SUCCESS)
4484 #endif
4485 {
4486 status = NETC_ETH_IP_STATUS_SUCCESS;
4487 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
4488 }
4489
4490 return status;
4491 }
4492
4493 Netc_Eth_Ip_StatusType Netc_Eth_Ip_CheckFrameStatus(uint8 ctrlIndex,
4494 uint8 ring,
4495 uint32 ConsumerIndex,
4496 const uint8 *buff,
4497 Netc_Eth_Ip_TxInfoType *info)
4498
4499 {
4500
4501 Netc_Eth_Ip_TxBDRType *txBDR;
4502 uint32 LastDescrCheckIndex;
4503 volatile uint32 CurrDescrCheckIndex;
4504 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4505 uint32 currentTimeHigh;
4506 uint32 currentTimeLow;
4507 uint64 nanoSeconds;
4508 #ifdef NETC_ETH_0_USED
4509 uint16 ManagementInfoIndex;
4510 #endif /* NETC_ETH_0_USED */
4511 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
4512 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
4513
4514 LastDescrCheckIndex= Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring];
4515 /* Get the addres of the current BDR to get status for it. */
4516 CurrDescrCheckIndex = (uint32)( (LastDescrCheckIndex + NETC_ETH_IP_PRODUCER_INCR) % \
4517 (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring] );
4518
4519 /* Verification that the current frame we check is mapped on the right BD in hardware
4520 In Autosar case this check will never happen because the frame buffers are always provided in order
4521 from the upper layer.
4522 */
4523 #ifdef MCAL_ENABLE_FAULT_INJECTION
4524 MCAL_FAULT_INJECTION_POINT(ETH_READ_BUFFER_ADDRESS_FIP);
4525 #endif
4526 if (buff == Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffAddr[ring][LastDescrCheckIndex])
4527 {
4528 if ((ConsumerIndex != LastDescrCheckIndex) && \
4529 ((boolean)TRUE == Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][LastDescrCheckIndex]))
4530 {
4531 /* Get the descriptor corresponding to the buff pointer (by looping through the descriptors) */
4532 txBDR = (Netc_Eth_Ip_TxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ring]) + (((uint32)(LastDescrCheckIndex / NETC_ETH_IP_PRODUCER_INCR)) * ((uint32)(sizeof(Netc_Eth_Ip_TxBDRType)))));
4533 /* Check if there was a writeback in the descriptor */
4534 if (NETC_ETH_IP_TXBD_WRITEBACK_MASK == (txBDR->buffConfig & NETC_ETH_IP_TXBD_WRITEBACK_MASK))
4535 {
4536 /* Check the STATUS bitfield and read the possible errors and store them in info */
4537 if ((0U != (uint16)(((Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->FlagsAndStatus & NETC_ETH_IP_TX_WB_STATUS_MASK)) && \
4538 (NULL_PTR != info))
4539 {
4540 info->txStatus = (Netc_Eth_Ip_TxStatusType)(((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->FlagsAndStatus & NETC_ETH_IP_TX_WB_STATUS_MASK);
4541 }
4542 else
4543 {
4544 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
4545 /* Get the frame Timestamp */
4546 if (NULL_PTR != info)
4547 {
4548 /*Read the HIGH Part from SICTR registers in a succesive manner, first the LOW part, then imediately, the HIGH part*/
4549 currentTimeLow = (uint32)(netcSIsBase[ctrlIndex]->SICTR0);
4550 currentTimeHigh = (uint32)(netcSIsBase[ctrlIndex]->SICTR1);
4551
4552 /*Check for overflow on Low part of the timer*/
4553 if( (uint32) (((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->Timestamp) > currentTimeLow)
4554 {
4555 currentTimeHigh--;
4556 }
4557
4558 nanoSeconds = (uint64) ( (uint64)(((uint64)currentTimeHigh) << 32U) | (uint64)((const Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->Timestamp );
4559
4560 /*Take the nanoseconds*/
4561 info->timestamp.nanoseconds = (uint32) (NETC_ETH_IP_GET_NANOSECONDS(nanoSeconds));
4562
4563 /*Take the seconds, the low part of 32bits*/
4564 info->timestamp.seconds = (uint32) (NETC_ETH_IP_NANO_TO_SECONDS(nanoSeconds) & NETC_ETH_IP_SECONDS_LOW_MASK_U64);
4565
4566 /*Take the seconds, the high part of 16bits*/
4567 info->timestamp.secondsHi = (uint16) ((NETC_ETH_IP_NANO_TO_SECONDS(nanoSeconds) >> 32U) & 0xFFFFU);
4568 }
4569
4570 #ifdef NETC_ETH_0_USED
4571 if ((NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType) && ((uint8)0U == ring))
4572 {
4573 ManagementInfoIndex = LastDescrCheckIndex / NETC_ETH_IP_PRODUCER_INCR;
4574
4575 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][ManagementInfoIndex].TxTimeStampID = (uint16)(((Netc_Eth_Ip_TxBDRWritebackType *)txBDR)->TxTimestampID);
4576
4577 /* Mark frame as sent in management object */
4578 switch(Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][ManagementInfoIndex].State)
4579 {
4580 case NETC_ETH_IP_TX_MGMT_QUEUED:
4581 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][ManagementInfoIndex].State = NETC_ETH_IP_TX_MGMT_READY;
4582 break;
4583 case NETC_ETH_IP_TX_MGMT_QUEUED_TIMESTAMP:
4584 Netc_Eth_Ip_TxManagementInfoBuff[ctrlIndex][ManagementInfoIndex].State = NETC_ETH_IP_TX_MGMT_WAITING_TIMESTAMP;
4585 break;
4586 default:
4587 /* This case should never be accessed. */
4588 break;
4589 }
4590 }
4591 #endif
4592 #else
4593 (void)info;
4594 #endif
4595
4596 }
4597 }
4598 else
4599 {
4600 if (NULL_PTR != info)
4601 {
4602 /* The writeback will only be set if there is a problem sending the frame.
4603 If the frame is sent successfully the status needs to be set manually */
4604 info->txStatus = NETC_ETH_TX_NO_ERR;
4605 }
4606 }
4607 /* Update status of the data buffer. */
4608 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][LastDescrCheckIndex] = FALSE;
4609 /* Update the value for the last data buffer checked for the next call. */
4610 Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring] = CurrDescrCheckIndex;
4611 }
4612 else
4613 {
4614 status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
4615 }
4616 }
4617 else
4618 {
4619 status = NETC_ETH_IP_STATUS_BUFF_NOT_FOUND;
4620 }
4621
4622 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
4623 #if (NETC_ETH_IP_FILL_LEVEL_API_ENABLE == STD_ON)
4624 Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].NumberOfUsedBuff = ((ConsumerIndex <= Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring]) ?
4625 (Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring] - ConsumerIndex) : (Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].TotalNumberOfBuff + 1U - ConsumerIndex + Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring]));
4626
4627 if (Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].MaxNumberOfUsedBuff < Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].NumberOfUsedBuff)
4628 {
4629 Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].MaxNumberOfUsedBuff = Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].NumberOfUsedBuff;
4630 }
4631 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
4632 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
4633
4634 return status;
4635 }
4636
4637 /*FUNCTION**********************************************************************
4638 *
4639 * Function Name : Netc_Eth_Ip_ConfigCreditBasedShaperReg
4640 * Description : Internal function for configuring credit based shaper registers.
4641 *
4642 *END**************************************************************************/
4643 static inline void Netc_Eth_Ip_ConfigCreditBasedShaperReg(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
4644 {
4645 uint8 trafficClass;
4646 uint32 localPtcTmSDUR;
4647
4648 (void)ctrlIndex;
4649 if(config->generalConfig->cbsConfig != NULL_PTR)
4650 {
4651 for(trafficClass = 0U; trafficClass < NETC_ETH_IP_NUMBER_OF_PRIORITIES; trafficClass++)
4652 {
4653 /* Coonfigure the maximum frame size per shaping class, Max 2000 */
4654 localPtcTmSDUR = IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCTMSDUR;
4655 localPtcTmSDUR &= ~ENETC_PORT_PTCTMSDUR_MAXSDU_MASK;
4656 localPtcTmSDUR |= ENETC_PORT_PTCTMSDUR_MAXSDU(config->generalConfig->cbsConfig[trafficClass]->EthMaxSizedFrame);
4657 IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCTMSDUR = localPtcTmSDUR;
4658
4659 IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCCBSR0 = ENETC_PORT_PTCCBSR0_CBSE(config->generalConfig->cbsConfig[trafficClass]->EthEgressCBShaperEnable ? 1U : 0U)
4660 | ENETC_PORT_PTCCBSR0_BW(config->generalConfig->cbsConfig[trafficClass]->EthEgressCBShaperBandwidth);
4661 IP_NETC__ENETC0_PORT->TCT_NUM[trafficClass].PTCCBSR1 = ENETC_PORT_PTCCBSR1_HI_CREDIT(config->generalConfig->cbsConfig[trafficClass]->EthEgressHiCredit);
4662 }
4663 }
4664 }
4665
4666 /*FUNCTION**********************************************************************
4667 *
4668 * Function Name : Netc_Eth_Ip_SetupErrorReporting
4669 * Description : Internal function for configuring register used in reporting error to Pcie Event collector.
4670 *
4671 *END**************************************************************************/
4672 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetupErrorReporting(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config)
4673 {
4674 /** @brief Enum with the generic Pcie Functions present in the NETC SOC. */
4675 const Netc_Eth_Ip_PcieFunction Netc_Eth_Ip_PcieFunctionMapping[FEATURE_NETC_NUMBER_OF_FUNC] = {TIMER, EMDIO, SWITCH, PSI};
4676
4677 uint8 u8Iterator = 0U;
4678 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
4679
4680 if (
4681 ((IP_NETC__NETC_F0_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
4682 NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
4683 (NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
4684 NETC_F0_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U) ||
4685 ((IP_NETC__NETC_F1_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
4686 NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
4687 (NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
4688 NETC_F1_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U) ||
4689 ((IP_NETC__NETC_F2_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
4690 NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
4691 (NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
4692 NETC_F2_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U) ||
4693 ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCI_CFH_CMD & ((uint16) (NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK <<
4694 NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT) |
4695 (NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK <<
4696 NETC_F3_PCI_HDR_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT))) == (uint16)0U)
4697 )
4698 {
4699 Status = NETC_ETH_IP_STATUS_ERROR;
4700 }
4701
4702 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator++)
4703 {
4704 /* Initialize the error reporting structure which will revel the status on SWITCH, TIMER, EMDIO and PSI */
4705 Netc_Eth_Ip_ErrorStatus[u8Iterator].Function = Netc_Eth_Ip_PcieFunctionMapping[u8Iterator];
4706 Netc_Eth_Ip_ErrorStatus[u8Iterator].StatusErrors = 0U;
4707 }
4708
4709 for (u8Iterator = FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator < (FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS + FEATURE_NETC_NUMBER_OF_FUNC); u8Iterator++)
4710 {
4711 /* Initialize the error reporting structure which will reveal the status on each VSI */
4712 Netc_Eth_Ip_ErrorStatus[u8Iterator].Function = VSI;
4713 Netc_Eth_Ip_ErrorStatus[u8Iterator].StatusErrors = 0U;
4714 }
4715
4716 /*For the Event Collector to assert INTA for a reported error, it must clear the interrupt disable bit:*/
4717 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCI_CFH_CMD = ierc_pci_PCI_CFH_CMD_INTR_DISABLE(0u);
4718
4719 /* Enable the Pcie AER Error Reporting */
4720 if (psi0Config->enableUncorrectableErrors)
4721 {
4722 Netc_Eth_Ip_SetupErrorReporting_EnableUncorrectableErrors(psi0Config);
4723 }
4724 if (psi0Config->enableCorrectableErrors)
4725 {
4726 Netc_Eth_Ip_SetupErrorReporting_EnableCorrectableErrors(psi0Config);
4727 }
4728
4729 return Status;
4730 }
4731
4732 #if (NETC_ETH_MAX_NUMBER_OF_IPFTABLE_LIST > 0U)
4733 /* inline function for initializing ingress port filter table entries data during ENETC init */
4734 static inline void Netc_Eth_Ip_InitIPFTableEntryData(const Netc_Eth_Ip_ConfigType * Config, uint8 IPFTableListIdx, Netc_Eth_Ip_IngressPortFilterEntryDataType *IngressPortFilterTableEntry)
4735 {
4736 uint8 MacByteIdx;
4737 uint8 IpByteIdx;
4738 uint8 PayloadDataIdx;
4739
4740 IngressPortFilterTableEntry->IngressPortFilterEntryID = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterEntryID;
4741
4742 /* fill in cfge data */
4743 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeTargetForSelectedFilterAction = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeTargetForSelectedFilterAction;
4744 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeIpv = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeIpv;
4745 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeDr = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeDr;
4746 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeRelativePrecedentResolution = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeRelativePrecedentResolution;
4747 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideIpv = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeOverrideIpv;
4748 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideDr = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeOverrideDr;
4749 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeWakeOnLanTriggerEnable = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeWakeOnLanTriggerEnable;
4750 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterForwardingAction = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeFilterForwardingAction;
4751 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterAction = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterCfgeData.CfgeFilterAction;
4752
4753 /* fill in keye data */
4754 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePrecedence = 3U;
4755 IngressPortFilterTableEntry->IngressPortFilterkeyeData.keyeFrmAttributeFlags = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.keyeFrmAttributeFlags;
4756 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask;
4757 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint;
4758 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask;
4759 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation;
4760 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask;
4761 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Dst Mac Address */
4762 {
4763 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDstMacAddr[MacByteIdx];
4764 }
4765 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Dst Mac Address Mask */
4766 {
4767 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeDstMacAddrMask[MacByteIdx];
4768 }
4769 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Src Mac Address */
4770 {
4771 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeSrcMacAddr[MacByteIdx];
4772 }
4773 for (MacByteIdx = 0U; MacByteIdx < 6U; MacByteIdx++) /* Src Mac Address Mask */
4774 {
4775 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[MacByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeSrcMacAddrMask[MacByteIdx];
4776 }
4777 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation;
4778 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask;
4779 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherType = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeEtherType;
4780 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeEtherTypeMask;
4781 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocol = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPProtocol;
4782 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocolMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPProtocolMask;
4783 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Source Address */
4784 {
4785 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddress[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPSourceAddress[IpByteIdx];
4786 }
4787 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Source Address Mask */
4788 {
4789 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddressMask[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPSourceAddressMask[IpByteIdx];
4790 }
4791 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePort = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4SourcePort;
4792 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePortMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4SourcePortMask;
4793 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Destination Address */
4794 {
4795 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddress[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPDestinationAddress[IpByteIdx];
4796 }
4797 for (IpByteIdx = 0U; IpByteIdx < 4U; IpByteIdx++) /* IP Destination Address Mask */
4798 {
4799 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[IpByteIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[IpByteIdx];
4800 }
4801 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPort = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4DestinationPort;
4802 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPortMask = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyeL4DestinationPortMask;
4803
4804 /* fill in payload data */
4805 for (PayloadDataIdx = 0U; PayloadDataIdx < 24U; PayloadDataIdx++)
4806 {
4807 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[PayloadDataIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyePayloadBytes[PayloadDataIdx];
4808 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[PayloadDataIdx] = (*(*Config->generalConfig).IngressPortFilterTableList)[IPFTableListIdx].IngressPortFilterkeyeData.KeyePayloadBytesMask[PayloadDataIdx];
4809 }
4810
4811 }
4812 #endif
4813 /*FUNCTION**********************************************************************
4814 *
4815 * Function Name : Netc_Eth_Ip_ClearErrorStatus
4816 * Description : Internal function that reads the status bit of a error reporting registers and clears it.
4817 *
4818 *END**************************************************************************/
4819 static inline boolean Netc_Eth_Ip_ClearErrorStatus (volatile uint32 *RegAddress)
4820 {
4821 boolean returnValue = FALSE;
4822
4823 if ((*RegAddress & NETC_ETH_IP_CLEAR_ERROR_STATUS_MASK) != 0U)
4824 {
4825 *RegAddress |= NETC_ETH_IP_CLEAR_ERROR_STATUS_MASK;
4826 returnValue = TRUE;
4827 }
4828
4829 return returnValue;
4830 }
4831 /*FUNCTION**********************************************************************
4832 *
4833 * Function Name : Netc_Eth_Ip_GetErrorStatisticsForEMDIO
4834 * Description : Internal function for reading the error status registers for EMDIO
4835 *
4836 *END**************************************************************************/
4837 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForEMDIO (const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
4838 {
4839 uint8 countRegisters = 0U;
4840
4841 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
4842 {
4843 /*This is the EMDIO uncorrectable non-fatal integrity error status register*/
4844 if (Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *)&(((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUNIESR)))
4845 {
4846 if (Buffers[countRegisters] != NULL_PTR)
4847 {
4848 Buffers[countRegisters]->RegName = EMDIOUNIESR;
4849 Buffers[countRegisters]->RegRawValueLow = ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUNIESR;
4850 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
4851 countRegisters++;
4852 }
4853 }
4854 /* EMDIO system bus error status register. */
4855 if (Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUFSBESR)))
4856 {
4857 if (Buffers[countRegisters] != NULL_PTR)
4858 {
4859 /* EMDIO system bus error. */
4860 Buffers[countRegisters]->RegName = EMDIOUFSBESR;
4861 Buffers[countRegisters]->RegRawValueLow = ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUFSBESR;
4862 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
4863 countRegisters++;
4864 }
4865 }
4866 }
4867 return countRegisters;
4868 }
4869
4870 /*FUNCTION**********************************************************************
4871 *
4872 * Function Name : Netc_Eth_Ip_GetSystemBusErrorStatisticsForSWITCH
4873 * Description : Internal function for reading the system bus non fatal error status registers for SWITCH
4874 *
4875 *END**************************************************************************/
4876 static inline void Netc_Eth_Ip_GetSystemBusErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
4877 {
4878 /* Switch system bus error.*/
4879 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__SW0_COMMON->UNSBESR)))
4880 {
4881 if (Buffers[*countRegisters] != NULL_PTR)
4882 {
4883 Buffers[*countRegisters]->RegName = UNSBESR;
4884 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNSBESR;
4885 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4886 (*countRegisters)++;
4887 }
4888 if (Buffers[*countRegisters] != NULL_PTR)
4889 {
4890 /* Indicates how many system bus error events have been encountered. UNSBESR[SB_ID] indicates the last source*/
4891 Buffers[*countRegisters]->RegName = UNSBECTR;
4892 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNSBECTR;
4893 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4894 (*countRegisters)++;
4895 }
4896 }
4897 }
4898
4899 /*FUNCTION**********************************************************************
4900 *
4901 * Function Name : Netc_Eth_Ip_GetMemoryErrorStatisticsForSWITCH
4902 * Description : Internal function for reading the Uncorrectable non-fatal memory error status registers for SWITCH
4903 *
4904 *END**************************************************************************/
4905 static inline void Netc_Eth_Ip_GetMemoryErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
4906 {
4907 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__SW0_COMMON->UNMESR0)))
4908 {
4909 if (Buffers[*countRegisters] != NULL_PTR)
4910 {
4911 /* Memory ID + Syndrome*/
4912 Buffers[*countRegisters]->RegName = UNMESR0;
4913 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNMESR0;
4914 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4915 (*countRegisters)++;
4916 }
4917 if (Buffers[*countRegisters] != NULL_PTR)
4918 {
4919 /* Address information (row) of last ECC event.*/
4920 Buffers[*countRegisters]->RegName = UNMESR1;
4921 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNMESR1;
4922 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4923 (*countRegisters)++;
4924 }
4925 if (Buffers[*countRegisters] != NULL_PTR)
4926 {
4927 /* This is the uncorrectable non-fatal memory error count register which tracks how many events have been detected.*/
4928 Buffers[*countRegisters]->RegName = UNMECTR;
4929 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNMECTR;
4930 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4931 (*countRegisters)++;
4932 }
4933 }
4934 }
4935
4936 /*FUNCTION**********************************************************************
4937 *
4938 * Function Name : Netc_Eth_Ip_GetPort0ErrorStatisticsForSWITCH
4939 * Description : Internal function for reading the Port0 error status registers for SWITCH
4940 *
4941 *END**************************************************************************/
4942 static inline void Netc_Eth_Ip_GetPort0ErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
4943 {
4944 if (Buffers[*countRegisters] != NULL_PTR)
4945 {
4946 Buffers[*countRegisters]->RegName = PM0_RERR;
4947 Buffers[*countRegisters]->RegRawValueLow = (uint32)(IP_NETC__SW0_ETH_MAC_PORT0->PM0_RERRN);
4948 Buffers[*countRegisters]->RegRawValueHigh = (uint32)(IP_NETC__SW0_ETH_MAC_PORT0->PM0_RERRN >> 32U);
4949 (*countRegisters)++;
4950 }
4951 if (Buffers[*countRegisters] != NULL_PTR)
4952 {
4953 /* EventError.*/
4954 Buffers[*countRegisters]->RegName = PM0_EVENT;
4955 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT0->PM0_IEVENT;
4956 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4957 (*countRegisters)++;
4958 }
4959 if (Buffers[*countRegisters] != NULL_PTR)
4960 {
4961 /* A count of received MAC frames / MAC frame fragments rejected due to unknown
4962 SMD value or arriving with an SMD-C when no frame is in progress.*/
4963 Buffers[*countRegisters]->RegName = MAC_MERGE_MMFSECR0;
4964 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT0->MAC_MERGE_MMFSECR;
4965 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4966 (*countRegisters)++;
4967 }
4968 if (Buffers[*countRegisters] != NULL_PTR)
4969 {
4970 /* A count of MAC frames with reassembly errors.*/
4971 Buffers[*countRegisters]->RegName = MAC_MERGE_MMFAECR0;
4972 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT0->MAC_MERGE_MMFAECR;
4973 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4974 (*countRegisters)++;
4975 }
4976 }
4977
4978 /*FUNCTION**********************************************************************
4979 *
4980 * Function Name : Netc_Eth_Ip_GetPort1ErrorStatisticsForSWITCH
4981 * Description : Internal function for reading the Port1 error status registers for SWITCH
4982 *
4983 *END**************************************************************************/
4984 static inline void Netc_Eth_Ip_GetPort1ErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
4985 {
4986 if (Buffers[*countRegisters] != NULL_PTR)
4987 {
4988 Buffers[*countRegisters]->RegName = PM1_RERR;
4989 Buffers[*countRegisters]->RegRawValueLow = (uint32)(IP_NETC__SW0_ETH_MAC_PORT1->PM1_RERRN);
4990 Buffers[*countRegisters]->RegRawValueHigh = (uint32)(IP_NETC__SW0_ETH_MAC_PORT1->PM1_RERRN >> 32U);
4991 (*countRegisters)++;
4992 }
4993 if (Buffers[*countRegisters] != NULL_PTR)
4994 {
4995 /* EventError.*/
4996 Buffers[*countRegisters]->RegName = PM1_EVENT;
4997 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT1->PM1_IEVENT;
4998 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
4999 (*countRegisters)++;
5000 }
5001 if (Buffers[*countRegisters] != NULL_PTR)
5002 {
5003 /* A count of received MAC frames / MAC frame fragments rejected due to unknown
5004 SMD value or arriving with an SMD-C when no frame is in progress.*/
5005 Buffers[*countRegisters]->RegName = MAC_MERGE_MMFSECR1;
5006 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT1->MAC_MERGE_MMFSECR;
5007 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5008 (*countRegisters)++;
5009 }
5010 if (Buffers[*countRegisters] != NULL_PTR)
5011 {
5012 /* A count of MAC frames with reassembly errors.*/
5013 Buffers[*countRegisters]->RegName = MAC_MERGE_MMFAECR1;
5014 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_ETH_MAC_PORT1->MAC_MERGE_MMFAECR;
5015 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5016 (*countRegisters)++;
5017 }
5018 }
5019
5020 /*FUNCTION**********************************************************************
5021 *
5022 * Function Name : Netc_Eth_Ip_GetIntegrityFaultStatisticsForSWITCH
5023 * Description : Internal function for reading the uncorrectable non-fatal integrity error statistics registers for SWITCH
5024 *
5025 *END**************************************************************************/
5026 static inline void Netc_Eth_Ip_GetIntegrityFaultStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5027 {
5028 /* Integrity fault*/
5029 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->UNIESR)))
5030 {
5031 if (Buffers[*countRegisters] != NULL_PTR)
5032 {
5033 Buffers[*countRegisters]->RegName = UNIESR;
5034 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNIESR;
5035 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5036 (*countRegisters)++;
5037 }
5038 /* Indicates the number of non-fatal integrity faults detected which includes internal FCS and parity errors.*/
5039 if (Buffers[*countRegisters] != NULL_PTR)
5040 {
5041 Buffers[*countRegisters]->RegName = UNIECTR;
5042 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UNIECTR;
5043 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5044 (*countRegisters)++;
5045 }
5046 }
5047 }
5048
5049 /*FUNCTION**********************************************************************
5050 *
5051 * Function Name : Netc_Eth_Ip_GetFatalErrorStatisticsForSWITCH
5052 * Description : Internal function for reading the fatal error statistics registers for SWITCH
5053 *
5054 *END**************************************************************************/
5055 static inline void Netc_Eth_Ip_GetFatalErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5056 {
5057 /* Fatal system bus error status register. */
5058 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->UFSBESR)))
5059 {
5060 if (Buffers[*countRegisters] != NULL_PTR)
5061 {
5062 Buffers[*countRegisters]->RegName = UFSBESR;
5063 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFSBESR;
5064 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5065 (*countRegisters)++;
5066 }
5067 }
5068 /* Uncorrectable fatal memory error status register 0.*/
5069 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->UFMESR0)))
5070 {
5071 if (Buffers[*countRegisters] != NULL_PTR)
5072 {
5073 Buffers[*countRegisters]->RegName = UFMESR0;
5074 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFMESR0;
5075 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5076 (*countRegisters)++;
5077 }
5078 if (Buffers[*countRegisters] != NULL_PTR)
5079 {
5080 Buffers[*countRegisters]->RegName = UFMESR1;
5081 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFMESR1;
5082 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5083 (*countRegisters)++;
5084 }
5085 }
5086 /* Fatal integrity error status register. */
5087 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__SW0_COMMON->UFIESR)))
5088 {
5089 if (Buffers[*countRegisters] != NULL_PTR)
5090 {
5091 Buffers[*countRegisters]->RegName = UFIESR;
5092 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->UFIESR;
5093 Buffers[*countRegisters]->RegRawValueHigh = 0U;
5094 (*countRegisters)++;
5095 }
5096 }
5097 }
5098
5099 /*FUNCTION**********************************************************************
5100 *
5101 * Function Name : Netc_Eth_Ip_GetCorrectableErrorStatisticsForSWITCH
5102 * Description : Internal function for reading the Correctable error statistics registers for SWITCH
5103 *
5104 *END**************************************************************************/
5105 static inline void Netc_Eth_Ip_GetCorrectableErrorStatisticsForSWITCH (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5106 {
5107 /* Internal memory single bit ECC error*/
5108 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(IP_NETC__SW0_COMMON->CMESR)))
5109 {
5110 if (Buffers[*countRegisters] != NULL_PTR)
5111 {
5112 /* correctable memory error */
5113 Buffers[*countRegisters]->RegName = CMESR;
5114 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__SW0_COMMON->CMESR;
5115 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5116 (*countRegisters)++;
5117 }
5118 }
5119 }
5120
5121 /*FUNCTION**********************************************************************
5122 *
5123 * Function Name : Netc_Eth_Ip_GetErrorStatisticsForSWITCH
5124 * Description : Internal function for gathering error statistics information for SWITCH
5125 *
5126 *END**************************************************************************/
5127 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForSWITCH (const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5128 {
5129 uint8 countRegisters = 0U;
5130
5131 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerCorrectableErrEnabled)
5132 {
5133 Netc_Eth_Ip_GetCorrectableErrorStatisticsForSWITCH(&countRegisters, Buffers);
5134 }
5135
5136 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5137 {
5138 Netc_Eth_Ip_GetSystemBusErrorStatisticsForSWITCH (&countRegisters, Buffers);
5139
5140 Netc_Eth_Ip_GetMemoryErrorStatisticsForSWITCH (&countRegisters, Buffers);
5141
5142 /* Incremented for each frame received with an error (except for undersized/fragment frame):
5143 FIFO overflow error
5144 CRC error
5145 Payload length error
5146 Jabber and oversized error
5147 Alignment error
5148 A non-fatal error has occurred in the Ethernet MAC bound to PORT0. See PMa_IEVENT for details and how to clear the event*/
5149 if((IP_NETC__SW0_COMMON->UNMACESR & (uint32)0x01) != (uint32)0U)
5150 {
5151 Netc_Eth_Ip_GetPort0ErrorStatisticsForSWITCH(&countRegisters, Buffers);
5152 }
5153
5154 if((IP_NETC__SW0_COMMON->UNMACESR & (uint32)0x02) != (uint32)0U)
5155 {
5156 Netc_Eth_Ip_GetPort1ErrorStatisticsForSWITCH (&countRegisters, Buffers);
5157 }
5158
5159 Netc_Eth_Ip_GetIntegrityFaultStatisticsForSWITCH(&countRegisters, Buffers);
5160
5161 Netc_Eth_Ip_GetFatalErrorStatisticsForSWITCH(&countRegisters, Buffers);
5162 }
5163 return countRegisters;
5164 }
5165
5166 /*FUNCTION**********************************************************************
5167 *
5168 * Function Name : Netc_Eth_Ip_GetErrorStatisticsForTIMER
5169 * Description : Internal function for gathering error statistics information for TIMER
5170 *
5171 *END**************************************************************************/
5172 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForTIMER(const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5173 {
5174 uint8 countRegisters = 0U;
5175
5176 /* timer system bus error. */
5177 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5178 {
5179 if (Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(((IP_NETC__TMR0_GLOBAL->ERROR).TIMER).TUFSBESR )))
5180 {
5181 if (Buffers[countRegisters] != NULL_PTR)
5182 {
5183 Buffers[countRegisters]->RegName = TUFSBESR;
5184 Buffers[countRegisters]->RegRawValueLow = ((IP_NETC__TMR0_GLOBAL->ERROR).TIMER).TUFSBESR;
5185 Buffers[countRegisters]->RegRawValueHigh = (uint32)0U;
5186 countRegisters++;
5187 }
5188 }
5189 }
5190 return countRegisters;
5191 }
5192
5193 /*FUNCTION**********************************************************************
5194 *
5195 * Function Name : Netc_Eth_Ip_GetCorrectableErrorStatisticsForENETC
5196 * Description : Internal function for reading the Correctable error statistics registers for ENETC
5197 *
5198 *END**************************************************************************/
5199 static inline void Netc_Eth_Ip_GetCorrectableErrorStatisticsForENETC (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5200 {
5201 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->CMESR)))
5202 {
5203 if (Buffers[*countRegisters] != NULL_PTR)
5204 {
5205 /* correctable memory error */
5206 Buffers[*countRegisters]->RegName = CMESR;
5207 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->CMESR;
5208 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5209 (*countRegisters)++;
5210 }
5211 }
5212 }
5213
5214 /*FUNCTION**********************************************************************
5215 *
5216 * Function Name : Netc_Eth_Ip_GetMemoryErrorStatisticsForENETC
5217 * Description : Internal function for reading the memory error statistics registers for ENETC
5218 *
5219 *END**************************************************************************/
5220 static inline void Netc_Eth_Ip_GetMemoryErrorStatisticsForENETC(uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5221 {
5222 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UNMESR0)))
5223 {
5224 if (Buffers[*countRegisters] != NULL_PTR)
5225 {
5226 /* Memory ID + Syndrome*/
5227 Buffers[*countRegisters]->RegName = UNMESR0;
5228 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNMESR0;
5229 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5230 (*countRegisters)++;
5231 }
5232 if (Buffers[*countRegisters] != NULL_PTR)
5233 {
5234 /* Address information (row) of last ECC event.*/
5235 Buffers[*countRegisters]->RegName = UNMESR1;
5236 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNMESR1;
5237 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5238 (*countRegisters)++;
5239 }
5240 if (Buffers[*countRegisters] != NULL_PTR)
5241 {
5242 /* This is the uncorrectable non-fatal memory error count register which tracks how many events have been detected.*/
5243 Buffers[*countRegisters]->RegName = UNMECTR;
5244 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNMECTR;
5245 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5246 (*countRegisters)++;
5247 }
5248 }
5249 }
5250
5251 /*FUNCTION**********************************************************************
5252 *
5253 * Function Name : Netc_Eth_Ip_GetIntegrityFaultStatisticsForENETC
5254 * Description : Internal function for reading the integrity error statistics registers for ENETC
5255 *
5256 *END**************************************************************************/
5257 static inline void Netc_Eth_Ip_GetIntegrityFaultStatisticsForENETC (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5258 {
5259 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UNIESR)))
5260 {
5261 if (Buffers[*countRegisters] != NULL_PTR)
5262 {
5263 Buffers[*countRegisters]->RegName = UNIESR;
5264 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNIESR;
5265 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5266 (*countRegisters)++;
5267 }
5268 if (Buffers[*countRegisters] != NULL_PTR)
5269 {
5270 Buffers[*countRegisters]->RegName = UNIECTR;
5271 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UNIECTR;
5272 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5273 (*countRegisters)++;
5274 }
5275 }
5276 }
5277
5278 /*FUNCTION**********************************************************************
5279 *
5280 * Function Name : Netc_Eth_Ip_GetMemoryErrorStatisticsForENETC
5281 * Description : Internal function for reading the fatal error statistics registers for ENETC
5282 *
5283 *END**************************************************************************/
5284 static inline void Netc_Eth_Ip_GetFatalErrorStatisticsForENETC (uint8 *countRegisters, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5285 {
5286 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UFMESR0)))
5287 {
5288 if (Buffers[*countRegisters] != NULL_PTR)
5289 {
5290 Buffers[*countRegisters]->RegName = UFMESR0;
5291 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UFMESR0;
5292 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5293 (*countRegisters)++;
5294 }
5295 if (Buffers[*countRegisters] != NULL_PTR)
5296 {
5297 Buffers[*countRegisters]->RegName = UFMESR1;
5298 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UFMESR1;
5299 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5300 (*countRegisters)++;
5301 }
5302 }
5303
5304 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(IP_NETC__ENETC0_COMMON->UFIESR)))
5305 {
5306 if (Buffers[*countRegisters] != NULL_PTR)
5307 {
5308 Buffers[*countRegisters]->RegName = UFIESR;
5309 Buffers[*countRegisters]->RegRawValueLow = IP_NETC__ENETC0_COMMON->UFIESR;
5310 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5311 (*countRegisters)++;
5312 }
5313 }
5314 }
5315
5316 /*FUNCTION**********************************************************************
5317 *
5318 * Function Name : Netc_Eth_Ip_GetMemoryErrorStatisticsForENETC
5319 * Description : Internal function for gathering error statistics information for SWITCH
5320 *
5321 *END**************************************************************************/
5322 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForENETC(const uint8 ctrlIdx, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5323 {
5324 uint8 countRegisters = 0U;
5325
5326 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerCorrectableErrEnabled)
5327 {
5328 Netc_Eth_Ip_GetCorrectableErrorStatisticsForENETC(&countRegisters, Buffers);
5329 }
5330
5331 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5332 {
5333 Netc_Eth_Ip_GetMemoryErrorStatisticsForENETC(&countRegisters, Buffers);
5334
5335 Netc_Eth_Ip_GetIntegrityFaultStatisticsForENETC(&countRegisters, Buffers);
5336
5337 Netc_Eth_Ip_GetFatalErrorStatisticsForENETC(&countRegisters, Buffers);
5338 }
5339
5340 return countRegisters;
5341 }
5342
5343 /*FUNCTION**********************************************************************
5344 *
5345 * Function Name : Netc_Eth_Ip_GetProgrammingErrorStatisticsForSI
5346 * Description : Internal function for reading the programming error statistics registers for for a SI (siIndex).
5347 *
5348 *END**************************************************************************/
5349 static inline void Netc_Eth_Ip_GetProgrammingErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5350 {
5351 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(netcSIsBase[siIndex]->SIUPESR)))
5352 {
5353 if (Buffers[*countRegisters] != NULL_PTR)
5354 {
5355 Buffers[*countRegisters]->RegName = SIUPESR;
5356 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUPESR;
5357 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5358 (*countRegisters)++;
5359 }
5360 if (Buffers[*countRegisters] != NULL_PTR)
5361 {
5362 Buffers[*countRegisters]->RegName = SIUPECTR;
5363 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUPECTR;
5364 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5365 (*countRegisters)++;
5366 }
5367 }
5368 }
5369
5370 /*FUNCTION**********************************************************************
5371 *
5372 * Function Name : Netc_Eth_Ip_GetMemoryErrorStatisticsForSI
5373 * Description : Internal function for reading the non-fatal memory error statistics registers for for a SI (siIndex).
5374 *
5375 *END**************************************************************************/
5376 static inline void Netc_Eth_Ip_GetMemoryErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5377 {
5378 /* Multi-bit ECC error. */
5379 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(netcSIsBase[siIndex]->SIUNMESR0)))
5380 {
5381 if (Buffers[*countRegisters] != NULL_PTR)
5382 {
5383 Buffers[*countRegisters]->RegName = SIUNMESR0;
5384 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUNMESR0;
5385 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5386 (*countRegisters)++;
5387 }
5388 if (Buffers[*countRegisters] != NULL_PTR)
5389 {
5390 Buffers[*countRegisters]->RegName = SIUNMESR1;
5391 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUNMESR1;
5392 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5393 (*countRegisters)++;
5394 }
5395 if (Buffers[*countRegisters] != NULL_PTR)
5396 {
5397 Buffers[*countRegisters]->RegName = SIUNMECTR;
5398 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUNMECTR;
5399 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5400 (*countRegisters)++;
5401 }
5402 }
5403 }
5404
5405 /*FUNCTION**********************************************************************
5406 *
5407 * Function Name : Netc_Eth_Ip_GetFatalMemoryErrorStatisticsForSI
5408 * Description : Internal function for reading the Fatal memory error statistics registers for for a SI (siIndex).
5409 *
5410 *END**************************************************************************/
5411 static inline void Netc_Eth_Ip_GetFatalMemoryErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5412 {
5413 /* Fatal Multi-bit ECC error. */
5414 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(netcSIsBase[siIndex]->SIUFMESR0)))
5415 {
5416 if (Buffers[*countRegisters] != NULL_PTR)
5417 {
5418 Buffers[*countRegisters]->RegName = SIUFMESR0;
5419 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFMESR0;
5420 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5421 (*countRegisters)++;
5422 }
5423 if (Buffers[*countRegisters] != NULL_PTR)
5424 {
5425 Buffers[*countRegisters]->RegName = SIUFMESR1;
5426 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFMESR1;
5427 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5428 (*countRegisters)++;
5429 }
5430 }
5431
5432 }
5433
5434 /*FUNCTION**********************************************************************
5435 *
5436 * Function Name : Netc_Eth_Ip_GetFatalIntegrityErrorStatisticsForSI
5437 * Description : Internal function for reading the Fatal integrity error statistics registers for for a SI (siIndex).
5438 *
5439 *END**************************************************************************/
5440 static inline void Netc_Eth_Ip_GetFatalIntegrityErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5441 {
5442 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *) &(netcSIsBase[siIndex]->SIUFIESR)))
5443 {
5444 if (Buffers[*countRegisters] != NULL_PTR)
5445 {
5446 Buffers[*countRegisters]->RegName = SIUFIESR;
5447 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFIESR;
5448 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5449 (*countRegisters)++;
5450 }
5451 }
5452 }
5453
5454 /*FUNCTION**********************************************************************
5455 *
5456 * Function Name : Netc_Eth_Ip_GetFatalSystemBusErrorStatisticsForSI
5457 * Description : Internal function for reading the Fatal System bus error statistics registers for for a SI (siIndex).
5458 *
5459 *END**************************************************************************/
5460 static inline void Netc_Eth_Ip_GetFatalSystemBusErrorStatisticsForSI (uint8 *countRegisters, const uint8 ctrlIdx, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5461 {
5462 uint32 sbStatus = 0U;
5463
5464 if(Netc_Eth_Ip_ClearErrorStatus((volatile uint32 *) &(netcSIsBase[siIndex]->SIUFSBESR)))
5465 {
5466 if (Buffers[*countRegisters] != NULL_PTR)
5467 {
5468 Buffers[*countRegisters]->RegName = SIUFSBESR;
5469 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SIUFSBESR;
5470 Buffers[*countRegisters]->RegRawValueHigh = 0U;
5471 (*countRegisters)++;
5472 }
5473
5474 for (uint8 idx = 0U; idx < Netc_Eth_Ip_apxState[ctrlIdx]->SIGeneralConfig[siIndex]->NumberOfTxBDR; idx++)
5475 {
5476 /*A system bus error has occurred during one or more transactions related to this transmit ring, including possibly
5477 the transmit BD writeback entry itself. To avoid the possibility of referencing unreliable
5478 BD writeback contents,
5479 See error detect register SIUNSBESR/SIUFSBESR for more information. Write 1 to clear.*/
5480 sbStatus= netcSIsBase[siIndex]->BDR_NUM[idx].TBSR;
5481
5482 if ((sbStatus & (uint32)0x00010000) != 0U)
5483 {
5484 sbStatus &= ~((uint32)0x00010000);
5485 netcSIsBase[siIndex]->BDR_NUM[idx].TBSR = sbStatus;
5486 if (Buffers[*countRegisters] != NULL_PTR)
5487 {
5488 Buffers[*countRegisters]->RegName = TBCIR;
5489 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->BDR_NUM[idx].TBCIR;
5490 /* save also the current BDR with error */
5491 Buffers[*countRegisters]->RegRawValueHigh = (uint32)idx;
5492 (*countRegisters)++;
5493 }
5494 }
5495 }
5496
5497 for (uint8 idx = 0U; idx < Netc_Eth_Ip_apxState[ctrlIdx]->SIGeneralConfig[siIndex]->NumberOfRxBDR; idx++)
5498 {
5499 sbStatus= netcSIsBase[siIndex]->BDR_NUM[idx].RBSR;
5500 if ((sbStatus & (uint32)0x00010000) != 0U)
5501 {
5502 sbStatus &= ~((uint32)0x00010000);
5503 netcSIsBase[siIndex]->BDR_NUM[idx].RBSR = sbStatus;
5504 if (Buffers[*countRegisters] != NULL_PTR)
5505 {
5506 Buffers[*countRegisters]->RegName = RBPIR;
5507 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->BDR_NUM[idx].RBPIR;
5508 /* save also the current BDR with error */
5509 Buffers[*countRegisters]->RegRawValueHigh = (uint32)idx;
5510 (*countRegisters)++;
5511 }
5512 }
5513 }
5514 }
5515 }
5516
5517 /*FUNCTION**********************************************************************
5518 *
5519 * Function Name : Netc_Eth_Ip_GetCorrectableErrorStatisticsForSI
5520 * Description : Internal function for reading the Correctable error statistics registers for for a SI (siIndex).
5521 *
5522 *END**************************************************************************/
5523 static inline void Netc_Eth_Ip_GetCorrectableErrorStatisticsForSI (uint8 *countRegisters, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5524 {
5525 if(Netc_Eth_Ip_ClearErrorStatus( (volatile uint32 *)&(netcSIsBase[siIndex]->SICMESR)))
5526 {
5527 if (Buffers[*countRegisters] != NULL_PTR)
5528 {
5529 Buffers[*countRegisters]->RegName = SICMESR;
5530 Buffers[*countRegisters]->RegRawValueLow = netcSIsBase[siIndex]->SICMESR;
5531 Buffers[*countRegisters]->RegRawValueHigh = (uint32)0U;
5532 (*countRegisters)++;
5533 }
5534 }
5535 }
5536
5537 /*FUNCTION**********************************************************************
5538 *
5539 * Function Name : Netc_Eth_Ip_GetErrorStatisticsForSI
5540 * Description : Function that reads the registers for error statistics for a SI (siIndex) and reports the statistics to upper layers.
5541 *
5542 *END**************************************************************************/
5543 static inline uint8 Netc_Eth_Ip_GetErrorStatisticsForSI(const uint8 ctrlIdx, const uint8 siIndex, Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
5544 {
5545 uint8 countRegisters = 0U;
5546
5547 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerUncorrectableErrEnabled)
5548 {
5549 Netc_Eth_Ip_GetProgrammingErrorStatisticsForSI(&countRegisters, siIndex, Buffers);
5550
5551 Netc_Eth_Ip_GetMemoryErrorStatisticsForSI(&countRegisters, siIndex, Buffers);
5552
5553 Netc_Eth_Ip_GetFatalMemoryErrorStatisticsForSI(&countRegisters, siIndex, Buffers);
5554
5555 Netc_Eth_Ip_GetFatalSystemBusErrorStatisticsForSI(&countRegisters, ctrlIdx, siIndex, Buffers);
5556
5557 Netc_Eth_Ip_GetFatalIntegrityErrorStatisticsForSI(&countRegisters, siIndex, Buffers);
5558 }
5559
5560 if (Netc_Eth_Ip_apxState[ctrlIdx]->PcieAerCorrectableErrEnabled)
5561 {
5562 Netc_Eth_Ip_GetCorrectableErrorStatisticsForSI(&countRegisters, siIndex, Buffers);
5563 }
5564
5565 return countRegisters;
5566 }
5567
5568 /*FUNCTION**********************************************************************
5569 *
5570 * Function Name : Netc_Eth_Ip_ProcessErrorStatusForInterruptForFunctions
5571 * Description : Function that checks the error status register bit, clears it and fills in the Netc_Eth_Ip_ErrorStatus structure on the
5572 * pcie Function index with the type of error.
5573 *END**************************************************************************/
5574 static inline void Netc_Eth_Ip_ProcessErrorStatusForInterruptForFunctions(const uint8 ctrlIndex, const uint8 index)
5575 {
5576 Netc_Eth_Ip_ErrorStatus[index].StatusErrors = 0u;
5577
5578 if ((netcPCIePFBase[index]->PCIE_CFC_AER_UCORR_ERR_STAT & NETC_ETH_IP_UCORR_STATUS_BIT) != (uint32)0U)
5579 {
5580 /* Interrupt enable bit check
5581 Un-masked interrupts are marked as 0*/
5582 if ((netcPCIePFBase[index]->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_UCORR_ERR_MASK_SHIFT)) == (uint32)0U)
5583 {
5584 /* Clean error status bit */
5585 netcPCIePFBase[index]->PCIE_CFC_AER_UCORR_ERR_STAT = (uint32)NETC_ETH_IP_UCORR_STATUS_BIT;
5586 /* Report error in case this feature is enabled in configuration */
5587 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5588 {
5589 /*If the reg bit is 0 - Error is Non-fatal else is Fatal*/
5590 if((netcPCIePFBase[index]->PCIE_CFC_AER_UCORR_ERR_SEV & NETC_ETH_IP_UCORR_SEV_MASK) != 0U)
5591 {
5592 Netc_Eth_Ip_ErrorStatus[index].StatusErrors = NETC_ETH_IP_FATAL_ERROR;
5593 }
5594 else
5595 {
5596 Netc_Eth_Ip_ErrorStatus[index].StatusErrors = NETC_ETH_IP_NON_FATAL_ERROR;
5597 }
5598 }
5599 }
5600 }
5601
5602 if ((netcPCIePFBase[index]->PCIE_CFC_AER_CORR_ERR_STAT & NETC_ETH_IP_CORR_STATUS_BIT) != (uint32)0U)
5603 {
5604 /* Un-masked interrupts are marked as 0*/
5605 if ((netcPCIePFBase[index]->PCIE_CFC_AER_CORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_CORR_ERR_MASK_SHIFT)) == (uint32)0U)
5606 {
5607 netcPCIePFBase[index]->PCIE_CFC_AER_CORR_ERR_STAT = NETC_ETH_IP_CORR_STATUS_BIT;
5608 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerCorrectableErrEnabled)
5609 {
5610 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5611 Netc_Eth_Ip_ErrorStatus[index].StatusErrors |= NETC_ETH_IP_CORRECTABLE_ERROR;
5612 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5613 }
5614 }
5615 }
5616 }
5617
5618 /*FUNCTION**********************************************************************
5619 *
5620 * Function Name : Netc_Eth_Ip_ProcessErrorStatusForInterruptForVSIs
5621 * Description : Function that checks the error status register bit, clears it and fills in the Netc_Eth_Ip_ErrorStatus structure on the
5622 * VSIx index with the type of error.
5623 *END**************************************************************************/
5624 static inline void Netc_Eth_Ip_ProcessErrorStatusForInterruptForVSIs(const uint8 ctrlIndex, const uint8 index)
5625 {
5626 /* Index used to address the netcVFBase array that contains base addresses for all VFs. NULL_PTR is added on position 0 as the hardware has only 7 VF starting from 1 */
5627 uint8 relativeIndex = 0U;
5628
5629 Netc_Eth_Ip_ErrorStatus[index].StatusErrors = 0u;
5630
5631 /* netcVFBase has the index 0 null since virtual station interfaces start from 1
5632 relativeIndex = Function array index - relative number in the list of functions (TIMER EMDIO SWITCH PSI VF1 ...VF8) + 1 (VFs start from 1)*/
5633 relativeIndex = index - FEATURE_NETC_NUMBER_OF_FUNC + 1u;
5634
5635 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_STAT & NETC_ETH_IP_UCORR_STATUS_BIT) != (uint32)0U)
5636 {
5637 /* Un-masked interrupts are marked as 0*/
5638 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_UCORR_ERR_MASK_SHIFT)) == (uint32)0U)
5639 {
5640
5641 netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_STAT = NETC_ETH_IP_UCORR_STATUS_BIT;
5642 /*If the reg bit is 0 - Error is Non-fatal else is Fatal*/
5643 if((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_SEV & NETC_ETH_IP_UCORR_SEV_MASK) != 0U)
5644 {
5645 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5646 {
5647 Netc_Eth_Ip_ErrorStatus[index].StatusErrors = NETC_ETH_IP_FATAL_ERROR;
5648 }
5649 }
5650 else
5651 {
5652 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5653 {
5654 Netc_Eth_Ip_ErrorStatus[index].StatusErrors |= NETC_ETH_IP_NON_FATAL_ERROR;
5655 }
5656 }
5657 }
5658 }
5659 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_CORR_ERR_STAT & NETC_ETH_IP_CORR_STATUS_BIT) != (uint32)0U)
5660 {
5661 /* Un-masked interrupts are marked as 0*/
5662 if ((netcVFBase[relativeIndex]->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_CORR_ERR_MASK_SHIFT)) != (uint32)0U)
5663 {
5664 netcVFBase[relativeIndex]->PCIE_CFC_AER_CORR_ERR_STAT = NETC_ETH_IP_CORR_STATUS_BIT;
5665 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerCorrectableErrEnabled)
5666 {
5667 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5668 Netc_Eth_Ip_ErrorStatus[index].StatusErrors |= NETC_ETH_IP_CORRECTABLE_ERROR;
5669 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5670 }
5671 }
5672 }
5673 }
5674
5675 /*FUNCTION**********************************************************************
5676 *
5677 * Function Name : Netc_Eth_Ip_ProcessErrorStatusForInterruptForVSIs
5678 * Description : Function that checks the error status register bit, clears it and fills in the Netc_Eth_Ip_ErrorStatus structure on the
5679 * PSI0 index with the type of error.
5680 *END**************************************************************************/
5681 static inline void Netc_Eth_Ip_ProcessErrorStatusForInterruptForPSI0(const uint8 ctrlIndex)
5682 {
5683 /* Uncorrectable Error reporting for PSI0 */
5684 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_STAT & NETC_ETH_IP_UCORR_STATUS_BIT) != (uint32)0U)
5685 {
5686 /* Un-masked interrupts are marked as 0*/
5687 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_UCORR_ERR_MASK_SHIFT)) == (uint32)0U)
5688 {
5689 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_STAT = NETC_ETH_IP_UCORR_STATUS_BIT;
5690 /*If the reg bit is 0 - Error is Non-fatal else is Fatal*/
5691 if((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_SEV & NETC_ETH_IP_UCORR_SEV_MASK) != 0U)
5692 {
5693 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5694 {
5695 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors = NETC_ETH_IP_FATAL_ERROR;
5696 }
5697 }
5698 else
5699 {
5700 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerUncorrectableErrEnabled)
5701 {
5702 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors = NETC_ETH_IP_NON_FATAL_ERROR;
5703 }
5704 }
5705 }
5706 }
5707 /* Correctable Error reporting for PSI0 */
5708 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_STAT & NETC_ETH_IP_CORR_STATUS_BIT) != (uint32)0U)
5709 {
5710 /* Un-masked interrupts are marked as 0*/
5711 if ((IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_MASK & ((uint32)1U << NETC_ETH_IP_CORR_ERR_MASK_SHIFT)) == (uint32)0U)
5712 {
5713 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_STAT = NETC_ETH_IP_CORR_STATUS_BIT;
5714 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerCorrectableErrEnabled)
5715 {
5716 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5717 Netc_Eth_Ip_ErrorStatus[NETC_ETH_IP_PSI0_FUNCTION_INDEX].StatusErrors |= NETC_ETH_IP_CORRECTABLE_ERROR;
5718 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27();
5719 }
5720 }
5721 }
5722 }
5723
5724
5725 static inline void Netc_Eth_Ip_Init_FirstPart(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
5726 {
5727 /* Configure VLAN to IPV - Station interface VLAN to IPV mapping register 0/1 (SIVLANIPVMR0/1) and Station interface VLAN to IPV mapping register 1 (SIVLANIPVMR1) */
5728 Netc_Eth_Ip_Init_VlanToIpvMapping(ctrlIndex, config);
5729
5730 /* Configure IPV to BDR - Station interface IPV to ring mapping register (SIIPVBDRMR0) */
5731 Netc_Eth_Ip_Init_IpvToBdrMapping(ctrlIndex, config);
5732
5733 /* Initialize State structure */
5734 Netc_Eth_Ip_InitStateStructure(ctrlIndex, config);
5735
5736 /* Configure Command ring */
5737 Netc_Eth_Ip_InitCBDR(ctrlIndex);
5738 }
5739
5740 static inline void Netc_Eth_Ip_Init_SecondPart(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
5741 {
5742 Netc_Eth_Ip_InitNTMPTables(ctrlIndex, config);
5743 /* Initialize TX BDRs */
5744 Netc_Eth_Ip_InitTxBD(ctrlIndex, config);
5745 /* Initialize RX BDRs */
5746 Netc_Eth_Ip_InitRxBD(ctrlIndex, config);
5747
5748 }
5749
5750 /*==================================================================================================
5751 * GLOBAL FUNCTIONS
5752 ==================================================================================================*/
5753
5754 /*FUNCTION**********************************************************************
5755 *
5756 * Function Name : Netc_Eth_Ip_Init
5757 * implements Netc_Eth_Ip_Init_Activity
5758 *END**************************************************************************/
5759 Netc_Eth_Ip_StatusType Netc_Eth_Ip_Init(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
5760 {
5761 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
5762
5763 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5764 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
5765 DevAssert(config != NULL_PTR);
5766 #endif
5767
5768 /* Configure SI */
5769 Status = Netc_Eth_Ip_InitSI(ctrlIndex, config);
5770
5771 /* Added to be sure this is not executed when VSI get a timeout. */
5772 if(NETC_ETH_IP_STATUS_SUCCESS == Status)
5773 {
5774 Netc_Eth_Ip_Init_FirstPart(ctrlIndex, config);
5775
5776 /* only for PSI0 */
5777 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType)
5778 {
5779 /* pseudo port speed configuration*/
5780 IP_NETC__ENETC0_PORT->PCR &= ~ENETC_PORT_PCR_PSPEED_MASK;
5781 IP_NETC__ENETC0_PORT->PCR |= ENETC_PORT_PCR_PSPEED(NETC_ETH_IP_SHAPING_PSPEED_2000MBITS);
5782 /* clock frequency from configuration, used for credit based shapers*/
5783 Netc_Eth_Ip_NetcClockFrequency = config->netcClockFrequency;
5784 /* Configure Credit Based Shaper registers */
5785 Netc_Eth_Ip_ConfigCreditBasedShaperReg(ctrlIndex, config);
5786 #if (NETC_ETH_MAX_NUMBER_OF_IPFTABLE_LIST > 0U)
5787 /* Initialize IPF table */
5788 Status = Netc_Eth_Ip_InitIngressPortFilterTable(ctrlIndex, config);
5789 #endif
5790 }
5791 Netc_Eth_Ip_Init_SecondPart(ctrlIndex, config);
5792 /* Check if any interrupt is enabled and configure the hardware */
5793 if ((TRUE == (*config->siConfig).EnableSIMsgInterrupt) ||
5794 ((*config->siConfig).TxInterrupts != 0U) ||
5795 ((*config->siConfig).RxInterrupts != 0U))
5796 {
5797 /* Enable interrupts for the current controller. */
5798 Netc_Eth_Ip_EnableIrq(ctrlIndex, config);
5799 }
5800
5801 Netc_Eth_Ip_ConfigPtr[ctrlIndex] = config;
5802
5803 }
5804 return Status;
5805 }
5806
5807 /*FUNCTION**********************************************************************
5808 *
5809 * Function Name : Netc_Eth_Ip_StartTSN
5810 * Description : function for starting the Time Sensitive Networking functionality
5811 * implements Netc_Eth_Ip_StartTSN_Activity
5812 *END**************************************************************************/
5813 Std_ReturnType Netc_Eth_Ip_StartTSN(uint8 ctrlIndex)
5814 {
5815 Std_ReturnType status = E_OK;
5816
5817 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5818 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
5819 DevAssert(Netc_Eth_Ip_ConfigPtr[ctrlIndex] != NULL_PTR);
5820 #endif
5821
5822 #if (NETC_ETH_IP_NUMBER_OF_RP_ENTRIES > 0U)
5823 status |= Netc_Eth_Ip_ConfigRatePolicerTable(ctrlIndex,Netc_Eth_Ip_ConfigPtr[ctrlIndex]);
5824 #endif
5825 #if (NETC_ETH_NUMBER_OF_STREAMIDENTIFICATION_ENTRIES > 0U)
5826 status |= Netc_Eth_Ip_ConfigISITable(ctrlIndex,Netc_Eth_Ip_ConfigPtr[ctrlIndex]);
5827 #endif
5828 #if (NETC_ETH_NUMBER_OF_INGRESSSTREAM_ENTRIES > 0U)
5829 status |= Netc_Eth_Ip_ConfigIngressStreamTable(ctrlIndex,Netc_Eth_Ip_ConfigPtr[ctrlIndex]);
5830 #endif
5831 #if (NETC_ETH_NUMBER_OF_SGCL_ENTRIES > 0U)
5832 status |= Netc_Eth_Ip_ConfigSGCL(ctrlIndex,Netc_Eth_Ip_ConfigPtr[ctrlIndex]);
5833 #endif
5834 #if (NETC_ETH_NUMBER_OF_SGI_ENTRIES > 0U)
5835 status |= Netc_Eth_Ip_ConfigSGI(ctrlIndex,Netc_Eth_Ip_ConfigPtr[ctrlIndex]);
5836 #endif
5837
5838 (void)ctrlIndex;
5839 (void)Netc_Eth_Ip_ConfigPtr;
5840
5841 return status;
5842 }
5843
5844 /*FUNCTION**********************************************************************
5845 *
5846 * Function Name : Netc_Eth_Ip_ConfigureCreditBasedShaper
5847 * Description : function for configuring the CBS
5848 * implements Netc_Eth_Ip_ConfigureCreditBasedShaper_Activity
5849 *END**************************************************************************/
5850 Std_ReturnType Netc_Eth_Ip_ConfigureCreditBasedShaper(const uint8 ctrlIndex, const uint8 TrafficClass, const uint64 idleSlope)
5851 {
5852 Std_ReturnType status = E_OK;
5853 uint64 portTxRate;
5854 uint64 largeBandwidth;
5855 uint32 bandwidth;
5856 uint64 largeEgressHiCredit;
5857 uint32 egressHiCredit;
5858 uint32 Netc_Eth_Ip_MaxFrameSize;
5859
5860 #if(STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5861 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
5862 /* A Slope of zero would cause a bandwidth of zero and this would cause a buffer leak */
5863 DevAssert(idleSlope > 0U);
5864 DevAssert(TrafficClass < NETC_ETH_IP_NUMBER_OF_PRIORITIES);
5865 #endif
5866
5867 (void)ctrlIndex;
5868
5869 /*This is a pseudo-port. */
5870 portTxRate = 2000000000UL;
5871
5872 largeBandwidth = idleSlope / (portTxRate / 10000UL); /* bandwidth is in % and 100th precision, so need to divide by 10000 */
5873 if( largeBandwidth < 100UL )
5874 {
5875 largeBandwidth = 100UL; /* Min of 1% bandwidth, otherwise frames would get stuck in the switch */
5876 }
5877 /* Round and convert to uint32 */
5878 bandwidth = (uint32)(largeBandwidth/100UL);
5879 bandwidth = ((uint64)((((uint64)bandwidth)*100UL)+50UL)>largeBandwidth)?bandwidth:(bandwidth+1UL);
5880
5881 /* High Credit in credits
5882 hiCredit (bits) = maxSizedFrame * (idleSlope / portTxRate)
5883 bandwidth = idleSlope / portTxRate
5884 Then:
5885 hiCredit (bits) = maxSizedFrame * bandwidth
5886
5887 hiCredit (credits) = hiCredit (bits) * (ClockFrequency / portTxRate)
5888 Then:
5889 hiCredit (credits) = maxSizedFrame * bandwidth * (ClockFrequency / portTxRate)
5890 */
5891 Netc_Eth_Ip_MaxFrameSize = IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCTMSDUR;
5892 largeEgressHiCredit = largeBandwidth * Netc_Eth_Ip_MaxFrameSize * (Netc_Eth_Ip_NetcClockFrequency / (portTxRate)) / 100UL; /* Bandwidth is in %, need to div by 100 */
5893 /* Round and convert to uint32 */
5894 egressHiCredit = (uint32)(largeEgressHiCredit/100UL);
5895 egressHiCredit = (((egressHiCredit*100UL)+50UL)>egressHiCredit)?egressHiCredit:(egressHiCredit+1UL);
5896 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07();
5897 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 &= ~ENETC_PORT_PTCCBSR0_BW_MASK;
5898 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 |= ENETC_PORT_PTCCBSR0_BW(bandwidth);
5899 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07();
5900 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR1 = ENETC_PORT_PTCCBSR1_HI_CREDIT(egressHiCredit);
5901
5902 return status;
5903 }
5904
5905 /*FUNCTION**********************************************************************
5906 *
5907 * Function Name : Netc_Eth_Ip_EnableCreditBasedShaper
5908 * Description : function for enabling a CBS
5909 * implements Netc_Eth_Ip_EnableCreditBasedShaper_Activity
5910 *END**************************************************************************/
5911 Std_ReturnType Netc_Eth_Ip_EnableCreditBasedShaper(const uint8 ctrlIndex, const uint8 TrafficClass, const boolean Enable)
5912 {
5913 Std_ReturnType status = E_OK;
5914
5915 #if(STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5916 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
5917 DevAssert(TrafficClass < NETC_ETH_IP_NUMBER_OF_PRIORITIES);
5918 #endif
5919 (void)ctrlIndex;
5920 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08();
5921 /* clear the bit first */
5922 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 &= ~ENETC_PORT_PTCCBSR0_CBSE_MASK;
5923 /* write the bit */
5924 IP_NETC__ENETC0_PORT->TCT_NUM[TrafficClass].PTCCBSR0 |= ENETC_PORT_PTCCBSR0_CBSE((TRUE==Enable)?1U:0U);
5925 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08();
5926
5927 return status;
5928 }
5929
5930 /*FUNCTION**********************************************************************
5931 *
5932 * Function Name : Netc_Eth_Ip_EnableController
5933 * implements Netc_Eth_Ip_EnableController_Activity
5934 *END**************************************************************************/
5935 Netc_Eth_Ip_StatusType Netc_Eth_Ip_EnableController(uint8 ctrlIndex)
5936 {
5937
5938 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5939 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
5940 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
5941 #endif
5942 if (Netc_Eth_Ip_apxState[ctrlIndex]->RxInterrupts != 0U)
5943 {
5944 Netc_Eth_Ip_EnableController_RxCoalescing(ctrlIndex);
5945 }
5946 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
5947 if (Netc_Eth_Ip_apxState[ctrlIndex]->TxInterrupts != 0U)
5948 {
5949 Netc_Eth_Ip_EnableController_TxCoalescing(ctrlIndex);
5950 }
5951
5952
5953 /* Set the EN bit in Station interface mode register (SIMR) */
5954 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
5955 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
5956
5957 return NETC_ETH_IP_STATUS_SUCCESS;
5958 }
5959
5960 /*FUNCTION**********************************************************************
5961 *
5962 * Function Name : Netc_Eth_Ip_DisableController
5963 * implements Netc_Eth_Ip_DisableController_Activity
5964 *END**************************************************************************/
5965 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DisableController(uint8 ctrlIndex)
5966 {
5967 uint32 ringCounter = 0U;
5968 uint32 currBDIdx = 0U;
5969 Netc_Eth_Ip_TxBDRType *txTmpBDR;
5970 Netc_Eth_Ip_RxBDRType *rxTmpBDR;
5971 boolean isPendingRing = FALSE;
5972 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
5973
5974 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
5975 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
5976 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
5977 #endif
5978 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02();
5979
5980 /* Check whether any transmit pending ring haven been consumed before disable the SI */
5981 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR; ringCounter++)
5982 {
5983 if (netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBPIR != netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBCIR)
5984 {
5985 isPendingRing = TRUE;
5986 break;
5987 }
5988 }
5989
5990 if (isPendingRing == FALSE)
5991 {
5992 /* Clear the EN bit in Station interface mode register (SIMR) */
5993 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
5994
5995 /* Restore all information related with the TX operations. */
5996 /* Loop through all the configured transmission rings */
5997 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR; ringCounter++)
5998 {
5999 /* Write the interrupt settings as configured */
6000 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER &= ~NETC_F3_SI0_TBIER_TXTIE_MASK;
6001 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICEN_MASK;
6002 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER &= ~NETC_F3_SI0_TBIER_TXFIE_MASK;
6003 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR1 = 0U; /* &= ~NETC_F3_SI0_TBICR1_ICTT_MASK; */
6004 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICPT_MASK;
6005 /* Reset producer and consumer indexes. */
6006 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBPIR = 0U;
6007 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBCIR = 0U;
6008 txTmpBDR = Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ringCounter];
6009 /* Loop through all descriptors of the ring. */
6010 for (currBDIdx = 0U; currBDIdx < Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ringCounter]; currBDIdx++)
6011 {
6012 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6013 /* Write in the buffer descriptor the extended bit */
6014 txTmpBDR->buffConfig |= NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;
6015 txTmpBDR->extendBuffConfig |= (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));
6016 #else
6017 /* For the last descriptor write the final flag */
6018 txTmpBDR->buffConfig |= (NETC_ETH_IP_TXBD_FINAL_MASK & (~NETC_ETH_IP_TXBD_WRITEBACK_MASK));
6019 #endif
6020 txTmpBDR++;
6021
6022 /* Reset TX state variable realted to each descriptor. */
6023 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ringCounter][currBDIdx] = FALSE;
6024 }
6025 /* Reset TX state variable realted to each ring. */
6026 Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ringCounter] = 0U;
6027 Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ringCounter] = 0U;
6028 Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ringCounter] = 0U;
6029 }
6030
6031 /* Restore all information related with the RX operations. */
6032 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR; ringCounter++)
6033 {
6034 /* Write the interrupt settings as configured */
6035 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBIER &= ~NETC_F3_SI0_RBIER_RXTIE_MASK;
6036 /* Write the producer and consumer indexes with 0 */
6037 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBPIR = 0U;
6038 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBCIR = 0U;
6039 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICEN_MASK;
6040 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR1 = 0U; /* &= ~NETC_F3_SI0_RBICR1_ICTT_MASK; Changed due to CWE violation*/
6041 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICPT_MASK;
6042 rxTmpBDR = Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ringCounter];
6043 /* Loop through all descriptors of the queue */
6044 for (currBDIdx = 0U; currBDIdx < Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ringCounter]; currBDIdx++)
6045 {
6046 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
6047 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
6048 {
6049 #endif
6050 rxTmpBDR->configRxBD[0U] = (uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxDataBufferAddr[ringCounter]) + \
6051 (uint32)(currBDIdx * Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ringCounter]);
6052 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
6053 }
6054 #endif
6055 rxTmpBDR->configRxBD[1U] = 0U;
6056 rxTmpBDR->configRxBD[2U] = 0U;
6057 rxTmpBDR->configRxBD[3U] = 0U;
6058 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6059 rxTmpBDR->extendConfigRxBD[0U] = 0U;
6060 rxTmpBDR->extendConfigRxBD[1U] = 0U;
6061 rxTmpBDR->extendConfigRxBD[2U] = 0U;
6062 rxTmpBDR->extendConfigRxBD[3U] = 0U;
6063 #endif
6064 rxTmpBDR++;
6065 }
6066
6067 /* Reset RX state variable realted to each ring. */
6068 Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ringCounter] = Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ringCounter];
6069 Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ringCounter] = 0U;
6070 }
6071
6072 Status = NETC_ETH_IP_STATUS_SUCCESS;
6073 }
6074 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02();
6075
6076 return Status;
6077 }
6078
6079 /*FUNCTION**********************************************************************
6080 *
6081 * Function Name : Netc_Eth_Ip_GetTxBuff
6082 * implements Netc_Eth_Ip_GetTxBuff_Activity
6083 *END**************************************************************************/
6084 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxBuff(uint8 ctrlIndex,
6085 uint8 ring,
6086 Netc_Eth_Ip_BufferType *buff,
6087 uint16 *buffId)
6088 {
6089 uint32 nextProducerIdx;
6090 uint32 currProducerIdx;
6091 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
6092
6093 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6094 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6095 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
6096 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
6097 DevAssert(buff != NULL_PTR);
6098 #endif
6099
6100 currProducerIdx = Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring];
6101
6102 /* Get the next producer index and the overflow status for producer counter. */
6103 nextProducerIdx = currProducerIdx + NETC_ETH_IP_PRODUCER_INCR;
6104 if (nextProducerIdx >= (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring])
6105 {
6106 nextProducerIdx = 0U;
6107 }
6108
6109 /* Test frame length */
6110 if (buff->length < NETC_ETH_IP_MIN_FRAME_LENGTH)
6111 {
6112 status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
6113 }
6114 /* ATTENTION! This mechanism is implemented to be sure that producer index will NOT be equal with the consumer index. */
6115 else if(nextProducerIdx == Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
6116 {
6117 status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
6118 }
6119 else
6120 {
6121 if (buff->length > Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring])
6122 {
6123 status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
6124 buff->length = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]);
6125 }
6126 else
6127 {
6128 #if (NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
6129 if (!Netc_Eth_Ip_ControllerHasExternalTxBufferManagement[ctrlIndex])
6130 {
6131 #endif
6132 buff->data = (uint8*) ((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxDataBufferAddr[ring] + \
6133 (currProducerIdx * Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffMaxLenAddr[ring]));
6134 #if (NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
6135 }
6136 #endif
6137 /* If used, return the buffer index */
6138 if (buffId != NULL_PTR)
6139 {
6140 *buffId = (uint16)(currProducerIdx);
6141 }
6142
6143 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
6144 exection before the previous else if condition is completed. */
6145 MCAL_INSTRUCTION_SYNC_BARRIER();
6146 MCAL_DATA_SYNC_BARRIER();
6147 /* Marked the data buff as used. */
6148 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][currProducerIdx] = TRUE;
6149 }
6150 }
6151
6152 return status;
6153 }
6154
6155 /*FUNCTION**********************************************************************
6156 *
6157 * Function Name : Netc_Eth_Ip_GetTxMultiBuff
6158 * implements Netc_Eth_Ip_GetTxMultiBuff_Activity
6159 *END**************************************************************************/
6160 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxMultiBuff(uint8 ctrlIndex,
6161 uint8 ring,
6162 uint16 NumBuffers,
6163 const uint16 BufferLength[],
6164 uint16 *buffId)
6165 {
6166 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
6167 uint32 ProducerIndex;
6168 uint32 NextProducerIndex;
6169 uint16 FreeBuffers = 0U;
6170
6171 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6172 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6173 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
6174 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
6175 #endif
6176
6177 ProducerIndex = (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring];
6178 NextProducerIndex = ProducerIndex;
6179
6180 /*Check if the first buffer has length of at least 16 bytes. The hardware limits the first buffer to be of at least 16bytes.*/
6181 if (BufferLength[NETC_ETH_IP_FIRST_BUFFER_IDX] < NETC_ETH_IP_MIN_FRAME_LENGTH)
6182 {
6183 Status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
6184 }
6185 else
6186 {
6187 while ((FreeBuffers < NumBuffers) && (NETC_ETH_IP_STATUS_SUCCESS == Status))
6188 {
6189 NextProducerIndex = (NextProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
6190 /* If the buffer descriptor is free */
6191 if (NextProducerIndex != Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
6192 {
6193 if (BufferLength[FreeBuffers] <= (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]))
6194 {
6195 FreeBuffers++;
6196 }
6197 else
6198 {
6199 Status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
6200 }
6201 }
6202 else
6203 {
6204 Status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
6205 }
6206 }
6207 }
6208
6209 if (FreeBuffers == NumBuffers)
6210 {
6211 *buffId = (uint16)(ProducerIndex);
6212 }
6213
6214 return Status;
6215 }
6216
6217 /*FUNCTION**********************************************************************
6218 *
6219 * Function Name : Netc_Eth_Ip_SendMultiBufferFrame
6220 * implements Netc_Eth_Ip_SendMultiBufferFrame_Activity
6221 *END**************************************************************************/
6222 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendMultiBufferFrame(uint8 ctrlIndex,
6223 uint8 ring,
6224 Netc_Eth_Ip_BufferType Buffers[],
6225 const Netc_Eth_Ip_TxOptionsType *options,
6226 uint16 NumBuffers)
6227 {
6228 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
6229 Netc_Eth_Ip_TxBDRType *txBD;
6230 uint16 FreeBuffers = 0U;
6231 uint16 BufferIndex = 0U;
6232 uint16 FrameLength = 0U;
6233 /* Read the producer index */
6234 uint32 ProducerIndex = (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring]; /* Increment the producer index; making sure it wraps around according to the length of the ring */
6235 uint32 NextProducerIndex = ProducerIndex;
6236 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
6237 Std_ReturnType CacheStatus = E_NOT_OK;
6238 #endif
6239
6240 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6241 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6242 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
6243 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
6244 #endif
6245
6246 /*Check if the first buffer does not exceed 16 bytes. The hardware limits the first buffer to 16bytes.*/
6247 if (Buffers[NETC_ETH_IP_FIRST_BUFFER_IDX].length < NETC_ETH_IP_MIN_FRAME_LENGTH)
6248 {
6249 Status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
6250 }
6251 else
6252 {
6253 while ((FreeBuffers < NumBuffers) && (NETC_ETH_IP_STATUS_SUCCESS == Status))
6254 {
6255 NextProducerIndex = (NextProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
6256 /* If the buffer descriptor is free */
6257 if (NextProducerIndex != Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
6258 {
6259 /* If the Length doesn't exceed the size of the descriptor, move to next buffer */
6260 if (Buffers[FreeBuffers].length <= (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]))
6261 {
6262 FreeBuffers++;
6263 }
6264 else
6265 {
6266 Status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
6267 }
6268 /* Calculate the size of the whole frame */
6269 FrameLength += Buffers[BufferIndex].length;
6270 }
6271 else
6272 {
6273 Status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
6274 }
6275 }
6276 }
6277
6278 if (FreeBuffers == NumBuffers)
6279 {
6280 while (BufferIndex < NumBuffers)
6281 {
6282 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][ProducerIndex] = TRUE;
6283 /* Save the address of the external buffer to be used in GetTransmitStatus for correctly identifying the descriptor. */
6284 Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffAddr[ring][ProducerIndex] = Buffers[BufferIndex].data;
6285
6286 txBD = (Netc_Eth_Ip_TxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ring]) + (((uint32)(ProducerIndex / NETC_ETH_IP_PRODUCER_INCR)) * ((uint32)(sizeof(Netc_Eth_Ip_TxBDRType)))));
6287 /* Write buffer and frame length in the buffer descriptor. */
6288 txBD->length = (((uint32)FrameLength << 16U) | Buffers[BufferIndex].length);
6289 /* Write buffer address in the descriptor. */
6290 txBD->dataBuffAddr = (uint32)Buffers[BufferIndex].data;
6291 /* Clear the high part of buffer address(used for 64 bit address). */
6292 txBD->RESERVED_0 = (uint32)0U;
6293 ProducerIndex = (ProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
6294
6295 /* Update buffer descriptor for transmission */
6296 if (BufferIndex != (NumBuffers - 1U))
6297 {
6298 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6299 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;
6300 txBD->extendBuffConfig = 0U;
6301 #else
6302 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK;
6303 #endif
6304 }
6305 else
6306 {
6307 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6308 /* Write in the buffer descriptor the extended bit */
6309 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK;
6310 txBD->extendBuffConfig = NETC_ETH_IP_TXBD_FINAL_MASK;
6311 #else
6312 /* Write the final flag and clear writeback field. */
6313 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_FINAL_MASK;
6314 #endif
6315 }
6316 Netc_Eth_Ip_ConfigureBufferDescriptors(BufferIndex, options, txBD);
6317 BufferIndex++;
6318 }
6319 /* Writes in memory for BD are optimized and syncronization before starting transmission need to be done
6320 to assure that transmission BD is write correctly in memory. */
6321 MCAL_DATA_SYNC_BARRIER();
6322
6323 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
6324 /* Before sending, Flush + Invalidate cache in order write back the contents to main memory and mark the cache lines as invalid so that
6325 the future reads will be done from the memory. */
6326 CacheStatus = Cache_Ip_Clean(CacheType, CACHE_IP_DATA, TRUE);
6327 if (E_NOT_OK == CacheStatus)
6328 {
6329 Status = NETC_ETH_IP_STATUS_CACHE_ERROR;
6330 }
6331 else
6332 {
6333 #endif
6334 /* Update the current value of the producer index. */
6335 Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring] = (uint16)ProducerIndex;
6336 /* Write the producer index into register to start frame sending. */
6337 netcSIsBase[ctrlIndex]->BDR_NUM[ring].TBPIR = ProducerIndex;
6338
6339 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
6340 }
6341 #endif
6342 }
6343 return Status;
6344 }
6345
6346 /*FUNCTION**********************************************************************
6347 *
6348 * Function Name : Netc_Eth_Ip_SendFrame
6349 * implements Netc_Eth_Ip_SendFrame_Activity
6350 *END**************************************************************************/
6351 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendFrame(uint8 ctrlIndex,
6352 uint8 ring,
6353 Netc_Eth_Ip_BufferType *buff,
6354 const Netc_Eth_Ip_TxOptionsType *options)
6355 {
6356 Netc_Eth_Ip_TxBDRType *txBD;
6357 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
6358 uint32 ProducerIndex;
6359 uint32 NextProducerIndex;
6360 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
6361 Std_ReturnType CacheStatus = E_NOT_OK;
6362 #endif
6363
6364 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6365 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6366 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
6367 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
6368 DevAssert(buff != NULL_PTR);
6369 #endif
6370
6371 /* Read the producer index */
6372 ProducerIndex = (uint32)Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring];
6373 /* Increment the producer index; making sure it wraps around according to the length of the ring */
6374 NextProducerIndex = (ProducerIndex + NETC_ETH_IP_PRODUCER_INCR) % Netc_Eth_Ip_apxState[ctrlIndex]->TxRingSize[ring];
6375
6376 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS)
6377 /* Test frame length */
6378 if (buff->length < NETC_ETH_IP_MIN_FRAME_LENGTH)
6379 {
6380 Status = NETC_ETH_IP_STATUS_INVALID_FRAME_LENGTH;
6381 }
6382 else if (buff->length > Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring])
6383 {
6384 Status = NETC_ETH_IP_STATUS_TX_BUFF_OVERFLOW;
6385 buff->length = Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring];
6386 }
6387 else
6388 {
6389 /* ATTENTION! This mechanism is implemented to be sure that producer index will NOT be equal with the consumer index,
6390 because in the equality case the transmition will be stopped. */
6391 if(NextProducerIndex != Netc_Eth_Ip_apxState[ctrlIndex]->lastTxDataBuffAddrIdx[ring])
6392 {
6393 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
6394 exection before the previous else if condition is completed. */
6395 MCAL_INSTRUCTION_SYNC_BARRIER();
6396 MCAL_DATA_SYNC_BARRIER();
6397 Netc_Eth_Ip_apxState[ctrlIndex]->LockTxBuffDescr[ring][ProducerIndex] = TRUE;
6398 #else
6399 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
6400 exection before the previous else if condition is completed. */
6401 MCAL_INSTRUCTION_SYNC_BARRIER();
6402 MCAL_DATA_SYNC_BARRIER();
6403 #endif /* NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS */
6404 /* Save the address of the external buffer to be used in GetTransmitStatus for correctly identifying the descriptor. */
6405 Netc_Eth_Ip_apxState[ctrlIndex]->TxDataBuffAddr[ring][ProducerIndex] = buff->data;
6406
6407 txBD = (Netc_Eth_Ip_TxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstTxRingDescAddr[ring]) + (uint32)((ProducerIndex / NETC_ETH_IP_PRODUCER_INCR) * ((uint32)(sizeof(Netc_Eth_Ip_TxBDRType)))));
6408 /* Write buffer and frame length in the buffer descriptor. */
6409 txBD->length = (((uint32)buff->length << 16U) | buff->length);
6410 /* Write buffer address in the descriptor. */
6411 txBD->dataBuffAddr = (uint32)buff->data;
6412 /* Clear the high part of buffer address(used for 64 bit address). */
6413 txBD->RESERVED_0 = (uint32)0U;
6414
6415 /* Check if there was a writeback in the descriptor */
6416 if (NETC_ETH_IP_TXBD_WRITEBACK_MASK == (txBD->buffConfig & NETC_ETH_IP_TXBD_WRITEBACK_MASK))
6417 {
6418 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6419 /* Write in the buffer descriptor the extended bit */
6420 txBD->buffConfig = (NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_EXTENDED_BUFFER_MASK);
6421 txBD->extendBuffConfig = NETC_ETH_IP_TXBD_FINAL_MASK;
6422 #else
6423 /* Write the final flag and clear writeback field. */
6424 txBD->buffConfig = NETC_ETH_IP_TXBD_FRAME_INTERRUPT_MASK | NETC_ETH_IP_TXBD_FINAL_MASK;
6425 #endif
6426 }
6427
6428 if(options != NULL_PTR)
6429 {
6430 if ((NETC_ETH_IP_SWT_MANAGEMNT == options->Flag) && (ctrlIndex == 0U) && (ring == 0U)) /* Management frame */
6431 {
6432 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6433 #ifdef NETC_ETH_0_USED
6434 /* Resetting the management frame flag here is OK as long as there is no chance of re-using the position in the array
6435 before the message it points to is processed. This is indeed ensured by the ProvideTxBuffer function which needs to
6436 successfully provide a buffer if the SetManagementInfo function, which sets the flag, is to be called. */
6437 if (Netc_Eth_Ip_TxManagementInfoBuff[0U][ProducerIndex / NETC_ETH_IP_PRODUCER_INCR].State == NETC_ETH_IP_TX_MGMT_PREPARED)
6438 {
6439 Netc_Eth_Ip_TxManagementInfoBuff[0U][ProducerIndex / NETC_ETH_IP_PRODUCER_INCR].State = NETC_ETH_IP_TX_MGMT_QUEUED;
6440 }
6441 else
6442 {
6443 Netc_Eth_Ip_TxManagementInfoBuff[0U][ProducerIndex / NETC_ETH_IP_PRODUCER_INCR].State = NETC_ETH_IP_TX_MGMT_QUEUED_TIMESTAMP;
6444 }
6445 #endif
6446 #endif
6447 /* Set Flag(FL) type; set ingress or egress port value; set value of flag qualifier(FLQ). */
6448 txBD->buffConfig |= ((((uint32)NETC_ETH_IP_FLQ_VALUE) << NETC_ETH_IP_FLQ_SHIFT) | \
6449 ((uint32)options->IngrOrEgrPortNumber << NETC_ETH_IP_INGR_EGRESS_PORT_SHIFT));
6450 if(1U == options->SwtMgSendingOpt)
6451 {
6452 txBD->buffConfig |= ((uint32)options->SwtMgSendingOpt << NETC_ETH_IP_SMSO_SHIFT) | \
6453 ((uint32)options->TimestampRefReq << NETC_ETH_IP_TSR_SHIFT) | \
6454 ((uint32)options->InternalPriority << NETC_ETH_IP_IPV_SHIFT) | \
6455 ((uint32)options->DiscardResilience << NETC_ETH_IP_DR_SHIFT);
6456 }
6457 }
6458 else if (NETC_ETH_IP_TXSTART == options->Flag) /* Frame with preset time to be sent at */
6459 {
6460 txBD->buffConfig |= ((((uint32)NETC_ETH_IP_TXSTART) << NETC_ETH_IP_FL_SHIFT) |
6461 (((uint32)options->TxStartEnable) << NETC_ETH_IP_TSR_SHIFT) |
6462 (options->TxStartTime));
6463 }
6464 else /* Regular frame */
6465 {
6466 /*MISRA C-2012 Rule 15.7*/
6467 }
6468 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
6469 txBD->timestamp = options->Timestamp;
6470 txBD->extendVlanBuffConfig = ((((uint32)options->PriorityCodePoint) << NETC_ETH_IP_PCP_SHIFT) & NETC_ETH_IP_PCP_MASK) | \
6471 ((((uint32)options->DropEligible) << NETC_ETH_IP_DEI_SHIFT) & NETC_ETH_IP_DEI_MASK) | \
6472 ((((uint32)options->VlanID) << NETC_ETH_IP_VID_SHIFT) & NETC_ETH_IP_VID_MASK ) | \
6473 ((((uint32)options->TagProtocolID) << NETC_ETH_IP_TPID_SHIFT) & NETC_ETH_IP_TPID_MASK);
6474 txBD->extendBuffConfig |= (((uint32)options->ExtensionFlags) << NETC_ETH_IP_E_FLAGS_SHIFT) & NETC_ETH_IP_E_FLAGS_MASK;
6475 #endif
6476 }
6477
6478 /* Writes in memory for BD are optimized and syncronization before starting transmission need to be done
6479 to assure that transmission BD is write correctly in memory. */
6480 MCAL_DATA_SYNC_BARRIER();
6481
6482 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
6483 /* Before sending, Flush + Invalidate cache in order write back the contents to main memory and mark the cache lines as invalid so that
6484 the future reads will be done from the memory. */
6485 CacheStatus = Cache_Ip_Clean(CacheType, CACHE_IP_DATA, TRUE);
6486 if (E_NOT_OK == CacheStatus)
6487 {
6488 Status = NETC_ETH_IP_STATUS_CACHE_ERROR;
6489 }
6490 else
6491 {
6492 #endif
6493 /* Update the current value of the producer index. */
6494 Netc_Eth_Ip_apxState[ctrlIndex]->LogicTxProducerIndex[ring] = (uint16)NextProducerIndex;
6495 /* Write the producer index into register to start frame sending. */
6496 netcSIsBase[ctrlIndex]->BDR_NUM[ring].TBPIR = NextProducerIndex;
6497
6498 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
6499 #if (NETC_ETH_IP_FILL_LEVEL_API_ENABLE == STD_ON)
6500 Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].NumberOfUsedBuff++;
6501 if (Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].MaxNumberOfUsedBuff < Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].NumberOfUsedBuff)
6502 {
6503 Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].MaxNumberOfUsedBuff = Netc_Eth_Ip_Tx_FillLevelInfo[ctrlIndex][ring].NumberOfUsedBuff;
6504 }
6505 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
6506 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
6507
6508 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
6509 }/* if (E_NOT_OK == CacheStatus) */
6510 #endif
6511
6512 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_TX_BUFFERS)
6513 }
6514 else
6515 {
6516 Status = NETC_ETH_IP_STATUS_TX_BUFF_BUSY;
6517 }
6518 }
6519 #endif
6520
6521 return Status;
6522 }
6523
6524 /*FUNCTION**********************************************************************
6525 *
6526
6527 * Function Name : Netc_Eth_Ip_GetTransmitStatus
6528 * implements Netc_Eth_Ip_GetTransmitStatus_Activity
6529 *END**************************************************************************/
6530 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTransmitStatus(uint8 ctrlIndex,
6531 uint8 ring,
6532 const Netc_Eth_Ip_BufferType *buff,
6533 Netc_Eth_Ip_TxInfoType *info)
6534 {
6535 uint32 ConsumerIndex;
6536 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
6537
6538 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6539 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6540 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
6541 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR);
6542 DevAssert(buff != NULL_PTR);
6543 #endif
6544 /* Read the consumer index */
6545 ConsumerIndex = netcSIsBase[ctrlIndex]->BDR_NUM[ring].TBCIR;
6546
6547 status = Netc_Eth_Ip_CheckFrameStatus(ctrlIndex, ring, ConsumerIndex, buff->data, info);
6548
6549 return status;
6550 }
6551
6552 /*FUNCTION**********************************************************************
6553 *
6554 * Function Name : Netc_Eth_Ip_ReleaseTxBuffers
6555 * implements Netc_Eth_Ip_ReleaseTxBuffers_Activity
6556 *END**************************************************************************/
6557 void Netc_Eth_Ip_ReleaseTxBuffers(const uint8 CtrlIdx, const uint8 Ring)
6558 {
6559 uint32 CurrDescrCheckIndex;
6560 uint32 ConsumerIndex;
6561 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6562 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6563 DevAssert(Netc_Eth_Ip_apxState[CtrlIdx] != NULL_PTR);
6564 DevAssert(Ring < Netc_Eth_Ip_apxState[CtrlIdx]->NumberOfTxBDR);
6565 #endif
6566
6567 /* Read the consumer index */
6568 ConsumerIndex = netcSIsBase[CtrlIdx]->BDR_NUM[Ring].TBCIR;
6569 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29();
6570
6571 CurrDescrCheckIndex = (Netc_Eth_Ip_apxState[CtrlIdx]->lastTxDataBuffAddrIdx[Ring]) % \
6572 (uint32)(Netc_Eth_Ip_apxState[CtrlIdx]->TxRingSize[Ring]);
6573
6574 while((TRUE == Netc_Eth_Ip_apxState[CtrlIdx]->LockTxBuffDescr[Ring][CurrDescrCheckIndex]) && \
6575 (ConsumerIndex != CurrDescrCheckIndex))
6576 {
6577 Netc_Eth_Ip_apxState[CtrlIdx]->LockTxBuffDescr[Ring][CurrDescrCheckIndex] = FALSE;
6578 CurrDescrCheckIndex = (CurrDescrCheckIndex + NETC_ETH_IP_PRODUCER_INCR) % \
6579 (uint32)(Netc_Eth_Ip_apxState[CtrlIdx]->TxRingSize[Ring]);
6580 }
6581
6582 Netc_Eth_Ip_apxState[CtrlIdx]->lastTxDataBuffAddrIdx[Ring] = CurrDescrCheckIndex;
6583 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29();
6584
6585 }
6586
6587 /*FUNCTION**********************************************************************
6588 *
6589 * Function Name : Netc_Eth_Ip_SetMacAddr
6590 * implements Netc_Eth_Ip_SetMacAddr_Activity
6591 *END**************************************************************************/
6592 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetMacAddr(uint8 CtrlIndex, const uint8 *MacAddr)
6593 {
6594 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
6595
6596 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6597 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6598 DevAssert(MacAddr != NULL_PTR);
6599 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
6600 #endif
6601
6602 /* If the controller is the PSI it should write directly the MAC address. */
6603 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
6604 {
6605 IP_NETC__ENETC0_PORT->PMAR0 = ((uint32)MacAddr[0U]) | ((uint32)MacAddr[1U] << 8U) | ((uint32)MacAddr[2U] << 16U) | ((uint32)MacAddr[3U] << 24U);
6606 IP_NETC__ENETC0_PORT->PMAR1 = ((uint32)MacAddr[4U]) | ((uint32)MacAddr[5U] << 8U);
6607 }
6608 /* If the controller is a VSI a mailbox request is sent to the PSI to change the MAC address. */
6609 else
6610 {
6611 uint16 PsiRspMessage;
6612 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_MAC_ADDR_SET, MacAddr, &PsiRspMessage);
6613 }
6614
6615 return Status;
6616 }
6617
6618 /*FUNCTION**********************************************************************
6619 *
6620 * Function Name : Netc_Eth_Ip_GetMacAddr
6621 * implements Netc_Eth_Ip_GetMacAddr_Activity
6622 *END**************************************************************************/
6623 void Netc_Eth_Ip_GetMacAddr(uint8 CtrlIndex, uint8 *MacAddr)
6624 {
6625 uint32 tempRegValue;
6626
6627 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6628 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6629 DevAssert(MacAddr != NULL_PTR);
6630 #endif
6631
6632 /* Get from physical Address lower register. */
6633 tempRegValue = netcSIsBase[CtrlIndex]->SIPMAR0;
6634 MacAddr[0U] = (uint8)(tempRegValue & 0xFFU);
6635 MacAddr[1U] = (uint8)((tempRegValue >> 8U) & 0xFFU);
6636 MacAddr[2U] = (uint8)((tempRegValue >> 16U) & 0xFFU);
6637 MacAddr[3U] = (uint8)((tempRegValue >> 24U) & 0xFFU);
6638
6639 /* Get from physical Address high register. */
6640 tempRegValue = netcSIsBase[CtrlIndex]->SIPMAR1;
6641 MacAddr[4U] = (uint8)(tempRegValue & 0xFFU);
6642 MacAddr[5U] = (uint8)((tempRegValue >> 8U) & 0xFFU);
6643 }
6644
6645 /*FUNCTION**********************************************************************
6646 *
6647 * Function Name : Netc_Eth_Ip_GetCounter
6648 * implements Netc_Eth_Ip_GetCounter_Activity
6649 *END**************************************************************************/
6650 uint32 Netc_Eth_Ip_GetCounter(uint8 CtrlIndex, Netc_Eth_Ip_CounterType Counter)
6651 {
6652 const volatile uint32 *CounterAddr;
6653
6654 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
6655 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
6656 #endif
6657 /* Compute addres of the counter. */
6658 CounterAddr = (volatile uint32 *)((uint32)netcSIsBase[CtrlIndex] + (uint32)Counter);
6659
6660 return *CounterAddr;
6661 }
6662
6663 /*!
6664 * @brief : Function for accessing two 32 bits counters.
6665 * @details : Function for extracting the counter value using base/offset
6666 *
6667 * @param[in] baseAddressValue base address in uint32
6668 * @param[in] offsetAddressValue offset from the base
6669 *
6670 * @return Register value
6671 */
6672 static inline uint64 Netc_Eth_Ip_Extract64bitsFrom32bitsReg(const uint32 baseAddressValue, const uint32 offsetAddressValue)
6673 {
6674 uint32 lessSignificantPtrValue;
6675 const volatile uint32 *ptrToLessSignificantData;
6676 uint64 lessSignificantAddressData, mostSignificantAddressData;
6677
6678 /* The most significant is higher in memory, the next address to get the next 32 bits */
6679 lessSignificantPtrValue = baseAddressValue + offsetAddressValue;
6680
6681 /* Convert back the numbers in pointers */
6682 ptrToLessSignificantData = (volatile uint32 *) lessSignificantPtrValue;
6683
6684 /* Note that there is only one higher value buffer, should be exclusive... semaphore, what about the other cores? High level problem to be aware of */
6685 lessSignificantAddressData = ptrToLessSignificantData[0U];
6686 mostSignificantAddressData = ptrToLessSignificantData[1U];
6687
6688 /* putting it all together */
6689 return ((mostSignificantAddressData << NETC_ETH_IP_32BIT_SHIFT) | lessSignificantAddressData);
6690 }
6691
6692 /*!
6693 * @brief : Function for accessing two 32 bits counters in a table.
6694 * @details : Function for getting the two 32 bits counters using two 32 bits accesses.
6695 *
6696 * @param[in] Reg 32bits register pointer
6697 *
6698 * @return Register value
6699 */
6700 static inline uint64 Netc_Eth_Ip_GetCounterLocal(const volatile uint32 *Reg)
6701 {
6702 return Netc_Eth_Ip_Extract64bitsFrom32bitsReg((uint32) Reg, 0U);
6703 }
6704
6705 /*!
6706 * @brief : Function for initializing NTMP table.
6707 * @details : Function enables the netc controller, initializes the tables and then diasbles the netc controller
6708 *
6709 * @param[in] ctrlIndex controller index
6710 * @param[in] config controller configuration
6711 *
6712 */
6713 static inline void Netc_Eth_Ip_InitNTMPTables(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
6714 {
6715 #if defined(ERR_IPV_NETC_E051130)
6716 #if (STD_ON == ERR_IPV_NETC_E051130)
6717 Netc_Eth_Ip_StatusType Status;
6718 #endif
6719 #endif
6720
6721 /* Tables initialization should be done after enabling the controller. Set the EN bit in Station interface mode register (SIMR) to enable psi0*/
6722 netcSIsBase[ctrlIndex]->SIMR |= NETC_F3_SI0_SIMR_EN_MASK;
6723
6724 /* only for PSI0 */
6725 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType)
6726 {
6727 /* Init Time Gate Scheduling Table*/
6728 /* check if TAS is enabled or not on PSI0*/
6729 Netc_Eth_Ip_PortTimeAwareShaperEnabled = (*config->generalConfig).portTimeAwareShaperEnable;
6730
6731 if (TRUE == Netc_Eth_Ip_PortTimeAwareShaperEnabled)
6732 {
6733 #if defined(ERR_IPV_NETC_E051130)
6734 #if (STD_ON == ERR_IPV_NETC_E051130)
6735 /* Default time gate scheduling conditions on the pseudo port */
6736 Status = Netc_Eth_Ip_InitTimeGateSchedulingFeature(ctrlIndex);
6737 if (Status == NETC_ETH_IP_STATUS_SUCCESS)
6738 {
6739 #endif
6740 #endif
6741 /* Add time gate scheduling table entries data */
6742 Netc_Eth_Ip_InitTimeGateSchedulingTableEntryData(config);
6743 #if defined(ERR_IPV_NETC_E051130)
6744 #if (STD_ON == ERR_IPV_NETC_E051130)
6745 }
6746 #endif
6747 #endif
6748 }
6749
6750 /* Init Vlan Filter Table*/
6751 #if (NETC_ETH_IP_NUMBER_OF_VLAN_FILTER_ENTRIES > 0U)
6752 Netc_Eth_Ip_ConfigVLANFilterTable(ctrlIndex, config);
6753 #endif
6754 }
6755
6756 /* Init Receive Flow Steering Table */
6757 (void)Netc_Eth_Ip_ConfigRfsTable(ctrlIndex, config);
6758
6759 /* After table initializatios the controller should be disabled. Clear the EN bit in Station interface mode register (SIMR) to disalbe psi0 */
6760 netcSIsBase[ctrlIndex]->SIMR &= ~NETC_F3_SI0_SIMR_EN_MASK;
6761 }
6762
6763 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT))
6764 static inline void Netc_Eth_Ip_ReadFrame_AddCustomRxTagHeader(uint8 ctrlIndex,
6765 uint8 ring,
6766 const uint8* tagBytes,
6767 Netc_Eth_Ip_BufferType *buff
6768 )
6769 {
6770 uint16 byteId;
6771 const Netc_Eth_Ip_RxBDRType *rxBDR;
6772 uint32 HostReason;
6773
6774 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
6775 HostReason = ((rxBDR->configRxBD[3U] >> NETC_ETH_IP_HOSTREASON_WB_SHIFT) & NETC_ETH_IP_HOSTREASON_WB_MASK);
6776 if ((0U == ctrlIndex) && (0U == ring) && (NETC_ETH_IP_HOSTREASON_SW_PTP == HostReason))
6777 {
6778 /* Shift data to leave space for tag */
6779 for (byteId = (buff->length - 1U); byteId >= NETC_ETH_IP_RX_CUSTOM_TAG_START_BYTE; byteId--)
6780 {
6781 (buff->data)[byteId + (uint16)(NETC_ETH_IP_RX_CUSTOM_TAG_NUM_BYTES)] = (buff->data)[byteId];
6782 }
6783
6784 /* Number of bytes that will be added before the payload. */
6785 for (byteId = 0U; byteId < (uint16)(NETC_ETH_IP_RX_CUSTOM_TAG_NUM_BYTES); byteId++)
6786 {
6787 (buff->data)[byteId + NETC_ETH_IP_RX_CUSTOM_TAG_START_BYTE] = tagBytes[byteId];
6788 }
6789 buff->length += NETC_ETH_IP_RX_CUSTOM_TAG_NUM_BYTES;
6790 }
6791 }
6792 #endif /* defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT) */
6793
6794
6795 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF))
6796 static inline void Netc_Eth_Ip_HostReasonTimeStamp(uint8 ctrlIndex,
6797 uint8 ring,
6798 Netc_Eth_Ip_StatusType* status,
6799 uint32 CurrLowTime
6800 )
6801 {
6802 const Netc_Eth_Ip_TxTimestampResponseType *TempTxResponse;
6803 uint16 TxTimestampID;
6804 Netc_Eth_Ip_TimeType LatestTxTimestamp = { 0U, 0U};
6805 uint32 CurrHighTime = 0U;
6806
6807 CurrHighTime = netcSIsBase[0U]->SICTR1;
6808
6809 if ((0U == ctrlIndex) && (0U == ring))
6810 {
6811 TempTxResponse = (Netc_Eth_Ip_TxTimestampResponseType *)Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
6812 TxTimestampID = TempTxResponse->TxTimestampID;
6813
6814 LatestTxTimestamp.nanosecondsL = TempTxResponse->Timestamp;
6815 LatestTxTimestamp.nanosecondsH = CurrHighTime;
6816 if(CurrLowTime < LatestTxTimestamp.nanosecondsL)
6817 {
6818 LatestTxTimestamp.nanosecondsH--;
6819 }
6820
6821 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][TxTimestampInfoBuffIdx].TimestampValue.nanosecondsL = LatestTxTimestamp.nanosecondsL;
6822 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][TxTimestampInfoBuffIdx].TimestampValue.nanosecondsH = LatestTxTimestamp.nanosecondsH;
6823 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][TxTimestampInfoBuffIdx].TxTimeStampID = TxTimestampID;
6824 TxTimestampInfoBuffIdx++;
6825 TxTimestampInfoBuffIdx = (NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR / NETC_ETH_IP_PRODUCER_INCR == TxTimestampInfoBuffIdx) ? 0U : TxTimestampInfoBuffIdx;
6826
6827 *status = NETC_ETH_IP_STATUS_HOSTREASON_TIMESTAMP;
6828 }
6829 }
6830 #endif
6831
6832
6833
6834 static inline void Netc_Eth_Ip_ReadFrame_ReturnBufferDetails(uint8 ctrlIndex,
6835 uint8 ring,
6836 Netc_Eth_Ip_BufferType *buff
6837 )
6838 {
6839 const Netc_Eth_Ip_RxBDRType *rxBDR;
6840 uint32 rxIndex = 0;
6841 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
6842 uint32 bufferIndex = 0;
6843 #endif
6844
6845 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
6846 rxIndex = Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring];
6847 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
6848 bufferIndex = ring * NETC_ETH_MAX_NUMBER_OF_RXBD + rxIndex;
6849
6850 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
6851 {
6852 #endif
6853 /* All conditions meet, return buffer data details. */
6854 buff->data = (uint8 *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxDataBufferAddr[ring]) + \
6855 (rxIndex * Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring]));
6856 #if (NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS == STD_ON)
6857 }
6858 else
6859 {
6860 buff->data = (uint8*)Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffAddr[bufferIndex];
6861 }
6862 #endif
6863 /* According to the requirement CPR_RTD_00284.eth */
6864 if (rxBDR->configRxBD[2U] > Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring])
6865 {
6866 buff->length = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring] & NETC_ETH_IP_RXBD_LENGTH_MASK);
6867 }
6868 else
6869 {
6870 buff->length = (uint16)(rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_LENGTH_MASK);
6871 }
6872 }
6873
6874 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON==NETC_ETH_IP_CUSTOM_TAG_SUPPORT))
6875 static inline void Netc_Eth_Ip_ReadFrame_CustomizedTPID(uint8 ctrlIndex,
6876 uint8 ring,
6877 uint8 *tagBytes,
6878 uint32 HostReason
6879 )
6880 {
6881 Netc_Eth_Ip_RxBDRType *rxBDR;
6882 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
6883 if ((0U == ctrlIndex) && (0U == ring) && (NETC_ETH_IP_HOSTREASON_SW_PTP == HostReason))
6884 {
6885 /* Could be another customised TPID */
6886 tagBytes[0U] = (uint8)((Netc_Eth_Ip_apxState[0U]->generalConfig->CustomTPID >> 8) & 0xFFU);
6887 tagBytes[1U] = (uint8)(Netc_Eth_Ip_apxState[0U]->generalConfig->CustomTPID & 0xFFU);
6888 tagBytes[2U] = NETC_ETH_IP_RX_CUSTOM_TAG_TYPE(2U) | NETC_ETH_IP_RX_CUSTOM_TAG_SUBTYPE(0U);
6889 tagBytes[3U] = NETC_ETH_IP_RX_CUSTOM_TAG_DR((uint8)(Netc_Eth_Ip_apxState[0U]->generalConfig->CustomDR)) | NETC_ETH_IP_RX_CUSTOM_TAG_IPV((uint8)(Netc_Eth_Ip_apxState[0U]->generalConfig->CustomIPV));
6890 tagBytes[4U] = NETC_ETH_IP_RX_CUSTOM_TAG_SRCPORT((rxBDR->configRxBD[1U] & NETC_ETH_IP_RXBD_SRC_PORT_MASK)) | \
6891 NETC_ETH_IP_RX_CUSTOM_TAG_SRCSWITCH(0U);
6892 tagBytes[5U] = NETC_ETH_IP_RX_CUSTOM_TAG_HOSTREASON(HostReason);
6893 }
6894 }
6895 #endif
6896
6897
6898 static inline void Netc_Eth_Ip_EnableController_RxCoalescing(uint8 ctrlIndex)
6899 {
6900 uint8 ringCounter = 0U;
6901
6902 /* Assumption: If the Coalescing ISR is enabled on the ctrlIndex, it means all the rings will have the ISR enabled.
6903 Context: If at least one controller has the Tx Coalesing Isr Enabled, TxCoalescingIsrEnabled will be true if the generated thresholds will not be 0. */
6904 boolean RxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[ctrlIndex]->RxTimerThreshold[0U] != 0U) &&
6905 (Netc_Eth_Ip_apxState[ctrlIndex]->RxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ;
6906
6907 /* Tx and Rx Interrupts enabled*/
6908 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR; ringCounter++)
6909 {
6910 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
6911 /* Write the interrupt settings as configured */
6912 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBIER |= (uint32)1U;
6913 if (RxCoalescingIsrEnabled)
6914 {
6915 /*If timer threshold is used it should be set when RBaICR0[ICEN]=0 to avoid missing a "first packet" received condition which starts the timer.*/
6916 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR1 |= NETC_F3_SI0_RBICR1_ICTT( Netc_Eth_Ip_apxState[ctrlIndex]->RxTimerThreshold[ringCounter]);
6917 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 |= NETC_F3_SI0_RBICR0_ICPT(Netc_Eth_Ip_apxState[ctrlIndex]->RxPacketsThreshold[ringCounter]);
6918 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].RBICR0 |= NETC_F3_SI0_RBICR0_ICEN(1U);
6919 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
6920 }
6921 else
6922 {
6923 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03();
6924 }
6925 }
6926 }
6927
6928
6929 static inline void Netc_Eth_Ip_EnableController_TxCoalescing(uint8 ctrlIndex)
6930 {
6931 uint8 ringCounter = 0U;
6932
6933 /* Assumption: If the Coalescing ISR is enabled on the ctrlIndex, it means all the rings will have the ISR enabled.
6934 Context: If at least one controller has the Tx Coalesing Isr Enabled, TxCoalescingIsrEnabled will be true if the generated thresholds will not be 0. */
6935 boolean TxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[ctrlIndex]->TxTimerThreshold[0U] != 0U) &&
6936 (Netc_Eth_Ip_apxState[ctrlIndex]->TxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ;
6937 for (ringCounter = 0U; ringCounter < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfTxBDR; ringCounter++)
6938 {
6939
6940 if (TxCoalescingIsrEnabled)
6941 {
6942 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER = NETC_F3_SI0_TBIER_TXTIE(1U);
6943 /*If timer threshold is used it should be set when TBaICR0[ICEN]=0 to avoid missing a "firstpacket" transmitted condition which starts the timer.*/
6944 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR1 |= NETC_F3_SI0_TBICR1_ICTT( Netc_Eth_Ip_apxState[ctrlIndex]->TxTimerThreshold[ringCounter]);
6945 /*If packet threshold is used it should be set when TBaICR0[ICEN] is set */
6946 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBICR0 |= (NETC_F3_SI0_TBICR0_ICEN(1U) | NETC_F3_SI0_TBICR0_ICPT(Netc_Eth_Ip_apxState[ctrlIndex]->TxPacketsThreshold[ringCounter]));
6947
6948 }
6949 else
6950 {
6951 netcSIsBase[ctrlIndex]->BDR_NUM[ringCounter].TBIER = NETC_F3_SI0_TBIER_TXFIE(1U);
6952 }
6953 }
6954 }
6955
6956 static inline void Netc_Eth_Ip_SetupErrorReporting_EnableUncorrectableErrors(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config)
6957 {
6958 uint8 u8Iterator = 0U;
6959 /* For the Event Collector to assert INTA for a reported error, it must enable the reporting of the error
6960 When set, this bit enables the generation of an interrupt when a fatal error is reported by any of the Integrated Endpoints (iEPs)
6961 or the Event Collector itself.*/
6962 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCIE_CFC_AER_ROOT_ERR_CMD |= (ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN(1U) |
6963 ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN(1U));
6964 /*Unmask interrupts for ENETC0, SWITCH, TIMER, EMDIO*/
6965 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator++ )
6966 {
6967 netcPCIePFBase[u8Iterator]->PCIE_CFC_AER_UCORR_ERR_MASK = NETC_F1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(0U);
6968 }
6969
6970 /*Unmask interrupts for PSI0*/
6971 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_UCORR_ERR_MASK = NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(0U);
6972
6973 /*Unmask interrupts for vfs*/
6974 for (u8Iterator = 1U; u8Iterator < FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS; u8Iterator++ )
6975 {
6976 netcVFBase[u8Iterator]->PCIE_CFC_AER_UCORR_ERR_MASK = NETC_VF1_PCI_HDR_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(0U);
6977 }
6978
6979 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_ETH_NUMBER_OF_CTRLS; u8Iterator++ )
6980 {
6981 netcSIsBase[u8Iterator]->SIUPECR = NETC_F3_SI0_SIUPECR_RD(0U);
6982 netcSIsBase[u8Iterator]->SIUNSBECR = NETC_F3_SI0_SIUNSBECR_THRESHOLD(psi0Config->errorReportingSystemBusErrorsThreshold);
6983 netcSIsBase[u8Iterator]->SIUNMECR = NETC_F3_SI0_SIUNMECR_RD(0U) | NETC_F3_SI0_SIUNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
6984 netcSIsBase[u8Iterator]->SIUFSBECR = NETC_F3_SI0_SIUFSBECR_RD(0U);
6985 netcSIsBase[u8Iterator]->SIUFMECR = NETC_F3_SI0_SIUFMECR_RD(0U);
6986 netcSIsBase[u8Iterator]->SIUFIECR = NETC_F3_SI0_SIUFIECR_RD(0U);
6987 }
6988
6989 /* Switch system bus error. */
6990 IP_NETC__SW0_COMMON->UNSBECR = NETC_F2_COMMON_UNSBECR_THRESHOLD(psi0Config->errorReportingSystemBusErrorsThreshold);
6991
6992
6993 IP_NETC__SW0_COMMON->UNMACECR = ~NETC_F2_COMMON_UNMACECR_PORT0(0U) |
6994 ~NETC_F2_COMMON_UNMACECR_PORT1(0U) |
6995 ~NETC_F2_COMMON_UNMACECR_PORT2(0U);
6996 IP_NETC__ENETC0_COMMON->UNMACECR = NETC_F3_COMMON_UNMACECR_PORT0(0u);
6997
6998 /*Internal memory multi bit ECC error */
6999 IP_NETC__NETC_PRIV->UNMECR = NETC_PRIV_UNMECR_RD(0U) | NETC_PRIV_UNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
7000 IP_NETC__ENETC0_COMMON->UNMECR = NETC_F3_COMMON_UNMECR_RD(0U) | NETC_F3_COMMON_UNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
7001 IP_NETC__SW0_COMMON->UNMECR = NETC_F2_COMMON_UNMECR_RD(0U) | NETC_F2_COMMON_UNMECR_THRESHOLD(psi0Config->errorReportingMultiBitECCErrorsThreshold);
7002
7003 /*integrity error Uncorrectable Non-Fatal Integrity Faults */
7004 ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUNIECR = NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold) | NETC_F1_GLOBAL_EMDIOUNIECR_RD(0U);
7005
7006 /*integrity error Uncorrectable Non-Fatal Integrity Faults*/
7007 IP_NETC__NETC_PRIV->UNIECR = NETC_PRIV_UNIECR_RD(0U) |NETC_PRIV_UNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold);
7008 IP_NETC__ENETC0_COMMON->UNIECR = NETC_F3_COMMON_UNIECR_RD(0U) | NETC_F3_COMMON_UNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold);
7009 IP_NETC__SW0_COMMON->UNIECR = NETC_F2_COMMON_UNIECR_RD(0U) | NETC_F2_COMMON_UNIECR_THRESHOLD(psi0Config->errorReportigIntegrityErrorsThreshold);
7010
7011 ((IP_NETC__TMR0_GLOBAL->ERROR).TIMER).TUFSBECR = NETC_F0_GLOBAL_TUFSBECR_RD(0U);
7012 ((IP_NETC__EMDIO_GLOBAL->ERROR).EMDIO).EMDIOUFSBECR = NETC_F1_GLOBAL_EMDIOUFSBECR_RD(0U);
7013 IP_NETC__SW0_COMMON->UFSBECR = NETC_F2_COMMON_UFSBECR_RD(0U);
7014
7015 IP_NETC__NETC_PRIV->UFMECR = NETC_PRIV_UFMECR_RD(0U);
7016 IP_NETC__ENETC0_COMMON->UFMECR = NETC_F3_COMMON_UFMECR_RD(0U) ;
7017 IP_NETC__SW0_COMMON->UFMECR = NETC_F2_COMMON_UFMECR_RD(0U);
7018
7019 IP_NETC__NETC_PRIV->UFIECR = NETC_PRIV_UFIECR_RD(0U);
7020 IP_NETC__ENETC0_COMMON->UFIECR = NETC_F3_COMMON_UFIECR_RD(0U) ;
7021 IP_NETC__SW0_COMMON->UFIECR = NETC_F2_COMMON_UFIECR_RD(0U);
7022
7023 IP_NETC__SW0_COMMON->UFSBECR = NETC_F2_COMMON_UFSBECR_RD(0U);
7024 }
7025
7026
7027 static inline void Netc_Eth_Ip_SetupErrorReporting_EnableCorrectableErrors(const Netc_Eth_Ip_EnetcGeneralConfigType *psi0Config)
7028 {
7029 uint8 u8Iterator = 0U;
7030 /* For the Event Collector to assert INTA for a reported error, it must enable the reporting of the error
7031 When set, this bit enables the generation of an interrupt when a correctable error is reported by any of the Integrated Endpoints (iEPs)
7032 or the Event Collector itself.*/
7033 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCIE_CFC_AER_ROOT_ERR_CMD |= ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN(1U);
7034
7035 /* Function F0 (Timer) and F1 (EMDIO) must not clear mask bit, enabling reporting of correctable interrupts, to prevent loss of uncorrectable error reporting.*/
7036 for (u8Iterator = 2U; u8Iterator < FEATURE_NETC_NUMBER_OF_FUNC; u8Iterator++ )
7037 {
7038 netcPCIePFBase[u8Iterator]->PCIE_CFC_AER_CORR_ERR_MASK = NETC_F0_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(0U);
7039 }
7040
7041 /*Unmask interrupts for PSI0*/
7042 IP_NETC__NETC_F3_PCI_HDR_TYPE0->PCIE_CFC_AER_CORR_ERR_MASK = NETC_F3_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(0U);
7043
7044 for (u8Iterator = 1U; u8Iterator < FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS; u8Iterator++ )
7045 {
7046 netcVFBase[u8Iterator]->PCIE_CFC_AER_CORR_ERR_MASK = NETC_VF1_PCI_HDR_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(0U);
7047 }
7048
7049 for (u8Iterator = 0U; u8Iterator < FEATURE_NETC_ETH_NUMBER_OF_CTRLS; u8Iterator++ )
7050 {
7051 netcSIsBase[u8Iterator]->SICMECR = NETC_F3_SI0_SICMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold);
7052 }
7053
7054 IP_NETC__NETC_PRIV->CMECR = NETC_PRIV_CMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold);
7055 IP_NETC__ENETC0_COMMON->CMECR = NETC_F3_COMMON_CMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold) ;
7056 IP_NETC__SW0_COMMON->CMECR = NETC_F2_COMMON_CMECR_THRESHOLD(psi0Config->errorReportigSingleECCErrorsThreshold);
7057 }
7058
7059
7060 static inline void Netc_Eth_Ip_DeleteMACFilterEntry_MarkEntryEmpty(const uint8 CtrlIndex,
7061 boolean* const MatchedEntry,
7062 const uint8 CurrentEntry,
7063 const uint8 *MacAddr)
7064 {
7065 uint8 MACBytesMached = 0U;
7066 /* There will be one entry removed at a time. */
7067 if(*MatchedEntry == FALSE)
7068 {
7069 while((MacAddr[MACBytesMached] == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].MACAddr[MACBytesMached]) && (MACBytesMached < NETC_ETH_IP_MAC_BYTES_SIZE))
7070 {
7071 MACBytesMached++;
7072 }
7073
7074 if(NETC_ETH_IP_MAC_BYTES_SIZE == MACBytesMached)
7075 {
7076 /* Provide data was matched. */
7077 *MatchedEntry = TRUE;
7078 /* Mark entry as an empty slot. */
7079 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus = FALSE;
7080 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
7081 }
7082 else
7083 {
7084 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
7085 }
7086 }
7087 else
7088 {
7089 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01();
7090 }
7091 }
7092
7093
7094 static inline void Netc_Eth_Ip_ConfigureBufferDescriptors(const uint16 BufferIndex, const Netc_Eth_Ip_TxOptionsType *options, Netc_Eth_Ip_TxBDRType *txBD)
7095 {
7096 if ((0U == BufferIndex) && (options != NULL_PTR))
7097 {
7098 if(NETC_ETH_IP_SWT_MANAGEMNT == options->Flag)
7099 {
7100 /* Set Flag(FL) type; set ingress or egress port value; set value of flag qualifier(FLQ). */
7101 txBD->buffConfig |= (((uint32)NETC_ETH_IP_FLQ_VALUE << NETC_ETH_IP_FLQ_SHIFT) | \
7102 ((uint32)(options->IngrOrEgrPortNumber) << NETC_ETH_IP_INGR_EGRESS_PORT_SHIFT));
7103 if(1U == options->SwtMgSendingOpt)
7104 {
7105 txBD->buffConfig |= ((((uint32)options->SwtMgSendingOpt) << NETC_ETH_IP_SMSO_SHIFT) | \
7106 (((uint32)options->TimestampRefReq) << NETC_ETH_IP_TSR_SHIFT) | \
7107 (((uint32)options->InternalPriority) << NETC_ETH_IP_IPV_SHIFT) | \
7108 (((uint32)options->DiscardResilience) << NETC_ETH_IP_DR_SHIFT));
7109 }
7110 }
7111 else if (NETC_ETH_IP_TXSTART == options->Flag)
7112 {
7113 txBD->buffConfig |= (((uint32)NETC_ETH_IP_TXSTART) << NETC_ETH_IP_FL_SHIFT) | \
7114 (((uint32)options->TxStartEnable) << NETC_ETH_IP_TSR_SHIFT) | \
7115 (options->TxStartTime);
7116 }
7117 else
7118 {
7119 /*MISRA C-2012 Rule 15.7*/
7120 }
7121 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7122 txBD->timestamp = options->Timestamp;
7123 txBD->extendVlanBuffConfig = ((((uint32)options->PriorityCodePoint) << NETC_ETH_IP_PCP_SHIFT) & NETC_ETH_IP_PCP_MASK) | \
7124 ((((uint32)options->DropEligible) << NETC_ETH_IP_DEI_SHIFT) & NETC_ETH_IP_DEI_MASK) | \
7125 ((((uint32)options->VlanID) << NETC_ETH_IP_VID_SHIFT) & NETC_ETH_IP_VID_MASK ) | \
7126 ((((uint32)options->TagProtocolID) << NETC_ETH_IP_TPID_SHIFT) & NETC_ETH_IP_TPID_MASK);
7127 txBD->extendBuffConfig |= (((uint32)options->ExtensionFlags) << NETC_ETH_IP_E_FLAGS_SHIFT) & NETC_ETH_IP_E_FLAGS_MASK;
7128 #endif
7129 }
7130 }
7131
7132 static inline void Netc_Eth_Ip_InitSI_ConfigureVSI(const uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config)
7133 {
7134 uint8 u8Iterator;
7135 uint8 siHwId;
7136 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
7137 const Netc_Eth_Ip_GeneralSIConfigType *SiConfig;
7138 #endif
7139 /* Configure the VSIs using config->generalConfig */
7140 for (u8Iterator = 0U; u8Iterator < (*config->generalConfig).numberOfConfiguredSis; u8Iterator++)
7141 {
7142 /* Identify the PSI in the list of SIs to configure */
7143 siHwId = (*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].siId;
7144
7145 /* Enable PSI; In reset configuration PSI is already started, but to be sure that will not be any problems. */
7146 if (TRUE == (*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].enableSi)
7147 {
7148 /** Assure that SI is not enabled. */
7149 netcSIsBase[siHwId]->SIMR &= ~(NETC_F3_SI0_SIMR_EN_MASK);
7150
7151 if (ctrlIndex == siHwId)
7152 {
7153 /* Master enable for a station interface.*/
7154 IP_NETC__ENETC0_BASE->PMR = IP_NETC__ENETC0_BASE->PMR | (NETC_F3_PMR_SI0EN_MASK << siHwId);
7155
7156 /* For the PSI the MAC address will be configured both for the ENETC Port and for the PSI0 */
7157 /* Configure the port primary MAC address */
7158 IP_NETC__ENETC0_PORT->PMAR0 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[0U]) | \
7159 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[1U]) << 8U) | \
7160 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[2U]) << 16U) | \
7161 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[3U]) << 24U);
7162 IP_NETC__ENETC0_PORT->PMAR1 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[4U]) | \
7163 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[5U]) << 8U);
7164 IP_NETC__ENETC0_PORT->POR = 0U; /* Enable Rx and Tx Path for port (for S32N the default status for Rx and Tx path is disabled.) */
7165 }
7166 else
7167 {
7168
7169 /* Master enable for a station interface.*/
7170 IP_NETC__ENETC0_BASE->PMR = IP_NETC__ENETC0_BASE->PMR | (NETC_F3_PMR_SI0EN_MASK << siHwId);
7171
7172 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers */
7173 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR0 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[0U]) | \
7174 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[1U]) << 8U) | \
7175 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[2U]) << 16U) | \
7176 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[3U]) << 24U);
7177
7178 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR1 = ((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[4U]) | \
7179 (((uint32)(*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].primaryMACAddress[5U] )<< 8U);
7180 /* Configure where the PSI receives the message for enabled VSIs. */
7181 if(NULL_PTR != config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U])
7182 {
7183 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.VSI_NUM[siHwId - 1U].PSIVMSGRCVAR0 = (uint32)config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U] | \
7184 NETC_ETH_IP_VSITOPSI_MSG_SIZE;
7185 }
7186 }
7187
7188 /* Number of entries in a MSI table for the current SI. */
7189 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR2 = NETC_ETH_IP_NUM_OF_ENTRIES_MSITABLE;
7190
7191 /* Configure the number or TX and RX BD Rings for each SI */
7192 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_NUM_TX_BDR_MASK | NETC_F3_PSICFGR0_NUM_RX_BDR_MASK);
7193
7194 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_NUM_TX_BDR((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].NumberOfTxBDR) | \
7195 NETC_F3_PSICFGR0_NUM_RX_BDR((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].NumberOfRxBDR);
7196
7197 /* Configure the bandwidth weight for the current SI */
7198 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIBW((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].SIBandwidthWeight);
7199
7200 /* Configure pruning to be enabled by default for each SI. */
7201 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SPE_MASK;
7202
7203 /* Configure the station interface PRIO to TC mapping register for the current SI */
7204 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR1 = NETC_F3_PSICFGR1_TC0_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[0]) | \
7205 NETC_F3_PSICFGR1_TC1_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[1]) | \
7206 NETC_F3_PSICFGR1_TC2_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[2]) | \
7207 NETC_F3_PSICFGR1_TC3_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[3]) | \
7208 NETC_F3_PSICFGR1_TC4_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[4]) | \
7209 NETC_F3_PSICFGR1_TC5_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[5]) | \
7210 NETC_F3_PSICFGR1_TC6_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[6]) | \
7211 NETC_F3_PSICFGR1_TC7_MAP((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].priorityToTrafficClassMapping[7]);
7212
7213 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
7214 SiConfig = &((*config->generalConfig->stationInterfaceGeneralConfig)[siHwId]);
7215
7216 if (TRUE == SiConfig->EnableSIVlan)
7217 {
7218 /* Enable VLAN and select tag protocol, priority code point, drop eligible indicator and VLAN identifier */
7219 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR = NETC_F3_PSIVLANR_TPID(SiConfig->SiVLANConfig.ProtocolIdentifier) |
7220 NETC_F3_PSIVLANR_PCP(SiConfig->SiVLANConfig.PriorityCodePoint) |
7221 NETC_F3_PSIVLANR_VID(SiConfig->SiVLANConfig.VlanIdentifier) |
7222 NETC_F3_PSIVLANR_E(1U) | NETC_F3_PSIVLANR_DEI((SiConfig->SiVLANConfig.DropIndicator) ? 1U : 0U);
7223 }
7224 else
7225 {
7226 /* Disable VLAN and select tag protocol */
7227 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR &= ~NETC_F3_PSIVLANR_E(1U);
7228 }
7229
7230 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_SIVC_MASK | NETC_F3_PSICFGR0_SIVIE_MASK | NETC_F3_PSICFGR0_VTE_MASK);
7231 /* Insert VLAN Ethertype and enable insertion of the SI-based VLAN into frames sent by this SI. This config apply for generic */
7232 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIVC(SiConfig->SIVlanControl) |
7233 NETC_F3_PSICFGR0_SIVIE((SiConfig->EnableSoftwareVlanInsert) ? 1U : 0U) |
7234 NETC_F3_PSICFGR0_VTE((SiConfig->EnableVLANTagExtract) ? 1U : 0U);
7235 #endif
7236
7237 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_ASE(((*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].enableAntiSpoofing) ? 1U : 0U);
7238
7239 if (ctrlIndex != siHwId)
7240 {
7241 /* Enable bus for virtual function. */
7242 netcVFBase[u8Iterator]->PCI_CFH_CMD |= NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(1U);
7243 }
7244 }
7245 }
7246
7247 }
7248
7249
7250
7251 /*FUNCTION**********************************************************************
7252 *
7253 * Function Name : Netc_Eth_Ip_GetCounter64
7254 * implements Netc_Eth_Ip_GetCounter64_Activity
7255 *END**************************************************************************/
7256 uint64 Netc_Eth_Ip_GetCounter64(uint8 CtrlIndex, Netc_Eth_Ip_CounterType Counter)
7257 {
7258 uint64 CounterValue;
7259
7260 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7261 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7262 #endif
7263
7264 CounterValue = Netc_Eth_Ip_GetCounterLocal((volatile uint32 *)((uint32)netcSIsBase[CtrlIndex] + (uint32)Counter));
7265
7266 return CounterValue;
7267 }
7268
7269 /*FUNCTION**********************************************************************
7270 *
7271 * Function Name : Netc_Eth_Ip_IsFrameAvailable
7272 * implements Netc_Eth_Ip_IsFrameAvailable_Activity
7273 *END**************************************************************************/
7274 boolean Netc_Eth_Ip_IsFrameAvailable(uint8 ctrlIndex, uint8 ring)
7275 {
7276 const Netc_Eth_Ip_RxBDRType *rxBDR;
7277 boolean bFrameAvailable = FALSE;
7278 uint32 rxConsumerIdx;
7279 uint32 rxProducerIdx;
7280 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
7281 #if (STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
7282 uint32 rxCurrentOccupied;
7283 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
7284 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
7285
7286 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7287 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7288 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
7289 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR);
7290 #endif
7291
7292 rxConsumerIdx = netcSIsBase[ctrlIndex]->BDR_NUM[ring].RBCIR;
7293 rxProducerIdx = netcSIsBase[ctrlIndex]->BDR_NUM[ring].RBPIR;
7294
7295 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
7296 #if (STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
7297 /* Update maximum fill level of current ring */
7298 rxCurrentOccupied = (rxConsumerIdx > rxProducerIdx) ? (Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ring] - rxConsumerIdx + rxProducerIdx) : (rxProducerIdx - rxConsumerIdx);
7299
7300 if (rxCurrentOccupied > Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[ctrlIndex][ring])
7301 {
7302 Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[ctrlIndex][ring] = rxCurrentOccupied;
7303 }
7304 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
7305 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
7306
7307 /* Get the current descriptor corresponding to the buff pointer (by looping through the descriptors) */
7308 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
7309
7310 /* If the producer index is different from consumer index, then a frame is in the point to be receive. */
7311 /* If the ready bit is set in the writeback descriptor at least a frame is available */
7312 if ( (rxProducerIdx != rxConsumerIdx) && \
7313 (NETC_ETH_IP_RXBD_READY_MASK == (rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_READY_MASK)) )
7314 {
7315 bFrameAvailable = TRUE;
7316 }
7317
7318 return bFrameAvailable;
7319 }
7320
7321 /*FUNCTION**********************************************************************
7322 *
7323 * Function Name : Netc_Eth_Ip_ReadFrame
7324 * implements Netc_Eth_Ip_ReadFrame_Activity
7325 *END**************************************************************************/
7326 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ReadFrame(uint8 ctrlIndex,
7327 uint8 ring,
7328 Netc_Eth_Ip_BufferType *buff,
7329 Netc_Eth_Ip_RxInfoType *info)
7330 {
7331 const Netc_Eth_Ip_RxBDRType *rxBDR;
7332
7333 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7334 uint32 CurrLowTime = 0U;
7335 uint32 CurrHighTime = 0U;
7336 uint32 rxIndex = 0;
7337 uint64 nanoseconds = 0U;
7338 #ifdef NETC_ETH_0_USED
7339 #if (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT)
7340
7341 uint8 tagBytes[NETC_ETH_IP_RX_CUSTOM_TAG_NUM_BYTES] = { 0U };
7342 #endif /*STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT*/
7343 #endif /* NETC_ETH_0_USED */
7344 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
7345 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
7346 uint32 HostReason;
7347
7348 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7349 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7350 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
7351 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR);
7352 DevAssert(buff != NULL_PTR);
7353 #endif
7354 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
7355 Std_ReturnType CacheStatus = E_NOT_OK;
7356 #endif
7357 /* Get the current descriptor corresponding to the buff pointer (by looping through the descriptors) */
7358 rxBDR = Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring];
7359 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7360 rxIndex = Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring];
7361 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
7362 if (NETC_ETH_IP_RXBD_READY_MASK != (rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_READY_MASK))
7363 {
7364 status = NETC_ETH_IP_STATUS_RX_QUEUE_EMPTY;
7365 }
7366 else
7367 {
7368 /* Store information about received frame. */
7369 if (NULL_PTR != info)
7370 {
7371 info->L4cksum = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_L4_FLAG_MASK) > 0U) ? TRUE : FALSE;
7372 info->L3cksum = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_L3_FLAG_MASK) > 0U) ? TRUE : FALSE;
7373 info->finalDes = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_FINAL_MASK) > 0U) ? TRUE : FALSE;
7374 info->timestampReceived = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_TIMESTAMP_FLAG_MASK) > 0U) ? TRUE : FALSE;
7375 info->vlanHeaderAvl = ((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_VLAN_HEAD_FLAG_MASK) > 0U) ? TRUE : FALSE;
7376 #ifdef MCAL_ENABLE_FAULT_INJECTION
7377 MCAL_FAULT_INJECTION_POINT(ETH_CHANGE_BUFFER_LENGTH_FIP_1);
7378 #endif
7379 if (rxBDR->configRxBD[2U] > Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring])
7380 {
7381 info->pktLen = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring] & NETC_ETH_IP_RXBD_LENGTH_MASK);
7382 }
7383 else
7384 {
7385 info->pktLen = (uint16)(rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_LENGTH_MASK);
7386 }
7387 info->rxStatus = (Netc_Eth_Ip_RxStatusType)((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_ERROR_MASK) >> NETC_ETH_IP_RXBD_ERROR_SHIFT);
7388 info->hostReason = (Netc_Eth_Ip_HostReasonType)((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_HOST_REASON_MASK) >> NETC_ETH_IP_RXBD_HOST_REASON_SHIFT);
7389 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
7390 info->VlanInfo.ProtocolIdentifier = (Netc_Eth_Ip_VlanProtocolIdentifierType)(rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_TPID_MASK);
7391 info->VlanInfo.PriorityCodePoint = (uint8)((rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_PCP_MASK) >> NETC_ETH_IP_RXBD_PCP_SHIFT);
7392 info->VlanInfo.DropIndicator = (((uint8)((rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_DEI_MASK) >> NETC_ETH_IP_RXBD_DEI_SHIFT) == 1U) ?
7393 TRUE : FALSE);
7394 info->VlanInfo.VlanIdentifier = (uint16)((rxBDR->configRxBD[2U] & NETC_ETH_IP_RXBD_VID_MASK) >> NETC_ETH_IP_RXBD_VID_SHIFT);
7395 #endif
7396 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7397 /* Read the low register then immediately the high register to get a synchronised 64-bit time value in nanoseconds */
7398 CurrLowTime = netcSIsBase[0U]->SICTR0;
7399 CurrHighTime = netcSIsBase[0U]->SICTR1;
7400 #endif
7401 }
7402
7403 if (NETC_ETH_RX_NO_RECEIVE_ERR == (Netc_Eth_Ip_RxStatusType)((rxBDR->configRxBD[3U] & NETC_ETH_IP_RXBD_ERROR_MASK) >> 16U))
7404 {
7405 HostReason = ((rxBDR->configRxBD[3U] >> NETC_ETH_IP_HOSTREASON_WB_SHIFT) & NETC_ETH_IP_HOSTREASON_WB_MASK);
7406
7407 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON==NETC_ETH_IP_CUSTOM_TAG_SUPPORT))
7408 Netc_Eth_Ip_ReadFrame_CustomizedTPID(ctrlIndex, ring, tagBytes, HostReason);
7409 #endif /* defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON==NETC_ETH_IP_CUSTOM_TAG_SUPPORT) */
7410
7411 if ((NETC_ETH_IP_HOSTREASON_REGULAR_FRAME == HostReason) || (NETC_ETH_IP_HOSTREASON_SW_PTP == HostReason))
7412 {
7413
7414 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
7415 /* Mark the cache lines as invalid in order to get the new data from data buffers from memory. */
7416 CacheStatus = Cache_Ip_Invalidate(CacheType, CACHE_IP_DATA);
7417 if (E_NOT_OK == CacheStatus)
7418 {
7419 status = NETC_ETH_IP_STATUS_CACHE_ERROR;
7420 }
7421 else
7422 {
7423 #endif
7424 Netc_Eth_Ip_ReadFrame_ReturnBufferDetails(ctrlIndex, ring, buff);
7425
7426 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7427 if(CurrLowTime < rxBDR->extendConfigRxBD[0U])
7428 {
7429 CurrHighTime--;
7430 }
7431
7432 if (NULL_PTR != info)
7433 {
7434 nanoseconds = (uint64)(rxBDR->extendConfigRxBD[0U]) | (uint64)(((uint64)(CurrHighTime)) << 32U);
7435 info->PacketTimestamp.nanoseconds = NETC_ETH_IP_GET_NANOSECONDS(nanoseconds);
7436 info->PacketTimestamp.seconds = (uint32) (NETC_ETH_IP_NANO_TO_SECONDS(nanoseconds) & NETC_ETH_IP_SECONDS_LOW_MASK_U64);
7437 info->PacketTimestamp.secondsHi = (uint16) ((NETC_ETH_IP_NANO_TO_SECONDS(nanoseconds) >> 32U) & 0xFFFFU);
7438
7439 }
7440
7441 if (NETC_ETH_IP_HOSTREASON_SW_PTP == HostReason)
7442 {
7443 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
7444 exection before the previous else if condition is completed. */
7445 MCAL_INSTRUCTION_SYNC_BARRIER();
7446 MCAL_DATA_SYNC_BARRIER();
7447 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].RingIdx = ring;
7448 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].ReceivedDataPtr = buff->data;
7449 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].SourcePort = (uint8)(rxBDR->configRxBD[1U] & NETC_ETH_IP_RXBD_SRC_PORT_MASK);
7450
7451 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampValue.nanosecondsL = rxBDR->extendConfigRxBD[0U];
7452 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampValue.nanosecondsH = CurrHighTime;
7453
7454 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
7455 Netc_Eth_Ip_RxTimestampID = (Netc_Eth_Ip_RxTimestampID % (uint32)0xFFFFU) + (uint32)1U;
7456 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampID = Netc_Eth_Ip_RxTimestampID;
7457 Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][ring][rxIndex].TimestampValueInvalidForSwt = (boolean)FALSE;
7458 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
7459 }
7460 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
7461
7462 #if (STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT)
7463 }
7464 #endif /* STD_ON == NETC_ETH_IP_HAS_CACHE_MANAGEMENT */
7465 }
7466
7467 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF))
7468 else if(NETC_ETH_IP_HOSTREASON_TIMESTAMP == HostReason)
7469 {
7470 Netc_Eth_Ip_HostReasonTimeStamp(ctrlIndex, ring, &status, CurrLowTime);
7471 }
7472 #endif /* defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) */
7473 else
7474 {
7475 status = NETC_ETH_IP_STATUS_HOSTREASON_UNKNOWN;
7476 }
7477
7478 #if(defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT))
7479 /* Add custom Rx tag/header */
7480 Netc_Eth_Ip_ReadFrame_AddCustomRxTagHeader(ctrlIndex, ring, tagBytes, buff);
7481 info->pktLen += NETC_ETH_IP_RX_CUSTOM_TAG_NUM_BYTES;
7482 #endif /* defined(NETC_ETH_0_USED) && (STD_ON == NETC_ETH_IP_EXTENDED_BUFF) && (STD_ON == NETC_ETH_IP_CUSTOM_TAG_SUPPORT) */
7483 }
7484 else
7485 {
7486 status = NETC_ETH_IP_STATUS_ERROR;
7487 }
7488
7489 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
7490 /* Go to the next index. */
7491 Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring] = (Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring] + 1U) % \
7492 Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ring];
7493
7494 /* Increment the pointer to the current descriptor. */
7495 Netc_Eth_Ip_apxState[ctrlIndex]->RxCurrentDesc[ring] = (Netc_Eth_Ip_RxBDRType *)((uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ring]) + \
7496 (((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->rxCurrentIndex[ring]) * ((uint32)(sizeof(Netc_Eth_Ip_RxBDRType)))));
7497 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20();
7498
7499 }
7500
7501 return status;
7502 }
7503
7504 /*FUNCTION**********************************************************************
7505 *
7506 * Function Name : Netc_Eth_Ip_ProvideRxBuff
7507 * implements Netc_Eth_Ip_ProvideRxBuff_Activity
7508 *END**************************************************************************/
7509 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ProvideRxBuff(uint8 ctrlIndex,
7510 uint8 ring,
7511 const Netc_Eth_Ip_BufferType *buff)
7512 {
7513 uint16 CurrentConsumerIndex;
7514 Netc_Eth_Ip_RxBDRType *RxBDR;
7515 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7516 uint32 bufferIndex;
7517 #endif
7518
7519 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7520 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7521 DevAssert(Netc_Eth_Ip_apxState[ctrlIndex] != NULL_PTR);
7522 DevAssert(ring < Netc_Eth_Ip_apxState[ctrlIndex]->NumberOfRxBDR);
7523
7524 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7525 if (Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
7526 {
7527 DevAssert(buff != NULL_PTR);
7528 }
7529 #endif /* (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS) */
7530
7531 #endif /* (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT) */
7532
7533 CurrentConsumerIndex = Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ring];
7534 RxBDR = (Netc_Eth_Ip_RxBDRType *)((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxRingDescAddr[ring] + (((uint32)CurrentConsumerIndex) * ((uint32)(sizeof(Netc_Eth_Ip_RxBDRType)))));
7535
7536 /* Configure descriptor by setting the address of data buffer and clear the rest of it. */
7537 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7538 bufferIndex = ring * FEATURE_NETC_RX_BDR_COUNT + CurrentConsumerIndex;
7539
7540 /* In case the current controller has Internal Buffer Management for reception, restore the data buffer */
7541 if (!Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[ctrlIndex])
7542 {
7543 #endif
7544 RxBDR->configRxBD[0U] = ((uint32)Netc_Eth_Ip_apxState[ctrlIndex]->FirstRxDataBufferAddr[ring] + \
7545 (uint32)(CurrentConsumerIndex * Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffMaxLenAddr[ring]));
7546 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7547 }
7548 else
7549 {
7550 Netc_Eth_Ip_apxState[ctrlIndex]->RxDataBuffAddr[bufferIndex] = (uint32)buff->data;
7551 RxBDR->configRxBD[0U] = (uint32)buff->data;
7552 }
7553 #else
7554 /* Avoid compiler warning */
7555 (void)buff;
7556 #endif
7557
7558 RxBDR->configRxBD[1U] = 0U;
7559 RxBDR->configRxBD[2U] = 0U;
7560 RxBDR->configRxBD[3U] = 0U;
7561 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7562 RxBDR->extendConfigRxBD[0U] = 0U;
7563 RxBDR->extendConfigRxBD[1U] = 0U;
7564 RxBDR->extendConfigRxBD[2U] = 0U;
7565 RxBDR->extendConfigRxBD[3U] = 0U;
7566 #endif
7567 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28();
7568 /* Update consumer index. */
7569 Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ring] = (CurrentConsumerIndex + 1U) % \
7570 Netc_Eth_Ip_apxState[ctrlIndex]->RxRingSize[ring];
7571 netcSIsBase[ctrlIndex]->BDR_NUM[ring].RBCIR = (uint32)(Netc_Eth_Ip_apxState[ctrlIndex]->LogicRxConsumerIndex[ring]);
7572 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28();
7573
7574
7575 return NETC_ETH_IP_STATUS_SUCCESS;
7576 }
7577
7578 /*FUNCTION**********************************************************************
7579 *
7580 * Function Name : Netc_Eth_Ip_ProvideMultipleRxBuff
7581 * implements Netc_Eth_Ip_ProvideMultipleRxBuff_Activity
7582 *END**************************************************************************/
7583 void Netc_Eth_Ip_ProvideMultipleRxBuff(const uint8 CtrlIndex,
7584 const uint8 Ring,
7585 uint8* BuffList[],
7586 uint16* BuffListSize)
7587 {
7588 uint16 ConsumerIndex = 0U;
7589 uint16 LastRxConsumerRead = 0U;
7590 volatile Netc_Eth_Ip_RxBDRType *RxBDR;
7591 uint16 BuffListIndex = 0U;
7592
7593 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7594 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
7595 exection before the previous else if condition is completed. */
7596 MCAL_INSTRUCTION_SYNC_BARRIER();
7597 MCAL_DATA_SYNC_BARRIER();
7598 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7599 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
7600 DevAssert(Ring < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfRxBDR);
7601 DevAssert(BuffListSize != NULL_PTR);
7602 DevAssert(*BuffListSize > 1U);
7603 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7604 if (Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[CtrlIndex])
7605 {
7606 DevAssert(BuffList != NULL_PTR);
7607 }
7608 #endif
7609 #endif
7610
7611 ConsumerIndex = Netc_Eth_Ip_apxState[CtrlIndex]->LogicRxConsumerIndex[Ring];
7612 LastRxConsumerRead = Netc_Eth_Ip_apxState[CtrlIndex]->rxCurrentIndex[Ring];
7613 do
7614 {
7615 RxBDR = (Netc_Eth_Ip_RxBDRType *)((uint32)(Netc_Eth_Ip_apxState[CtrlIndex]->FirstRxRingDescAddr[Ring]) + ((uint32)ConsumerIndex * ((uint32)(sizeof(Netc_Eth_Ip_RxBDRType)))));
7616
7617 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7618 /* In case the current controller has Internal Buffer Management for reception */
7619 if (Netc_Eth_Ip_ControllerHasExternalRxBufferManagement[CtrlIndex])
7620 {
7621 RxBDR->configRxBD[0U] = (uint32)BuffList[BuffListIndex];
7622 }
7623 else
7624 {
7625 #else
7626 (void)BuffList;
7627 #endif
7628 RxBDR->configRxBD[0U] = ((uint32)Netc_Eth_Ip_apxState[CtrlIndex]->FirstRxDataBufferAddr[Ring] + \
7629 (ConsumerIndex * (uint32)Netc_Eth_Ip_apxState[CtrlIndex]->RxDataBuffMaxLenAddr[Ring]));
7630
7631 #if (STD_ON == NETC_ETH_IP_HAS_EXTERNAL_RX_BUFFERS)
7632 }
7633 #endif
7634 RxBDR->configRxBD[1U] = 0U;
7635 RxBDR->configRxBD[2U] = 0U;
7636 RxBDR->configRxBD[3U] = 0U;
7637
7638 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7639 RxBDR->extendConfigRxBD[0U] = 0U;
7640 RxBDR->extendConfigRxBD[1U] = 0U;
7641 RxBDR->extendConfigRxBD[2U] = 0U;
7642 RxBDR->extendConfigRxBD[3U] = 0U;
7643 #endif
7644 ConsumerIndex = (ConsumerIndex + (uint16)1U) % Netc_Eth_Ip_apxState[CtrlIndex]->RxRingSize[Ring];
7645 /* Go to the next buffer */
7646 BuffListIndex++;
7647 } while((ConsumerIndex != LastRxConsumerRead) && (BuffListIndex < *BuffListSize));
7648
7649 /* Return how many descriptors have been restored. */
7650 *BuffListSize = BuffListIndex;
7651
7652 /* Update consumer index. */
7653
7654 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
7655 exection before the previous else if condition is completed. */
7656 MCAL_INSTRUCTION_SYNC_BARRIER();
7657 MCAL_DATA_SYNC_BARRIER();
7658 Netc_Eth_Ip_apxState[CtrlIndex]->LogicRxConsumerIndex[Ring] = (uint16)ConsumerIndex;
7659 netcSIsBase[CtrlIndex]->BDR_NUM[Ring].RBCIR = ConsumerIndex;
7660 }
7661 /*FUNCTION**********************************************************************
7662 *
7663 * Function Name : Netc_Eth_Ip_GetPowerState
7664 * implements Netc_Eth_Ip_GetPowerState_Activity
7665 *END**************************************************************************/
7666 Netc_Eth_Ip_PowerStateType Netc_Eth_Ip_GetPowerState(uint8 CtrlIndex)
7667 {
7668 Netc_Eth_Ip_PowerStateType status = NETC_ETH_STATE_ACTIVE;
7669
7670 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7671 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7672 DevAssert(NULL_PTR != netcSIsBase[CtrlIndex]);
7673 #endif
7674
7675 if( 0U == (netcSIsBase[CtrlIndex]->SIMR & NETC_F3_SI0_SIMR_EN_MASK))
7676 {
7677 status = NETC_ETH_STATE_INACTIVE;
7678 }
7679 return status;
7680 }
7681
7682 /*FUNCTION**********************************************************************
7683 *
7684 * Function Name : Netc_Eth_Ip_AddMulticastDstAddrToHashFilter
7685 * implements Netc_Eth_Ip_AddMulticastDstAddrToHashFilter_Activity
7686 *END**************************************************************************/
7687 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddMulticastDstAddrToHashFilter(const uint8 CtrlIndex, \
7688 const uint8 *MacAddr)
7689 {
7690 uint8 HashValue;
7691 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
7692
7693 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7694 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7695 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
7696 #endif
7697
7698 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
7699 {
7700 HashValue = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
7701
7702 /* Add MAC entry in the software table. */
7703 Status = Netc_Eth_Ip_AddMACFilterEntry(CtrlIndex, HashValue, MacAddr);
7704
7705 if(NETC_ETH_IP_STATUS_SUCCESS == Status)
7706 {
7707 /* 64 entries in table, the 5th bit of the HashValue selects between registers used. */
7708 if(0U != ((uint32)HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER))
7709 {
7710 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
7711 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR1 |= (uint32)(1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
7712 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
7713
7714 }
7715 else
7716 {
7717 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
7718 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR0 |= (uint32)(1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
7719 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09();
7720
7721 }
7722 }
7723 }
7724 else
7725 {
7726 uint16 PsiRspMessage;
7727 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_ADD_RX_MAC_ADDR_FILTER, MacAddr, &PsiRspMessage);
7728 }
7729
7730 return Status;
7731 }
7732
7733 /*FUNCTION**********************************************************************
7734 *
7735 * Function Name : Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter
7736 * implements Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter_Activity
7737 *END**************************************************************************/
7738 Netc_Eth_Ip_StatusType Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter(const uint8 CtrlIndex, \
7739 const uint8 *MacAddr)
7740 {
7741 uint8 HashValue;
7742 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
7743
7744 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7745 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7746 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
7747 #endif
7748
7749 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
7750 {
7751 HashValue = Netc_Eth_Ip_ComputeMACHashValue(MacAddr);
7752
7753 Status = Netc_Eth_Ip_DeleteMACFilterEntry(CtrlIndex, HashValue, MacAddr);
7754
7755 if(NETC_ETH_IP_STATUS_DELETE_MAC_ADDR == Status)
7756 {
7757 /* 64 entries in table, the 5th bit of the HashValue selects between registers used. */
7758 if((HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER) != (uint8)0U)
7759 {
7760 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
7761 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR1 &= ~(uint32)(1U << ((uint32)HashValue & NETC_ETH_IP_HASH_VALUE));
7762 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
7763
7764 }
7765 else
7766 {
7767 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
7768 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR0 &= ~(uint32)(1U << ((uint32)HashValue & NETC_ETH_IP_HASH_VALUE));
7769 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10();
7770 }
7771
7772 /*Mark the status variable as STATUS_SUCCESS, after hash deletion, since IPW expects it */
7773 Status = NETC_ETH_IP_STATUS_SUCCESS;
7774 }
7775 }
7776 else
7777 {
7778 uint16 PsiRspMessage;
7779 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_DELETE_RX_MAC_ADDR_FILTER, MacAddr, &PsiRspMessage);
7780 }
7781
7782 return Status;
7783 }
7784
7785 /*FUNCTION**********************************************************************
7786 *
7787 * Function Name : Netc_Eth_Ip_SetMulticastForwardAll
7788 * implements Netc_Eth_Ip_SetMulticastForwardAll_Activity
7789 *END**************************************************************************/
7790 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetMulticastForwardAll(const uint8 CtrlIndex, const boolean EnableMulticast)
7791 {
7792 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
7793
7794 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7795 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7796 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
7797 #endif
7798
7799 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
7800 {
7801 if(EnableMulticast)
7802 {
7803 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
7804 /* Enable MAC multicast promiscuous mode. */
7805 IP_NETC__ENETC0_BASE->PSIPMMR |= ((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
7806 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
7807 }
7808 else
7809 {
7810 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
7811 /* Disable MAC multicast promiscuous mode. */
7812 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
7813 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11();
7814 }
7815 }
7816 else
7817 {
7818 uint16 PsiRspMessage;
7819 if(EnableMulticast)
7820 {
7821 /* Enable MAC multicast promiscuous mode. */
7822 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_ENABLE_MULTICAST, NULL_PTR, &PsiRspMessage);
7823 }
7824 else
7825 {
7826 /* Disable MAC multicast promiscuous mode. */
7827 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_DISABLE_MULTICAST, NULL_PTR, &PsiRspMessage);
7828 }
7829 }
7830
7831 return Status;
7832 }
7833
7834 /*FUNCTION**********************************************************************
7835 *
7836 * Function Name : Netc_Eth_Ip_CloseMulticastReceiving
7837 * implements Netc_Eth_Ip_CloseMulticastReceiving_Activity
7838 *END**************************************************************************/
7839 Netc_Eth_Ip_StatusType Netc_Eth_Ip_CloseMulticastReceiving(const uint8 CtrlIndex)
7840 {
7841 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_SUCCESS;
7842
7843 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7844 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7845 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
7846 #endif
7847
7848 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType)
7849 {
7850 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12();
7851 /* Disable MAC multicast promiscuous mode. */
7852 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
7853
7854 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR1 = 0x0U;
7855 IP_NETC__ENETC0_BASE->NUM_SI[CtrlIndex].PSIMMHFR0 = 0x0U;
7856
7857
7858 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12();
7859
7860 }
7861 else
7862 {
7863 uint16 PsiRspMessage;
7864 /* Disable MAC multicast promiscuous mode. */
7865 Status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_CLOSE_FILTER, NULL_PTR, &PsiRspMessage);
7866 }
7867
7868 return Status;
7869 }
7870
7871 /*FUNCTION**********************************************************************
7872 *
7873 * Function Name : Netc_Eth_Ip_SetTxCoalescingThresholds
7874 * implements Netc_Eth_Ip_SetTxCoalescingThresholds_Activity
7875 *END**************************************************************************/
7876 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetTxCoalescingThresholds(uint8 CtrlIdx, uint8 RingIdx, uint16 PacketsThreshold, uint32 TimerThreshold)
7877 {
7878
7879 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7880 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7881 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIdx]);
7882 #endif
7883 boolean TxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[CtrlIdx]->TxTimerThreshold[RingIdx] != 0U) &&
7884 (Netc_Eth_Ip_apxState[CtrlIdx]->TxPacketsThreshold[RingIdx] != 0U)) ? TRUE : FALSE ;
7885
7886 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
7887 uint8 HwValueOfPackets = 0U;
7888
7889 if (TxCoalescingIsrEnabled)
7890 {
7891 if (PacketsThreshold < Netc_Eth_Ip_apxState[CtrlIdx]->TxRingSize[RingIdx])
7892 {
7893 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05();
7894 /* First disable the Coalescing ISR AND clear the previous values. */
7895 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICEN_MASK;
7896 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR1 = 0U; /* &= ~NETC_F3_SI0_TBICR1_ICTT_MASK; */
7897 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 &= ~NETC_F3_SI0_TBICR0_ICPT_MASK;
7898
7899 if (TimerThreshold != 0U)
7900 {
7901 /*If timer threshold is used it should be set when TBaICR0[ICEN]=0 to avoid missing a "firstpacket" transmitted condition which starts the timer.*/
7902 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR1 |= NETC_F3_SI0_TBICR1_ICTT(TimerThreshold);
7903 Netc_Eth_Ip_apxState[CtrlIdx]->TxTimerThreshold[RingIdx] = TimerThreshold;
7904 }
7905
7906 if (PacketsThreshold != 0U)
7907 {
7908 HwValueOfPackets = Netc_Eth_Ip_CoalescingTxPacketsConversion(PacketsThreshold);
7909 /*If packet threshold is used it should be set when TBaICR0[ICEN] is set */
7910 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 |= (NETC_F3_SI0_TBICR0_ICEN_MASK | NETC_F3_SI0_TBICR0_ICPT(HwValueOfPackets));
7911 Netc_Eth_Ip_apxState[CtrlIdx]->TxPacketsThreshold[RingIdx] = HwValueOfPackets;
7912 }
7913
7914 /* Case when the ICEN bit is not enabled when Timer Threshold is set */
7915 if ((PacketsThreshold == 0U) && (TimerThreshold != 0U))
7916 {
7917 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].TBICR0 |= NETC_F3_SI0_TBICR0_ICEN_MASK;
7918 }
7919 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05();
7920
7921 Status = NETC_ETH_IP_STATUS_SUCCESS;
7922 }
7923 }
7924
7925 return Status;
7926 }
7927
7928 /*FUNCTION**********************************************************************
7929 *
7930 * Function Name : Netc_Eth_Ip_SetRxCoalescingThresholds
7931 * implements Netc_Eth_Ip_SetRxCoalescingThresholds_Activity
7932 *END**************************************************************************/
7933 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetRxCoalescingThresholds(uint8 CtrlIdx, uint8 RingIdx, uint16 PacketsThreshold, uint32 TimerThreshold)
7934 {
7935
7936 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7937 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7938 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIdx]);
7939 #endif
7940 boolean RxCoalescingIsrEnabled = ((Netc_Eth_Ip_apxState[CtrlIdx]->RxTimerThreshold[RingIdx] != 0U) &&
7941 (Netc_Eth_Ip_apxState[CtrlIdx]->RxPacketsThreshold[RingIdx] != 0U)) ? TRUE : FALSE ;
7942 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
7943
7944 if (RxCoalescingIsrEnabled)
7945 {
7946 if (PacketsThreshold <= Netc_Eth_Ip_apxState[CtrlIdx]->RxRingSize[RingIdx])
7947 {
7948 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04();
7949 /* First disable the Coalescing ISR AND clear the previous values. */
7950 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICEN_MASK;
7951 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR1 = 0U; /* &= ~NETC_F3_SI0_RBICR1_ICTT_MASK; Changed due to CWE violation*/
7952 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 &= ~NETC_F3_SI0_RBICR0_ICPT_MASK;
7953
7954 if (PacketsThreshold != 0U )
7955 {
7956 /*If timer threshold is used it should be set when RBaICR0[ICEN]=0 to avoid missing a "first packet" received condition which starts the timer.*/
7957 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 |= NETC_F3_SI0_RBICR0_ICPT(PacketsThreshold);
7958 Netc_Eth_Ip_apxState[CtrlIdx]->RxPacketsThreshold[RingIdx] = PacketsThreshold;
7959 }
7960
7961 if (TimerThreshold != 0U)
7962 {
7963 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR1 |= NETC_F3_SI0_RBICR1_ICTT(TimerThreshold);
7964 Netc_Eth_Ip_apxState[CtrlIdx]->RxTimerThreshold[RingIdx] = TimerThreshold;
7965 }
7966
7967 if ((PacketsThreshold != 0U)|| (TimerThreshold != 0U))
7968 {
7969 netcSIsBase[CtrlIdx]->BDR_NUM[RingIdx].RBICR0 |= NETC_F3_SI0_RBICR0_ICEN_MASK;
7970 }
7971 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04();
7972
7973 Status = NETC_ETH_IP_STATUS_SUCCESS;
7974 }
7975 }
7976
7977 return Status;
7978 }
7979
7980 #if (STD_ON == NETC_ETH_IP_EXTENDED_BUFF)
7981 #ifdef NETC_ETH_0_USED
7982 /*FUNCTION**********************************************************************
7983 *
7984 * Function Name : Netc_Eth_Ip_ManagementFrame
7985 * implements Netc_Eth_Ip_ManagementFrame_Activity
7986 *END**************************************************************************/
7987 Netc_Eth_Ip_StatusType Netc_Eth_Ip_ManagementFrame(const uint8 CtrlIdx, uint16 BuffIdx, uint8 SwitchIndex, uint8 PortIndex, boolean Enable)
7988 {
7989 uint16 CurrentIndex;
7990 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_UNSUPPORTED;
7991
7992 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
7993 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
7994 DevAssert(Netc_Eth_Ip_apxState[CtrlIdx] != NULL_PTR);
7995 #endif
7996
7997 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIdx]->SiType)
7998 {
7999 CurrentIndex = Netc_Eth_Ip_apxState[CtrlIdx]->LogicTxProducerIndex[0U];
8000
8001 if (Enable == TRUE)
8002 {
8003 if (Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].State == NETC_ETH_IP_TX_MGMT_FREE)
8004 {
8005 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].State = NETC_ETH_IP_TX_MGMT_PREPARED;
8006 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].CtrlIdx = CtrlIdx;
8007 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].TxBuffId = BuffIdx;
8008 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].SwitchIndex = SwitchIndex;
8009 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].PortIndex = PortIndex;
8010 Status = NETC_ETH_IP_STATUS_SUCCESS;
8011 }
8012 }
8013 else
8014 {
8015 if (Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].TxBuffId == BuffIdx)
8016 {
8017 Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR].State = NETC_ETH_IP_TX_MGMT_FREE;
8018 Status = NETC_ETH_IP_STATUS_SUCCESS;
8019 }
8020 }
8021 }
8022
8023 return Status;
8024 }
8025
8026 /*FUNCTION**********************************************************************
8027 *
8028 * Function Name : Netc_Eth_Ip_TimestampTxFrame
8029 * implements Netc_Eth_Ip_TimestampTxFrame_Activity
8030 *END**************************************************************************/
8031 Netc_Eth_Ip_StatusType Netc_Eth_Ip_TimestampTxFrame(const uint8 CtrlIdx, const uint16 BuffIdx, const boolean Enable)
8032 {
8033 uint16 CurrentIndex;
8034 volatile Netc_Eth_Ip_TxManagementInfoType *TxMgmtInfo;
8035 Netc_Eth_Ip_TxManagementStateType TxMgmtObjState;
8036 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
8037 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8038 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8039 DevAssert(Netc_Eth_Ip_apxState[CtrlIdx] != NULL_PTR);
8040 #endif
8041 if (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIdx]->SiType)
8042 {
8043 CurrentIndex = Netc_Eth_Ip_apxState[CtrlIdx]->LogicTxProducerIndex[0U];
8044 TxMgmtInfo = &Netc_Eth_Ip_TxManagementInfoBuff[0U][CurrentIndex / (uint16)NETC_ETH_IP_PRODUCER_INCR];
8045 TxMgmtObjState = TxMgmtInfo->State;
8046
8047 if (TxMgmtInfo->TxBuffId == BuffIdx)
8048 {
8049 if ((TxMgmtObjState == NETC_ETH_IP_TX_MGMT_PREPARED) || (TxMgmtObjState == NETC_ETH_IP_TX_MGMT_PREPARED_TIMESTAMP))
8050 {
8051 TxMgmtInfo->State = (Enable == TRUE) ? NETC_ETH_IP_TX_MGMT_PREPARED_TIMESTAMP : NETC_ETH_IP_TX_MGMT_PREPARED;
8052 Status = NETC_ETH_IP_STATUS_SUCCESS;
8053 }
8054 }
8055 }
8056
8057 return Status;
8058 }
8059
8060 /*FUNCTION**********************************************************************
8061 *
8062 * Function Name : Netc_Eth_Ip_GetTxTimestampInfo
8063 * implements Netc_Eth_Ip_GetTxTimestampInfo_Activity
8064 *END**************************************************************************/
8065 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxTimestampInfo(const uint8 CtrlIdx, \
8066 const uint32 BuffIdx, \
8067 Netc_Eth_Ip_TxManagementInfoType **MgmtInfo, \
8068 Netc_Eth_Ip_TxTimestampInfoType **TimestampInfo
8069 )
8070 {
8071 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
8072 uint32 BufferIdx;
8073 uint32 TsBufferIdx;
8074 *MgmtInfo = NULL_PTR;
8075 *TimestampInfo = NULL_PTR;
8076 uint16 tempBufferIdx;
8077 uint8 tempCtrlIdx;
8078
8079 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8080 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8081 #endif
8082
8083 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23();
8084
8085 /* Search for timestamps associated to the frame with BuffIdx */
8086 for(BufferIdx = 0U; BufferIdx < NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR / NETC_ETH_IP_PRODUCER_INCR; BufferIdx++)
8087 {
8088 tempBufferIdx = Netc_Eth_Ip_TxManagementInfoBuff[0U][BufferIdx].TxBuffId;
8089 tempCtrlIdx = Netc_Eth_Ip_TxManagementInfoBuff[0U][BufferIdx].CtrlIdx;
8090 if ((Netc_Eth_Ip_TxManagementInfoBuff[0U][BufferIdx].State != NETC_ETH_IP_TX_MGMT_FREE) && (BuffIdx == (uint32)tempBufferIdx) && (CtrlIdx == (uint32)tempCtrlIdx))
8091 {
8092 *MgmtInfo = (Netc_Eth_Ip_TxManagementInfoType *)&Netc_Eth_Ip_TxManagementInfoBuff[0U][BufferIdx];
8093 Status = NETC_ETH_IP_STATUS_SUCCESS;
8094
8095 if (Netc_Eth_Ip_TxManagementInfoBuff[0U][BufferIdx].State == NETC_ETH_IP_TX_MGMT_WAITING_TIMESTAMP)
8096 {
8097 for (TsBufferIdx = 0U; TsBufferIdx < NETC_ETH_0_TXBDR_0_MAX_NUM_OF_DESCR / NETC_ETH_IP_PRODUCER_INCR; TsBufferIdx++)
8098 {
8099 if (Netc_Eth_Ip_TxTimestampInfoBuff[0U][TsBufferIdx].TxTimeStampID == (*MgmtInfo)->TxTimeStampID)
8100 {
8101 (*MgmtInfo)->State = NETC_ETH_IP_TX_MGMT_READY;
8102 *TimestampInfo = (Netc_Eth_Ip_TxTimestampInfoType *)&Netc_Eth_Ip_TxTimestampInfoBuff[0U][TsBufferIdx];
8103 break;
8104 }
8105 }
8106 }
8107 break;
8108 }
8109 }
8110
8111 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23();
8112
8113 return Status;
8114 }
8115
8116 /*FUNCTION**********************************************************************
8117 *
8118 * Function Name : Netc_Eth_Ip_ReleaseUnusedTxBuff
8119 *END**************************************************************************/
8120 void Netc_Eth_Ip_ReleaseUnusedTxBuff(uint8 CtrlIndex, uint8 Ring)
8121 {
8122 uint32 CurrentProducerIdx;
8123
8124 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8125 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8126 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
8127 DevAssert(Ring < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfTxBDR);
8128 #endif
8129
8130 CurrentProducerIdx = Netc_Eth_Ip_apxState[CtrlIndex]->LogicTxProducerIndex[Ring];
8131
8132 /* When the development error is enabled we need to add a barrier first in order to avoid speculative
8133 exection before the previous else if condition is completed. */
8134 MCAL_INSTRUCTION_SYNC_BARRIER();
8135 MCAL_DATA_SYNC_BARRIER();
8136 Netc_Eth_Ip_apxState[CtrlIndex]->LockTxBuffDescr[Ring][CurrentProducerIdx] = FALSE;
8137 }
8138 #endif /* NETC_ETH_0_USED */
8139
8140 /*FUNCTION**********************************************************************
8141 *
8142 * Function Name : Netc_Eth_Ip_GetRxTimestampInfo
8143 * implements Netc_Eth_Ip_GetRxTimestampInfo_Activity
8144 *END**************************************************************************/
8145 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetRxTimestampInfo(const uint8 CtrlIdx, const uint8 *DataPtr, Netc_Eth_Ip_RxTimestampInfoType **RxTimestampInfo)
8146 {
8147 uint8 RingCounter;
8148 uint32 DescrCounter;
8149 uint32 LastRxTimestampID = (uint32)0U;
8150 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
8151
8152 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8153 DevAssert(CtrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8154 DevAssert(DataPtr != NULL_PTR);
8155 #endif
8156
8157 *RxTimestampInfo = NULL_PTR;
8158
8159 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24();
8160 for (RingCounter = 0U; RingCounter < Netc_Eth_Ip_apxState[CtrlIdx]->NumberOfRxBDR; RingCounter++)
8161 {
8162 for(DescrCounter = 0U; DescrCounter < NETC_ETH_IP_MAX_NUMBER_OF_RXDESCRIPTORS; DescrCounter++)
8163 {
8164 /* Pointer for searched data was found. */
8165 if (DataPtr == Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].ReceivedDataPtr)
8166 {
8167 if(RingCounter == Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].RingIdx)
8168 {
8169 /* Assure that current data is valid. */
8170 if((boolean)FALSE == Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampValueInvalidForSwt)
8171 {
8172 if(Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampID > LastRxTimestampID)
8173 {
8174 Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampValueInvalidForSwt = (boolean)TRUE;
8175 LastRxTimestampID = Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampID;
8176 *RxTimestampInfo = (Netc_Eth_Ip_RxTimestampInfoType *)&Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter];
8177 Status = NETC_ETH_IP_STATUS_SUCCESS;
8178 }
8179 else
8180 {
8181 /* Mark the rest of timestamps as invalid.
8182 This mechanism will helps not to read wrong timestamps for consecutives calls of function. */
8183 Netc_Eth_Ip_RxTimestampInfoBuff[CtrlIdx][RingCounter][DescrCounter].TimestampValueInvalidForSwt = (boolean)TRUE;
8184 }
8185 }
8186 }
8187 }
8188 }
8189 }
8190 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24();
8191
8192 return Status;
8193 }
8194
8195 #endif /* STD_ON == NETC_ETH_IP_EXTENDED_BUFF */
8196
8197 /*FUNCTION**********************************************************************
8198 *
8199 * Function Name : Netc_Eth_Ip_GetSysTime
8200 * implements Netc_Eth_Ip_GetSysTime_Activity
8201 *END**************************************************************************/
8202 void Netc_Eth_Ip_GetSysTime(uint8 ctrlIndex, Netc_Eth_Ip_TimeType *TimePtr)
8203 {
8204
8205 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8206 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]);
8207 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8208 DevAssert(NULL_PTR != TimePtr );
8209 #endif
8210
8211 Netc_Eth_Ip_GetCurrentTick(ctrlIndex, TimePtr);
8212 }
8213
8214 /*FUNCTION**********************************************************************
8215 *
8216 * Function Name : Netc_Eth_Ip_Deinit
8217 * implements Netc_Eth_Ip_Deinit_Activity
8218 *END**************************************************************************/
8219 Netc_Eth_Ip_StatusType Netc_Eth_Ip_Deinit(uint8 ctrlIndex)
8220 {
8221 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8222 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8223 #endif
8224
8225 uint32 StartTime;
8226 uint32 ElapsedTime;
8227 uint32 TimeoutTicks;
8228 Netc_Eth_Ip_StatusType Status = NETC_ETH_IP_STATUS_ERROR;
8229
8230 /*Check if the controller is VSI. Deinit is not supported for PSI*/
8231 if (NETC_ETH_IP_VIRTUAL_SI == Netc_Eth_Ip_apxState[ctrlIndex]->SiType)
8232 {
8233 /*Initiate function level reset*/
8234 netcVFBase[ctrlIndex]->PCI_CFC_PCIE_DEV_CTL = NETC_F1_PCI_HDR_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(1U);
8235
8236 /* Wait until VSI FLR is complete */
8237 Netc_Eth_Ip_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, NETC_ETH_IP_TIMEOUT_VALUE_US);
8238 do
8239 {
8240 if (NETC_F1_PCI_HDR_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(0U) == netcVFBase[ctrlIndex]->PCI_CFC_PCIE_DEV_CTL)
8241 {
8242 Status = NETC_ETH_IP_STATUS_SUCCESS;
8243 break;
8244 }
8245 else
8246 {
8247 Status = NETC_ETH_IP_STATUS_TIMEOUT;
8248 }
8249 }while(!Netc_Eth_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
8250
8251 /* Reset global state variable */
8252 Netc_Eth_Ip_apxState[ctrlIndex] = NULL_PTR;
8253 }
8254
8255 return Status;
8256 }
8257
8258
8259 /*FUNCTION**********************************************************************
8260 *
8261 * Function Name : Netc_Eth_Ip_PCIe_AER_Handler
8262 *
8263 *END**************************************************************************/
8264 void Netc_Eth_Ip_PCIe_AER_Handler(uint8 ctrlIndex)
8265 {
8266 uint8 i = 0U;
8267
8268 if (IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCIE_CFC_AER_ROOT_ERR_STAT != 0U)
8269 {
8270 IP_NETC__IERC_F0_PCI_HDR_TYPE0->PCIE_CFC_AER_ROOT_ERR_STAT = NETC_ETH_IP_AER_ROOT_CLEAR_STATUS_MASK;
8271 /* Error reporting for TIMER EMDIO SWITCH ENETC */
8272 for( i = 0U; i < FEATURE_NETC_NUMBER_OF_FUNC; i++)
8273 {
8274 /* At this point the status error bit is checked and cleared.
8275 The structure that contains information on the error Netc_Eth_Ip_ErrorStatus will be filled in */
8276 Netc_Eth_Ip_ProcessErrorStatusForInterruptForFunctions(ctrlIndex, i);
8277 }
8278
8279 /* Error reporting for VSIx */
8280 for (i = FEATURE_NETC_NUMBER_OF_FUNC; i < (FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS + FEATURE_NETC_NUMBER_OF_FUNC ); i++)
8281 {
8282 /* At this point the status error bit is checked and cleared.
8283 The structure that contains information on the error Netc_Eth_Ip_ErrorStatus will be filled in */
8284 Netc_Eth_Ip_ProcessErrorStatusForInterruptForVSIs(ctrlIndex, i);
8285 }
8286
8287 /* At this point the status error bit for PSI0 is checked and cleared.
8288 The structure that contains information on the error Netc_Eth_Ip_ErrorStatus will be filled in */
8289 Netc_Eth_Ip_ProcessErrorStatusForInterruptForPSI0(ctrlIndex);
8290
8291 if (Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerErrorReportingCallback != NULL_PTR)
8292 {
8293 Netc_Eth_Ip_apxState[ctrlIndex]->PcieAerErrorReportingCallback (ctrlIndex, (const Netc_Eth_Ip_PcieFunctionErrorsReported *)&Netc_Eth_Ip_ErrorStatus);
8294 }
8295 }
8296 }
8297
8298 /*FUNCTION**********************************************************************
8299 *
8300 * Function Name : Netc_Eth_Ip_EnableIngressPortFiltering
8301 * Description : Ethernet enables the ingress port filtering lookup function.
8302 * implements Netc_Eth_Ip_EnableIngressPortFiltering_Activity
8303 *END**************************************************************************/
8304 Std_ReturnType Netc_Eth_Ip_EnableIngressPortFiltering( const uint8 CtrlIndex, boolean Enable )
8305 {
8306 Std_ReturnType Status = E_OK;
8307 uint32 RegVal;
8308
8309 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8310 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
8311 #endif
8312
8313 (void)CtrlIndex;
8314
8315 /* Convert the value */
8316 RegVal = (Enable) ? (0x1UL) : (0x0UL);
8317
8318 /* write the PIPFCR[EN] bit */
8319 IP_NETC__ENETC0_PORT->PIPFCR = RegVal;
8320
8321 return Status;
8322 }
8323
8324 /* inline function for filling in Access Keye data in function Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff() */
8325 static inline Netc_Eth_Ip_StatusType FillInAccessKeyeData(const Netc_Eth_Ip_AccessMethodType accessMethod, const volatile uint32 *pAccessKey)
8326 {
8327 uint8 ItemIdx;
8328 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
8329
8330 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26();
8331 switch (accessMethod)
8332 {
8333 case NETC_ETH_ENTRY_ID_MATCH:
8334 /* fill in Entry_ID field */
8335 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = pAccessKey[0U];
8336 break;
8337 case NETC_ETH_EXACT_MATCH_KEY_ELEMENT_MATCH:
8338 /* Not Applicable for Ingress Port Filter table*/
8339 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
8340 break;
8341 case NETC_ETH_SEARCH_METHOD:
8342 /* fill in Resume_Entry_ID field */
8343 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ENTRYID_FIELD] = pAccessKey[0U];
8344 break;
8345 case NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH:
8346 /* fill in keye_data field */
8347 for (ItemIdx = 1U; ItemIdx <= NETC_ETH_IP_INGRESSPORTFILTERTABLE_KEYE_DATA_LEN; ItemIdx++)
8348 {
8349 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ItemIdx] = pAccessKey[ItemIdx - 1U];
8350 }
8351 break;
8352 default:
8353 /* Not Applicable for Ingress Port Filter table*/
8354 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
8355 break;
8356 }
8357 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26();
8358
8359 return status;
8360 }
8361
8362 /*FUNCTION**********************************************************************
8363 *
8364 * Function Name : Netc_Eth_Ip_DumpErrorCapture
8365 * Description : Function used for getting statistics over an error reported by the Event collector interrupt
8366 * Prerequisites: Allocate an array of Netc_Eth_Ip_ErrorCaptureRegisterInformation with a length equal to
8367 * NETC_ETH_IP_MAX_UNCORRECTABLE_ERROR_REPORTING_STATISTICS_LENGTH or
8368 * NETC_ETH_IP_MAX_CORRECTABLE_ERROR_REPORTING_STATISTICS_LENGTH or sum of them in case both uncorrectable and correctable errors are reported
8369 * for the function.
8370 * implements Netc_Eth_Ip_DumpErrorCapture_Activity
8371 *END**************************************************************************/
8372 void Netc_Eth_Ip_DumpErrorCapture ( const uint8 ctrlIdx,
8373 const Netc_Eth_Ip_PcieFunction function,
8374 uint8 *numberOfRegisters,
8375 uint8 siIndex,
8376 Netc_Eth_Ip_ErrorCaptureRegisterInformation* const Buffers[])
8377 {
8378 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8379 DevAssert(ctrlIdx < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8380 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIdx]);
8381 DevAssert(Netc_Eth_Ip_apxState[ctrlIdx]->SiType == NETC_ETH_IP_PHYSICAL_SI);
8382 DevAssert(numberOfRegisters != NULL_PTR);
8383 #endif
8384 volatile uint8 countRegisters = 0U;
8385
8386 switch (function)
8387 {
8388 case EMDIO:
8389 *numberOfRegisters = Netc_Eth_Ip_GetErrorStatisticsForEMDIO(ctrlIdx, Buffers);
8390 break;
8391
8392 case SWITCH:
8393 /* Return the value of the registers that have been written */
8394 *numberOfRegisters = Netc_Eth_Ip_GetErrorStatisticsForSWITCH(ctrlIdx, Buffers);
8395 break;
8396
8397 case TIMER:
8398 *numberOfRegisters = Netc_Eth_Ip_GetErrorStatisticsForTIMER(ctrlIdx, Buffers);
8399 break;
8400
8401 case ENETC:
8402
8403 *numberOfRegisters = Netc_Eth_Ip_GetErrorStatisticsForENETC(ctrlIdx, Buffers);
8404 break;
8405
8406 case PSI:
8407 case VSI:
8408 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8409 DevAssert(siIndex < 8U);
8410 #endif
8411 *numberOfRegisters = Netc_Eth_Ip_GetErrorStatisticsForSI(ctrlIdx, siIndex, Buffers);
8412 break;
8413
8414 default:
8415 *numberOfRegisters = countRegisters;
8416 break;
8417 }
8418 }
8419 /*FUNCTION**********************************************************************
8420 * Function Name : Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff
8421 * Description : Internal function for initializing the Ingress Port Filter Table Request Data Buffer.
8422 *
8423 *END**************************************************************************/
8424 static Netc_Eth_Ip_StatusType Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff( uint32 ActionsData,
8425 const volatile uint32 *pAccessKey,
8426 const Netc_Eth_Ip_IngressPortFilterCfgeDataType *pCfgeData,
8427 Netc_Eth_Ip_AccessMethodType accessMethod
8428 )
8429 {
8430 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
8431
8432 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
8433 /* ------initialize the table request data buffer------ */
8434 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD] = ActionsData; /* fill in Actions field */
8435
8436 /* initialize ACCESS_KEY */
8437 status = FillInAccessKeyeData(accessMethod, pAccessKey);
8438
8439 /* initialize CFGE_DATA. This portion is present only for commands which perform an update or add. */
8440 if (pCfgeData != NULL_PTR)
8441 {
8442
8443 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_INGRESSPORTFILTER_CFGE_CONFIG_FIELD] = (NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_IPV(pCfgeData->CfgeIpv) \
8444 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_OIPV(pCfgeData->CfgeOverrideIpv ? 1U : 0U) \
8445 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_DR(pCfgeData->CfgeDr) \
8446 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_ODR(pCfgeData->CfgeOverrideDr ? 1U : 0U) \
8447 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTFA(pCfgeData->CfgeFilterForwardingAction) \
8448 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_WOLTE(pCfgeData->CfgeWakeOnLanTriggerEnable ? 1U : 0U) \
8449 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTA(pCfgeData->CfgeFilterAction) \
8450 | NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_RPR(pCfgeData->CfgeRelativePrecedentResolution));
8451 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[NETC_ETH_IP_INGRESSPORTFILTER_CFGE_FLTATGT_FIELD] = pCfgeData->CfgeTargetForSelectedFilterAction;
8452
8453 }
8454 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
8455
8456 return status;
8457 }
8458
8459 /*FUNCTION**********************************************************************
8460 *
8461 * Function Name : Netc_Eth_Ip_AddIngressPortFilterTableEntry
8462 * Description : Ethernet adds Ingress Port Filter table entry function.
8463 * implements Netc_Eth_Ip_AddIngressPortFilterTableEntry_Activity
8464 *END**************************************************************************/
8465 Netc_Eth_Ip_StatusType Netc_Eth_Ip_AddIngressPortFilterTableEntry( uint8 CtrlIndex,
8466 uint32 *MatchedEntries,
8467 Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry
8468 )
8469 {
8470 Netc_Eth_Ip_StatusType status;
8471 uint32 ActionsData;
8472 uint8 ByteIdx;
8473 uint8 CfgeDataIdx;
8474 uint8 PayloadIdx;
8475
8476 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8477 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
8478 DevAssert(MatchedEntries != NULL_PTR);
8479 DevAssert(IngressPortFilterTableEntry != NULL_PTR);
8480 #endif
8481
8482 /* clear the variable MatchedEntries first */
8483 *MatchedEntries = 0U;
8484
8485 /* set STSEU and CFGEU flag */
8486 ActionsData = (NETC_ETH_IP_IPFTABLE_REQFMT_ACTIONS_FIELD_STSEU(1U) | NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_CFGEU(1U));
8487
8488 /* inialize KEYE_DATA */
8489 Netc_Eth_Ip_IPFKeyeData[0U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePrecedence;
8490 Netc_Eth_Ip_IPFKeyeData[2U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask) << NETC_ETH_IP_16BIT_SHIFT) \
8491 | IngressPortFilterTableEntry->IngressPortFilterkeyeData.keyeFrmAttributeFlags;
8492 Netc_Eth_Ip_IPFKeyeData[3U] = NETC_ETH_IP_IPFTABLE_KEYE_DATA_DSCPMASK(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask) \
8493 | NETC_ETH_IP_IPFTABLE_KEYE_DATA_DIFFSCP(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint);
8494 Netc_Eth_Ip_IPFKeyeData[4U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask) << NETC_ETH_IP_16BIT_SHIFT) \
8495 | (IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation << NETC_ETH_IP_8BIT_SHIFT); /* big endian for TCI */
8496 Netc_Eth_Ip_IPFKeyeData[5U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[1U]) << NETC_ETH_IP_8BIT_SHIFT) \
8497 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[2U]) << NETC_ETH_IP_16BIT_SHIFT) \
8498 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[3U]) << NETC_ETH_IP_24BIT_SHIFT);
8499 Netc_Eth_Ip_IPFKeyeData[6U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[4U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[5U]) << NETC_ETH_IP_8BIT_SHIFT) \
8500 | (((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[1U]) << NETC_ETH_IP_8BIT_SHIFT)) << NETC_ETH_IP_16BIT_SHIFT);
8501 Netc_Eth_Ip_IPFKeyeData[7U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[2U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[3U]) << NETC_ETH_IP_8BIT_SHIFT) \
8502 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[4U]) << NETC_ETH_IP_16BIT_SHIFT) \
8503 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[5U]) << NETC_ETH_IP_24BIT_SHIFT);
8504 Netc_Eth_Ip_IPFKeyeData[8U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[1U]) << NETC_ETH_IP_8BIT_SHIFT) \
8505 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[2U]) << NETC_ETH_IP_16BIT_SHIFT) \
8506 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[3U]) << NETC_ETH_IP_24BIT_SHIFT);
8507 Netc_Eth_Ip_IPFKeyeData[9U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[4U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[5U]) << NETC_ETH_IP_8BIT_SHIFT) \
8508 | (((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[0U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[1U]) << NETC_ETH_IP_8BIT_SHIFT)) << NETC_ETH_IP_16BIT_SHIFT);
8509 Netc_Eth_Ip_IPFKeyeData[10U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[2U]) | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[3U]) << NETC_ETH_IP_8BIT_SHIFT) \
8510 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[4U]) << NETC_ETH_IP_16BIT_SHIFT) \
8511 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[5U]) << NETC_ETH_IP_24BIT_SHIFT);
8512 Netc_Eth_Ip_IPFKeyeData[11U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask) << NETC_ETH_IP_16BIT_SHIFT) \
8513 | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation;
8514 Netc_Eth_Ip_IPFKeyeData[12U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask) << NETC_ETH_IP_16BIT_SHIFT) \
8515 | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask;
8516 Netc_Eth_Ip_IPFKeyeData[13U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocolMask) << NETC_ETH_IP_8BIT_SHIFT) | (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocol);
8517 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8518 {
8519 Netc_Eth_Ip_IPFKeyeData[ByteIdx + 17U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddress[ByteIdx];
8520 }
8521 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8522 {
8523 Netc_Eth_Ip_IPFKeyeData[ByteIdx + 23U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddressMask[ByteIdx];
8524 }
8525 Netc_Eth_Ip_IPFKeyeData[27U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePortMask) << NETC_ETH_IP_16BIT_SHIFT) | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePort;
8526 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8527 {
8528 Netc_Eth_Ip_IPFKeyeData[ByteIdx + 29U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddress[ByteIdx];
8529 }
8530 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8531 {
8532 Netc_Eth_Ip_IPFKeyeData[ByteIdx + 35U] = IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[ByteIdx];
8533 }
8534 Netc_Eth_Ip_IPFKeyeData[39U] = ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPortMask) << NETC_ETH_IP_16BIT_SHIFT) | IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPort;
8535
8536 CfgeDataIdx = 0U;
8537 PayloadIdx = 0U;
8538 for (ByteIdx = 0U; ByteIdx < 12U; ByteIdx++)
8539 {
8540 Netc_Eth_Ip_IPFKeyeData[CfgeDataIdx + 41U] = (uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx]) \
8541 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx]) << NETC_ETH_IP_8BIT_SHIFT) \
8542 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx + 1U]) << NETC_ETH_IP_16BIT_SHIFT) \
8543 | ((uint32)(IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx + 1U]) << NETC_ETH_IP_24BIT_SHIFT);
8544 PayloadIdx++;
8545 CfgeDataIdx++;
8546 }
8547
8548 /* only supports "NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH" access method */
8549 status = Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff(ActionsData, &Netc_Eth_Ip_IPFKeyeData[0U], &(IngressPortFilterTableEntry->IngressPortFilterCfgeData), NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH);
8550 if (NETC_ETH_IP_STATUS_SUCCESS == status)
8551 {
8552 /* fill in operation data for config field of Request Header*/
8553 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
8554 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
8555 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_PORT_FILTER_TABLE_ID;
8556 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH; /* for Adding an ingress port filter entry, the Access Method should only be NETC_ETH_TERNARY_MATCH_KEY_ELEMENT_MATCH */
8557 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_ADD_FOLLOWEDBY_QUERY_CMD; /* can only use "Add followed by a Query" command to add an ingress port filter table entry */
8558 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
8559 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_RSPBUFFER_LEN);
8560
8561 /* send command */
8562 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
8563 #if defined(ERR_IPV_NETC_051243)
8564 #if (STD_ON == ERR_IPV_NETC_051243)
8565 /* Error code 0x8A is not a real error. check it on Errata. */
8566 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
8567 {
8568 #endif
8569 #else
8570 if (status == NETC_ETH_IP_STATUS_SUCCESS)
8571 {
8572 #endif
8573 status = NETC_ETH_IP_STATUS_SUCCESS;
8574 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
8575 /* It's an "Add followed by a Query", but even if this entry is added successfully, the MatchedEntry is still 0. So here we can not check the MatchedEntries parameter. */
8576 IngressPortFilterTableEntry->IngressPortFilterEntryID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U]; /* Get the Entry_ID from response data buffer */
8577 }
8578 }
8579 else
8580 {
8581 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
8582 }
8583
8584 return status;
8585 }
8586
8587 /* inline function for filling in part of keye data in function FillInIPFTableEntryData() */
8588 static inline void Netc_Eth_Ip_FillInKeyeDataForIPF(Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry)
8589 {
8590 uint8 ByteIdx;
8591 uint8 PayloadIdx;
8592 uint8 CfgeDataIdx;
8593
8594 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
8595 for (ByteIdx = 2U; ByteIdx < 6U; ByteIdx++)
8596 {
8597 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[12U] & NETC_ETH_IP_0XFF_MASK);
8598 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[12U] >>= NETC_ETH_IP_8BIT_SHIFT;
8599 }
8600 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
8601
8602 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformation = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[13U] & NETC_ETH_IP_0XFFFF_MASK);
8603 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeInnerVLANTagControlInformationMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[13U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
8604 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherType = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[14U] & NETC_ETH_IP_0XFFFF_MASK);
8605 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeEtherTypeMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[14U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
8606 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocol = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[15U] & NETC_ETH_IP_0XFF_MASK);
8607 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPProtocolMask = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[15U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8608 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8609 {
8610 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddress[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 19U];
8611 }
8612 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8613 {
8614 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPSourceAddressMask[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 25U];
8615 }
8616 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePort = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[29U] & NETC_ETH_IP_0XFFFF_MASK);
8617 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4SourcePortMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[29U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
8618 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8619 {
8620 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddress[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 31U];
8621 }
8622 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8623 {
8624 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeIPDestinationAddressMask[ByteIdx] = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[ByteIdx + 37U];
8625 }
8626 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPort = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[41U] & NETC_ETH_IP_0XFFFF_MASK);
8627 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeL4DestinationPortMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[41U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFFFF_MASK);
8628
8629 CfgeDataIdx = 0U;
8630 PayloadIdx = 0U;
8631 for (ByteIdx = 0U; ByteIdx < 12U; ByteIdx++)
8632 {
8633 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] & NETC_ETH_IP_0XFF_MASK);
8634 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytes[ByteIdx + PayloadIdx + 1U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8635 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8636 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePayloadBytesMask[ByteIdx + PayloadIdx + 1U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[CfgeDataIdx + 43U] >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8637 PayloadIdx++;
8638 CfgeDataIdx++;
8639 }
8640 }
8641
8642 /* inline function for filling in IngressPortFilterTableEntry data in function Netc_Eth_Ip_QueryIngressPortFilterTableEntry() */
8643 static inline void Netc_Eth_Ip_FillInIPFTableEntryData(Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry)
8644 {
8645 uint8 ByteIdx;
8646 uint32 CfgeData;
8647
8648 /* fill in structure Netc_Eth_Ip_IngressPortFilterEntryDataType with data from response data buffer */
8649 IngressPortFilterTableEntry->IngressPortFilterEntryID = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[1U]; /* Entry_ID */
8650
8651 /* KEYE_DATA */
8652 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyePrecedence = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[2U] & NETC_ETH_IP_0XFFFF_MASK);
8653 IngressPortFilterTableEntry->IngressPortFilterkeyeData.keyeFrmAttributeFlags = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U] & NETC_ETH_IP_0XFFFF_MASK);
8654 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeFrmAttributeFlagsMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[4U] & NETC_ETH_IP_0XFFFF0000_MASK) >> NETC_ETH_IP_16BIT_SHIFT);
8655 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePoint = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U] & NETC_ETH_IP_IPFTABLE_KEYE_DATA_DIFFSCP_MASK);
8656 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDifferentiatedServicesCodePointMask = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[5U] & NETC_ETH_IP_IPFTABLE_KEYE_DATA_DSCPMASK_MASK) \
8657 >> NETC_ETH_IP_IPFTABLE_KEYE_DATA_DSCPMASK_SHIFT);
8658 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformation = (uint16)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[6U] & NETC_ETH_IP_0XFFFF_MASK);
8659 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeOuterVLANTagControlInformationMask = (uint16)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[6U] & NETC_ETH_IP_0XFFFF0000_MASK) >> NETC_ETH_IP_16BIT_SHIFT);
8660 SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
8661
8662 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8663 {
8664 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U] & NETC_ETH_IP_0XFF_MASK);
8665 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[7U] >>= NETC_ETH_IP_8BIT_SHIFT;
8666 }
8667
8668 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[4U] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] & NETC_ETH_IP_0XFF_MASK);
8669 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddr[5U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8670 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[0U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8671 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[1U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[8U] >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8672 for (ByteIdx = 2U; ByteIdx < 6U; ByteIdx++)
8673 {
8674 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeDstMacAddrMask[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U] & NETC_ETH_IP_0XFF_MASK);
8675 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[9U] >>= NETC_ETH_IP_8BIT_SHIFT;
8676 }
8677 for (ByteIdx = 0U; ByteIdx < 4U; ByteIdx++)
8678 {
8679 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[ByteIdx] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[10U] & NETC_ETH_IP_0XFF_MASK);
8680 Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[10U] >>= NETC_ETH_IP_8BIT_SHIFT;
8681 }
8682 SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25();
8683
8684 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[4U] = (uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] & NETC_ETH_IP_0XFF_MASK);
8685 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddr[5U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] >> NETC_ETH_IP_8BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8686 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[0U] = (uint8)((Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] >> NETC_ETH_IP_16BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8687 IngressPortFilterTableEntry->IngressPortFilterkeyeData.KeyeSrcMacAddrMask[1U] = ((uint8)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[11U] >> NETC_ETH_IP_24BIT_SHIFT) & NETC_ETH_IP_0XFF_MASK);
8688
8689 Netc_Eth_Ip_FillInKeyeDataForIPF(IngressPortFilterTableEntry); /* fill in the rest part of the KEYE_DATA */
8690
8691 /* Match Count data */
8692 IngressPortFilterTableEntry->IngressPortFilterMatchCount = (uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[55U]);
8693 IngressPortFilterTableEntry->IngressPortFilterMatchCount |= ((uint64)(Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[56U]) << NETC_ETH_IP_32BIT_SHIFT);
8694
8695 /* CFGE_DATA */
8696 CfgeData = Netc_Eth_Ip_EnetcTableDataBuffer.TableDataField[57U]; /* config field in CFGE_DATA */
8697 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeIpv = (uint8)(CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_IPV_MASK);
8698 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideIpv = (((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_OIPV_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_OIPV_SHIFT) != 0x0UL) ? TRUE : FALSE;
8699 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeDr = (uint8)((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_DR_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_DR_SHIFT);
8700 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeOverrideDr = (((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_ODR_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_ODR_SHIFT) != 0x0UL) ? TRUE : FALSE;
8701 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterForwardingAction = ((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTFA_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTFA_SHIFT);
8702 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeWakeOnLanTriggerEnable = (((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_WOLTE_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_WOLTE_SHIFT) != 0x0UL) ? TRUE : FALSE;
8703 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeFilterAction = ((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTA_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_FLTA_SHIFT);
8704 IngressPortFilterTableEntry->IngressPortFilterCfgeData.CfgeRelativePrecedentResolution = (uint8)((CfgeData & NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_RPR_MASK) >> NETC_ETH_IP_IPFTABLE_CFGE_CONFIG_RPR_SHIFT);
8705 }
8706
8707 /*FUNCTION**********************************************************************
8708 *
8709 * Function Name : Netc_Eth_Ip_QueryIngressPortFilterTableEntry
8710 * Description : Ethernet querys Ingress Port Filter table entry function.
8711 * implements Netc_Eth_Ip_QueryIngressPortFilterTableEntry_Activity
8712 *END**************************************************************************/
8713 Netc_Eth_Ip_StatusType Netc_Eth_Ip_QueryIngressPortFilterTableEntry( const uint8 CtrlIndex,
8714 uint32 *MatchedEntries,
8715 Netc_Eth_Ip_IngressPortFilterEntryDataType * IngressPortFilterTableEntry
8716 )
8717 {
8718 Netc_Eth_Ip_StatusType status;
8719 uint32 ActionsData;
8720
8721
8722 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8723 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
8724 DevAssert(MatchedEntries != NULL_PTR);
8725 DevAssert(IngressPortFilterTableEntry != NULL_PTR);
8726 #endif
8727
8728 /* clear the variable MatchedEntries first */
8729 *MatchedEntries = 0U;
8730
8731 /* only support "full query" */
8732 ActionsData = NETC_ETH_IP_ENETCTABLE_REQFMT_ACTIONS_FIELD_QUERY_ACTIONS(NETC_ETH_TABLES_FULL_QUERY);
8733
8734 /* inialize KEYE_DATA with Entry_ID */
8735 Netc_Eth_Ip_IPFKeyeData[0U] = IngressPortFilterTableEntry->IngressPortFilterEntryID;
8736
8737 status = Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff(ActionsData, &Netc_Eth_Ip_IPFKeyeData[0U], NULL_PTR, NETC_ETH_ENTRY_ID_MATCH);
8738 if (NETC_ETH_IP_STATUS_SUCCESS == status)
8739 {
8740 /* fill in operation data for config field of Request Header*/
8741 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
8742 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
8743 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_PORT_FILTER_TABLE_ID;
8744 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
8745 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_QUERY_CMD;
8746 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
8747 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_RSPBUFFER_LEN);
8748
8749 /* send command */
8750 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
8751 #if defined(ERR_IPV_NETC_051243)
8752 #if (STD_ON == ERR_IPV_NETC_051243)
8753 /* Error code 0x8A is not a real error. check it on Errata. */
8754 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
8755 {
8756 #endif
8757 #else
8758 if (status == NETC_ETH_IP_STATUS_SUCCESS)
8759 {
8760 #endif
8761 status = NETC_ETH_IP_STATUS_SUCCESS;
8762 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
8763 /* if found a matched entry, then fill in the structure */
8764 if (1U == *MatchedEntries)
8765 {
8766 Netc_Eth_Ip_FillInIPFTableEntryData(IngressPortFilterTableEntry);
8767 }
8768 }
8769 }
8770 else
8771 {
8772 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
8773 }
8774
8775 return status;
8776 }
8777
8778 /*FUNCTION**********************************************************************
8779 *
8780 * Function Name : Netc_Eth_Ip_DeleteIngressPortFilterTableEntry
8781 * Description : Ethernet deletes Ingress Port Filter table entry function.
8782 * implements Netc_Eth_Ip_DeleteIngressPortFilterTableEntry_Activity
8783 *END**************************************************************************/
8784 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DeleteIngressPortFilterTableEntry( const uint8 CtrlIndex,
8785 uint32 *MatchedEntries,
8786 uint32 IngressPortFilterEntryId
8787 )
8788 {
8789 Netc_Eth_Ip_StatusType status;
8790 uint32 KeyeData[1U];
8791 uint32 ActionsData = 0x0UL;
8792
8793 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8794 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
8795 DevAssert(MatchedEntries != NULL_PTR);
8796 #endif
8797
8798 /* clear the variable MatchedEntries first */
8799 *MatchedEntries = 0U;
8800
8801 /* inialize KEYE_DATA with Entry_ID */
8802 KeyeData[0U] = IngressPortFilterEntryId;
8803
8804 status = Netc_Eth_Ip_FillInIngressPortFilterTableReqDataBuff(ActionsData, &KeyeData[0U], NULL_PTR, NETC_ETH_ENTRY_ID_MATCH);
8805 if (NETC_ETH_IP_STATUS_SUCCESS == status)
8806 {
8807 /* fill in operation data for config field of Request Header*/
8808 Netc_Eth_Ip_OperationData.CmdCompletionInt = 0x0U; /* command completion interrupt disabled */
8809 Netc_Eth_Ip_OperationData.Version = NETC_ETH_IP_CMDBD_REQFMT_PROTOCOL_VERSION; /* protocol version = 2 */
8810 Netc_Eth_Ip_OperationData.TableId = NETC_ETH_IP_INGRESS_PORT_FILTER_TABLE_ID;
8811 Netc_Eth_Ip_OperationData.AccessMethod = NETC_ETH_ENTRY_ID_MATCH;
8812 Netc_Eth_Ip_OperationData.Cmd = NETC_ETH_DELETE_CMD;
8813 Netc_Eth_Ip_OperationData.ReqBuffLength = (NETC_ETH_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN);
8814 Netc_Eth_Ip_OperationData.RspBuffLength = (NETC_ETH_IP_TABLE_COMMON_RSPBUFFER_4BYTE_LEN);
8815
8816 /* send command */
8817 status = Netc_Eth_Ip_SendCommand(CtrlIndex, &Netc_Eth_Ip_OperationData);
8818 #if defined(ERR_IPV_NETC_051243)
8819 #if (STD_ON == ERR_IPV_NETC_051243)
8820 /* Error code 0x8A is not a real error. check it on Errata. */
8821 if ((status == NETC_ETH_IP_STATUS_NOT_REAL_ERROR) || (status == NETC_ETH_IP_STATUS_SUCCESS))
8822 {
8823 #endif
8824 #else
8825 if (status == NETC_ETH_IP_STATUS_SUCCESS)
8826 {
8827 #endif
8828 status = NETC_ETH_IP_STATUS_SUCCESS;
8829 Netc_Eth_Ip_GetMatchedEntries(CtrlIndex, MatchedEntries);
8830 }
8831 }
8832 else
8833 {
8834 status = NETC_ETH_CBDRSTATUS_ACCESSMETHOD_ERROR;
8835 }
8836
8837 return status;
8838 }
8839
8840
8841 /*FUNCTION**********************************************************************
8842 *
8843 * Function Name : Netc_Eth_Ip_GetSyncState
8844 * Description : Get Timer Syncronization state function.
8845 * implements Netc_Eth_Ip_GetSyncState_Activity
8846 *END**************************************************************************/
8847 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetSyncState( const uint8 CtrlIndex,
8848 boolean *SyncState
8849 )
8850 {
8851 static volatile uint16 PSIRspMessage;
8852 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
8853
8854 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8855 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8856 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
8857 DevAssert(SyncState != NULL_PTR);
8858 #endif
8859
8860 /* If the controller is of physical type it can directly read the sync state from the register,
8861 otherwise it must use VSI to PSI messaging to request a read from the PSI */
8862 if(Netc_Eth_Ip_apxState[CtrlIndex]->SiType == NETC_ETH_IP_PHYSICAL_SI)
8863 {
8864 *SyncState = ((IP_NETC__ENETC0_SI0->SITSR & NETC_F3_SI0_SITSR_SYNC_MASK) == 1UL) ? (boolean)TRUE: (boolean)FALSE;
8865 }
8866 else
8867 {
8868 status = Netc_Eth_Ip_VsiToPsiMsg(CtrlIndex, NETC_ETH_IP_VSITOPSI_GET_SYNC_STATE, NULL_PTR, (uint16 *) &PSIRspMessage);
8869 *SyncState = (boolean) PSIRspMessage;
8870 }
8871
8872 return status;
8873 }
8874
8875 /*FUNCTION**********************************************************************
8876 *
8877 * Function Name : Netc_Eth_Ip_SetSiPhysAddr
8878 * Description : Set the MAC addresses of PSI/VSIs from the PSI controller .
8879 * implements Netc_Eth_Ip_SetSiPhysAddr_Activity
8880 *END**************************************************************************/
8881 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetSiPhysAddr(const uint8 CtrlIndex,
8882 const uint8 SiId,
8883 const uint8 *MacAddr)
8884 {
8885 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
8886
8887 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8888 DevAssert(CtrlIndex == NETC_ETH_IP_PSI_INDEX);
8889 DevAssert(SiId < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8890 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]);
8891 DevAssert(MacAddr != NULL_PTR);
8892 #endif
8893
8894 /* Check if the controller is PSI. MAC changing allowed only for PSI */
8895 if( (NETC_ETH_IP_PHYSICAL_SI == Netc_Eth_Ip_apxState[CtrlIndex]->SiType) && \
8896 (NULL_PTR != MacAddr))
8897 {
8898 /* VSI MAC change */
8899 if(NETC_ETH_IP_PSI_INDEX != SiId)
8900 {
8901 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers. */
8902 IP_NETC__ENETC0_BASE->NUM_SI[SiId].PSIPMAR0 = (uint32)MacAddr[0U] | \
8903 ((uint32)MacAddr[1U] << 8U ) | \
8904 ((uint32)MacAddr[2U] << 16U) | \
8905 ((uint32)MacAddr[3U] << 24U);
8906 IP_NETC__ENETC0_BASE->NUM_SI[SiId].PSIPMAR1 = (uint32)MacAddr[4U] | \
8907 ((uint32)MacAddr[5U] << 8U);
8908 }
8909 else
8910 {
8911 /* For the PSI the MAC address will be configured both for the ENETC Port and for the PSI0 */
8912 /* Configure the port primary MAC address */
8913 IP_NETC__ENETC0_PORT->PMAR0 = (uint32)MacAddr[0U] | \
8914 ((uint32)MacAddr[1U] << 8U) | \
8915 ((uint32)MacAddr[2U] << 16U) | \
8916 ((uint32)MacAddr[3U] << 24U);
8917 IP_NETC__ENETC0_PORT->PMAR1 = (uint32)MacAddr[4U] | \
8918 ((uint32)MacAddr[5U] << 8U);
8919 }
8920
8921 }
8922 else
8923 {
8924 status = NETC_ETH_IP_STATUS_UNSUPPORTED;
8925 }
8926
8927 return status;
8928 }
8929
8930 #if defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE)
8931 #if (NETC_ETH_IP_FILL_LEVEL_API_ENABLE == STD_ON)
8932 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxRingFillLevel(const uint8 CtrlIndex, const uint8 RingIdx, Netc_Eth_Ip_FillLevelInfo * FillInfo)
8933 {
8934 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
8935
8936 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8937 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8938 DevAssert(FillInfo != NULL_PTR);
8939 #endif
8940
8941 FillInfo->TotalNumberOfBuff = Netc_Eth_Ip_Tx_FillLevelInfo[CtrlIndex][RingIdx].TotalNumberOfBuff;
8942 FillInfo->MaxNumberOfUsedBuff = Netc_Eth_Ip_Tx_FillLevelInfo[CtrlIndex][RingIdx].MaxNumberOfUsedBuff;
8943 FillInfo->NumberOfUsedBuff = Netc_Eth_Ip_Tx_FillLevelInfo[CtrlIndex][RingIdx].NumberOfUsedBuff;
8944
8945 Netc_Eth_Ip_Tx_FillLevelInfo[CtrlIndex][RingIdx].MaxNumberOfUsedBuff = 0U;
8946
8947 return status;
8948 }
8949
8950 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetRxRingFillLevel(const uint8 CtrlIndex, const uint8 RingIdx, Netc_Eth_Ip_FillLevelInfo * FillInfo)
8951 {
8952 Netc_Eth_Ip_StatusType status = NETC_ETH_IP_STATUS_SUCCESS;
8953 uint32 rxConsumerIdx;
8954 uint32 rxProducerIdx;
8955
8956 #if (STD_ON == NETC_ETH_IP_DEV_ERROR_DETECT)
8957 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS);
8958 DevAssert(Netc_Eth_Ip_apxState[CtrlIndex] != NULL_PTR);
8959 DevAssert(RingIdx < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfRxBDR);
8960 DevAssert(FillInfo != NULL_PTR);
8961 #endif
8962
8963 rxConsumerIdx = Netc_Eth_Ip_apxState[CtrlIndex]->LogicRxConsumerIndex[RingIdx];
8964 rxProducerIdx = netcSIsBase[CtrlIndex]->BDR_NUM[RingIdx].RBPIR;
8965
8966 FillInfo->TotalNumberOfBuff = Netc_Eth_Ip_apxState[CtrlIndex]->RxRingSize[RingIdx] - 1U;
8967 FillInfo->NumberOfUsedBuff = (rxConsumerIdx > rxProducerIdx) ? (Netc_Eth_Ip_apxState[CtrlIndex]->RxRingSize[RingIdx] - rxConsumerIdx + rxProducerIdx) : (rxProducerIdx - rxConsumerIdx);
8968 if (FillInfo->NumberOfUsedBuff > Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[CtrlIndex][RingIdx])
8969 {
8970 FillInfo->MaxNumberOfUsedBuff = FillInfo->NumberOfUsedBuff;
8971 }
8972 else
8973 {
8974 FillInfo->MaxNumberOfUsedBuff = Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[CtrlIndex][RingIdx];
8975 }
8976
8977 Netc_Eth_Ip_RxFifo_MaxNumberOfUsedBuff[CtrlIndex][RingIdx] = 0U;
8978
8979 return status;
8980 }
8981 #endif /* STD_ON == NETC_ETH_IP_FILL_LEVEL_API_ENABLE */
8982 #endif /* defined(NETC_ETH_IP_FILL_LEVEL_API_ENABLE) */
8983
8984 #define ETH_43_NETC_STOP_SEC_CODE
8985 #include "Eth_43_NETC_MemMap.h"
8986
8987 #ifdef __cplusplus
8988 }
8989 #endif
8990
8991 /** @} */
8992
