1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Netc_Eth_Ip_Irq.c
9 * @internal
10 *
11 * @addtogroup NETC_ETH_DRIVER NETC_ETH Driver
12 * @{
13 */
14
15 #ifdef __cplusplus
16 extern "C"{
17 #endif
18
19 /*==================================================================================================
20 * INCLUDE FILES
21 * 1) system and project includes
22 * 2) needed interfaces from external units
23 * 3) internal and external interfaces from this unit
24 ==================================================================================================*/
25 #include "Netc_Eth_Ip.h"
26 #include "Netc_Eth_Ip_Irq.h"
27 #if(NETC_ETH_IP_DEV_ERROR_DETECT == STD_ON)
28 #include "Devassert.h"
29 #endif
30
31 /*==================================================================================================
32 * SOURCE FILE VERSION INFORMATION
33 ==================================================================================================*/
34 #define NETC_ETH_IP_IRQ_VENDOR_ID_C 43
35 #define NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4
36 #define NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7
37 #define NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0
38 #define NETC_ETH_IP_IRQ_SW_MAJOR_VERSION_C 1
39 #define NETC_ETH_IP_IRQ_SW_MINOR_VERSION_C 0
40 #define NETC_ETH_IP_IRQ_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * FILE VERSION CHECKS
44 ==================================================================================================*/
45 /* Checks against NETC_ETH_IP_IRQ.h */
46 #if (NETC_ETH_IP_IRQ_VENDOR_ID_C != NETC_ETH_IP_VENDOR_ID)
47 #error "Netc_Eth_Ip.c and Netc_Eth_Ip.h have different vendor ids"
48 #endif
49 #if ((NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION) || \
50 (NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MINOR_VERSION) || \
51 (NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != NETC_ETH_IP_AR_RELEASE_REVISION_VERSION))
52 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
53 #endif
54 #if ((NETC_ETH_IP_IRQ_SW_MAJOR_VERSION_C != NETC_ETH_IP_SW_MAJOR_VERSION) || \
55 (NETC_ETH_IP_IRQ_SW_MINOR_VERSION_C != NETC_ETH_IP_SW_MINOR_VERSION) || \
56 (NETC_ETH_IP_IRQ_SW_PATCH_VERSION_C != NETC_ETH_IP_SW_PATCH_VERSION) \
57 )
58 #error "Software Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
59 #endif
60
61 /* Checks against NETC_ETH_IP_IRQ.h */
62 #if (NETC_ETH_IP_IRQ_VENDOR_ID_C != NETC_ETH_IP_IRQ_VENDOR_ID)
63 #error "Netc_Eth_Ip.c and Netc_Eth_Ip.h have different vendor ids"
64 #endif
65 #if ((NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
66 (NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
67 (NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION))
68 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
69 #endif
70 #if ((NETC_ETH_IP_IRQ_SW_MAJOR_VERSION_C != NETC_ETH_IP_IRQ_SW_MAJOR_VERSION) || \
71 (NETC_ETH_IP_IRQ_SW_MINOR_VERSION_C != NETC_ETH_IP_IRQ_SW_MINOR_VERSION) || \
72 (NETC_ETH_IP_IRQ_SW_PATCH_VERSION_C != NETC_ETH_IP_IRQ_SW_PATCH_VERSION) \
73 )
74 #error "Software Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
75 #endif
76 /*==================================================================================================
77 * GLOBAL CONSTANTS
78 ==================================================================================================*/
79 #define ETH_43_NETC_START_SEC_VAR_INIT_UNSPECIFIED
80 #include "Eth_43_NETC_MemMap.h"
81
82 extern Netc_Eth_Ip_VfBaseType *netcVFBase[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
83
84 #define ETH_43_NETC_STOP_SEC_VAR_INIT_UNSPECIFIED
85 #include "Eth_43_NETC_MemMap.h"
86
87 /*==================================================================================================
88 * GLOBAL VARIABLES
89 ==================================================================================================*/
90 /* Pointers to NETC internal driver state for each Instance. */
91 extern Netc_Eth_Ip_StateType *Netc_Eth_Ip_apxState[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
92
93 /* Pointer to each SI base. */
94 extern Netc_Eth_Ip_SiBaseType *netcSIsBase[8U];
95
96 /*==================================================================================================
97 * LOCAL FUNCTION PROTOTYPES
98 ==================================================================================================*/
99 /**
100 * @brief
101 *
102 * @param CtrlIndex
103 */
104 static inline void Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex);
105
106 /**
107 * @brief
108 *
109 * @param CtrlIndex
110 */
111 void Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex);
112
113 /**
114 * @brief Local function used to process PSI Message Receive event
115 *
116 * @param VSIIndex
117 */
118 static inline void Netc_Eth_Ip_ProcessMsgRcv(uint8 VSIIndex);
119
120 /**
121 * @brief Local function used to re-initialize the VSI after a Function Level Reset event
122 *
123 * @param VSIIndex
124 */
125 static inline void Netc_Eth_Ip_InitVSIAfterFlr(uint8 VSIIndex);
126
127 /*==================================================================================================
128 * LOCAL FUNCTIONS
129 ==================================================================================================*/
130 /* implements Netc_Eth_Ip_MSIX_Tx_Activity */
Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex)131 static inline void Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex)
132 {
133 uint8 RingIndex;
134 uint32 TxRingIntStatus = netcSIsBase[CtrlIndex]->SITXIDR0;
135 /*
136 * Checking the first queue Interrupt Enable flag
137 * In order to fulfill requirement CPR_RTD_00664, the interrupt enable flag for the first queue is checked for the following reasons:
138 * 1. The interrupts are enabled at controller level, therefore if one queue has the interrupt enabled, then all of the queues will have it.
139 * 2. In ETH driver case, the queues are mandatory configured in order, so that the first queue enables the interrupt, then all of the queues will have the interrupt enable flag set
140 * 3. Performance reason: one check vs no.of queues checks
141 */
142 if(NETC_ETH_IP_TBIER_TXFIE_MASK == (netcSIsBase[CtrlIndex]->BDR_NUM[0U].TBIER & NETC_ETH_IP_TBIER_TXFIE_MASK))
143 {
144 /* Clear TX interrupt flag for all SIs. */
145 netcSIsBase[CtrlIndex]->SITXIDR0 = TxRingIntStatus;
146 /* The flags for frame interrupt are allocated in the upper 16 bits of the register,
147 shift them in the lower part. */
148 TxRingIntStatus >>= 16UL;
149
150 if (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex])
151 {
152 for(RingIndex = 0U; RingIndex < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfTxBDR; RingIndex++)
153 {
154 /** TODO: Update this callback for both layers. */
155 if ((1U == (TxRingIntStatus >> RingIndex)) && (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]->TxCallback[RingIndex]))
156 {
157 Netc_Eth_Ip_apxState[CtrlIndex]->TxCallback[RingIndex](Netc_Eth_Ip_apxState[CtrlIndex]->CtrlLogicalIndex, RingIndex);
158 }
159 }
160 }
161 }
162 else if(NETC_ETH_IP_TBIER_TXTIE_MASK == (netcSIsBase[CtrlIndex]->BDR_NUM[0U].TBIER & NETC_ETH_IP_TBIER_TXTIE_MASK))
163 {
164 /* Clear TX interrupt flag for all SIs. */
165 netcSIsBase[CtrlIndex]->SITXIDR0 = TxRingIntStatus;
166 /* Keep only coalescing interrupt status. */
167 TxRingIntStatus &= 0x0000FFFFUL;
168
169 if (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex])
170 {
171 for(RingIndex = 0U; RingIndex < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfTxBDR; RingIndex++)
172 {
173 /** TODO: Update this callback for both layers. */
174 if ((1U == (TxRingIntStatus >> RingIndex)) && (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]->TxCallback[RingIndex]))
175 {
176 Netc_Eth_Ip_apxState[CtrlIndex]->TxCallback[RingIndex](Netc_Eth_Ip_apxState[CtrlIndex]->CtrlLogicalIndex, RingIndex);
177 }
178 }
179 }
180 }
181 else
182 {
183 /* MISRA C-2012 Rule 15.7 */
184 }
185
186 }
187
188 /* implements Netc_Eth_Ip_MSIX_Rx_Activity */
Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex)189 void Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex)
190 {
191 uint8 RingIndex;
192 uint32 interruptStatus = netcSIsBase[CtrlIndex]->SIRXIDR0;
193 /*
194 * Checking the first queue Interrupt Enable flag
195 * In order to fulfill requirement CPR_RTD_00664, the interrupt enable flag for the first queue is checked for the following reasons:
196 * 1. The interrupts are enabled at controller level, therefore if one queue has the interrupt enabled, then all of the queues will have it.
197 * 2. In ETH driver case, the queues are mandatory configured in order, so that the first queue enables the interrupt, then all of the queues will have the interrupt enable flag set
198 * 3. Performance reason: one check vs no.of queues checks
199 */
200 if (NETC_ETH_IP_RBIER_RXTIE_MASK == netcSIsBase[CtrlIndex]->BDR_NUM[0u].RBIER)
201 {
202 /* Clear RX interrupt flag for all SIs.*/
203 netcSIsBase[CtrlIndex]->SIRXIDR0 = interruptStatus;
204
205 /* Check is current controller was intialized. Req CPR_RTD_00011 is fulfilled.*/
206 if (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex])
207 {
208 /* Check all rings of the current controller. */
209 for(RingIndex = 0; RingIndex < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfRxBDR; RingIndex++)
210 {
211 if ((1U == (interruptStatus >> RingIndex)) && (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]->RxCallback[RingIndex]))
212 {
213 Netc_Eth_Ip_apxState[CtrlIndex]->RxCallback[RingIndex](Netc_Eth_Ip_apxState[CtrlIndex]->CtrlLogicalIndex, RingIndex);
214 }
215 }
216 }
217 }
218 }
219
Netc_Eth_Ip_ProcessMsgRcv(uint8 VSIIndex)220 static inline void Netc_Eth_Ip_ProcessMsgRcv(uint8 VSIIndex)
221 {
222 const Netc_Eth_Ip_GeneralSIConfigType * SIConfig;
223 const Netc_Eth_Ip_VsiToPsiMsgType *CmdMacReceivedAddr;
224 Netc_Eth_Ip_VsiToPsiMsgActionType CommandType;
225 uint8 HashValue;
226 Netc_Eth_Ip_StatusType PSIResponse = NETC_ETH_IP_STATUS_NOT_REAL_ERROR;
227
228 CmdMacReceivedAddr =(const Netc_Eth_Ip_VsiToPsiMsgType *)(netcSIsBase[NETC_ETH_IP_PSI_INDEX]->MSGSR.PSI_A.VSI_NUM[VSIIndex - 1U].PSIVMSGRCVAR0 & \
229 NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_MASK);
230 CommandType = (Netc_Eth_Ip_VsiToPsiMsgActionType)((uint16)((uint32)CmdMacReceivedAddr->Class << 8U) + ((uint32)CmdMacReceivedAddr->Command));
231
232 /* Check if the driver was intialized. Req CPR_RTD_00011 is fulfilled.*/
233 if (NULL_PTR != Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX])
234 {
235 /*Get the SI general configuration */
236 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
237
238 switch(CommandType)
239 {
240 case NETC_ETH_IP_VSITOPSI_MAC_ADDR_SET:
241 {
242 if (SIConfig->changeMACAllowed == TRUE)
243 {
244 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers. */
245 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIPMAR0 = (uint32)(CmdMacReceivedAddr->Data[2U]) | \
246 ((uint32)(CmdMacReceivedAddr->Data[3U]) << 8U ) | \
247 ((uint32)(CmdMacReceivedAddr->Data[4U]) << 16U) | \
248 ((uint32)(CmdMacReceivedAddr->Data[5U]) << 24U);
249 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIPMAR1 = (uint32)(CmdMacReceivedAddr->Data[6U]) | \
250 ((uint32)(CmdMacReceivedAddr->Data[7U]) << 8U);
251 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
252 }
253 else
254 {
255 PSIResponse = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
256 }
257
258 break;
259 }
260 case NETC_ETH_IP_VSITOPSI_ADD_RX_MAC_ADDR_FILTER:
261 {
262 if (SIConfig->hashFilterUpdateAllowed == TRUE)
263 {
264 HashValue = CmdMacReceivedAddr->Data[0U];
265 if ((HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER) != (uint8)0U)
266 {
267 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR1 |= (uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
268 }
269 else
270 {
271 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR0 |= (uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
272 }
273
274 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
275 }
276 else
277 {
278 PSIResponse = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
279 }
280
281 break;
282 }
283 case NETC_ETH_IP_VSITOPSI_DELETE_RX_MAC_ADDR_FILTER:
284 {
285 if (SIConfig->hashFilterUpdateAllowed == TRUE)
286 {
287 HashValue = CmdMacReceivedAddr->Data[0U];
288 if ((HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER) != (uint8)0U)
289 {
290 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR1 &= ~(uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
291 }
292 else
293 {
294 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR0 &= ~(uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
295 }
296
297 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
298 }
299 else
300 {
301 PSIResponse = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
302 }
303
304 break;
305 }
306 case NETC_ETH_IP_VSITOPSI_ENABLE_MULTICAST:
307 {
308 if (SIConfig->multicastPromiscuousChangeAllowed == TRUE)
309 {
310 /* Enable MAC multicast promiscuous mode. */
311 IP_NETC__ENETC0_BASE->PSIPMMR |= ((uint32)((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)));
312
313 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
314 }
315 else
316 {
317 PSIResponse = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
318 }
319
320 break;
321 }
322 case NETC_ETH_IP_VSITOPSI_DISABLE_MULTICAST:
323 {
324 if (SIConfig->multicastPromiscuousChangeAllowed == TRUE)
325 {
326 /* Disable MAC multicast promiscuous mode. */
327 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32) ((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)));
328
329 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
330 }
331 else
332 {
333 PSIResponse = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
334 }
335
336 break;
337 }
338 case NETC_ETH_IP_VSITOPSI_CLOSE_FILTER:
339 {
340 if (SIConfig->multicastPromiscuousChangeAllowed == TRUE)
341 {
342 /* Disable MAC multicast promiscuous mode. */
343 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)));
344 }
345
346 if (SIConfig->hashFilterUpdateAllowed == TRUE)
347 {
348 /* Clear all entries in filter. */
349 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR1 = (uint32)0x0U;
350 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR0 = (uint32)0x0U;
351 }
352
353 /* A positive response is expected by current IPW implementation*/
354 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
355
356 break;
357 }
358 case NETC_ETH_IP_VSITOPSI_GET_SYNC_STATE:
359 {
360 if ((IP_NETC__ENETC0_SI0->SITSR & NETC_F3_SI0_SITSR_SYNC_MASK) != 0U)
361 {
362 PSIResponse = NETC_ETH_IP_PSITOVSI_SYNC_STATUS_TRUE;
363 }
364 else
365 {
366 PSIResponse = NETC_ETH_IP_PSITOVSI_SYNC_STATUS_FALSE;
367 }
368
369 break;
370 }
371 default:
372 {
373 /* Do nothing. */
374 break;
375 }
376 }
377 }
378
379 /* Write the PSI response to MC (Message Code) field and Set the MSn (Message Sent) bit to the corresponding VSI */
380 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.PSIMSGSR = ((uint32)PSIResponse << NETC_ETH_IP_PSI_MSG_POS) | (NETC_ETH_IP_VSI_ENABLE << VSIIndex);
381
382 /* Mark the processing as complete by clearing the MR bit from PSIMSGRR. */
383 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.PSIMSGRR = (uint32)((uint32)NETC_ETH_IP_MSG_RCV_COMPLETE << VSIIndex);
384 }
385
386
Netc_Eth_Ip_InitVSIAfterFlr(uint8 VSIIndex)387 static inline void Netc_Eth_Ip_InitVSIAfterFlr(uint8 VSIIndex)
388 {
389 const Netc_Eth_Ip_GeneralSIConfigType * SIConfig;
390 uint8 siHwId;
391
392 /* Check if the driver was intialized. Req CPR_RTD_00011 is fulfilled.*/
393 if (NULL_PTR != Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX])
394 {
395 /*Get the SI general configuration */
396 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
397
398 /* Identify the VSI in the list of SIs to configure */
399 siHwId = SIConfig->siId;
400
401 /* Enable/disable MAC multicast/unicast promiscuous mode. */
402 IP_NETC__ENETC0_BASE->PSIPMMR = ((uint32)(Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->generalConfig->maskMACPromiscuousMulticastEnable) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT) | \
403 (uint32)(Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->generalConfig->maskMACPromiscuousUnicastEnable);
404
405 if (TRUE == SIConfig->enableSi)
406 {
407 /** Assure that SI is not enabled. */
408 netcSIsBase[siHwId]->SIMR &= ~(NETC_F3_SI0_SIMR_EN_MASK);
409
410 /* Master enable for a station interface.*/
411 IP_NETC__ENETC0_BASE->PMR = IP_NETC__ENETC0_BASE->PMR | (NETC_F3_PMR_SI0EN_MASK << siHwId);
412
413 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers */
414 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR0 = ((uint32)SIConfig->primaryMACAddress[0U]) | \
415 (((uint32)SIConfig->primaryMACAddress[1U]) << 8U) | \
416 (((uint32)SIConfig->primaryMACAddress[2U]) << 16U) | \
417 (((uint32)SIConfig->primaryMACAddress[3U]) << 24U);
418
419 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR1 = ((uint32)SIConfig->primaryMACAddress[4U]) | \
420 (((uint32)SIConfig->primaryMACAddress[5U]) << 8U);
421
422 /* Configure where the PSI receives the message for enabled VSIs. */
423 /* if(NULL_PTR != config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U])
424 {
425 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.VSI_NUM[siHwId - 1U].PSIVMSGRCVAR0 = (uint32)config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U] | \
426 NETC_ETH_IP_VSITOPSI_MSG_SIZE;
427 }
428 */
429
430 /* Number of entries in a MSI table for the current SI. */
431 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR2 = NETC_ETH_IP_NUM_OF_ENTRIES_MSITABLE;
432
433 /* Configure the number or TX and RX BD Rings for each SI */
434 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_NUM_TX_BDR_MASK | NETC_F3_PSICFGR0_NUM_RX_BDR_MASK);
435
436 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_NUM_TX_BDR(SIConfig->NumberOfTxBDR) | \
437 NETC_F3_PSICFGR0_NUM_RX_BDR(SIConfig->NumberOfRxBDR);
438
439 /* Configure the bandwidth weight for the current SI */
440 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIBW(SIConfig->SIBandwidthWeight);
441
442 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
443 if (TRUE == SIConfig->EnableSIVlan)
444 {
445 /* Enable VLAN and select tag protocol, priority code point, drop eligible indicator and VLAN identifier */
446 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR = NETC_F3_PSIVLANR_TPID(SIConfig->SiVLANConfig.ProtocolIdentifier) |
447 NETC_F3_PSIVLANR_PCP(SIConfig->SiVLANConfig.PriorityCodePoint) |
448 NETC_F3_PSIVLANR_VID(SIConfig->SiVLANConfig.VlanIdentifier) |
449 NETC_F3_PSIVLANR_E(1U) | NETC_F3_PSIVLANR_DEI((uint8)SIConfig->SiVLANConfig.DropIndicator);
450 }
451 else
452 {
453 /* Disable VLAN and select tag protocol */
454 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR &= ~NETC_F3_PSIVLANR_E(1U);
455 }
456
457 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_SIVC_MASK | NETC_F3_PSICFGR0_SIVIE_MASK | NETC_F3_PSICFGR0_VTE_MASK);
458 /* Insert VLAN Ethertype and enable insertion of the SI-based VLAN into frames sent by this SI. This config apply for generic */
459 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIVC(SIConfig->SIVlanControl) |
460 NETC_F3_PSICFGR0_SIVIE((uint8)SIConfig->EnableSoftwareVlanInsert) |
461 NETC_F3_PSICFGR0_VTE((SIConfig->EnableVLANTagExtract) ? 1U : 0U); ;
462 #endif
463
464 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_ASE((SIConfig->enableAntiSpoofing) ? 1U : 0U);
465
466 /* Enable bus for virtual function. */
467 netcVFBase[VSIIndex]->PCI_CFH_CMD |= NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(1U);
468
469 }
470 }
471
472 }
473
474
475 /*==================================================================================================
476 * GLOBAL FUNCTIONS
477 ==================================================================================================*/
478 /* implements Netc_Eth_Ip_MSIX_SIMsgEvent_Activity */
Netc_Eth_Ip_MSIX_SIMsgEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)479 void Netc_Eth_Ip_MSIX_SIMsgEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
480 {
481 uint8 CounterRxMsgFromVsi;
482 uint8 RxMsgFromVsiMask;
483 uint32 FlrMask;
484
485 /*Check if the Interrupt for PSI is enabled*/
486 if ((netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIER & NETC_ETH_IP_PSIIER_MASK) != (uint32)0U)
487 {
488 /* Status of received messages. */
489 RxMsgFromVsiMask = (uint8)(netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIDR & NETC_ETH_IP_PSI_MR_EV_MASK);
490
491 /* Function Level Reset Mask. */
492 FlrMask = (uint32)(netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIDR & NETC_ETH_IP_FLR_EV_MASK);
493
494 /* Clear status for messages that will be addressed and for the SI that will be reset at function level. */
495 netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIDR = (uint32)RxMsgFromVsiMask | (uint32)FlrMask;
496 /*Check if driver is initialized on the current controller */
497 if (NULL_PTR != Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX])
498 {
499 for(CounterRxMsgFromVsi = 1U; CounterRxMsgFromVsi < FEATURE_NETC_ETH_NUMBER_OF_CTRLS; CounterRxMsgFromVsi++)
500 {
501 if((((uint32)1U << CounterRxMsgFromVsi) & (uint32)RxMsgFromVsiMask) != (uint32)0U)
502 {
503 Netc_Eth_Ip_ProcessMsgRcv(CounterRxMsgFromVsi);
504 }
505
506 if((((uint32)1U << NETC_ETH_IP_PSI_IDR_FLR(CounterRxMsgFromVsi)) & (uint32)FlrMask) != (uint32)0U)
507 {
508 Netc_Eth_Ip_InitVSIAfterFlr(CounterRxMsgFromVsi);
509 }
510 }
511 }
512 }
513
514 (void)RxChannelId;
515 (void)RxBuffer;
516 (void)BufferSize;
517 }
518
Netc_Eth_Ip_0_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)519 void Netc_Eth_Ip_0_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
520 {
521 Netc_Eth_Ip_MSIX_Tx(0U);
522 (void)RxChannelId;
523 (void)RxBuffer;
524 (void)BufferSize;
525 }
526
Netc_Eth_Ip_1_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)527 void Netc_Eth_Ip_1_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
528 {
529 Netc_Eth_Ip_MSIX_Tx(1U);
530 (void)RxChannelId;
531 (void)RxBuffer;
532 (void)BufferSize;
533 }
534
Netc_Eth_Ip_2_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)535 void Netc_Eth_Ip_2_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
536 {
537 Netc_Eth_Ip_MSIX_Tx(2U);
538 (void)RxChannelId;
539 (void)RxBuffer;
540 (void)BufferSize;
541 }
542
Netc_Eth_Ip_3_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)543 void Netc_Eth_Ip_3_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
544 {
545 Netc_Eth_Ip_MSIX_Tx(3U);
546 (void)RxChannelId;
547 (void)RxBuffer;
548 (void)BufferSize;
549 }
550
Netc_Eth_Ip_4_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)551 void Netc_Eth_Ip_4_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
552 {
553 Netc_Eth_Ip_MSIX_Tx(4U);
554 (void)RxChannelId;
555 (void)RxBuffer;
556 (void)BufferSize;
557 }
558
Netc_Eth_Ip_5_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)559 void Netc_Eth_Ip_5_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
560 {
561 Netc_Eth_Ip_MSIX_Tx(5U);
562 (void)RxChannelId;
563 (void)RxBuffer;
564 (void)BufferSize;
565 }
566
Netc_Eth_Ip_6_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)567 void Netc_Eth_Ip_6_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
568 {
569 Netc_Eth_Ip_MSIX_Tx(6U);
570 (void)RxChannelId;
571 (void)RxBuffer;
572 (void)BufferSize;
573 }
574
Netc_Eth_Ip_7_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)575 void Netc_Eth_Ip_7_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
576 {
577 Netc_Eth_Ip_MSIX_Tx(7U);
578 (void)RxChannelId;
579 (void)RxBuffer;
580 (void)BufferSize;
581 }
582
583
Netc_Eth_Ip_0_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)584 void Netc_Eth_Ip_0_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
585 {
586 Netc_Eth_Ip_MSIX_Rx(0U);
587 (void)RxChannelId;
588 (void)RxBuffer;
589 (void)BufferSize;
590 }
591
Netc_Eth_Ip_1_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)592 void Netc_Eth_Ip_1_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
593 {
594 Netc_Eth_Ip_MSIX_Rx(1U);
595 (void)RxChannelId;
596 (void)RxBuffer;
597 (void)BufferSize;
598 }
599
Netc_Eth_Ip_2_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)600 void Netc_Eth_Ip_2_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
601 {
602 Netc_Eth_Ip_MSIX_Rx(2U);
603 (void)RxChannelId;
604 (void)RxBuffer;
605 (void)BufferSize;
606 }
607
Netc_Eth_Ip_3_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)608 void Netc_Eth_Ip_3_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
609 {
610 Netc_Eth_Ip_MSIX_Rx(3U);
611 (void)RxChannelId;
612 (void)RxBuffer;
613 (void)BufferSize;
614 }
615
Netc_Eth_Ip_4_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)616 void Netc_Eth_Ip_4_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
617 {
618 Netc_Eth_Ip_MSIX_Rx(4U);
619 (void)RxChannelId;
620 (void)RxBuffer;
621 (void)BufferSize;
622 }
623
Netc_Eth_Ip_5_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)624 void Netc_Eth_Ip_5_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
625 {
626 Netc_Eth_Ip_MSIX_Rx(5U);
627 (void)RxChannelId;
628 (void)RxBuffer;
629 (void)BufferSize;
630 }
631
Netc_Eth_Ip_6_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)632 void Netc_Eth_Ip_6_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
633 {
634 Netc_Eth_Ip_MSIX_Rx(6U);
635 (void)RxChannelId;
636 (void)RxBuffer;
637 (void)BufferSize;
638 }
639
Netc_Eth_Ip_7_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)640 void Netc_Eth_Ip_7_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
641 {
642 Netc_Eth_Ip_MSIX_Rx(7U);
643 (void)RxChannelId;
644 (void)RxBuffer;
645 (void)BufferSize;
646 }
647
ISR(Netc_Eth_Ip_ErrorReporting)648 ISR(Netc_Eth_Ip_ErrorReporting)
649 {
650 Netc_Eth_Ip_PCIe_AER_Handler(0u);
651 }
652
653 #ifdef __cplusplus
654 }
655 #endif
656
657 /** @} */
658
